Intel Atom® Processor C3000 Product Family Specification Update

Intel Atom® Processor C3000
Product Family
Specification Update
March 2018
Order Number: 336345-005US
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Intel Atom® Processor C3000 Product Family
Specification Update
2
March 2018
Order Number: 336345-005US
Contents—Intel Atom® Processor C3000 Product Family
Contents
Revision History .........................................................................................................4
Preface.......................................................................................................................5
Affected Documents/Related Documents ................................................................5
Nomenclature .....................................................................................................6
Summary Tables of Changes ......................................................................................7
Codes Used in Summary Tables.............................................................................7
Stepping................................................................................................7
Status ...................................................................................................7
Identification Information .......................................................................................11
Component Identification using Programming Interface .......................................... 11
Component Marking Information ......................................................................... 37
Errata.......................................................................................................................39
Specification Changes ..............................................................................................50
Specification Clarifications .......................................................................................51
Documentation Changes ..........................................................................................52
March 2018
Order Number: 336345-005US
Intel Atom® Processor C3000 Product Family
Specification Update
3
Intel Atom® Processor C3000 Product Family—Revision History
Revision History
Date
Revision
Description
March 2018
005US
Updated Identification Information.
Added the following errata:
• Intel® Processor Trace Timing Packets May Not be Generated When Clock
Modulation is Enabled
• Processor Host Root Complex May Incorrectly Route Memory Accesses to Intel®
Trace Hub
January 2018
004US
Added the following erratum:
• NEWCENTURY_STS Cannot Be Cleared
December 2017
003US
Added the following Specification Change:
• Optional SMBALERT# Signal in SMB Controller - Legacy
Added the following erratum:
• Incorrect Number of Enabled Cores Reported in MSR_CORE_THREAD_COUNT
September 2017
002US
Updated the following erratum:
• Performance Monitoring Event Branch Retired May Increment Twice For Near RET
Imm16
August 2017
001US
•
Initial Release
§§
Intel Atom® Processor C3000 Product Family
Specification Update
4
March 2018
Order Number: 336345-005US
Preface—Intel Atom® Processor C3000 Product Family
Preface
This document is an update to the specifications contained in the Affected Documents/
Related Documents table below. This document is a compilation of device and
documentation sighting, specification clarifications and changes. It is intended for
hardware system manufacturers and software developers of applications, operating
systems, or tools.
Information types defined in Nomenclature are consolidated into the specification
update and are no longer published in other documents.
This document may also contain information that was not previously published.
Affected Documents/Related Documents
Document Number/
Location
Document Title
Intel® 64 and IA-32 Architectures Software Developer’s Manual
325462
1
Intel® 64 and IA-32 Intel Architectures Optimization Reference Manual
248966
1
Intel 64 and IA-32 Architectures Software Developer’s Manual Documentation
Changes
252046
1
Intel® Virtualization Technology Specification for Directed I/O Architecture
Specification
D51397
1
®
Notes:
1.
This document can be downloaded from http://www.intel.com/content/www/us/en/processors/
architectures-software-developer-manuals.html.
March 2018
Order Number: 336345-005US
Intel Atom® Processor C3000 Product Family
Specification Update
5
Intel Atom® Processor C3000 Product Family—Preface
Nomenclature
S-Spec Number is a five-digit code used to identify products. Products are
differentiated by their unique characteristics, such as, core speed, L2 cache size,
package type, etc. as described in the processor identification information table. Read
all notes associated with each S-Spec number.
QDF Number is a four digit code used to distinguish between engineering samples.
These samples are used for qualification and early design validation. The functionality
of these parts can range from mechanical only to fully functional. This document has a
processor identification information table that lists these QDF numbers and the
corresponding product details.
Errata are design defects or errors. Errata may cause the behavior of the Intel Atom®
Processor C3000 Product Family to deviate from published specifications. Hardware and
software designed to be used with any given stepping must assume that all errata
documented for that stepping are present in all devices.
Specification Changes are modifications to the current published specifications.
These changes will be incorporated in any new release of the specification.
Specification Clarifications describe a specification in greater detail or further
highlight a specification’s impact to a complex design situation. These clarifications will
be incorporated in any new release of the specification.
Documentation Changes include typos, errors, or omissions from the current
published specifications. These will be incorporated in any new release of the
specification.
Note:
Errata remain in the specification update throughout the product’s lifecycle, or until a
particular stepping is no longer commercially available. Under these circumstances,
errata removed from the specification update are archived and available upon request.
Specification changes, specification clarifications and documentation changes are
removed from the specification update when the appropriate changes are made to the
appropriate product specification or user documentation (datasheets, manuals, etc.).
Intel Atom® Processor C3000 Product Family
Specification Update
6
March 2018
Order Number: 336345-005US
Summary Tables of Changes—Intel Atom® Processor C3000 Product Family
Summary Tables of Changes
The following tables indicate the errata, specification changes, specification
clarifications, and documentation changes which apply to the Intel Atom® Processor
C3000 Product Family. Intel may fix some of the errata in a future stepping of the
component, and account for the other outstanding issues through documentation or
specification changes as noted. These tables uses the following notations:
Codes Used in Summary Tables
Stepping
X:
Errata exists in the stepping indicated. Specification Change or
Clarification that applies to this stepping.
(No mark)
or (Blank box):
This erratum is Fixed in listed stepping or specification change
does not apply to listed stepping.
Doc:
Document change or update will be implemented.
Plan Fix:
This erratum may be Fixed in a future stepping of the product.
Fixed:
This erratum has been previously Fixed.
No Fix:
There are no plans to fix this erratum.
Status
March 2018
Order Number: 336345-005US
Intel Atom® Processor C3000 Product Family
Specification Update
7
Intel Atom® Processor C3000 Product Family—Summary Tables of Changes
Table 1.
Errata Summary Table (Sheet 1 of 2)
Stepping
Number
B1
(Production)
Status
Errata Title
DNV1.
X
No Fix
HECI Line Interrupt May Not be Generated
DNV2.
X
No Fix
xHCI Host Controller Reset May Cause A System Hang
DNV3.
X
No Fix
USB DBC-EXI Is Not Enumerated Correctly
DNV4.
X
No Fix
Performance Monitoring Event Branch Retired May Increment Twice For Near RET
Imm16
DNV5.
X
No Fix
NCSI_RXD Output Cannot be Tri-State to Meet NCSI Specification
DNV6.
X
No Fix
The X553 Ethernet Controller Transmitter Transition Time Does Not Conform To IEEE
802.3 Specification
DNV7.
X
No Fix
10 GBASE-KR Transmitter Does Not Fully Conform To Specification For Equalization
DNV8.
X
No Fix
Split Access to APIC-access Page May Access Virtual-APIC Page
DNV9.
X
No Fix
PEBS Record EventingIP Field May be Incorrect After CS.Base Change
DNV10.
X
No Fix
Performance Monitor Instructions Retired Event May Not Count Consistently
DNV11.
X
No Fix
SMRAM State-Save Area Above the 4GB Boundary May Cause Unpredictable System
Behavior
DNV12.
X
No Fix
POPCNT Instruction May Take Longer to Execute Than Expected
DNV13.
X
No Fix
APIC-access VM Exit May Occur instead of SMAP #PF
DNV14.
X
No Fix
Some Performance Counter Overflows May Not Be Logged in
IA32_PERF_GLOBAL_STATUS When FREEZE_PERFMON_ON_PMI is Enabled
DNV15.
X
No Fix
Performance Monitoring OFFCORE_RESPONSE1 Event May Improperly Count L2
Evictions
DNV16.
X
No Fix
Debug Exception May Not be Generated on Memory Read Spanning a Cacheline
Boundary
DNV17.
X
No Fix
Intel® PT CR3 Filtering Compares Bits [11:5] of CR3 and IA32_RTIT_CR3_MATCH
Outside of PAE Paging Mode
DNV18.
X
No Fix
Intel® PT OVF Packet May Be Followed by TIP.PGD Packet
DNV19.
X
No Fix
Intel® PT OVF May Be Followed By an Unexpected FUP Packet
DNV20.
X
No Fix
Performance Monitoring COREWB Offcore Response Event May Overcount
DNV21.
X
No Fix
FBSTP May Update FOP/FIP/FDP/FSW Before Exception or VM Exit
DNV22.
X
No Fix
PEBS Record May be Generated When Counters Frozen
DNV23.
X
No Fix
IA32_PERF_GLOBAL_INUSE[62] May be Set
DNV24.
X
No Fix
xHCI Split-Transactions Error Counter Reset Issue
DNV25.
X
No Fix
An Unsupported Request May Log in the Integrated Error Handler (IEH) After PCI
Enumeration
Intel Atom® Processor C3000 Product Family
Specification Update
8
March 2018
Order Number: 336345-005US
Summary Tables of Changes—Intel Atom® Processor C3000 Product Family
Table 1.
Errata Summary Table (Sheet 2 of 2)
Stepping
Number
B1
(Production)
Status
Errata Title
DNV26.
X
No Fix
Data Breakpoints May Not be Detected on Split Reads
DNV27.
X
No Fix
Intel® Trace Hub PTI Pattern Generator May Stop Working When Width is Changed
While Enabled
DNV28.
X
No Fix
UART_IE_TXD Signal May Be Low When IE Enters The Off State (Cloff)
DNV29.
X
No Fix
Intel® Trace Hub May Report Timeout Error Incorrectly
DNV30.
X
No Fix
Larger Than 32-bit Writes to Intel® Trace Hub CSR_MTB_BAR May Cause a System
Hang
DNV31.
X
No Fix
Potential Partial Trace Data Loss in Intel® Trace Hub ODLA When Storing to Memory
DNV32.
X
No Fix
Intel® Trace Hub Pipeline Empty Bit For PTI May be Not Set
DNV33.
X
No Fix
Intel® Trace Hub TAP Data Registers Are Read-once
DNV34.
X
No Fix
Performance Monitoring Event Branch Retired May Increment Twice For Near RET
Imm16
DNV35.
X
No Fix
Incorrect Number of Enabled Cores Reported in MSR_CORE_THREAD_COUNT
DNV36.
X
No Fix
NEWCENTURY_STS Cannot Be Cleared
DNV37.
X
No Fix
Intel® Processor Trace Timing Packets May Not be Generated When Clock
Modulation is Enabled
DNV38.
X
No Fix
Processor Host Root Complex May Incorrectly Route Memory Accesses to Intel®
Trace Hub
March 2018
Order Number: 336345-005US
Intel Atom® Processor C3000 Product Family
Specification Update
9
Intel Atom® Processor C3000 Product Family—Summary Tables of Changes
Table 2.
Specification Changes
Number
1.
Table 3.
Specification Change
Optional SMBALERT# Signal in SMB Controller - Legacy
Specification Clarifications
Number
NA
Table 4.
Specification Clarification
None to report at this time.
Documentation Changes
Number
NA
Documentation Change
None to report at this time.
§§
Intel Atom® Processor C3000 Product Family
Specification Update
10
March 2018
Order Number: 336345-005US
Identification Information—Intel Atom® Processor C3000 Product Family
Identification Information
Component Identification using Programming Interface
The CPU Identification (CPUID) instruction returns processor identification and feature
information to the EAX, EBX, ECX, and EDX registers, as determined by input entered
in EAX (and in some cases, ECX as well).
Details of the instruction can be found in the Instruction Set Reference portion of the
Intel® 64 and IA-32 Architectures Software Developer’s Manual.
When CPUID executes with EAX set to 01h, the SoC version information is returned in
EAX. See Figure 1, “Version Information Returned by CPUID in EAX”.
Figure 1.
Version Information Returned by CPUID in EAX
Note:
Once the SoC product is launched, the Intel® 64 and IA-32 Architectures Software
Developer’s Manual will refer to the SoC as having “DisplayFamily_DisplayModel” as
06_5FH.
Leaves 0 through 15h provides Basic CPUID Information.
Leaves 80000000h through 80000008h provide Extended CPUID Information.
Table 5, “CPUID Leaf 0h” through Table 25, “Extended CPUID Leaf 80000008h” contain
descriptions of the leaves and sub-leaves.
March 2018
Order Number: 336345-005US
Intel Atom® Processor C3000 Product Family
Specification Update
11
Intel Atom® Processor C3000 Product Family—Identification Information
CPUID Leaf 0 — Basic CPUID Information
Table 5.
Leaf
[EAX]
(Hex)
0
CPUID Leaf 0h
Sub-leaf
[ECX]
(Hex)
CPUID
Results
Bits
Meaning
Returned
Value
What Value
Indicates
Leaf 15h is the final leaf
for SoC Basic CPUID
Features
EAX
[31:0]
Maximum CPUID input value in
EAX that is recognized by the SoC
for its Basic CPUID Information.
Normally
0x15.
See bit 22
(BOOT_NT4)
of MSR 1A0h,
IA32_MISC_E
NABLE.
EBX
[31:0]
Intel identification, ASCII encoded
“uneG”
0x756E6547
“Genu”
ECX
[31:0]
Intel identification, ASCII encoded
“letn”
0x6C65746E
“ntel”
EDX
[31:0]
Intel identification, ASCII encoded
“Ieni”
0x49656E69
“ineI”
n/a
CPUID Leaf 1 — Version and Feature Information
Table 6.
Leaf
[EAX]
(Hex)
CPUID Leaf 1h, Output EAX and EBX
Sub-leaf
[ECX]
(Hex)
CPUID
Results
EAX
1
n/a
EBX
Bits
Meaning
[3:0]
Stepping ID
[7:4]
Model
Returned
Value
Varies by
product
release
0xF
What Value
Indicates
A0 Stepping = 0
A1 Stepping = 0
B0 Stepping = 1
0xF
[11:8]
Family ID
6
6
[13:12]
Processor Type
0
Original OEM Processor
[15:14]
(Reserved)
0
[19:16]
Extended Model ID
5
[27:20]
Extended Family ID
0
[7:0]
Brand Index
0
Brand String Method
used rather than Brand
Index Method
[15:8]
CLFLUSH line size
8
64 bytes
[23:16]
Maximum number of addressable
IDs for logical processors in this
package
0x20
[31:24]
APIC ID assigned during power up
Varies
Intel Atom® Processor C3000 Product Family
Specification Update
12
5
32 IDs Max
March 2018
Order Number: 336345-005US
Identification Information—Intel Atom® Processor C3000 Product Family
Table 7.
Leaf
[EAX]
(Hex)
1
CPUID Leaf 1h, Output ECX (Sheet 1 of 2)
Sub-leaf
[ECX]
(Hex)
n/a
CPUID
Results
ECX
March 2018
Order Number: 336345-005US
Bits
Returned
Value
Meaning
What Value
Indicates
0
SSE3 - Intel® Streaming SIMD
Extensions 3 (Intel® SSE3)
1
Supported
1
PCLMULDQ - PCLMULDQ
instruction
1
Supported
2
DTES64 - 64-bit DS Area
1
Supported
3
MONITOR/MWAIT feature
supported
4
DS_CPL - CPL Qualified Debug
Store
Varies
1
Depends on value of bit
18 in IA_MISC_ENABLE
(MSR 1A0h)
Supported
5
VMX - Virtual Machine Extensions
1
Supported
6
SMX - Safer Mode Extensions
0
Not Supported
7
EIST - Intel Enhanced SpeedStep®
Technology
1
Supported
1
Supported
®
Thermal Monitor 2
8
TM2 - Intel
9
SSSE3 - Supplemental Streaming
SIMD Extensions 3
1
Supported
10
CNXT-ID - L1 Context ID
0
Not Supported
11
Privacy MSR
1
Supported
12
FMA - Intel® Fast Memory Access
(Intel® FMA) extensions using
YMM state
0
Not Supported
13
CMPXCHG16B/CX16 - Compare
and Exchange Bytes features
1
Supported
14
xTPR Update Control - Allow
changing bit 23 of
IA32_MISC_ENABLE (MSR 1A0h)
1
Supported
15
PDCM - PerfMon and Debug
Capability, altering
IA32_PERF_CAPABILITIES
(MSR 345h)
1
Supported
16
(Reserved)
0
17
PCID - Process-Context Identifiers
0
Not Supported
18
DCA - Ability to prefetch data from
memory-mapped device
0
Not Supported
19
SSE4.1 - Intel® Streaming SIMD
Extensions 4.1
1
Supported
20
SSE4.2 - Intel® Streaming SIMD
Extensions 4.2
1
Supported
21
x2APIC - Extended Interrupt Mode
1
Supported
22
MOVBE - MOVBE instruction
1
Supported
23
POPCNT - POPCNT instruction
1
Supported
24
TSC-Deadline
1
Supported
25
AESNI - AESNI instruction
1
Supported
26
XSAVE - XSAVE/XRSTOR extended
states, XSETBV/XGETBV
instructions, and XCRO
1
Supported
Intel Atom® Processor C3000 Product Family
Specification Update
13
Intel Atom® Processor C3000 Product Family—Identification Information
Table 7.
CPUID Leaf 1h, Output ECX (Sheet 2 of 2)
OSXSAVE - A value of 1 indicates
the OS has set CR4.OSXSAVE
Varies
28
AVX - AVX instruction extensions.
0
Not Supported
29
F16C/IVBNI - 16-bit
floating-point conversion
instructions
0
Not Supported
Supported
27
1
n/a
ECX
30
RDRAND - RDRAND instruction
1
31
(Reserved)
0
Intel Atom® Processor C3000 Product Family
Specification Update
14
March 2018
Order Number: 336345-005US
Identification Information—Intel Atom® Processor C3000 Product Family
Table 8.
Leaf
[EAX]
(Hex)
1
CPUID Leaf 1h, Output EDX (Sheet 1 of 2)
Sub-leaf
[ECX]
(Hex)
n/a
CPUID
Results
Bits
What Value
Indicates
0
FPU - Floating Point Unit on Chip
1
Supported
1
VME - Virtual 8086 Mode
Enhancements
1
Supported
2
DE - Debugging Extensions
1
Supported
3
PSE - Page Size Extension
1
Supported
4
TSC - Time Stamp Counter
1
Supported
5
MSR - Model Specific Registers
RDMSR & WRMSR Instructions
1
Supported
6
PAE - Physical Address Extension
1
Supported
7
MCE - Machine Check Exception
1
Supported
8
CX8 - CMPXCHG8B Instruction
1
Supported
9
APIC - APIC On-Chip
10
(Reserved)
0
11
SEP - SYSTENTER & SYSEXIT
Instructions
1
Supported
12
MTRR - Memory Type Range
Registers
1
Supported
13
PGE - Page Global Bit
1
Supported
14
MCA - Machine Check Architecture
1
Supported
15
CMOV - Conditional Move
Instruction
1
Supported
16
PAT - Page Attribute Table
1
Supported
17
PSE-36 - 36-bit Page Size
Extension
1
Supported.
Physical addresses may
be up to 39 bits
18
PSN - Processor Serial Number
0
Not Supported
Supported
EDX
March 2018
Order Number: 336345-005US
Returned
Value
Meaning
Varies
1 if bit 11 of
IA32_APIC_BASE (MSR
1Bh) is set
19
CLFSH - CLFLUSH Instruction
1
20
(Reserved)
0
21
DS - Debug Store
1
Supported
22
ACPI - Software Controlled Clock
Facilities
1
Supported
23
MMX - Intel MMXTM technology
1
Supported
Intel Atom® Processor C3000 Product Family
Specification Update
15
Intel Atom® Processor C3000 Product Family—Identification Information
Table 8.
1
CPUID Leaf 1h, Output EDX (Sheet 2 of 2)
n/a
EDX
24
FXSR - FXSAVE and FXRSTOR
Instructions
1
Supported
25
SSE - Intel® Streaming SIMD
Extensions
1
Supported
26
SSE2 - Intel® Streaming SIMD
Extensions 2
1
Supported
27
SS - Self Snoop
1
Supported
28
HTT - Max APIC IDs reserved field
is Valid. See CPUID, Leaf 1,
EBX[23:16]
1
Supported
29
TM - Intel® Thermal Monitor
1
Supported
30
(Reserved)
0
31
PBE - Pending Break-Enable
1
Intel Atom® Processor C3000 Product Family
Specification Update
16
Supported
March 2018
Order Number: 336345-005US
Identification Information—Intel Atom® Processor C3000 Product Family
CPUID Leaf 2 — Cache and TLB Information
Table 9.
Leaf
[EAX]
(Hex)
CPUID Leaf 2h
Sub-leaf
[ECX]
(Hex)
CPUID
Results
Bits
Returned
Value
What Value
Indicates
[7:0]
Loop value - Number of times
CPUID leaf 2 must be executed to
retrieve complete information
about caches and TLBs.
0x01
One time
[15:8]
Micro Translation Lookaside Buffer
(uTLB) Descriptor
0xA0
4K pages,
fully associative,
32 entries
[23:16]
Data Translation Lookaside Buffer
(DTLB) Descriptor
0x64
4K pages,
4-way,
512 entries
[30:24]
Instruction Translation Lookaside
Buffer (ITLB) Descriptor
0x61
4K pages,
fully associative,
48 entries
[31]
Valid bit
[7:0]
Large-Page DTLB Descriptor
0xC2
2M and 4M pages,
4-way,
16 entries
[15:8]
General
0xFF
CPUID leaf 2 does not
report cache descriptor
information. Use CPUID
leaf 4 instead
[31:16]
(Reserved)
0
ECX
[31:0]
(Reserved)
0
EDX
[31:0]
(Reserved)
0
EAX
2
Meaning
n/a
EBX
0
Bits [30:0] are valid
CPUID Leaf 3— Reserved
The 96-bit processor serial number is not supported. For CPUID with EAX = 3, the
results in EAX, EBX, ECX and EDS are reserved and zeros are returned.
March 2018
Order Number: 336345-005US
Intel Atom® Processor C3000 Product Family
Specification Update
17
Intel Atom® Processor C3000 Product Family—Identification Information
CPUID Leaf 4— Deterministic Cache Parameters
CPUID leaf 4 has three sub-leaves.
Table 10.
Leaf
[EAX]
(Hex)
CPUID Leaf 4h (Sheet 1 of 2)
Sub-leaf
[ECX]
(Hex)
CPUID
Results
Bits
[4:0]
EAX
0
EBX
ECX
4
EDX
EAX
ECX
Returned
Value
Cache Type
0x1
[7:5]
Cache Level
0x1
8
Self Initializing Cache?
What Value
Indicates
Data Cache
Level 1 (L1)
1
Yes
No
9
Fully Associative?
0
[13:10]
(Reserved)
0
[25:14]
Max number of addressable IDs for
logical processors sharing this
cache
0
[31:26]
Max number of addressable IDs for
processor cores in the SoC physical
package (minus 1)
0xF
[11:0]
System Coherency Line Size
(minus 1)
[21:12]
Physical Line Partitions
[31:22]
[31:0]
0x3F
Max number is 1
Max number is 16
64
0
1 partition
Ways (minus 1)
5
6 Ways
Sets (minus 1)
0x3F
64 Sets
0
Write-back Invalidate/Invalidate
1
WBINVD/INVD is not
guaranteed to act upon
lower level caches of
non-originating threads
sharing this cache.
1
Cache Inclusiveness
0
Cache is not inclusive of
lower cache levels
2
Complex Cache Indexing
1
Complex Cache
Indexing supported
[31:3]
(Reserved)
0
[4:0]
Cache Type
0x2
Instruction Cache
[7:5]
Cache Level
0x1
Level 1 (L1)
8
Self Initializing Cache?
1
Yes
9
Fully Associative?
0
No
[13:10]
(Reserved)
0
[25:14]
Max number of addressable IDs for
logical processors sharing this
cache
0
[31:26]
Max number of addressable IDs for
processor cores in the SoC physical
package (minus 1)
0xF
[11:0]
System Coherency Line Size
(minus 1)
1
EBX
Meaning
0x3F
Max number is 1
Max number is 16
64
[21:12]
Physical Line Partitions
0
1 partition
[31:22]
Ways (minus 1)
7
8 Ways
[31:0]
Sets (minus 1)
0x3F
64 Sets
Intel Atom® Processor C3000 Product Family
Specification Update
18
March 2018
Order Number: 336345-005US
Identification Information—Intel Atom® Processor C3000 Product Family
Table 10.
CPUID Leaf 4h (Sheet 2 of 2)
1
EDX
EAX
4
2
EBX
ECX
0
Write-back Invalidate/Invalidate
1
WBINVD/INVD is not
guaranteed to act upon
lower level caches of
non-originating threads
sharing this cache.
1
Cache Inclusiveness
0
Cache is not inclusive of
lower cache levels
2
Complex Cache Indexing
1
Complex Cache
Indexing supported
[31:3]
(Reserved)
0
[4:0]
Cache Type
0x3
[7:5]
Cache Level
0x2
8
Self Initializing Cache?
Yes
No
9
Fully Associative?
0
[13:10]
(Reserved)
0
[25:14]
Maximum number of addressable
IDs for logical processors sharing
this cache (minus 1)
0x3
Max number is 4
[31:26]
Maximum number of addressable
IDs for processor cores in the SoC
physical package (minus 1)
0xF
Max number is 16
[11:0]
System Coherency Line Size
(minus 1)
[21:12]
Physical Line Partitions
[31:22]
Ways
[31:0]
Sets (minus 1)
0x3F
0
0xF
0x7FF
64
1 partition
16 Ways
2048 Sets
0
Write-back Invalidate/Invalidate
1
WBINVD/INVD is not
guaranteed to act upon
lower level caches of
non-originating threads
sharing this cache.
1
Cache Inclusiveness
0
Cache is not inclusive of
lower cache levels
Direct mapped cache
2
Complex Cache Indexing
0
[31:3]
(Reserved)
0
EAX
[31:0]
(Reserved)
0
EBX
[31:0]
(Reserved)
0
ECX
[31:0]
(Reserved)
0
EDX
[31:0]
(Reserved)
0
March 2018
Order Number: 336345-005US
Level 2 (L2)
1
EDX
3+
Unified Cache
Intel Atom® Processor C3000 Product Family
Specification Update
19
Intel Atom® Processor C3000 Product Family—Identification Information
CPUID Leaf 5— MONITOR/MWAIT
Except for EDX[31:0], values shown in Table 11, “CPUID Leaf 5h” are valid only when
MONITOR/MWAIT instructions are enabled.
Table 11.
Leaf
[EAX]
(Hex)
CPUID Leaf 5h
Sub-leaf
[ECX]
(Hex)
CPUID
Results
EAX
EBX
ECX
5
n/a
Bits
Meaning
Returned
Value
0x40
this can vary
depending on
filter size
What Value
Indicates
64 bytes or the filter
size, whichever is
smaller
[15:0]
Smallest monitor-line size in bytes
[31:16]
(Reserved)
[15:0]
Largest monitor-line size in bytes
[31:16]
(Reserved)
0
0
Enumeration of MONITOR-WAIT
extensions
1
Supported
1
Supports treating interrupts as
break-event for MWAIT, even when
interrupts disabled
1
Supported
[31:2]
(Reserved)
0
[3:0]
Number of MWAIT C0 sub-states
supported
0
0
[7:4]
Number of MWAIT C1 sub-states
supported
2
2
[11:8]
Number of MWAIT C2 sub-states
supported
0
0
[15:12]
Number of MWAIT C3 sub-states
supported
2
2
[19:16]
Number of MWAIT C4 sub-states
supported
4
4
[23:20]
Number of MWAIT C5 sub-states
supported
2
2
[27:24]
Number of MWAIT C6 sub-states
supported
0
0
[31:28]
Number of MWAIT C7 sub-states
supported
0
0
EDX
Intel Atom® Processor C3000 Product Family
Specification Update
20
0
0x40
this can vary
depending on
filter size
64 bytes or the filter
size, whichever is
smaller
March 2018
Order Number: 336345-005US
Identification Information—Intel Atom® Processor C3000 Product Family
CPUID Leaf 6— Digital Thermometer and Power Management
Table 12.
Leaf
[EAX]
(Hex)
CPUID Leaf 6h
Sub-leaf
[ECX]
(Hex)
CPUID
Results
EAX
6
n/a
EBX
Bits
March 2018
Order Number: 336345-005US
What Value
Indicates
0
Digital Thermal Sensor (DTS)
support
1
1
Intel® Turbo Boost Technology
0 or 1
2
ARAT APIC-Timer-always-running feature
1
3
(Reserved)
0
4
PLN - Power limit notification
controls support
0
Not Supported
5
ECMD - Clock modulation duty
cycle extension support
0
Not Supported
6
PTM - Package thermal
management support
0
Not Supported
[31:7]
(Reserved)
0
[3:0]
Number of Interrupt Thresholds in
Digital Thermal Sensor (DTS)
2
[31:4]
(Reserved)
0
0
Hardware Coordination Feedback
Capability
1
[2:1]
(Reserved)
0
3
Performance-Energy BIAS
Preference support
0
[31:4]
(Reserved)
0
[31:0]
(Reserved)
0
ECX
EDX
Returned
Value
Meaning
Supported
Support varies by
product SKU. BIOS can
also disable this
technology
Supported
2 thresholds
Supported.
IA32_MPERF (MSR E7h)
and IA32_APERF (MSR
E8h) are present
Not Supported
IA32_ENERGY_PERFOR
MANCE_BIAS (MSR
1B0h) is not available
Intel Atom® Processor C3000 Product Family
Specification Update
21
Intel Atom® Processor C3000 Product Family—Identification Information
CPUID Leaf 7— Extended feature Flags
The output shown in Table 13, “CPUID Leaf 7h” depends on the ECX input value.
Table 13.
Leaf
[EAX]
(Hex)
CPUID Leaf 7h (Sheet 1 of 2)
Sub-leaf
[ECX]
(Hex)
CPUID
Results
EAX
7
0
EBX
Bits
Meaning
Returned
Value
What Value
Indicates
[31:0]
Maximum supported sub-leaf for
CPUID leaf 7
0
Only sub-leaf 0
0
FSGSBASE - Support for
RDFSBASE/RDGSBASE/WRFSBASE
/WRGSBASE
1
Supported
1
Support for IA32_TSC_ADJUST
(MSR 3Bh)
1
Supported
2
SGX - Support for Secure Enclaves
(SE) and Intel® Software Guard
Extensions (Intel® SGX)
0
Not Supported
3
BMI1 - Bit Manipulation Set 1
0
Not Supported
4
HLE
0
Not Supported
5
AVX2 - Intel® Advanced Vector
Extensions 2 (Intel® AVX2)
0
Not Supported
6
(Reserved)
0
7
SMEP - Supervisor-Mode
Execution Prevention
1
Supported
8
BMI2 - Bit Manipulation Set 2
0
Not Supported
9
ERMS - Support for Enhanced REP
MOV/STOSB
1
Supported
10
INVPCID - Support for INVPCID
instruction
0
Not Supported
11
RTM - HLE+/RTM
0
Not Supported
12
Support for Platform Quality of
Service Monitoring (PQM)
capability
0
Not Supported
13
FPU CS and FPU DS Deprecation
1
The processor
depreciates FPU CS and
FPU DS values and
these fields are 0000h
14
Intel® Memory Protection
Extensions (Intel® MPX)
1
Supported
15
Support for Platform Quality of
Service Enforcement (PQE)
1
Supported
16
AVX512F - Intel® Advanced
Vector Extensions 512 (Intel® AVX512) Foundation instructions)
0
Not Supported
17
AVX512DQ - Intel® Advanced
Vector Extensions 512 (Intel® AVX512)
0
Not Supported
18
RDSEED - Read Random SEED
instruction
1
Supported
19
(Reserved)
0
20
SMAP - Supervisory Mode Access
Protection and the LAC/STAC
instructions
1
Intel Atom® Processor C3000 Product Family
Specification Update
22
Supported
March 2018
Order Number: 336345-005US
Identification Information—Intel Atom® Processor C3000 Product Family
Table 13.
CPUID Leaf 7h (Sheet 2 of 2)
EBX
7
AVX512IFMA - Intel® Advanced
Vector Extensions 512 (Intel® AVX512)
0
Not Supported
22
PCOMMIT - Persistent Commit
instruction
0
Not Supported
23
CLFLUSHOPT - Flush a Cache Line
Optimized instruction
1
Supported
24
(Reserved)
0
25
Intel® Processor Trace (Intel® PT)
1+
Intel®
1
Supported
26
AVX512PF Advanced
Vector Extensions 512 (Intel® AVX512)
0
Not Supported
27
AVX512ER - Intel® Advanced
Vector Extensions 512 (Intel® AVX512)
0
Not Supported
28
AVX512CD - Intel® Advanced
Vector Extensions 512 (Intel® AVX512)
0
Not Supported
29
SHA - Intel® Secure Hash
Algorithm Extensions (Intel® SHA
Extensions)
1
Supported
30
AVX512BW - Intel® Advanced
Vector Extensions 512 (Intel®
AVX-512)
0
Not Supported
31
AVX512VL - Intel® Advanced
Vector Extensions 512 (Intel®
AVX-512)
0
Not Supported
0
PREFETCHWT1 - PREFETCHWT1
instruction
0
Not Supported
1
AVX512VBMI - Intel® Advanced
Vector Extensions 512 (Intel®
AVX-512)
0
Not Supported
0
ECX
7
21
[31:2]
(Reserved)
0
EDX
[31:0]
(Reserved)
0
EAX
[31:0]
(Reserved)
0
EBX
[31:0]
(Reserved)
0
ECX
[31:0]
(Reserved)
0
EDX
[31:0]
(Reserved)
0
March 2018
Order Number: 336345-005US
Intel Atom® Processor C3000 Product Family
Specification Update
23
Intel Atom® Processor C3000 Product Family—Identification Information
CPUID Leaf 8 — Reserved
CPUID leaf 8 is not supported and is reserved. Zeros are returned.
CPUID Leaf 9 — Direct Cache Access (DCA) Information
CPUID leaf 9 is not supported and is reserved. Zeros are returned.
CPUID Leaf Ah — Architectural Performance Monitoring
Table 14.
Leaf
[EAX]
(Hex)
CPUID Leaf Ah
Sub-leaf
[ECX]
(Hex)
CPUID
Results
Bits
n/a
EDX
What Value
Indicates
Version ID of architectural
performance monitoring
4
Version 4
[15:8]
Number of general-purpose,
performance monitoring counters
per logical processor
4
4 counters
[23:16]
Bit width of general-purpose,
performance monitoring counter
0x30
[31:24]
Length of EBX bit vector to
enumerate architectural events
7
7
0
Core Cycle event unavailable
0
Core Cycle event is
available
1
Instruction Retired event
unavailable
0
Instruction Retired
event is available
2
Reference Cycles event unavailable
0
Reference Cycles event
is available
3
Last-level cache (L2 Cache)
reference event unavailable
0
Last-level cache (L2
Cache) reference event
is available
4
Last-level cache (L2 Cache) misses
event unavailable
0
Last-level cache (L2
Cache) misses event is
available
5
Branch instruction retired event
unavailable
0
Branch instruction
retired event is
available
6
Branch mispredict retired event
unavailable
0
Branch mispredict
retired event is
available
[31:0]
(Reserved)
0
[4:0]
Number of fixed-function
performance counters (if Version
ID > 1)
3
[12:5]
Bit width of fixed-function
performance counters (if Version
ID > 1)
0x30
[31:13]
(Reserved)
EBX
ECX
Returned
Value
[7:0]
EAX
A
Meaning
Intel Atom® Processor C3000 Product Family
Specification Update
24
48 bits
3 counters
48 bits
0
March 2018
Order Number: 336345-005US
Identification Information—Intel Atom® Processor C3000 Product Family
CPUID Leaf Bh — Extended Topology Enumeration
CPUID leaf Bh has two sub-leaves.
Table 15.
Leaf
[EAX]
(Hex)
CPUID Leaf Bh
Sub-leaf
[ECX]
(Hex)
CPUID
Results
EAX
EBX
0
ECX
EDX
EAX
B
EBX
1
ECX
2+
Bits
Meaning
Returned
Value
What Value
Indicates
[4:0]
Number of bits to shift right on
x2APIC ID (EDX[31:0]) to get a
unique topology ID of the next
level type
1
[31:5]
(Reserved)
0
[15:0]
Number of logical processors at
this level type. The number reflects
configuration as shipped by Intel
1
[31:16]
(Reserved)
0
[7:0]
Level Number - Same value as ECX
input
0
Level 0
SMT level
[15:8]
Level Type
1
[31:16]
(Reserved)
0
[31:0]
x2APIC ID the current logical
processor
[4:0]
Number of bits to shift right on
x2APIC ID (EDX[31:0]) to get a
unique topology ID of the next
level type
5
[31:5]
(Reserved)
0
[15:0]
Number of logical processors at
this level type. The number reflects
configuration as shipped by Intel
[31:16]
(Reserved)
0
[7:0]
Level Number - Same value as ECX
input
1
Shift right 1 bit
1 logical processor
Varies
2, 4, 8, 0xB,
or 0x10
Shift right 5 bits
2, 4, 8, 12, or 16
depending on product
SKU
Level 1
[15:8]
Level Type
2
Core level
[31:16]
(Reserved)
-
0
EDX
[31:0]
x2APIC ID the current logical
processor
EAX
[31:0]
(Reserved)
EBX
[31:0]
(Reserved)
ECX
[31:0]
Original ECX
EDX
[31:0]
(Reserved)
Varies
0
0
2+
0
CPUID Leaf Ch — Reserved
CPUID leaf Ch is not supported and is reserved. Zeros are returned.
CPUID Leaf Dh — Intel® Memory Protection Extensions (Intel® MPX), XSAVE
Feature
CPUID leaf Dh has six sub-leaves (0 through 4, and 8) and is shown in Table 16,
“CPUID Leaf Dh”. The other sub-leaves are reserved.
March 2018
Order Number: 336345-005US
Intel Atom® Processor C3000 Product Family
Specification Update
25
Intel Atom® Processor C3000 Product Family—Identification Information
Table 16.
Leaf
[EAX]
(Hex)
CPUID Leaf Dh (Sheet 1 of 2)
Sub-leaf
[ECX]
(Hex)
CPUID
Results
Meaning
Returned
Value
What Value
Indicates
0
X87 State - Legacy Floating Point
(x87/MMX)
1
Legacy FP state can be
managed by XSAVE
1
SSE State - Intel® Streaming
SIMD Extensions (Intel® SSE)
1
Intel® SSE state can be
managed by XSAVE
2
AVX State - Advanced Vector
Extensions (Intel® AVX)
0
Intel® AVX state cannot
be managed by XSAVE
3
BNDREGS State - Intel® Memory
Protection Extensions (Intel® MPX)
BNDREGS
1
Intel® MPX Bound
Registers (BNDREGS)
can be managed by
XSAVE
4
BNDCSR State - Intel® Memory
Protection Extensions (Intel® MPX)
BNDCSR
1
Intel® MPX Bound
Control and Status
Register (BNDCSR) can
be managed by XSAVE
[7:5]
AVX-512 State - Intel® Advanced
Vector Extensions 512 (Intel®
AVX-512)
0
Intel® AVX-512 not
supported and cannot
can be managed by
XSAVE
8
PT State - Intel® Processor Trace
(Intel® PT), used for IA32_XSS
(MSR DA0h)
0
Intel® PT MSRs state
cannot can be managed
by XSAVE
9
PKRU State - Protection-key
feature’s register PKRU
0
PKRU state cannot can
be managed by XSAVE
[31:10]
(Reserved)
0
EBX
[31:0]
Maximum size required for features
enabled in XCR0
0x240
576 bytes
ECX
[31:0]
Max size required by all processor
supported features
0x440
1088 bytes
EDX
[31:0]
(Reserved)
0
0
Availability of XSAVEOPT
1
Available
1
Support of XSAVEC and compact
extensions of legacy XSTROR
1
Supported
2
Support of XGETBV Leaf 1
1
Supported
3
Support of XSAVES and XRSTORS
instructions, and IA32_XSS (MSR
DA0h)
1
Supported
[31:4]
(Reserved)
0
[31:0]
Maximum size required for features
enabled in XCR0 | IA32_XSS (MSR
DA0h)
[7:0]
(Reserved)
0
8
PT State - Intel® Processor Trace
(Intel® PT)
1
[31:9]
(Reserved)
0
[31:0]
(Reserved)
0
EAX
0
D
Bits
EAX
1
EBX
ECX
EDX
Intel Atom® Processor C3000 Product Family
Specification Update
26
0x240
576 bytes
Corresponding bit in
IA32_XSS (MSR DA0h)
can be set
March 2018
Order Number: 336345-005US
Identification Information—Intel Atom® Processor C3000 Product Family
Table 16.
CPUID Leaf Dh (Sheet 2 of 2)
2
3
D
4
EAX
[31:0]
(Reserved)
0
EBX
[31:0]
(Reserved)
0
ECX
[31:0]
(Reserved)
0
EDX
[31:0]
(Reserved)
0
EAX
[31:0]
Intel® Memory Protection
Extensions (Intel® MPX) - Size of
feature state-save area
EBX
[31:0]
Intel® MPX - Offset of feature
state-save area
ECX
[31:0]
(Reserved)
0
EDX
[31:0]
(Reserved)
0
EAX
[31:0]
Intel® MPX - Size of feature
state-save area
EBX
[31:0]
Intel® MPX - Offset of feature
state-save area
ECX
[31:0]
(Reserved)
0
EDX
[31:0]
(Reserved)
0
EAX
[31:0]
Intel® Processor Trace (Intel® PT)
- Size of Intel® PT state-save area
EBX
[31:0]
(Reserved)
0
0
Intel® PT - Supervisor State
1
8
ECX
All other
values of
ECX
0x40
0x3C0
0x40
0x400
0x80
[31:1]
(Reserved)
0
EDX
[31:0]
(Reserved)
0
EAX
[31:0]
(Reserved)
0
EBX
[31:0]
(Reserved)
0
ECX
[31:0]
(Reserved)
0
EDX
[31:0]
(Reserved)
0
March 2018
Order Number: 336345-005US
64 bytes
960 bytes
64 bytes
1024 bytes
128 bytes
Intel® PT is supported
in IA32_XSS (MSR
DA0h)
Intel Atom® Processor C3000 Product Family
Specification Update
27
Intel Atom® Processor C3000 Product Family—Identification Information
CPUID Leaf Eh — Reserved
CPUID leaf Eh is not supported and is reserved. Zeros are returned.
CPUID Leaf Fh — Platform and Cache Quality of Service (QoS)
CPUID leaf Fh, Platform QoS Monitoring Enumeration and Cache QoS Monitoring
Capability, is not supported and is reserved. Zeros are returned.
CPUID Leaf 10h — Platform and Cache QoS Enforcement Enumeration
CPUID leaf 10h contains three sub-leaves and is show in Table 17, “CPUID Leaf 10h”.
Table 17.
Leaf
[EAX]
(Hex)
CPUID Leaf 10h
Sub-leaf
[ECX]
(Hex)
CPUID
Results
EAX
0
1
10
EBX
Returned
Value
What Value
Indicates
[31:0]
(Reserved)
0
0
(Reserved)
0
1
L3 Cache
0
SoC has no L3 Cache
Supports L2 Cache QoS
Enforcement
2
L2 Cache
1
[31:3]
(Reserved)
0
[31:0]
(Reserved)
0
EDX
[31:0]
(Reserved)
0
EAX
[31:0]
(Reserved)
0
EBX
[31:0]
(Reserved)
0
ECX
[31:0]
(Reserved)
0
EDX
[31:0]
(Reserved)
0
[4:0]
Length of Masks (minus 1)
7
[31:5]
(Reserved)
0
EBX
[31:0]
Bitmask
0
ECX
[31:0]
(Reserved)
0
[15:0]
Highest COS number supported for
this ResID (minus 1)
3
EDX
3+
Meaning
ECX
EAX
2
Bits
[31:16]
(Reserved)
0
EAX
[31:0]
(Reserved)
0
EBX
[31:0]
(Reserved)
0
ECX
[31:0]
(Reserved)
0
EDX
[31:0]
(Reserved)
0
Intel Atom® Processor C3000 Product Family
Specification Update
28
8
4 is highest number
March 2018
Order Number: 336345-005US
Identification Information—Intel Atom® Processor C3000 Product Family
CPUID Leaf 11h — Reserved
CPUID leaf 11h is not supported and is reserved. Zeros are returned.
CPUID Leaf 12h — Reserved
CPUID leaf 12h is not supported and is reserved. Zeros are returned.
CPUID Leaf 13h — Reserved
CPUID leaf 13h is not supported and is reserved. Zeros are returned.
March 2018
Order Number: 336345-005US
Intel Atom® Processor C3000 Product Family
Specification Update
29
Intel Atom® Processor C3000 Product Family—Identification Information
CPUID Leaf 14h — Intel® Processor Trace (Intel® PT) Enumeration
CPUID leaf 14h has two sub-leaves and is shown in Table 18, “CPUID Leaf 14h”.
Table 18.
Leaf
[EAX]
(Hex)
CPUID Leaf 14h (Sheet 1 of 2)
Sub-leaf
[ECX]
(Hex)
CPUID
Results
EAX
EBX
0
14
ECX
Bits
[31:0]
Meaning
Maximum valid sub-leaf
Returned
Value
What Value
Indicates
1
Only sub-leaves 0 and 1
are valid
0
CR3 Filtering Support
1
IA32_RTIT_CTL (MSR
570h) can be set to 1,
and that
IA32_RTIT_CR3_MATC
H (MSR 572h) can be
accessed
1
Support for Cycle-Accurate Mode
and Configurable PSB
1
Supported
2
Support for IP filtering, TraceStop
filtering, and MTC timing packet
1
Supported
3
Support for Processor Trace MSRs
preserved across warm reset
1
Supported
[31:4]
(Reserved)
0
0
Support of ToPA Output scheme
1
Supported. Tracing can
be enabled with the
ToPA bit of
IA32_RTIT_CTL (MSR
570h)
1
ToPA Tables Support Multiple
Output Regions
1
Supported
2
Support of Single-Range Output
scheme
1
Supported
3
Support of output to Trace
Transport subsystem
0
Not Supported
[30:2]
(Reserved)
0
Generated packets
which contain IP
payloads contain LIP
values, which include
the CS base component
31
Support of IP payloads contain LIP
1
[31:0]
(Reserved)
0
[1:0]
Number of configurable Address
Ranges for filtering supported
2
[15:2]
(Reserved)
0
[31:16]
Bitmap of supported MTC Period
encodings
0x249
0x249
[15:0]
Bitmap of supported Cycle
Threshold Value encodings
0xFFFF
0xFFFF
[31:16]
Bitmap of supported configurable
PSB Frequency encodings
0x003F
0x003F
ECX
[31:0]
(Reserved)
0
EDX
[31:0]
(Reserved)
0
EDX
EAX
1
EBX
Intel Atom® Processor C3000 Product Family
Specification Update
30
2 ranges
March 2018
Order Number: 336345-005US
Identification Information—Intel Atom® Processor C3000 Product Family
Table 18.
14
CPUID Leaf 14h (Sheet 2 of 2)
2+
EAX
[31:0]
(Reserved)
0
EBX
[31:0]
(Reserved)
0
ECX
[31:0]
(Reserved)
0
EDX
[31:0]
(Reserved)
0
CPUID Leaf 15h — Time Stamp Counter (TSC) and Crystal Clock Ratio
CPUID leaf 15h is the last Basic CPUID leaf.
Table 19.
Leaf
[EAX]
(Hex)
15
Basic CPUID Leaf 15h
Sub-leaf
[ECX]
(Hex)
n/a
CPUID
Results
Bits
Meaning
Returned
Value
EAX
[31:0]
Denominator of TSC/crystal clock
ratio
EBX
[31:0]
Numerator of TSC/crystal clock
ratio
ECX
[31:0]
(Reserved)
0
EDX
[31:0]
(Reserved)
0
March 2018
Order Number: 336345-005US
3
0xC0
What Value
Indicates
3
192
Intel Atom® Processor C3000 Product Family
Specification Update
31
Intel Atom® Processor C3000 Product Family—Identification Information
CPUID Leaves 16h through 7FFFFFFFh — Reserved
CPUID leaves 16h through 7FFFFFFFh are not supported and are reserved. Each of
these leaves produces the same EAX, EBX, ECX, and EDS values as leaf 15h.
CPUID leaves greater than 80000000h are also reserved and produce the same EAX,
EBX, ECX, and EDS values as leaf 15h.
CPUID Leaf 80000000h — Maximum EAX Value for CPUID Instruction
Table 20.
Leaf
[EAX]
(Hex)
80000000
Extended CPUID Leaf 80000000h
Sub-leaf
[ECX]
(Hex)
n/a
CPUID
Results
Bits
Meaning
Returned
Value
EAX
[31:0]
Maximum input value in EAX for
Extended Function CPUID
information
EBX
[31:0]
(Reserved)
0
ECX
[31:0]
(Reserved)
0
EDX
[31:0]
(Reserved)
0
Intel Atom® Processor C3000 Product Family
Specification Update
32
0x80000008
What Value
Indicates
0x80000008 is the
maximum value
March 2018
Order Number: 336345-005US
Identification Information—Intel Atom® Processor C3000 Product Family
CPUID Leaf 80000001h — Extended Feature Flags
Table 21.
Leaf
[EAX]
(Hex)
Extended CPUID Leaf 80000001h
Sub-leaf
[ECX]
(Hex)
CPUID
Results
Meaning
Returned
Value
What Value
Indicates
EAX
[31:0]
(Reserved)
0
EBX
[31:0]
(Reserved)
0
0
Availability of LAHF and SAHF
instructions in 64-bit mode
1
Available
5
Availability of LZCNT instruction
0
Not Available
[7:1]
(Reserved)
0
8
Availability of PREFETCHW
instruction
1
[31:9]
(Reserved)
0
[10:0]
(Reserved)
0
11
Availability of SYSCALL and
SYSTRET instructions in 64-bit
mode
1
[19:12]
(Reserved)
0
20
Availability of the Execute Disable
Bit
[25:21]
(Reserved)
ECX
80000001
Bits
n/a
Varies
EDX
March 2018
Order Number: 336345-005US
Available
Available
1 indicates Available.
Will be 1 whenever the
NX_DISABLE bit of
IA32_CR_MISC_ENABL
ES (MSR 1A0h) = 0
0
26
1GB Pages
1
Enabled
27
RDTSCP/IA32_TSC_AUX
1
1
28
(Reserved)
0
29
Availability of Intel® 64
Architecture
1
[31:30]
(Reserved)
0
Available
Intel Atom® Processor C3000 Product Family
Specification Update
33
Intel Atom® Processor C3000 Product Family—Identification Information
CPUID Leaves 80000002h, 80000003h, and 80000004h— Intel Processor
Brand String
Table 22.
Leaf
[EAX]
(Hex)
Extended CPUID Leaves 80000002h, 80000003h, and 80000004h
Sub-leaf
[ECX]
(Hex)
CPUID
Results
EAX
80000002
80000003
80000004
n/a
n/a
n/a
Bits
Meaning
Returned
Value
[31:0]
65746E49
EBX
[31:0]
2952286C
ECX
[31:0]
6F744120
EDX
[31:0]
4D54286D
EAX
[31:0]
50432029
EBX
[31:0]
ECX
[31:0]
EDX
[31:0]
2E322040
EAX
[31:0]
48473030
Processor Brand String
What Value
Indicates
33432055
20383538
EBX
[31:0]
7A
ECX
[31:0]
0
EDX
[31:0]
0
CPUID Leaf 80000005h — Reserved
CPUID leaf 80000005h is not supported and is reserved. Zeros are returned.
CPUID Leaf 80000006h — Cache Parameters
Table 23.
Leaf
[EAX]
(Hex)
80000006
Extended CPUID Leaf 80000006h
Sub-leaf
[ECX]
(Hex)
n/a
CPUID
Results
Bits
Meaning
Returned
Value
EAX
[31:0]
(Reserved)
0
EBX
[31:0]
(Reserved)
0
[7:0]
Cache Line Size
ECX
[15:12]
Associativity field
[31:16]
Cache size in 1k units
[31:0]
(Reserved)
EDX
Intel Atom® Processor C3000 Product Family
Specification Update
34
0x40
0x8
0x800
What Value
Indicates
64
8
2048 1k units (2MB)
0
March 2018
Order Number: 336345-005US
Identification Information—Intel Atom® Processor C3000 Product Family
CPUID Leaf 80000007h — Advanced Power Management
Table 24.
Leaf
[EAX]
(Hex)
80000007
Extended CPUID Leaf 80000007h
Sub-leaf
[ECX]
(Hex)
n/a
CPUID
Results
Bits
Meaning
Returned
Value
EAX
[31:0]
(Reserved)
0
EBX
[31:0]
(Reserved)
0
ECX
[31:0]
(Reserved)
0
[7:0]
(Reserved)
0
EDX
8
Always Running TSC
1
[31:9]
(Reserved)
0
What Value
Indicates
Available
CPUID Leaf 80000008h — Virtual/Physical Address Sizes
Table 25.
Leaf
[EAX]
(Hex)
Extended CPUID Leaf 80000008h
Sub-leaf
[ECX]
(Hex)
CPUID
Results
EAX
80000008
n/a
Bits
Meaning
Returned
Value
[7:0]
Number of Physical Address Bits
0x27
39 bits
[15:8]
Number of Linear Address Bits
0x30
48 bits
[31:16]
(Reserved)
0
EBX
[31:0]
(Reserved)
0
ECX
[31:0]
(Reserved)
0
EDX
[31:0]
(Reserved)
0
March 2018
Order Number: 336345-005US
What Value
Indicates
Intel Atom® Processor C3000 Product Family
Specification Update
35
Intel Atom® Processor C3000 Product Family—Identification Information
The BIOS is able to determine the silicon stepping of the entire SoC. This is
accomplished by reading the 32-bit Manufacturer ID Register in configuration space,
bus 0, device 0, function 0, offset F4h. The Bit 15:8 shows manufacturing ID which is
processor ID. PCI Rev ID is located on bus0, device 31, function0, offset 08h bit 7:0.
Table 26 shows the information received when this register is read.
Table 26.
SoC Stepping Information
Parameter
B1
SoC
Process ID
0Fh
PC Rev ID
11
In addition to verifying the processor signature, the BIOS needs the platform ID to
properly target the microcode update. The platform ID is determined by reading bits
[52:50] of the IA32_PLATFORM_ID register, (MSR 17h). This is a 64-bit register and is
read using the RDMSR instruction. The three platform ID bits, when read as a Binary
Coded Decimal (BCD) number, indicate the bit position in the microcode update header
processor flags field that is associated with the installed processor.
Intel Atom® Processor C3000 Product Family
Specification Update
36
March 2018
Order Number: 336345-005US
Identification Information—Intel Atom® Processor C3000 Product Family
Component Marking Information
The Intel Atom® Processor C3000 Product Family may be identified by the following
component markings:
Table 27.
Component Marking Information
Stepping
SKU Name
S-Spec
Top Marking
Core Count
B1 Production
SKU 0
SR3F3
SR3F3
16C
B1 Production
SKU 1
SR383
SR383
16C
B1 Production
SKU 2
SR387
SR387
12C
B1 Production
SKU 3
SR386
SR386
12C
B1 Production
SKU 4
SR385
SR385
8C
B1 Production
SKU 5
SR381
SR381
16C
B1 Production
SKU 6
SR38A
SR38A
12C
B1 Production
SKU 7
SR389
SR389
8C
B1 Production
SKU 8
SR388
SR388
4C
B1 Production
SKU 9
SR3L7
SR3L7
4C
B1 Production
SKU 10
SR38B
SR38B
2C
B1 Production
SKU 11
SR38C
SR38C
12C
B1 Production
SKU 12
SR38F
SR38F
8C
B1 Production
SKU 13
SR3JX
SR3JX
4C
B1 Production
SKU 14
SR38D
SR38D
2C
Note:
For detailed SKU definition, please refer to chapter 1 of the Intel® Atom™ Processor C3000 Product
Family External Design Specification [EDS], Volumes 1, 2, 3, and 4 (Doc ID #558579).
March 2018
Order Number: 336345-005US
Intel Atom® Processor C3000 Product Family
Specification Update
37
Intel Atom® Processor C3000 Product Family—Identification Information
Figure 2.
Top Markings
Table 28.
Top Markings
Side
Group
Line
Text
Example
Top
1
1
\ (this is the Intel swirl)
Top
1
2
INTEL CONFIDENTIAL
INTEL CONFIDENTIAL
Top
1
3
NA
NA
Top
1
4
“SPEC””SPEC#Q” “SPEED”GHZ
QJ3C 1.70GHZ
Top
1
5
{FPO} {e1}
Top
4
7
Blank/Number
FPO45678
752RP488801939
§§
Intel Atom® Processor C3000 Product Family
Specification Update
38
March 2018
Order Number: 336345-005US
Errata—Intel Atom® Processor C3000 Product Family
Errata
DNV1.
HECI Line Interrupt May Not be Generated
Problem:
There are three different HECI (Host Embedded Controller Interface) interfaces used to
communicate between IE (Innovation Engine)/ME (Management Engine) and the host
CPU cores. Due to this erratum, if any HECI interfaces are configured to send different
types of line interrupts (INTA, INTB, INTC, INTD, SMI, SCI and NMI), then interrupts
may not be generated as expected.
Implication:
An interrupt being missed may lead to the system hanging or experiencing other
unexpected behavior. MSIs are not affected by this erratum.
Workaround: Software should configure all line interrupts to use the same type or use MSIs.
Status:
No Fix.
DNV2.
xHCI Host Controller Reset May Cause A System Hang
Problem:
xHCI Host Controller may not respond following system software setting (Bit 1 = '1')
the Host Controller Reset (HCRST) of the USB Command register (xHCIBAR+ 80h).
Implication:
CATERR may occur resulting in a system hang.
Workaround: A 1ms delay is necessary following system software setting (Bit 1 = '1') the Host
Controller Reset (HCRST) of the USB Command register (xHCIBAR + 80h).
Status:
No Fix.
DNV3.
USB DBC-EXI Is Not Enumerated Correctly
Problem:
USB DBC-EXI (Debug Capability External Interface) incorrectly returned non-zero
indexes with zero length device descriptor strings.
Implication:
Software may fail to enumerate the device when non-zero length device descriptor
strings are returned with non-zero indexes.
Workaround: Software can ignore device descriptor strings that are zero length even if the index is
non-zero.
Status:
No Fix.
March 2018
Order Number: 336345-005US
Intel Atom® Processor C3000 Product Family
Specification Update
39
Intel Atom® Processor C3000 Product Family—Errata
DNV4.
Performance Monitoring Event Branch Retired May Increment Twice
For Near RET Imm16
Problem:
A Near RET imm16 instruction may increment performance monitoring event
BR_INST_RETIRED.ALL_BRANCHES (Event C4H, UMask 00H) twice instead of once.
This erratum does not occur if the UMask bits 3 (BR_INST_RETIRED.REMOVE_RET)
and/or 7 (BR_INST_RETIRED.REMOVE_NOT_TAKEN_JCC) are set.
Implication:
A performance monitoring counter counting the branch retired event may overcount.
Software relying on the branch retired event incrementing deterministically may not
function correctly.
Workaround: None identified. Software could have one counter count all branches other than nottaken JCC (UMask 7FH) and another counter count not-taken JCC (UMask 80) and sum
them to produce the total count.
Status:
No Fix.
DNV5.
NCSI_RXD Output Cannot be Tri-State to Meet NCSI Specification
Problem:
When a NCSI (Network Controller Sideband Interface) interface is de-selected, the
NCSI receive Data NCSI_RXD[1:0] lines are constantly driven to “0” instead of entering
tri-state mode.
Implication:
This erratum prevents correct functionality of a shared-bus (multi-drop) NCSI topology.
This issue does not affect point-to-point NCSI configuration design topology.
Workaround: None identified.
Status:
No Fix.
DNV6.
The X553 Ethernet Controller Transmitter Transition Time Does Not
Conform To IEEE 802.3 Specification
Problem:
The X553 transmitter may not meet IEEE 802.3 clause 70 1000BASE-X specification for
transition time compliance.
Implication:
Compliance Testing may report specification violations. Intel has not observed any
functional impact due to this errata. Intel has obtained a waiver.
Workaround: None identified.
Status:
No Fix.
DNV7.
10 GBASE-KR Transmitter Does Not Fully Conform To Specification For
Equalization
Problem:
The processor's 10GBASE-KR transmitter does not conform to
IEEE 802.3ap-2007 electrical specification.
— Section 72.7.1.11 - For any coefficient update, the magnitudes of the changes
in v1, v2, and v3 shall be within 5 mV of each other but processor's limit is
11mV.
— Table 72-8 - The pre cursor equalization ratio (Rpre) is to be in range 0.95 1.05 with a coefficient status of c (1) disabled, c(0) maximum, and c(-1)
disabled; the processor Rpre ratio is in the range 0.95 to 1.08 with the
coefficient status listed.
Implication:
Compliance testing may report specification violations. Intel has not observed any
functional impact due to this erratum. Intel has obtained a waiver.
Workaround: None identified.
Status:
No Fix.
Intel Atom® Processor C3000 Product Family
Specification Update
40
March 2018
Order Number: 336345-005US
Errata—Intel Atom® Processor C3000 Product Family
DNV8.
Split Access to APIC-access Page May Access Virtual-APIC Page
Problem:
A read from the APIC-access page that splits a cacheline boundary should cause an
APIC-access VM exit. Due to this erratum, the processor may redirect such accesses to
the virtual-APIC page without causing an APIC-access VM exit.
Implication:
Guest software that attempts to access its APIC with a cacheline split may not be
properly virtualized.
Workaround: None identified.
Status:
No Fix.
DNV9.
PEBS Record EventingIP Field May be Incorrect After CS.Base Change
Problem:
Due to this erratum, a PEBS (Precise Event Base Sampling) record generated after an
operation that changes the CS.Base may contain an incorrect address in the EventingIP
field.
Implication:
Software attempting to identify the instruction that caused the PEBS event may report
an incorrect instruction when non-zero CS.Base is supported and CS.Base is changed.
Intel has not observed this erratum to impact the operation of any commercially
available system.
Workaround: None identified.
Status:
No Fix.
DNV10.
Performance Monitor Instructions Retired Event May Not Count
Consistently
Problem:
Performance Monitor Instructions Retired (Event C0H; Umask 00H) and the instruction
retired fixed counter (IA32_FIXED_CTR0 MSR (309H)) are used to track the number of
instructions retired. Due to this erratum, certain situations may cause the counter(s) to
increment when no instruction has retired or to not increment when specific
instructions have retired.
Implication:
A performance counter counting instructions retired may over or under count. The
count may not be consistent between multiple executions of the same code.
Workaround: None identified.
Status:
No Fix.
DNV11.
SMRAM State-Save Area Above the 4GB Boundary May Cause
Unpredictable System Behavior
Problem:
If BIOS uses the RSM instruction to load the SMBASE register with a value that would
cause any part of the SMRAM state-save area to have an address above 4-GBytes,
subsequent transitions into and out of SMM (system-management mode) might save
and restore processor state from incorrect addresses.
Implication:
This erratum may cause unpredictable system behavior. Intel has not observed this
erratum with any commercially available system.
Workaround: Ensure that the SMRAM state-save area is located entirely below the 4GB address
boundary.
Status:
No Fix.
March 2018
Order Number: 336345-005US
Intel Atom® Processor C3000 Product Family
Specification Update
41
Intel Atom® Processor C3000 Product Family—Errata
DNV12.
POPCNT Instruction May Take Longer to Execute Than Expected
Problem:
POPCNT instruction execution with a 32 or 64 bit operand may be delayed until
previous non-dependent instructions have executed.
Implication:
Software using the POPCNT instruction may experience lower performance than
expected.
Workaround: None identified.
Status:
No Fix.
DNV13.
APIC-access VM Exit May Occur instead of SMAP #PF
Problem:
A supervisor-mode data access through a user-mode page should cause a #PF if
CR4.SMAP (Supervisor-Mode Access Prevention) is 1 and EFLAGS.AC is 0. Due to this
erratum, a guest supervisor mode access to the APIC-access page may cause an APICaccess VM exit instead of a #PF due to SMAP.
Implication:
A guest may miss an SMAP violation if it maps its APIC through a user-mode page.
Intel has not observed this erratum with any commercially available software.
Workaround: Guest software should not map their APIC to a user mode page and attempt to access
it from supervisor mode.
Status:
No Fix.
DNV14.
Some Performance Counter Overflows May Not Be Logged in
IA32_PERF_GLOBAL_STATUS When FREEZE_PERFMON_ON_PMI is
Enabled
Problem:
When enabled, FREEZE_PERFMON_ON_PMI bit 12 in IA32_DEBUGCTL MSR (1D9H)
freezes PMCs (performance monitoring counters) on a PMI (Performance Monitoring
Interrupt) request by setting CTR_Frz bit 49 in IA32_PERF_GLOBAL_STATUS MSR
(38EH). Due to this erratum, if FREEZE_PERFMON_ON_PMI is enabled, PMC overflows
that occur within a few cycles of a PMI being pended may not be logged in
IA32_PERF_GLOBAL_STATUS MSR.
Implication:
A performance counter may overflow but not set the overflow bit in
IA32_PERF_GLOBAL_STATUS MSR.
Workaround: Re-enabling the PMCs in UA32_PERF_GLOBAL_CTRL will log the overflows that were
not previously logged in IA32_GLOBAL_STATUS.
Status:
No Fix.
DNV15.
Performance Monitoring OFFCORE_RESPONSE1 Event May Improperly
Count L2 Evictions
Problem:
Due to this erratum, a performance monitoring counter configured to count
OFFCORE_RESPONSE1 (Event B7H, Umask 02H) uses MSR_OFFCORE_RSP0.COREWB
(MSR 1A6H, bit 3) instead of the expected MSR_OFFCORE_RSP1.COREWB (MSR 1A7H,
bit 3).
Implication:
A performance monitoring counter using the OFFCORE_RESPONSE1 event will not
count L2 evictions as expected when the COREWB value is not the same in
MSR_OFFCORE_RSP1 and in MSR_OFFCORE_RSP0.
Workaround: None identified
Status:
No Fix.
Intel Atom® Processor C3000 Product Family
Specification Update
42
March 2018
Order Number: 336345-005US
Errata—Intel Atom® Processor C3000 Product Family
DNV16.
Debug Exception May Not be Generated on Memory Read Spanning a
Cacheline Boundary
Problem:
A debug exception should be generated on a read which accesses an address specified
by a breakpoint address register (DR0-DR3) and its LENn field (in DR7) configured to
monitor data reads. Due to this erratum, under complex microarchitectural conditions
the processor may not trigger a debug exception on a memory read that spans a
cacheline boundary.
Implication:
When this erratum occurs, a debugger is not notified of a read that matches a data
breakpoint.
Workaround: None identified.
Status:
No Fix.
DNV17.
Intel® PT CR3 Filtering Compares Bits [11:5] of CR3 and
IA32_RTIT_CR3_MATCH Outside of PAE Paging Mode
Problem:
CR3[11:5] are used to locate the page-directory-pointer table only in PAE paging
mode. When using Intel PT (Processor Trace), those bits of CR3 are compared to
IA32_RTIT_CR3_MATCH (MSR 572H) when IA32_RTIT_CTL.CR3Filter (MSR 570H bit 7)
is set, independent of paging mode.
Implication:
Any value written to the ignored CR3[11:5] bits which can only be non-zero outside of
PAE paging mode must also be written to IA32_RTIT_CR3_MATCH[11:5] in order to
result in a CR3 filtering match.
Workaround: None identified.
Status:
No Fix.
DNV18.
Intel® PT OVF Packet May Be Followed by TIP.PGD Packet
Problem:
If Intel PT (Processor Trace) encounters an internal buffer overflow and generates an
OVF (Overflow) packet just as IA32_RTIT_CTL (MSR 570H) bit 0 (TraceEn) is cleared,
or during a far transfer that causes IA32_RTIT_STATUS.ContextEn[1] (MSR 571H) to
be cleared, the OVF may be followed by a TIP.PGD (Target Instruction Pointer - Packet
Generation Disable) packet.
Implication:
The Intel PT decoder may not expect a TIP.PGD to follow an OVF which could cause a
decoder error.
Workaround: The Intel PT decoder should ignore a TIP.PGD that immediately follows OVF.
Status:
No Fix.
DNV19.
Intel® PT OVF May Be Followed By an Unexpected FUP Packet
Problem:
Certain Intel PT (Processor Trace) packets, including FUPs (Flow Update Packets),
should be issued only between TIP.PGE (Target IP Packet - Packet Generation Enable)
and TIP.PGD (Target IP Packet - Packet Generation Disable) packets. When outside a
TIP.PGE/TIP.PGD pair, as a result of IA32_RTIT_STATUS.FilterEn[0] (MSR 571H) being
cleared, an OVF (Overflow) packet may be unexpectedly followed by a FUP.
Implication:
The Intel PT decoder may incorrectly assume that tracing is enabled and resume
decoding from the FUP IP.
Workaround: The Intel PT decoder may opt to scan ahead for other packets to confirm whether
PacketEn is set.
Status:
No Fix.
March 2018
Order Number: 336345-005US
Intel Atom® Processor C3000 Product Family
Specification Update
43
Intel Atom® Processor C3000 Product Family—Errata
DNV20.
Performance Monitoring COREWB Offcore Response Event May
Overcount
Problem:
An L2 eviction may affect the OFFCORE_RSP0 or OFFCORE_RSP1 performance
monitoring events if it is configured to count COREWB occurrences or average offcore
request latency even if the eviction was caused by an access made by a different core
sharing the L2 cache.
Implication:
The offcore response events may overcount when configured to count COREWB
occurrence.
Workaround: None identified.
Status:
No Fix.
DNV21.
FBSTP May Update FOP/FIP/FDP/FSW Before Exception or VM Exit
Problem:
Due to this erratum, a FBSTP whose memory access causes an exception (e.g. #PF or
#GP) or VM exit (e.g. EPT violation), may unexpectedly update FOP, FIP, FDP, FSW.IE or
FSW.PE. FSW.ES is not affected by this erratum.
Implication:
An x87 exception handler that executes an FBSTP but relies on the FP exception state
being unchanged after taking a memory exception may not behave as expected. Intel
has not observed this erratum with any commercially available software.
Workaround: None identified.
Status:
No Fix.
DNV22.
PEBS Record May be Generated When Counters Frozen
Problem:
When Performance Monitoring counters are frozen due to
IA32_PERF_GLOBAL_STATUS.CTR_Frz MSR (38EH, bit 59) being set, a PEBS (Processor
Event Based Sampling) record may still be generated for counter 0 when the event
specified by IA32_PERFEVTSEL0 MSR (186H) occurs.
Implication:
An unexpected PEBS record may cause performance analysis software to behave
unexpectedly.
Workaround: None identified.
Status:
No Fix.
DNV23.
IA32_PERF_GLOBAL_INUSE[62] May be Set
Problem:
IA32_PERF_GLOBAL_INUSE MSR (392H) bit 62 is reserved. However, due to this
erratum, it may sometimes be read as 1.
Implication:
A read of IA32_PERF_GLOBAL_INUSE MSR may see bit 62 set in the result.
Workaround: None identified.
Status:
No Fix.
Intel Atom® Processor C3000 Product Family
Specification Update
44
March 2018
Order Number: 336345-005US
Errata—Intel Atom® Processor C3000 Product Family
DNV24.
xHCI Split-Transactions Error Counter Reset Issue
Problem:
The xHCI controller may not reset its split transaction error counter if a high-speed USB
hub propagates a mal-formed bit from a low-speed or full-speed USB device exhibiting
non-USB specification compliant signal quality.
Implication:
Device dependent. Full Speed and Low Speed devices behind the hub may be reenumerated and may cause a device to not function as expected.
Workaround: None identified.
Status:
No Fix.
DNV25.
An Unsupported Request May Log in the Integrated Error Handler
(IEH) After PCI Enumeration
Problem:
During PCI enumeration, unclaimed Type1 configuration cycles are forwarded to the
Primary to Secondary bridge (P2SB) which is the subtractive agent. The Integrated
Error Handler (IEH) in the P2SB claims Type1 Configuration cycles targeting either
Device 4 or Device 5 and logs an Unsupported Request.
Implication:
When enabling the system error reporting, this error will always be seen by the IEH at
start up.
Workaround: Set the URE bit in the RCEC_ERRUNCMSK register to prevent generating an interrupt.
Clear the following IEH RCEC registers after PCI enumeration.
• RCEC_ERRUNCSTS.URE=1
• RCEC_DEVSTS.NFED=1
• RCEC_DEVSTS.URD=1
Status:
No Fix.
DNV26.
Data Breakpoints May Not be Detected on Split Reads
Problem:
A debug exception should be generated on a read which accesses an address specified
by a breakpoint address register and its LENn field configured to monitor data reads.
Due to this erratum, under complex microarchitectural conditions the processor may
not trigger a debug exception on a cacheline split memory read.
Implication:
A debugger may not be notified when a read occurs that should match a data
breakpoint if the read splits a cacheline.
Workaround: None identified.
Status:
No Fix.
March 2018
Order Number: 336345-005US
Intel Atom® Processor C3000 Product Family
Specification Update
45
Intel Atom® Processor C3000 Product Family—Errata
DNV27.
Intel® Trace Hub PTI Pattern Generator May Stop Working When
Width is Changed While Enabled
Problem:
Intel® TH (Trace Hub) PTI (Parallel Trace Interface) pattern generator feature is used to
test the connectivity between PTI port and trace capture hardware. Due to this
erratum, once enabled the pattern generator may hang if the width is decreased.
Implication:
Intel TH's pattern generator feature stops working when users decrease the width.
Workaround: Intel TH's PTI pattern generator width should be reconfigured only after an Intel® Trace
Hub soft reset. Intel® Trace Hub Soft reset can be done by setting NPKDSC.FLR bit to
'1'.
Status:
No Fix.
DNV28.
UART_IE_TXD Signal May Be Low When IE Enters The Off State (Cloff)
Problem:
If IE (Innovation Engine) owns the IE UART pins and has them configured in UART
mode when the IE enters the off state (Cloff) the UART_IE_TXD signal is driven low
when it should be driven high.
Implication:
Due to this erratum, the UART connected to the IE UART might interpret UART_IE_TXD
low as a continue stream of “0”s.
Workaround: The IE needs to program the UART_IE_TXD pin as a GPO (General Purpose Output)
driving “1” before entering Cloff. When existing Cloff IE needs to put UART_IE_TXD
back into UART mode. Please refer to the Innovation Engine Developers Guide,
Document #558866 for more information.
Status:
No Fix.
DNV29.
Intel® Trace Hub May Report Timeout Error Incorrectly
Problem:
Intel® Trace Hub can incorrectly report a timeout error in the NPKDSC
(Device 4,5,6; Function 0; Offset 80h) register when the ICTOT
(Inbound CCB Timeout Timer) and ISTOT (Inbound Switch Timeout Timer) are
programmed from 0 to any non-zero value.
Implication:
The user may observe a timeout error when none has occurred. Intel has not observed
this erratum in commercially available software.
Workaround: None identified.
Status:
No Fix.
DNV30.
Larger Than 32-bit Writes to Intel® Trace Hub CSR_MTB_BAR May
Cause a System Hang
Problem:
Intel® Trace Hub fails to fully receive or respond to writes larger than 32-bits to
CSR_MTB_BAR (BAR0) MMIO region. This may lead to a system hang.
Implication:
When this erratum occurs, the system may hang.
Workaround: None identified.
Status:
No Fix.
Intel Atom® Processor C3000 Product Family
Specification Update
46
March 2018
Order Number: 336345-005US
Errata—Intel Atom® Processor C3000 Product Family
DNV31.
Potential Partial Trace Data Loss in Intel® Trace Hub ODLA When
Storing to Memory
Problem:
When ODLA (On-Die Logic Analyzer) is configured to trace to memory, under complex
microarchitectural conditions, the trace may lose a timestamp.
Implication:
Some ODLA trace data may be lost. This erratum does not affect other trace data
sources. Typically lost trace data will be displayed as “OVERFLOW.” Subsequent
timestamps will allow the trace decoder to resume tracing. Intel has not observed this
erratum in commercially available software.
Workaround: None identified. For a particular workload, changing the memory buffer size or disabling
deep compression may eliminate the microarchitectural condition that caused the
erratum.
Status:
No Fix.
DNV32.
Intel® Trace Hub Pipeline Empty Bit For PTI May be Not Set
Problem:
If the PTI (Parallel Trace Interface) Port P2NULL bit in the GTHOPT0 register
(CSR_MTB_BAR; Offset 0; bit 19) is set during tracing, and subsequently cleared
(during tracing or after tracing is completed), the PLE (Pipeline Empty) bit (GTHSTAT
register; Offset 0xD4; bit 2) may not be set to 1 even when the pipeline is empty.
Implication:
Software may loop continuously waiting for Intel® Trace Hub PTI PLE bit to be set.
Workaround: If P2NULL must be set during tracing, then termination of tracing must involve these
additional steps: When pipeline empty is not set within a microsecond of terminating
tracing, sending a FLAG packet may enable PTI PLE bit to be set. If the PTI PLE bit is
not set after the FLAG packet is sent, software should repeat the sending a FLAG
packet and checking the PLE bit up to two more times.
Status:
No Fix.
DNV33.
Intel® Trace Hub TAP Data Registers Are Read-once
Problem:
Each Intel® Trace Hub TAP DR (Data Register) stores data shifted-in on the TDI pin into
the DR on a TAP read operation.
Implication:
Intel® Trace Hub TAP DRs can be read only once. Subsequent DR reads will deliver
unexpected data.
Workaround: None identified. Do not perform repeated reads.
Status:
No Fix.
March 2018
Order Number: 336345-005US
Intel Atom® Processor C3000 Product Family
Specification Update
47
Intel Atom® Processor C3000 Product Family—Errata
DNV34.
Performance Monitoring Event Branch Retired May Increment Twice
For Near RET Imm16
Problem:
A Near RET imm16 instruction may increment performance monitoring event
BR_INST_RETIRED.ALL_BRANCHES (Event C4H, UMask 00H) twice instead of once.
This erratum does not occur if the UMask bits 3 (BR_INST_RETIRED.REMOVE_RET)
and/or 7 (BR_INST_RETIRED.REMOVE_NOT_TAKEN_JCC) are set.
Implication:
A performance monitoring counter counting the branch retired event may overcount.
Software relying on the branch retired event incrementing deterministically may not
function correctly.
Workaround: None identified. Software could have one counter count all branches other than nottaken JCC (UMask 7FH) and another counter count not-taken JCC (UMask 80) and sum
them to produce the total count.
Status:
No Fix.
DNV35.
Incorrect Number of Enabled Cores Reported in
MSR_CORE_THREAD_COUNT
Problem:
For 16-core processors, the CORE_COUNT field (bits [31:15]) of
MSR_CORE_THREAD_COUNT(MSR 035H) will report a value of 0 instead of 16.
Implication:
Due to this erratum, software that uses MSR_CORE_THREAD_COUNT to discover the
number of cores may operate incorrectly.
Workaround: It is possible for BIOS to contain a workaround for this erratum.
Status:
No Fix.
DNV36.
NEWCENTURY_STS Cannot Be Cleared
Problem:
The NEWCENTURY_STS bit in TCO1_STS register (TCOBASE + 4h, bit7) cannot be
cleared by software writing a “1” back to the bit position. If the bit is written again the
system may hang.
Implication:
When this erratum occurs, the system may hang. The failure only can be seen when
the Year byte rolls over from 99 to 00.
Workaround: None Identified.
Status:
No Fix.
DNV37.
Intel® Processor Trace Timing Packets May Not be Generated When
Clock Modulation is Enabled
Problem:
Intel® Processor Trace timing packets TSC (Timestamp), TMA (TSC/MTC Align), and
CBR (Core:Bus Ratio) should be generated when the clocks resume when TM1 duty
cycling is active or Clock Modulation is enabled (IA32_CLOCK_MODULATION MSR
0x19A bits 4:0). Due to this erratum when clock modulation is enabled, these packets
may not be generated in certain microarchitectural conditions.
Implication:
Due to this erratum, the debugger may be unable to properly track wall-clock time in
portions of the trace.
Workaround: Disable clock modulation when Intel® Processor Trace is in use to partially work around
this erratum. Note that clock modulation due to TM1 cannot be mitigated. TM1 should
not be active in properly thermally managed systems.
Status:
No Fix.
Intel Atom® Processor C3000 Product Family
Specification Update
48
March 2018
Order Number: 336345-005US
Errata—Intel Atom® Processor C3000 Product Family
DNV38.
Processor Host Root Complex May Incorrectly Route Memory Accesses
to Intel® Trace Hub
Problem:
The Intel® Trace Hub RTIT_BAR (B0:D31:F7 offset 20h) is reported as a 2KB memory
range. Due to this erratum, the processor Host Root Complex will forward addresses
from RTIT_BAR to RTIT_BAR +4MB -1 to Intel® Trace Hub.
Implication:
Devices assigned within the RTIT_BAR to RTIT_BAR + 4MB -1 space may not function
correctly.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status:
No Fix.
March 2018
Order Number: 336345-005US
Intel Atom® Processor C3000 Product Family
Specification Update
49
Intel Atom® Processor C3000 Product Family—Specification Changes
Specification Changes
1.
Optional SMBALERT# Signal in SMB Controller - Legacy
The optional SMBALERT# signal (SMB_LEG_ALRT_N) is wake event when the system is
in S4 or S5 (soft off) power state.
§§
Intel Atom® Processor C3000 Product Family
Specification Update
50
March 2018
Order Number: 336345-005US
Specification Clarifications—Intel Atom® Processor C3000 Product Family
Specification Clarifications
There are no specification clarifications at this time.
§§
March 2018
Order Number: 336345-005US
Intel Atom® Processor C3000 Product Family
Specification Update
51
Intel Atom® Processor C3000 Product Family—Documentation Changes
Documentation Changes
There are no documentation changes at this time.
§§
Intel Atom® Processor C3000 Product Family
Specification Update
52
March 2018
Order Number: 336345-005US