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TDA8295
Digital global standard low IF demodulator for analog TV and
FM radio
Rev. 01 — 4 February 2008
Product data sheet
1. General description
The TDA8295 is an alignment-free digital multistandard vision and sound low IF signal
PLL demodulator for positive and negative video modulation including AM and FM mono
sound processing. It can be used in all countries worldwide for M/N, B/G/H, I, D/K,
L and L-accent standard. CVBS and SSIF/mono audio is provided via two DACs. FM radio
preprocessing is included for simple interfacing with demodulator/stereo decoder
backends.
The IC is especially suited for the application with the NXP Silicon Tuner TDA8275A or
TDA1827x.
All the processing is done in the digital domain.
The chip has an ‘easy programming’ mode to make the I2C-bus protocol very simple. In
principle, only one bit sets the proper standard with recommended content. However, if
this is not suitable, free programming is always possible.
2. Features
n Digital IF demodulation for all analog TV standards worldwide (M/N, B/G/H, D/K, I,
L and L-accent standard)
n Multistandard true synchronous demodulation with active carrier regeneration
n Alignment-free
n 16 MHz typical reference frequency input (from low IF tuner) or operating as crystal
oscillator
n Internal PLL synthesizer which allows the use of a low-cost crystal (typically 16 MHz)
n Especially suited for the NXP Silicon Tuner TDA8275A or TDA1827x
n No SAW filter needed
n Low application effort and external component count in combination with the
TDA8275A or TDA1827x
n Pin compatible with predecessor TDA8290
n Simple upgrade of TDA8290 possible
n 12-bit IF ADC on chip running with 54 MHz or 27 MHz
n Two 10-bit DACs on chip for CVBS and SSIF or audio
n Easy programming for I2C-bus
n High flexibility due to various I2C-bus programming registers
n I2C-bus interface and I2C-bus feed-through for tuner programming
n Four I2C-bus addresses selectable via two external pins
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
n Gated IF AGC acting on black level by using H/V PLL or peak IF AGC (I2C-bus
selectable)
n Internal digital logarithmic IF AGC amplifier with up to 48 dB gain and 68 dB control
range
n Peak search tuner IF AGC for optimal adaptive drive of the IF ADC
n Switchable IF PLL and IF AGC loop bandwidths
n Precise AFC and lock detector
n Accurate group delay equalization for all standards
n Very robust IF demodulator coping with adverse field conditions
n Wide PLL pull-in range up to ±1660 kHz (I2C-bus selectable)
n CVBS and SSIF or audio output with simple postfilter (capacitor only)
n CVBS gain levelling stage to provide nearly constant signal amplitude during
overmodulation
n Video equalizer with eight settings
n Nyquist filter in video baseband
n Excellent video S/N (typically 62 dB weighted)
n High selectivity video low-pass filter for all standards
n Low video into sound crosstalk
n Sound performance comparable to QSS single reference concepts
n AM/FM mono sound demodulator
n Switchable de-emphasis
n Excellent FM sound
n Good AM sound
n High FM Deviation mode for China
n Preprocessing of FM radio (mono and stereo) with highly selective digital band-pass
filter
n No ceramic filter or external components needed for FM radio
n FM radio available in mono
n Automatic or forced mute for mono sound
n Automatic or forced blank for video
n Mostly digital FIR filter implementation (NSC notches and video low-pass filters)
n Three GPIO pins
n Low total power dissipation (typically 324 mW)
n Standby mode (typically 7 mW)
n 40-pin HVQFN package
n CMOS technology (0.12 µm 1.2 V and 3.3 V)
3. Applications
n PC TV applications
n DVD recorders
TDA8295_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 4 February 2008
2 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
4. Quick reference data
Table 1.
Quick reference data
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Power supply
VDD(1V2)
supply voltage (1.2 V)
digital and analog
1.08
1.2
1.32
V
VDD(3V3)
supply voltage (3.3 V)
digital and analog
2.97
3.3
3.63
V
IDD(tot)(1V2)
total supply current (1.2 V)
IDD(tot)(3V3)
Ptot
-
28
33
mA
[1]
-
125
136
mA
default settings; 75 Ω drive;
fs = 54 MHz at ADC; including DAC
loads; RRSET = 1 kΩ
[1]
-
434
490
mW
Power-save mode; fs = 54 MHz at
ADC; including DAC loads;
RRSET = 2 kΩ; see Section 13.6
[2]
-
324
369
mW
-
7
10
mW
total supply current (3.3 V)
total power dissipation
Standby mode
IF input
Vi(p-p)
peak-to-peak input voltage for full-scale ADC input (0 dBFS)
1.8
2.0
2.2
V
Vi
input voltage
operational input related to ADC full
scale; all standards; sum of all signals
−3
−3
−3
dBFS
fi
input frequency
PC / SC1
M/N standard
-
5.75 / 1.25 -
MHz
B standard
-
6.75 / 1.25 -
MHz
G/H standard
-
7.75 / 2.25 -
MHz
I standard
-
7.75 / 1.75 -
MHz
DK and L standard
-
7.75 / 1.25 -
MHz
L-accent standard
-
1.25 / 7.75 -
MHz
FM radio
-
1.25
-
MHz
wide
60
60
60
kHz
±830
±830
±830
kHz
115
117
-
%
Carrier recovery FPLL
B−3dB(cl)
closed-loop −3 dB
bandwidth
∆fpullin
pull-in frequency range
mover(PC)
picture carrier
overmodulation index
[3]
black for L/L-accent standard; flat field
white else
IF demodulation (video equalizer in Flat mode)
αsup(stpb)
stop-band suppression
video low-pass filter (M/N, B/G/H, I,
D/K, L/L-accent standard)
-
−60
-
dB
tripple(GDE)
group delay equalizer
ripple time
peak value for B/G/H half, D/K half,
I flat, M (FCC) full, L/L-accent full
standard
-
20
40
ns
TDA8295_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 4 February 2008
3 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 1.
Quick reference data …continued
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
0.8
1.0
1.2
V
0.8
1.0
1.2
V
all standards except M/N
4.8
4.85
-
MHz
M/N standard
3.9
4.05
-
MHz
CVBS output
Vo(p-p)
peak-to-peak output
voltage
negative PC modulation (all standards
except L/L-accent); 75 Ω DC load;
sync-white modulation
90 % (nominal)
positive PC modulation (L/L-accent
standard); 75 Ω DC load; sync-white
modulation
97 % (nominal)
Bvideo(−3dB)
−3 dB video bandwidth
overall video response; CVBS
equalizer flat
αresp(f)
frequency response
video equalizer; 8 equally spaced
settings; value at 3.9 MHz
−5
-
+4.5
dB
Gdif
differential gain
“ITU-T J.63 line 330”
-
1.5
3
%
ϕdif
differential phase
“ITU-T J.63 line 330”
-
1.5
3
deg
(S/N)w
weighted signal-to-noise
ratio
all standards; unified weighting filter
(“ITU-T J.61”); PC at −6 dBFS
58
62
-
dB
all standards except B/G/H
30
35
40
mV
B/G/H standard
27
32
37
mV
FM radio (single carrier)
460
530
610
mV
M standard; 54 % modulation
degree (±13.5 kHz FM deviation
before pre-emphasis)
125
143
165
mV
B, G/H, I, D, K standard; 54 %
modulation degree (±27 kHz
FM deviation before pre-emphasis)
125
143
165
mV
M standard; related to ±25 kHz
peak deviation before pre-emphasis
7
7
7
dB
B, G/H, I, D, K standard; related to
±50 kHz peak deviation before
pre-emphasis
7
7
7
dB
FM; for 50 kHz deviation before
pre-emphasis (25 kHz for M standard)
-
0.1
0.2
%
AM; m = 80 %
-
0.6
1
%
SSIF/mono sound output
Vo(SSIF)(RMS) RMS SSIF output voltage
Vo(AF)(RMS)
αhr(AF)
THD
RMS AF output voltage
AF headroom
total harmonic distortion
1 kΩ DC or AC load; no modulation;
PC / SC1 = 13 dB; scaled linearly for
all other ratios
1 kΩ DC or AC load
before clipping; 1 kΩ DC or AC load
TDA8295_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 4 February 2008
4 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 1.
Quick reference data …continued
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
BAF(−3dB)
−3 dB AF bandwidth
AM
20
27
-
kHz
FM
40
50
-
kHz
54
58
-
dB
43
46
-
dB
AF weighted
signal-to-noise ratio
(S/N)w(AF)
via internal mono sound demodulator;
“ITU-R BS.468-4”; FM mode related to
27 kHz deviation before pre-emphasis;
10 % residual PC; SC1
color bar picture
via internal mono sound demodulator;
“ITU-R BS.468-4”; AM; m = 54 %; 3 %
residual PC; SC1
color bar picture
[1]
50 % ADC current; 100 % video DAC current; 50 % sound DAC current.
[2]
50 % ADC current; 50 % video DAC current; 25 % sound DAC current.
[3]
The pull-in range can be doubled to ±1660 kHz by I2C-bus register like described in Table 16. Then the AFC read-out has 256 steps.
5. Ordering information
Table 2.
Ordering information
Type number
TDA8295HN
Package
Name
Description
Version
HVQFN40
plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6 × 6 × 0.85 mm
SOT618-1
TDA8295_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 4 February 2008
5 of 77
TDA8295_1
Product data sheet
Rev. 01 — 4 February 2008
2
FILTERS
AND
AGC AMPLIFIER
BIT STREAM
DAC
PEAK DETECTOR
AND
INTEGRATOR
IF
ADC
Fig 1. Functional diagram of TDA8295
tuner
IF AGC
low IF
signal
crystal or
frequency
reference
CLOCK
PROCESSOR
AND PLL
PLL
DEMODULATOR
GATED AGC
DETECTOR
AND
INTEGRATOR
VIDEO
LOW-PASS
FILTER
SUPPLY, REFERENCE
AND
DECOUPLING
CORDIC AM/FM
SOUND DEMODULATOR
SSIF AND FM RADIO
BAND-PASS FILTERS
NYQUIST
SLOPE
H/V PLL
SWITCH
I2C-bus
I2C-BUS
UPSAMPLER
VIDEO/
GROUP DELAY
EQUALIZER
SOUND
DAC
UPSAMPLER
VIDEO
DAC
001aah354
analog SSIF
or
mono sound
analog
CVBS
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xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
NXP Semiconductors
TDA8295
Digital global standard low IF demodulator for analog TV and FM radio
6. Functional diagram
© NXP B.V. 2008. All rights reserved.
6 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
7. Pinning information
31 GPIO2/SDA_O
32 GPIO1/SCL_O
33 GPIO0/VSYNC
35 VSSDR
34 VDDDR(3V3)
36 i.c.
37 IF_AGC
terminal 1
index area
39 VDDD(ADC)(3V3)
38 i.c.
40 VSSA(ADC)
7.1 Pinning
IF_POS
1
30 TRST_N
IF_NEG
2
29 SDA
VDDA(ADC)(3V3)
3
28 SCL
VDDD1(1V2)
4
27 TCK
VSSD1
5
i.c.
6
VDDA(PLL)(1V2)
7
24 TMS
XIN
8
23 TDI
XOUT
9
22 TDO
26 VSSD2
TDA8295HN
25 VDDD2(1V2)
SADDR1 20
SADDR0 19
VDDA(DAC2)(3V3) 18
S_IOUTP 17
S_IOUTN 16
V_IOUTP 14
VDDA(DAC1)(3V3) 15
V_IOUTN 13
RSET 11
21 RST_N
VSSA(DAC) 12
VSSA(PLL) 10
008aaa095
Transparent top view
Fig 2. Pin configuration for HVQFN40
Table 3.
Pin allocation table
Pin
Symbol
Pin
Symbol
1
IF_POS
2
IF_NEG
3
VDDA(ADC)(3V3)
4
VDDD1(1V2)
5
VSSD1
6
i.c.
7
VDDA(PLL)(1V2)
8
XIN
9
XOUT
10
VSSA(PLL)
11
RSET
12
VSSA(DAC)
13
V_IOUTN
14
V_IOUTP
15
VDDA(DAC1)(3V3)
16
S_IOUTN
17
S_IOUTP
18
VDDA(DAC2)(3V3)
19
SADDR0
20
SADDR1
21
RST_N
22
TDO
23
TDI
24
TMS
25
VDDD2(1V2)
26
VSSD2
27
TCK
28
SCL
29
SDA
30
TRST_N
TDA8295_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 4 February 2008
7 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 3.
Pin allocation table …continued
Pin
Symbol
Pin
Symbol
31
GPIO2/SDA_O
32
GPIO1/SCL_O
33
GPIO0/VSYNC
34
VDDDR(3V3)
35
VSSDR
36
i.c.
37
IF_AGC
38
i.c.
39
VDDD(ADC)(3V3)
40
VSSA(ADC)
7.2 Pin description
Table 4.
Pin description
Pin
Type[1][2]
Description
21
I
The RST_N input is asynchronous and active LOW, and clears the TDA8295.
When RST_N goes LOW, the circuit immediately enters its Reset mode and
normal operation will resume four XIN signal falling edges later after RST_N
returns HIGH. Internal register contents are all initialized to their default values.
The minimum width of RST_N at LOW level is four XIN clock periods.
XIN
8
I
Crystal oscillator input pin. In Slave mode (typically), the XIN input simply
receives a 16 MHz clock signal from an external device (typically from the
TDA8275A or TDA1827x). In Oscillator mode, a fundamental 16 MHz (typically)
crystal is connected between pin XIN and pin XOUT.
XOUT
9
O
Crystal oscillator output pin. In Slave mode, the XOUT output is not connected.
In Oscillator mode a fundamental 16 MHz (typically) crystal is connected
between pin XIN and pin XOUT.
SDA
29
I/O, OD
I2C-bus bidirectional serial data. SDA is an open-drain output and therefore
requires an external pull-up resistor (typically 4.7 kΩ).
SCL
28
I
I2C-bus clock input. SCL is nominally a square wave with a maximum frequency
of 400 kHz. It is generated by the system I2C-bus master.
SADDR0
19
I
SADDR1
20
I
These two bits allow to select four possible I2C-bus addresses, and therefore
permits to use several TDA8295 in the same application and/or to avoid conflict
with other ICs. The complete I2C-bus address is: 1, 0, 0, SADDR1, 0, 1,
SADDR0 (see also Section 9.1).
Symbol
Reset
RST_N
Reference
I2C-bus
I2C-bus feed-through switch or GPIO
GPIO2/SDA_O
31
I/O, OD
SDA_O is equivalent to SDA but can be 3-stated by I2C-bus programming. It is
the output of a switch controlled by I2CSW_EN parameter. SDA_O is an
open-drain output and therefore requires an external pull-up resistor
(see Section 9.3.20).
GPIO1/SCL_O
32
I/O, OD
SCL_O is equivalent to SCL input but can be 3-stated by I2C-bus programming.
SCL_O is an open-drain output and therefore requires an external pull-up
resistor (see Section 9.3.20). For proper functioning of the I2C-bus feed-through,
a capacitor C = 33 pF to GND must be added (see Section 13.6).
33
I/O, OD
vertical synchronization pulse needed for the NXP Silicon Tuner
(see Section 9.3.20)
37
I/O, OD, T tuner IF AGC output
V-sync or GPIO
GPIO0/VSYNC
Tuner IF AGC
IF_AGC
TDA8295_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 4 February 2008
8 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 4.
Pin description …continued
Symbol
Pin
Type[1][2]
Description
TMS
24
I
Test mode select provides the logic levels needed to change the TAP controller
from state to state during the boundary scan test.
TRST_N
30
I
Test reset is used to reset the TAP controller (active LOW). Grounding is
mandatory in Functional mode.
TCK
27
I
Test clock is used to drive the TAP controller.
TDI
23
I
Test data input is the serial data input for the test data instruction.
TDO
22
O
Test data output is the serial test data output pin. The data is provided on the
falling edge of TCK.
IF_POS
1
AI
IF positive analog input for internal ADC
IF_NEG
2
AI
IF negative analog input for internal ADC
V_IOUTP
14
AO
positive analog current output of the video output
V_IOUTN
13
AO
negative analog current output of the video output
S_IOUTP
17
AO
positive analog current output of the SSIF/mono sound output
S_IOUTN
16
AO
negative analog current output of the SSIF/mono sound output
RSET
11
I
External bias setting of the DACs. An external resistor (1 kΩ typical) has to be
connected between RSET and the analog ground of the board. This resistor
generates the current into the DACs and also defines the full scale output
current. The total parasitic capacitance seen externally from the RSET pin has to
be lower than 20 pF.
Boundary scan
ADC
DAC
Supplies and grounds
VDDA(DAC1)(3V3)
15
PS
DAC1 (video DAC) and DAC reference module analog supply voltage (3.3 V
typical)
VDDA(DAC2)(3V3)
18
PS
DAC2 (sound DAC) analog supply voltage (3.3 V typical)
VSSA(DAC)
12
GND
DAC reference module analog ground supply voltage (0 V typical)
VDDA(ADC)(3V3)
3
PS
IF ADC analog supply voltage (3.3 V typical)
VDDD(ADC)(3V3)
39
PS
IF ADC digital supply voltage (3.3 V typical)
VSSA(ADC)
40
GND
ADC analog ground supply voltage (0 V typical)
VDDD1(1V2)
4
PS
ADC, PLL and DACs digital supply voltage (1.2 V typical)
VSSD1
5
GND
ADC, PLL and DACs digital ground supply voltage (0 V typical)
VDDA(PLL)(1V2)
7
PS
crystal oscillator and clock PLL analog supply voltage (1.2 V typical)
VSSA(PLL)
10
GND
crystal oscillator and clock PLL analog ground supply voltage (0 V typical)
VDDD2(1V2)
25
PS
core digital supply voltage (1.2 V typical)
VSSD2
26
GND
core digital ground supply voltage (0 V typical)
VDDDR(3V3)
34
PS
ring digital supply voltage (3.3 V typical)
VSSDR
35
GND
ring digital ground supply voltage (0 V typical)
i.c.
36
I
internally connected; connect to ground
i.c.
38
I
internally connected; connect to ground
i.c.
6
I
internally connected; connect to ground
Other pins
[1]
All digital inputs are 5 V tolerant (except pin XIN).
TDA8295_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 4 February 2008
9 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
[2]
The pin types are defined in Table 5.
Table 5.
Pin type description
Type
Description
AI
analog input
AO
analog output
GND
ground
I
digital input
I/O
digital input and output
O
digital output
OD
open-drain output
PS
power supply
T
3-state
8. Functional description
8.1 IF ADC
The low IF spectrum (1 MHz to 10 MHz) from the Silicon Tuner TDA8725A or TDA1827x
is fed symmetrically to the 12-bit IF ADC of the TDA8295, where it is sampled with
54 MHz or 27 MHz. All the anti-aliasing filtering is already done in the Silicon Tuner.
8.2 Filters
The internal filters permit to reduce the sampling rate to 13.5 MHz, and to form a complex
signal to ease the effort of further signal processing. Before this, the DC offset (coming
from the ADC) is removed.
In addition, standard dependent notch filters for the adjacent sound carriers protect the
picture carrier PLL from malfunctioning and avoid disturbances (i.e. moire) becoming
visible in the video output.
8.3 PLL demodulator
The second-order PLL is the core block of the whole IC. It is very robust against adverse
field conditions, like excessive overmodulation, no residual carrier presence or unwanted
phase or frequency modulation of the picture carrier. The PLL output is the synchronously
demodulated channel.
The AFC data is available via the I2C-bus.
8.4 Nyquist filter, video low-pass filter, video and group delay equalizer,
video leveling
The afore-mentioned down-mixed complex signal at the mixer CORDIC output, already
consisting of the demodulated content of the picture carrier together with the sound
carriers (the so-called intercarriers), is running through a Nyquist filter to get a flat video
response and is made real.
Afterwards, a video low-pass filter suppresses the sound carriers and other disturbers.
TDA8295_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 4 February 2008
10 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Next comes the equalizer circuit to remove the transmitter group delay predistortion.
A video leveling stage follows, which brings the output within the SCART specification
( 3dB overall), despite heavy overmodulation. The response time is made very slow.
Finally, a video equalizer allows to compensate the perhaps non-flat frequency response
from the tuner or to change the overall video response according to customer wish (i.e.
peaking or early roll-off).
8.5 Upsampler and video DAC
The filtered and compensated CVBS signal is connected to the oversampled 10-bit video
DAC (fs = 108 MHz) via an interpolation stage. The strong oversampling replaces a former
complicated LCR postfiltering by a simple first-order RC low-pass filter to remove the DAC
image frequencies sufficiently. This holds also for the sound DAC, described in
Section 8.6.
8.6 SSIF/mono sound processing
The complex signal is routed via a band-pass and interpolation filter to the 10-bit sound
DAC for the recovery of the second sound carriers (SSIF). A very sharp band-pass filter at
5.5 MHz is added in the FM Radio mode to remove neighbor channels. This also eases
the dynamic burden on the following ADC in the demodulator/decoder chip. The
afore-mentioned high-selectivity band-pass, which replaces the former ceramic filter, is
located behind a frequency shifter. In there, the incoming wanted FM radio channel from
the Silicon Tuner is changed from 1.25 MHz to 5.5 MHz.
Moreover, the complex signal is demodulated in a linear CORDIC detector and low-pass
filtered to attenuate the video spectrum and the second sound carrier, respectively other
disturbers above the intercarrier. The output of the linear CORDIC (phase information) is
differentiated for getting the demodulated FM audio. The AM demodulation is executed in
a synchronous fashion by using a narrow-band PLL demodulator.
A de-emphasis filter is implemented for FM standards, before the audio is interpolated to
108 MHz as in the CVBS case.
The mono audio is made available in the sound DAC via an I2C-bus controlled selector in
case the intercarrier path is not used for driving an external stereo demodulator.
However, if the mono audio output has to meet the SCART specification, an external
cheap operational amplifier with 12 dB gain becomes necessary, because the low supply
voltage for the TDA8295 doesn’t allow such high levels like 2 V (RMS) maximum.
8.7 Tuner IF AGC
This AGC controls the tuner IF AGC amplifier in the TDA8275A or TDA1827x in such a
way, that the IF ADC is always running with a permanent headroom of 3 dB for the sum of
all signals present at the ADC input. This ensures an always optimal exploitation of the
dynamic range in the IF ADC.
The detection is done in peak Search mode during a field period. The attack time is made
much faster than the decay time in order to avoid transient clipping effects in the IF ADC.
This can happen during channel change or airplane flutter conditions.
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
The above wideband, slowly acting AGC loop (uncorrelated) is of first-order integral
action. It is closed via the continuous tuner IF AGC amplifier in the Silicon Tuner via a
bit stream DAC (PWM signal at 13.5 MHz, 27 MHz or 54 MHz) and an external and
uncritical first-order RC low-pass.
8.8 Digital IF AGC
Common to both IF AGC concepts is the peak search algorithm as long as the H/V PLL is
not locked. This is of advantage for the acquisition by avoiding hang-ups due to excessive
overloading, so being able to leave the saturated condition by reducing the gain.
Two Detection modes are made available in the IC via I2C-bus.
• Black level gated AGC:
The first mode uses an IF AGC detector which is gated with a very robust and
well-proven H/V sync PLL block on board. Gating occurs on the black level (most of
the time on the back porch) of the video signal and the control is delivered after an
error integration and exponential weighting to the internal IF AGC amplifier. This
IF AGC amplifier, in fact a multiplier, has a control range of −20 dB to +48 dB.
• Peak AGC:
A fast attack and slow decay action cares for a good and nearly clip-free transient
behavior. This proved to be more robust for non-standard signals, like sync clipping
along the transmitter/receiver chain.
With respect to the IF AGC speed generally, only the gated black level or peak sync
IF AGC can be made fast. However the peak search one, used for positive modulation
standards (L and L-accent standard), is rather slow because the VITS is present only
once in a field.
The correlated or narrow-band AGC loop, closed via the continuous IF AGC amplifier
in the TDA8295, is of first-order integral action and settles at a constant IF input level
with a permanent headroom of 12 dB (picture carrier). This headroom is needed for
the own sound carriers and the leaking neighbor (N − 1) spectrum.
8.9 Clock generation
Finally, either an external reference frequency (i.e. from the Silicon Tuner) or an own
on-chip crystal oscillator in the TDA8295 feeds the internal PLL synthesizer to generate
the necessary clock signals.
9. I2C-bus control
9.1 Protocol of the I2C-bus serial interface
The TDA8295 internal registers are accessible by means of the I2C-bus serial interface.
The SDA bidirectional pin is used as the data input/output pin and SCL as the clock input
pin. The highest SCL speed is 400 kHz.
TDA8295_1
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Rev. 01 — 4 February 2008
12 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
9.1.1 Write mode
S
BYTE 1
A
BYTE 2
A
BYTE 3
A
start
address 0
ack
start index
ack
data 1
ack
BYTE n
A
data n
ack
....
P
stop
001aad381
Fig 3. I2C-bus Write mode
Table 6.
Address format
7
6
5
4
3
2
1
0
1
0
0
SADDR1
0
1
SADDR0
R/W
Table 7.
I2C-bus transfer description
Field
Bit
Description
S
-
START condition
Byte 1
7 to 5
device address
4
SADDR1
3 and 2
device address
1
SADDR0
0
R/W = 0 for write action
A
-
acknowledge
Byte 2
7 to 0
start index
A
-
acknowledge
Byte 3
7 to 0
data 1
A
-
acknowledge
Byte n
7 to 0
data n
A
-
acknowledge
P
-
STOP condition
:
S
BYTE 1
A
BYTE 2
A
BYTE 3
A
P
start
1000 0100
ack
0000 0001
ack
0000 0010
ack
stop
001aah355
a. Address 84h, write 02h in register 01h
S
BYTE 1
A
BYTE 2
A
BYTE 3
A
BYTE 4
A
P
start
1000 0100
ack
0000 0010
ack
0000 0101
ack
0000 0100
ack
stop
001aah356
b. Address 84h, write 05h in register 02h and 04h in register 03h
Fig 4. Examples I2C-bus Write mode
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Rev. 01 — 4 February 2008
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
9.1.2 Read mode
S
BYTE 1
A
BYTE 2
A
S
BYTE 3
A
BYTE 4
A
start
address 0
ack
start index
ack
start
address 1
ack
value 1
ack
....
BYTE n
A
value n
ack
P
stop
001aad423
Fig 5. I2C-bus Read mode
Table 8.
I2C-bus transfer description
Field
Bit
Description
S
-
START condition
Byte 1
7 to 5
device address
4
SADDR1
3 and 2
device address
1
SADDR0
0
R/W = 0 for write action
A
-
acknowledge
Byte 2
7 to 0
start index
A
-
acknowledge
S
-
START condition (without stop before)
Byte 3
7 to 5
device address
4
SADDR1
3 and 2
device address
1
SADDR0
0
R/W = 1 for read action
A
-
acknowledge
Byte 4
7 to 0
value 1
A
-
acknowledge
Byte n
7 to 0
value n
A
-
acknowledge
P
-
STOP condition
:
S
BYTE 1
A
BYTE 2
A
S
BYTE 3
A
BYTE 4
A
BYTE 5
A
P
start
1000 0100
ack
0000 0010
ack
start
1000 0101
ack
0000 0101
ack
0000 0100
ack
stop
001aah357
Address 84h, read register 02h with value 05h and read register 03h with value 04h
Fig 6. Example I2C-bus Read mode
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
9.2 Register overview
The TDA8295 internal registers are accessible by means of the I2C-bus serial interface as
described in Section 9.1. In Table 9 and Table 10 an overview of all the registers is given,
the register description can be found in Section 9.3.
TDA8295_1
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TDA8295_1
Product data sheet
Rev. 01 — 4 February 2008
PC_PLL_FUNC
PC_PLL_THRES
PC_PLL_WGT
PC_FLL_FUNC
CARDET_LEVEL
DTO_PC_LOW
DTO_PC_MID
DTO_PC_HIGH
DTO_SC_LOW
DTO_SC_MID
DTO_SC_HIGH
FILTERS_1
FILTERS_2
GRP_DELAY
D_IF_AGC_SET_1
D_IF_AGC_SET_2
D_IF_AGC_FORCE
T_IF_AGC_SET
T_IF_AGC_LIM
T_IF_AGC_FORCE
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
V_SYNC_DEL
CVBS_SET
1Ch
1Dh
reserved
ADC_HEADR
03h
19h
to
1Bh
DIV_FUNC
02h
T_IF_AGC_FS
EASY_PROG
01h
18h
STANDARD[7:0]
STANDARD
00h
-
AGC_TRI
-
6
-
D_IF_AGC_
MODE
-
-
-
LIM_ON
-
VS_WIDTH[1:0]
reserved
-
T_FORCE
UP_LIM[3:0]
POL_TIF
D_FORCE
-
-
VS_POL
-
T_FORCE_VAL[6:0]
T_IF_AGC_SPEED[6:0]
D_FORCE_VAL[6:0]
-
GRP_DEL[4:0]
-
VS_DEL[4:0]
-
PLL_ON
-
-
LOW_LIM[3:0]
SBP[3:0]
PULL_IN
VID_MOD
-
1
FOR_BLK
AUTO_BLK
T_IF_AGC_FS[2:0]
PH_ERR_THRES[3:0]
NOTCH_FILT[4:0]
DC_NOTCH
POL_DET
-
2
ADC_HEADR[3:0]
0
-
3
CAR_DET_LVL[4:0]
-
-
-
-
4
D_IF_AGC_AVG[4:0]
-
-
-
FLL_LIM[5:0]
PHASE_GAIN[6:0]
-
-
-
-
5
D_AGC_ERR_ D_IF_AGC_BW[6:0]
LIM
D_IF_AGC_
CORR
-
-
VID_FILT[2:0]
DTO_SC[23:16]
DTO_SC[15:8]
DTO_SC[7:0]
DTO_PC[23:16]
DTO_PC[15:8]
DTO_PC[7:0]
-
FLL_ON
PHASE_PER
-
PC_PLL_BW[4:0]
-
AGC_SEL
-
7 (MSB)
I2C-bus registers
Index Name
Table 9.
VID_LVL
RST_INT
CAR_DET
IF_SWAP
ACTIVE
0 (LSB)
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Digital global standard low IF demodulator for analog TV and FM radio
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CVBS_LVL[7:0]
CVBS_LEVEL
CVBS_EQ
SOUNDSET_1
SOUNDSET_2
SOUND_LEVEL
SSIF_LEVEL
ADC_SAT
AFC
HVPLL_STAT
D_IF_AGC_STAT
T_IF_AGC_STAT
reserved
ANALOG_DEBUG
not used
IDENTITY
CLB_STDBY
reserved
ANALOG_STAT
ADC_CTL
ADC_CTL_2
VIDEODAC_CTL
AUDIODAC_CTL
DAC_REF_CLK_CTL -
PLL_REG00
not used
PLL_REG04
not used
PLL_REG06
1Eh
1Fh
20h
21h
Product data sheet
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
to
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
to
3Bh
3Ch
3Dh
3Eh
-
-
-
-
TDA8295_1
Rev. 01 — 4 February 2008
0
-
-
-
0
0
0
-
GAINSET
-
-
-
IDENTITY[7:0]
-
-
CLK_EN
-
-
-
0
DA_CLK_INV
B_DA_S[5:0]
B_DA_V[5:0]
-
CS[2:0]
LOAD_DACV
-
-
-
-
T_IF_AGC_STAT[7:0]
reserved
5
BYP_PLL
-
-
-
PLL_AUTO
DA_PLL_BYP
-
LOAD_DACS
-
-
-
-
NOISE_DET
-
-
-
AM_FM_SND[1:0]
6
D_IF_AGC_STAT[7:0]
-
AFC[7:0]
ADC_SAT[7:0]
-
-
-
-
CVBS_EQ[7:0]
7 (MSB)
I2C-bus registers …continued
Index Name
Table 9.
DIRECTO
-
-
-
0
B_REF[3:0]
-
PLL_LOCK
-
-
-
-
MAC_DET
SSIF_LVL[4:0]
SND_LVL[4:0]
HD_DK
DEEMPH[4:0]
4
DIRECTI
-
-
-
0
-
DCIN
reserved
reserved
-
-
-
FIDT
FOR_MUTE
3
0
-
0
-
0
-
TWOS
-
-
-
V_LOCK
AUTO_MUTE
2
PD_ADC
CLB
-
DAC_TEST
N_H_LOCK
0 (LSB)
0
-
0
-
0
PD_PLL
-
0
-
0
PD_DA_REF
PD_DA_S
PD_DA_V
AD_PLL_BYP AD_SR54M
SLEEP
STDBY
-
ADC_TEST
F_H_LOCK
SSIF_SND[1:0]
1
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Digital global standard low IF demodulator for analog TV and FM radio
© NXP B.V. 2008. All rights reserved.
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-
PLL_REG07
PLL_REG08
PLL_REG09
PLL_REG10
XTALOSC_CTL
GPIOREG_0
GPIOREG_1
GPIOREG_2
3Fh
40h
41h
42h
Product data sheet
43h
44h
45h
46h
I2CSW_ON
-
0
0
6
-
-
0
0
5
-
-
PSEL[4:0]
0
4
CLK_INV_GP2 CLK_INV_GP1 CLK_INV_GP0 -
I2CSW_EN
GP1_CF[3:0]
-
0
NSEL[6:0]
MSEL[7:0]
7 (MSB)
I2C-bus registers …continued
Index Name
Table 9.
-
GP2_CF[3:0]
GP0_CF[3:0]
-
0
3
GP2_VAL
HF
0
2
GP1_VAL
0
0
1
GP0_VAL
0
0
0
0 (LSB)
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TDA8295
Digital global standard low IF demodulator for analog TV and FM radio
TDA8295_1
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 10.
I2C-bus register reference
Index
Name
I2C-bus access
Default value
Reference
00h
STANDARD
R/W
01h
Table 11
01h
EASY_PROG
R/W
00h
Table 12
02h
DIV_FUNC
R/W
04h
Table 14
03h
ADC_HEADR
R/W
01h
Table 15
04h
PC_PLL_FUNC
R/W
27h
Table 16
05h
PC_PLL_THRES
R/W
04h
Table 17
06h
PC_PLL_WGT
R/W
10h
Table 18
07h
PC_FLL_FUNC
R/W
84h
Table 19
08h
CARDET_LEVEL
R/W
08h
Table 20
09h
DTO_PC_LOW
R/W
85h
Table 21
0Ah
DTO_PC_MID
R/W
F6h
Table 21
0Bh
DTO_PC_HIGH
R/W
92h
Table 21
0Ch
DTO_SC_LOW
R/W
55h
Table 22
0Dh
DTO_SC_MID
R/W
55h
Table 22
0Eh
DTO_SC_HIGH
R/W
55h
Table 22
0Fh
FILTERS_1
R/W
21h
Table 23
10h
FILTERS_2
R/W
11h
Table 24
11h
GRP_DELAY
R/W
01h
Table 25
12h
D_IF_AGC_SET_1
R/W
A0h
Table 26
13h
D_IF_AGC_SET_2
R/W
90h
Table 27
14h
D_IF_AGC_FORCE
R/W
67h
Table 28
15h
T_IF_AGC_SET
R/W
88h
Table 29
16h
T_IF_AGC_LIM
R/W
F0h
Table 30
17h
T_IF_AGC_FORCE
R/W
3Fh
Table 31
18h
T_IF_AGC_FS
R/W
02h
Table 32
19h
reserved
R/W
88h
-
1Ah
reserved
R/W
80h
-
1Bh
reserved
R/W
00h
-
1Ch
V_SYNC_DEL
R/W
6Fh
Table 33
1Dh
CVBS_SET
R/W
01h
Table 34
1Eh
CVBS_LEVEL
R/W
73h
Table 35
1Fh
CVBS_EQ
R/W
08h
Table 36
20h
SOUNDSET_1
R/W
21h
Table 37
21h
SOUNDSET_2
R/W
02h
Table 38
22h
SOUND_LEVEL
R/W
08h
Table 39
23h
SSIF_LEVEL
R/W
04h
Table 40
24h
ADC_SAT
R
-
Table 41
25h
AFC
R
-
Table 42
26h
HVPLL_STAT
R
-
Table 44
27h
D_IF_AGC_STAT
R
-
Table 45
28h
T_IF_AGC_STAT
R
-
Table 46
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 10.
I2C-bus register reference …continued
Index
Name
I2C-bus access
Default value
Reference
29h
reserved
R
-
-
2Ah
ANALOG_DEBUG
R/W
00h
Table 47
2Bh to 2Eh
not used
-
-
-
2Fh
IDENTITY
R
-
Table 48
30h
CLB_STDBY
R/W
01h
Table 49
31h
reserved
R/W
00h
-
32h
ANALOG_STAT
R
-
Table 50
33h
ADC_CTL
R/W
24h
Table 51
34h
ADC_CTL_2
R/W
01h
Table 52
35h
VIDEODAC_CTL
R/W
7Eh
Table 53
36h
AUDIODAC_CTL
R/W
00h
Table 54
37h
DAC_REF_CLK_CTL
R/W
00h
Table 55
38h
PLL_REG00
R/W
20h
Table 56
39h to 3Bh
not used
-
-
-
3Ch
PLL_REG04
R/W
00h
Table 57
3Dh
not used
R/W
-
-
3Eh
PLL_REG06
R/W
61h
Table 58
3Fh
PLL_REG07
R/W
00h
Table 60
40h
PLL_REG08
R/W
1Ah
Table 60
41h
PLL_REG09
R/W
02h
Table 60
42h
PLL_REG10
R/W
01h
Table 60
43h
XTALOSC_CTL
R/W
00h
Table 61
44h
GPIOREG_0
R/W
11h
Table 62
45h
GPIOREG_1
R/W
01h
Table 63
46h
GPIOREG_2
R/W
07h
Table 65
9.3 Register description
If registers (or bit groups contained in registers) are programmed with invalid values, i.e.
values different from those described in the tables below, the default behavior is chosen
for the related block.
9.3.1 Standard setting with easy programming
With the implemented ‘easy programming’, only one bit sets the TV or FM radio standard
with recommended register content. If not suitable however, any of these registers can be
written with other settings. With the rising edge of the bit ACTIVE, the registers 02h to 23h
are programmed internally with the standard dependent settings according to Table 13.
The content of registers with address 24h and higher is untouched.
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 11. STANDARD register (address 00h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
7 to 0 STANDARD[7:0] R/W
Description
TV or FM radio standard selection (easy
programming)
0000 0001*
M/N standard
0000 0010
B standard
0000 0100
G/H standard
0000 1000
I standard
0001 0000
D/K standard
0010 0000
L standard
0100 0000
L-accent standard
1000 0000
FM radio
Table 12. EASY_PROG register (address 01h) bit description
Legend: * = default value.
Bit
Access Value
Description
7 to 1 -
Symbol
R/W
not used
0
R/W
ACTIVE
-
With the rising edge of this bit, the registers
02h to 23h are programmed with the standard
dependent settings (see Table 13).
0*
no action
1
no action
0 to 1
activate easy programming
Example: To set the device to B standard e.g., please do the following steps.
1. Write 02h to register STANDARD, address 00h (set B standard)
2. Write 00h to register EASY_PROG, address 01h (make sure that ACTIVE = 0)
3. Write 01h to register EASY_PROG, address 01h (due to 0 to 1 transition of ACTIVE
the device is set to B standard, i.e. registers 02h to 23h are programmed
automatically according to Table 13)
4. Write 01h to register EASY_PROG, address 01h (reset ACTIVE to logic 0)
TDA8295_1
Product data sheet
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 13.
Easy programming values
Register
Standard
Index Name
M/N[1]
B
G/H
I
D/K
L
L-accent
FM radio
02h
DIV_FUNC
04h
04h
04h
04h
04h
06h
07h
00h
03h
ADC_HEADR
01h
01h
01h
01h
01h
01h
01h
01h
04h
PC_PLL_FUNC
27h
27h
27h
27h
27h
27h
27h
22h
05h
PC_PLL_THRES
04h
04h
04h
04h
04h
04h
04h
04h
06h
PC_PLL_WGT
10h
10h
10h
10h
10h
10h
10h
10h
07h
PC_FLL_FUNC
84h
84h
84h
84h
84h
84h
84h
04h
08h
CARDET_LEVEL
08h
08h
08h
08h
08h
08h
08h
08h
09h
DTO_PC_LOW
85h
00h
7Bh
7Bh
7Bh
7Bh
26h
00h
0Ah
DTO_PC_MID
F6h
00h
09h
09h
09h
09h
B4h
00h
0Bh
DTO_PC_HIGH
92h
80h
6Dh
6Dh
6Dh
6Dh
17h
80h
0Ch
DTO_SC_LOW
55h
DAh
DAh
1Dh
5Fh
5Fh
5Fh
DAh
0Dh
DTO_SC_MID
55h
4Bh
4Bh
C7h
42h
42h
42h
4Bh
0Eh
DTO_SC_HIGH
55h
68h
68h
71h
7Bh
7Bh
7Bh
68h
0Fh
FILTERS_1
21h
42h
44h
44h
44h
44h
44h
90h
10h
FILTERS_2
11h
12h
12h
12h
12h
12h
12h
14h
11h
GRP_DELAY
01h
02h
02h
10h
04h
08h
08h
10h
12h
D_IF_AGC_SET_1
A0h
A0h
A0h
A0h
A0h
A0h
A0h
A0h
13h
D_IF_AGC_SET_2
90h
90h
90h
90h
90h
90h
90h
08h
14h
D_IF_AGC_FORCE 67h
67h
67h
67h
67h
67h
67h
E7h
15h
T_IF_AGC_SET
88h
88h
88h
88h
88h
88h
88h
88h
16h
T_IF_AGC_LIM
F0h
F0h
F0h
F0h
F0h
F0h
F0h
F0h
17h
T_IF_AGC_FORCE 3Fh
3Fh
3Fh
3Fh
3Fh
3Fh
3Fh
3Fh
18h
T_IF_AGC_FS
02h
02h
02h
02h
02h
02h
02h
02h
19h
reserved
88h
88h
88h
88h
88h
88h
88h
88h
1Ah
reserved
80h
80h
80h
80h
80h
80h
80h
80h
1Bh
reserved
00h
00h
00h
00h
00h
00h
00h
00h
1Ch
V_SYNC_DEL
6Fh
6Fh
6Fh
6Fh
6Fh
6Fh
6Fh
6Fh
1Dh
CVBS_SET
01h
01h
01h
01h
01h
01h
01h
04h
1Eh
CVBS_LEVEL
73h
73h
73h
73h
73h
6Ch
6Ch
73h
1Fh
CVBS_EQ
08h
08h
08h
08h
08h
08h
08h
10h
20h
SOUNDSET_1
21h
22h
22h
22h
22h
44h
44h
22h
21h
SOUNDSET_2
02h
02h
02h
02h
02h
02h
02h
02h
22h
SOUND_LEVEL
08h
04h
04h
04h
04h
04h
04h
02h
23h
SSIF_LEVEL
04h
04h
04h
04h
04h
04h
04h
04h
[1]
M/N standard settings are equal to the power-on reset (default) values.
TDA8295_1
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
9.3.2 Diverse functions (includes tuner IF AGC Pin mode)
Table 14. DIV_FUNC register (address 02h) bit description
Legend: * = default value.
Bit
Symbol
Access Value Description
7
AGC_SEL R/W
It determines the tuner IF AGC output Pin mode. The
open-drain output can be used in special applications in
need of a higher control voltage.
0*
Normal mode
1
6
AGC_TRI
Open-drain mode
R/W
When AGC_TRI is set to logic 1 the tuner IF AGC output
pin is in 3-state mode. This mode is useful for paralleling a
channel decoder for instance.
0*
Normal mode
1
3-state mode
5 and 4 -
R/W
-
not used
3
-
R/W
0
reserved, must be set to logic 0
2
POL_DET R/W
The polarity detector ensures the proper polarity of the
video signal. So, the sync impulses of the video output are
near ground level.
0
polarity detector off
1*
1
polarity detector on
VID_MOD R/W
Selects video modulation. The only standards with positive
video modulation are L and L-accent.
0*
negative video modulation
1
0
positive video modulation
IF_SWAP R/W
When HIGH, the demodulator expects a swapped IF
spectrum. This is the case in L-accent standard. This option
is also built in for flexibility reasons.
0*
normal IF spectrum expected
1
swapped IF spectrum expected
9.3.3 ADC headroom
Table 15. ADC_HEADR register (address 03h) bit description
Legend: * = default value.
Bit
Symbol
7 to 4 -
Access Value Description
R/W
-
3 to 0 ADC_HEADR[3:0] R/W
not used
ADC_HEADR adjusts the needed headroom for the
wanted channel’s own sound carriers and the N − 1
adjacent sound carriers (PC in L-accent standard).
The ADC headroom is related to the sum of all
signals. This function is built in for debugging
purposes.
0001*
ADC headroom 3 dB
0010
ADC headroom 6 dB
0100
ADC headroom 9 dB
1000
ADC headroom 12 dB
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
9.3.4 Picture carrier PLL functions
Table 16. PC_PLL_FUNC register (address 04h) bit description
Legend: * = default value.
Bit
Symbol
7 to 3 PC_PLL_BW[4:0]
2
1
0
PLL_ON
PULL_IN
CAR_DET
Access Value
Description
R/W
picture carrier PLL loop bandwidth selection
0 0001
loop bandwidth 15 kHz
0 0010
loop bandwidth 30 kHz
0 0100*
loop bandwidth 60 kHz
0 1000
loop bandwidth 130 kHz
1 0000
loop bandwidth 280 kHz (for very bad transmitter
quality)
R/W
the picture carrier PLL can be disengaged (e.g. in
FM radio standard)
0
PLL off (FM radio)
1*
PLL on
R/W
PULL_IN selects the pull-in range of the picture
carrier PLL/FPLL
0
pull-in range ±1.66 MHz
1*
pull-in range ±830 kHz
R/W
The carrier detector freezes the PLL in case of a
picture carrier overmodulation (especially when the
picture carrier is very low or disappears). In
addition, the picture carrier DTO value is forced to
an optimal one to avoid picture carrier phase drift.
To adjust the threshold see CAR_DET_LVL.
0*
carrier detector off
1
carrier detector on
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 17. PC_PLL_THRES register (address 05h) bit description
Legend: * = default value.
Bit
Symbol
7 to 4 -
Access Value Description
R/W
-
3 to 0 PH_ERR_THRES[3:0] R/W
not used
When the settable threshold for the linear phase
detector as part of the picture carrier PLL is
passed, the phase detector slope is weighted
according to the settings in PHASE_GAIN. This
feature is of advantage during adverse field
conditions. In case multipath happens like
ghosts, the PC PLL should not follow the sudden
phase jumps. So, the PC PLL is made slow
(lower loop bandwidth) with PC_PLL_THRES
after surpassing the threshold. This threshold is
related to a fraction of FS. There, FS is 90° if
PHASE_PER is logic 0 (default) or 180° when
logic 1. If the ICPM or ICFM is large because of
bad transmitters with oscillator pulling or
modulator imbalance, the PC PLL should follow
as true as possible. This can be done by
increasing the loop bandwidth with overweighting
(see PHASE_GAIN, Table 18).
0001
1⁄
32
FS
0010
1⁄
16
FS
0100*
1⁄
8
FS
1000
1⁄
4
FS
Table 18. PC_PLL_WGT register (address 06h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7
PHASE_PER
R/W
By default, the linear phase detector transfer
function is repetitive in π. This allows a good
picture carrier overmodulation performance,
because the PC PLL doesn’t need to reacquire
the 180° phase modulation, caused by the
excessive AM index above m = 100 % (negative
residual picture carrier).
0*
π (needed for overmodulation)
1
2π
6 to 0 PHASE_GAIN[6:0] R/W
phase error weighting (adaptive loop speed), see
also PH_ERR_THRES in Table 17 for
explanation
000 0001
× 1⁄16
000 0010
× 1⁄8
000 0100
× 1⁄4
000 1000
× 1⁄2
001 0000*
flat (no weighting)
010 0000
×2
100 0000
×4
TDA8295_1
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25 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 19. PC_FLL_FUNC register (address 07h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7
FLL_ON
R/W
The FLL can be switched off for debugging purposes.
In Functional mode, FLL_ON must be logic 1 for all
cases.
0
FLL off (only for debugging)
1*
6
LIM_ON
FLL on
R/W
The default value is logic 0 to have a normal action
FLL. However, some flexibility has been included for
field investigations and debugging purposes.
0*
limitation off
1
limitation on
5 to 0 FLL_LIM[5:0] R/W
With these settings, the FLL action can be reduced. For
better acquisition behavior, a large value should be
chosen. The settings are ‘don’t care’ if LIM_ON is
logic 0.
00 0001
1⁄
4096
FS
00 0010
1⁄
2048
FS
00 0100*
1⁄
1024
FS
00 1000
1⁄
512
FS
01 0000
1⁄
256
FS
10 0000
1⁄
128
FS
Table 20. CARDET_LEVEL register (address 08h) bit description
Legend: * = default value.
Bit
Symbol
7 to 5 -
Access Value
Description
R/W
not used
-
4 to 0 CAR_DET_LVL[4:0] R/W
determines the action threshold of the above
carrier detector; if carrier detector is off,
CAR_DET_LVL settings are irrelevant
0 0001
carrier detector action below 0.5 % residual PC
0 0010
carrier detector action below 1 % residual PC
0 0100
carrier detector action below 2 % residual PC
0 1000*
carrier detector action below 4 % residual PC
1 0000
carrier detector action below 8 % residual PC
X XXXX
don’t care if CAR_DET = 0
TDA8295_1
Product data sheet
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26 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
9.3.5 Picture and sound carrier DTO
Table 21. DTO_PC_LOW, DTO_PC_MID and DTO_PC_HIGH register (address 09h to 0Bh) bit description
Legend: * = default value.
Address Register
Bit
Symbol
Access Value Description
09h
DTO_PC_LOW 7 to 0 DTO_PC[7:0]
R/W
85h*
0Ah
DTO_PC_MID
R/W
F6h*
0Bh
DTO_PC_HIGH 7 to 0 DTO_PC[23:16] R/W
92h*
7 to 0 DTO_PC[15:8]
With the digitally tuned picture carrier oscillator
(DTO_PC), the IF frequency for the picture carrier
demodulation can be set. This function is
implemented for general purpose applications which
are different from nominal TV standards. It can also
be used for debugging purposes. The DTO_PC is
part of the picture carrier PLL. To set the DTO_PC
value to a certain PC input frequency (fIF), please
use the following formula:
13.5 MHz – f IF
24
DTO_PC = -------------------------------------- × 2 . If e.g. the IF
13.5 MHz
picture carrier input frequency is 5.75 MHz
(M/N standard), one gets 92 F685h as result for
DTO_PC.
Table 22. DTO_SC_LOW, DTO_SC_MID and DTO_SC_HIGH register (address 0Ch to 0Eh) bit description
Legend: * = default value.
Address Register
Bit
Symbol
Access Value Description
0Ch
DTO_SC_LOW 7 to 0 DTO_SC[7:0]
R/W
55h*
0Dh
DTO_SC_MID
R/W
55h*
0Eh
DTO_SC_HIGH 7 to 0 DTO_SC[23:16] R/W
55h*
7 to 0 DTO_SC[15:8]
The DTO_SC is part of the FM/AM mono sound
demodulator. DTO_SC is calculated in the same
way as DTO_PC (described above). In case of
M/N standard (sound carrier at 4.5 MHz), one gets
55 5555h for DTO_SC.
TDA8295_1
Product data sheet
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
9.3.6 Filter settings
Table 23. FILTERS_1 register (address 0Fh) bit description
Legend: * = default value.
Bit
Symbol
7 to 5 VID_FILT[2:0]
4 to 0 NOTCH_FILT[4:0]
Access Value
Description
R/W
video low-pass filter to remove all unwanted
frequencies (own sound carriers) above video
content (see Figure 7)
001*
video low-pass filter 4 MHz
010
video low-pass filter 5 MHz
100
video low-pass filter off
R/W
The notch filter attenuates the adjacent sound
carrier N − 1, which is located differently
dependent on channel spacing 6 MHz, 7 MHz or
8 MHz (see Figure 8).
0 0001*
notch filter for 6 MHz channel spacing
(M/N standard)
0 0010
notch filter for 7 MHz channel spacing
(B standard)
0 0100
notch filter for 8 MHz channel spacing (G/H,
D/K, I, L and L-accent standard)
1 0000
notch/low-pass filter off
001aah358
10
αresp(f)
(dB)
−10
(1)
(2)
−30
−50
−70
0
1
2
3
4
5
6
7
f (MHz)
(1) M/N standard.
(2) All other standards.
Fig 7. Video low-pass filters for sound carrier suppression
TDA8295_1
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
001aah359
10
αresp(f)
(dB)
0
−10
(1)
(2)
(3)
−20
−30
−40
−50
−60
0
2
4
6
8
10
12
14
f (MHz)
Notch filter for NSC (NPC for L-accent standard)
(1) M/N standard.
(2) B standard.
(3) G/H, D/K, I, L and L-accent standard.
Fig 8. Notch filter for adjacent sound carrier suppression
Table 24. FILTERS_2 register (address 10h) bit description
Legend: * = default value.
Bit
Symbol
7 to 5 4
Access Value Description
R/W
-
DC_NOTCH R/W
notch filter to remove ADC DC offset
0
1*
3 to 0 SBP[3:0]
not used
R/W
off
on
The SSIF band-pass attenuates unwanted video
frequencies, e.g. color carrier. For FM radio standard it
provides almost channel selectivity (see Figure 9).
0001*
SSIF band-pass 4.5 MHz (M/N standard)
0010
SSIF band-pass 6.2 MHz (all other TV standards)
0100
SSIF band-pass 5.5 MHz high selectivity (FM radio)
1000
SSIF band-pass off
TDA8295_1
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29 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
001aah360
10
αresp(f)
(dB)
(1)
(2)
(3)
−10
−30
−50
−70
0
2
4
6
8
10
12
14
f (MHz)
(1) M/N standard.
(2) All other standards.
(3) FM radio.
Fig 9. SSIF and FM radio band-pass filters
9.3.7 Group delay equalization
Table 25. GRP_DELAY register (address 11h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7 to 5 -
R/W
not used
4 to 0 GRP_DEL[4:0]
R/W
-
group delay equalization to correct the transmitter
predistortion
0 0001*
group delay M/N standard
0 0010
group delay B/G/H standard
0 0100
group delay D/K standard
0 1000
group delay L/L-accent standard
1 0000
group delay I (flat) standard
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
9.3.8 Digital IF AGC functions
Table 26. D_IF_AGC_SET_1 register (address 12h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7
D_IF_AGC_CORR
R/W
This determines the condition under which the
digital IF AGC switches to Correlated mode. If
D_IF_AGC_CORR is HIGH, the digital IF AGC
works in a Correlated mode only if N_H_LOCK,
F_H_LOCK and V_LOCK are active (see
H/V PLL read-out in Table 44). If LOW, the
Correlated mode is activated when N_H_LOCK
and V_LOCK are active.
6
D_IF_AGC_MODE
0
H-lock + V-lock
1*
H-lock + fast H-lock + V-lock
R/W
If HIGH, the digital IF AGC detection and gating
is done during the back porch of the video
signal. This Detection mode can be used for all
standards (also L/L-accent standard) without
impact on the IF AGC loop speed.
0*
peak sync AGC (slow peak white L/L-accent
standard)
1
black level AGC detection
5 to 1 D_IF_AGC_AVG[4:0] R/W
With D_IF_AGC_AVG the number of lines for
averaging during the digital IF AGC gating
window is set. This is only valid if the AGC mode
is correlated (H/V PLL locked). With the
averaging, the line noise at low RF levels is
reduced.
0 0001
2 samples
0 0010
4 samples
0 0100
8 samples
0 1000
16 samples
1 0000*
0
RST_INT
R/W
0*
normal operation
1
reset IF AGC integrator
TDA8295_1
Product data sheet
32 samples
The digital IF AGC integrator can be set to zero
(i.e. lowest digital IF AGC gain). This option can
be used for debugging purposes.
© NXP B.V. 2008. All rights reserved.
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 27. D_IF_AGC_SET_2 register (address 13h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7
D_AGC_ERR_LIM
R/W
With D_AGC_ERR_LIM the digital IF AGC
error slope is limited. This can improve
performance under the presence of e.g.
impulsive noise that can confuse the AGC
detector.
0
limitation off
1*
limitation on
6 to 0 D_IF_AGC_BW[6:0] R/W
digital IF AGC 3 dB-loop bandwidth setting
000 0001
25 Hz
000 0010
50 Hz
000 0100
100 Hz
000 1000
200 Hz
001 0000*
400 Hz
010 0000
800 Hz
100 0000
1.6 kHz
Table 28. D_IF_AGC_FORCE register (address 14h) bit description
Legend: * = default value.
Bit
Symbol
Access Value Description
7
D_FORCE
R/W
the IF AGC output voltage can be forced externally
to a fixed voltage, determined by IF_AGC_EXT
0*
IF AGC normal operation
1
IF AGC output voltage determined by
D_FORCE_VAL
6 to 0 D_FORCE_VAL[6:0] R/W
This determines the digital IF AGC forced value
and is a ‘don’t care’ if D_FORCE is LOW. The
format is twos complement. The default is 67h,
which equals 0 dB internal gain. In the following
some possible settings for 6 dB gain steps are
shown.
51h
−12 dB
5Ch
−6 dB
67h*
0 dB
72h
+6 dB
7Dh
+12 dB
08h
+18 dB
13h
+24 dB
1Eh
+30 dB
29h
+36 dB
34h
+42 dB
3Fh
+48 dB
XXh
don’t care if D_FORCE = 0
TDA8295_1
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
9.3.9 Tuner IF AGC functions
Table 29. T_IF_AGC_SET register (address 15h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7
POL_TIF
R/W
tuner IF AGC polarity
0
inverted tuner IF AGC polarity
1*
normal tuner IF AGC polarity: the higher
the necessary gain, the higher the IF
AGC voltage
6 to 0 T_IF_AGC_SPEED[6:0] R/W
T_IF_AGC_SPEED determines the tuner
IF AGC loop speed
000 0001
−18 dB nominal
000 0010
−12 dB nominal
000 0100
−6 dB nominal
000 1000*
nominal speed (determined by the tuner
IF control slope)
001 0000
+6 dB nominal
010 0000
+12 dB nominal
100 0000
+18 dB nominal
Table 30. T_IF_AGC_LIM register (address 16h) bit description
Legend: * = default value.
Bit
Symbol
7 to 4 UP_LIM[3:0]
Access Value
Description
R/W
The tuner IF AGC output voltage can be limited to
interface with concepts having power supply < 3.3 V.
UP_LIM determines the upper limit from 1⁄2 FS (= 0h) to
FS (= Fh). The format is straight binary.
1111*
3 to 0 LOW_LIM[3:0]
set upper limit to maximum
R/W
LOW_LIM determines the lower tuner IF AGC output
limit from 0 (= 0h) to 1⁄2 FS (= Fh). The format is straight
binary.
0000*
set lower limit to minimum
Table 31. T_IF_AGC_FORCE register (address 17h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7
T_FORCE
R/W
the tuner IF AGC output voltage can be forced
externally to a fixed voltage, determined by
T_FORCE_VAL
6 to 0 T_FORCE_VAL[6:0]
0*
tuner IF AGC normal operation
1
tuner IF AGC output voltage determined by
T_FORCE_VAL
R/W
T_FORCE_VAL determines the tuner IF AGC
forced value. So the tuner IF AGC can be fixed to
a certain value for debugging purposes. Format is
straight binary.
3Fh*
0.5 × VDD(3V3), i.e. 1.65 V nominally
XXh
don’t care if T_FORCE = 0
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Digital global standard low IF demodulator for analog TV and FM radio
Table 32. T_IF_AGC_FS register (address 18h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7 to 3 -
R/W
not used
2 to 0 T_IF_AGC_FS[2:0]
R/W
-
by increasing the IF AGC noise shaper sampling
rate (fs), the noise shaper in-band disturbance
(line clamping noise) can be heavily reduced
000
fs = 13.5 MHz
010*
fs = 27 MHz
100
fs = 54 MHz
9.3.10 V-sync adjustment
Table 33. V_SYNC_DEL register (address 1Ch) bit description
Legend: * = default value.
Bit
Symbol
Access Value
7 and 6 VS_WIDTH[1:0] R/W
5
4 to 0
VS_POL
VS_DEL[4:0]
Description
VS_WIDTH determines the width (in horizontal
lines) of the V-sync gating pulse (needed for gating
of tuner RF AGC2)
00
width 1 line (64 µs)
01*
width 2 lines
10
width 4 lines
11
width 16 lines
R/W
VS_POL determines the polarity of the V-sync
pulse: if VS_POL = 1, the first edge of the pulse is
positive, else negative.
0
first edge negative
1*
first edge positive
R/W
VS_DEL determines the first edge position of the
output V-sync pulse compared to the beginning of
the vertical blanking interval:
pulse_position = ( VS_DEL – 12 ) lines
0Fh*
first edge 3 lines after beginning of vertical
interval
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
9.3.11 CVBS settings
Table 34. CVBS_SET register (address 1Dh) bit description
Legend: * = default value.
Bit
Symbol
Access Value Description
7 to 3 -
R/W
2
R/W
FOR_BLK
-
not used
when active, the video output is always blanked, e.g. for
channel change (forced blank)
0*
no action
1
1
AUTO_BLK
video blanked
R/W
when active, the video output is blanked if the horizontal
line lock flag (N_H_LOCK, see Table 44) is not present
0*
auto-blanking off
1
0
VID_LVL
auto-blanking on
R/W
the video levelling stage ensures a constant and clipping
free video output level (important for excessive picture
carrier overmodulation)
0
video levelling stage off
1*
video levelling stage on
Table 35. CVBS_LEVEL register (address 1Eh) bit description
Legend: * = default value.
Bit
Symbol
Access Value
7 to 0 CVBS_LVL[7:0] R/W
Description
With this byte, the nominal video output level is freely
programmable. The format is unsigned integer (offset
binary). Settings below 40h and above C0h, which
correspond to −5 dB (40h) and +4.5 dB (C0h) related to
the default value, are forbidden. In the following some
possible settings in 1 dB steps are shown.
51h
−3 dB nominal
5Bh
−2 dB nominal
66h
−1 dB nominal
73h*
nominal: 1 V (p-p) video output level (sync-peak)
81h
+1 dB nominal
91h
+2 dB nominal
A2h
+3 dB nominal
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Digital global standard low IF demodulator for analog TV and FM radio
Table 36. CVBS_EQ register (address 1Fh) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7 to 0 CVBS_EQ[7:0] R/W
The video equalizer can be used for the
compensation of a principal tuner tilt or to change
the video frequency according to customer taste.
The figures given are at 5 MHz CVBS with respect
to low frequencies (see Figure 10).
0000 0001
The video frequency response is −8 dB for
5 MHz.
0000 0010
The video frequency response is −6 dB for
5 MHz.
0000 0100
The video frequency response is −4 dB for
5 MHz.
0000 1000*
The video frequency response is −2 dB for
5 MHz.
0001 0000
The video frequency response is made flat in this
mode.
0010 0000
The video frequency response is +2 dB
(peaking) for 5 MHz.
0100 0000
The video frequency response is +4 dB
(peaking) for 5 MHz.
1000 0000
The video frequency response is +6 dB
(peaking) for 5 MHz.
001aah361
10
αresp(f)
(dB)
6
2
−2
−6
−10
0
1
2
3
4
5
6
7
f (MHz)
Fig 10. Video equalizer curves
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Digital global standard low IF demodulator for analog TV and FM radio
9.3.12 SSIF and mono sound settings
Table 37. SOUNDSET_1 register (address 20h) bit description
Legend: * = default value.
Bit
Symbol
7
-
Access Value
R/W
6 and 5 AM_FM_SND[1:0]
-
Description
not used
R/W
Output mode for inbuilt FM/AM mono sound
demodulator
01*
4 to 0
DEEMPH[4:0]
FM sound
10
AM sound (only L/L-accent standard)
XX
don’t care if SSIF output is chosen
(SSIF_SND[1:0] = 10)
R/W
mono sound de-emphasis adjustment to
compensate transmitter pre-emphasis; or
low-pass filter to remove out of audio band
interferers
0 0001*
de-emphasis of 75 µs for M/N standard or
non-European FM radio to compensate the
transmitter pre-emphasis
0 0010
de-emphasis of 50 µs for B/G/H, D/K and
I standard or European FM radio to
compensate the transmitter pre-emphasis
0 0100
low-pass filter with 30 kHz −3 dB cut-off
frequency to remove out of audio band
interferers
0 1000
low-pass filter with 140 kHz −3 dB cut-off
frequency to drive an external BTSC stereo
decoder
1 0000
The de-emphasis filter is bypassed. This
can be used for debugging or other
purposes.
Table 38. SOUNDSET_2 register (address 21h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7 to 5
-
R/W
not used
4
HD_DK
R/W
-
When active, the internal FM mono sound
demodulator can handle excessive FM deviations up
to 400 kHz. This might happen in D/K standard
China. To activate this mode, it is mandatory to set
D/K standard first. The sound output level has to be
adapted accordingly by the microprocessor to avoid
sound DAC clipping. E.g. for 400 kHz FM deviation,
the −12 dB setting of the sound level register
(see Table 39) is recommended.
0*
high Deviation mode off
1
high Deviation mode on
X
don’t care if SSIF output is chosen
(SSIF_SND[1:0] = 10)
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Digital global standard low IF demodulator for analog TV and FM radio
Table 38. SOUNDSET_2 register (address 21h) bit description …continued
Legend: * = default value.
Bit
Symbol
Access Value
Description
3
FOR_MUTE
R/W
When active, the mono sound signal is always muted.
This setting only makes sense in case the sound DAC
output is also set to mono sound
(SSIF_SND[1:0] = 01). FOR_MUTE has no function if
SSIF_SND[1:0] = 10.
2
AUTO_MUTE
0*
off
1
on
X
don’t care if SSIF output is chosen
(SSIF_SND[1:0] = 10)
R/W
When active, the mono sound signal is muted if the
horizontal lock flag (N_H_LOCK) disappears. This
setting only makes sense in case the sound DAC
output is also set to mono sound
(SSIF_SND[1:0] = 01). FOR_MUTE has no function if
SSIF_SND[1:0] =10.
0*
off
1
on
X
don’t care if SSIF output is chosen
(SSIF_SND[1:0] = 10)
1 and 0 SSIF_SND[1:0] R/W
either mono sound or SSIF can be chosen for the
sound DAC output
01
mono sound
10*
SSIF
Table 39. SOUND_LEVEL register (address 22h) bit description
Legend: * = default value.
Bit
Symbol
7 to 5 -
Access Value
Description
R/W
not used
-
4 to 0 SND_LVL[4:0] R/W
mono sound output level
0 0001
−12 dB nominal; implemented for flexibility reasons.
With this setting, the adaptation to different standard
requirements can be done.
0 0010
−6 dB nominal; implemented for flexibility reasons.
With this setting, the adaptation to different standard
requirements can be done. It is chosen for FM radio
because of the large FM deviation involved.
0 0100
Nominal setting; FM deviations up to 100 kHz can be
processed without sound DAC clipping. The clipping
level is 535 mV (RMS) typically.
0 1000*
+6 dB nominal; chosen for M/N standard due to less
nominal frequency deviation
1 0000
+12 dB nominal; implemented for flexibility reasons.
With this setting, the adaptation to different standard
requirements can be done.
X XXXX
don’t care if SSIF output is chosen
(SSIF_SND[1:0] = 10)
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Digital global standard low IF demodulator for analog TV and FM radio
Table 40. SSIF_LEVEL register (address 23h) bit description
Legend: * = default value.
Bit
Symbol
7 to 5 -
Access Value
Description
R/W
not used
-
4 to 0 SSIF_LVL[4:0] R/W
SSIF output level
0 0001
−12 dB nominal; implemented for flexibility reasons.
With this setting, the adaptation to different standard
requirements can be done.
0 0010
−6 dB nominal; implemented for flexibility reasons.
With this setting, the adaptation to different standard
requirements can be done.
0 0100*
Nominal setting; typical output level is 55 mV (RMS)
for PC / SC ratio of 13 dB (see Section 12).
0 1000
+6 dB nominal; implemented for flexibility reasons.
With this setting, the adaptation to different standard
requirements can be done.
1 0000
+12 dB nominal; implemented for flexibility reasons.
With this setting, the adaptation to different standard
requirements can be done.
X XXXX
don’t care if mono sound output is chosen
(SSIF_SND[1:0] = 01)
9.3.13 Status registers: ADC saturation, AFC, H/V PLL and AGC
Table 41.
Bit
ADC_SAT register (address 24h) bit description
Symbol
Access Value
7 to 0 ADC_SAT[7:0] R
-
Description
With ADC_SAT, the ADC saturation percentage in a
period of 40 ms can be calculated by the following
ADC_SAT
formula: saturation = ------------------------- (%) .
256
Table 42.
Bit
AFC register (address 25h) bit description
Symbol
7 to 0 AFC[7:0]
Access Value
Description
R
This is the readout for AFC. AFC contains the
frequency deviation from nominal IF picture carrier. The
format is twos complement, 13.2 kHz steps are done
per LSB. See Table 43 for details. The frequency
deviation could also be given by the following formula:
-
– AFC × 6 750
f IF – f nom = ---------------------------------- (kHz) . For a frequency
256
deviation from the nominal IF picture carrier greater
than the FPLL pull-in capability (−830.6 kHz to
+843.8 kHz or −1674.3 kHz to +1687.5 kHz), the
output reading is undefined. The AFC lock indication
can be taken from the N_H_LOCK information from the
H-sync PLL. The lock occurs inside a frequency
window, which is determined by the pull-in capability of
the FPLL.
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Digital global standard low IF demodulator for analog TV and FM radio
Table 43.
Calculation of frequency deviation from AFC value
Deviation from nominal AFC[7] AFC[6] AFC[5] AFC[4] AFC[3] AFC[2] AFC[1] AFC[0]
IF frequency[1]
fIF = fnom − 1674.3 kHz
0
1
1
1
1
1
1
1
fIF = fnom − 1661.1 kHz
0
1
1
1
1
1
1
0
:
:
:
:
:
:
:
:
:
fIF = fnom − 830.6 kHz
0
0
1
1
1
1
1
1
fIF = fnom − 817.4 kHz
0
0
1
1
1
1
1
0
:
:
:
:
:
:
:
:
:
fIF = fnom − 13.2 kHz
0
0
0
0
0
0
0
1
fIF = fnom
0
0
0
0
0
0
0
0
fIF = fnom + 13.2 kHz
1
1
1
1
1
1
1
1
:
:
:
:
:
:
:
:
:
fIF = fnom + 830.6 kHz
1
1
0
0
0
0
0
1
fIF = fnom + 843.8 kHz
1
1
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
fIF = fnom + 1674.3 kHz
1
0
0
0
0
0
0
1
fIF = fnom + 1687.5 kHz
1
0
0
0
0
0
0
0
[1]
See Section 12 for nominal IF frequencies.
Table 44.
Bit
HVPLL_STAT register (address 26h) bit description
Symbol
Access Value
Description
R
-
not used
5
NOISE_DET R
-
This flag gets HIGH in case the video S/N (weighted)
drops below 30 dB. For proper and noise free video
signals it stays LOW. It can be used for debugging and
other purposes.
4
MAC_DET
R
-
This flag indicates the presence of copy-guarded video
content from STBs or VCRs. It can be used for
debugging and other purposes.
3
FIDT
R
-
This flag indicates the frame rate (50 Hz or 60 Hz).
When active, 60 Hz is detected. It can be used for
debugging and other purposes.
2
V_LOCK
R
-
This flag is active, if a proper frame (50 Hz or 60 Hz) is
detected. It can be used for debugging and other
purposes.
1
F_H_LOCK
R
-
This flag is active, if a proper H-sync (15.625 kHz or
15.734 kHz) is detected (Fast mode). It can be used for
debugging and other purposes.
0
N_H_LOCK
R
-
This flag is active, if a proper H-sync (15.625 kHz or
15.734 kHz) is detected (Normal mode). It can be used
for debugging and other purposes.
7 and 6 -
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Digital global standard low IF demodulator for analog TV and FM radio
Table 45.
Bit
D_IF_AGC_STAT register (address 27h) bit description
Symbol
Access Value
7 to 0 D_IF_AGC_STAT[7:0] R
-
Description
D_IF_AGC_STAT is the digital IF AGC status
readout byte. Contains the digital IF AGC loop
DC information. The format is twos
complement. To get the internal gain in dB, the
following formula can be used:
D_IF_AGC_STAT + 50
gain = -------------------------------------------------------- (dB) .
3.675
Table 46.
Bit
T_IF_AGC_STAT register (address 28h) bit description
Symbol
7 to 0 T_IF_AGC_STAT[7:0]
Access Value
Description
R
T_IF_AGC_STAT is the IF AGC status readout
byte. Contains the tuner IF AGC loop DC
information. The format is offset binary.
-
9.3.14 Debug register for ADC and DAC test
Table 47. ANALOG_DEBUG register (address 2Ah) bit description
Legend: * = default value.
Bit
Symbol
7 to 2 1
0
Access Value
R/W
-
ADC_TEST R/W
Description
not used
If ADC_TEST is HIGH, the ADC input signal is interpolated
to 108 MHz and fed to video and sound DAC output; the
main circuitry is bypassed. This feature is intended mainly
for debugging purposes and performance judgment.
0*
Normal mode
1
ADC Test mode
DAC_TEST R/W
DAC Test mode; in this test mode an internally generated
sine wave is given out to video and sound DAC. The
amplitude at DAC output is −1.7 dBFS. The frequency can
be set by DTO_PC. Please use the following formula:
DTO_PC
f = --------------------- × 13.5 MHz . Due to the sampling theorem
24
2
only frequencies up to 6.75 MHz can be generated. This
feature is intended mainly for debugging purposes and
performance judgment.
0*
Normal mode
1
DAC Test mode
X
don’t care if ADC_TEST = 1
9.3.15 Chip identification and Standby mode
Table 48.
Bit
IDENTITY register (address 2Fh) bit description
Symbol
Access Value
7 to 0 IDENTITY[7:0] R
Description
1000 1010 chip identification, value corresponds to TDA8295
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Digital global standard low IF demodulator for analog TV and FM radio
Table 49. CLB_STDBY register (address 30h) bit description
Legend: * = default value.
Bit
Symbol Access Value
7 to 2 1
0
R/W
-
not used
STDBY R/W
CLB
Description
When STDBY is set to logic 1, the chip enters in Standby
mode, and its power consumption is reduced. The IF AGC pin
is set to high-ohmic. The default value is logic 0, which means
that the chip is active.
0*
Normal mode
1
Standby mode
This signal clears the TDA8295 through the I2C-bus interface
(software reset). To activate the reset, just write CLB = 0. This
software reset will not affect the content of the registers.
R/W
0
activate soft reset
1*
normal operation
9.3.16 Status of clock PLL and video/sound DAC load
Table 50.
ANALOG_STAT register (address 32h) bit description
Bit
Symbol
Access Value
Description
7
-
R
not used
6
LOAD_DACV R
5
4
-
output load identification video DAC
0
Normal mode
1
If active, the video DAC output voltage is above
reference voltage.
LOAD_DACS R
PLL_LOCK
3 to 0 -
output load identification sound DAC
0
Normal mode
1
If active, the sound DAC output voltage is above
reference voltage.
R
R
clock PLL lock indicator
0
clock PLL unlocked
1
indicates that the clock PLL is locked
-
reserved
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Digital global standard low IF demodulator for analog TV and FM radio
9.3.17 ADC control
In the TDA8295 a 12-bit ADC is implemented sampling with a 54 MHz clock (27 MHz
optional).
Table 51. ADC_CTL register (address 33h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
7
GAINSET R/W
The track and hold circuit in the converter has a
programmable gain setting, which is controlled by the
GAINSET parameter. In case the gain of the track and hold is
increased, the input range of the ADC is decreased
accordingly.
0*
1
6 to 4 CS[2:0]
3
DCIN
R/W
1
0
SLEEP
PD_ADC
1.0 V (p-p) (6 dB gain)
000
not allowed
001
not allowed
010*
0.50 (recommended for 54 MHz sampling)
011
0.75
100
1.00
101
1.25
110
1.50
111
not allowed
R/W
The input signal of the ADC can be either AC coupled by
means of two capacitors or connected directly to the inputs
(DC coupled).
1
TWOS
2.0 V (p-p)
The current consumption of the ADC can be programmed
with these two bits. It is possible to increase or decrease the
current by the following ratio:
0*
2
Description
R/W
AC coupling
DC coupling
This parameter controls the output format of the ADC.
0
offset binary format
1*
twos complement format
R/W
When HIGH, SLEEP sets the ADC into its Sleep mode. Both
bias current and clock are switched off. In this mode, the
current consumption is reduced by a factor of 6. The
reference circuit will remain active in order to guarantee a fast
recovery from Sleep mode.
0*
Normal mode
1
ADC Sleep mode
R/W
When HIGH, PD_ADC sets the ADC into its Power-down
mode. All internal currents are switched off. In this mode, the
current consumption is near zero (leakage current only).
0*
Normal mode
1
ADC Power-down mode
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Digital global standard low IF demodulator for analog TV and FM radio
Table 52. ADC_CTL_2 register (address 34h) bit description
Legend: * = default value.
Bit
Symbol
7 to 2 1
0
Access Value
R/W
-
AD_PLL_BYP R/W
AD_SR54M
Description
not used
The clock PLL can be bypassed for the ADC sampling
clock. Then the crystal output is directly taken for ADC
sampling.
0*
Normal mode
1
Bypass mode
R/W
AD_SR54M sets the ADC sampling rate
0
ADC sampling rate 27 MHz; first decimation filter is
bypassed
1*
ADC sampling rate 54 MHz
9.3.18 Video and sound DAC control
The TDA8295 implements two 10-bit DAC modules (CVBS and sound outputs) which are
sampled by a 108 MHz clock. A reference module derives biasing currents for the two
DACs.
Table 53. VIDEODAC_CTL register (address 35h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7
-
R/W
reserved, must be set to logic 0
0
6 to 1 B_DA_V[5:0] R/W
0
PD_DA_V
B_DA_V is the coarse output level adjustment
parameters of the video DAC. See Section 13.3.
00 0000
minimum current setting
11 1111*
maximum current setting
R/W
When HIGH, PD_DA_V sets the video DAC into its
Power-down mode.
0*
Normal mode
1
video DAC Power-down mode
Table 54. AUDIODAC_CTL register (address 36h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7
-
R/W
reserved, must be set to logic 0
0
6 to 1 B_DA_S[5:0] R/W
0
PD_DA_S
B_DA_S is the coarse output level adjustment
parameters of the sound DAC. See Section 13.3.
00 0000*
minimum current setting
11 1111
maximum current setting
R/W
When HIGH, PD_DA_S sets the sound DAC into its
Power-down mode.
0*
Normal mode
1
sound DAC Power-down mode
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Digital global standard low IF demodulator for analog TV and FM radio
Table 55. DAC_REF_CLK_CTL register (address 37h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
7
-
R/W
6
DA_CLK_INV R/W
-
1*
DA_PLL_BYP R/W
4 to 1 B_REF[3:0]
0
PD_DA_REF
not used
For debugging purposes, the DAC clock polarity can be
inverted.
0
5
Description
inverted polarity
normal polarity
If active, the clock PLL for DAC sampling can be
bypassed. Then, the crystal output is directly taken for
DAC sampling.
0*
Normal mode
1
Bypass mode
R/W
For accuracy, one external resistor connected to
pin RSET and board ground controls the bias current.
Moreover, B_REF permits to adjust this bias current from
−7 % to +7 % (see Section 13.3). Format is signed
binary.
1111
minimum fine current
0000*
nominal fine current
0111
maximum fine current
R/W
When HIGH, PD_DA_REF sets the reference module
into its Power-down mode.
0*
Normal mode
1
Power-down mode
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Digital global standard low IF demodulator for analog TV and FM radio
9.3.19 Clock generation (PLL and crystal oscillator)
The TDA8295 implements a crystal oscillator which can be used either in Slave mode or
in Oscillator mode (see Section 13.7), and a multipurpose PLL which receives XIN as
input clock, and delivers the system clock of the IC (108 MHz).
Table 56. PLL_REG00 register (address 38h) bit description
Legend: * = default value.
Access Value
Description
7 and 6 -
Bit
Symbol
R/W
reserved, must be set to logic 00
5
R/W
PLL_AUTO
00
clock PLL mode control
0
The sequencing of the programming and monitoring
of the PLL can be made ‘manually’ through CLK_EN,
BYP_PLL, PD_PLL and LOCK, according to the
following set of instructions:
After a hardware reset:
•
•
Set PLL_AUTO to logic 0
By default, CLK_EN = BYP_PLL = PD_PLL = 1,
LOCK = 0, the PLL is in Power-down mode, is not
locked, and the output clock is the clock of the
quartz oscillator used to resynchronize reset
signals in the TDA8295
Then:
4 to 0
-
Table 57.
R/W
•
•
Set BYP_PLL and CLK_EN to logic 0
•
Set PD_PLL to logic 0, in order that the PLL
takes those parameters into account and starts
up
•
Then, wait for a minimum time of 500 µs (which is
the maximum time the PLL should take to lock).
This time could be used to make the
programming of the other I2C-bus registers.
•
Set CLK_EN to logic 1 to enable the sampling
frequency to the rest of the chip
•
Optionally, verify that LOCK = 1
Set MSEL, NSEL and PSEL that are
corresponding to the frequency required value
1*
The sequencing of the programming and monitoring
of the PLL is handled automatically by the TDA8295
at initialization and each time one of the M, N, P
parameters is changed. Thus, the user has only to
program M, N, P and then once the PLL is locked, its
output clock becomes enabled automatically.
0 0000
reserved, must be set to logic 0 0000
PLL_REG04 register (address 3Ch) bit description
Bit
Symbol
Access Value
Description
7 to 3
-
R/W
-
not used
2 to 0
-
R/W
000
reserved, must be set to logic 000
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Digital global standard low IF demodulator for analog TV and FM radio
Table 58. PLL_REG06 register (address 3Eh) bit description
Legend: * = default value.
Bit
Symbol
Access Value
7
-
R/W
6
CLK_EN
R/W
0
BYP_PLL
reserved, must be set to logic 0
CLK_EN controls the PLL output clock
0
PLL output clock disable
1*
PLL output clock enable
X
5
Description
R/W
don’t care if PLL_AUTO = 1
When HIGH, the internal clocks (for logic, ADC, and
DACs) are directly controlled by the pin XIN.
BYP_PLL acts both on external multiplexers and on
internal PLL bypass. When PLL initialization is
automatic (PLL_AUTO = 1), BYP_PLL is not
considered.
0
internal clocks are controlled by PLL clock
1*
internal clocks are controlled by pin XIN
X
don’t care if PLL_AUTO = 1
4
DIRECTO
R/W
0*
3
DIRECTI
R/W
0*
When DIRECTI is set to logic 1, the pre-divider is
bypassed. If DIRECTO is equal to logic 1, then it is
the post-divider, which is bypassed. Please see
Table 59 for further details.
2 and 1 -
R/W
00
reserved, must be set to logic 00
0
R/W
PD_PLL
Put the PLL in Power-down mode if equal to logic 1.
When PLL initialization is automatic
(PLL_AUTO = 1), PD_PLL is not considered.
0
PLL active
1*
PLL Power-down mode
X
don’t care if PLL_AUTO = 1
Table 59. Truth table for PLL output clock frequency
Legend: * = default value.
DIRECTI
DIRECTO
PLL output clock frequency[1]
1
1
fclk(o)(PLL) = fVCO = fi × 2 × M
1
0
f VCO
fi × M
f clk(o)(PLL) = ------------ = ---------------P
2×P
0
1
fi × 2 × M
f clk(o)(PLL) = f VCO = ------------------------N
0*
0*
f VCO
fi × M
f clk(o)(PLL) = ------------ = ---------------N×P
2×P
[1]
For description of M, N and P see Table 60.
For optimum performances, the following relations must be respected:
• 275 MHz ≤ fVCO ≤ 550 MHz
• 4 kHz ≤ fi ≤ 150 MHz if DIRECTI = 1, else 4 kHz ≤ fi / N ≤ 150 MHz
TDA8295_1
Product data sheet
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Rev. 01 — 4 February 2008
47 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 60. PLL_REG07, PLL_REG08, PLL_REG09 and PLL_REG10 register (address 3Fh to 42h) bit description
Legend: * = default value.
Address Register
3Fh
Bit
Symbol
PLL_REG07 7
Access Value Description
-
R/W
-
not used
6 to 0 -
R/W
00h
reserved, must be set to 00h
40h
PLL_REG08 7 to 0 MSEL[7:0] R/W
1Ah*
It programs the M parameter (M = MSEL + 1). M is the PLL
feedback-divider.
41h
PLL_REG09 7 to 1 NSEL[6:0] R/W
01h*
It programs the N parameter (N = NSEL + 1). N is the PLL
pre-divider.
0
42h
-
R/W
0
reserved, must be set to logic 0
PLL_REG10 7 to 5 -
R/W
000
reserved, must be set to logic 000
01h*
It programs the P parameter (P = PSEL + 1). P is the PLL
post-divider.
4 to 0 PSEL[4:0] R/W
Table 61. XTALOSC_CTL register (address 43h) bit description
Legend: * = default value.
Bit
Symbol Access Value Description
7 to 3
-
R/W
2
HF
R/W
1 and 0 -
R/W
-
not used
With HF, the transconductance of the oscillator gain stage can be set. For
fXIN > 20 MHz, HF should be set to logic 1.
0*
recommended for standard application (16 MHz)
1
recommended if fXIN > 20 MHz
00
reserved, must be set to logic 00
TDA8295_1
Product data sheet
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Rev. 01 — 4 February 2008
48 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
9.3.20 GPIOs
In the TDA8295, three general purpose input/outputs are implemented.
Table 62. GPIOREG_0 register (address 44h) bit description
Legend: * = default value.
Bit
Symbol
7 to 4 GP1_CF[3:0]
3 to 0 GP0_CF[3:0]
Access Value
Description
R/W
It determines how the general purpose pin GPIO1 is
configured.
0000
The GPIO1 pin is in Input mode. The input value is
stored in GP1_VAL.
0001*
The GPIO1 pin is in Open-drain mode. The output
value is determined by GP1_VAL.
0011
The GPIO1 pin is in Output mode. The PLL output
clock divided by two is delivered.
0100
to
1011
The GPIO1 pin is in Output mode. HVPLL signals are
delivered. The output is a one bit signal of
HVPLL_BUS[7:0] according to Table 64.
XXXX
Don’t care if I2CSW_EN = 1. Then the pad is
configured as I2C-bus feed-through like described in
Table 63.
R/W
It determines how the general purpose pin GPIO0 is
configured.
0000
The GPIO0 pin is in Input mode. The input value is
stored in GP0_VAL.
0001*
The GPIO0 pin is in Open-drain mode. The output
value is determined by GP0_VAL.
0011
The GPIO0 pin is in Output mode. The PLL output
clock divided by two is delivered.
0100
to
1011
The GPIO0 pin is in Output mode. HVPLL signals are
delivered. The output is a one bit signal of
HVPLL_BUS[7:0] according to Table 64.
Table 63. GPIOREG_1 register (address 45h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7
I2CSW_EN
R/W
0*
6
I2CSW_ON
R/W
0*
When I2CSW_EN = 1, GPIO1 and GPIO2 are
configured as an I2C-bus feed-through independently of
the GP1_CF and GP2_CF value. When
I2CSW_ON = 0, the feed-through switch is open, and
GPIO1 and GPIO2 are in 3-state. When the switch is
closed (I2CSW_ON = 1), the I2C-bus clock and data
signals (SCL and SDA) are available on the GPIO1 and
GPIO2 pins.
R/W
-
5 and 4 -
not used
TDA8295_1
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Rev. 01 — 4 February 2008
49 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 63. GPIOREG_1 register (address 45h) bit description …continued
Legend: * = default value.
Bit
Symbol
3 to 0
GP2_CF[3:0] R/W
Table 64.
Access Value
Description
It determines how the general purpose pin GPIO2 is
configured.
0000
The GPIO2 pin is in Input mode. The input value is
stored in GP2_VAL.
0001*
The GPIO2 pin is in Open-drain mode. The output
value is determined by GP2_VAL.
0011
The GPIO2 pin is in Output mode. The PLL output
clock divided by two is delivered.
0100
to
1011
The GPIO2 pin is in Output mode. HVPLL signals are
delivered. The output is a one bit signal of
HVPLL_BUS[7:0] according to Table 64.
XXXX
Don’t care if I2CSW_EN = 1. Then the pad is
configured as I2C-bus feed-through.
HVPLL bus mapping
HVPLL_BUS bit
Signal
HVPLL_BUS[7]
V_SYNC
HVPLL_BUS[6]
H_SYNC
HVPLL_BUS[5]
NOISE_DET
HVPLL_BUS[4]
MAC_DET
HVPLL_BUS[3]
FIDT
HVPLL_BUS[2]
V_LOCK
HVPLL_BUS[1]
F_H_LOCK
HVPLL_BUS[0]
N_H_LOCK
Table 65. GPIOREG_2 register (address 46h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
7
CLK_INV_GP2 R/W
0*
6
CLK_INV_GP1 R/W
0*
5
CLK_INV_GP0 R/W
0*
Description
With CLK_INV_GPx, the output clock polarity can be
changed. This is only useful when
GPx_CF[3:0] = 0011.
4 and 3 -
R/W
-
not used
2
GP2_VAL
R/W
1*
GP2_VAL controls the value of the pin GPIO2 when
GP2_CF[3:0] = 0001. When GP2_CF[3:0] = 0000,
GPIO2 is an input pin which value can be read
through the I2C-bus stored in GP2_VAL.
1
GP1_VAL
R/W
1*
GP1_VAL controls the value of the pin GPIO1 when
GP1_CF[3:0] = 0001. When GP1_CF[3:0] = 0000,
GPIO1 is an input pin which value can be read
through the I2C-bus stored in GP1_VAL.
0
GP0_VAL
R/W
1*
GP0_VAL controls the value of the pin GPIO0 when
GP0_CF[3:0] = 0001. When GP0_CF[3:0] = 0000,
GPIO0 is an input pin which value can be read
through the I2C-bus stored in GP0_VAL.
TDA8295_1
Product data sheet
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Rev. 01 — 4 February 2008
50 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
10. Limiting values
Table 66. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1][2]
Symbol
Parameter
VDDDC(1V2)
Conditions
Min
Max
Unit
core digital supply voltage (1.2 V)
−0.5
+3.32
V
VDDA(ADC)(3V3)
ADC analog supply voltage (3.3 V)
−0.5
+5.63
V
VDDA(PLL)(1V2)
PLL analog supply voltage (1.2 V)
−0.5
+3.32
V
VDDA(OSC)(1V2)
oscillator analog supply voltage (1.2 V)
−0.5
+3.32
V
Vi
input voltage
pins IF_POS and IF_NEG
−0.5
+5.63
V
digital input pins (5 V tolerant)
−0.5
+7.5
V
pin XIN
−0.5
+4.0
V
-
300
°C
-
0.5
W
Tlead
lead temperature
Ptot
total power dissipation
Tstg
storage temperature
−40
+125
°C
Tj
junction temperature
-
125
°C
Tamb
ambient temperature
Vesd
Tamb = 70 °C
electrostatic discharge voltage
0
70
°C
pins SDA, SCL, SADDR0 and
SADDR1; machine model
[3]
-
±150
V
all other pins; machine model
[4]
-
±200
V
[1]
Stresses above the absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum ratings
conditions for extended periods may affect device reliability.
[2]
The maximum allowed ambient temperature Tamb depends on the assembly condition of the package and especially on the design of
the PCB. The application mounting must be done in such a way that the maximum junction temperature Tj(max) is never exceeded.
[3]
Class A according to EIA/JESD22-A115.
[4]
Class B according to EIA/JESD22-A115.
11. Thermal characteristics
Table 67.
Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from junction to
ambient
in still air
33
K/W
The thermal resistance depends strongly on the nature of the PCB used in the application
and on its design. The thermal resistance given in Table 67 corresponds to the value that
can be measured on a multilayer PCB (4 layers) as defined by EIA/JESD51-2. This value
is given for information only.
The junction temperature influences strongly the reliability of an IC. The PCB used in the
application contributes on a large part to the overall thermal characteristic. It must
therefore be designed to insure that the junction temperature of the IC never exceeds
Tj(max) = 125 °C at the maximum ambient temperature.
The IC has to be soldered to ground with its die-attached paddle. Plenty of vias are
recommended to remove the heat.
TDA8295_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 4 February 2008
51 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
12. Characteristics
Table 68. Characteristics
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Power supply
VDD(1V2)
supply voltage (1.2 V)
digital and analog
1.08
1.2
1.32 V
VDD(3V3)
supply voltage (3.3 V)
digital and analog
2.97
3.3
3.63 V
IDD(tot)(1V2)
total supply current (1.2 V)
IDD(tot)(3V3)
Ptot
-
28
33
mA
[1]
-
125
136
mA
default settings; 75 Ω drive;
fs = 54 MHz at ADC; including
DAC loads; RRSET = 1 kΩ
[1]
-
434
490
mW
Power-save mode;
fs = 54 MHz at ADC; including
DAC loads; RRSET = 2 kΩ;
see Section 13.6
[2]
-
324
369
mW
Standby mode
-
7
10
mW
total supply current (3.3 V)
total power dissipation
Digital I/Os
VIH
HIGH-level input voltage
all inputs (except pin XIN);
including voltage on outputs in
3-state mode
0.7 × VDD(3V3) -
6.0
V
VIL
LOW-level input voltage
all inputs (except pin XIN);
including voltage on outputs in
3-state mode
-
0.8
V
VOH
HIGH-level output voltage
source current 4 mA
VDD(3V3) − 0.4 -
-
V
VOL
LOW-level output voltage
sink current 4 mA
-
-
0.4
V
Ci
input capacitance
-
-
5
pF
-
108
-
MHz
-
-
±200 10−6
-
16
-
-
Master clock
fclk(o)(PLL)
PLL output clock frequency
∆f/fclk
relative frequency deviation
from clock frequency
[3]
Reference frequency in Slave mode
fclk(ext)
external clock frequency
MHz
Vi(RMS)
RMS input voltage
AC coupled
200
250
-
mV
SRr
rising slew rate
external clock
30
-
-
mV/ns
tjit(cc)
cycle-to-cycle jitter time
RMS value
-
12.5
-
ps
Ci
input capacitance
on pin XIN
-
3
-
pF
-
16
-
MHz
-
-
±200 10−6
0
-
70
Reference frequency in Oscillator mode (with a crystal)
fxtal
crystal frequency
∆fxtal/fxtal
relative crystal frequency
variation
Tamb(xtal)
crystal ambient temperature
temperature, ageing and
spreading
TDA8295_1
Product data sheet
°C
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 4 February 2008
52 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 68. Characteristics …continued
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Vi(p-p)
peak-to-peak input voltage
for full-scale ADC input
(0 dBFS)
1.8
2.0
2.2
V
Ri(dif)
differential input resistance
10
15
-
kΩ
Ci(dif)
differential input capacitance
-
2
3
pF
Vi
input voltage
operational input related to
ADC full scale; all standards;
sum of all signals
−3
−3
−3
dBFS
fi
input frequency
PC / SC1
M/N standard
-
5.75 / 1.25 -
MHz
B standard
-
6.75 / 1.25 -
MHz
G/H standard
-
7.75 / 2.25 -
MHz
I standard
-
7.75 / 1.75 -
MHz
DK and L standard
-
7.75 / 1.25 -
MHz
L-accent standard
IF input
-
1.25 / 7.75 -
MHz
FM radio
-
1.25
-
MHz
Hilbert filter stop-band
−60
-
-
dB
−40
-
-
dB
−40
-
-
dB
IF selectivity
αsup(stpb)
stop-band suppression
decimation filter stop-band
notch for NSC (NPC for
L-accent standard)
[4]
Carrier recovery FPLL
B−3dB(cl)
closed-loop −3 dB
bandwidth
ultrawide
280
280
280
kHz
superwide
130
130
130
kHz
wide
60
60
60
kHz
medium
30
30
30
kHz
15
15
15
kHz
±830
±830
±830 kHz
115
117
-
%
13
-
-
kHz
narrow
∆fpullin
pull-in frequency range
mover(PC)
picture carrier
overmodulation index
black for L/L-accent standard;
flat field white else
fstep(AFC)
AFC step frequency
128 steps
[5]
[5]
IF demodulation (video equalizer in Flat mode)
BT(tot)
total transition bandwidth
Nyquist filter; all standards
1
1
1
MHz
αsup(stpb)
stop-band suppression
Nyquist filter; all standards
−60
-
-
dB
video low-pass filter (M/N,
B/G/H, I, D/K, L/L-accent
standard)
-
−60
-
dB
TDA8295_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 4 February 2008
53 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 68. Characteristics …continued
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Bvideo(−1dB)
−1 dB video bandwidth
M/N standard
-
3.9
-
MHz
B/G/H, I, D/K, L/L-accent
standard
-
4.9
-
MHz
peak value for B/G/H half,
D/K half, I flat, M (FCC) full,
L/L-accent full standard
-
20
40
ns
400
-
-
Hz
0.2
-
-
Hz
negative modulation (all
standards except
L/L-accent)
3
3
3
ms
positive modulation
(L/L-accent standard)
100
100
100
ms
−20
-
+48
dB
with TDA8275A;
positive modulation
-
4000
-
ms
with TDA8275A;
negative modulation
-
500
-
ms
with TDA1827x;
positive modulation
-
3000
-
ms
with TDA1827x;
negative modulation
-
600
-
ms
0.9
1.0
1.1
kHz
tripple(GDE)
group delay equalizer ripple
time
Digital IF AGC (internal loop)
B−3dB(cl)
closed-loop −3 dB
bandwidth
negative modulation (all
standards except L/L-accent)
[6]
positive modulation
(L/L-accent standard)
tresp
∆GAGC
response time
±20 dB level change; video
settled within ±3 dB
AGC gain range
Tuner IF AGC (external loop)
tresp
f−3dB(lpf)
response time
low-pass filter −3 dB
frequency
at 60 dBµV (RMS) PC input;
±20 dB level change; video
settled within ±3 dB
IF AGC postfilter
TDA8295_1
Product data sheet
[7]
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 4 February 2008
54 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 68. Characteristics …continued
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
65 %
-
0.7
0.9
V
90 % (nominal)
0.8
1.0
1.2
V
115 %
-
1.0
1.2
V
65 %
-
0.7
0.9
V
97 % (nominal)
0.8
1.0
1.2
V
115 %
-
1.0
1.2
V
all standards except M/N
4.8
4.85
-
MHz
M/N standard
MHz
CVBS output
Vo(p-p)
peak-to-peak output voltage negative PC modulation (all
standards except L/L-accent);
75 Ω DC load; sync-white
modulation
positive PC modulation
(L/L-accent standard);
75 Ω DC load; sync-white
modulation
Bvideo(−3dB)
−3 dB video bandwidth
overall video response; CVBS
equalizer flat
3.9
4.05
-
αresp(f)
frequency response
video equalizer; 8 equally
spaced settings; value at
3.9 MHz
−5
-
+4.5 dB
Gdif
differential gain
“ITU-T J.63 line 330”
-
1.5
3
%
ϕdif
differential phase
“ITU-T J.63 line 330”
-
1.5
3
deg
-
1
2
%
all standards except
L/L-accent
-
1
3
%
L/L-accent standard in peak
white AGC detection
-
1
5
%
-
2
5
%
1.1 MHz (related to
black-to-white in RMS,
equals CC + 3.6 dB)
-
64
-
dB
3.3 MHz (related to CC)
-
75
-
dB
Vstlt/VCVBS(p-p) synchronization tilt voltage
to peak-to-peak CVBS
voltage ratio
Vftlt/VCVBS(p-p) frame tilt voltage to
peak-to-peak CVBS voltage
ratio
∆Vtro/Vtro
relative transient response
overshoot voltage variation
αIM(blue)
intermodulation suppression carrier levels related to PC
(blue)
sync; PC = −3.2 dB;
CC = −19.2 dB; SC = −13 dB
2T pulse
TDA8295_1
Product data sheet
[8]
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 4 February 2008
55 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 68. Characteristics …continued
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
αIM(yellow)
intermodulation suppression carrier levels related to PC
(yellow)
sync; PC = −10 dB;
CC = −19.2 dB; SC = −13 dB
1.1 MHz (related to
black-to-white in RMS,
equals CC + 3.6 dB)
3.3 MHz (related to CC)
(S/N)w
weighted signal-to-noise
ratio
all standards; unified
weighting filter (“ITU-T J.61”);
PC at −6 dBFS
TDA8295_1
Product data sheet
Min
Typ
Max Unit
-
69
-
dB
-
81
-
dB
58
62
-
dB
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 4 February 2008
56 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 68. Characteristics …continued
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
PSRR
power supply rejection ratio
fripple = 70 Hz; 100 mV (p-p);
video signal: gray; level: 50 %;
TDA8295 stand alone; input
level: 60 dBµV (RMS) PC
positive video modulation;
L standard; 1.2 V
positive video modulation;
L standard; 3.3 V
[9]
negative video modulation;
B standard; 1.2 V
negative video modulation;
B standard; 3.3 V
[9]
Min
Typ
Max Unit
-
52
-
dB
-
30
-
dB
-
51
-
dB
-
30
-
dB
-
26
-
dB
-
22
-
dB
-
43
-
dB
-
32
-
dB
-
26
-
dB
-
22
-
dB
-
43
-
dB
-
32
-
dB
-
56
-
dB
fripple = 70 Hz; 100 mV (p-p);
video signal: gray; level: 50 %;
together with TDA8275A;
input level: 60 dBµV (RMS)
PC
positive video modulation;
L standard; 1.2 V
positive video modulation;
L standard; 3.3 V
[9]
negative video modulation;
B standard; 1.2 V
negative video modulation;
B standard; 3.3 V
[9]
fripple = 70 Hz; 100 mV (p-p);
video signal: gray; level: 50 %;
together with TDA1827x; input
level: 60 dBµV (RMS) PC
positive video modulation;
L standard; 1.2 V
positive video modulation;
L standard; 3.3 V
[9]
negative video modulation;
B standard; 1.2 V
negative video modulation;
B standard; 3.3 V
αsup(f)L(unw)
unwanted leakage
frequency suppression
4.8 MHz video modulation;
related to black-to-white in
10 MHz to 200 MHz band
TDA8295_1
Product data sheet
[9]
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 4 February 2008
57 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 68. Characteristics …continued
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
M standard
-
4.5
-
MHz
B/G/H standard
-
5.5
-
MHz
I standard
-
6.0
-
MHz
D/K/L/L-accent standard
-
6.5
-
MHz
FM radio
-
5.5
-
MHz
all standards except B/G/H
30
35
40
mV
B/G/H standard
27
32
37
mV
FM radio (single carrier)
460
530
610
mV
M standard; 54 %
modulation degree
(±13.5 kHz FM deviation
before pre-emphasis)
125
143
165
mV
B, G/H, I, D, K standard;
54 % modulation degree
(±27 kHz FM deviation
before pre-emphasis)
125
143
165
mV
L/L-accent standard; AM;
m = 54 %
110
126
145
mV
FM radio; 30 % modulation
degree (±22.5 kHz FM
deviation before
pre-emphasis)
56
65
75
mV
high Deviation mode
(D/K standard China);
FM deviation before
pre-emphasis ±400 kHz;
sound level setting: −12 dB
487
560
644
mV
SSIF/mono sound output
fo(SSIF)
Vo(SSIF)(RMS)
Vo(AF)(RMS)
SSIF output frequency
RMS SSIF output voltage
RMS AF output voltage
SC1 or FM radio carrier
1 kΩ DC or AC load;
no modulation;
PC / SC1 = 13 dB; scaled
linearly for all other ratios
1 kΩ DC or AC load
TDA8295_1
Product data sheet
[10]
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 4 February 2008
58 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 68. Characteristics …continued
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
αhr(AF)
AF headroom
before clipping; 1 kΩ DC or
AC load
τdeemp
B−3dB
THD
de-emphasis time constant
−3 dB bandwidth
total harmonic distortion
BAF(−3dB)
−3 dB AF bandwidth
αAM
AM suppression
Min
Typ
Max Unit
M standard; related to
±25 kHz peak deviation
before pre-emphasis
7
7
7
dB
B, G/H, I, D, K standard;
related to ±50 kHz peak
deviation before
pre-emphasis
7
7
7
dB
L/L-accent standard;
PC / SC1 ratio for start of
audio output clipping; AM;
m = 100 %; related to mean
SC1
1
1
1
dB
FM radio; 30 % modulation
degree related to ±22.5 kHz
peak deviation before
pre-emphasis
7
7
7
dB
M/N standard (mono);
FM radio USA
75
75
75
µs
B/G/H, I, D/K standard;
FM radio Europe
50
50
50
µs
L/L-accent standard
30
30
30
kHz
M-BTSC standard
140
140
140
kHz
FM; for 50 kHz deviation
before pre-emphasis (25 kHz
for M standard)
-
0.1
0.2
%
AM; m = 80 %
-
0.6
1
%
AM
20
27
-
kHz
FM
40
50
-
kHz
of FM demodulator;
AM: f = 1 kHz; m = 54 %
referenced to 27 kHz FM
deviation
40
46
-
dB
audio low-pass filter
TDA8295_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 4 February 2008
59 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 68. Characteristics …continued
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
(S/N)w(AF)
AF weighted signal-to-noise
ratio
via internal mono sound
demodulator;
“ITU-R BS.468-4”; FM mode
related to 27 kHz deviation
before pre-emphasis; 10 %
residual PC; SC1
Min
Typ
Max Unit
black picture
54
58
-
dB
flat field white picture
53
57
-
dB
6 kHz sine wave picture
52
56
-
dB
250 kHz square wave
picture
52
56
-
dB
crosshatch picture
52
56
-
dB
color bar picture
54
58
-
dB
via internal mono sound
demodulator;
“ITU-R BS.468-4”; AM;
m = 54 %; 3 % residual PC;
SC1
black picture
43
45
-
dB
flat field white picture
43
46
-
dB
color bar picture
43
46
-
dB
47
51
-
dB
via internal mono sound
demodulator;
“ITU-R BS.468-4”;
FM Radio mode
TDA8295_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 4 February 2008
60 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 68. Characteristics …continued
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
(S/N)w(SC1)
first sound carrier weighted
signal-to-noise ratio
via external SSIF sound
demodulator in Dual mode;
“ITU-R BS.468-4”; FM mode
related to 27 kHz deviation
before pre-emphasis; 10 %
residual PC
Min
Typ
Max Unit
black picture
60
64
-
dB
flat field white picture
60
64
-
dB
6 kHz sine wave picture
54
58
-
dB
250 kHz square wave
picture
55
59
-
dB
crosshatch picture
54
58
-
dB
color bar picture
59
63
-
dB
black picture
40
43
-
dB
flat field white picture
40
43
-
dB
color bar picture
40
43
-
dB
black picture
58
62
-
dB
flat field white picture
58
62
-
dB
6 kHz sine wave picture
54
58
-
dB
250 kHz square wave
picture
46
50
-
dB
crosshatch picture
56
60
-
dB
color bar picture
57
61
-
dB
60
64
-
dB
via SSIF sound demodulator;
“ITU-R BS.468-4”; AM;
m = 54 %; 3 % residual PC
(S/N)w(SC2)
(S/N)w
second sound carrier
weighted signal-to-noise
ratio
weighted signal-to-noise
ratio
via external SSIF sound
demodulator in Dual mode;
“ITU-R BS.468-4”; FM mode
related to 27 kHz deviation
before pre-emphasis; 10 %
residual PC
FM radio; via SSIF sound
demodulator in Mono mode;
“ITU-R BS.468-4”
TDA8295_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 4 February 2008
61 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 68. Characteristics …continued
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 12) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
PSRR
power supply rejection ratio
fripple = 70 Hz; 100 mV (p-p);
video signal: gray; level: 50 %;
TDA8295 stand alone
FM sound; 1.2 V
FM sound; 3.3 V
[9]
AM sound; 1.2 V
AM sound; 3.3 V
[9]
Min
Typ
Max Unit
-
72
-
dB
-
33
-
dB
-
68
-
dB
-
37
-
dB
fripple = 70 Hz; 100 mV (p-p);
video signal: gray; level: 50 %;
together with TDA8275A;
input level: 60 dBµV (RMS)
PC
FM sound; 1.2 V
FM sound; 3.3 V
-
72
-
dB
[9]
-
33
-
dB
-
22
-
dB
[9]
-
22
-
dB
AM sound; 1.2 V
AM sound; 3.3 V
fripple = 70 Hz; 100 mV (p-p);
video signal: gray; level: 50 %;
together with TDA1827x; input
level: 60 dBµV (RMS) PC
FM sound; 1.2 V
FM sound; 3.3 V
-
72
-
dB
[9]
-
33
-
dB
-
22
-
dB
[9]
-
22
-
dB
-
33
-
dB
AM sound; 1.2 V
AM sound; 3.3 V
αsup(f)L(unw)
unwanted leakage
frequency suppression
related to SSIF (SC1) in
10 MHz to 200 MHz band
[1]
50 % ADC current; 100 % video DAC current; 50 % sound DAC current.
[2]
50 % ADC current; 50 % video DAC current; 25 % sound DAC current.
[3]
See Section 9.3.19 for PLL setting.
[4]
Standard dependent located at 7.25 MHz, 8.25 MHz, 9.25 MHz, 9.75 MHz and 10.25 MHz.
[5]
The pull-in range can be doubled to ±1660 kHz by I2C-bus register like described in Table 16. Then the AFC read-out has 256 steps.
[6]
To counteract a fast IF level reduction, the digital IF AGC loop has a speed-up circuit for positive video modulation.
[7]
In the ordinary system application, this slow response is counteracted by the fast digital IF AGC loop. ADC clipping is practically avoided
by fast-attack AGC characteristic.
[8]
HAD: 250 ns for M standard, 200 ns for others.
[9]
The values given are measured with an IF AGC time constant of 5 Hz. For that, capacitor C7 in Figure 12 must be chosen 220 nF
instead of 2.2 nF. Doing so, the PSRR on 3.3 V together with the tuner can be improved.
[10] SC2 is not listed, but supported for all world standards.
TDA8295_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 4 February 2008
62 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
13. Application information
13.1 Typical application
I2C-bus
I2C-bus
SDA_O
SCL_O
V-sync
SDA
SCL V_IOUTN
VSYNC
V_IOUTP
CVBS
SAA71xx
TDA8275A
TDA1827x
IF_POS
low IF signal
TDA8295
IF_NEG
(TUNER ICs)
S_IOUTP
IF_AGC
tuner IF AGC
S_IOUTN
XIN
reference frequency
SSIF
(AUDIO AND
VIDEO
DECODER)
processed
audio and video
RSET
001aah420
Fig 11. Typical application of TDA8295
TDA8295_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 4 February 2008
63 of 77
TDA8295_1
Rev. 01 — 4 February 2008
low IF
AGND
150 kΩ
C7
2.2 nF
R1
1 nF
C4
1 nF
C3
100 pF
IF_AGC
IF_NEG
IF_POS
XIN
40
29
37
2
1
8
9
I2C-bus
R3
100 Ω
7
220 nF
AGND DGND
DGND
28
R4
100 Ω
10
19
5
20
4
21
F1
220 nF
R2
33
25
DGND
2.2 kΩ
C8
100 nF
DGND
C12
32
35
31
3.3 V
C11
470 nF
DGND
DGND
R8
2.2 Ω
IC1
34
6
TDA8295
26
C13
F2
470 nF
DGND
3.3 V supply
DGND
38
DGND
R7
10 Ω
36
39
DGND
F3
3
30
AGND/
DGND
27
12
C16
AGND
1.2 V supply
DGND
23
15
22
Fig 12. Detailed application diagram of TDA8295
11
V_IOUTP
V_IOUTN
R13
R14
75 Ω
39 Ω
C5
470 pF
CVBS
AGND
C1
47 µF
C6
270 pF
75 Ω
AGND AGND
S_IOUTN R16
AGND
1.2 V
16
R15
75 Ω
AGND AGND
S_IOUTP
SSIF or
17
AUDIO
14
13
R12
1 kΩ
AGND
AGND
DGND
18
R11
1Ω
3.3 V
470 nF
AGND
AGND
R10
1Ω
DGND
DGND
3.3 V
C14
3.3 V
470 nF
DGND
C15
47 µF
DGND
24
AGND
R9
10 Ω
3.3 V
Preferred components: SMD R1 has to be placed near to TDA8295 pin 37 and SMD C7 near to TDA8275A or TDA1827x
F1, F2, F3: BLM18AG102SN1 ferrite bead
to TDA8275A
or TDA1827x
reference
frequency
C2
XOUT
AGND
VDDA(PLL)(1V2)
220 nF
VSSA(ADC)
SDA
VSSA(PLL)
AGND
SCL
VSSD1
SADDR0
VDDD1(1V2)
SADDR1
VDDD2(1V2)
R5
10 Ω
RST_N
VSSDR
C9
GPIO0/VSYNC
VSSD2
R6
10 Ω
GPIO1/SCL_O
VDDDR(3V3)
i.c.
C10
GPIO2/SDA_O
3.3 V
i.c.
VDDD(ADC)(3V3)
i.c.
VDDA(DAC2)(3V3)
1.2 V
TMS
VDDA(ADC)(3V3)
TRST_N
VSSA(DAC)
TCK
VDDA(DAC1)(3V3)
1.2 V
TDI
RSET
Product data sheet
TDO
1.2 V
001aah421
to SCART or
processor
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx
xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx
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NXP Semiconductors
TDA8295
Digital global standard low IF demodulator for analog TV and FM radio
13.2 Detailed application diagram
© NXP B.V. 2008. All rights reserved.
64 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
13.3 DAC connection
This DAC has a differential current output capable of driving a doubly terminated 75 Ω
transmission line without external buffers. But it can also be used in single-ended
applications. In that case both outputs still need proper termination. The off-chip resistive
load must be connected to ground.
With the B_DA_V and B_DA_S coarse output level adjustment registers, the output
current can be increased (linearly) up to two times. However, the maximum output voltage
at both V_IOUTP, V_IOUTN and S_IOUTP, S_IOUTN output nodes still is 1.5 V.
DNL and INL increase when the external biasing resistor is increased. When higher load
resistances are used, distortion will increase linearly. About 12 dB increase in harmonic
distortion is expected at 150 Ω.
Several measures can be taken in order to reach good performance. Decouple the
VDDA(DAC1)(3V3) and the VDDA(DAC2)(3V3) supplies with at least 100 nF. Place the external
bias resistor close to the chip. Do not add decoupling capacitance to pin RSET.
The following relation gives the value of the full-scale current IFS in function of the bias
resistance value, FineControl (B_REF) and CoarseControl (B_DA_V or B_DA_S):
1.216
100
1 64 + CoarseControl
I FS = ------------- × -------------------------------------------- × --- × ------------------------------------------------ × 64
RSET 100 – FineControl 5
48
(1)
−7 ≤ FineControl ≤ +7
0 ≤ CoarseControl ≤ 63
For programming of FineControl (B_REF) see Table 55, for CoarseControl signals
B_DA_V see Table 53, for B_DA_S see Table 54.
13.4 ADC connection
The input signals of the ADC (IF_POS and IF_NEG) can be either AC coupled by means
of two capacitors or connected directly to the inputs (DC coupled). This selection is done
by programming of DCIN, see Table 51.
In case of AC coupling, DCIN should be set to logic 0, which enables two resistive dividers
between VDDA(ADC)(3V3) and VSSD1 take care of the correct DC biasing of the input signals.
In case only a single-ended input signal is available, this signal should be connected to
the IF_POS input by means of a coupling capacitor whereas the IF_NEG input should be
connected to ground using a similar capacitor.
In case the input signal is DC coupled, the input resistor network can be switched off by
setting the DCIN bit to logic 1. When using the ADC in this mode, the Common mode level
of the input signals should be at 0.5 × VDDA(ADC)(3V3). In case of single-ended operation,
the input signal should be connected directly to the IF_POS input and the IF_NEG input
should be connected to a voltage equal to the Common mode level of the input signal
(0.5 × VDDA(ADC)(3V3)).
The peak-to-peak input range can be set to 1 V (p-p) or 2 V (p-p) by programming of
GAINSET (see Table 51). With a differential input the performances of the ADC are
slightly better with GAINSET = 0 whereas with a single-ended input they are slightly better
with GAINSET = 1.
TDA8295_1
Product data sheet
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Rev. 01 — 4 February 2008
65 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
13.5 Reset operation
13.5.1 Hardware reset
minimum width at LOW is 4 × TXIN
RST_N
XIN
TXIN
the TDA8295 enters
immediately in its reset mode
TDA8295 normal operation
starts after 4 falling edges of XIN
001aah362
Fig 13. Hardware reset operation
After a hardware reset, the registers are set to default (power-on reset values) according
to Table 10. M/N standard is the default standard.
13.5.2 Software reset
A software reset can be done each time something has been programmed. The software
reset does not affect the content of the registers but clears the flip-flops in the design. For
the activation of the software reset see Table 49 bit CLB.
13.6 Application hints
• In case GPIO1 and GPIO2 are configured as I2C-bus feed-through, a capacitor
C = 33 pF to GND must be added at pin 32 (GPIO1/SCL_O). This ensures a reliable
behavior in Read mode.
• The detailed application diagram (see Figure 12) shows the video DAC connection
driving a 75 Ω DC load and the sound DAC driving > 1 kΩ AC/DC load. Power-save
mode: In order to reduce power consumption, the video DAC can be run with half
current and the sound DAC with a quarter current by changing RSET (R12 in
Figure 12) to 2 kΩ. This is possible, if the audio/video processor is rather high-ohmic
(> 1 kΩ). The following components in Figure 12 have to be replaced then:
R13 = 75 Ω; R15 and R16 = 150 Ω; C5 = 220 pF; C6 = 120 pF. A performance
degradation is not expected in the Power-save mode.
The TDA8295 has been designed in such a way, that a simple upgrade of the predecessor
TDA8290 is possible:
1. Change the 1.8 V power supply to 1.2 V. This can be done easily with a variable
voltage regulator, where the sense pin is grounded. This delivers the band gap
voltage of 1.25 V to the output. Or take a fixed regulator.
2. The RSET resistor (R12 in Figure 12) has to be decreased by 20 % in order to make
the DAC output swing higher (1.5 V instead of 1.25 V).
3. Pin 6 and pin 36 (both internally connected pins) can still stay connected to the 1.2 V
power supply, as done in the PCBs for the predecessor TDA8290 without harm.
However, take grounds for new designs, because they are more easily accessible on
a PCB.
TDA8295_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 4 February 2008
66 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
13.7 Crystal connection
The typical crystal frequency value is 16 MHz. The values of the passive components
depend on crystal manufacturer. The oscillator can be set in two configurations depending
on the origin of the crystal. Figure 14 describes the case of an crystal shared with the
tuner and the TDA8295 (Slave mode), Figure 15 the case of an crystal dedicated to the
TDA8295 (Oscillator mode).
TDA8295
TDA8295
Rbias
Rbias
XIN
XIN
XTAL
XOUT
XOUT
100 nF
C1
clock signal
from tuner
n.c.
GND
C2
GND
001aah364
001aah363
Slave mode
Oscillator mode
Fig 14. Reference clock application
Fig 15. Oscillator application
In Oscillator mode, only a crystal and the load capacitances C1 and C2 need to be
connected externally since the feedback resistance is integrated on chip. In this mode the
oscillator gain stage can have a normal or large transconductance, determined by the HF
bit (see also Table 61). A large transconductance is required for higher oscillation
frequencies, higher series resistance of the crystal and higher external load capacitors.
For an accurate time reference it is advised to use the load capacitors as specified in
Table 69. CL is the typical load capacitance of the crystal and is usually specified by the
crystal manufacturer.
Table 69.
Crystal parameters together with external components
Fundamental
oscillation
frequency
Crystal load
capacitance
CL(xtal) (pF)
Crystal series
resistance
Rs(xtal) (Ω)
External load capacitors
C1 (pF)
C2 (pF)
10
< 300
18
18
20
< 300
39
39
30
< 300
56
56
10
< 300
18
18
20
< 200
39
39
Bit HF = 0
1 MHz to 5 MHz
5 MHz to 10 MHz
30
< 100
56
56
10 MHz to
15 MHz
10
< 160
18
18
20
< 60
39
39
15 MHz to
20 MHz
10
< 80
18
18
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TDA8295
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Digital global standard low IF demodulator for analog TV and FM radio
Table 69.
Crystal parameters together with external components …continued
Fundamental
oscillation
frequency
Crystal load
capacitance
CL(xtal) (pF)
Crystal series
resistance
Rs(xtal) (Ω)
External load capacitors
C1 (pF)
C2 (pF)
10 MHz to
15 MHz
10
< 200
18
18
20
< 120
39
39
15 MHz to
20 MHz
10
< 180
18
18
20
< 100
39
39
20 MHz to
25 MHz
10
< 160
18
18
20
< 80
39
39
25 MHz to
30 MHz
10
< 130
18
18
20
< 60
39
39
30 MHz to
35 MHz
10
< 120
18
18
35 MHz to
40 MHz
10
< 100
18
18
40 MHz to
45 MHz
10
< 80
18
18
45 MHz to
50 MHz
10
< 60
18
18
Bit HF = 1
14. Test information
14.1 Boundary scan interface (“IEEE Std. 1149.1”)
The TDA8295 implements a boundary scan architecture to allow access to, and control of,
board test support features within integrated circuits through a TAP. The TAP controller is
a synchronous state machine that controls the sequence of operations on the TAP
circuitry when the TMS signal changes. All state transitions occur on the basis of the TMS
value on the rising edge of TCK. The instruction register is a shift register based design. It
decodes the test to be performed and/or the test data register to be accessed. The
instructions are shifted into the register through the TDI and are latched as the current
instruction at the completion of the shifting process. The TDA8295 boundary scan
architecture includes: a TAP controller, a scannable instruction register and three
scannable test data registers: a boundary scan register, a device ID register, and a bypass
register.
The supported instructions are: EXTEST, IDCODE, SAMPLE, INTEST, CLAMP, HIGHZ
and BYPASS.
The boundary scan register is composed of 16 cells (see Table 70). Each cell is
associated either to an input pad, an output pad, a bidirectional pad or to the bidirectional
or 3-state command itself. All cells are of ‘observe and control’ type.
The device ID register is a 32-bit identification register that is included in the scan register
itself and contains the ID number. It is a fixed value that identifies the chip.
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TDA8295
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Digital global standard low IF demodulator for analog TV and FM radio
ID number structure is:
ID version [3:0] = 1h
ID part number [15:0] = 224Ch
ID manufacturer [11:1] = 015h
ID mandatory [0] = 1h
IDCODE [31:0] = 1224 C02Bh
When the boundary scan function is not used, please connect the four dedicated input
pins (TRST_N, TCK, TDI and TMS) to GND.
BOUNDARY
SCAN
REGISTER
DEVICE ID
REGISTER
MUX
BYPASS
REGISTER
control
MUX
FF
TDO
INSTRUCTION
DECODE
TDI
INSTRUCTION
REGISTER
TMS
TCK
TRST_N
TEST
ACCESS
PORT
CONTROLLER
select
3-state enable
001aac078
Fig 16. Boundary scan block diagram
TDA8295_1
Product data sheet
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Rev. 01 — 4 February 2008
69 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 70.
Boundary scan register list
Pad signal
Chain position
Pad type
Scan type
Control signal
IF_AGC
[1]
Bidir
control/observe
U1.vagc_cmd
[2]
Ctrl
control/observe
U1.vagc_cmd
[3]
Bidir
control/observe
U1.gpio0_cmd
[4]
Ctrl
control/observe
U1.gpio0_cmd
[5]
Bidir
control/observe
U1.gpio1_cmd
[6]
Ctrl
control/observe
U1.gpio1_cmd
[7]
Bidir
control/observe
U1.gpio2_cmd
[8]
Ctrl
control/observe
U1.gpio2_cmd
[9]
Bidir
control/observe
U1.sda_cmd
GPIO0
GPIO1
GPIO2
SDA
[10]
Ctrl
control/observe
U1.sda_cmd
SCL
[11]
input
control/observe
-
RST_N
[12]
input
control/observe
-
SADDR1
[13]
Ctrl
control/observe
U1.saddr1_cmd
[14]
Bidir
control/observe
U1.saddr1_cmd
[15]
Ctrl
control/observe
U0.saddr1_cmd
[16]
Bidir
control/observe
U0.saddr1_cmd
SADDR0
Table 71.
Boundary scan electrical characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tcy
cycle time
TCK
25
-
-
ns
tsu
set-up time
TDI and TMS
0
-
-
ns
th
hold time
TDI and TMS
4
-
-
ns
td(TDO)
delay time on pin TDO
on 50 pF
-
-
12
ns
Tcy
TCK
tsu
th
TDI, TMS
td
TDO
001aac079
Fig 17. Boundary scan timing diagram
TDA8295_1
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TDA8295
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Digital global standard low IF demodulator for analog TV and FM radio
15. Package outline
HVQFN40: plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6 x 6 x 0.85 mm
A
B
D
SOT618-1
terminal 1
index area
A
E
A1
c
detail X
C
e1
1/2 e
e
20
y
y1 C
v M C A B
w M C
b
11
L
21
10
e
e2
Eh
1/2 e
1
30
terminal 1
index area
40
31
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D(1)
Dh
E(1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
6.1
5.9
4.25
3.95
6.1
5.9
4.25
3.95
0.5
4.5
4.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT618-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
01-08-08
02-10-22
Fig 18. Package outline SOT618-1 (HVQFN40)
TDA8295_1
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Rev. 01 — 4 February 2008
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TDA8295
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Digital global standard low IF demodulator for analog TV and FM radio
16. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus PbSn soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
TDA8295_1
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Rev. 01 — 4 February 2008
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 19) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 72 and 73
Table 72.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 73.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 19.
TDA8295_1
Product data sheet
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73 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 19. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
17. Abbreviations
Table 74.
Abbreviations
Acronym
Description
ADC
Analog-to-Digital Converter
AFC
Automatic Frequency Control
AGC
Automatic Gain Control
CC
Color Carrier
CMOS
Complementary Metal-Oxide Semiconductor
CORDIC
COordinate Rotation DIgital Computer
CVBS
Color Video Blanking Signal
DAC
Digital-to-Analog Converter
DTO
Digitally Tuned Oscillator
DVD
Digital Versatile Disc
FIR
Finite Impulse Response
FLL
Frequency-Locked Loop
FPLL
Frequency Phase-Locked Loop
FS
Full Scale
GPIO
General Purpose Input Output
H/V
Horizontal and Vertical
HAD
Half Amplitude Duration
IC
Integrated Circuit
ICFM
Incidental Carrier Frequency Modulation
TDA8295_1
Product data sheet
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Rev. 01 — 4 February 2008
74 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 74.
Abbreviations …continued
Acronym
Description
ICPM
Incidental Carrier Phase Modulation
ID
IDentification
IF
Intermediate Frequency
NPC
Neighbor Picture Carrier
NSC
Neighbor Sound Carrier
PC
Picture Carrier
PCB
Printed-Circuit Board
PLL
Phase-Locked Loop
PWM
Pulse Width Modulation
QSS
Quasi Split Sound
SAW
Surface Acoustic Wave
SC
Sound Carrier
SMD
Surface Mounted Device
SSIF
Second Sound Intermediate Frequency
STB
Set-Top Box
TAP
Test Access Port
VCR
Video Cassette Recorder
VITS
Vertical Interval Test Signal
18. Revision history
Table 75.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
TDA8295_1
20080204
Product data sheet
-
-
TDA8295_1
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Rev. 01 — 4 February 2008
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
19.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
Silicon Tuner — is a trademark of NXP B.V.
20. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
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Rev. 01 — 4 February 2008
76 of 77
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
21. Contents
1
2
3
4
5
6
7
7.1
7.2
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
9
9.1
9.1.1
9.1.2
9.2
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
9.3.9
9.3.10
9.3.11
9.3.12
9.3.13
9.3.14
9.3.15
9.3.16
9.3.17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 3
Ordering information . . . . . . . . . . . . . . . . . . . . . 5
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 6
Pinning information . . . . . . . . . . . . . . . . . . . . . . 7
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional description . . . . . . . . . . . . . . . . . . 10
IF ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PLL demodulator . . . . . . . . . . . . . . . . . . . . . . 10
Nyquist filter, video low-pass filter, video
and group delay equalizer, video leveling . . . . 10
Upsampler and video DAC . . . . . . . . . . . . . . . 11
SSIF/mono sound processing. . . . . . . . . . . . . 11
Tuner IF AGC . . . . . . . . . . . . . . . . . . . . . . . . . 11
Digital IF AGC. . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock generation. . . . . . . . . . . . . . . . . . . . . . . 12
2
I C-bus control . . . . . . . . . . . . . . . . . . . . . . . . . 12
Protocol of the I2C-bus serial interface . . . . . . 12
Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Register overview . . . . . . . . . . . . . . . . . . . . . . 15
Register description . . . . . . . . . . . . . . . . . . . . 20
Standard setting with easy programming . . . . 20
Diverse functions (includes tuner IF AGC
Pin mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
ADC headroom . . . . . . . . . . . . . . . . . . . . . . . . 23
Picture carrier PLL functions . . . . . . . . . . . . . 24
Picture and sound carrier DTO . . . . . . . . . . . . 27
Filter settings . . . . . . . . . . . . . . . . . . . . . . . . . 28
Group delay equalization . . . . . . . . . . . . . . . . 30
Digital IF AGC functions . . . . . . . . . . . . . . . . . 31
Tuner IF AGC functions . . . . . . . . . . . . . . . . . 33
V-sync adjustment . . . . . . . . . . . . . . . . . . . . . 34
CVBS settings. . . . . . . . . . . . . . . . . . . . . . . . . 35
SSIF and mono sound settings. . . . . . . . . . . . 37
Status registers: ADC saturation, AFC,
H/V PLL and AGC. . . . . . . . . . . . . . . . . . . . . . 39
Debug register for ADC and DAC test . . . . . . 41
Chip identification and Standby mode . . . . . . 41
Status of clock PLL and video/sound DAC
load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
ADC control . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.3.18
9.3.19
9.3.20
10
11
12
13
13.1
13.2
13.3
13.4
13.5
13.5.1
13.5.2
13.6
13.7
14
14.1
15
16
16.1
16.2
16.3
16.4
17
18
19
19.1
19.2
19.3
19.4
20
21
Video and sound DAC control . . . . . . . . . . . .
Clock generation (PLL and crystal oscillator).
GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Thermal characteristics . . . . . . . . . . . . . . . . .
Characteristics . . . . . . . . . . . . . . . . . . . . . . . .
Application information . . . . . . . . . . . . . . . . .
Typical application . . . . . . . . . . . . . . . . . . . . .
Detailed application diagram . . . . . . . . . . . . .
DAC connection . . . . . . . . . . . . . . . . . . . . . . .
ADC connection . . . . . . . . . . . . . . . . . . . . . . .
Reset operation . . . . . . . . . . . . . . . . . . . . . . .
Hardware reset. . . . . . . . . . . . . . . . . . . . . . . .
Software reset . . . . . . . . . . . . . . . . . . . . . . . .
Application hints . . . . . . . . . . . . . . . . . . . . . . .
Crystal connection . . . . . . . . . . . . . . . . . . . . .
Test information. . . . . . . . . . . . . . . . . . . . . . . .
Boundary scan interface (“IEEE Std. 1149.1”)
Package outline . . . . . . . . . . . . . . . . . . . . . . . .
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering . . . . . . . . . . . . . . .
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
46
49
51
51
52
63
63
64
65
65
66
66
66
66
67
68
68
71
72
72
72
72
73
74
75
76
76
76
76
76
76
77
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 4 February 2008
Document identifier: TDA8295_1