SPIF215A
USB to Serial-ATA Bridge
Preliminary
APR. 26, 2006
Version 1.1
Sunplus Technology reserves the right to change this documentation without prior notice. Information provided by Sunplus Technology is believed to be
accurate and reliable.
However, Sunplus Technology makes no warranty for any errors which may appear in this document. Contact Sunplus Technology to
obtain the latest version of device specifications before placing your order.
No responsibility is assumed by Sunplus Technology for any infringement of patent
or other rights of third parties which may result from its use. In addition, Sunplus products are not authorized for use as critical components in life support
devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the
user, without the express written approval of Sunplus.
SPIF215A
Table of Contents
PAGE
1. GENERAL DESCRIPTION .......................................................................................................................................................................... 3
2. FEATURES.................................................................................................................................................................................................. 3
2.1. OVERALL FEATURE ................................................................................................................................................................................ 3
2.2. USB FEATURES ..................................................................................................................................................................................... 3
2.3. SERIAL-ATA FEATURES .......................................................................................................................................................................... 3
2.4. APPLICATION EXAMPLES ........................................................................................................................................................................ 3
3. REFERENCES ............................................................................................................................................................................................ 3
4. BLOCK DIAGRAM ...................................................................................................................................................................................... 4
5. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 5
5.1. PIN DESCRIPTIONS ................................................................................................................................................................................ 5
5.2. PIN DIAGRAM......................................................................................................................................................................................... 5
5.3. PIN LISTING ........................................................................................................................................................................................... 6
6. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 8
6.1. POWER MANAGEMENT ........................................................................................................................................................................... 8
6.1.1. USB Suspend Power Management Mode ................................................................................................................................ 8
6.1.2. SATA Partial Power Management Mode ................................................................................................................................... 8
6.1.3. SATA Slumber Power Management Mode................................................................................................................................ 8
6.2. HOT-PLUG SUPPORT ............................................................................................................................................................................. 8
6.2.1. USB Hot-Plug Support .............................................................................................................................................................. 8
6.2.2. SATA Hot-Plug Support............................................................................................................................................................. 9
6.2.3. SPIF215A Hot-Plug Support ..................................................................................................................................................... 9
6.3. POWER-ON RESET ................................................................................................................................................................................. 9
7. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 10
7.1. POWER REQUIREMENT ........................................................................................................................................................................ 10
7.2. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 10
7.3. RECOMMENDED/TYPICAL OPERATING CONDITIONS ............................................................................................................................... 10
7.4. DC CHARACTERISTICS ......................................................................................................................................................................... 10
7.5. USB INTERFACE DC CHARACTERISTICS ................................................................................................................................................11
7.6. USB INTERFACE TIMING SPECIFICATION ............................................................................................................................................... 12
7.7. USB REFERENCE CLOCK INPUT REQUIREMENTS .................................................................................................................................. 12
7.8. SATA INTERFACE DC CHARACTERISTICS .............................................................................................................................................. 12
7.9. SATA INTERFACE TIMING SPECIFICATION .............................................................................................................................................. 13
7.10. SATA REFERENCE CLOCK INPUT REQUIREMENTS ................................................................................................................................. 14
8. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 15
8.1. PACKAGE INFORMATION ....................................................................................................................................................................... 15
8.1.1. 64 pin TQFP............................................................................................................................................................................ 15
8.2. ORDERING INFORMATION ..................................................................................................................................................................... 17
8.3. STORAGE CONDITION AND PERIOD FOR PACKAGE ................................................................................................................................. 17
8.4. RECOMMENDED SMT TEMPERATURE PROFILE...................................................................................................................................... 17
9. DISCLAIMER............................................................................................................................................................................................. 18
10. REVISION HISTORY ................................................................................................................................................................................. 19
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SPIF215A
USB 2.0 TO SERIAL-ATA HOST BRIDGE
1.GENERAL DESCRIPTION
The Sunplus SPIF215A is a single-chip solution for USB to
2.2. USB Features
Serial-ATA(SATA) host bridge. It has a USB high-speed device
„ Compliant with USB 2.0 specifications and pass USB
port and a SATA 1.5G host port. It received standard Mass
certification.
Storage Device Class (MSDC) SCSI command from USB host and
„ Support USB high speed (480Mbps) and full speed transfer
translate into ATA/ATAPI command to SATA device. The maximum
rate (12Mbps).
throughput can goes up to 30MB/sec.
„ Support Mass Storage Device Class bulk only transfer.
„ Support USB vendor command (Control Endpoint) and SCSI
vendor command.
2.FEATURES
„ Support USB host controller for UHCI, OHCI, EHCI mode.
SPIF215A has many special features that can provide our
customers to make their end products unique.
2.3. Serial-ATA Features
„ Compliant with Serial-ATA 1.0A specifications
2.1. Overall Feature
„ Support Serial-ATA generation 1 transfer rate of 1.5Gb/s
„ Fabricated in 0.18um CMOS process with 1.8v core and 3.3v
„ Support spread spectrum in receiver
I/Os.
„ Support Serial-ATA power saving mode: Partial and Slumber
„ Peak data transfer throughput at 30MB/sec.
mode.
„ Available in 64-pin TQFP package with e-Pad.
1
„ Support PIO, MDMA and UDMA mode data transfer.
„ Embedded Memory, USB PHY and SATA PHY have isolated
BIST.
2.4. Application Examples
„ Full scan for high production test coverage
„
USB External HDD, Enclosures, Mobil Rack
„ Support General purpose I/O feature.
„ Support HDD security feature.
„ Support ATA pass through command feature.
2
3. REFERENCES
„ Pass Microsoft™ WHQL certification.
For more details information about USB and SATA technology,
„ Support Window 98/ME/2K/XP, Linux , Mac 10 OS platform
please refer to the following industry specifications:
„ Serial-ATA
/
High
Speed
Serialized
ATA
Attachment
specification, Revision 1.0A.
„ Universal Serial Bus Specification Revision 2.0.
1
For e-Pad of SPIF215A, please always connect e-Pad to the
ground of application board.
2
Please check with your agent to get all application or design
document.
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4. BLOCK DIAGRAM
Fig 4-1: SPIF215A Functional Blocks Diagram
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SPIF215A
5.SIGNAL DESCRIPTIONS
5.1. Pin Descriptions
Table 5-1: Pin Types
Pin Type
Pin Description
I/O
Bi-directional Pin
I
Input Pin
O
Output Pin
T
Tri-state Output Pin
A
Analog pin
USB
USB D+ D-
SATA
SATA TX+ TX- RX+ RX-
5.2. Pin Diagram
The SPIF215A pin diagram is showed in Figure 5-1.
Figure 5-1 SPIF215A Pin Diagram
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SPIF215A
5.3. Pin Listing
Table 5-2: SPIF215A Pin Listing
Pin
Pin Name
Type
Pin Description
1
DVSS
GND
Digital Ground
2
D3V3
PWR
Digital 3.3V Power
3
UD1V8
PWR
USB Digital 1.8V Power
4
UDVSS
GND
USB Digital Ground
5
UXI
I
USB Crystal Oscillator Input / External Clock Input
6
UXO
O
USB Crystal Oscillator Output
7
UD3V3
PWR
USB Crystal 3.3V Power
8
UREXT
A
USB External Resistor 12Kohm
9
A3V3RX
GND
USB Analog Ground for PHY RX
10
AVSSRX
PWR
USB Analog Power for PHY RX
11
NC
USB
No connection
12
DM
USB
USB High Speed D-
13
DP
USB
USB High Speed D+
14
NC
USB
No connection
15
A3V3TX
PWR
USB Analog power for PHY TX
16
AVSSTX
GND
USB Analog Ground for PHY TX
17
GPIO 9
I/O
General purpose I/O
18
GPIO 8
I/O
General purpose I/O
19
GPIO 3
I/O
General purpose I/O
20
D3V3
21
DVSS
GND
Digital Ground
22
D1V8
PWR
Digital 1.8V Power
23
EXTM_WEN
PWR
Digital 3.3V Power
O
External Memory Write Enable
24
EXTM_REN
O
External Memory Read Enable
25
GPIO 2
I/O
General purpose I/O
26
GPIO 1
I/O
General purpose I/O
27
GPIO 0
I/O
28
PM_EXTERN
I
External PM
29
TEST_MD3
I
Test Mode Selection Bit 3
30
TEST_MD2
I
Test Mode Selection Bit 2
31
TEST_MD1
I
Test Mode Selection Bit 1
32
TEST_MD0
I
Test Mode Selection Bit 0
33
D3V3
PWR
34
DVSS
GND
35
SXI
I
SATA Crystal Oscillator Input / External Clock Input
36
SXO
O
SATA Crystal Oscillator Output
37
A1V8
PWR
SATA 1.8V Analog Power
38
AVSS
GND
SATA Analog Ground
39
SREXT
A
General purpose I/O
Digital 3.3V Power
Digital Ground
SATA External Reference Resistor Input
40
RXP
SATA
SATA Differential Receive +ve
41
RXN
SATA
SATA Differential Receive –ve
42
A1V8
PWR
SATA 1.8V Analog Power
43
AVSS
GND
SATA Analog Ground
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SPIF215A
Pin
Pin Name
Type
Pin Description
44
TXN
SATA
SATA Differential Transmit –ve
45
TXP
SATA
SATA Differential Transmit +ve
46
OLED
T
47
D3V3
PWR
Digital 3.3V Power
48
DVSS
GND
Digital Ground
HDD active LED output
49
RESET_B
I
Low Active Reset
50
EXTM_ALE
O
External Memory Address Latch Enable
51
I2C_SCL
I/O
I2C Clock
52
I2C_SDA
I/O
I2C Data
53
UART_TX
O
8051 UART TX
54
GPIO4
I/O
General purpose I/O
55
GPIO 5
I/O
General purpose I/O
56
GPIO 6
I/O
General purpose I/O
57
GPIO 7
I/O
General purpose I/O
58
D1V8
PWR
Digital 1.8V Power
59
DVSS
GND
Digital Ground
60
D3V3
PWR
Digital 3.3V Power
61
Reserve
Reserve
62
Reserve
Reserve
63
Reserve
Reserve
64
USB_VBUS
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USB VBUS
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6.FUNCTIONAL DESCRIPTIONS
6.1. Power Management
SPIF215A support both USB and SATA power management
mechanism.
Partial mode status is reported in both the SStatus register (‘0010’
in the IPM field) and the SMisc register (bit 4).
If SATA device initial a partial/slumber request, SPIF215A will
decide whether accept or not depend on current USB status. If
Partial mode is cleared by setting the ComWake bit in the Smisc
USB host is not access SATA device, SPIF215A might let SATA
register. This will send a COMWAKE signal to the device through
device goes into partial/slumber mode and stop its SATA
the Serial ATA link to initiate a Partial to On sequence. Partial
connection.
mode can also be cleared through receipt of OOB signals from the
device.
If USB host try to access SATA device when SATA device is power
down, SPIF215A will issue a comm reset OOB signal to wake up
6.1.3. SATA Slumber Power Management Mode
device and re-establish the SATA connection.
Slumber mode may be initiated by software through the SMisc
register (bit 1). By setting the bit, software causes PMREQ_S
If
USB
host
suspend
SPIF215A,
SPIF215A
will
send
primitives to be sent to the Serial ATA device, which will respond
partial/slumber request to power down SATA device before goes
with either a PMACK or PMNAK. If a PMACK is received the
into suspend. SPIF215A will also wait up SATA device when it is
Slumber mode is entered. A PMNAK is ignored; the request
wake up by the USB host.
remains asserted.
6.1.1. USB Suspend Power Management Mode
The Serial ATA device may initiate slumber mode. This is indicated
USB host will periodically sending SOF packet in constant timing
by the reception of PMREQ_S primitives. Software enables the
interval. If device haven’t received any USB bus activity for more
acknowledgement of this request by setting the IPM value in the
than 3ms, it will have to try to pull up D+ through 1.5K Ohm
SControl register to ‘001x’. If enabled, a PMACK will be sent to the
resistor to detect whether host want to reset or suspend the device.
device; if not enabled, a PMNAK will be sent. When the request is
If suspend, device will have to power down as much logic as
received and its acknowledgement is enabled, Slumber mode is
possible because device must not consume more than 500µA
entered.
from VBUS during suspend.
When host try to wake up device drive a Resume-K (DM high, DP
Slumber mode status is reported in both the SStatus register
low) to wake up device. If device try to initialize the connection, it
(‘0110’ in the IPM field) and the SMisc register (bit 5).
will also drive a Resume-K to host.
Slumber mode is cleared by setting the ComWake bit in the Smisc
6.1.2. SATA Partial Power Management Mode
register. This will send a COMWAKE signal to the device through
Partial mode may be initiated by software through the SMisc
the Serial ATA link to initiate a Slumber to On sequence. Slumber
register (bit 0). By setting the bit, the software causes PMREQ_P
mode can also be cleared through receipt of OOB signals from the
primitives (Power Management REQuest – Partial) to be sent to
device.
the Serial ATA device, which will respond with either a PMACK or
PMNAK. If a PMACK is received the Partial mode is entered; A
6.2. Hot-Plug Support
PMNAK is ignored; the request remains asserted.
SPIF215A support both SATA and USB hot-plug feature.
The Serial ATA device may initiate partial mode. This is indicated
6.2.1. USB Hot-Plug Support
by the reception of PMREQ_P primitives from the device.
USB device uses VBUS status to detect if it is plug into a host.
Software enables the acknowledgement of this request by setting
When it does, it will raise it D+ and host will detect device present
the IPM value in the SControl register to ‘00x1’ If enabled, a
and start building up communication channel. Device also uses
PMACK will be sent to the device; if not enabled, a PMNAK will be
VBUS falling to detect if it has been unplug from host and will
sent. When the request is received and its acknowledgement is
reset all its status to wait for another plug-in action.
enabled, Partial mode is entered.
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For full-speed device, it will raise pull up resistor at D+ to create
For high-speed device, host will keep sending SOF packet in idle
an IDLE-J situation. If the device is unplugged or want to create
situation. Because both host and device has 45ohm pull down
software disconnect situation by take out pull up resistor, host will
termination resistor, the voltage level is normal. If device
detect D+D- is changing from IDLE-J to SE0 and recognize as
unplugged or want to create software disconnect situation by take
device unplugged.
out its pull down resistor, the voltage level is twice as normal
voltage because equivalent resistor is increased.
Device detect host method
Host detect device method
VBUS rise
host
absent
D+ rise
host
present
speed emulation pass
full speed
device
present
device
absent
D+ fall during idle
VBUS fall
high speed
device
present
SOF voltage level too large
(termination resistor at
device disappear)
Fig 6-1: USB Hot Plug Mechanism
6.2.2. SATA Hot-Plug Support
SATA use differential signal squelch level to detect if host/device is
If any site is unplug or create a software disconnect situation by
present. Host will keep sending (can be disable to reduce power
stop it transmitter from sending differential signal, the other site
consumption) OOB signal to let device detect its present. If a
will sense the differential signal disappear and know the other site
device received host OOB signal, it will also return OOB signal to
is unplugged.
let host detect its present and communication channel is
established.
Host detect device method
Device detect host method
RX differential signal show
OOB of comm reset
host
absent
Periodically TX OOB comm reset signal
until received comm init from RX
host
present
device
absent
RX differential
signal disappear
device
present
RX differential
signal disappear
Fig 6-2: SATA Hot Plug Mechanism
6.2.3. SPIF215A Hot-Plug Support
later, SPIF216 will restart its USB connection procedure and users
SPIF216A can perform software USB disconnect function by
will see a new USB device plugged in. If SATA device is suddenly
taking out 45ohm termination in high speed or taking out 1.5K pull
unplugged,
SPIF216A
will
also
perform
USB
software
disconnection to show users an USB device is unplugged.
up resistor on DP in full speed. All SATA device connection status
will all reflect on USB site. For example, if SPIF216A is plugged
into USB host without SATA device connection. SPIF216 will
6.3. Power-on reset
perform USB software disconnection and users will not see any
SPIF215A has embedded a power on reset circuit.
USB device plugged in information. If SATA device is plugged in
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7.ELECTRICAL SPECIFICATIONS
7.1. Power Requirement
7-1: Total Power Dissipation (Typical corner, TA =25℃)
Symbol
IIO
Parameter
Limits
Condition
Absolute digital I/O pad power supply
Unit
Min.
Typ.
Max.
3.3V
1.0
4.5
6.0
mA
ICORE
Absolute digital core power supply
1.8V
8-
18
25
mA
IAUSB
Absolute analog power supply for USB PHY
3.3V
0
25-
30
mA
IASATA
Absolute analog power supply for SATA PHY
1.8V
64-
68
80
mA
Note: Max total power < 432mW
7.2. Absolute Maximum Ratings
Table 7-2: Absolute Maximum Ratings (Typical corner, 25℃)
Symbol
Limits
Parameter
Unit
Min.
Typ.
Max.
Absolute digital I/O pad power supply voltage
3.0
3.3
3.6
VCORE
Absolute digital power supply
1.62
1.8
1.98
V
VAUSB
Absolute analog power supply voltage for USB PHY
3.0
3.3
3.6
V
VASATA
Absolute analog power supply voltage for SATA PHY
1.62
1.8
1.98
V
Absolute storage temperature
-20
25
105
℃
VIO
TSTR
V
7.3. Recommended/Typical Operating Conditions
Table 7-3: Recommended/Typical Operating Conditions
Symbol
VCORE
VIO
Limits
Parameter
Unit
Min.
Typ.
Max.
Operating digital power supply voltage
1.62
1.8
1.98
V
Operating digital I/O pad
3.0
3.3
3.6
V
supply voltage
VAUSB
Operating analog power supply voltage for USB PHY
3.0
3.3
3.6
V
VASATA
Operating analog power supply voltage for SATA PHY
1.62
1.8
1.98
0
25
70
V
℃
TSTR
Operating temperature
7.4. DC Characteristics
Table 7-4: DC Characteristics
0
(Testing condition: VCORE =1.8V VAUSB, VASATA = 3.3V Ta =25 C, Unless otherwise noted)
Symbol
Parameter
Limits
Condition
Unit
Min.
Typ.
Max.
VIL
Input low voltage
-0.3
-
0.8
V
VIH
Input high voltage
2.0
-
VIO+0.3
V
VTH
Threshold point
1.45
1.59
1.77
V
VT
Schmitt trig. Low to High threshold point
1.47
1.50
1.50
V
Schmitt trig. high to low threshold point
0.90
0.94
0.96
V
+
VT
-
II
IOZ
Input leakage current
VI=5.5V or 0V
-
-
±10
µA
Tri-state output leakage current
VO=5.5V or 0V
-
-
±10
µA
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Symbol
Parameter
Limits
Condition
Unit
Min.
Typ.
Max.
RPU
Pull-up resistor
46
70
114
KΩ
RPD
Pull-down resistor
30
58
129
KΩ
VOL
Output low voltage
IOL (min)
-
-
0.4
V
VOH
Output high voltage
IOH (min)
2.4
-
-
V
IOL
Low level output current
VOL=0.4V
2mA
2.2
3.3
4.2
mA
VOL=0.4V
4mA
4.5
6.6
8.3
mA
VOL=0.4V
8mA
8.9
13.2
16.7
mA
VOL=0.4V
12mA
13.4
19.7
25.0
mA
VOL=0.4V
16mA
17.9
26.3
33.4
mA
VOL=0.4V
24mA
26.8
39.5
50.0
mA
VOL=2.4V
2mA
3.1
6.2
10.1
mA
VOL=2.4V
4mA
6.1
12.4
20.2
mA
VOL=2.4V
8mA
12.3
24.8
40.5
mA
VOL=2.4V
12mA
18.5
37.1
60.8
mA
VOL=2.4V
16mA
24.6
49.5
81.0
mA
VOL=2.4V
24mA
36.9
74.3
121.5
mA
IOH
High level output current
Note: Above information are TSMC standard IO PADs specifications. SPIF215A haven’t decided which type of IOs to be used.
7.5. USB Interface DC Characteristics
Table 7-5: USB DC Characteristics (Typical corner, 25℃)
Symbol
Parameter
Limits
Condition
Min.
Typ.
Unit
Max.
Input Levels for Full-Speed
VIH
Single Ended High (driven)
2.0
-
V
VIHZ
Single Ended High (floating)
2.7
-
3.6
V
VIL
Single Ended Low
-
-
0.8
V
VDI
Differential input | (D+) - (D-) | sensitivity
0.2
-
-
V
VCM
Differential common mode range
0.8
-
2.5
V
Input Levels for High-Speed
VHSSQ
HS differential squelch threshold
100
-
150
mV
VHSDSC
HS differential disconnect threshold
525
-
625
mV
VHSCM
HS data common mode voltage range
-50
-
500
mV
Output Levels for Full-Speed
VOL
Low
0.0
-
0.3
V
VOH
High
2.8
-
3.6
V
VOSE1
SE1
0.8
-
-
V
VCRS
Signal crossover voltage
1.3
-
2.0
V
Output Levels for High-Speed
VHSOI
HS Idle level
-10
-
10
mV
VHSOH
HS data signaling high
360
-
440
mV
VHSOL
HS data signaling low
-10
-
10
mV
VCHIRPJ
Chirp J level (differential voltage)
700
-
1100
mV
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SPIF215A
Symbol
VCHIRPK
Parameter
Limits
Condition
Chirp K level (differential voltage)
Unit
Min.
Typ.
Max.
-900
-
-500
mV
Note: Above information same as USB specification Rev.2.0 Chapter 7.3.2
7.6. USB Interface Timing Specification
0
Table 7-6: USB Electrical Characteristics (Typical corner, 3.3V/1.8V, 25 )
Symbol
Parameter
Limits
Condition
Unit
Min.
Typ.
Max.
Full Speed Driver Characteristics
TFR
Rise time
4.0
-
20
ns
TFF
Fall time
4.0
-
20
ns
Differential rise fall time matching
90
-
111.11
%
11.994
-
12.006
Mbps
TFRFM
TFDRATHS
Full
Speed
data
rate
(HS
capable)
High Speed Driver Characteristics
THSR
Rise time
500
-
-
ps
THSF
Fall time
500
-
-
ps
479.760
-
480.240
Mbps
THSDRAT
High Speed data rate
Note: Above information same as USB specification Rev.2.0 Chapter 7.3.2
7.7. USB Reference Clock Input Requirements
Table 7-7: USB Reference Clock Input Requirements (Typical corner, 3.3V/1.8V, 25℃)
Symbol
Parameter
RUEXT
REXT
FUREF
REFCLK frequency
Limits
Condition
Unit
Min.
Typ.
Max.
-
12.47
-
Kohm
12MHz
-500
-
+500
ppm
TUREFRF
REFCLK rise and fall time
20% ~ 80%
-
-
4.0
ns
TUREFD
REFCLK duty cycle
20% ~ 80%
40
-
60
%
7.8. SATA Interface DC Characteristics
Table 7-8: SATA DC Characteristics (Typical corner, 1.8V, 25℃)
Symbol
Parameter
Limits
Condition
Unit
Min.
Typ.
Max.
VCM,DD
Common mode voltage
DC to DC
200
250
450
mV
VCM,AD
Common mode voltage
AC to DC
0
-
2.0
mV
VCM,DA
Common mode voltage
DC to AC
0
-
2.0
mV
Vdiff,tx
TX+/TX- differential peak-to-peak
400
500
600
mVp-p
325
400
600
mVp-p
50
100
200
mVp-p
voltage swing
Vdiff,rx
RX+/RX- differential peak-to-peak
voltage swing
Vsqth
Squelch
differential
detector
threshold
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SPIF215A
Symbol
Zdiff,tx
Parameter
TX differential pair impedance
Limits
Condition
TDR differential mode
Unit
Min.
Typ.
Max.
85
100
115
Ohm
85
100
115
Ohm
100ps edge 20~80%
Zdiff,rx
RX differential pair impedance
TDR differential mode
100ps edge 20~80%
ZSE,tx
TX single-ended impedance
TDR 100ps edge 20~80%
40
-
-
Ohm
ZSE,rx
RX single-ended impedance
TDR 100ps edge 20~80%
40
-
-
Ohm
-
-
12
nF
CACcoupling
Coupling capacitance for AC
coupled TX and RX pairs
Note: Above information same as SATA specification Rev. 1.0a Chapter 6.6.1
7.9. SATA Interface Timing Specification
Table 7-9: SATA Electrical Characteristics (Typical corner, 1.8V, 25℃)
Symbol
Parameter
Limits
Condition
Min.
Unit
Typ.
Max.
TUI
Unit interval (bit rate)
1.5G +- 350ppm
666.43
-
670.12
ps
Trise
Rise time at transmitter
20% ~ 80%
0.15
0.3
0.41
UI
Tfall
Fall time at transmitter
20% ~ 80%
0.15
0.3
0.41
UI
Tskew
Differential skew at transmitter
-
-
20
ps
Fskew,DC
Tx DC clock frequency skew
-350
-
+350
ppm
-5000
-
+0
ppm
304
320
336
ns
175
-
525
ns
101.3
106.7
112
ns
55
-
175
ns
Exclude 0~5000ppm
SSC down spread AC
modulation
Fskew,AC
Tcomreset,H
Tx AC clock frequency skew
COMRESET/COMINIT detector
ON
threshold spacing
Tcomreset,L
COMRESET/COMINIT detector
OFF
threshold spacing
Tcomwake,H
COMWAKE detector ON
threshold spacing
Tcomwake,L
COMWAKE detector OFF
threshold spacing
Tcomwake,S
COMWAKE transmit spacing
103.5
106.7
109.9
ns
UIOOB
OOB data period
646.67
-
686.67
ps
Note: Above information same as SATA specification Rev. 1.0a Chapter 6.6.1
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SPIF215A
7.10. SATA Reference Clock Input Requirements
Table 7-10: CLKI Reference Clock Input Requirements (Typical corner, 1.8V, 25℃)
Symbol
Parameter
Limits
Condition
RSEXT
Nominal frequency
FSREF
CLKI frequency tolerance
TSREFRF
Rise and fall time at CLKI
25MHz reference clock, 20% ~ 80%
TSREFD
CLKI duty cycle
20% ~ 80%
© Sunplus Technology Co., Ltd.
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REXT = 1k 1%
14
Unit
Min.
Typ.
Max.
-
25
-
Ohm
-350
-
+350
ppm
-
-
4.0
ns
40
-
60
%
APR. 26, 2006
Version: 1.1
SPIF215A
8.PACKAGE/PAD LOCATIONS
8.1. Package Information
8.1.1. 64 pin TQFP
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SPIF215A
Fig 8-1: SPIF215A in TQFP-64 package
◎E-Pad dimension could be changed without notice.
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SPIF215A
8.2. Ordering Information
Product Number
Package Type
SPIF215A - HF021
Green Package form – TQFP 64*
8.3. Storage Condition and Period for Package
Package
Moisture sensitivity level
Max. Reflow temperature
Floor life storage condition
Dry pack
TQFP
LEVEL 3
255 +5/-0℃
168Hrs @ ≦30℃/ 60% R.H.
Yes
Note1: Please refer to IPC/JEDEC standard J-STD-020A and EIA JEDEC stand JFSD22-A112
Note2: or refer to the “CAUTION Note” on dry pack bag.
8.4. Recommended SMT Temperature Profile
This “Recommended” temperature profile is a rough guideline for
PPF(Pre-Plated Frame) product with 63/37 solder paste, we
SMT process reference. Most of SUNPLUS leadframe base
recommend 240℃~245℃ for peak temperature.
product choice Matte Tin and Sn/Bi for plating recipe. For
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SPIF215A
9.DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of
sale only.
SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or
regarding the freedom of the described chip(s) from patent infringement.
MERCHANTABILITY OR FITNESS FOR ANY PURPOSE.
prices at any time without notice.
FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF
SUNPLUS reserves the right to halt production or alter the specifications and
Accordingly, the reader is cautioned to verify that the data sheets and other information in this
publication are current before placing orders.
Products described herein are intended for use in normal commercial applications.
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are
specifically not recommended without additional processing by SUNPLUS for such applications.
Please note that application circuits
illustrated in this document are for reference purposes only.
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SPIF215A
10. REVISION HISTORY
Date
Revision #
APR. 26, 2006
1.1
Description
1. Update SPIF215A pin description.
Page
21
2. Correct 1.8V tolerance from 5% to 10%.
3. Correct operation temperature.
JUN. 21, 2005
1.0
Product Release,
15
1. Add some AC and DC specification.
2. Add and modify USB DC timing specification.
3. Change package information.
16 - 19
4. Correct the pin description.
MAY. 17, 2005
0.3
1. Modify Pin8 description from 12.47K to 12K
6
2. Remove the original 5.3 section because SPIF215A don’t support GPIO feature.
3. Correct Pin assignment error on Pin 15 and Pin16.
JAN. 24, 2005
0.2
1. Modify Pin assignment; Remove all register information, Program interface, and Modify
text error.
2. Modify 8. PACKAGE/PAD LOCATIONS
AUG. 31, 2004
0.1
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Original
16 - 17
24
19
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Mipaper at www.lcis.com.tw
Mipaper at www.lcis.com.tw