Avnet, Xilinx® ATCA PICMG Design Kit

Avnet, Xilinx® ATCA PICMG Design Kit
ATCA Test Procedure Description
This memo outlines the details of the functional test platform developed for the Xilinx
ATCA card and provides a proposed test procedure. A single FPGA configuration has
been developed to test the vast majority of the interfaces on the ATCA card. The only
exception is the Ethernet port, which is tested using an adapted MultiBERT design. The
testing first involves verification of the power circuitry, testing the impedance for shorts
to ground, then powering the board and verifying the proper voltage levels. Then the test
platform is loaded to test the various interfaces on the board, with test status being
displayed on a PC terminal. Finally, the MultiBERT platform is used to complete the
testing by verifying the Ethernet interface.
The entire test is approximately 6 minutes long. Much of this time is spent in the memory
test, which is quite thorough and therefore takes most of the test time to complete.
Test Environment
The testing requires the functional test ATCA chassis populated with the fabric loopback
boards in connector P23 of slots 2 through 5. The ATCA card under test is placed in slot
1, with a PC connected to the serial connector, J1, for a terminal and the Ethernet port
connected to the PC using a crossover cable. The serial communication link uses 9600
baud with 1 start and 1stop bit, no parity or handshaking.
Copyright © 2004 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. AVNET AVENUE and AVNET AVENUE & Design are trademarks of Avnet, Inc.
All other brands and trademarks are property of their respective owners.
Avnet Design Services
Released
1
Rev 1.0
12/22/2004
Literature # ADS-005000
Test Procedure
The following steps are used for testing the ATCA card:
1. Configure the ATCA card for testing:
• Install JMPR 11, 12, 13, 14, 5, 6
• Short pins 2 and 3 on JMPR 3 and 4 (VTT_MGT)
• Short pins 3 and 4, 7 and 8, 11 and 12, and 15 and 16 on J10 (front panel
Ethernet)
• Short pins 1 and 2 on J12 and J15 (front panel Ethernet LEDs)
• Short pins 1 and 2 on JMPR16 (no PM in JTAG chain)
• Short pins 1 and 2 on JMPR2
• Leave J204 open
• Leave JMPR 7, 8, 9, 10 open
• Short pins 1 and 2 on JMPR15 (BREFCLK = 125MHz)
• Install the Trace & Debug loopback connector on P109
• Copy appropriate image, EDD-003686 -01 for a XC2VP50 or EDD003687-01 for a XC2VP70, to a CompactFlash card and install on the board
• Select SystemAce Configuration 0 (arrow points to SystemAce Reset
button)
2. Verify the impedance and voltage levels of the power supplies
Power Supply
Limits (V)
Min. Max.
Test Point
Impedance
(> 30 Ohms
Y/N)
Voltage
(V)
Pass/Fa
il (P/F)
VCCA_MGT 2.25 2.75
JMPR5
VTT_MGT
1.6
2.0
U12-4
VTTDDR
1.125 1.375
U1001-6
VREF_DDR 1.125 1.375
U1001-14
VCC3V3_BOO 3.0
3.6
U21-5
T
VCC12V
10.8 13.2
JMPR7
VCC2V5
2.25 2.75
JMPR11
VCC1V5
1.35 1.65
JMPR13
VCC5
4.5
5.5
U31-15
Note: Voltage limits have been provided for ±%10.
3. Verify LEDS:
• FPGA Init On (Red)
• FPGA Done On (Blue) after short delay
• SystemAce Status Blinking, then On after short delay (Green)
• SystemAce Error initially Off but Flashing (Red) with the CompactFlash
card ejected
Copyright © 2004 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. AVNET AVENUE and AVNET AVENUE & Design are trademarks of Avnet, Inc.
All other brands and trademarks are property of their respective owners.
Avnet Design Services
Released
2
Rev 1.0
12/22/2004
Literature # ADS-005000
•
Sequence of FPGA controlled LEDs:
- All On
- All Off
- Red On
- Green On
- Amber On
- Blue On
- PLB Error Green
- OPB Error Green
- MGT On (16 one by one)
- Red off
- Green Off
- Amber Off
- Blue Off
- PLB Error Red
- OPB Error Red
- MGT Off (16 one by one)
4. Run the Automated Test Suite:
• After the completion of the LED test, the following tests are completed:
- MGT Test
- IIC Test
- SPI Test
- Memory Test
- Trace & Debug Test
- Hardware Address Test
- BREFCLK Select IO Test
- ATCA Ejector Switch Test
- 12V Enable Test
- SystemAce Test
- SystemAce Configuration Switch Test
- SystemAce Clock Enable Test
5. Press the CPU Reset switch. Ensure that the banner is displayed on the terminal,
the Ethernet PHY LEDS flash (2 Green, 1 Amber), and the front panel Ethernet
RJ45 connector LEDs flash (1 Green, 1 Amber)
6. Press FPGA Prog switch and ensure that FPGA Done LED turns off and the
FPGA Init LED turns on (Red)
Copyright © 2004 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. AVNET AVENUE and AVNET AVENUE & Design are trademarks of Avnet, Inc.
All other brands and trademarks are property of their respective owners.
Avnet Design Services
Released
3
Rev 1.0
12/22/2004
Literature # ADS-005000
7. Ethernet Test
• Select SystemAce Configuration 1
• Press SystemAce Reset switch
• Confirm the successful ping of IP address 192.168.1.1 just prior to the
Linux login prompt in the terminal output.
At the completion of the automated test suite, the user is exited to the PPCBoot Lite
monitor prompt. This can also be accessed at the start of the testing by exiting the test
suite. Typing help at the prompt displays a menu of available commands, which includes
the various tests run by the automated test suite. By using these commands, the user can
run any of the individual tests to aid debugging a failed board, etc.
The CPU Trace & Debug test uses a loopback connector. The connections provided by
this connector and the association to the GPIO core used in the FPGA are detailed in the
following tables.
Mictor Pin #s
21 --> 38
19 --> 36
17 --> 34
15 --> 32
11 --> 30
7 --> 26
6 --> 24 --> 28
Signal Names
CPU_TRST --> TS6
CPU_TDI --> TS5
CPU_TMS --> TS4
CPU_TCK --> TS3
CPU_TDO --> TS2E
CPU_HALT_N --> TS2O
TRC_CLK --> TS1O -->
TS1E
Mictor Connector Loopback Connections
GPIO
Bit #s
0
Mictor
Pin #s
6
Signal
GPIO Mictor
Names
Bit #s Pin #s
TRC_CL
8
38
K
TRC_TS1 9
7
O
TRC_TS2 10
11
O
TRC_TS1 11
19
E
TRC_TS2 12
15
E
TRC_TS3 13
17
TRC_TS4 14
21
TRC_TS5
Mictor Connector to GPIO Mapping
1
24
2
26
3
28
4
30
5
6
7
32
34
36
Signal Names
TRC_TS6
CPU_HALT_
N
CPU_TDO
CPU_TDI
CPU_TCK
CPU_TMS
CPU_TRST
Copyright © 2004 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. AVNET AVENUE and AVNET AVENUE & Design are trademarks of Avnet, Inc.
All other brands and trademarks are property of their respective owners.
Avnet Design Services
Released
4
Rev 1.0
12/22/2004
Literature # ADS-005000
The MGTs are referenced by the test software as channels 0 through 15. The mapping of
these channels to the ATCA designations is detailed in the following table.
MGT Channel
ATCA Designation
0
channel 1 port 0
1
channel 1 port 1
2
channel 1 port 2
3
channel 1 port 3
4
channel 2 port 0
5
channel 2 port 1
6
channel 2 port 2
7
channel 2 port 3
8
channel 3 port 0
9
channel 3 port 1
10
channel 3 port 2
11
channel 3 port 3
12
channel 4 port 0
13
channel 4 port 1
14
channel 4 port 2
15
channel 4 port 3
MGT Channel Mapping
Similarly, the test software references the various IIC Bus devices using the following
names. The mapping of these names to the device reference designators is given below.
IIC Bus Name
Reference
Designator
U251
U255
U20
U252
FPGA Temp Sensor
System Monitor 1
System Monitor 2
Ambient Temperature
1
Ambient Temperature
2
Ambient Temperature
3
Ambient Temperature
4
EEPROM
RTC
U10
U33
U34
U253
U4
IIC Bus Mapping
Copyright © 2004 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. AVNET AVENUE and AVNET AVENUE & Design are trademarks of Avnet, Inc.
All other brands and trademarks are property of their respective owners.
Avnet Design Services
Released
5
Rev 1.0
12/22/2004
Literature # ADS-005000