Intel® Workstation System SC5650SCWS
Technical Product Specification
Intel order number: E81822-002
Revision 1.2
April 2010
Enterprise Platforms and Services Division
Revision History
Intel® Workstation System SC5650SCWS TPS
Revision History
Date
Revision
Number
Modifications
September 2009
1.0
March 2010
1.1
Initial Release
- Updated Section 3.3
1.2
- Updated Section 2.1 and 3.2 to add Intel® Xeon® Processor 5600 series support
- Removed CCC and CNCA related notice
April 2010
ii
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Intel order number: E81822-002
Intel® Workstation System SC5650SCWS TPS
Disclaimers
Disclaimers
Information in this document is provided in connection with Intel® products. No license, express or implied,
by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as
provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever,
and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including
liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any
patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications. Intel may make changes to specifications and product descriptions
at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked
"reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility
whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® Workstation System SC5650SCWS may contain design defects or errors known as errata
which may cause the product to deviate from published specifications. Current characterized errata are
available on request.
Intel Corporation server baseboards contain a number of high-density VLSI and power delivery
components that need adequate airflow to cool. Intel’s own chassis are designed and tested to meet the
intended thermal requirements of these components when the fully integrated system is used together. It
is the responsibility of the system integrator that chooses not to use Intel developed server building
blocks to consult vendor datasheets and operating parameters to determine the amount of air flow
required for their specific application and environmental conditions. Intel Corporation can not be held
responsible if components fail or the workstation board does not operate correctly when used outside any
of their published operating or non-operating limits.
Intel, Pentium, Itanium, and Xeon are trademarks or registered trademarks of Intel Corporation.
*Other brands and names may be claimed as the property of others.
Copyright © Intel Corporation 2009-2010.
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Table of Contents
Intel® Workstation System SC5650SCWS TPS
Table of Contents
1.
2.
3.
Introduction .......................................................................................................................... 1
1.1
Chapter Outline ........................................................................................................ 1
1.2
Workstation System Use Disclaimer ........................................................................ 1
Overview ............................................................................................................................... 3
2.1
Intel® Workstation System SC5650SCWS Feature Set ........................................... 3
2.2
Intel® Workstation System SC5650SCWS Layout .................................................. 5
2.2.1
Front View Components .......................................................................................... 5
2.2.2
Internal Components ............................................................................................... 7
2.2.3
Back Panel Components ......................................................................................... 8
2.2.4
Front Panel Components ......................................................................................... 8
2.2.5
Mechanical Locks .................................................................................................... 9
2.2.6
Mechanical Locks .................................................................................................... 9
2.2.7
System Color ......................................................................................................... 10
2.2.8
Rack and Cabinet Mouting Option ......................................................................... 10
2.2.9
Workstation Board Connector and Component Layout ......................................... 10
2.2.10
Workstation Board Mechanical Drawings .............................................................. 13
2.2.11
Rear I/O Layout ..................................................................................................... 19
Functional Architecture ..................................................................................................... 21
3.1
3.1.1
Intel® QuickPath Interconnect ................................................................................ 22
3.1.2
PCI Express* Ports ................................................................................................ 22
3.1.3
Enterprise South Bridge Interface (ESI) ................................................................ 23
3.1.4
Manageability Engine (ME) .................................................................................... 23
3.1.5
Controller Link (CL) ................................................................................................ 23
3.2
iv
Intel® 5520 I/O Hub (IOH) ...................................................................................... 22
Processor Support ................................................................................................. 23
3.2.1
Processor Population Rules .................................................................................. 23
3.2.2
Mixed Processor Configurations. ........................................................................... 23
3.2.3
Intel® Hyper-Threading Technology (Intel® HT) ..................................................... 25
3.2.4
Enhanced Intel SpeedStep® Technology (EIST) ................................................... 25
3.2.5
Intel® Turbo Boost Technology .............................................................................. 25
3.2.6
Execute Disable Bit Feature .................................................................................. 26
3.2.7
Core Multi-Processing ........................................................................................... 26
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Table of Contents
3.2.8
Direct Cache Access (DCA) .................................................................................. 26
3.2.9
Unified Retention System Support ......................................................................... 26
3.3
Memory Subsystem ............................................................................................... 27
3.3.1
Memory Subsystem Nomenclature ........................................................................ 27
3.3.2
Supported Memory ................................................................................................ 29
3.3.3
Processor Cores, QPI Links and DDR3 Channels Frequency Configuration ........ 29
3.3.4
Publishing System Memory ................................................................................... 32
3.3.5
Memory Interleaving .............................................................................................. 33
3.3.6
Memory Test .......................................................................................................... 33
3.3.7
Memory Scrub Engine ........................................................................................... 33
3.3.8
Memory RAS ......................................................................................................... 33
3.3.9
Memory Population and Upgrade Rules ................................................................ 34
3.3.10
Supported Memory Configuration .......................................................................... 36
3.3.11
Memory Error Handling .......................................................................................... 38
3.4
ICH10R .................................................................................................................. 39
3.4.1
Serial ATA Support ................................................................................................ 39
3.4.2
USB 2.0 Support .................................................................................................... 42
3.5
PCI Subsystem ...................................................................................................... 42
3.6
Intel® SAS Entry RAID Module AXX4SASMOD (Accessory) ................................. 43
3.6.1
3.7
3.7.1
SAS RAID Support ................................................................................................ 44
Baseboard Management Controller ....................................................................... 45
BMC Embedded LAN Channel .............................................................................. 46
3.8
Serial Ports ............................................................................................................ 47
3.9
Floppy Disk Controller ........................................................................................... 48
3.10
Keyboard and Mouse Support ............................................................................... 48
3.11
Video Support ........................................................................................................ 48
3.11.1
Video Modes .......................................................................................................... 49
3.11.2
Dual Video ............................................................................................................. 49
3.11.3
Graphics Card Population Guide ........................................................................... 50
3.12
3.12.1
Network Interface Controller (NIC) ........................................................................ 50
MAC Address Definition ......................................................................................... 51
3.13
Audio Codec .......................................................................................................... 52
3.14
IEEE 1394a Support .............................................................................................. 53
3.15
Trusted Platform Module (TPM) ............................................................................ 54
3.15.1
Overview ................................................................................................................ 54
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3.15.2
ACPI Support ......................................................................................................... 57
3.17
Intel® Virtualization Technology ............................................................................. 57
3.18
1000-W Power Supply ........................................................................................... 59
Mechanical Overview ............................................................................................. 60
4.1.2
Airflow Requirements ............................................................................................. 62
4.1.3
Acoustic Requirements .......................................................................................... 62
4.1.4
Temperature Requirements ................................................................................... 62
4.1.5
AC Input Voltage Requirements ............................................................................ 63
4.1.6
DC Output Specification ........................................................................................ 68
4.1.7
Power Connectors ................................................................................................. 68
4.1.8
DC Output Specifications ....................................................................................... 72
4.1.9
Control and Indicator Functions ............................................................................. 79
Platform Management ........................................................................................................ 81
Feature Support ..................................................................................................... 81
5.1.1
IPMI 2.0 Features .................................................................................................. 81
5.1.2
Non-IPMI Features ................................................................................................ 81
5.2
Optional Advanced Management Feature Support ............................................... 83
5.2.1
Enabling Advanced Management Features ........................................................... 83
5.2.2
Keyboard, Video, and Mouse (KVM) Redirection .................................................. 84
5.2.3
Media Redirection .................................................................................................. 84
5.2.4
Web Services for Management (WS-MAN) ........................................................... 85
5.2.5
Embedded Web server .......................................................................................... 86
5.2.6
Local Directory Authentication Protocol (LDAP) .................................................... 86
5.3
Platform Control ..................................................................................................... 87
5.3.1
Memory Open and Closed Loop Thermal Throttling .............................................. 88
5.3.2
Fan Speed Control ................................................................................................. 88
5.4
Intel® Intelligent Power Node Manager .................................................................. 91
5.4.1
Manageability Engine (ME) .................................................................................... 91
5.4.2
Manageability Engine (ME) .................................................................................... 91
BIOS Setup Utility ............................................................................................................... 93
6.1
vi
Intel® I/O Acceleration Technology ........................................................................ 58
4.1.1
5.1
6.
Intel® Virtualization Technology for Directed IO (VT-d).......................................... 58
Power Sub-system ............................................................................................................. 59
4.1
5.
TPM security BIOS ................................................................................................ 54
3.16
3.17.1
4.
Intel® Workstation System SC5650SCWS TPS
Logo / Diagnostic Screen....................................................................................... 93
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7.
8.
6.2
BIOS Boot Popup Menu ........................................................................................ 93
6.3
BIOS Setup Utility .................................................................................................. 93
6.3.1
Operation ............................................................................................................... 94
6.3.2
Server Platform Setup Utility Screens ................................................................... 96
Connector/Header Locations and Pin-outs.................................................................... 132
7.1
Board Connector Information ............................................................................... 132
7.2
Power Connectors ............................................................................................... 133
7.3
System Management Headers ............................................................................ 135
7.3.1
Intel® Remote Management Module 3 (Intel® RMM3) Connector ........................ 135
7.3.2
LCP / IPMB Header ............................................................................................. 135
7.3.3
HSBP Header ...................................................................................................... 136
7.3.4
SGPIO Header ..................................................................................................... 136
7.4
Front Panel Connector......................................................................................... 136
7.5
I/O Connectors ..................................................................................................... 137
7.5.1
NIC Connectors ................................................................................................... 137
7.5.2
SATA Connectors ................................................................................................ 137
7.5.3
SAS Module Slot .................................................................................................. 138
7.5.4
Serial Port Connectors ......................................................................................... 139
7.5.5
USB Connector .................................................................................................... 139
7.5.6
IEEE 1394a connectors ....................................................................................... 141
7.6
Audio Connectors ................................................................................................ 142
7.7
Onboard Video Header ........................................................................................ 142
7.8
Fan Headers ........................................................................................................ 143
Jumper Blocks .................................................................................................................. 145
8.1
9.
Table of Contents
CMOS Clear and Password Reset Usage Procedure ......................................... 146
8.1.1
Clearing the CMOS .............................................................................................. 146
8.1.2
Clearing the Password ......................................................................................... 146
8.2
Force BMC Update Procedure ............................................................................ 147
8.3
BIOS Recovery .................................................................................................... 147
Intel® Light Guided Diagnostics ...................................................................................... 149
9.1
5-V Stand-by LED ................................................................................................ 149
9.2
Fan Fault LEDs .................................................................................................... 150
9.3
System Status LED and System ID LED ............................................................. 151
9.4
DIMM Fault LEDs ................................................................................................ 153
9.5
POST Code Diagnostic LEDs .............................................................................. 154
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10. Design and Environmental Specifications ..................................................................... 155
10.1
Intel® Workstation System SC5650SCWS Design Specifications ....................... 155
10.2
MTBF ................................................................................................................... 155
10.2.1
Processor Power Support .................................................................................... 156
11. Regulatory and Certification Information....................................................................... 157
11.1
Product Regulatory Compliance .......................................................................... 157
11.1.1
Product Safety Compliance ................................................................................. 157
11.1.2
Product EMC Compliance – Class A Compliance ............................................... 157
11.1.3
Certifications / Registrations / Declarations ......................................................... 158
11.2
Product Regulatory Compliance Markings .......................................................... 159
11.3
Electromagnetic Compatibility Notices ................................................................ 159
FCC (USA) ......................................................................................................................... 159
ICES-003 (Canada) ............................................................................................................ 161
Europe (CE Declaration of Conformity) .............................................................................. 161
VCCI (Japan) ...................................................................................................................... 161
BSMI (Taiwan) .................................................................................................................... 161
RRL KCC (Korea) ............................................................................................................... 162
11.4
Product Ecology Change (EU RoHS) .................................................................. 162
11.5
Product Ecology Change (CRoHS) ..................................................................... 162
11.6
China Packaging Recycle Marks (or GB18455-2001) ......................................... 165
11.7
CA Perchlorate Warning ...................................................................................... 165
11.8
End-of-Life / Product Recycling ........................................................................... 165
Appendix A: Integration and Usage Tips.................................................................................. 166
Appendix B: Processor Active Heat Sink Installation .............................................................. 168
Appendix C: BMC Sensor Tables ............................................................................................... 170
Appendix D: Platform Specific BMC Appendix ......................................................................... 180
Appendix E: POST Code Diagnostic LED Decoder ..................................................................... 181
Appendix F: POST Error Messages and Handling ..................................................................... 186
Appendix G: Installation Guidelines ......................................................................................... 191
Glossary .................................................................................................................................... 193
Reference Documents .............................................................................................................. 197
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List of Figures
List of Figures
Figure 1. Front View Components (with Front Bezel Assembly) .................................................. 6
Figure 2. Front View Components (without Front Bezel Assembly) ............................................. 6
Figure 3. Internal Components ..................................................................................................... 7
Figure 4. Back Panel Components ............................................................................................... 8
Figure 5. Front Panel Components ............................................................................................... 9
Figure 6. Mechanical Locks ........................................................................................................ 10
Figure 7. Workstation Board Connector and Components Layout ............................................. 11
Figure 8. Major Board Components ............................................................................................ 12
Figure 9. Mounting Hole Positions .............................................................................................. 13
Figure 10. Major Connector Pin-1 Locations (1 of 2) .................................................................. 14
Figure 11. Major Connector Pin-1 Locations (2 of 2) .................................................................. 15
Figure 12. Primary Side Keepout Zone (1 of 2) .......................................................................... 16
Figure 13. Primary Side Keepout Zone (2 of 2) .......................................................................... 16
Figure 14. Primary Side Air Duct Keepout Zone ......................................................................... 17
Figure 15. Primary Side Card-Side Keepout Zone ..................................................................... 18
Figure 16. Second Side Keepout Zone ....................................................................................... 19
Figure 17. Rear I/O Layout ......................................................................................................... 20
Figure 18. Intel® Workstation System SC5650SCWS Functional Block Diagram....................... 21
Figure 19. Unified Retention System and Unified Back Plate Assembly .................................... 27
Figure 20. Intel® Workstation System SC5650SCWS DIMM Slots Arrangement ....................... 28
Figure 21. Intel® SAS Entry RAID Module AXX4SASMOD Component and Connector Layout . 44
Figure 22. Integrated BMC Hardware ......................................................................................... 46
Figure 23. Setup Utility – TPM Configuration Screen ................................................................. 56
Figure 24. Mechanical Drawing of the 1000-W Power Supply Enclosure ................................... 61
Figure 25. LED Markings ........................................................................................................... 63
Figure 26. Output Voltage Timing ............................................................................................... 76
Figure 27. Turn On/Off Timing (Power Supply Signals) .............................................................. 77
Figure 28: Server Platform with Embedded Platform Control ..................................................... 87
Figure 29. SMBUS Block Diagram .............................................................................................. 92
Figure 30. Setup Utility — Main Screen Display ......................................................................... 97
Figure 31. Setup Utility — Advanced Screen Display ................................................................. 99
Figure 32. Setup Utility — Processor Configuration Screen Display ........................................ 100
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Intel® Workstation System SC5650SCWS TPS
Figure 33. Setup Utility — Memory Configuration Screen Display............................................ 103
Figure 34. Setup Utility — Configure RAS and Performance Screen Display .......................... 105
Figure 35. Setup Utility — Mass Storage Controller Configuration Screen Display .................. 106
Figure 36. Setup Utility — Serial Port Configuration Screen Display ........................................ 108
Figure 37. Setup Utility — USB Controller Configuration Screen Display ................................ 109
Figure 38. Setup Utility — PCI Configuration Screen Display .................................................. 111
Figure 39. Setup Utility — System Acoustic and Performance Configuration Screen Display . 113
Figure 40. Setup Utility — Security Configuration Screen Display ........................................... 114
Figure 41. Setup Utility — Server Management Configuration Screen Display ........................ 116
Figure 42. Setup Utility — Console Redirection Screen Display .............................................. 118
Figure 43. Setup Utility — Server Management System Information Screen Display .............. 120
Figure 44. Setup Utility — Boot Options Screen Display .......................................................... 121
Figure 45. Setup Utility — Add New Boot Option Screen Display ............................................ 123
Figure 46. Setup Utility — Delete Boot Option Screen Display ................................................ 124
Figure 47. Setup Utility — Hard Disk Order Screen Display ..................................................... 125
Figure 48. Setup Utility — CDROM Order Screen Display ....................................................... 125
Figure 49. Setup Utility — Floppy Order Screen Display .......................................................... 126
Figure 50. Setup Utility — Network Device Order Screen Display............................................ 127
Figure 51. Setup Utility — BEV Device Order Screen Display.................................................. 127
Figure 52. Setup Utility — Boot Manager Screen Display ........................................................ 128
Figure 53. Setup Utility — Error Manager Screen Display ........................................................ 129
Figure 54. Setup Utility — Exit Screen Display ......................................................................... 130
Figure 55. Jumper Blocks ......................................................................................................... 145
Figure 56. 5V Stand-by Status LED Location ........................................................................... 149
Figure 57. Fan Fault LED Locations ......................................................................................... 150
Figure 58. System Status LED and ID LED Location ............................................................... 151
Figure 59. DIMM Fault LEDs Location ...................................................................................... 153
Figure 60. POST Code Diagnostic LED Location ..................................................................... 154
Figure 61. Active Processor Heatsink Installation..................................................................... 169
Figure 62. Diagnostic LED Placement Diagram ....................................................................... 181
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List of Tables
List of Tables
Table 1. IOH High-Level Summary ............................................................................................. 22
Table 2. Mixed Processor Configurations ................................................................................... 24
Table 3. Memory Running Frequency vs. Processor SKU.......................................................... 30
Table 4. Memory Running Frequency vs. Memory Population ................................................... 30
Table 5. Supported DIMM Population under the Dual Processors Configuration ....................... 37
Table 6. Supported DIMM Population under the Single Processor Configuration ...................... 37
Table 7. Onboard SATA Storage Mode Matrix ........................................................................... 41
Table 8. Intel® Workstation System SC5650SCWS PCI Bus Segment Characteristics ............. 42
Table 9. Intel® SAS Entry RAID Module AXX4SASMOD Storage Mode .................................... 44
Table 10. Serial A Port Configuration Jumper Pin-out ................................................................ 47
Table 11. Rear Serial A Port RJ-45 to DB9 Pin-out .................................................................... 47
Table 12. Serial B Header Pin-out .............................................................................................. 48
Table 13. Video Modes ............................................................................................................... 49
Table 14. Graphics Card Population ........................................................................................... 50
Table 15. Onboard NIC Status LED ............................................................................................ 51
Table 16. Setup Utility – Security Configuration Screen Fields .................................................. 56
Table 17. Sound Power Requirement ......................................................................................... 62
Table 18. Thermal Requirements ............................................................................................... 62
Table 19. AC Input Rating........................................................................................................... 63
Table 20. AC Line Sag Transient Performance .......................................................................... 64
Table 21. AC Line Surge Transient Performance ....................................................................... 64
Table 22. Performance Criteria ................................................................................................... 64
Table 23. AC Line Dropout / Holdup ........................................................................................... 65
Table 24. Efficiency..................................................................................................................... 67
Table 25. Cable Lengths ............................................................................................................. 68
Table 26. P1 Baseboard Power Connector ................................................................................ 68
Table 27. P2 Processor 1 Power Connector ............................................................................... 69
Table 28. P3 Processor 2 Power Connector ............................................................................... 70
Table 29. P4 Power Signal Connector ........................................................................................ 70
Table 30. P5 PCI Express Connector ......................................................................................... 70
Table 31. P6 PCI Express Connector ......................................................................................... 71
Table 32. P9-P12 Peripheral Power Connectors ........................................................................ 71
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Table 33. P13 Right-angle SATA Power Connector ................................................................... 71
Table 34. P14 SATA Power Connector ...................................................................................... 72
Table 35. Load Ratings ............................................................................................................... 72
Table 36. Pre-set Lighter Load ................................................................................................... 73
Table 37. Pre-set Lighter Voltage Regulation Limits ................................................................... 73
Table 38. Voltage Regulation Limits ........................................................................................... 74
Table 39. Transient Load Requirements ..................................................................................... 74
Table 40. Capacitive Loading Conditions ................................................................................... 75
Table 41. Ripple and Noise......................................................................................................... 75
Table 42. Output Voltage Timing ................................................................................................ 76
Table 43. Turn On / Off Timing ................................................................................................... 76
Table 44. Over-current Protection (OCP) 240VA ........................................................................ 78
Table 45. Over-voltage Protection Limits .................................................................................... 78
Table 46. PSON# Signal Characteristic ...................................................................................... 79
Table 47. PWOK Signal Characteristics ..................................................................................... 80
Table 48. LED Indicators ............................................................................................................ 80
Table 49. Basic and Advanced Management Features .............................................................. 83
Table 50. SC5650SCWS Fan Domain Table .............................................................................. 89
Table 51. BIOS Setup Page Layout ............................................................................................ 94
Table 52. BIOS Setup: Keyboard Command Bar........................................................................ 95
Table 53. Setup Utility — Main Screen Fields ............................................................................ 97
Table 54. Setup Utility — Advanced Screen Display Fields ....................................................... 99
Table 55. Setup Utility — Processor Configuration Screen Fields ............................................ 101
Table 56. Setup Utility — Memory Configuration Screen Fields ............................................... 104
Table 57. Setup Utility — Configure RAS and Performance Screen Fields .............................. 105
Table 58. Setup Utility — Mass Storage Controller Configuration Screen Fields ..................... 107
Table 59. Setup Utility — Serial Ports Configuration Screen Fields ......................................... 108
Table 60. Setup Utility — USB Controller Configuration Screen Fields .................................... 110
Table 61. Setup Utility — PCI Configuration Screen Fields ...................................................... 111
Table 62. Setup Utility — System Acoustic and Performance Configuration Screen Fields ..... 113
Table 63. Setup Utility — Security Configuration Screen Fields ............................................... 114
Table 64. Setup Utility — Server Management Configuration Screen Fields ........................... 117
Table 65. Setup Utility — Console Redirection Configuration Fields ........................................ 119
Table 66. Setup Utility — Server Management System Information Fields .............................. 120
Table 67. Setup Utility — Boot Options Screen Fields ............................................................. 122
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Table 68. Setup Utility — Add New Boot Option Fields ............................................................ 123
Table 69. Setup Utility — Delete Boot Option Fields ................................................................ 124
Table 70. Setup Utility — Hard Disk Order Fields ..................................................................... 125
Table 71. Setup Utility — CDROM Order Fields ....................................................................... 126
Table 72. Setup Utility — Floppy Order Fields .......................................................................... 126
Table 73. Setup Utility — Network Device Order Fields ........................................................... 127
Table 74. Setup Utility — BEV Device Order Fields ................................................................. 128
Table 75. Setup Utility — Boot Manager Screen Fields ............................................................ 128
Table 76. Setup Utility — Error Manager Screen Fields ........................................................... 129
Table 77. Setup Utility — Exit Screen Fields ............................................................................ 130
Table 78. Board Connector Matrix ............................................................................................ 132
Table 79. Power Connector Pin-out (J1K3) .............................................................................. 133
Table 80. CPU 1 Power Connector Pin-out (J9A1) ................................................................... 134
Table 81. CPU 2 Power Connector Pin-out (J9K1) ................................................................... 134
Table 82. Power Supply Signal Connector Pin-out (J9K2) ....................................................... 134
Table 83. Intel® RMM3 Connector Pin-out (J1C1) .................................................................... 135
Table 84. LPC / IPMB Header Pin-out (J1G6) .......................................................................... 135
Table 85. HSBP Header Pin-out (J1F5, J1G3) ......................................................................... 136
Table 86. SGPIO Header Pin-out (J1G2) ................................................................................. 136
Table 87. Front Panel SSI Standard 24-pin Connector Pin-out (J1B3) .................................... 136
Table 88. RJ-45 10/100/1000 NIC Connector Pin-out (JA5A1, JA6A2) .................................... 137
Table 89. SATA / SAS Connector Pin-out (J1E3, J1G1, J1G4, J1G5, J1F1, J1F4) ................. 138
Table 90. SAS Module Slot Pin-out (J2J1) ............................................................................... 138
Table 91. External RJ45 Serial A Port Pin-out (J8A2) .............................................................. 139
Table 92. Internal 9-pin Serial B Header Pin-out (J1B1) ........................................................... 139
Table 93. External USB Connector Pin-out (JA5A1, JA6A2) .................................................... 139
Table 94. Internal USB Connector Pin-out (J1D1) .................................................................... 140
Table 95. Internal USB Connector Pin-out (J1D4) .................................................................... 140
Table 96. Pin-out of Internal USB Connector for Low-Profile Solid State Drive (J1D3) ............ 140
Table 97. Internal Type A USB Port Pin-out (J1H2) ................................................................. 141
Table 98.External IEEE 1394a Port Pin-out (J8A2) .................................................................. 141
Table 99. Internal 1394 Port Pin-out (J1D2) ............................................................................. 141
Table 100. Internal Front Panel Audio Header Pin-out (J1D2) ................................................. 142
Table 101. Internal S/PDIF Header Pin-out (J4C1) .................................................................. 142
Table 102. Onboard Video Header Pin-out (J3B2) ................................................................... 143
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Table 103. SSI 4-pin Fan Header Pin-out (J7K1, J9A2, J5B1) ................................................. 143
Table 104. SSI 6-pin Fan Header Pin-out (J1K1, J1K2, J1K4, J1K5) ....................................... 144
Table 105. Workstation Board Jumpers (J1E2, J1E4, J1E5, J1H1, J2C1, J2C2, J4B2) .......... 145
Table 106. System Status LED ................................................................................................. 152
Table 107. Workstation System Design Specifications ............................................................. 155
Table 108. MTBF Estimate ....................................................................................................... 156
Table 109. Intel® Xeon® Processor Dual Processor TDP Guidelines ....................................... 156
Table 110. Compatible Heatsink Matrix .................................................................................... 168
Table 111. Integrated BMC Core Sensors ................................................................................ 172
Table 112. Platform Specific BMC Features ............................................................................. 180
Table 113. POST Progress Code LED Example ...................................................................... 181
Table 114. POST Codes and Messages .................................................................................. 182
Table 115. POST Error Messages and Handling ...................................................................... 187
Table 116. POST Error Beep Codes ........................................................................................ 190
Table 117. BMC Beep Codes ................................................................................................... 190
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Intel® Workstation System SC5650SCWS TPS
1.
Introduction
Introduction
This Technical Product Specification (TPS) provides board-specific information detailing the
features, functionality, and high-level architecture of the Intel® Workstation System
SC5650SCWS.
In addition, you can obtain design-level information for specific subsystems by ordering the
External Product Specifications (EPS) or External Design Specifications (EDS) for a given
subsystem. EPS and EDS documents are not publicly available and must be ordered through
your local Intel representative.
1.1
Chapter Outline
This document is divided into the following chapters:
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1.2
Chapter 1 – Introduction
Chapter 2 – Overview
Chapter 3 – Functional Architecture
Chapter 4 – Power Sub-system
Chapter 5 – Platform Management
Chapter 6 – BIOS Setup Utility
Chapter 7 – Connector / Header Locations and Pin-outs
Chapter 8 – Jumper Blocks
Chapter 9 – Intel® Light Guided Diagnostics
Chapter 10 – Design and Environmental Specifications
Chapter 11 – Regulatory and Certification Information
Appendix A – Integration and Usage Tips
Appendix B – Processor Active Heat Sink Installation
Appendix C – BMC Sensor Tables
Appendix D – Platform Specific BMC Appendix
Appendix E – POST Code Diagnostic LED Decoder
Appendix F – POST Error Messages and Handling
Appendix G – Installation Guidelines
Glossary
Reference Documents
Workstation System Use Disclaimer
Intel Corporation workstation systems contain a number of high-density VLSI and power
delivery components that need adequate airflow to cool. Intel ensures through its own chassis
development and testing that when Intel® server building blocks are used together, the fully
integrated system will meet the intended thermal requirements of these components. It is the
responsibility of the system integrator who chooses not to use Intel developed server building
blocks to consult vendor datasheets and operating parameters to determine the amount of
airflow required for their specific application and environmental conditions. Intel Corporation
Revision 1.2
Intel order number: E81822-002
1
Introduction
Intel® Workstation System SC5650SCWS TPS
cannot be held responsible if components fail or the workstation board does not operate
correctly when used outside any of their published operating or non-operating limits.
2
Revision 1.2
Intel order number: E81822-002
Intel® Workstation System SC5650SCWS TPS
2.
Overview
Overview
The Intel® Workstation System SC5650SCWS has a monolithic printed circuit board (PCB) with
features designed to support the performance workstation market.
2.1
Intel® Workstation System SC5650SCWS Feature Set
Feature
Processor
Description
• Support for one or two Intel® Xeon® Processor(s) 5500 series up to 130W Thermal Design Power
• Support for one or two Intel® Xeon® Processor(s) 5600 series up to 130W Thermal Design Power
• 4.8 GT/s, 5.86 GT/s, and 6.4 GT/s Intel® QuickPath Interconnect (Intel® QPI)
• FC-LGA 1366 Socket B
• Enterprise Voltage Regulator-Down (EVRD) 11.1
Memory
• Six memory channels (three channels for each processor socket)
ƒ
Channel A, B, C, D, E, and F
• 12 DIMM slots
ƒ
Two DIMM slots per channel
• Support for 800/1066/1333 MT/s ECC Registered DDR3 Memory (RDIMM), ECC or Non-ECC
Unbuffered DDR3 Memory (UDIMM).
• No support for mixing of RDIMMs and UDIMMs.
Chipset
• Intel® 5520 Chipset
• Intel® 82801JIR I/O Controller Hub (ICH10R)
Add-in Card Slots
• Two full-length/full-height PCI Express* Gen2 x16 slots
• One full-length/full-height PCI Express* Gen1 slot (x4 Mechanically, x1 Electrically)
• One full-length/full-height PCI Express* Gen1 slot (x8 Mechanically, x4 Electrically) , shared with
SAS Module Slot*
• One 32-bit/33-MHz PCI slot, keying for 5-volt and Universal PCI add-in card.
Hard Drive and
Optical Drive
Support
• Optical devices are supported.
RAID Support
• Intel® Embedded Server RAID Technology II through onboard SATA connectors provides SATA
RAID 0, 1, and 10 with optional RAID 5 support provided by the Intel® RAID Activation Key
AXXRAKSW5.
• Six SATA connectors at 1.5 Gbps and 3 Gbps.
• Four SAS connectors at 3 Gbps through optional Intel® SAS Entry RAID Module AXX4SASMOD.
• Intel® Embedded Server RAID Technology II through optional Intel® SAS Entry RAID Module
AXX4SASMOD provides SAS RAID 0, 1, and 10 with optional RAID 5 support provided by the Intel®
RAID Activation Key AXXRAKSW5.
• IT/IR RAID through optional Intel® SAS Entry RAID Module AXX4SASMOD provides entry hardware
RAID 0, 1, 10/1E, and native SAS pass through mode.
• 4 ports full featured SAS/SATA hardware RAID through optional Intel® Integrated RAID Module
SROMBSASMR (AXXROMBSASMR), provides RAID 0, 1, 5, 6 and striping capability for spans 10,
50, 60.
USB Drive Support
• One internal type A USB port with USB 2.0 support that supports a peripheral, such as a floppy
drive.
• One internal low-profile USB port for USB Solid State Drive.
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Overview
Intel® Workstation System SC5650SCWS TPS
Feature
I/O Control Support
Description
• External connections:
ƒ RJ-45 serial port A connection
ƒ One DH 10 serial port connector (optional)
ƒ Two RJ-45 NIC connectors for 10/100/1000 Mb connections: Dual GbE through the Intel®
82575EB Network Connection.
ƒ Four USB 2.0 ports at the back of the board.
ƒ 7.1 channel Audio Connections
ƒ One IEEE1394a connector
• Internal connections:
ƒ Two 9-pin USB headers, each supports two USB 2.0 ports
ƒ One DH10 serial port B header
ƒ Six SATA connectors at 1.5 Gbps and 3 Gbps
ƒ Four SAS connectors at 3 Gbps (optional)
ƒ One SSI-compliant 24-pin front control panel header
Video Support
• ServerEngines* LLC Pilot II* with 64 MB DDR2 memory, 8 MB allocated to graphics
ƒ Integrated 2D video controller
ƒ Onboard video connector available with optional accessory cable (FXXSCVDCBL).
ƒ Dual monitor video mode is supported
• Support add-in PCI Express* graphics cards
ƒ Single graphics card configuration at PCI Express* slot 6 with graphics card up to 300W.
ƒ Dual graphics cards conifiguration at PCI Express* slot 4 and slot 6 with each graphics card
up to 150W.
ƒ Keep PCI Express* Slot 3 empty for optimal air flow when populating a graphics card in PCI
Express* slot 4.
ƒ Graphics cards with power greater than 75W must be self-cooled with exhaust out the back
of the chassis
LAN
Two Gigabit NICs through Intel® 82575EB PHYs with Intel® I/O Acceleration Technology 2 support.
Audio Codec
• 7.1 channel audio support based on Realtek* ALC889 with 16/20/24-bit S/PDIF support
ƒ External audio connections through rear I/O
ƒ One internal 3-pin S/PDIF connector
ƒ One internal 2x5-pin audio connector
1394
• Two IEEE 1394a ports through Texas Instruments* TSB43AB22A
ƒ One external IEEE 1394a port through rear I/O
ƒ One internal 2x5-pin IEEE 1394a connector
Security
• Trusted Platform Module based on ST19NP18
Server
Management
• Onboard ServerEngines* LLC Pilot II* Controller
ƒ Integrated Baseboard Management Controller (Integrated BMC), IPMI 2.0 compliant
ƒ Integrated Super I/O on LPC interface
• Support for Intel® Remote Management Module 3
• Intel® Light-Guided Diagnostics on field replaceable units
• Support for Intel® System Management Software 3.1 and beyond
• Support for Intel® Intelligent Power Node Manager (Need PMBus-compliant power supply)
BIOS Flash
4
Winbond* W25X64
Intel order number: E81822-002
Revision 1.2
Intel® Workstation System SC5650SCWS TPS
Feature
Overview
Description
Workstation Board
Form Factor
EEB SSI (12”x13”)
Chassis Dimensions
• Pedestal Configuration: 17.8 inches high, 9.256 inches wide, 19 inches deep
• Rack Configuration: 9.256 inches high, 17.6 inches wide, 19 inches deep
Peripherals
• Two multi-mount 5.25-inch peripheral bays
• One 3.5-inch peripheral bay
Control Panel
(dependent on
option selected)
• Front Control Panel
LEDs and displays
(dependent on
option selected)
• With Front Control Panel
• Intel® Local Control Panel (optional)
ƒ NIC1 Activity
ƒ NIC2 Activity
ƒ Power/Sleep
ƒ System Status LED
Power Supply
• One 10000-W PFC power supply
Cooling
• Two 120-mm system fans (rear fan and PCI zone)
• One 92-mm system fans (Hard Disk Cage fan)
• Active processor heat sink(s) is required
* The PCI Express* Gen 1 slot (x8 Mechanically, x4 Electrically) is not available when the SAS module slot is in use
and vice versa.
2.2
Intel® Workstation System SC5650SCWS Layout
2.2.1
Front View Components
A
B
C
Revision 1.2
5.25-inch Device Drive Bays
Front Control Panel
3.5-inch Drive Bay Access Door
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Overview
Intel® Workstation System SC5650SCWS TPS
D
E
F
Drive Bay Access Door
Door Lock
Front Panel USB Ports
Figure 1. Front View Components (with Front Bezel Assembly)
A
B
C
D
E
5.25-inch Device Drive Bays
3.5-inch Device Drive Bay
Fixed Hard Disk Cage
Fixed Hard Disk Cage EMI Shield (show open)
Front Panel USB Ports
Figure 2. Front View Components (without Front Bezel Assembly)
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2.2.2
Overview
Internal Components
A
B
C
D
E
F
G
H
I
J
Tool-less Device Bay Locks
5.25-inch Device Bays
3.5-inch Device Bay
Drive Cage Retention Mechanism
PCI Add-in Card Guide / System Fan
Assembly
Workstation Board
Front Panel USB Ports
Rear Tool-less PCI Retention
Mechanisms
Fan Duct / System Fan Assembly
Power Supply
Figure 3. Internal Components
Revision 1.2
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Overview
2.2.3
Intel® Workstation System SC5650SCWS TPS
Back Panel Components
A
B
C
D
E
F
G
H
I
Power Supply
A/C Power In
Rear I/O Shield
PCI Add-in Card Slots
External SCSI Port Knockout
Rear System Fan Assembly
Location to Install Padlock Loop
External SCSI Port Knockout
Alternate Serial B Port
Figure 4. Back Panel Components
2.2.4
8
Front Panel Components
Intel order number: E81822-002
Revision 1.2
Intel® Workstation System SC5650SCWS TPS
Callout
Button / LED Name
Color
A
Power LED
Green
B
Power Button
C
Overview
Condition
Description
On
Power on
Off
Power off
N/A
N/A
Powers the system on or off
NMI Button
N/A
N/A
Used to force system halt and dump memory
contents to screen or file
D
Reset Button
N/A
N/A
Reboots and initializes the system
On
Linked
E
NIC1 Activity
F
NIC2 Activity
G
Hard Drive Activity
Green
Green
Green
Green
H
System Status LED
Blink
LAN activity
Off
Idle
On
Linked
Blink
LAN activity
Off
Idle
Blink
Hard drive activity
On
System booted and ready
Blink
System ready, but degraded: some CPU fault,
DIMM killed, and so forth
On
Critical alarm: Critical power module failure,
critical fan failure, voltage (power supply),
voltage, thermal fault, and so forth
Blink
Non-critical failure: Redundant fan failure,
redundant power failure, non-critical power
and voltage, and so forth
Off
AC Power off;
Off
Powered Down (DC-off state or S5), and no
degraded, non-critical, critical conditions
exist*
Amber
Off
Figure 5. Front Panel Components
* When the workstation is powered down (transitions to the DC-off state or S5), the BMC is still
on standby power and retains the sensor and front panel status LED state established before
the power-down event. If the system status is normal when the system is powered down (the
LED is in a solid green state), the system status LED will be off.
2.2.5
2.2.6
Mechanical Locks
Mechanical Locks
The Intel® Workstation System SC5650SCWS chassis support the installation of a padlock loop
(see letter “A” in the following figure) at the rear of the chassis. Additionally, the system ships
with a two-position mechanical lock (see letter “B”) on the front bezel assembly to prevent
access to the hard drives and the interior of the system.
Revision 1.2
Intel order number: E81822-002
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Overview
Intel® Workstation System SC5650SCWS TPS
Figure 6. Mechanical Locks
2.2.7
System Color
®
The Intel Workstation System SC5650SCWS chassis is offered in one color - Black (GE701).
2.2.8
Rack and Cabinet Mouting Option
®
The Intel Workstation System SC5650SCWS supports a rack mount configuration. The rack
mount kit includes the chassis slide rails, rack handle, rack orientation label, screws, and
manual. This rack mount kit is designed to meet the EIA-310-D enclosure specification. General
rack compatibility is further described in the Server Rack Cabinet Compatibility Guide found at
http://support.intel.com.
2.2.9
Workstation Board Connector and Component Layout
The following figure shows the board layout of the workstation board in the Intel® Workstation
System SC5650SCWS. Each connector and major component is identified by a number or letter,
and a description follows each figure.
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Revision 1.2
Intel® Workstation System SC5650SCWS TPS
Overview
Figure 7. Workstation Board Connector and Components Layout
Revision 1.2
Intel order number: E81822-002
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Overview
Intel® Workstation System SC5650SCWS TPS
Callout
A
Description
S/PDIF Header
Callout
X
Description
System Fan 3 Header
B
Slot 1, 32-bit / 33-MHz PCI, 5V
Y
System Fan 4 Header
C
Intel® Remote Management 3 Slot
Z
System Fan 2 Header
D
Slot 2, PCI Express* Gen1 x4 (x8 Mechanically)
AA
System Fan 1 Header
E
IEEE 1394a Header
BB
Main Power Connector
F
Slot 3, PCI Express* Gen1 x1 (x4 Mechanically)
CC
LCP/IPMB header
G
Low-profile USB Solid State Drive Header
DD
SATA SGPIO Header
H
Slot 4, PCI Express* Gen2 x 16
EE
Type A USB Port
I
Onboard Video Header
FF
SATA Port 0
J
Slot 6, PCI Express* Gen2 x16
GG
SATA Port 1
K
Battery
HH
HSBP_B
L
System Fan 5 Header
II
SATA Port 2
M
Back panel I/O Ports
JJ
HSBP_A
N
Internal Audio Connector
KK
SATA Port 3
O
Diagnostic and Identify LEDs
LL
SATA Software RAID 5 Key Header
P
Power Connector for CPU 1 and Memory attached to
CPU 1
MM
Chassis Intrusion Header
Q
CPU 1 Fan Header
NN
SATA Port 4
R
DIMM Sockets from CPU 1 Socket (Channel A, B, and C)
OO
SATA Port 5
S
Power Connector for CPU 2 and memory attached to
CPU 2
PP
HDD Activity LED (Connect to Add-in Card HDD
Activity LED Header)
T
Auxiliary Power Signal Connector
QQ
USB Connector
U
CPU 2 Fan Header
RR
USB Connector
V
DIMM Sockets from CPU 2 Socket (Channel D, E, and F)
SS
Front panel header
W
SAS Module Slot
TT
DH-10 Serial B header
Figure 8. Major Board Components
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Revision 1.2
Intel® Workstation System SC5650SCWS TPS
2.2.10
Overview
Workstation Board Mechanical Drawings
Figure 9. Mounting Hole Positions
Revision 1.2
Intel order number: E81822-002
13
Overview
Intel® Workstation System SC5650SCWS TPS
Figure 10. Major Connector Pin-1 Locations (1 of 2)
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Intel® Workstation System SC5650SCWS TPS
Overview
Figure 11. Major Connector Pin-1 Locations (2 of 2)
Revision 1.2
Intel order number: E81822-002
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Overview
Intel® Workstation System SC5650SCWS TPS
Figure 12. Primary Side Keepout Zone (1 of 2)
Figure 13. Primary Side Keepout Zone (2 of 2)
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Intel® Workstation System SC5650SCWS TPS
Overview
Figure 14. Primary Side Air Duct Keepout Zone
Revision 1.2
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Overview
Intel® Workstation System SC5650SCWS TPS
Figure 15. Primary Side Card-Side Keepout Zone
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Intel® Workstation System SC5650SCWS TPS
Overview
Figure 16. Second Side Keepout Zone
2.2.11
Rear I/O Layout
The following figure shows the layout of the rear I/O components for the Intel® Workstation
System SC5650SCWS.
Revision 1.2
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Overview
Intel® Workstation System SC5650SCWS TPS
Callout
A
Description
Callout
Description
G
Audio: Side Surround out
H
Audio: Front Surround out
C
Diagnostic LEDs
Serial A Port (Top)
IEEE 1394a Port (Bottom)
ID LED
I
Audio: Microphone in
D
System Status LED
J
E
Audio: Back Surround out
K
F
Audio: Center / LFE out
L
Audio: Line-in
NIC Port 1 (1 Gb, Default Management
Port)
USB Port 2 (Top), 3 (Bottom)
NIC Port 2 (1Gb)
USB Port 0 (Top), 1 (Bottom)
B
Figure 17. Rear I/O Layout
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Intel® Workstation System SC5650SCWS TPS
3.
Functional Architecture
Functional Architecture
The architecture and design of the Intel® Workstation System SC5650SCWS is based on the
Intel® 5520 and ICH10R chipset. The chipset is designed for systems based on the Intel® Xeon®
Processor 5500 Series or Intel® Xeon® Processor 5600 Series in an FC-LGA 1366 Socket B
package with Intel® QuickPath Interconnect (Intel® QPI) speed at 6.40 GT/s, 5.86 GT/s, and
4.80 GT/s.
The chipset contains two main components:
– Intel® 5520 I/O Hub (IOH), which provides a connection point between various I/O
components and the Intel® QuickPath Interconnect (Intel® QPI) based processors
– Intel® ICH10 RAID (ICH10R) I/O controller hub for the I/O subsystem
This chapter provides a high-level description of the functionality associated with each chipset
component and the architectural blocks that make up the workstation board.
Figure 18. Intel® Workstation System SC5650SCWS Functional Block Diagram
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Functional Architecture
3.1
Intel® Workstation System SC5650SCWS TPS
Intel® 5520 I/O Hub (IOH)
The Intel® 5520 I/O Hub (IOH) on the Intel® Workstation System SC5650SCWS provides a
connection point between various I/O components and Intel® QPI based processors, which
includes the following core platform functions:
– Intel® QPI link interface for the processor subsystem
– PCI Express* Ports
– Enterprise South Bridge Interface (ESI) for connecting Intel® ICH10R
– Manageability Engine (ME)
– Controller Link (CL)
– SMBus Interface
– Intel® Virtualization Technology for Directed I/O (Intel® VT-d)
The following table shows the high-level features of the Intel® 5520 IOH:
Table 1. IOH High-Level Summary
IOH SKU
Intel® QPI Ports
Supported Processor
PCI Express*
Lanes
Manageability
5520
2
Intel® Xeon® Processor 5500 Series
36
Intel® Intelligent Power
Node Manager
3.1.1
Intel® QuickPath Interconnect
The Intel® Workstation System SC5650SCWS provides two full-width, cache-coherent, linkbased Intel® QuickPath Interconnect interfaces from Intel® 5520 IOH for connecting Intel® QPI
based processors. The two Intel® QPI link interfaces support full-width communication only and
have the following main features:
Packetized protocol with 18 data/protocol bits and 2 CRC bits per link per direction
„
Supporting 4.8 GT/s, 5.86 GT/s, and 6.4 GT/s
Fully-coherent write cache with inbound write combining
Read Current command support
Support for 64-byte cache line size
z
z
z
z
3.1.2
PCI Express* Ports
®
The Intel 5520 IOH is capable of interfacing with up to 36 PCI Express* Gen2 lanes, which
support devices with the following link width: x16, x8, x4, x2, and x1.
All ports support PCI Express* Gen1 and Gen2 transfer rates.
For a detailed PCI Express* Slots definition of the Intel® Workstation System SC5650SCWS,
refer Section 3.5, PCI Subsystem.
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3.1.3
Functional Architecture
Enterprise South Bridge Interface (ESI)
One x4 ESI link interface that supports the PCI Express* Gen1 (2.5 Gbps) transfer rate for
connecting Intel® ICH10R in the Intel® Workstation System SC5650SCWS.
3.1.4
Manageability Engine (ME)
An embedded ARC controller is within the IOH providing the Intel® Server Platform Services
(SPS). The controller is also commonly referred to as the Manageability Engine (ME).
3.1.5
Controller Link (CL)
The Controller Link is a private, low-pin count (LPC), low power, communication interface
between the IOH and the ICH10 portions of the Manageability Engine subsystem.
3.2
Processor Support
The Intel® Workstation System SC5650SCWS supports one or two Intel® Xeon® Processor 5500
Series or Intel® Xeon® Processor 5600 Series with a 4.8 GT/s, 5.86 GT/s, or 6.4 GT/s Intel® QPI
link interface and Thermal Design Power (TDP) up to 130 W.
The workstation boards do not support previous generations of the Intel® Xeon® processors.
For a complete, updated list of supported processors, see:
http://support.intel.com/support/motherboards/server/S5520SC/. On the Support tab, look for
“Compatibility” and then “Supported Processor List”.
3.2.1
Processor Population Rules
You must populate processors in sequential order. Therefore, you must populate processor
socket 1 (CPU 1) before processor socket 2 (CPU 2).
When only one processor is installed, it must be in the socket labeled CPU1, which is located
near the rear edge of the workstation board. When a single processor is installed, no terminator
is required in the second processor socket.
For optimum performance, when two processors are installed, both must be the identical
revision and have the same core voltage and Intel® QPI/core speed.
3.2.2
Mixed Processor Configurations.
The following table describes mixed processor conditions and recommended actions for the
Intel® Workstation System SC5650SCWS. Errors fall into one of three categories:
z
Revision 1.2
Halt: If the system can boot, it pauses at a blank screen with the text
“Unrecoverable fatal error found. System will not boot until the error is resolved” and
“Press <F2> to enter setup”, regardless of if the “Post Error Pause” setup option is
enabled or disabled. After entering setup, the error message displays on the Error
Manager screen and an error is logged to the System Event Log (SEL) with the error
code. The system cannot boot unless the error is resolved. The user must replace
the faulty part and restart the system.
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Functional Architecture
z
z
Intel® Workstation System SC5650SCWS TPS
Pause: If the “Post Error Pause” setup option is enabled, the system goes directly to
the Error Manager screen to display the error and log the error code to SEL.
Otherwise, the system continues to boot and no prompt is given for the error,
although the error code is logged to the Error Manager and in a SEL message.
Minor: The message is displayed on the screen or on the Error Manager screen.
The system continues booting in a degraded state regardless of if the “Post Error
Pause” setup option is enabled or disabled. The user may want to replace the
erroneous unit.
Table 2. Mixed Processor Configurations
Error
Processor family not
identical
Processor stepping
mismatch
Severity
Halt
Pause
System Action
The BIOS detects the error condition and responds as follows:
–
Logs the error into the system event log (SEL)
–
Alerts the Integrated BMC about the configuration error.
–
Does not disable the processor
–
Displays “0194: Processor 0x family mismatch detected” message in the
Error Manager.
–
Halts the system and will not boot until the fault condition is remedied.
The BIOS detects the stepping difference and responds as follows:
–
Checks to see whether the steppings are compatible – typically +/- one
stepping.
–
If so, no error is generated (this is not an error condition).
–
Continues to boot the system successfully.
Otherwise, this is a stepping mismatch error, and the BIOS responds as
follows:
Processor cache not
identical
Processor frequency
(speed) not identical
Halt
Halt
–
Displays “0193: Processor 0x stepping mismatch” message in the Error
Manager and logs it into the SEL.
–
Takes Minor Error action and continues to boot the system.
The BIOS detects the error condition and responds as follows:
–
Logs the error into the SEL.
–
Alerts the Integrated BMC about the configuration error.
–
Does not disable the processor.
–
Displays “0192: Processor 0x cache size mismatch detected” message in
the Error Manager.
–
Halts the system and does not boot until the fault condition is remedied.
The BIOS detects the error condition and responds as follows:
–
Adjusts all processor frequencies to the highest common frequency.
–
No error is generated – this is not an error condition.
–
Continues to boot the system successfully.
If the frequencies for all processors cannot be adjusted to be the same, then
the BIOS:
–
Logs the error into the SEL.
–
Displays “0197: Processor 0x family is not supported” message in the
Error Manager.
– Halts the system and will not boot until the fault condition is remedied.
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Intel® Workstation System SC5650SCWS TPS
Error
Severity
Processor Intel®
QuickPath Interconnect
speeds not identical
Halt
Functional Architecture
System Action
The BIOS detects the error condition and responds as follows:
–
Adjusts all processor QPI frequencies to highest common frequency.
–
No error is generated – this is not an error condition
–
Continues to boot the system successfully.
If the link speeds for all QPI links cannot be adjusted to be the same, then the
BIOS:
–
Logs the error into the SEL.
–
Displays “0195: Processor 0x Intel® QPI speed mismatch” message in the
Error Manager.
– Halts the system and will not boot until the fault condition is remedied.
Processor microcode
missing
3.2.3
Minor
The BIOS detects the error condition and responds as follows:
–
Logs the error into the SEL.
–
Does not disable the processor.
–
Displays “8180: Processor 0x microcode update not found” message in
the Error Manager or on the screen.
–
The system continues to boot in a degraded state, regardless of the
setting of POST Error Pause in Setup.
Intel® Hyper-Threading Technology (Intel® HT)
If the installed processor supports the Intel® Hyper-Threading Technology, the BIOS Setup
provides an option to enable or disable this feature. The default is enabled.
The BIOS creates additional entries in the ACPI MP tables to describe the virtual processors.
The SMBIOS Type 4 structure shows only the installed physical processors. It does not
describe the virtual processors.
Because some operating systems are not able to efficiently use the Intel® HT Technology, the
BIOS does not create entries in the Multi-Processor Specification, Version 1.4 tables to describe
the virtual processors.
3.2.4
Enhanced Intel SpeedStep® Technology (EIST)
If the installed processor supports Enhanced Intel SpeedStep® Technology, the BIOS Setup
provides an option to enable or disable this feature. The default is enabled.
3.2.5
Intel® Turbo Boost Technology
Intel® Turbo Boost Technology opportunistically and automatically allows the processor to run
faster than the marked frequency if the part is operating below power, temperature, and current
limits.
If the processor supports this feature, the BIOS setup provides an option to enable or disable
this feature. The default is enabled.
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Functional Architecture
3.2.6
Intel® Workstation System SC5650SCWS TPS
Execute Disable Bit Feature
The Execute Disable Bit feature (XD bit) can prevent data pages from being used by malicious
software to execute code. A processor with the XD bit feature can provide memory protection in
one of the following modes:
z
z
Legacy protected mode if Physical Address Extension (PAE) is enabled.
Intel® 64 mode when 64-bit extension technology is enabled (Entering Intel® 64
mode requires enabling PAE).
You can enable and disable the XD bit in the BIOS Setup. The default behavior is enabled.
3.2.7
Core Multi-Processing
The BIOS setup provides the ability to selectively enable one or more cores. The default
behavior is to enable all cores. This is done through the BIOS setup option for active core count.
The BIOS creates entries in the Multi-Processor Specification, Version 1.4 tables to describe
multi-core processors.
3.2.8
Direct Cache Access (DCA)
Direct Cache Access (DCA) is a system-level protocol in a multi-processor system to improve
I/O network performance, thereby providing higher system performance. The basic idea is to
minimize cache misses when a demand read is executed. This is accomplished by placing the
data from the I/O devices directly into the processor cache through hints to the processor to
perform a data pre-fetch and install it in its local caches.
The BIOS setup provides an option to enable or disable this feature. The default behavior is
enabled.
3.2.9
Unified Retention System Support
The server boards comply with Unified Retention System (URS) and Unified Backplate
Assembly. The workstation board ships with Unified Backplate Assembly at each processor
socket.
The URS retention transfers load to the server boards via the Unified Backplate Assembly. The
URS spring, captive in the heatsink, provides the necessary compressive load for the thermal
interface material (TIM). All components of the URS heatsink solution are captive to the
heatsink and only require a Phillips* screwdriver to attach to the Unified Backplate Assembly.
Refer to the following figure for the stacking order of URS components.
The Unified Backplate Assembly is removable, allowing for the use of non-Intel® heatsink
retention solutions.
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Functional Architecture
Figure 19. Unified Retention System and Unified Back Plate Assembly
3.3
Memory Subsystem
The Intel® Xeon® Processor 5500 Series or Intel® Xeon® Processor 5600 Series on the Intel®
Workstation System SC5650SCWS are populated on CPU sockets. Each processor installed on
the CPU socket has an integrated memory controller (IMC), which supports up to three DDR3
channels and groups DIMMs on the workstation into autonomous memory.
3.3.1
Memory Subsystem Nomenclature
The nomenclature for DIMM sockets implemented in the Intel® Workstation System
SC5650SCWS is represented in the following figures.
DIMMs are organized into physical slots on DDR3 memory channels that belong to
processor sockets.
z
The memory channels for CPU 1 socket are identified as Channels A, B, and C. The
memory channels for CPU 2 socket are identified as Channels D, E, and F.
z
The DIMM identifiers on the silkscreen on the board provide information about which
channel / CPU Socket they belong to. For example, DIMM_A1 is the first slot on
Channel A of CPU 1 socket. DIMM_D1 is the first slot on Channel D of CPU 2
Socket.
z
Processor sockets are self-contained and autonomous. However, all configurations
in the BIOS setup, such as RAS, Error Management, and so forth, are applied
commonly across sockets.
The Intel® Workstation System SC5650SCWS supports six DDR3 memory channels (three
channels per processor) with two DIMM slots per channel, thus supporting up to 12 DIMMs in a
two-processor configuration. Refer to following figure for the Intel® Workstation System
SC5650SCWS DIMM slots arrangement.
z
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Functional Architecture
Workstation Board
Intel® Workstation System SC5650SCWS TPS
CPU Socket
CPU 1
Intel® Workstation System
SC5650SCWS
CPU 2
DIMM Identifier
A1 (Blue)
A2 (Black)
B1 (Blue)
B2 (Black)
C1 (Blue)
C2 (Black)
D1 (Blue)
D2 (Black)
E1 (Blue)
E2 (Black)
F1 (Blue)
F2 (Black)
Channel / Slot
Channel A, Slot 0
Channel A, Slot 1
Channel B, Slot 0
Channel B, Slot 1
Channel C, Slot 0
Channel C, Slot 1
Channel D, Slot 0
Channel D, Slot 1
Channel E, Slot 0
Channel E, Slot 1
Channel F, Slot 0
Channel F, Slot 1
Figure 20. Intel® Workstation System SC5650SCWS DIMM Slots Arrangement
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3.3.2
Functional Architecture
Supported Memory
Intel® Workstation System SC5650SCWS supports up to 12 DDR3 DIMMs with 1.5
V.
Intel® Workstation System SC5650SCWS supports Registered DDR3 DIMMs
(RDIMMs), and ECC Unbuffered DDR3 DIMMs (UDIMMs).
„
Mixing of RDIMMs and UDIMMs is not supported.
„
Mixing memory type, size, speed and/or rank on this platform has not been
validated and is not supported
„
Mixing memory vendors is not supported on this platform by Intel
„
Non-ECC memory is not supported and has not been validated in a server
environment
®
Intel Workstation System SC5650SCWS supports the following DIMM and DRAM
technologies:
„
RDIMMs:
–
Single-, Dual-, and Quad-Rank
–
x 4 or x8 DRAM with 1 Gb and 2 Gb technology - no support for 2 Gb
DRAM based 2 GB or 4 GB RDIMMs
–
DDR3 1333 (Single- and Dual-Rank only), DDR3 1066, and DDR3 800
„
UDIMMs:
–
Single- and Dual-Rank
–
x8 DRAM with 1 Gb or 2 Gb technology
–
DDR3 1333, DDR3 1066, and DDR3 800
z
z
z
3.3.3
Processor Cores, QPI Links and DDR3 Channels Frequency Configuration
®
The Intel Xeon® 5500 series processor or Intel® Xeon® Processor 5600 Series connects to
other Intel® Xeon® 5500 series processors or Intel® Xeon® Processor 5600 Series and Intel®
5520 IOH through the Intel® QPI link interface. The frequencies of the processor cores and the
QPI links of Intel® Xeon® 5500 series processor or Intel® Xeon® Processor 5600 Series
processor are independent from each other. There are no gear-ratio requirements for the Intel®
Xeon® Processor 5500 Series or Intel® Xeon® Processor 5600 Series.
Intel® 5520 IOH supports 4.8 GT/s, 5.86 GT/s, and 6.4 GT/s frequencies for the QPI links.
During QPI initialization, the BIOS configures both endpoints of each QPI link to the same
supportable speeds for the correct operation.
During memory discovery, the BIOS arrives at a fastest common frequency that matches the
requirements of all components of the memory system and then configures the DDR3 DIMMs
for the fastest common frequency.
In addition, rules in the following tables also determine the global common memory system
frequency.
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Table 3. Memory Running Frequency vs. Processor SKU
DIMM Type
DDR3 800
DDR3 1066
DDR3 1333
800
800
800
800
Processor Integrated
Memory Controller
(IMC) Max. Frequency
(Hz)
1066
800
1066
1066
1333
800
1066
1333
Memory Running Frequency (Hz) =
Fastest Common Frequency of Processor IMC and
Memory
Table 4. Memory Running Frequency vs. Memory Population
Ranks Per DIMM
800MHz
1066MHz
1333MHz
RDIMM
1
Y
Y
Y
1N
SR or DR
RDIMM
1
Y
Y
N
1N
QR only
All RDIMMs run at 800MHz or 1066MHz when
Quad-Rank RDIMM is installed in any channel.
RDIMM
2
Y
Y
N
1N
SR or DR
All RDIMMs run at 800MHz or 1066MHz when
two RDIMMs (Single-Rank or Dual-Rank) are
installed in the same channel.
RDIMM
2
Y
N
N
1N
QR only
All RDIMMs run at 800MHz when two RDIMMs
(either or both are Quad-Rank RDIMMs) are
installed in the same channel.
1
Y
Y
Y
1N
SR or DR
All UDIMMs run at the fastest common
frequency of processor IMCs and installed
memory: 800MHz, 1066MHz, or 1333MHz.
2
Y
Y
N
2N
SR or DR
All RDIMMs run at the fastest common
frequency of processor IMCs and installed
DIMM Type
UDIMM
w/ or w/o ECC
UDIMM
30
Memory Running Frequency
(Y/N)
DIMM
Populated Per
Channel
Command /
Address Rate
SR: Single-Rank
DR: Dual-Rank
Description
QR: Quad-Rank
Intel order number: E81822-002
All RDIMMs run at the fastest common
frequency of processor IMCs and installed
memory: 800MHz, 1066MHz, or 133MHz
Revision 1.2
Intel® Workstation System SC5650SCWS TPS
DIMM Type
DIMM
Populated Per
Channel
Functional Architecture
Memory Running Frequency
(Y/N)
800MHz
1066MHz
1333MHz
Ranks Per DIMM
Command /
Address Rate
SR: Single-Rank
DR: Dual-Rank
Description
QR: Quad-Rank
memory: 800MHz, 1066MHz, or 133MHz
w/ or w/o ECC
1N: One clock cycle for the DRAM commands arrive at the DIMMs to execute.
2N: Two clock cycles for the DRAM commands arrive at the DIMMs to execute.
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Functional Architecture
3.3.4
Publishing System Memory
z
z
z
z
3.3.4.1
Intel® Workstation System SC5650SCWS TPS
The BIOS displays the “Total Memory” of the system during POST if Quiet Boot is
disabled in the BIOS Setup. This is the total size of memory discovered by the BIOS
during POST, and is the sum of the individual sizes of installed DDR3 DIMMs in the
system.
The BIOS also provides the total memory of the system in the BIOS setup (Main
page and Advanced | Memory Configuration Page). This total is the same as the
amount described by the previous bullet.
The BIOS displays the “Effective Memory” of the system in the BIOS Setup
(Advanced | Memory Configuration Page). The term Effective Memory refers to the
total size of all active DDR3 DIMMs (not disabled) and not being used as redundant
units in Mirrored Channel Mode.
If Quiet Boot is disabled, the BIOS displays the total system memory on the
diagnostic screen at the end of POST. This total is the same as the amount
described by the first bullet.
Memory Reservation for Memory-mapped Functions
A region of size 40 MB of memory below 4 GB is always reserved for mapping chipset,
processor, and BIOS (flash) spaces as memory-mapped I/O regions. This region appears as a
loss of memory to the operating system.
This (and other) reserved regions are reclaimed by the operating system if PAE is enabled in
the operating system.
In addition to this memory reservation, the BIOS creates another reserved region for memorymapped PCI Express* functions, including a standard 64 MB or 256 MB of standard PC Express
MMIO configuration space. This is based on the setup selection “Maximize Memory below 4GB”.
If this is set to “Enabled”, the BIOS maximizes usage of memory below 4 GB, for an operating
system without PAE capability, by limiting PCI Express* Extended Configuration Space to 64
buses, rather that the standard 256 buses.
3.3.4.2
High-Memory Reclaim
When 4 GB or more of physical memory is installed (physical memory is the memory installed
as DDR3 DIMMs), the reserved memory is lost. However, the Intel® 5500/5520 I/O Hub provides
a feature called high-memory reclaim, which allows the BIOS and the operating system to
remap the lost physical memory into system memory above 4 GB (the system memory is the
memory the processor can see).
The BIOS always enables high-memory reclaim if it discovers installed physical memory equal
to or greater than 4 GB. For the operating system, you can recover the reclaimed memory only
if the PAE feature in the processor is supported and enabled. Most operating systems support
this feature. For details, refer to the relevant operating system’s manuals.
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3.3.5
Functional Architecture
Memory Interleaving
®
The Intel Xeon® Processor 5500 Series and Intel® Xeon® Processor 5600 Series support the
following memory interleaving mode:
ƒ
Bank Interleaving – Interleave cache-line data between participant ranks.
ƒ
Channel Interleaving – Interleave between the channel when not in Mirrored Channel
Mode.
ƒ
Socket Interleaving – Interleaved memory can spread between both CPU sockets when
NUMA mode is disabled, given both CPU sockets are populated and DDR3 DIMMs are
installed in slots for both sockets.
3.3.6
Memory Test
3.3.6.1
Integrated Memory BIST Engine
®
The Intel Xeon® Processor 5500 series and Intel® Xeon® Processor 5500 Series incorporate an
integrated Memory Built-in Self Test (BIST) engine that is enabled to provide extensive
coverage of memory errors at both the memory cells and the data paths emanating from the
DDR3 DIMMs.
The BIOS also uses the Memory BIST to initialize memory at the end of the memory discovery
process.
3.3.7
Memory Scrub Engine
®
The Intel Xeon® Processor 5500 Series and Intel® Xeon® Processor 5500 Series incorporates a
memory scrub engine, which performs periodic checks on the memory cells, and identifies and
corrects single-bit errors. Two types of scrubbing operations are supported:
ƒ
Demand scrubbing – Executes when an error is encountered during normal read/write
of data.
ƒ
Patrol scrubbing – Proactively walks through populated memory space seeking soft
errors.
By default, the BIOS enables both demand scrubbing and patrol scrubbing.
Demand scrubbing is not possible when memory mirroring is enabled. Therefore, if the memory
is configured for mirroring, the BIOS disables it automatically.
3.3.8
Memory RAS
3.3.8.1
RAS Features
®
The Intel Workstation System SC5650SCWS supports the following memory channel modes:
•
•
Independent Channel Mode
Mirrored Channel Mode – Provides Channel RAS feature
These channel modes are used in conjunction with the standard Memory Test (Built-in Self-Test
(BIST) and Memory Scrub engines to provide full RAS support.
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Functional Architecture
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Channel RAS feature is supported only if both CPU sockets are populated and support the right
population. For more information, refer to Section 3.3.9.
3.3.8.2
Independent Channel Mode
In the Independent Channel mode, you can populate multiple channels on any channel in any
order. The Independent Channel mode provides less RAS capability but better DIMM isolation
in case of errors. Moreover, it allows the best interleave mode possible and thereby increases
performance and thermal characteristics.
Adjacent slots on a DDR3 Channel from the Intel® Xeon® Processor 5500 series do not need
matching size and organization in independent channel mode. However, the speed of the
channel is configured to the maximum common speed of the DIMMs.
The Single Channel mode is established using the Independent Channel mode by populating
the DIMM slots from Channel A.
3.3.8.3
Mirrored Channel Mode
The Mirrored Channel mode is a RAS feature in which two identical images of memory channel
data are maintained, providing maximum redundancy. On the Intel® Xeon® Processor 5500
series based Intel® Workstation Board, the mirroring is achieved across channels. Active
channels hold the primary image and the other channels hold the secondary image of the
system memory. The integrated memory controller in the Intel® Xeon® Processor 5500 series
alternates between both channels for read transactions. Write transactions are issued to both
channels under normal circumstances. The mirrored image is a redundant copy of the primary
image; therefore, the system can continue to operate despite the presence of sporadic
uncorrectable errors, resulting in 100% data recovery.
In Mirrored Channel mode, channel A (or D) and channel B (or E) function as the mirrors, while
Channel C (or F) is unused. The effective system memory is reduced by at least one-half. For
example, if the system is operating in the Mirrored Channel mode and the total size of the DDR3
DIMMs is 2 GB, then the effective memory size is 1 GB because half of the DDR3 DIMMs are
the secondary images.
If Channel C (or F) is populated, the BIOS disables the Mirrored Channel mode. This is because
the BIOS will always give preference to the maximization of memory capacity over memory RAS
because RAS is an enhanced feature.
The BIOS provides a setup option to enable mirroring if the current DIMM population is valid for
the Mirrored Channel mode of operation. When memory mirroring is enabled, the BIOS
attempts to configure the memory system accordingly. If the BIOS finds the DIMM population is
unsuitable for mirroring, it falls back to the default Independent Channel mode with maximum
interleaved memory.
3.3.9
Memory Population and Upgrade Rules
Populating and upgrading the system memory requires careful positioning of the DDR3 DIMMs
based on the following factors:
ƒ
34
Current RAS mode of operation
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Functional Architecture
ƒ
Existing DDR3 DIMM population
ƒ
DDR3 DIMM characteristics
ƒ
Optimization techniques used by the Intel® Xeon® Processor 5500 Series to maximize
memory bandwidth
In the Independent Channel mode, all the DDR3 channels operate independently. Also, you can
use the Independent Channel mode to support single DIMM configuration in Channel A and in
the Single Channel mode.
You must observe and apply the following general rules when selecting and configuring memory
to obtain the best performance from the system:
1. Mixing RDIMMs and UDIMMs is not supported.
2. You must populate CPU1 socket first in order to enable and operate CPU2 socket.
3. When CPU2 socket is empty, DIMMs populated in slots D1 through F2 are unusable.
4. If both CPU sockets are populated, but Channels A through C are empty, the platform
can still function with remote memory in Channels D through F. However, platform
performance suffers latency due to remote memory.
5. Must always start populating DDR3 DIMMs in the first slot on each memory channel
(Memory slot A1, B1, C1, D1, E1, or F1). For example, if memory slot A1 is empty, slot
A2 is not available.
6. Must always populate the Quad-Rank DIMM starting with the first slot (Memory slot A1,
B1, C1, D1, E1, or F1) on each memory channel. For example, when installing one
Quad-Rank RDIMM with one Single- or Dual-Rank RDIMM in memory channel A, you
must populate the Quad-Rank RDIMM in slot A1.
7. If an installed DDR3 DIMM has faulty or incompatible SPD data, it is ignored during
memory initialization and is (essentially) disabled by the BIOS. If a DDR3 DIMM has no
or missing SPD information, the slot in which it is placed is treated as empty by the BIOS.
8. The memory operational mode is configurable at the channel level. The following two
modes are supported: Independent Channel Mode and Mirrored Channel Mode.
9. The BIOS selects the mode that enables all the installed memory by default. Since the
Independent Channel Mode enables all the channels simultaneously, this mode
becomes the default mode of operation.
10. When only CPU1 socket is populated, Mirrored Channel mode is selected only if the
DIMMs are populated to conform to that channel RAS mode. If it fails to comply with the
population rule, then the BIOS configures the CPU1 socket to default to the Independent
Channel mode.
11. If both CPU sockets are populated and the installed DIMMs are associated with both
CPU sockets, then Mirrored Channel Mode can only be selected if both the CPU
sockets are populated to conform to that mode. If either or both sockets fail to comply
with the population rule, the BIOS configures both the CPU sockets to default to the
Independent Channel mode.
12. DIMM parameters matching requirements for Mirrored Channel Mode is local to the CPU
socket. For example, while CPU1 memory channels A, B, and C have one match of
timing, technology and size, CPU 2 memory channels D, E, and F can have a different
match of the parameters, channel RAS still functions.
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13. The Minimal memory population possible is DIMM_A1. In this configuration, the system
operates in the Independent Channel Mode. Mirrored Channel Mode is not possible.
14. The minimal population upgrade recommended for enabling CPU 2 socket are
DIMM_A1 and DIMM_D1. This configuration supports only the Independent Channel
mode.
15. In the Mirrored Channel mode, memory population on Channels A and B should be
identical, including across adjacent slots on the channels, memory population on
Channels D and E should be identical, including across adjacent slots on the channels.
The DIMMs on successive slots are not required to be identical and can have different
sizes and/or timings, but the overall channel timing reduces according to the slowest
DIMM. If Channels A and B are not identical, or Channels D and E are not identical, the
BIOS selects default Independent Channel Mode.
16. If Channel C or F is not empty, the BIOS disables the Mirrored Channel Mode.
17. When only CPU1 socket is populated, minimal population upgrade for Mirrored Channel
Mode are DIMM_A1 and DIMM_B1. DIMM_A1 and DIMM_B1 must be identical,
otherwise, they will revert to Independent Channel Mode.
18. When both CPU sockets are populated, minimal population upgrade for the Mirrored
Channel Mode are DIMM_A1, DIMM_B1, DIMM_D1 and DIMM_E1. DIMM_A1 and
DIMM_B1 as a pair must be identical, and so must DIMM_D1 and DIMM_E1 as a pair.
The DIMMs on different CPU sockets need not be identical in size and/or sizing,
although overall channel timing reduces according to the slowest DIMM.
3.3.10
Supported Memory Configuration
3.3.10.1
Supported Memory Configurations
The following sections describe the memory configurations supported and validated on the
Intel® Workstation System SC5650SCWS.
3.3.10.1.1 Levels of support
The Intel® Workstation System SC5650SCWS supports the following categories of memory
configurations:
ƒ
ƒ
ƒ
Supported – These configurations were verified by Intel to work but only limited
validation was performed. Not all possible DDR3 DIMM configurations were validated
due to the large number of possible configuration combinations. Supported
configurations are highlighted in light gray in Tables 5 and 6.
Validated – These configurations received broad validation by Intel. Intel can provide
customers with information on specific configurations that were validated. Validated
configurations are highlighted in dark gray in Tables 5 and 6.
All populated DIMMs are identical.
The following is a description of the columns in Tables 5 and 6:
ƒ X – Indicates the DIMM is populated.
ƒ M – Indicates whether the configuration supports the Mirrored Channel mode of
operation. It is one of the following: Y indicating Yes; N indicating No.
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ƒ
Functional Architecture
N – Identifies the total number of DIMMs that constitute the given configuration.
Table 5. Supported DIMM Population under the Dual Processors Configuration
CPU1 Socket = Populated
#
N
1
1
X
2
2
X
3
2
X
4
2
X
5
3
X
6
3
X
7
3
X
8
4
X
A1
A2
B1
B2
C1
CPU2 Socket = Populated
C2
D1
D2
E1
E2
F1
F2
M
N
X
N
X
N
X
X
X
X
N
X
N
X
X
N
X
X
N
X
N
9
4
X
10
6
X
X
11
6
X
12
7
X
X
X
X
X
X
X
13
8
X
X
X
X
X
X
X
14
8
X
X
X
X
X
X
X
N
15
9
X
X
X
X
X
X
X
X
X
N
16
12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Y
X
X
Y
X
X
X
X
X
X
N
N
X
X
Y
X
X
N
Table 6. Supported DIMM Population under the Single Processor Configuration
CPU1 Socket = Populated
#
N
1
1
X
2
2
X
3
2
X
X
4
3
X
X
5
4
X
X
X
6
4
X
X
X
X
7
6
X
X
X
X
A1
A2
B1
B2
C1
CPU2 Socket = Empty
C2
D1
D2
E1
E2
F1
F2
M
N
X
N
Y
X
N
X
N
Y
X
X
N
Note: The generic principles and guidelines described in the previous sections also apply to
Tables 5 and 6.
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Functional Architecture
3.3.11
Intel® Workstation System SC5650SCWS TPS
Memory Error Handling
The BIOS classifies memory errors into the following categories:
38
ƒ
Correctable ECC errors: This correction could be the result of an ECC correction, a
successfully retried memory cycle, or both.
ƒ
Unrecoverable/Fatal ECC Errors: The ECC engine detects these errors but cannot
correct them.
ƒ
Address Parity Errors: An Address Parity Error is logged as such in the SEL, but in all
other ways, is treated the same as an Uncorrectable ECC Error.
Revision 1.2
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3.4
Functional Architecture
ICH10R
The ICH10R provides extensive I/O support. Functions and capabilities include:
ƒ
PCI Express* Base Specification, Revision 1.1 support
ƒ
PCI Local Bus Specification, Revision 2.3 support for 33-MHz PCI operations (supports
up to four REQ#/GNT# pairs)
ƒ
ACPI Power Management Logic Support, Revision 3.0a
ƒ
Enhanced DMA controller, interrupt controller, and timer functions
ƒ
Integrated Serial ATA host controllers with independent DMA operation on up to six
ports and AHCI support
ƒ
USB host interface with support for up to 12 USB ports; six UHCI host controllers; and
two EHCI high-speed USB 2.0 host controllers
ƒ
Integrated 10/100/1000 Gigabit Ethernet MAC with System Defense
ƒ
System Management Bus (SMBus) Specification, Version 2.0, with additional support for
I2C devices
ƒ
Low-Pin Count (LPC) interface support
ƒ
Firmware Hub (FWH) interface support
ƒ
Serial Peripheral Interface (SPI) support
3.4.1
Serial ATA Support
The ICH10R has an integrated Serial ATA (SATA) controller that supports independent DMA
operation on six ports and supports data transfer rates of up to 3.0 Gb/s. The six SATA ports on
the workstation board are numbered SATA-0 through SATA-5. You can enable/disable the
SATA ports and/or configure them by accessing the BIOS Setup utility during POST.
3.4.1.1
Intel® Embedded Server RAID Technology II Support
The Intel® Embedded Server RAID Technology II (Intel® ESRTII) feature provides RAID modes
0, 1, and 10. If RAID 5 is needed with Intel® ESRTII, you must install the optional Intel® RAID
Activation Key AXXRAKSW5 accessory. You must place this activation key on the SATA
Software RAID 5 connector located on the workstation board of Intel® Workstation System
SC5650SCWS. For installation instructions, refer to the documentation accompanying the
workstation board and the activation key.
When Intel® Embedded Server RAID Technology II of the SATA controller is enabled, enclosure
management is provided through the SATA_SGPIO connector on the workstation board when a
cable is attached between this connector and the backplane or I2C interface.
For the locations of Intel® RAID Activation Key connector and SATA SGPIO connector, refer to
Figure 2. Major Board Components.
Revision 1.2
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Intel® Workstation System SC5650SCWS TPS
Intel® Embedded Server RAID Technology II functionality requires the following items:
40
•
•
ICH10R I/O Controller Hub
Software RAID option is selected on BIOS menu for SATA controller
•
•
Intel® Embedded Server RAID Technology II Option ROM
Intel® Embedded Server RAID Technology II drivers, most recent revision
•
At least two SATA hard disk drives
Revision 1.2
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3.4.1.1.1
Functional Architecture
Intel® Embedded Server RAID Technology II Option ROM
The Intel® Embedded Server RAID Technology II for SATA Option ROM provides a pre-operating system user interface for the Intel®
Embedded Server RAID Technology II implementation and provides the ability to use an Intel® Embedded Server RAID Technology II
volume as a boot disk and detect any faults in the Intel® Embedded Server RAID Technology II volume(s).
3.4.1.2
Onboard SATA Storage Mode Matrix
Table 7. Onboard SATA Storage Mode Matrix
SW RAID = Intel® Embedded Server RAID Technology II (ESRTII)
Storage
Controller
Storage Mode*
Enhanced
Description
6 SATA ports at
Native mode
RAID Types and Levels
Supported
N/A
Driver
Chipset driver or
Operating System
embedded
RAID
Management
Software
RAID
Software
User’s Guide
N/A
N/A
N/A
N/A
SC5650SCWS
Compatible
Backplane
Broad OS Support
Compatibility
Onboard SATA
Controller
(ICH10R)
AHCI
SW RAID
6 SATA ports: port 0,
1, 2, 3 at IDE Legacy
mode, port 4, 5 at
Native mode
6 SATA ports using
the Advanced Host
Controller Interface
6 SATA Ports
N/A
Chipset driver or
Operating System
embedded
Broad OS Support
N/A
AHCI driver or
Operating System
embedded
AXX6DRV3GR
N/A
N/A
Broad OS Support
SW RAID 0/1/10
standard
SW RAID 5 with
optional AXXRAKSW5
ESRTII Driver
Microsoft
Windows* and
selected Linux*
Versions only
Intel® RAID Web
Console 2
Intel® RAID
Software
User’s Guide
* Select in BIOS Setup: “SATA Mode” Option on Advanced | Mass Storage Controller Configuration Screen
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Functional Architecture
3.4.2
Intel® Workstation System SC5650SCWS TPS
USB 2.0 Support
The USB controller functionality integrated into the ICH10R provides the workstation system
with an interface for up to 10 USB 2.0 ports. All ports are high-speed, full-speed, and low-speed
capable.
•
•
Four external connectors are located on the back edge of the workstation board.
Two internal 2x5 headers (J1D1 and J1D4) are provided; each is capable of supporting
two optional USB 2.0 ports.
•
One internal USB port type A connector (J1H2) is provided to support the installation of
a USB device inside the server chassis.
•
One internal low-profile 2x5 header (J1D3) is provided to support a low-profile USB Solid
State Drive.
Note: Each USB port supports a maximum 500 mA current. Only supports up to eight USB
ports to draw maximum current concurrently.
3.5
PCI Subsystem
The primary I/O buses for the Intel® Workstation System SC5650SCWS are PCI, PCI Express*
Gen1, and PCI Express* Gen2 with six independent PCI bus segments.
PCI Express* Gen1 and Gen2 are dual-simplex point-to point serial differential low-voltage
interconnects. A PCI Express* topology can contain a Host Bridge and several endpoints (I/O
devices). The signaling bit rate is 2.5 Gbit/s one direction per lane for Gen1 and 5.0 Gbit/s one
direction per lane for Gen2. Each port consists of a transmitter and receiver pair. A link between
the ports of two devices is a collection of lanes (x1, x2, x4, x8, x16, and so forth) All lanes within
a port must transmit data using the same frequency. The PCI buses comply with the PCI Local
Bus Specification, Revision 2.3.
The following tables list the characteristics of the PCI bus segments. Details about each bus
segment follow the table.
Table 8. Intel® Workstation System SC5650SCWS PCI Bus Segment Characteristics
PCI Bus Segment
PCI32
Voltage
5V
Width
32 bit
Speed
33 MHz
Type
PCI
ICH10R
PE1, PE2, PE3, PE4
ICH10R PCI
Express* Ports
PCI I/O Card Slots
PCI Slot 1;
IEEE 1394a Controller;
3.3 V
X4
10 Gb/s
PCI
Express*
Gen1
x4 PCI Express* Gen1 throughput to Slot 2
(x8 Mechanically) and SAS Module Slot
(Default to Slot 2, and switch to SAS Module
slot when Intel® SAS Entry RAID Module
AXX4SASMOD is detected)
This PCI Express* Gen1 slot is not available
when the SAS module slot is in use and vice
versa.
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PCI Bus Segment
PE5
Voltage
3.3 V
Width
X1
Speed
2.5 Gb/s
Type
PCI
Express*
Gen1
PCI I/O Card Slots
x1 PCI Express* Gen1 throughput to
onboard Integrated BMC
3.3 V
X1
2.5 Gb/s
PCI
Express*
Gen1
x1 PCI Express* Gen 1 throughput to Slot 3
(x4 Mechanically)
3.3 V
x4
10 Gb/s
PCI
Express*
Gen1
x4 PCI Express* Gen1 throughput to
onboard NIC (82575EB)
3.3 V
X16
80 Gb/S
PCI
Express*
Gen2
x16 PCI Express* Gen2 throughput to Slot 6
(x16 Mechanically)
3.3 V
X16
80 Gb/S
PCI
Express*
Gen2
x16 PCI Express* Gen2 throughput to Slot 4
(x16 Mechanically)
ICH10R PCI
Express* Port
PE6
ICH10R PCI
Express* Port
PE1, PE2
5520 IOH PCI
Express* Ports
PE3, PE4, PE5, PE6
5520 IOH PCI
Express* Ports
PE7, PE8, PE9,
PE10
5520 IOH PCI
Express* Ports
3.6
Functional Architecture
Intel® SAS Entry RAID Module AXX4SASMOD (Accessory)
The Intel® Workstation System SC5650SCWS provides a Serial Attached SCSI (SAS) module
slot (J2J1) for the installation of an optional Intel® SAS Entry RAID Module AXX4SASMOD.
Once the optional Intel® SAS Entry RAID Module AXX4SASMOD is detected, the x4 PCI
Express* links from the ICH10R to Slot 2 (x8 mechanically, x4 electrically) switches to the SAS
module slot.
The Intel® SAS Entry RAID Module AXX4SASMOD includes a SAS1064e controller that
supports x4 PCI Express* link widths and is a single-function PCI Express* end-point device.
The SAS controller supports the SAS protocol as described in the Serial Attached SCSI
Standard, version 1.0, and also supports SAS 1.1 features. A 32-bit external memory bus off the
SAS1064e controller provides an interface for Flash ROM and NVSRAM (Non-volatile Static
Random Access Memory) devices.
The Intel® SAS Entry RAID Module AXX4SASMOD provides four SAS connectors that support
up to four hard drives with a non-expander backplane or up to eight hard drives with an
expander backplane.
The Intel® SAS Entry RAID Module AXX4SASMOD also provides a SGPIO (Serial General
Purpose Input / Output) connector and a SCSI Enclosure Services (SES) connector for
backplane drive LED control.
Warning! Either the SGPIO or the SES connector supports backplane drive LED control. Do not
connect both SGPIO and SES connectors at the same time.
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Intel® Workstation System SC5650SCWS TPS
Figure 21. Intel® SAS Entry RAID Module AXX4SASMOD Component and Connector Layout
3.6.1
SAS RAID Support
The BIOS Setup Utility provides drive configuration options on the Advanced | Mass Storage
Controller Configuration setup page for the Intel® SAS Entry RAID Module AXX4SASMOD,
some of which affect the ability to configure RAID.
The “Intel® SAS Entry RAID Module” option is enabled by default once the Intel® SAS Entry
RAID Module AXX4SASMOD is present. When enabled, you can set the “Configure Intel® SAS
Entry RAID Module” to either “LSI* Integrated RAID” or “Intel® ESRTII” mode.
Table 9. Intel® SAS Entry RAID Module AXX4SASMOD Storage Mode
SW RAID = Intel® Embedded Server RAID Technology II (ESRTII)
IT/IR RAID = IT/IR RAID, Entry Hardware RAID
Storage
Mode*
Description
4 SAS Ports
IT/IR RAID
Up to 10 SAS or
SATA drives via
expander
backplanes
RAID Types and Levels
Supported
Native SAS pass through
mode without RAID
function.
Entry Hardware RAID.
- RAID 1 (IM mode)
- RAID 10/10E (IME
mode)
-
RAID 0 (IS Mode)
Driver
SAS MPT
driver (Fully
opensource
driver)
RAID
Management
Software
Intel® RAID Web
Console 2
RAID Software
User’s Guide
IT/IR RAID
Software
User’s Guide
Broad OS
support.
Compatible
Backplane
AXX6DRV3GR
AXX6DRV3GEXP
4 SAS Ports
SW RAID
Up to 8 SAS or
SATA drives via
expander
backplanes
SW RAID 0/1/10 standard
SW RAID 5 with optional
AXXRAKSW5
ESRTII
Driver
Intel® RAID Web
Console 2
Intel® RAID
Software
User’s Guide
*Select in BIOS Setup: “Configure Intel® SAS Entry RAID” Option on Advanced | Mass Storage Controller Configuration
Screen
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3.6.1.1
Functional Architecture
IT/IR RAID Mode
Supports entry hardware RAID 0, RAID 1, and RAID 1E and native SAS pass through mode.
Intel® ESRTII Mode
3.6.1.2
The Intel® Embedded Server RAID Technology II (Intel® ESRTII) feature provides RAID modes
0, 1, and 10. If RAID 5 is needed with Intel® ESRTII, you must install the optional Intel® RAID
Activation Key AXXRAKSW5 accessory. This activation key is placed on the SAS Software
RAID 5 connector located on the Intel® SAS Entry RAID Module AXX4SASMOD. For installation
instructions, refer to the documentation included with the SAS Module AXX4SASMOD and the
activation key.
When Intel® Embedded Server RAID Technology II is enabled with the SAS Module
AXX4SASMOD, enclosure management is provided through the SAS_SGPIO or SES connector
on the SAS Module AXX4SASMOD when a cable is attached between this connector and the
backplane or I2C interface.
3.7
Baseboard Management Controller
The Intel® Workstation System SC5650SCWS has an integrated BMC controller based on
ServerEngines* Pilot II. The BMC controller is provided by an embedded ARM9 controller and
associated peripheral functionality required for IPMI-based server management.
The following is a summary of the BMC management hardware features used by the BMC:
•
250 MHz 32-bit ARM9 Processor
•
•
Memory Management Unit (MMU)
Two 10/100 Ethernet Controllers with NC-SI support
•
•
16-bit DDR2 667 MHz interface
Dedicated RTC
•
•
•
12 10-bit ADCs
Eight Fan Tachometers
Four PWMs
•
•
Battery-backed Chassis Intrusion I/O Register
JTAG Master
•
•
Six I2C interfaces
General-purpose I/O Ports (16 direct, 64 serial)
Additionally, the BMC integrates a super I/O module with the following features:
•
•
•
Keyboard style/BT interface
Two 16550-compatible serial ports
Serial IRQ support
•
•
16 GPIO ports (shared with the BMC)
LPC to SPI bridge for system BIOS support
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•
Intel® Workstation System SC5650SCWS TPS
SMI and PME support
The BMC also contains an integrated KVMS subsystem and graphics controller with the
following features:
•
USB 2.0 for Keyboard, Mouse, and Storage devices
•
•
USB 1.1 interface for legacy PS/2 to USB bridging.
Hardware Video Compression for text and graphics
•
•
Hardware encryption
2D Graphics Acceleration
•
•
DDR2 graphics memory interface
Up to 1600x1200 pixel resolution
•
PCI Express* x1 support
Figure 22. Integrated BMC Hardware
3.7.1
BMC Embedded LAN Channel
The BMC hardware includes two dedicated 10/100 network interfaces:
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Functional Architecture
Interface 1: This interface is available from either of the available NIC ports in system that can
be shared with the host. Only one NIC may be enabled for management traffic at any time. The
default active interface is onboard NIC1.
Interface 2: This interface is available from Intel® Remote Management Module 3 (Intel®
RMM3), which is a dedicated management NIC and not shared with the host.
For these channels, you can enable support for IPMI-over-LAN and DHCP.
For security reasons, embedded LAN channels have the following default settings:
ƒ
IP Address: Static
ƒ
All users disabled
You cannot place IPMI-enabled network interfaces on the same subnet. This includes the Intel
RMM3’s onboard network interface and either of the BMC’s embedded network interfaces.
3.8
Serial Ports
The workstation board provides two serial ports: an external RJ-45 serial port and an internal
DH-10 serial header.
The rear RJ-45 serial A port is a fully-functional serial port that can support any standard serial
device. To allow support for either of the two serial port configuration standards, you must
appropriately configure a jumper block (J4B2) according to the needed standard. For serial
devices that require a DCD signal, you must configure the jumper block with the serial port
jumper over pins 2 and 3. For serial devices that require a DSR signal (Default), you must
configure the jumper block with the serial port jumper over pins 1 and 2.
Note: By default, the rear RJ-45 serial port is configured to support a DSR signal.
Table 10. Serial A Port Configuration Jumper Pin-out
Pins
1-2
3-4
What happens at system reset…
Rear RJ-45 Serial A port is configured for DSR to DTR (default)
Rear RJ-45 Serial A port is configured for DCD to DTR
For applications that require a DB9 serial connector, you must use an 8-pin RJ45-to-DB9
adapter (Accessory AXXRJ45DB92). The following table provides the pin-out required for the
adapter to provide RS232 support.
Table 11. Rear Serial A Port RJ-45 to DB9 Pin-out
RJ-45 Pins
1
2
3
4
5
Signal
Request to Send
Data Terminal Ready
Transmitted Data
Signal Ground
Ring Indicator
Abbreviation
RTS
DTR
TD
SGND
RI
Revision 1.2
Intel order number: E81822-002
DB9 pins
7
4
3
5
9
47
Functional Architecture
RJ-45 Pins
6
7
8
Intel® Workstation System SC5650SCWS TPS
Signal
Received Data
DCD or DSR
Clear To Send
Abbreviation
RD
DCD/DSR
CTS
DB9 pins
2
1 or 6 (refer note)
8
Note: The RJ45-to-DB9 adapter should match the configuration of the serial device used. One
of two pin-out configurations is used, depending on whether the serial device requires a DSR or
DCD signal. The final adapter configuration should also match the desired pin-out of the RJ-45
connector, as you can also configure it to support either DSR or DCD.
Serial B is an optional port that is accessed through a 9-pin internal DH-10 header. You can use
a standard DH-10 to DB9 cable to direct serial B to the rear of a chassis. The serial B interface
follows the standard RS232 pin-out as defined in the following table.
Table 12. Serial B Header Pin-out
3.9
Pins
1
Signal Name
DCD
2
DSR
3
RX
4
RTS
5
TX
6
CTS
7
DTR
8
RI
9
GND
Serial Port B Header Pin-out
Error! Objects cannot be created from
editing field codes.
Floppy Disk Controller
The Intel® Workstation System SC5650SCWS does not support a floppy disk controller interface.
However, the system BIOS recognizes USB floppy devices.
3.10 Keyboard and Mouse Support
The Intel® Workstation System SC5650SCWS does not support PS/2* interface keyboards and
mice. However, the system BIOS recognizes USB Specification-compliant keyboards and mice.
3.11 Video Support
The Intel® Workstation System SC5650SCWS integrated BMC includes a 2D SVGA video
controller and 8 MB video memory.
The 2D SVGA subsystem supports a variety of modes, up to 1600 x 1200 resolution in 8/16 bpp.
It also supports both CRT and LCD monitors with up to a 85-Hz vertical refresh rate.
You access onboard video using an optional accessory cable (FXXSCVDCBL), which provides
a standard 15-pin VGA connector. You can disable the onboard video controller using the BIOS
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Functional Architecture
Setup Utility or when an add-in video card is detected. The system BIOS provides the option for
Dual Monitor Video operation when an add-in video card is configured in the system.
3.11.1
Video Modes
The integrated video controller supports all standard IBM* VGA modes. The following table
shows the 2D modes supported for both CRT and LCD.
Table 13. Video Modes
2D Video Mode Support
2D Mode
640 x 480
800 x 600
1024 x 768
1152 x 864
1280 x 1024
1440 x 900
1600 x 1200
3.11.2
8 bpp
16 bpp
24 bpp
32 bpp
Supported
Supported
Supported
Supported
60, 72, 75, 85
60, 72, 75, 85
60, 72, 75, 85
60, 72, 75, 85
Supported
Supported
Supported
Supported
56, 60, 72, 75, 85
56, 60, 72, 75, 85
56, 60, 72, 75, 85
56, 60, 72, 75, 85
Supported
Supported
Supported
Supported
60, 70, 75, 85
60, 70, 75, 85
60, 70, 75, 85
60, 70, 75, 85
Supported
Supported
Supported
N/A
75
75
75
N/A
Supported
Supported
Supported
N/A
60, 75, 85
60, 75, 85
60
NA
Supported
Supported
Supported
N/A
60
60
60
NA
Supported
Supported
N/A
N/A
60. 65, 70, 75, 85
60. 65, 70
N/A
N/A
Refresh Rate (Hz)
Refresh Rate (Hz)
Refresh Rate (Hz)
Refresh Rate (Hz)
Refresh Rate (Hz)
Refresh Rate (Hz)
Refresh Rate (Hz)
Dual Video
The BIOS supports single- and dual-video modes. The dual-video mode is enabled by default.
ƒ
In single mode, the onboard video controller is disabled when an add-in video card is
detected.
ƒ
In dual mode (enable “Dual Monitor Video” in BIOS setup), the onboard video controller
is enabled and is the primary video device. The add-in video card is allocated resources
and considered the secondary video device.
ƒ
The BIOS Setup utility provides options on Advanced | PCI Configuration Screen to
configure the feature as follows:
Onboard Video
Enabled (default)
Disabled
Enabled
Dual Monitor Video
Shaded if onboard video is set to "Disabled"
Disabled (Default)
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Functional Architecture
3.11.3
Intel® Workstation System SC5650SCWS TPS
Graphics Card Population Guide
Table 14. Graphics Card Population
Graphics Card Support
One graphics card with maximum 300-W power in PCI Express* slot 6, or up to two graphics cards with maximum 150W power in PCI Express* slots 4 and 6.
Keep PCI Express* Slot 3 empty for optimal air flow when populating a graphics card in PCI Express* slot 4.
Note: Please follow the installation guide accompanying your graphics card for the power
connection and using the power adapter cable accompanying your graphics card (if any).
Graphics cards with power greater than 75-W must be self-cooled with exhaust out the back of
the chassis.
ATI* CrossFire* technology is considered fully validated by Intel workstation validation, Intel
validation may not meet all of ATI prescribed CrossFire* test requirements (if any).
3.12 Network Interface Controller (NIC)
The Intel® Workstation System SC5650SCWS provides dual onboard LAN ports with support for
10/100/1000 Mbps operation. The two LAN ports are based on the onboard Intel® 82575EB
controller, which is a single, compact component with two fully integrated GbE Media Access
Control (MAC) and Physical Layer (PHY) ports.
The Intel® 82575EB controller provides a standard IEEE 802.3 Ethernet interface for
1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab) and is
capable of transmitting and receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps.
Each network interface controller (NIC) port provides two LEDs:
50
ƒ
Link / activity LED (at the left of the connector): Indicates network connection when on,
and transmit / receive activity when blinking.
ƒ
The speed LED (at the right of the connector) indicates 1000-Mbps operation when
amber; 100-Mbps operation when green; and 10-Mbps when off. The following table
provides an overview of the LEDs.
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Functional Architecture
Table 15. Onboard NIC Status LED
LED Color
Green (Left)
Off / Green / Amber (Right)
3.12.1
LED State
NIC State
On
Active Connection
Blinking
Transmit / Receive activity
Off
10 Mbps
Green
100 Mbps
Amber
1000 Mbps
MAC Address Definition
®
Each Intel Workstation System SC5650SCWS has the following four MAC addresses assigned
to it at the Intel factory.
NIC 1 MAC address
ƒ NIC 2 MAC address - is assigned the NIC 1 MAC address +1
ƒ BMC LAN Channel MAC address – is assigned the NIC 1 MAC address +2
ƒ Intel® Remote Management Module 3 (Intel® RMM3) MAC address – is assigned the
NIC 1 MAC address +3
During the manufacturing process, each workstation system has a white MAC address sticker
placed on the top of the NIC 1 port. The sticker displays the NIC 1 MAC address and Intel®
RMM3 MAC address in both bar code and alphanumeric formats.
ƒ
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3.13 Audio Codec
The workstation system supports the Intel® High Definition audio subsystem based on the
Realtek* ALC889 audio codex.
The feature list for the ALC889 is as follows:
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
High-performance DACs with 108dB signal-to-noise ratio (A-weighting)
High-performance ADCs with 104dB signal-to-noise ration (A-weighting)
Meets Microsoft* WLP3.0x and future WLP4.0 Premium audio requirements
Ten DAC channels support 16/20/24-bit PCM format for 7.1 sound playback plus two
channels of concurrent independent stereo sound output (multiple streaming) through
the front panel output
Three stereo ADCs support 16/20/24-bit PCM format, multiple stereo recording
All DACs support 44.1k/48k/88.2k/96k/192kHz sample rates
All ADCs support 44.1k/48k/88.2k/96k/192kHz sample rates
Primary 16/20/24-bit S/PDIF-OUT supports 32k/44.1k/48k/88.2k/96k/192kHz sample
rates
Supports 44.1k/48k/96kHz ADAT digital output (Pin shared with S/PDIF-OUT)
All High-quality analog differential CD input
Supports external PCBEEP input and built-in digital BEEP generator
Up to four channels of microphone array input are supported for AEC/BF applications
Two jack detection pins, each designed to detect up to four plugged-in jacks
Supports analog GPIO2 for jack detection of CD input, which is used as a 9th analog port
Supports legacy analog mixer architecture
Three GPIOs (General Purpose Input and Output) for customized applications
Supports mono and stereo digital microphone interfaces (pins shared with GPIO0 and
GPIO1)
Hardware Zero-Detect output volume control
1 dB per step output volume and input volume control
The Intel® Workstation System SC5650SCWS provides one external audio connections through
the rear I/O and supports the following audio connection inside the chassis.
ƒ
ƒ
52
2x5-pin Audio Header (J8A1)
3-pin S/PDIF Out Header (J4C1)
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Intel® Workstation System SC5650SCWS TPS
Functional Architecture
3.14 IEEE 1394a Support
The Intel® Workstation System SC5650SCWS provides two IEEE 1394a ports via a Texas
Instruments* TSB43AB22A: an external 6-pin IEEE 1394a port through rear I/O panel and an
internal 2x5 pin IEEE 1394a port.
Both of the 1394 ports are capable of transferring data between the 32-bit/33-MHz PCI bus and
the 1394 bus at 100M bits/s, 200M bits/s, and 400M bits/s.
Note: Boot from IEEE 1394a device is not supported by the Intel® Workstation System
SC5650SCWS.
The feature list for the Texas Instruments* TSB43AB22A is as follows:
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial bus
and IEEE Std 1394a-2000.
Fully interoperable with FireWire and i.LINK implementations of IEEE Std 1394.
Compliant with Intel Mobile Power Guideline 2000.
Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset,
multi-speed concatenation, arbitration acceleration, fly-by concatenation, and port
disable/suspend/resume.
Power-down features to conserve energy in battery-powered applications include:
automatic device power down during suspend, PCI power management for link-layer,
and inactive ports powered down.
Ultralow-power sleep mode
Two IEEE Std 1394a-2000 fully compliant cable ports at 100M bits/s, 200M bits/s, and
400M bits/s.
Cable ports monitor line conditions for active connection to remote node.
Cable power presence monitoring.
Separate cable bias (TPBIAS) for each port.
1.8-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI
signaling environments.
Physical write posting of up to three outstanding transactions.
PCI burst transfers and deep FIFOs to tolerate large host latency.
PCI_CLKRUN protocol
External cycle timer control for customized synchronization.
Extended resume signaling for compatibility with legacy DV components.
PHY-Link logic performs system initialization and arbitration functions.
PHY-Link encode and decode functions included for data-strobe bit level encoding.
PHY-Link incoming data resynchronized to local clock.
Low-cost 24.576-MHz crystal provides transmit and receive data at 100M bits/s,
200M bits/s, and 400M bits/s.
Node power class information signaling for system power management.
Serial ROM interface supports 2-wire serial EEPROM devices.
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Two general-purpose I/Os
Register bits provide software control of contender bit, power class bits, link active
control bit, and IEEE Std 1394a-2000 features.
Fabricated in advanced low-power CMOS process.
PCI and CardBus register support.
Isochronous receive dual-buffer mode.
Out-of-order pipelining for asynchronous transmit requests.
Register access fail interrupt when the PHY SCLK is not active.
PCI power-management D0, D1, D2, and D3 power states.
Initial bandwidth available and initial channels available registers.
PME support per 1394 Open Host Controller Interface Specification.
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
3.15 Trusted Platform Module (TPM)
3.15.1
Overview
Trusted Platform Module (TPM) is a hardware-based security device that addresses the growing
concern on boot process integrity and offers better data protection. TPM protects the system
start-up process by ensuring it is tamper-free before releasing system control to the operating
system. A TPM device provides secured storage to store data, such as security keys and
passwords. In addition, a TPM device has encryption and hash functions. The Intel®
Workstation System SC5650SCWS implements TPM as per TPM PC Client specifications
revision 1.2 by the Trusted Computing Group (TCG).
A TPM device is affixed to the motherboard of the server and is secured from external software
attacks and physical theft. A pre-boot environment, such as the BIOS and operating system
loader, uses the TPM to collect and store unique measurements from multiple factors within the
boot process to create a system fingerprint. This unique fingerprint remains the same unless the
pre-boot environment is tampered with. Therefore, it is used to compare to future
measurements to verify the integrity of the boot process.
After the BIOS completes the measurement of its boot process, it hands off control to the
operating system loader and in turn to the operating system. If the operating system is TPMenabled, it compares the BIOS TPM measurements to those of previous boots to make sure the
system was not tampered with before continuing the operating system boot process. Once the
operating system is in operation, it optionally uses TPM to provide additional system and data
security (for example, Microsoft Vista* supports Bitlocker drive encryption).
3.15.2
TPM security BIOS
The BIOS TPM support conforms to the TPM PC Client Specific – Implementation Specification
for Conventional BIOS, version 1.2, and to the TPM Interface specification, version 1.2. The
BIOS adheres to the Microsoft Vista* BitLocker requirement. The role of the BIOS for TPM
security includes the following:
54
-
Measures and stores the boot process in the TPM microcontroller to allow a TPM
enabled operating system to verify system boot integrity.
-
Produces EFI and legacy interfaces to a TPM-enabled operating system for using TPM.
Revision 1.2
Intel order number: E81822-002
Intel® Workstation System SC5650SCWS TPS
Functional Architecture
-
Produces ACPI TPM device and methods to allow a TPM-enabled operating system to
send TPM administrative command requests to the BIOS.
-
Verifies operator physical presence. Confirms and executes operating system TPM
administrative command requests.
-
Provides BIOS Setup options to change TPM security states and to clear TPM ownership.
For additional details, refer to the TCG PC Client Specific Implementation Specification, the
TCG PC Client Specific Physical Presence Interface Specification, and the Microsoft BitLocker*
Requirement documents.
3.15.2.1
Physical Presence
Administrative operations to the TPM require TPM ownership or physical presence indication by
the operator to confirm the execution of administrative operations. The BIOS implements the
operator presence indication by verifying the setup Administrator password.
A TPM administrative sequence invoked from the operating system proceeds as follows:
1. User makes a TPM administrative request through the operating system’s security software.
2. The operating system requests the BIOS to execute the TPM administrative command
through TPM ACPI methods and then resets the system.
3. The BIOS verifies the physical presence and confirms the command with the operator.
4. The BIOS executes TPM administrative command(s), inhibits BIOS Setup entry and boots
directly to the operating system which requested the TPM command(s).
3.15.2.2
TPM Security Setup Options
The BIOS TPM Setup allows the operator to view the current TPM state and to carry out
rudimentary TPM administrative operations. Performing TPM administrative options through the
BIOS setup requires TPM physical presence verification.
Using BIOS TPM Setup, the operator can turn ON or OFF TPM functionality and clear the TPM
ownership contents. After the requested TPM BIOS Setup operation is carried out, the option
reverts to No Operation.
The BIOS TPM Setup also displays the current state of the TPM, whether TPM is enabled or
disabled and activated or deactivated. Note that while using TPM, a TPM-enabled operating
system or application may change the TPM state independent of the BIOS setup. When an
operating system modifies the TPM state, the BIOS Setup displays the updated TPM state.
The BIOS Setup TPM Clear option allows the operator to clear the TPM ownership key and
allows the operator to take control of the system with TPM. You use this option to clear security
settings for a newly initialized system or to clear a system for which the TPM ownership security
key was lost.
3.15.2.3
Security Screen
The Security screen provides fields to enable and set the user and administrative passwords
and to lock out the front panel buttons so they cannot be used. The Intel® Workstation System
Revision 1.2
Intel order number: E81822-002
55
Functional Architecture
Intel® Workstation System SC5650SCWS TPS
SC5650SCWS provides TPM settings through the security screen.
To access this screen from the Main screen, select the Security option.
Main
Advanced
Security
Server Management
Administrator Password Status
<Installed/Not Installed>
User Password Status
<Installed/Not Installed>
Set Administrator Password
[1234aBcD]
Set User Password
[1234aBcD]
Front Panel Lockout
Enabled / Disabled
TPM State
TPM Administrative Control
Boot Options
Boot Manager
<Enabled & Activated/Enabled & Deactivated/Disabled &
Activated/Disabled & Deactivated>
No Operation / Turn On / Turn Off / Clear Ownership
Figure 23. Setup Utility – TPM Configuration Screen
Table 16. Setup Utility – Security Configuration Screen Fields
Setup Item
56
Options
Help Text
Comments
Revision 1.2
Intel order number: E81822-002
Intel® Workstation System SC5650SCWS TPS
Setup Item
TPM State*
Options
Enabled and Activated
Functional Architecture
Help Text
Enabled and Deactivated
Disabled and Activated
Comments
Information only.
Shows the current TPM device state.
A disabled TPM device will not
execute commands that use TPM
functions and TPM security
operations will not be available.
Disabled and Deactivated
An enabled and deactivated TPM is
in the same state as a disabled TPM
except setting of TPM ownership is
allowed if not present already.
An enabled and activated TPM
executes all commands that use TPM
functions and TPM security
operations will be available.
TPM
Administrative
Control**
No Operation
Turn On
[No Operation] - No changes to current
state.
Turn Off
[Turn On] - Enables and activates TPM.
Clear Ownership
[Turn Off] - Disables and deactivates
TPM.
[Clear Ownership] - Removes the TPM
ownership authentication and returns
the TPM to a factory default state.
Note: The BIOS setting returns to [No
Operation] on every boot cycle by
default.
3.16 ACPI Support
The Intel® Workstation System supports S0, S1, S3, and S5 states. S1 is considered a sleep
state.
The wake-up sources are enabled by the ACPI operating systems with cooperation from the
drivers; the BIOS has no direct control over the wake-up sources when an ACPI operating
system is loaded. The role of the BIOS is limited to describing the wake-up sources to the
operating system.
The S5 state is equivalent to the operating system shutdown. No system context is saved when
going into S5.
3.17 Intel® Virtualization Technology
Intel® Virtualization Technology is designed to support multiple software environments sharing
same hardware resources. Each software environment may consist of an operating system and
applications. You can enable or disable the Intel® Virtualization Technology in the BIOS Setup.
The default behavior is disabled.
Revision 1.2
Intel order number: E81822-002
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Functional Architecture
Intel® Workstation System SC5650SCWS TPS
Note: After changing the Intel® Virtualization Technology option (disable or enable) in the BIOS
setup, users must perform an AC power cycle before the change takes effect.
3.17.1
Intel® Virtualization Technology for Directed IO (VT-d)
The Intel® Workstation System SC5650SCWS supports DMA remapping from inbound PCI
Express* memory Guest Physical Address (GPA) to Host Physical Address (HPA). PCI devices
are directly assigned to a virtual machine leading to a robust and efficient virtualization.
You can enable or disable the Intel® Virtualization Technology for Directed I/O in the BIOS
Setup. The default behavior is disabled.
Note: After changing the Intel® Virtualization Technology for Directed I/O options (disable or
enable) in the BIOS setup, users must perform an AC power cycle before the changes take
effect.
3.18 Intel® I/O Acceleration Technology
The Intel® Workstation System SC5650SCWS supports Intel® I/O Acceleration Technology by
default. The supported Intel® I/O Acceleration Technology version varies with the network
interface card controllers that attached to the server board, Intel® I/O Acceleration Technology
version 2 (IOAT-2) is supported with onboard Intel® 82575EB NICs.
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Revision 1.2
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Intel® Workstation System SC5650SCWS TPS
4.
Power Sub-system
4.1
1000-W Power Supply
Power Sub-system
The 1000-W specification defines a non-redundant power supply that supports entry server
systems. This 1000-W power supply has 8 outputs: 3.3V, 5V, 12V1, 12V2, 12V3, 12V4, -12V
and 5VSB. The power supply contains a single 80-mm fan for cooling the power supply and part
of the system.
Revision 1.2
Intel order number: E81822-002
59
Power Sub-system
4.1.1
60
Intel® Workstation System SC5650SCWS TPS
Mechanical Overview
Revision 1.2
Intel order number: E81822-002
Intel® Workstation System SC5650SCWS TPS
Power Sub-system
Figure 24. Mechanical Drawing of the 1000-W Power Supply Enclosure
Revision 1.2
Intel order number: E81822-002
61
Power Sub-system
4.1.2
Intel® Workstation System SC5650SCWS TPS
Airflow Requirements
The power supply incorporates one 80-mm fan for self-cooling and system cooling. The fan
provides no less than 14 CFM airflow through the power supply when installed in the system.
The cooling air enters the power module from the non-AC side.
4.1.3
Acoustic Requirements
The declared sound power level of the power supply assembly does not exceed the levels
specified in the following table.
Table 17. Sound Power Requirement
Operating Conditions
% of Maximum Loading
Condition
100%
LwAd (BA)
Maximum
Inlet Temperature
Condition
45ºC
Operating
40°C
60%
4.7
Idle
35°C
40%
4.0
6.5
The declared sound power level is measured according to ECMA 74 and reported according to
ECMA 109. The fan RPM settings for the two operating conditions are determined through
thermal analysis and/or testing prior to the sound power level measurement. To measure the
power supply assembly sound power levels corresponding to the two operating conditions, the
fan in the power supply assembly is powered externally to the two RPM settings. The 45°
Celcius inlet temperature is derived based on standard system ambient temperature
assumptions (25° Celcius and 35° Celcius), typical temperature rise within the system, and
thermal impact of fan speed control.
Pure Tones: The power supply assembly does not produce any prominent discrete tones, as
determined according to ECMA 74, Annex D.
4.1.4
Temperature Requirements
The power supply operates within all specified limits over the Top temperature range. All airflow
passes through the power supply and not over the exterior surfaces of the power supply.
Table 18. Thermal Requirements
Item
Top
Description
Operating temperature range.
MIN
0
MAX
45
Units
°C
Tnon-op
Item
Altitude
Non-operating temperature range.
Description
Maximum operating altitude
-40
MIN
70
MAX
1500
°C
Units
m
The power supply meets UL enclosure requirements for temperature rise limits. All sides of the
power supply, with exception of the air exhaust side, are classified as “Handle, knobs, grips, etc.,
held for short periods of time only.”
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Intel® Workstation System SC5650SCWS TPS
4.1.4.1
Power Sub-system
AC Input Connector
The AC input connector is an IEC 320 C-14 power inlet. This inlet is rated for 15A/250VAC.
4.1.4.2
LED Marking and Identification
The LED is green or amber when lit. The LED is labeled with the two symbols as illustrated:
Power Symbol
Fail Symbol
!
Figure 25. LED Markings
4.1.5
AC Input Voltage Requirements
4.1.5.1
AC Input Voltage Specification
The power supply operates within all specified limits over the input voltage range shown in the
following table. Harmonic distortion of up to 10% of the rated line voltage must not cause the
power supply to go out of specified limits. The power supply does power off if the AC input is
less than 75VAC +/-5VAC range. The power supply starts up if the AC input is greater than
85VAC +/-4VAC. Application of an input voltage below 85VAC does not cause damage to the
power supply, including a fuse blow.
Table 19. AC Input Rating
Parameter
MIN
Rated
VMAX
IMAX
Start up VAC
Voltage (110)
90 Vrms
100-127 Vrms
140 Vrms
15 A1,3
85VAC
4VAC
Voltage (220)
180 Vrms
200-240 Vrms
264 Vrms
7 A2,3
Revision 1.2
Intel order number: E81822-002
+/-
Power Off
VAC
75VAC
+/5VAC
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Power Sub-system
Intel® Workstation System SC5650SCWS TPS
Parameter
MIN
Rated
VMAX
Frequency
47 Hz
50/60
63 Hz
1.
2.
3.
IMAX
Start up VAC
Power Off
VAC
Maximum input current at low input voltage range is measured at 90VAC, at max load.
Maximum input current at high input voltage range is measured at 180VAC, at max load.
This requirement is not used for determining agency input current markings.
4.1.5.2
AC Line Transient Specification
AC line transient conditions are defined as “sag” and “surge” conditions. “Sag” conditions are
also commonly referred to as “brownout,” and are defined as AC line voltage drops below
nominal voltage conditions. “Surge” is defined as AC line voltage rises above nominal voltage
conditions.
The power supply meets requirements under the following AC line sag and surge conditions.
Table 20. AC Line Sag Transient Performance
Duration
Continuous
Sag
10%
Operating AC Voltage
Nominal AC Voltage ranges
Line Frequency
50/60Hz
Loading
100%
0 to 1 AC
cycle
> 1 AC cycle
100%
Nominal AC Voltage ranges
50/60Hz
60%
> 10%
Nominal AC Voltage ranges
50/60Hz
100%
Performance Criteria
No loss of function or
performance
No loss of function or
performance
Loss of function
acceptable, self
recoverable
Table 21. AC Line Surge Transient Performance
Duration
Continuous
0 to ½ AC
cycle
4.1.5.3
Surge
10%
30%
Operating AC Voltage
Nominal AC Voltages
Mid-point of nominal AC
Voltages
Line Frequency
50/60Hz
50/60Hz
Performance Criteria
No loss of function or performance
No loss of function or performance
Susceptibility Requirements
The power supply meets the following electrical immunity requirements when connected to a
cage with an external EMI filter that meets the criteria defined in the SSI document EPS Power
Supply Specification.
Table 22. Performance Criteria
Level
A
B
C
64
Description
The apparatus shall continue to operate as intended. No degradation of performance.
The apparatus shall continue to operate as intended. No degradation of performance
beyond spec limits.
Temporary loss of function is allowed provided the function is self-recoverable or can
be restored by the operation of the controls.
Revision 1.2
Intel order number: E81822-002
Intel® Workstation System SC5650SCWS TPS
4.1.5.3.1
Power Sub-system
Electrostatic Discharge Susceptibility
The power supply complies with the limits defined in EN 55024: 1998 using the IEC 61000-42:1995 test standard and performance criteria B defined in Annex B of CISPR 24.
4.1.5.3.2
Fast Transient/Burst
The power supply complies with the limits defined in EN55024: 1998 using the IEC 61000-44:1995 test standard and performance criteria B defined in Annex B of CISPR 24.
4.1.5.3.3
Radiated Immunity
The power supply complies with the limits defined in EN55024: 1998 using the IEC 61000-43:1995 test standard and performance criteria A defined in Annex B of CISPR 24.
4.1.5.3.4
Surge Immunity
The power supply is tested with the system for immunity to AC Ringwave and AC Unidirectional
wave, both up to 2kV, per EN 55024:1998, EN 61000-4-5:1995 and ANSI C62.45: 1992.
The pass criteria include: no unsafe operation is allowed under any condition; all power supply
output voltage levels must stay within proper specification levels; no change in operating state
or loss of data during and after the test profile; no component damage under any condition.
The power supply complies with the limits defined in EN55024: 1998 using the IEC 61000-45:1995 test standard and performance criteria B defined in Annex B of CISPR 24.
4.1.5.4
AC Line Fast Transient (EFT) Specification
The power supply meets the EN61000-4-5 directive and any additional requirements in
IEC1000-4-5: 1995 and the Level 3 requirements for surge-withstand capability, with the
following conditions and exceptions:
ƒ
ƒ
ƒ
These input transients do not cause any out-of-regulation conditions, such as overshoot
and undershoot, nor do they cause any nuisance trips of any of the power supply
protection circuits.
The surge-withstand test must not produce damage to the power supply.
The supply meets surge-withstand conditions under maximum and minimum DC-output
load conditions.
4.1.5.5
AC Line Dropout / Holdup
Table 23. AC Line Dropout / Holdup
Output Wattage
1000W
Loading
75%
Holdup time
20 ms
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Power Sub-system
Intel® Workstation System SC5650SCWS TPS
An AC line dropout is defined to be when the AC input drops to 0VAC at any phase of the AC
line for any length of time. During an AC dropout, the power supply meets dynamic voltage
regulation requirements. An AC line dropout of any duration does not cause any tripping of
control signals or protection circuits. If the AC dropout lasts longer than the hold-up time, the
power recovers and meets all turn-on requirements. The power supply meets the AC dropout
requirement over rated AC voltages and frequencies. A dropout of the AC line for any duration
does not cause damage to the power supply.
4.1.5.5.1
AC Line 5VSB Holdup
The 5VSB output voltage stays in regulation under its full load (static or dynamic) during an AC
dropout of 70ms min (=5VSB holdup time) whether the power supply is in the ON or OFF state
(PSON asserted or de-asserted).
4.1.5.6
Power Recovery
The power supply recovers automatically after an AC power failure. AC power failure is defined
to be any loss of AC power that exceeds the dropout criteria.
4.1.5.6.1
Voltage Brownout
The power supply complies with the limits defined in EN55024: 1998 using the IEC 61000-411:1995 test standard and performance criteria C defined in Annex B of CISPR 24.
In addition, the power supply meets the following Intel Requirement:
o
4.1.5.6.2
A continuous input voltage below the nominal input range shall not damage the
power supply or cause overstress to any power supply component. The power
supply must be able to return to normal power up state after a brownout condition.
Maximum input current under a continuous brownout shall not blow the fuse. The
power supply should tolerate a 3min ramp from 90VAC voltage to 0VAC after the
components have reached a steady state condition.
Voltage Interruptions
The power supply complies with the limits defined in EN55024: 1998 using the IEC 61000-411:1995 test standard and performance criteria C defined in Annex B of CISPR 24.
4.1.5.7
AC In-rush
AC line in-rush current does not exceed 50A peak, cold start at 20 degrees C, and no
component is damaged at hot start for up to one-quarter of the AC cycle, after which, the input
current is no more than the specified maximum input current listed in Table 19. The peak in-rush
current is less than the ratings of its critical components (including input fuse, bulk rectifiers, and
surge limiting device).
The power supply meets the in-rush requirements for any rated AC voltage during turn on at any
phase of AC voltage or during a single cycle AC dropout condition, as well as upon recovery
after AC dropout of any duration, and over the specified temperature range (Top).
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4.1.5.8
Power Sub-system
AC Line Isolation Requirements
The power supply meets all safety agency requirements for dielectric strength. Transformers’
isolation between primary and secondary windings complies with the 3000Vac (4242Vdc)
dielectric strength criteria. In addition, the insulation system complies with reinforced insulation
per safety standard IEC 950. Separation between the primary and secondary circuits, and
primary to ground circuits, complies with the IEC 950 spacing requirements.
4.1.5.9
AC Line Leakage Current
The maximum leakage current to ground for each power supply is 3.5mA when tested at
240VAC.
4.1.5.10
AC Line Fuse
The power supply has one line fused in the single line fuse on the Line (Hot) wire of the AC
input. The line fusing is acceptable for all safety agency requirements. The input fuse is a slow
blow type. AC in-rush current does not cause the AC line fuse to blow under any conditions. All
protection circuits in the power supply do not cause the AC fuse to blow unless a component in
the power supply has failed. This includes DC output load short conditions.
4.1.5.11
Power Factor Correction
The power supply incorporates a power factor correction circuit.
The power supply is tested as described in EN 61000-3-2: Electromagnetic Compatibility (EMC
Part 3: Limits – Section 2: “Limits for harmonic current emissions,” and meets the harmonic
current emissions limits specified for ITE equipment.
The power supply is tested as described in JEIDA MITI Guideline for Suppression of High
Harmonics in Appliances and General-Use Equipment, and meets the harmonic current
emissions limits specified for ITE equipment.
4.1.5.12
Efficiency
The following table provides the required minimum efficiency level at various loading conditions.
These efficiency levels are provided at three different load levels: 100%, 50% and 20%.
Efficiency is tested over an AC input voltage range of 115VAC to 220VAC.
Table 24. Efficiency
Loading
Recommended Efficiency
100% of Maximum
80%
50% of Maximum
80%
Revision 1.2
Intel order number: E81822-002
20% of Maximum
80%
67
Power Sub-system
4.1.6
Intel® Workstation System SC5650SCWS TPS
DC Output Specification
Table 25. Cable Lengths
Length
(mm)
To Connector
#
Number
of Pins
Description
Power Supply cover exit hole
850
P1
24
Baseboard Power Connector
Power Supply cover exit hole
350
P2
8
Processor 1 Power Connector
From
Power Supply cover exit hole
500
P3
8
Processor 2 Power Connector
Power Supply cover exit hole
350
P4
5
Power PSMI Connector
Power Supply cover exit hole
650
P5
6
PCIE Graphics card Power Connector
Power Supply cover exit hole
650
P6
6
PCIE Graphics card Power Connector
Power Supply cover exit hole
350
P9
4
Peripheral Power Connector
Extension
100
P10
4
Peripheral Power Connector
Power Supply cover exit hole
800
P11
4
Peripheral Power Connector
Extension
75
P12
4
Right-angle SATA Power Connector
Power Supply cover exit hole
800
P13
5
Right Angel SATA Power Connector
Extension
75
P14
5
SATA Power Signal Connector
4.1.7
Power Connectors
4.1.7.1
Baseboard Power Connector (P1)
Connector housing: 24-pin Molex* Mini-Fit Jr. 39-01-2245 or equivalent
Contact: Molex* Mini-Fit, HCS, Female, Crimp 44476 or equivalent
Table 26. P1 Baseboard Power Connector
Pin
Signal
18 AWG Color
Pin
Signal
18 AWG Color
1*
+3.3 VDC
3.3V RS
+3.3 VDC
COM
+5 VDC
5V RS
COM
+5 VDC
COM
PWR OK
5VSB
+12V3
+12V3 RS
+12V3
+3.3 VDC
Orange
Orange (24AWG)
Orange
Black
Red
Red (24AWG)
Black
Red
Black
Gray
Purple
Yellow
Yellow (24AWG)
Yellow
Orange
13
14
15
16
17
18
19
20
21
22
23
24
+3.3 VDC*
-12 VDC
COM
PSON#
COM
COM
COM
Reserved
+5 VDC
+5 VDC
+5 VDC
COM
Orange
Blue
Black
Green
Black
Black
Black
N.C.
Red
Red
Red
Black
2
3*
4*
5
6
7
8
9
10
11
12
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Power Sub-system
Notes:
•
•
5V Remote Sense Double Crimped into pin 4.
3.3V Locate Sense Double Crimped into pin 2.
4.1.7.2
Processor 1 Power Connector (P2)
Connector housing: 8-pin Molex* 39-01-2080 or equivalent
Contact: Molex* 39-00-0059 or equivalent
Table 27. P2 Processor 1 Power Connector
Pin
Signal
18 AWG Color
Pin
Signal
18 AWG Color
1
2
3
4
COM
COM
COM
COM
Black
Black
Black
Black
5
6
7
8
+12V1
+12V1
+12V1
+12V1
White
White
White
White
4.1.7.3
Processor 2 Power Connector (P3)
Connector housing: 8-pin Molex* 39-01-2080 or equivalent
Contact: Molex* 39-00-0059 or equivalent
Revision 1.2
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Power Sub-system
Intel® Workstation System SC5650SCWS TPS
Table 28. P3 Processor 2 Power Connector
Pin
Signal
18 AWG Color
Pin
Signal
18 AWG Color
1
2
3
4
COM
COM
COM
COM
Black
Black
Black
Black
5
6
7
8
+12V2
+12V2
+12V2
+12V2
White
White
White
White
4.1.7.4
Power Signal Connector (P4)
Connector housing: 5-pin Molex* 50-57-9405 or equivalent
Contacts: Molex* 16-02-0087 or equivalent
Table 29. P4 Power Signal Connector
Pin
1
2
3
4
5
4.1.7.5
Signal
I2C Clock
I2C Data
Reserved
COM
3.3RS
24 AWG Color
White
Yellow
N.C.
Black
Orange
PCI Express Connector (P5)
Connector housing: 6-pin Molex* 455590002 or equivalent
Contacts: Molex* Mini-Fit, HCS, Female, Crimp 44476
Table 30. P5 PCI Express Connector
4.1.7.6
PIN
SIGNAL
18 AWG Colors
PIN
SIGNAL
18 AWG Colors
1
+12V4
Green/Yellow strip
4
COM
Black
2
+12V4
Green/Yellow strip
5
COM
Black
3
+12V4
Green/Yellow strip
6
COM
Black
PCI Express Connector (P6)
Connector housing: 6-pin Molex* 455590002 or equivalent
Contacts: Molex* Mini-Fit, HCS, Female, Crimp 44476
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Power Sub-system
Table 31. P6 PCI Express Connector
PIN
SIGNAL
18 AWG Colors
PIN
SIGNAL
18 AWG Colors
1
+12V4
Green/Yellow strip
4
COM
Black
2
+12V4
Green/Yellow strip
5
COM
Black
3
+12V4
Green/Yellow strip
6
COM
Black
1.
4.1.7.7
Peripheral Power Connectors (P9-P12)
Connector housing: Amp* 1-480424-0 or equivalent
Contact: Amp* 61314-1 contact or equivalent
Table 32. P9-P12 Peripheral Power Connectors
Pin
1
2
3
4
4.1.7.8
Signal
+12 V5
COM
COM
+5 VDC
18 AWG Color
Green
Black
Black
Red
Right-Angle SATA Power Connector (P13)
Connector housing: JWT* F6002HS0-5P-18 or equivalent
Table 33. P13 Right-angle SATA Power Connector
Pin
1
2
3
4
5
Signal
+3.3V
COM
+5 VDC
COM
+12V5
18 AWG Color
Orange
Black
Red
Black
Green
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Power Sub-system
4.1.7.9
Intel® Workstation System SC5650SCWS TPS
SATA Power Connector (P14)
Connector housing: JWT* A3811H00-5P or equivalent;
Contact: JWT* A3811TOP-0D or equivalent
Table 34. P14 SATA Power Connector
Pin
Signal
18 AWG Color
1
2
3
4
5
+3.3VDC
COM
+5VDC
COM
+12V5
Orange
Black
Red
Black
Green
4.1.8
DC Output Specifications
4.1.8.1
Output Power / Currents
The following table defines the power and current ratings for the 1000-W power supply. The
combined output power of all outputs does not exceed the rated output power. The power
supply meets both static and dynamic voltage regulation requirements for the minimum loading
conditions.
Table 35. Load Ratings
Voltage
Minimum
Continuous
1.0 A
2.0 A
0.5 A
1.0 A
0.5 A
0.5 A
0.5A
Minimum Continuous
0.1 A
Maximum Continuous
Peak Load
+3.3V
24 A
+5V
30 A
+12V1
24 A
27 A
+12V2
24 A
27 A
+12V3
16 A
318 A
+12V4
16 A
18 A
+12V5
16A
Voltage
Maximum Continuous
Peak Load
+5VSB
5.0 A
6A
Notes:
1. Maximum continuous total DC output power should not exceed 1000 W.
2. Maximum continuous load on the combined 12V output shall not exceed 80 A.
3. Peak load on the combined 12V output shall not exceed 70 A.
4. Peak total DC output power should not exceed 1150 W.
5. Peak power and current loading shall be supported for a minimum of 12 seconds.
6. Combined 3.3V and 5V power shall not exceed 170 W.
4.1.8.2
Pre-set Power-on Requirement
When the power supply turns on, system loading may be very light before it comes out of reset.
Under these conditions, the power supply’s output voltage regulation may be relaxed to +/-10%
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Power Sub-system
on the 3.3V and 5V rails and +10 / -8% on the +12V rails. When the power supply is
subsequently loaded, it must begin to regulate and source current without fault.
Table 36. Pre-set Lighter Load
Voltage
+3.3V
+5V
+12V1
+12V2
+12V3
+12V4
+12V5
-12V
+5VSB
Minimum Continuous
Load
0A
0A
0.0 A
0.0 A
0.1 A
0.0 A
0.1A
0A
0.1 A
Maximum Continuous
Load
9.0 A
7.0 A
8.0 A
8.0 A
8.0 A
8.0 A
8.0A
0.5 A
3.0 A
Peak Load
Table 37. Pre-set Lighter Voltage Regulation Limits
Parameter
+3.3V
+5V
+12V1
+12V2
+12V3
+12V4
+12V5
- 12V
+5VSB
4.1.8.3
Tolerance
- 10% / +10%
- 10% / +10%
- 8% / +10%
- 8% / +10%
- 8% / +10%
- 8% / +10%
- 8% / +10%
- 5% / +9%
- 5% / +5%
MIN
+2.970
+4.500
+11.04
+11.04
+11.04
+11.04
+11.04
- 11.40
+4.75
NOM
+3.30
+5.00
+12.00
+12.00
+12.00
+12.00
+12.00
-12.00
+5.00
MAX
+3.630
+5.500
+13.20
+13.20
+13.20
+13.20
+13.20
-13.08
+5.25
Units
Vrms
Vrms
Vrms
Vrms
Vrms
Vrms
Vrms
Vrms
Vrms
Grounding
The output ground of the pins of the power supply provides the power return path. The output
connector ground pins are connected to safety ground (power supply enclosure). This
grounding is designed to ensure passing the maximum allowed common mode noise levels.
4.1.8.4
Standby Output
The 5VSB output is present when an AC input greater than the power supply turn-on voltage is
applied.
4.1.8.5
Remote Sense
The power supply has remote sense return (ReturnS) to regulate out ground drops for all output
voltages: +3.3V, +5V, +12V1, +12V2, +12V3, +12V4, +12V5, -12V, and 5VSB. The power
supply uses remote sense to regulate out drops in the system for the +3.3V outputs. The +5V,
+12V1, –12V and 5VSB outputs only use remote sense referenced to the ReturnS signal. The
remote sense input impedance to the power supply is greater than 200Ω on 3.3V, 5VS. This is
the value of the resistor connecting the remote sense to the output voltage internal to the power
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Power Sub-system
Intel® Workstation System SC5650SCWS TPS
supply. Remote sense is able to regulate out a minimum of a 200mV drop on the 3.3 output.
The remote sense return (ReturnS) is able to regulate out a minimum of a 200mV drop in the
power ground return. The current in any remote sense line is less than 5mA to prevent voltage
sensing errors. The power supply operates within specification over the full range of voltage
drops from the power supply’s output connector to the remote sense points.
4.1.8.6
Voltage Regulation
The power supply output voltages stay within the following voltage limits when operating at
steady state and dynamic loading conditions. These limits include the peak-peak ripple/noise.
Table 38. Voltage Regulation Limits
Parameter
+ 3.3V
+ 5V
+ 12V1
+ 12V2
+12V3
+12V4
+12V5
- 12V
+ 5VSB
4.1.8.7
Tolerance
- 5% / +5%
- 5% / +5%
- 5% / +5%
- 5% / +5%
- 5% / +5%
- 5% / +5%
- 5% / +5%
- 5% / +9%
- 5% / +5%
MIN
+3.14
+4.75
+11.40
+11.40
+11.40
+11.40
+11.40
-10.80
+4.75
NOM
+3.30
+5.00
+12.00
+12.00
+12.00
+12.00
+12.00
-12.00
+5.00
MAX
+3.46
+5.25
+12.60
+12.60
+12.60
+12.60
+12.60
-13.20
+5.25
Units
Vrms
Vrms
Vrms
Vrms
Vrms
Vrms
Vrms
Vrms
Vrms
Dynamic Loading
The output voltages remain within limits specified for the step loading and capacitive loading, as
shown in the following table. The load transient repetition rate is tested between 50 Hz and 5
kHz at duty cycles ranging from 10%-90%. The load transient repetition rate is only a test
specification. The Δ step load may occur anywhere between the MIN load and MAX load
conditions.
Table 39. Transient Load Requirements
Output
+3.3V
+5V
+12V
+5VSB
4.1.8.8
Δ Step Load Size12
7.0A
7.0A
25A
0.5A
Load Slew Rate
0.25 A/μsec
0.25 A/μsec
0.25 A/μsec
0.25 A/μsec
Test Capacitive Load
4700 μF
1000 μF
4700 μF
20 μF
1.
Step loads on each 12V output may happen simultaneously.
2.
The +12V should be tested with 2200μF evenly split between the four +12V rails.
Capactive Loading
The power supply is stable and meets all requirements with the following capacitive loading
ranges.
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Power Sub-system
Table 40. Capacitive Loading Conditions
4.1.8.9
Output
+3.3V
+5V
+12V(1, 2, 3, 4,5)
MIN
250
400
500 each
MAX
6800
4700
11,000
Units
μF
μF
μF
-12V
+5VSB
1
20
350
350
μF
μF
Closed Loop Stability
The power supply is unconditionally stable under all line / load / transient load conditions,
including capacitive load ranges. A minimum of 45 degrees phase margin and -10dB-gain
margin are required. Closed-loop stability is ensured at the maximum and minimum loads, as
applicable.
4.1.8.10
Common Mode Noise
The common mode noise on any output does not exceed 350mV pk-pk over the frequency band
of 10Hz to 30MHz.
4.1.8.11
Ripple / Noise
The maximum allowed ripple / noise output of the power supply is defined in the following table.
This is measured over a bandwidth of 10Hz to 20MHz at the power supply output connectors. A
10μF tantalum capacitor, in parallel with a 0.1μF ceramic capacitor, is placed at the point of
measurement.
Table 41. Ripple and Noise
+3.3V
50mVp-p
4.1.8.12
+5V
50mVp-p
+12V (1,2,3,4,5)
120mVp-p
-12V
120mVp-p
+5VSB
50mVp-p
Soft Starting
The power supply contains a control circuit that provides monotonic soft start for its outputs
without overstressing the AC line or any power supply components at any specified AC line or
load conditions. There is no requirement for rise time on the 5Vstby but the turn on/off is
monotonic.
4.1.8.13
Timing Requirements
The timing requirements for power supply operation are as follows. The output voltages must
rise from 10% to within regulation limits (Tvout_rise) within 5 to 70 ms, except for 5VSB, which is
allowed to rise from 1.0 to 25 ms. The +3.3V, +5V and +12V output voltages should start to rise
approximately at the same time. All outputs must rise monotonically. Each output voltage shall
reach regulation within 50ms (Tvout_on) of each other during turn on of the power supply. Each
output voltage shall fall out of regulation within 400msec (Tvout_off) of each other during turn off.
Revision 1.2
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Power Sub-system
Intel® Workstation System SC5650SCWS TPS
The following table shows the timing requirements for the power supply being turned on and off
via the AC input, with PSON held low and the PSON signal, with the AC input applied.
Table 42. Output Voltage Timing
Item
Tvout_rise
Tvout_on
Description
Output voltage rise time from each main output.
All main outputs must be within regulation of each
other within this time.
All main outputs must leave regulation within this
time.
T vout_off
MIN
5.01
MAX
701
50
Units
msec
msec
400
msec
1. The 5VSB output voltage rise time shall be from 1.0 ms to 25 ms.
Vout
V1
10%
Vout
V2
V3
V4
Tvout
rise
Tvout_off
Tvout_on
Figure 26. Output Voltage Timing
Table 43. Turn On / Off Timing
Item
Tsb_on_delay
Tac_on_delay
Tvout_holdup
Tpwok_holdup
Tpson_on_dela
y
Tpson_pwok
76
Description
Delay from AC being applied to 5VSB being within regulation.
Delay from AC being applied to all output voltages being
within regulation.
Time all output voltages stay within regulation after loss of
AC.
Delay from loss of AC to de-assertion of PWOK
Delay from PSON# active to output voltages within
regulation limits.
Delay from PSON# deactive to PWOK being de-asserted.
Minimum
Maximum
1500
2500
ms
21
20
5
Units
ms
ms
400
50
ms
ms
ms
Revision 1.2
Intel order number: E81822-002
Intel® Workstation System SC5650SCWS TPS
Item
Tpwok_on
Tpwok_off
Tpwok_low
Tsb_vout
T5VSB_holdup
Power Sub-system
Description
Delay from output voltages within regulation limits to PWOK
asserted at turn on.
Delay from PWOK de-asserted to output voltages (3.3V, 5V,
12V, -12V) dropping out of regulation limits.
Duration of PWOK being in the de-asserted state during an
off / on cycle using AC or the PSON signal.
Delay from 5VSB being in regulation to O/Ps being in
regulation at AC turn on.
Time the 5VSB output voltage stays within regulation after
loss of AC.
Minimum
Maximum
100
500
Units
ms
ms
1
ms
100
50
1000
ms
ms
70
AC Input
Tvout_holdup
Vout
Tpwok_low
TAC_on_delay
Tsb_on_delay
PWOK
5VSB
Tpwok_off
Tpwok_on
Tsb_on_delay
Tpwok_on
Tpwok_off
Tpson_pwok
Tpwok_holdup
T5VSB_holdup
Tsb_vout
Tpson_on_delay
PSON
AC turn on/off cycle
PSON turn on/off cycle
Figure 27. Turn On/Off Timing (Power Supply Signals)
4.1.8.14
Residual Voltage Immunity in Standby mode
The power supply is immune to any residual voltage placed on its outputs (typically a leakage
voltage through the system from standby output) up to 500mV. There is no additional heat
generated or stress of any internal components with this voltage applied to any individual output,
or to all outputs simultaneously. Residual voltage also does not trip the power supply protection
circuits during turn on.
Residual voltage at the power supply outputs for a no-load condition does not exceed 100mV
when AC voltage is applied and the PSON# signal is de-asserted.
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Power Sub-system
4.1.8.15
Intel® Workstation System SC5650SCWS TPS
Protection Circuits
Protection circuits inside the power supply cause only the power supply’s main outputs to shut
down. If the power supply latches off due to a protection circuit tripping, an AC cycle OFF for 15
sec and a PSON# cycle HIGH for 1 sec will reset the power supply.
4.1.8.16
Over-current Protection (OCP)
The power supply has a current limit to prevent the +3.3V, +5V, and +12V outputs from
exceeding the values shown in the following table. If the current limits are exceeded the power
supply will shut down and latch off. The latch will be cleared by toggling the PSON# signal or by
an AC power interruption. The power supply will not be damaged from repeated power cycling
in this condition. -12V and 5VSB are protected under over-current or shorted conditions so that
no damage can occur to the power supply. The 5VSB will auto recover after removing the OCP
limit.
Table 44. Over-current Protection (OCP) 240VA
Voltage
+3.3V
+5V
+12V1
+12V2
+12V3
+12V4
+12V5
-12V
5VSB
4.1.8.17
Over-current Limit
MIN
110% = 26.4A
110% = 33A
18A
18A
18A
18A
18A
0.625A
7.0A
Peak Load
MAX
150% = 36A
150% = 45A
20A
20A
20A
20A
20A
4.0A
Peak Limit
Delay
Over-voltage Protection (OVP)
The power supply over-voltage protection is locally sensed. The power supply will shut down
and latch off after an over voltage condition occurs. This latch can be cleared by toggling the
PSON# signal or by an AC power interruption. The following table contains the over-voltage
limits. The values are measured at the output of the power supply’s pins. The voltage never
exceeds the maximum levels when measured at the power pins of the power supply connector
during any single point of fail. The voltage will not trip any lower than the minimum levels when
measured at the power pins of the power supply connector. Exception: The +5VSB rail will autorecover after an OVP has been cleared.
Table 45. Over-voltage Protection Limits
Output Voltage
+3.3V
+5V
+12V1,2, 3, 4,5
-12V
+5VSB
78
MIN (V)
3.9
5.7
13.3
-13.3
5.7
MAX (V)
4.5
6.5
14.5
-16
6.5
Revision 1.2
Intel order number: E81822-002
Intel® Workstation System SC5650SCWS TPS
4.1.8.18
Power Sub-system
Over-temperature Protection (OTP)
The power supply is protected against over-temperature conditions caused by loss of fan
cooling or excessive ambient temperature. In an OTP condition the power supply will shut down.
When the power supply temperature drops to within specified limits, the power supply will
restore power automatically; the 5VSB always remains on. The OTP circuit has a built-in
hysteresis such that the power supply will not oscillate on and off due to a temperature
recovering condition. The OTP trip level has a minimum of 4 degrees C of ambient temperature
hysteresis.
4.1.9
Control and Indicator Functions
The following sections define the input and output signals from the power supply.
Signals that can be defined as low true use the following convention:
Signal# = low true
4.1.9.1
PSON# Input Signal
The PSON# signal is required to remotely turn on/off the power supply. PSON# is an active low
signal that turns on the +3.3V, +5V, +12V, and -12V power rails. When this signal is not pulled
low by the system, or left open, the outputs (except the +5VSB) turn off. This signal is pulled to
a standby voltage by a pull-up resistor internal to the power supply.
Table 46. PSON# Signal Characteristic
Signal Type
Accepts an open collector/drain input from the system.
Pull-up to VSB located in power supply.
PSON# = Low
PSON# = High or Open
ON
OFF
Logic level low (power supply ON)
Logic level high (power supply OFF)
Source current, Vpson = low
Power up delay: Tpson_on_delay
PWOK delay:
T pson_pwok
4.1.9.2
MIN
0V
2.1V
5msec
MAX
1.0V
5.25V
4mA
400msec
50msec
PWOK (Power OK) Output Signal
PWOK is a power OK signal and is pulled HIGH by the power supply to indicate that all the
outputs are within the regulation limits of the power supply. When any output voltage falls below
regulation limits or when AC power has been removed for a time sufficiently long so that power
supply operation is no longer guaranteed, PWOK will de-assert to a LOW state. The start of the
PWOK delay time is inhibited as long as any power supply output is in current limit.
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Power Sub-system
Intel® Workstation System SC5650SCWS TPS
Table 47. PWOK Signal Characteristics
Signal Type
Open collector/drain output from power supply. Pull-up to
VSB located in system.
PWOK = High
PWOK = Low
Power OK
Power Not OK
MIN
0V
2.4V
Logic level low voltage, Isink=4mA
Logic level high voltage, Isource=200μA
Sink current, PWOK = low
Source current, PWOK = high
PWOK delay: Tpwok_on
PWOK rise and fall time
Power down delay: T pwok_off
4.1.9.3
MAX
0.4V
5.25V
4mA
2mA
1000ms
100μsec
200msec
100ms
1ms
LED
There is a single bi-color LED to indicate power supply status. LED operation is defined in the
following table.
Table 48. LED Indicators
Power Supply Condition
LED
No AC power to all power supplies
Power supply critical event causing a shutdown: failure, OCP,
OVP, fan fail
AC present / Only 5VSB on (power supply off)
Output ON and OK
Off
Amber
1-Hz blink Green
Green
The LED is visible on the power supply’s exterior face. The LED’s location meets ESD
requirements. The LED is securely mounted in such a way that incidental pressure on the LED
will not cause it to be displaced.
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Intel® Workstation System SC5650SCWS TPS
5.
Platform Management
Platform Management
The platform management subsystem is based on the Integrated BMC features of the
ServerEngines* Pilot II. The onboard platform management subsystem consists of
communication buses, sensors, and the system BIOS, and server management firmware.
SMBUS Block Diagram provides an illustration of the Server Management Bus (SMBUS)
architecture as used on these server boards.
5.1
Feature Support
5.1.1
IPMI 2.0 Features
ƒ
Baseboard management controller (BMC).
ƒ
IPMI Watchdog timer.
ƒ
Messaging support, including command bridging and user/session support.
ƒ
Chassis device functionality, including power/reset control and BIOS boot flags support.
ƒ
Event receiver device: The BMC receives and processes events from other platform
subsystems.
ƒ
Field replaceable unit (FRU) inventory device functionality: The BMC supports access to
system FRU devices using IPMI FRU commands.
ƒ
System event log (SEL) device functionality: The BMC supports and provides access to
a SEL.
ƒ
Sensor data record (SDR) repository device functionality: The BMC supports storage
and access of system SDRs.
ƒ
Sensor device and sensor scanning/monitoring: The BMC provides IPMI management of
sensors. It polls sensors to monitor and report system health.
ƒ
IPMI interfaces:
ƒ
Host interfaces include system management software (SMS) with receive message
queue support and server management mode (SMM).
- IPMB interface.
- LAN interface that supports the IPMI-over-LAN protocol (RMCP, RMCP+).
Serial-over-LAN (SOL)
ƒ
ACPI state synchronization: The BMC tracks ACPI state changes provided by the BIOS.
ƒ
BMC Self-test: The BMC performs initialization and run-time self-tests, and makes
results available to external entities.
-
Refer to the Intelligent Platform Management Interface Specification Second Generation v2.0.
5.1.2
Non-IPMI Features
The BMC supports the following non-IPMI features. This list does not preclude support for future
enhancements or additions.
ƒ
In-circuit BMC firmware update
ƒ
Fault resilient booting (FRB): FRB2 is supported by the watchdog timer functionality.
Revision 1.2
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82
Intel® Workstation System SC5650SCWS TPS
ƒ
Chassis intrusion detection (dependant on platform support)
ƒ
Basic fan control using TControl version 2 SDRs
ƒ
Fan redundancy monitoring and support
ƒ
Power supply redundancy monitoring and support
ƒ
Hot swap fan support
ƒ
Acoustic management: Supports multiple fan profiles
ƒ
Signal testing support: The BMC provides test commands for setting and getting
platform signal states.
ƒ
The BMC generates diagnostic beep codes for fault conditions.
ƒ
System GUID storage and retrieval
ƒ
Front panel management: The BMC controls the system status LED and chassis ID LED.
It supports secure lockout of certain front panel functionality and monitors button
presses. The chassis ID LED is turned on using a front panel button or a command.
ƒ
Power state retention
ƒ
Power fault analysis
ƒ
Intel® Light-Guided Diagnostics
ƒ
Power unit management: Support for power unit sensor. The BMC handles power-good
dropout conditions.
ƒ
DIMM temperature monitoring: New sensors and improved acoustic management using
closed-loop fan control algorithm taking into account DIMM temperature readings.
ƒ
Address Resolution Protocol (ARP): The BMC sends and responds to ARPs (supported
on embedded NICs)
ƒ
Dynamic Host Configuration Protocol (DHCP): The BMC performs DHCP (supported on
embedded NICs)
ƒ
Platform environment control interface (PECI) thermal management support
ƒ
E-mail alerting
ƒ
Embedded web server
ƒ
Integrated KVM
ƒ
Integrated Remote Media Redirection
ƒ
Local Directory Access Protocol (LDAP) support
ƒ
Intel® Intelligent Power Node Manger support
Revision 1.2
Intel order number: E81822-002
Intel® Workstation System SC5650SCWS TPS
5.2
Platform Management
Optional Advanced Management Feature Support
This section explains the advanced management features supported by the BMC firmware.
Below Table lists basic and advanced feature support. Individual features may vary by platform.
For more information, refer to Appendix C.
Table 49. Basic and Advanced Management Features
Feature
IPMI 2.0 Feature Support
Basic*
X
Advanced**
X
In-circuit BMC Firmware Update
X
X
FRB 2
X
X
Chassis Intrusion Detection
X
X
Fan Redundancy Monitoring
X
X
Hot-Swap Fan Support
X
X
Acoustic Management
X
X
Diagnostic Beep Code Support
X
X
Power State Retention
X
X
ARP/DHCP Support
X
X
PECI Thermal Management Support
X
X
E-mail Alerting
X
Embedded Web Server
X
X
SSH Support
X
X
Integrated KVM
X
Integrated Remote Media Redirection
X
Local Directory Access Protocol (LDAP) for Linux
X
Intel® Intelligent Power Node Manager Support***
X
X
SMASH CLP
X
X
WS-Management
X
* Basic management features provided by integrated BMC
**Advanced management features available with optional Intel® Remote Management Module 3
***Intel® Intelligent Power Node Manager Support requires PMBus-compliant power supply
5.2.1
Enabling Advanced Management Features
BMC will enable advanced management features only when it detects the presence of the Intel®
Remote Management Module 3 (Intel® RMM3) card. Without the Intel® RMM3, the advanced
features are dormant.
5.2.1.1
Intel® Remote Management Module 3 (Intel® RMM3)
The Intel® RMM3 provides the BMC with an additional dedicated network interface. The
dedicated interface consumes its own LAN channel. Additionally, the Intel® RMM3 provides
additional flash storage for advanced features such as WS-MAN.
Revision 1.2
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Platform Management
5.2.2
Intel® Workstation System SC5650SCWS TPS
Keyboard, Video, and Mouse (KVM) Redirection
The advanced management features include support for keyboard, video, and mouse
redirection (KVM) over LAN. This feature is available remotely from the embedded web server
as a Java* applet. The client system must have a Java Runtime Environment (JRE) Version 1.6
(JRE6) or later to run the KVM or media redirection applets. You can download the latest Java
Runtime Environment (JRE) update: http://java.com/en/download/index.jsp
This feature is only enabled when the Intel® RMM3 is present.
Note: KVM Redirection is only available with onboard video controller, and the onboard video
controller must be enabled and used as the primary video output
The BIOS will detect one set of USB keyboard and mouse for the KVM redirection function of
Intel® RMM3, even if no presence of RMM3 is detected. Users will see one set of USB
keyboard and mouse in addition to the local USB connection on the BIOS Setup USB screen
with or without RMM3 installed.
5.2.2.1
Keyboard and Mouse
The keyboard and mouse are emulated by the BMC as USB human interface devices.
5.2.2.2
Video
Video output from the KVM subsystem is equivalent to video output on the local console via
onboard video controller. Video redirection is available once video is initialized by the system
BIOS. The KVM video resolutions and refresh rates will always match the values set in the
operating system.
5.2.2.3
Availability
Up to two remote KVM sessions are supported. An error displays on the web browser
attempting to launch more than two KVM sessions.
The default inactivity timeout is 30 minutes, but you may change the default through the
embedded web server. Remote KVM activation does not disable the local system keyboard,
video, or mouse. Unless the feature is disabled locally, remote KVM is not deactivated by local
system input.
KVM sessions will persist across system reset but not across an AC power loss.
5.2.3
Media Redirection
The embedded web server provides a Java* applet to enable remote media redirection. You
may use this in conjunction with the remote KVM feature or as a standalone applet.
The media redirection feature is intended to allow system administrators or users to mount a
remote IDE or USB CD-ROM, floppy drive, or a USB flash disk as a remote device to the server.
Once mounted, the remote device appears as a local device to the server, allowing system
administrators or users to boot the server or install software (including operating systems), copy
files, update the BIOS, and so forth, or boot the server from this device.
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The following capabilities are supported:
ƒ
The operation of remotely mounted devices is independent of the local devices on the
server. Both remote and local devices are usable in parallel.
ƒ
You can mount either IDE (CD-ROM, floppy) or USB devices as a remote device to the
server.
ƒ
It is possible to boot all supported operating systems from the remotely mounted device
and to boot from disk IMAGE (*.IMG) and CD-ROM or DVD-ROM ISO files. For more
information, refer to the Tested/supported Operating System List.
ƒ
It is possible to mount at least two devices concurrently.
ƒ
The mounted device is visible to (and usable by) the managed system’s operating
system and BIOS in both the pre- and post-boot states.
ƒ
The mounted device shows up in the BIOS boot order and it is possible to change the
BIOS boot order to boot from this remote device.
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It is possible to install an operating system on a bare metal server (no operating system
present) using the remotely mounted device. This may also require the use of KVM-r to
configure the operating system during install.
If either a virtual IDE or virtual floppy device is remotely attached during system boot, both
virtual IDE and virtual floppy are presented as bootable devices. It is not possible to present
only a single mounted device type to the system BIOS.
5.2.3.1
Availability
The default inactivity timeout is 30 minutes and is not user-configurable.
Media redirection sessions persist across system reset but not across an AC power loss.
5.2.4
Web Services for Management (WS-MAN)
The BMC firmware supports the Web Services for Management (WS-MAN) specification,
version 1.0.
5.2.4.1
Profiles
The BMC supports the following DMTF profiles for WS-MAN:
ƒ
Base Server Profile
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Fan Profile
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Physical Asset Profile
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Power State Management Profile
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Profile Registration Profile
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Record Log Profile
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Sensor Profile
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Software Inventory Profile (FW Version)
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Note: WS-MAN features will be made available after production launch.
5.2.5
Embedded Web server
The BMC provides an embedded web server for out-of-band management. User authentication
is handled by IPMI user names and passwords. Base functionality for the embedded web server
includes:
ƒ
Power Control
ƒ
Sensor Reading
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SEL Reading
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KVM/Media Redirection: Only available when the Intel® RMM3 is present.
ƒ
IPMI User Management
The web server is available on all enabled LAN channels. If a LAN channel is enabled, properly
configured, and accessible, the web server is available.
The web server may be contacted via HTTP or HTTPS. A user can modify the SSL certificates
using the web server. You cannot change the web server’s port (80/81).
For security reasons, you cannot use the null user (user 1) to access the web server. The
session inactivity timeout for the embedded web server is 30 minutes. This is not userconfigurable.
5.2.6
Local Directory Authentication Protocol (LDAP)
The BMC firmware supports the Linux Local Directory Authentication Protocol (LDAP) protocol
for user authentication. IPMI users/passwords and sessions are not supported over LDAP.
A user can configure LDAP usage through the embedded web server for authentication of future
embedded web sessions.
Note: Supports LDAP for Linux only.
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Platform Management
Platform Control
This server platform has embedded platform control which is capable of automatically adjusting
system performance and acoustic levels.
Performance
Throttling
Performance
Management
Integrated
Control
Acoustic
Management
Thermal
Monitoring
Fan Speed
Co n t r o l
Figure 28: Server Platform with Embedded Platform Control
Platform control optimizes system performance and acoustics levels through:
ƒ
Performance management
ƒ
Performance throttling
ƒ
Thermal monitoring
ƒ
Fan speed control
ƒ
Acoustics management
The platform components used to implement platform control include:
ƒ
Integrated baseboard management controller
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Platform sensors
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Variable speed system fans
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System BIOS
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BMC firmware
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Sensor data records as loaded by the FRUSDR Utility
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Memory type
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Memory Open and Closed Loop Thermal Throttling
Open-Loop Thermal Throttling (OLTT)
Throttling is a solution to cool the DIMMs by reducing memory traffic allowed on the memory
bus, which reduces power consumption and thermal output. With OLTT, the system throttles in
response to memory bandwidth demands instead of actual memory temperature. Since there is
no direct temperature feedback from the DDR3 DIMMs, the throttling behavior is preset rather
than conservatively based on the worst cooling conditions (for example, high inlet temperature
and low fan speeds). Additionally, the fans that provide cooling to the memory region are also
set to conservative settings (for example, higher minimal fan speed). OLTT produces a slightly
louder system than CLTT because minimal fan speeds must be set high enough to support any
DDR3 DIMMs in the worst memory cooling conditions.
Closed-Loop Thermal Throttling (CLTT)
CLTT works by throttling the DDR3 DIMMs response directly to memory temperature via
thermal sensors integrated on the Serial Presence Detect (SPD) of the DDR3 DIMMs. This is
the preferred throttling method because this approach lowers limitations on both memory power
and thermal threshold, therefore minimizing throttling impact on memory performance. This
reduces the utilization of high fan speeds because CLTT does not have to accommodate for the
worst memory cooling conditions; with a higher thermal threshold, CLTT enables memory
performance to achieve optimal levels.
5.3.2
Fan Speed Control
BIOS and BMC software work cooperatively to implement system thermal management support.
During normal system operation, the BMC will retrieve information from the BIOS and monitor
several platform thermal sensors to determine the required fan speeds.
In order to provide the proper fan speed control for a given system configuration, the BMC must
have the appropriate platform data programmed. Platform configuration data is programmed
using the FRUSDR utility during the system integration process and by System BIOS during run
time.
5.3.2.1
System Configuration Using the FRUSDR Utility
The Field Replaceable Unit and Sensor Data Record Update Utility (FRUSDR utility) is a
program used to write platform-specific configuration data to NVRAM on the server board. It
allows the user to select which supported chassis (Intel or Non-Intel) and platform chassis
configuration is used. Based on the input provided, the FRUSDR writes sensor data specific to
the configuration to NVRAM for the BMC controller to read each time the system is powered on.
5.3.2.2
Fan Speed Control from BMC and BIOS Inputs
Using the data programmed to NVRAM by the FRUSDR utility, the BMC is configured to monitor
and control the appropriate platform sensors and system fans each time the system is powered
on. After power-on, the BMC uses additional data provided to it by the System BIOS to
determine how to control the system fans.
The BIOS provides data to the BMC telling it which fan profile the platform is set up for:
Acoustics Mode or Performance Mode. The BIOS uses the parameters retrieved from the
thermal sensor data records (SDR), fan profile setting from BIOS Setup, and altitude setting
from the BIOS Setup to configure the system for memory throttling and fan speed control. If the
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BIOS fails to get the Thermal SDRs, then it uses the Memory Reference Code (MRC) default
settings for the memory throttling settings.
The <F2> BIOS Setup Utility provides options to set the fan profile or operating mode the
platform will operate under. Each operating mode has a predefined profile for which specific
platform targets are configured, which in turn determines how the system fans operate to meet
those targets. Platform profile targets are determined by which type of platform is selected when
running the FRUSDR utility and by the BIOS settings configured using the <F2> BIOS Setup.
5.3.2.2.1
Fan Domains
System fan speeds are controlled through pulse width modulation (PWM) signals, which are
driven separately for each domain by integrated PWM hardware. Fan speed is changed by
adjusting the duty-cycle, which is the percentage of time the signal is driven high in each pulse.
Refer to Appendix D for system specific fan domains.
Table 50. SC5650SCWS Fan Domain Table
5.3.2.3
Fan Domain
Fan Domain 0
Onboard Fan Header
CPU 1 Fan, CPU 2 Fan
Fan Domain 1
System Fan 5
Fan Domain 2
System Fan 1, System Fan 2
Fan Domain 3
System Fan 3, System Fan 4
Configuring the Fan Profile Using the BIOS Setup Utility
The BIOS uses options set in the <F2> BIOS Setup Utility to determine what fan profile the
system should operate under. These options include “THROTTLING MODE”, “ALTITUDE”, and
“SET FAN PROFILE”. Refer to “Section 5.3.2.2.7 System Acoustic and Performance
Configuration” for details of the BIOS options.
The “ALTITUDE” option is used to determine appropriate memory performance settings based
on the different cooling capability at different altitudes. At high altitude, memory performance
must be reduced to compensate for thinner air. Be advised, selecting an Altitude option to a
setting that does not meet the operating altitude of the server may limit the system fans’ ability
to provide adequate cooling to the memory. If the air flow is not sufficient to meet the needs of
the server even after throttling has occurred, the system may shut down due to excessive
platform thermals.
By default, the Altitude option is set to 301 m – 900 m which is believed to cover the majority of
the operating altitudes for these server platforms.
You can set the “SET FAN PROFILE” option to either the Performance mode (Default) or
Acoustics mode. Refer to the following sections for details describing the differences between
each mode. Changing the fan profile to Acoustics mode may affect system performance. The
“SET FAN PROFILE” BIOS option is hidden when CLTT is selected as the THROTTLING
MODE option.
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Performance Mode (Default)
With the platform running in Performance mode (Default), several platform control algorithm
variables are set to enhance the platform’s capability of operating at maximum performance
targets for the given system. In doing so, the platform is programmed with higher fan speeds at
lower ambient temperatures. This results in a louder acoustic level than is targeted for the given
platform, but the increased airflow of this operating mode greatly reduces both possible memory
throttling from occurring and dynamic fan speed changes based on processor utilization.
5.3.2.3.2
Acoustics Mode
With the platform running in Acoustics mode, several platform control algorithm variables are set
to ensure acoustic targets are not exceeded for specified Intel platforms. In this mode, the
platform is programmed to set the fans at lower speeds when the processor does not require
additional cooling due to high utilization / power consumption. Memory throttling is used to
ensure memory thermal limits are not exceeded.
Note: Fan speed control for a non-Intel chassis, as configured after running the FRUSDR utility
and selecting the Non-Intel Chassis option, is limited to only the CPU fans. The BMC only
requires the processor thermal sensor data to determine how fast to operate these fans. The
remaining system fans will operate at 100% operating limits due to unknown variables
associated with the given chassis and its fans. Therefore, regardless of whether the system is
configured for Performance Mode or Acoustics Mode, the system fans will always run at 100%
operating levels providing for maximum airflow. In this scenario, the Performance and Acoustic
mode settings only affect the allowable performance of the memory (higher BW for the
Performance mode).
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5.4
Platform Management
Intel® Intelligent Power Node Manager
Intel® Intelligent Power Node Manager is a platform (system)-level solution that provides the
system with a method of monitoring power consumption and thermal output, and adjusting
system variables to control those factors.
The BMC supports Intel® Intelligent Power Node Manager specification version 1.5. Additionally,
the platform must have an Intel® Intelligent Power Node Manager capable Manageability Engine
(ME) firmware installed.
The BMC firmware implements power-management features based on the Power Management
Bus (PMBus) 1.1 Specification.
Note: Intelligent Power Node Manager is only available on platforms that support PMBuscompliant power supplies.
5.4.1
Manageability Engine (ME)
5.4.2
Manageability Engine (ME)
An embedded ARC controller is within the IOH providing the Intel® Server Platform Services
(SPS). The controller is also commonly referred to as the Manageability Engine (ME).
ƒ
The functionality provided by the SPS firmware is different from Intel® Active
Management Technology (Intel® AMT) provided by the ME on client platforms.
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Figure 29. SMBUS Block Diagram
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6.
BIOS Setup Utility
6.1
Logo / Diagnostic Screen
BIOS Setup Utility
The Logo / Diagnostic Screen displays in one of two forms:
ƒ
ƒ
If Quiet Boot is enabled in the BIOS setup, a logo splash screen displays. By default,
Quiet Boot is enabled in the BIOS setup. If the logo displays during POST, press <Esc>
to hide the logo and display the diagnostic screen.
If a logo is not present in the flash ROM or if Quiet Boot is disabled in the system
configuration, the summary and diagnostic screens display.
The diagnostic screen displays the following information:
ƒ
BIOS ID
ƒ
Platform name
ƒ
Total memory detected (Total size of all installed DDR3 DIMMs)
ƒ
Processor information (Intel-branded string, speed, and number of physical processors
identified)
ƒ
Keyboards detected (if plugged in)
ƒ
Mouse devices detected (if plugged in)
6.2
BIOS Boot Popup Menu
The BIOS Boot Specification (BBS) provides for a Boot Popup Menu invoked by pressing the
<F6> key during POST. The BBS popup menu displays all available boot devices. The list order
in the popup menu is not the same as the boot order in the BIOS setup; it simply lists all the
bootable devices from which the system can be booted.
When a User Password or Administrator Password is active in Setup, the password is to access
the Boot Popup Menu.
6.3
BIOS Setup Utility
The BIOS Setup utility is a text-based utility that allows the user to configure the system and
view current settings and environment information for the platform devices. The Setup utility
controls the platform's built-in devices, boot manager, and error manager.
The BIOS Setup interface consists of a number of pages or screens. Each page contains
information or links to other pages. The advanced tab in Setup displays a list of general
categories as links. These links lead to pages containing a specific category’s configuration.
The following sections describe the look and behavior for platform setup.
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Operation
The BIOS Setup has the following features:
ƒ
Localization - The BIOS Setup uses the Unicode standard and is capable of displaying
setup forms in all languages currently included in the Unicode standard. The Intel®
workstation BIOS is only available in English.
ƒ
Console Redirection - The BIOS Setup is functional via console redirection over various
terminal emulation standards. This may limit some functionality for compatibility (for
example, color usage or some keys or key sequences or support of pointing devices).
6.3.1.1
Setup Page Layout
The setup page layout is sectioned into functional areas. Each occupies a specific area of the
screen and has dedicated functionality. The following table lists and describes each functional
area.
Table 51. BIOS Setup Page Layout
Functional Area
Title Bar
Description
The title bar is located at the top of the screen and displays the title of the form (page)
the user is currently viewing. It may also display navigational information.
Setup Item List
The Setup Item List is a set of controllable and informational items. Each item in the list
occupies the left column of the screen.
A Setup Item may also open a new window with more options for that functionality on
the board.
Item Specific Help Area
The Item Specific Help area is located on the right side of the screen and contains help
text for the highlighted Setup Item. Help information may include the meaning and
usage of the item, allowable values, effects of the options, and so forth.
Keyboard Command Bar
The Keyboard Command Bar is located at the bottom right of the screen and
continuously displays help for keyboard special keys and navigation keys.
6.3.1.2
Entering BIOS Setup
To enter the BIOS Setup, press the F2 function key during boot time when the OEM or Intel logo
displays. The following message displays on the diagnostics screen and under the Quiet Boot
logo screen:
Press <F2> to enter setup
When the Setup is entered, the Main screen displays. However, serious errors cause the
system to display the Error Manager screen instead of the Main screen.
6.3.1.3
Keyboard Commands
The bottom right portion of the Setup screen provides a list of commands used to navigate
through the Setup utility. These commands display at all times.
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Each Setup menu page contains a number of features. Each feature is associated with a value
field except those used for informative purposes. Each value field contains configurable
parameters. Depending on the security option selected and (in effect) by the password, a menu
feature’s value may or may not change. If a value cannot be changed, its field is made
inaccessible and appears grayed out.
Table 52. BIOS Setup: Keyboard Command Bar
Key
<Enter>
Option
Execute Command
Description
The <Enter> key is used to activate sub-menus when the selected feature is a submenu, or to display a pick list if a selected option has a value field, or to select a subfield for multi-valued features like time and date. If a pick list is displayed, the <Enter>
key selects the currently highlighted item, undoes the pick list, and returns the focus
to the parent menu.
<Esc>
Exit
The <Esc> key provides a mechanism for backing out of any field. When the <Esc> key
is pressed while editing any field or selecting features of a menu, the parent menu is
re-entered.
When the <Esc> key is pressed in any sub-menu, the parent menu is re-entered. When
the <Esc> key is pressed in any major menu, the exit confirmation window is displayed
and the user is asked whether changes can be discarded. If “No” is selected and the
<Enter> key is pressed, or if the <Esc> key is pressed, the user is returned to where
they were before <Esc> was pressed, without affecting any existing settings. If “Yes”
is selected and the <Enter> key is pressed, the setup is exited and the BIOS returns to
the main System Options Menu screen.
↑
Select Item
The up arrow is used to select the previous value in a pick list, or the previous option
in a menu item's option list. The selected item must then be activated by pressing the
<Enter> key.
↓
Select Item
The down arrow is used to select the next value in a menu item’s option list, or a value
field’s pick list. The selected item must then be activated by pressing the <Enter> key.
↔
Select Menu
The left and right arrow keys are used to move between the major menu pages. The
keys have no affect if a sub-menu or pick list is displayed.
<Tab>
Select Field
The <Tab> key is used to move between fields. For example, <Tab> can be used to
move from hours to minutes in the time item in the main menu.
-
Change Value
The minus key on the keypad is used to change the value of the current item to the
previous value. This key scrolls through the values in the associated pick list without
displaying the full list.
+
Change Value
The plus key on the keypad is used to change the value of the current menu item to
the next value. This key scrolls through the values in the associated pick list without
displaying the full list. On 106-key Japanese keyboards, the plus key has a different
scan code than the plus key on the other keyboards, but will have the same effect.
<F9>
Setup Defaults
Pressing <F9> causes the following to display:
Load Optimized Defaults?
Yes
No
If “Yes” is highlighted and <Enter> is pressed, all Setup fields are set to their default
values. If “No” is highlighted and <Enter> is pressed, or if the <Esc> key is pressed, the
user is returned to where they were before <F9> was pressed without affecting any
existing field values.
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Key
<F10>
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Option
Save and Exit
Description
Pressing <F10> causes the following message to display:
Save configuration and reset?
Yes
No
If “Yes” is highlighted and <Enter> is pressed, all changes are saved and the Setup is
exited. If “No” is highlighted and <Enter> is pressed, or the <Esc> key is pressed, the
user is returned to where they were before <F10> was pressed without affecting any
existing values.
6.3.1.4
Menu Selection Bar
The Menu Selection Bar is located at the top of the BIOS Setup Utility screen. It displays the
major menu selections available to the user. By using the left and right arrow keys, the user can
select the menus listed here. Some menus are hidden and become available by scrolling off the
left or right of the current selections.
6.3.2
Server Platform Setup Utility Screens
The following sections describe the screens available for the configuration of a server platform.
In these sections, tables are used to describe the contents of each screen. These tables follow
the following guidelines:
96
ƒ
The Setup Item, Options, and Help Text columns in the tables document the text and
values that also display on the BIOS Setup screens.
ƒ
In the Options column, the default values are displayed in bold. The BIOS Setup screen
does not display these values in bold. The bold text in this document serves as a
reference point.
ƒ
The Comments column provides additional information where it may be helpful. This
information does not display on the BIOS Setup screens.
ƒ
Information enclosed in angular brackets (< >) in the screen shots identifies text that can
vary, depending on the option(s) installed. For example <Current Date> is replaced by
the actual current date.
ƒ
Information enclosed in square brackets ([ ]) in the tables identifies areas where the user
needs to type in text instead of selecting from a provided option.
ƒ
Whenever information is changed (except Date and Time), the systems requires a save
and reboot to take place. Pressing <ESC> discards the changes and boots the system
according to the boot order set from the last boot.
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6.3.2.1
BIOS Setup Utility
Main Screen
Unless an error occurred, the Main screen is the first screen displayed when the BIOS Setup is
entered. If an error occurred, the Error Manager screen displays instead.
Main
Advanced
Security
Server Management
Boot Options
Boot Manager
Logged in as <Administrator or User>
<Platform Identification String>
Platform ID
System BIOS
Version
S5500.86B.xx.yy.zzzz
Build Date
<MM/DD/YYYY>
Memory
Total Memory
<How much memory is installed>
Quiet Boot
Enabled/Disabled
POST Error Pause
Enabled/Disabled
System Date
<Current Date>
System Time
<Current Time>
Figure 30. Setup Utility — Main Screen Display
Table 53. Setup Utility — Main Screen Fields
Setup Item
Logged in as
Options
Help Text
Platform ID
Comments
Information only. Displays password
level that setup is running in:
Administrator or User. With no
passwords set, Administrator is the
default mode.
Information only. Displays the
Platform ID.
System BIOS
Version
Information only. Displays the
current BIOS version.
xx = major version
yy = minor version
zzzz = build number
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Setup Item
Build Date
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Options
Help Text
Comments
Information only. Displays the
current BIOS build date.
Memory
Size
Quiet Boot
Information only. Displays the total
physical memory installed in the
system in MB or GB. The term
physical memory indicates the total
memory discovered in the form of
installed DDR3 DIMMs.
Enabled
Disabled
POST Error Pause
Enabled
Disabled
[Enabled] – Display the logo screen
during POST.
[Disabled] – Display the diagnostic
screen during POST.
[Enabled] – Go to the Error Manager
for critical POST errors.
[Disabled] – Attempt to boot and do
not go to the Error Manager for
critical POST errors.
System Date
[Day of week
MM/DD/YYYY]
If enabled, the POST Error Pause
option takes the system to the error
manager to review the errors when
major errors occur. This setting does
not affect minor and fatal error
displays.
System Date has configurable fields
for Month, Day, and Year.
Use [Enter] or [Tab] key to select the
next field.
Use [+] or [-] key to modify the
selected field.
System Time
[HH:MM:SS]
System Time has configurable fields
for Hours, Minutes, and Seconds.
Hours are in 24-hour format.
Use [Enter] or [Tab] key to select the
next field.
Use [+] or [-] key to modify the
selected field.
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6.3.2.2
BIOS Setup Utility
Advanced Screen
The Advanced screen provides an access point to configure several options. On this screen, the
user selects the option they want to configure. Configurations are performed on the selected
screen and not directly on the Advanced screen.
To access this screen from the Main screen, press the right arrow until the Advanced screen is
selected.
Main
Advanced
Security
Server Management
Boot Options
Boot Manager
► Processor Configuration
► Memory Configuration
► Mass Storage Controller Configuration
► Serial Port Configuration
► USB Configuration
► PCI Configuration
► System Acoustic and Performance Configuration
Figure 31. Setup Utility — Advanced Screen Display
Table 54. Setup Utility — Advanced Screen Display Fields
Setup Item
Processor Configuration
Help Text
View/Configure processor information and settings.
Memory Configuration
View/Configure memory information and settings.
Mass Storage Controller Configuration
Serial Port Configuration
View/Configure serial port information and settings.
USB Configuration
View/Configure USB information and settings.
PCI Configuration
View/Configure PCI information and settings.
System
Acoustic
Configuration
and
Performance View/Configure system acoustic and performance
information and settings.
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Processor Screen
The Processor screen allows the user to view the processor core frequency, system bus
frequency, and to enable or disable several processor options. This screen also allows the user
to view information about a specific processor. To access this screen from the Main screen,
select Advanced > Processor.
Advanced
Processor Configuration
Processor Socket
CPU 1
CPU 2
Processor ID
<CPUID>
<CPUID>
Processor Frequency
<Proc Freq>
<Proc Freq>
Microcode Revision
<Rev data>
L1 Cache RAM
L2 Cache RAM
Size of Cache
Size of Cache
<Rev data>
Size of Cache
L3 Cache RAM
Size of Cache
Size of Cache
Size of Cache
Processor 1 Version
<ID string from Processor 1>
Processor 2 Version
<ID string from Processor 2> or Not Present
®
Current Intel QPI Link Speed
®
<Slow / Fast >
<Unknown GT/s / 4.8 GT/s / 5.866 GT/s / 6.4 GT/s>
Intel QPI Link Frequency
®
Intel Turbo Boost Technology
®
Enhanced Intel SpeedStep Tech
®
Enabled / Disabled
Enabled / Disabled
Intel Hyper-Threading Tech
Enabled / Disabled
Core Multi-Processing
All / 1 / 2
Execute Disable Bit
Enabled / Disabled
Intel® Virtualization
Tech
Enabled/ Disabled
Intel® VT for Directed I/O
Enabled/ Disabled
Interrupt Remapping
Enabled / Disabled
Coherency Support
Enabled/ Disabled
ATS Support
Enabled / Disabled
Pass-through DMA Support
Enabled / Disabled
Hardware Prefetcher
Enabled / Disabled
Adjacent Cache Line Prefetch
Direct Cache Access (DCA)
Enabled / Disabled
Enabled / Disabled
Figure 32. Setup Utility — Processor Configuration Screen Display
100
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Intel® Workstation System SC5650SCWS TPS
BIOS Setup Utility
Table 55. Setup Utility — Processor Configuration Screen Fields
Setup Item
Processor ID
Options
Help Text
Comments
Information only. Processor
CPUID.
Processor Frequency
Information only. Current
frequency of the processor.
Microcode Revision
Information only. Revision of
the loaded microcode.
L1 Cache RAM
Information only. Size of the
Processor L1 Cache.
L2 Cache RAM
Information only. Size of the
Processor L2 Cache.
L3 Cache RAM
Information only. Size of the
Processor L3 Cache.
Processor 1 Version
Information only. ID string
from the Processor.
Processor 2 Version
Information only. ID string
from the Processor.
Current Intel® QPI Link
Speed
Information only. Current
speed the QPI Link is using.
Intel® QPI Link Frequency
Information only. Current
frequency the QPI Link is using.
Intel® Turbo Boost
Technology
Enabled
Enhanced Intel
SpeedStep® Tech
Enabled
Disabled
Disabled
Intel® Turbo Boost Technology allows the
processor to automatically increase its
frequency if it is running below power,
temperature, and current specifications.
This option is only visible if all
processors in the system
support Intel® Turbo Boost
Technology.
Enhanced Intel SpeedStep® Technology allows
the system to dynamically adjust processor
voltage and core frequency, which can result
in decreased average power consumption and
decreased average heat production.
Contact your OS vendor regarding OS support
of this feature.
Intel® Hyper-Threading
Tech
Enabled
Disabled
Intel® HT Technology allows multithreaded
software applications to execute threads in
parallel within each processor.
Contact your OS vendor regarding OS support
of this feature.
Core Multi-Processing
All
1
Execute Disable Bit
2
Enabled
Disabled
Enable 1, 2 or All cores of installed processors
packages.
Execute Disable Bit can help prevent certain
classes of malicious buffer overflow attacks.
Contact your OS vendor regarding OS support
of this feature.
Revision 1.2
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101
BIOS Setup Utility
Setup Item
Intel® Virtualization
Technology
Intel® Workstation System SC5650SCWS TPS
Options
Enabled
Disabled
Help Text
Intel® Virtualization Technology allows a
platform to run multiple operating systems
and applications in independent partitions.
Comments
Note: A change to this option requires the
system to be powered off and then back on
before the setting takes effect.
Intel® Virtualization
Technology for Directed
I/O
Enabled
Interrupt Remapping
Enabled
Coherency Support
Disabled
Enable/Disable Intel® Virtualization Technology
for Directed I/O.
Report the I/O device assignment to VMM
through DMAR ACPI Tables
Disabled
Enable/Disable Intel® VT-d Interrupt
Remapping support.
Only appears when Intel®
Virtualization Technology for
Directed I/O is enabled.
Enabled
Enable/Disable Intel® VT-d Coherency support.
Only appears when Intel®
Virtualization Technology for
Directed I/O is enabled.
Enable/Disable Intel® VT-d Address Translation
Services (ATS) support.
Only appears when Intel®
Virtualization Technology for
Directed I/O is enabled.
Enable/Disable Intel® VT-d Pass-through DMA
support.
Only appears when Intel®
Virtualization Technology for
Directed I/O is enabled.
Disabled
ATS Support
Enabled
Disabled
Pass-through DMA
Support
Enabled
Hardware Prefetcher
Enabled
Disabled
Disabled
Hardware Prefetcher is a speculative prefetch
unit within the processor(s).
Note: Modifying this setting may affect
system performance.
Adjacent Cache Line
Prefetch
Enabled
Disabled
[Enabled] - Cache lines are fetched in pairs
(even line + odd line).
[Disabled] - Only the current cache line
required is fetched.
Note: Modifying this setting may affect
system performance.
Direct Cache Access (DCA)
Enabled
Disabled
102
Allows processors to increase the I/O
performance by placing data from I/O devices
directly into the processor cache.
Revision 1.2
Intel order number: E81822-002
Intel® Workstation System SC5650SCWS TPS
6.3.2.2.2
BIOS Setup Utility
Memory Screen
The Memory screen allows the user to view details about the system memory DDR3 DIMMs
installed. This screen also allows the user to open the Configure Memory RAS and Performance
screen.
To access this screen from the Main screen, select Advanced > Memory.
Advanced
Memory Configuration
Total Memory
<Total Physical Memory Installed in System>
Effective Memory
<Total Effective Memory>
Current Configuration
<Independent / Mirror>
Current Memory Speed
<Speed that installed memory is running at.>
► Memory RAS and Performance Configuration
DIMM Information
DIMM_A1
Installed/Not Installed/Failed/Disabled
DIMM_A2
Installed/Not Installed/Failed/Disabled
DIMM_B1
Installed/Not Installed/Failed/Disabled
DIMM_B2
Installed/Not Installed/Failed/Disabled
DIMM_C1
Installed/Not Installed/Failed/Disabled
DIMM_C2
Installed/Not Installed/Failed/Disabled
DIMM_D1
Installed/Not Installed/Failed/Disabled
DIMM_D2
Installed/Not Installed/Failed/Disabled
DIMM_E1
Installed/Not Installed/Failed/Disabled
DIMM_E2
Installed/Not Installed/Failed/Disabled
DIMM_F1
Installed/Not Installed/Failed/Disabled
DIMM_F2
Installed/Not Installed/Failed/Disabled
Figure 33. Setup Utility — Memory Configuration Screen Display
Revision 1.2
Intel order number: E81822-002
103
BIOS Setup Utility
Intel® Workstation System SC5650SCWS TPS
Table 56. Setup Utility — Memory Configuration Screen Fields
Setup Item
Total Memory
Options
Help Text
Effective Memory
Comments
Information only. The amount of memory
available in the system in the form of
installed DDR3 DIMMs in units of MB or GB.
Information only. The amount of memory
available to the operating system in MB or
GB.
The Effective Memory is the difference
between Total Physical Memory and the sum
of all memory reserved for internal usage,
RAS redundancy and SMRAM. This difference
includes the sum of all DDR3 DIMMs that
failed Memory BIST during POST, or were
disabled by the BIOS during memory
discovery phase in order to optimize memory
configuration.
Current Configuration
Information only. Displays one of the
following:
– Independent Mode: System memory is
configured for optimal performance
and efficiency and no RAS is enabled.
–
Current Memory Speed
Memory RAS and
Performance
Configuration
DIMM_ XY
Mirror Mode: System memory is
configured for maximum reliability in
the form of memory mirroring.
Information only. Displays the speed the
memory is running at.
Configure memory RAS
(Reliability, Availability, and
Serviceability) and view
current memory
performance information
and settings.
Select to configure the memory RAS and
performance. This takes the user to a
different screen.
Displays the state of each DIMM socket
present on the board. Each DIMM socket field
reflects one of the following possible states:
– Installed: There is a DDR3 DIMM
installed in this slot.
–
Not Installed: There is no DDR3 DIMM
installed in this slot.
–
Disabled: The DDR3 DIMM installed in
this slot was disabled by the BIOS to
optimize memory configuration.
–
Failed: The DDR3 DIMM installed in this
slot is faulty / malfunctioning.
Note: X denotes the Channel Identifier and Y
denote the DIMM Identifier within the
Channel.
104
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BIOS Setup Utility
6.3.2.2.2.1
Configure Memory RAS and Performance Screen
The Configure Memory RAS and Performance screen allows the user to customize several
memory configuration options, such as whether to use Memory Mirroring.
To access this screen from the Main screen, select Advanced > Memory > Configure Memory
RAS and Performance.
Advanced
Memory RAS and Performance Configuration
Capabilities
Memory Mirroring Possible
Yes / No
Select Memory RAS Configuration
Maximum Performance / Mirroring
NUMA Optimized
Disabled/ Enabled
Figure 34. Setup Utility — Configure RAS and Performance Screen Display
Table 57. Setup Utility — Configure RAS and Performance Screen Fields
Setup Item
Memory Mirroring
Possible
Options
Yes / No
Help Text
Comments
Information only. Only displayed on
systems with chipsets capable of
Memory Mirroring.
Select Memory RAS
Configuration
Maximum Performance
Available modes depend on the current
memory population.
Only available if Mirroring is
possible.
NUMA Optimized
Mirroring
Enabled
Disabled
[Maximum Performance] - Optimizes
system performance.
[Mirroring] - Optimizes reliability by using
half of physical memory as a backup.
If enabled, BIOS includes ACPI tables that
are required for NUMA aware Operating
Systems.
Revision 1.2
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105
BIOS Setup Utility
6.3.2.2.3
Intel® Workstation System SC5650SCWS TPS
Mass Storage Controller Screen
The Mass Storage screen allows the user to configure the SATA/SAS controller when it is
present on the baseboard, module card of an Intel system.
To access this screen from the Main menu, select Advanced > Mass Storage.
Advanced
Mass Storage Controller Configuration
®
Intel Entry SAS RAID Module
®
Enabled / Disabled
Configure Intel Entry SAS RAID Module
IT/IR RAID / Intel® ESRTII
Onboard SATA Controller
Enabled / Disabled
Configure SATA Mode
ENHANCED / COMPATIBILITY / AHCI / SW RAID
► SATA Port 0
Not Installed/<Drive Info.>
► SATA Port 1
Not Installed/<Drive Info.>
► SATA Port 2
Not Installed/<Drive Info.>
► SATA Port 3
Not Installed/<Drive Info.>
► SATA Port 4
Not Installed/<Drive Info.>
► SATA Port 5
Not Installed/<Drive Info.>
Figure 35. Setup Utility — Mass Storage Controller Configuration Screen Display
106
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BIOS Setup Utility
Table 58. Setup Utility — Mass Storage Controller Configuration Screen Fields
Setup Item
Intel® Entry SAS RAID
Module
Options
Enabled
Disabled
Help Text
Enabled or Disable the Intel® SAS Entry RAID
Module
Comments
Unavailable if the SAS Module
(AXX4SASMOD) is not present.
Configure Intel® Entry
SAS RAID Module
IT/IR RAID
IT/IR RAID – Supports Entry-Level HW RAID 0, RAID
1, and RAID 1e, as well as native SAS pass through
mode; Intel® ESRTII - Intel® Embedded Server RAID
Technology II, which supports RAID 0, RAID 1, RAID
10 and RAID 5 mode. RAID 5 support requires
optional Software RAID 5 Activation Key
Unavailable if the SAS Module
(AXX4SASMOD) is disabled or not
present.
Onboard SATA
Controller
Enabled
SATA Mode
Enhanced
Intel® ESRTII
Onboard Serial ATA (SATA) controller.
Disabled
Compatibility
AHCI
SW RAID
[ENHANCED] - Supports up to 6 SATA ports with
IDE Native Mode.
[COMPATIBILITY] - Supports up to 4 SATA ports
[0/1/2/3] with IDE Legacy mode and 2 SATA ports
[4/5] with IDE Native Mode.
[AHCI] - Supports all SATA ports using the
Advanced Host Controller Interface.
[SW RAID] - Supports configuration of SATA ports
for RAID via RAID configuration software.
Disappears when the Onboard
SATA Controller is disabled.
Changing this setting requires a
reboot before you can set HDD
boot order.
[SW RAID] option is unavailable
when EFI Optimized Boot is
Enabled. You can only use SW
RAID in Legacy Boot mode.
Information only. This field is
unavailable when RAID Mode is
enabled.
SATA Port 0
< Not
Installed /
Drive
information>
SATA Port 1
< Not
Installed /
Drive
information>
Information only. This field is
unavailable when RAID Mode is
enabled.
SATA Port 2
< Not
Installed /
Drive
information>
Information only. This field is
unavailable when RAID Mode is
enabled.
SATA Port 3
< Not
Installed /
Drive
information>
Information only. This field is
unavailable when RAID Mode is
enabled.
SATA Port 4
< Not
Installed /
Drive
information>
Information only. This field is
unavailable when RAID Mode is
enabled.
SATA Port 5
< Not
Installed /
Drive
information>
Information only. This field is
unavailable when RAID Mode is
enabled.
Revision 1.2
Intel order number: E81822-002
107
BIOS Setup Utility
6.3.2.2.4
Intel® Workstation System SC5650SCWS TPS
Serial Ports Screen
The Serial Ports screen allows the user to configure the Serial A [COM 1] and Serial B [COM2]
ports.
To access this screen from the Main screen, select Advanced > Serial Port.
Advanced
Serial Port Configuration
Serial A Enable
Enabled/Disabled
Address
3F8h / 2F8h / 3E8h / 2E8h
IRQ
3 or 4
Serial B Enable
Enabled/Disabled
Address
3F8h / 2F8h / 3E8h / 2E8h
IRQ
3 or 4
Figure 36. Setup Utility — Serial Port Configuration Screen Display
Table 59. Setup Utility — Serial Ports Configuration Screen Fields
Setup Item
Serial A Enable
Options
Enabled
Help Text
Enable or Disable Serial port A.
Disabled
Address
3F8h
Select Serial port A base I/O address.
2F8h
3E8h
2E8h
IRQ
3
Select Serial port A interrupt request (IRQ) line.
4
Serial B Enable
Enabled
Enable or Disable Serial port B.
Disabled
Address
3F8h
Select Serial port B base I/O address.
2F8h
3E8h
2E8h
IRQ
3
Select Serial port B interrupt request (IRQ) line.
4
108
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6.3.2.2.5
BIOS Setup Utility
USB Configuration Screen
The USB Configuration screen allows the user to configure the USB controller options.
To access this screen from the Main screen, select Advanced > USB Configuration.
Advanced
USB Configuration
Detected USB Devices
<Total USB Devices in System>
USB Controller
Enabled / Disabled
Legacy USB Support
Enabled / Disabled / Auto
Port 60/64 Emulation
Enabled / Disabled
Make USB Devices Non-Bootable
Enabled / Disabled
USB Mass Storage Device Configuration
Device Reset timeout
10 seconds / 20 seconds / 30 seconds / 40 seconds
Mass Storage Devices:
<Mass storage devices one line/device>
Auto / Floppy/Forced FDD/Hard Disk/CD-ROM
USB 2.0 controller
Enabled / Disabled
Figure 37. Setup Utility — USB Controller Configuration Screen Display
Revision 1.2
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109
BIOS Setup Utility
Intel® Workstation System SC5650SCWS TPS
Table 60. Setup Utility — USB Controller Configuration Screen Fields
Setup Item
Detected USB
Devices
Options
Help Text
USB Controller
Enabled
[Enabled] - All onboard USB controllers are turned on and
accessible by the OS.
Disabled
Comments
Information only. Shows the number
of USB devices in the system.
[Disabled] - All onboard USB controllers are turned off and
inaccessible by the OS.
Legacy USB
Support
Enabled
Disabled
USB device boot support and PS/2 emulation for USB
keyboard and USB mouse devices.
Auto
[Auto] - Legacy USB support is enabled if a USB device is
attached.
Port 60/64
Emulation
Enabled
I/O port 60h/64h emulation support.
Disabled
Note: This may be needed for legacy USB keyboard support
when using an OS that is USB unaware.
Make USB Devices
Non-Bootable
Enabled
Exclude USB in Boot Table.
Disabled
[Enabled] - This removes all USB Mass Storage devices as
Boot options.
Grayed out if the USB Controller is
disabled.
Grayed out if the USB Controller is
disabled.
Grayed out if the USB Controller is
disabled.
[Disabled] - This allows all USB Mass Storage devices as Boot
options.
Device Reset
timeout
10 sec
USB Mass Storage device Start Unit command timeout.
20 sec
Setting to a larger value provides more time for a mass
storage device to be ready, if needed.
30 sec
Grayed out if the USB Controller is
disabled.
40 sec
One line for each
mass storage
device in system
Auto
Floppy
Forced FDD
Hard Disk
[Auto] - USB devices less than 530 MB are emulated as
floppies.
[Forced FDD] - HDD formatted drive are emulated as a FDD
(e.g., ZIP drive).
CD-ROM
Hidden if no USB Mass storage
devices are installed.
Grayed out if the USB Controller is
disabled.
This setup screen can show a
maximum of eight devices on this
screen.
If more than eight devices are
installed in the system, USB Devices
Enabled displays the correct count,
but can only display the first eight
devices.
USB 2.0 controller
110
Enabled
Onboard USB ports are enabled to support USB 2.0 mode.
Disabled
Contact your OS vendor regarding OS support of this feature.
Grayed out if the USB Controller is
disabled.
Revision 1.2
Intel order number: E81822-002
Intel® Workstation System SC5650SCWS TPS
6.3.2.2.6
BIOS Setup Utility
PCI Screen
The PCI Screen allows the user to configure the PCI add-in cards, onboard NIC controllers, and
video options.
To access this screen from the Main screen, select Advanced > PCI.
Advanced
PCI Configuration
Maximize Memory below 4GB
Enabled / Disabled
Memory Mapped I/O above 4GB
Enabled / Disabled
Onboard Video
Enabled / Disabled
Dual Monitor Video
Enabled / Disabled
Onboard NIC1 ROM
Enabled / Disabled
Onboard NIC2 ROM
Enabled / Disabled
Onboard NIC iSCSI ROM
Enabled / Disabled
NIC 1 MAC Address
<MAC #>
NIC 2 MAC Address
<MAC #>
Figure 38. Setup Utility — PCI Configuration Screen Display
Table 61. Setup Utility — PCI Configuration Screen Fields
Setup Item
Maximize Memory
below 4GB
Options
Enabled
Memory Mapped I/O
above 4GB
Enabled
Onboard Video
Dual Monitor Video
Comments
Disabled
Help Text
BIOS maximizes memory usage below 4GB for an OS
without PAE support, depending on the system
configuration. Only enable for an OS without PAE
support
Enable or disable memory mapped I/O of 64-bit PCI
devices to 4 GB or greater address space.
Enabled
Onboard video controller.
Disabled
Warning: System video is completely disabled if this
option is disabled and an add-in video adapter is not
installed.
When disabled, the system
requires an add-in video
card for the video to be
seen.
Enabled
If enabled. both the onboard video controller and an
add-in video adapter are enabled for system video.
The onboard video controller becomes the primary
video device.
Disabled
Disabled
Onboard NIC1 ROM
Enabled
Disabled
If enabled. loads the embedded option ROM for the
onboard network controllers.
Warning: If [Disabled] is selected, NIC1 cannot be
used to boot or wake the system.
Revision 1.2
Intel order number: E81822-002
111
BIOS Setup Utility
Setup Item
Onboard NIC2 ROM
Intel® Workstation System SC5650SCWS TPS
Options
Enabled
Disabled
Help Text
If enabled. loads the embedded option ROM for the
onboard network controllers.
Comments
Warning: If [Disabled] is selected, NIC2 cannot be
used to boot or wake the system.
Onboard NIC iSCSI ROM
Enabled
Disabled
If enabled. loads the embedded option ROM for the
onboard network controllers.
Warning: If [Disabled] is selected, NIC1 and NIC2
cannot be used to boot or wake the system.
This option is grayed out
and not accessible if either
the NIC1 or NIC2 ROMs are
enabled.
NIC 1 MAC Address
No entry
allowed
Information only. 12 hex
digits of the MAC address.
NIC 2 MAC Address
No entry
allowed
Information only. 12 hex
digits of the MAC address.
112
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Intel® Workstation System SC5650SCWS TPS
6.3.2.2.7
BIOS Setup Utility
System Acoustic and Performance Configuration
The System Acoustic and Performance Configuration screen allows the user to configure the
thermal characteristics of the system.
To access this screen from the Main screen, select Advanced > System Acoustic and
Performance Configuration.
Advanced
System Acoustic and Performance Configuration
Set Throttling Mode
Auto / CLTT / OLTT
Altitude
300m or less / 301m-900m / 901m – 1500m / Higher than 1500m
Set Fan Profile
Performance, Acoustic
Figure 39. Setup Utility — System Acoustic and Performance Configuration Screen Display
Table 62. Setup Utility — System Acoustic and Performance Configuration Screen Fields
Setup Item
Set Throttling
Mode
Altitude
Options
Auto
Help Text
[Auto] – Auto Throttling mode.
CLTT
[CLTT] – Closed Loop Thermal Throttling Mode.
OLTT
300m or less
[OLTT] – Open Loop Thermal Throttling Mode.
[300m or less] (980ft or less)
301m-900m
Optimal performance setting near sea level.
901m-1500m
[301m - 900m] (980ft - 2950ft)
Higher than 1500m
Optimal performance setting at moderate elevation.
Comments
[901m – 1500m] (2950ft – 4920ft)
Optimal performance setting at high elevation.
[Higher than 1500m] (4920ft or greater)
Optimal performance setting at the highest elevations.
Set Fan Profile
Performance
Acoustics
6.3.2.3
[Performance] - Fan control provides primary system
cooling before attempting to throttle memory.
This option is hidden
if CLTT is enabled.
[Acoustic] - The system will favor using throttling of
memory over boosting fans to cool the system if thermal
thresholds are met.
Security Screen
The Security screen allows the user to enable and set the user and administrative password.
This is done to lock out the front panel buttons so they cannot be used. This screen also allows
the user to enable and activate the Trusted Platform Module (TPM) security settings.
To access this screen from the Main screen, select Security.
Revision 1.2
Intel order number: E81822-002
113
BIOS Setup Utility
Main
Intel® Workstation System SC5650SCWS TPS
Advanced
Security
Server Management
Administrator Password Status
<Installed/Not Installed>
User Password Status
<Installed/Not Installed>
Set Administrator Password
[1234aBcD]
Set User Password
[1234aBcD]
Front Panel Lockout
Enabled / Disabled
TPM State
TPM Administrative Control
Boot Options
Boot Manager
<Enabled & Activated/Enabled & Deactivated/Disabled &
Activated/Disabled & Deactivated>
No Operation / Turn On / Turn Off / Clear Ownership
Figure 40. Setup Utility — Security Configuration Screen Display
Table 63. Setup Utility — Security Configuration Screen Fields
Setup Item
Administrator Password
Status
User Password Status
Options
<Installed
Help Text
Not Installed>
<Installed
Information only. Indicates
the status of the user
password.
Not Installed>
Set Administrator
Password
[123aBcD]
Administrator password is used
to control change access in BIOS
Setup Utility.
This option only controls
access to the setup.
Only alphanumeric characters can
be used. Maximum length is 7
characters. It is case sensitive.
Administrator has full access
to all the setup items.
Clearing the Administrator
password also clears the
user password.
Note: Administrator password
must be set in order to use the
user account.
Set User Password
[123aBcD]
Comments
Information only. Indicates
the status of the
administrator password.
User password is used to control
entry access to BIOS Setup
Utility.
Only alphanumeric characters can
be used. Maximum length is 7
characters. It is case sensitive.
Available only if the
administrator password is
installed. This option only
protects the setup.
User password only has
limited access to the setup
Note: Removing the administrator items.
password also automatically
removes the user password.
114
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Intel® Workstation System SC5650SCWS TPS
Setup Item
Front Panel Lockout
Options
Enabled
Help Text
If enabled, locks the power
button and reset button on the
system's front panel. If [Enabled]
is selected, power and reset must
be controlled via a system
management interface.
Disabled
TPM State
BIOS Setup Utility
Comments
Enabled and Activated
Information only.
Enabled and Deactivated
Shows the current TPM
device state.
Disabled and Activated
A disabled TPM device does
not execute commands that
use the TPM functions and
TPM security operations are
not available.
Disabled and Deactivated
An enabled and deactivated
TPM is in the same state as a
disabled TPM except setting
of the TPM ownership is
allowed if not present
already.
An enabled and activated
TPM executes all commands
that use the TPM functions
and TPM security operations
are also available.
TPM Administrative
Control
No Operation
[No Operation] - No changes to
current state.
Turn On
Turn Off
Clear Ownership
[Turn On] - Enables and activates
TPM.
[Turn Off] - Disables and
deactivates TPM.
[Clear Ownership] - Removes the
TPM ownership authentication
and returns the TPM to a factory
default state.
Note: The BIOS setting returns to
[No Operation] on every boot
cycle by default.
6.3.2.4
Server Management Screen
The Server Management screen allows the user to configure several server management
features. This screen also provides an access point to the screens for configuring console
redirection and displaying system information.
To access this screen from the Main screen, select Server Management.
Revision 1.2
Intel order number: E81822-002
115
BIOS Setup Utility
Main
Advanced
Intel® Workstation System SC5650SCWS TPS
Security
Server Management
Boot Options
Boot Manager
Assert NMI on SERR
Enabled / Disabled
Assert NMI on PERR
Enabled / Disabled
Resume on AC Power Loss
Stay Off / Last state / Reset
Clear System Event Log
Enabled / Disabled
FRB-2 Enable
Enabled / Disabled
O/S Boot Watchdog Timer
Enabled / Disabled
O/S Boot Watchdog Timer Policy
Power off / Reset
O/S Boot Watchdog Timer Timeout
5 minutes / 10 minutes / 15 minutes / 20 minutes
ACPI 1.0 Support
Enabled / Disabled
Plug & Play BMC Detection
Enabled / Disabled
► Console Redirection
► System Information
Figure 41. Setup Utility — Server Management Configuration Screen Display
116
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BIOS Setup Utility
Table 64. Setup Utility — Server Management Configuration Screen Fields
Setup Item
Assert NMI on SERR
Assert NMI on PERR
Resume on AC Power
Loss
Options
Enabled
Help Text
On SERR, generate an NMI and log an error.
Disabled
Note: [Enabled] must be selected for the Assert NMI on
PERR setup option to be visible.
Enabled
On PERR, generate an NMI and log an error.
Disabled
Note: This option is only active if the Assert NMI on
SERR option is [Enabled] selected.
Stay Off
System action to take on AC power loss recovery.
Last state
[Stay Off] - System stays off.
Reset
[Last State] - System returns to the same state before
the AC power loss.
Comments
[Reset] - System powers on.
Clear System Event
Log
Enabled
Disabled
If enabled, clears the System Event Log. All current
entries will be lost.
Note: This option is reset to [Disabled] after a reboot.
FRB-2 Enable
O/S Boot Watchdog
Timer
Enabled
Fault Resilient Boot (FRB).
Disabled
If enabled, the BIOS programs the BMC watchdog timer
for approximately 6 minutes. If the BIOS does not
complete POST before the timer expires, the BMC resets
the system.
Enabled
If enabled, the BIOS programs the watchdog timer with
the timeout value selected. If the OS does not complete
booting before the timer expires, the BMC resets the
system and an error is logged.
Disabled
Requires OS support or Intel Management Software.
O/S Boot Watchdog
Timer Policy
Power Off
Reset
If the OS boot watchdog timer is enabled, this is the
system action taken if the watchdog timer expires.
Grayed out when O/S Boot
Watchdog Timer is disabled.
[Reset] - System performs a reset.
[Power Off] - System powers off.
O/S Boot Watchdog
Timer Timeout
5 minutes
10 minutes
If the OS watchdog timer is enabled, this is the timeout
value used by the BIOS to configure the watchdog timer.
Grayed out when O/S Boot
Watchdog Timer is disabled.
15 minutes
20 minutes
Plug & Play BMC
Detection
Enabled
ACPI 1.0 Support
Enabled
Disabled
Disabled
If enabled, the BMC is detectable by OSs that support
plug and play loading of an IPMI driver. Do not enable if
your OS does not support this driver.
[Enabled] - Publish ACPI 1.0 version of FADT in Root
System Description Table.
May be required for compatibility with OS versions that
only support ACPI 1.0.
Needs to be [Enabled] for
Microsoft Windows 2000*
support.
Console Redirection
View/Configure console redirection information and
settings.
Takes the user to the
Console Redirection screen.
System Information
View system information
Takes the user to the
System Information screen.
Revision 1.2
Intel order number: E81822-002
117
BIOS Setup Utility
6.3.2.4.1
Intel® Workstation System SC5650SCWS TPS
Console Redirection Screen
The Console Redirection screen allows the user to enable or disable console redirection and
configure the connection options for this feature.
To access this screen from the Main screen, select Server Management > Console Redirection.
Server Management
Console Redirection
Console Redirection
Disabled / Serial Port A / Serial Port B
Flow Control
None / RTS/CTS
Baud Rate
9.6k / 19.2k / 38.4k / 57.6k / 115.2k
Terminal Type
PC-ANSI / VT100 / VT100+ / VT-UTF8
Legacy OS Redirection
Disabled / Enabled
Figure 42. Setup Utility — Console Redirection Screen Display
118
Revision 1.2
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Intel® Workstation System SC5650SCWS TPS
BIOS Setup Utility
Table 65. Setup Utility — Console Redirection Configuration Fields
Setup Item
Console Redirection
Options
Disabled
Serial Port A
Help Text
Console redirection allows a serial port to be used for
server management tasks.
Serial Port B
[Disabled] - No console redirection.
[Serial Port A] - Configure serial port A for console
redirection.
[Serial Port B] - Configure serial port B for console
redirection.
Enabling this option disables the display of the Quiet
Boot logo screen during POST.
Flow Control
None
Flow control is the handshake protocol.
RTS/CTS
Setting must match the remote terminal application.
[None] - Configure for no flow control.
[RTS/CTS] - Configure for hardware flow control.
Baud Rate
9600
Serial port transmission speed. Setting must match the
remote terminal application.
19.2K
38.4K
57.6K
115.2K
Terminal Type
PC-ANSI
VT100
Character formatting used for console redirection.
Setting must match the remote terminal application.
VT100+
VT-UTF8
Legacy OS Redirection
Disabled
Enabled
This option enables legacy OS redirection (i.e., DOS) on
serial port. If it is enabled, the associated serial port is
hidden from the legacy OS.
Revision 1.2
Intel order number: E81822-002
119
BIOS Setup Utility
6.3.2.5
Intel® Workstation System SC5650SCWS TPS
Server Management System Information Screen
The Server Management System Information screen allows the user to view part numbers,
serial numbers, and firmware revisions.
To access this screen from the Main screen, select Server Management > System
Information.
Server Management
System Information
Board Part Number
Board Serial Number
System Part Number
System Serial Number
Chassis Part Number
Chassis Serial Number
Asset Tag
BMC Firmware Revision
HSC Firmware Revision
ME Firmware Revision
SDR Revision
UUID
Figure 43. Setup Utility — Server Management System Information Screen Display
Table 66. Setup Utility — Server Management System Information Fields
Setup Item
Board Part Number
Comments
Information only
Board Serial Number
Information only
System Part Number
Information only
System Serial Number
Information only
Chassis Part Number
Information only
Chassis Serial Number
Information only
Asset Tag
Information only
BMC Firmware Revision
Information only
HSC Firmware Revision
Information only. If there is no HSC installed, the Firmware
Revision Number will appear as “0.00”.
ME Firmware Revision
Information only
SDR Revision
Information only
UUID
Information only
120
Revision 1.2
Intel order number: E81822-002
Intel® Workstation System SC5650SCWS TPS
6.3.2.6
BIOS Setup Utility
Boot Options Screen
The Boot Options screen displays any bootable media encountered during POST and allows the
user to configure the desired boot device.
To access this screen from the Main screen, select Boot Options.
Main
Advanced
Security
Server Management
Boot Options
System Boot Timeout
<0 - 65535>
Boot Option #1
<Available Boot devices>
Boot Option #2
<Available Boot devices>
Boot Option #x
<Available Boot devices>
Boot Manager
Hard Disk Order
CDROM Order
Floppy Order
Network Device Order
BEV Device Order
Add New Boot Option
►Delete Boot Option
EFI Optimized Boot
Enabled / Disabled
Use Legacy Video for EFI OS
Enabled / Disabled
Boot Option Retry
USB Boot Priority
Enabled / Disabled
Enabled / Disabled
Figure 44. Setup Utility — Boot Options Screen Display
Revision 1.2
Intel order number: E81822-002
121
BIOS Setup Utility
Intel® Workstation System SC5650SCWS TPS
Table 67. Setup Utility — Boot Options Screen Fields
Setup Item
Boot Timeout
Options
0 - 65535
Help Text
The number of seconds the BIOS should pause at
the end of POST to allow the user to press the
[F2] key for entering the BIOS Setup utility.
Valid values are 0-65535. Zero is the default. A
value of 65535 causes the system to go to the
Boot Manager menu and wait for user input for
every system boot.
Boot Option #x
Available
boot
devices.
Comments
After entering the necessary
timeout, press the Enter key
to register that timeout value
to the system. These settings
are in seconds.
Set system boot order by selecting the boot
option for this position.
Hard Disk Order
Set the order of the legacy devices in this group.
Displays when one or more
hard disk drives are in the
system.
CDROM Order
Set the order of the legacy devices in this group.
Displays when one or more
CD-ROM drives are in the
system.
Floppy Order
Set the order of the legacy devices in this group.
Displays when one or more
floppy drives are in the
system.
Network Device Order
Set the order of the legacy devices in this group.
Displays when one or more of
these devices are available in
the system.
BEV Device Order
Set the order of the legacy devices in this group.
Displays when one or more of
these devices are available in
the system.
Add New Boot Option
Add a new EFI boot option to the boot order.
This option is only displayed
if an EFI bootable device is
available to the system (for
example, a USB drive).
Delete Boot Option
Remove an EFI boot option from the boot order.
If the EFI shell is deleted, it is
restored on the next system
reboot. It cannot be
permanently deleted.
If enabled, the BIOS only loads modules required
for booting EFI-aware Operating Systems.
Grayed out when [SW RAID]
SATA Mode is Enabled. SW
RAID can only be used in
Legacy Boot mode.
If enabled, the BIOS will use the legacy video
ROM instead of the EFI video ROM.
Only appears when EFI
Optimized Boot is enabled.
EFI Optimized Boot
Enabled
Disabled
Use Legacy Video for EFI
OS
Enabled
Boot Option Retry
Enabled
USB Boot Priority
Disabled
Enabled
Disabled
Disabled
122
If enabled, this continually retries non-EFI-based
boot options without waiting for user input.
If enabled newly discovered USB devices will be
put to the top of their boot device category.
If disabled newly discovered USB devices will be
put at the bottom of the respective list
Revision 1.2
Intel order number: E81822-002
Intel® Workstation System SC5650SCWS TPS
BIOS Setup Utility
If all types of bootable devices are installed in the system, the default boot order is:
1.
2.
3.
4.
5.
6.
CD/DVD-ROM
Floppy Disk Drive
Hard Disk Drive
PXE Network Device
BEV (Boot Entry Vector) Device
EFI Shell and EFI Boot paths
6.3.2.6.1
Add New Boot Option Screen
The Add Boot Option screen allows the user to remove an EFI boot option from the boot order.
To access this screen from the Main screen, select Boot Options > Delete Boot Options.
Boot Options
Add New Boot Option
Add boot option label
Select File system
<Available File systems>
Path for boot option
Save
Figure 45. Setup Utility — Add New Boot Option Screen Display
Table 68. Setup Utility — Add New Boot Option Fields
Setup Item
Add boot option label
Options
Help Text
Create the label for the new boot
option.
Select File system
Select one from list
provided.
Select one file system from the list.
Path for boot option
Enter the path to boot option in the
format:
\path\filename.efi
Save
Save the boot option.
Revision 1.2
Intel order number: E81822-002
123
BIOS Setup Utility
6.3.2.6.2
Intel® Workstation System SC5650SCWS TPS
Delete Boot Option Screen
The Delete Boot Option screen allows the user to remove an EFI boot option from the boot
order. Note that while you can delete the Internal EFI Shell in this screen, it is restored to the
Boot Order on the next reboot. You cannot permanently delete the Internal EFI Shell.
To access this screen from the Main screen, select Boot Options > Delete Boot Options.
Boot Options
Delete Boot Option
Delete Boot Option
Select one to Delete / Internal EFI Shell
Figure 46. Setup Utility — Delete Boot Option Screen Display
Table 69. Setup Utility — Delete Boot Option Fields
Setup Item
Delete Boot Option
Options
Select one to Delete
Internal EFI Shell
124
Help Text
Remove an EFI boot option from the
boot order.
Comments
If the EFI shell is deleted, it
is restored on the next
system reboot. It cannot
be permanently deleted.
Revision 1.2
Intel order number: E81822-002
Intel® Workstation System SC5650SCWS TPS
6.3.2.6.3
BIOS Setup Utility
Hard Disk Order Screen
The Hard Disk Order screen allows the user to control the hard disks.
To access this screen from the Main screen, select Boot Options > Hard Disk Order.
Boot Options
Hard Disk #1
< Available Hard Disks >
Hard Disk #2
< Available Hard Disks >
Figure 47. Setup Utility — Hard Disk Order Screen Display
Table 70. Setup Utility — Hard Disk Order Fields
6.3.2.6.4
Setup Item
Hard Disk #1
Options
Available Legacy
devices for this
Device group.
Help Text
Set system boot order by selecting the boot
option for this position.
Hard Disk #2
Available Legacy
devices for this
Device group.
Set system boot order by selecting the boot
option for this position.
CDROM Order Screen
The CDROM Order screen allows the user to control the CDROM devices.
To access this screen from the Main screen, select Boot Options > CDROM Order.
Boot Options
CDROM #1
<Available CDROM devices>
CDROM #2
<Available CDROM devices>
Figure 48. Setup Utility — CDROM Order Screen Display
Revision 1.2
Intel order number: E81822-002
125
BIOS Setup Utility
Intel® Workstation System SC5650SCWS TPS
Table 71. Setup Utility — CDROM Order Fields
Setup Item
CDROM #1
Options
Available Legacy
devices for this
Device group.
Help Text
Set system boot order by selecting the boot
option for this position.
CDROM #2
Available Legacy
devices for this
Device group.
Set system boot order by selecting the boot
option for this position.
6.3.2.6.5
Floppy Order Screen
The Floppy Order screen allows the user to control the floppy drives.
To access this screen from the Main screen, select Boot Options > Floppy Order.
Boot Options
Floppy Disk #1
<Available Floppy Disk >
Floppy Disk #2
<Available Floppy Disk >
Figure 49. Setup Utility — Floppy Order Screen Display
Table 72. Setup Utility — Floppy Order Fields
126
Setup Item
Floppy Disk #1
Options
Available Legacy
devices for this
Device group.
Help Text
Set system boot order by selecting the boot
option for this position.
Floppy Disk #2
Available Legacy
devices for this
Device group.
Set system boot order by selecting the boot
option for this position.
Revision 1.2
Intel order number: E81822-002
Intel® Workstation System SC5650SCWS TPS
6.3.2.6.6
BIOS Setup Utility
Network Device Order Screen
The Network Device Order screen allows the user to control the network bootable devices.
To access this screen from the Main screen, select Boot Options > Network Device Order.
Boot Options
Network Device #1
<Available Network devices>
Network Device #2
<Available Network devices>
Figure 50. Setup Utility — Network Device Order Screen Display
Table 73. Setup Utility — Network Device Order Fields
Setup Item
Network Device #1
Options
Available Legacy
devices for this
Device group.
Help Text
Set system boot order by selecting the boot
option for this position.
Network Device #2
Available Legacy
devices for this
Device group.
Set system boot order by selecting the boot
option for this position.
6.3.2.6.7
BEV Device Order Screen
The BEV Device Order screen allows the user to control the BEV bootable devices.
To access this screen from the Main screen, select Boot Options > BEV Device Order.
Boot Options
BEV Device #1
<Available BEV devices>
BEV Device #2
<Available BEV devices>
Figure 51. Setup Utility — BEV Device Order Screen Display
Revision 1.2
Intel order number: E81822-002
127
BIOS Setup Utility
Intel® Workstation System SC5650SCWS TPS
Table 74. Setup Utility — BEV Device Order Fields
6.3.2.7
Setup Item
BEV Device #1
Options
Available Legacy
devices for this
Device group.
Help Text
Set system boot order by selecting the boot
option for this position.
BEV Device #2
Available Legacy
devices for this
Device group.
Set system boot order by selecting the boot
option for this position.
Boot Manager Screen
The Boot Manager screen allows the user to view a list of devices available for booting, and to
select a boot device for immediately booting the system.
To access this screen from the Main screen, select Boot Manager.
Main
Advanced
Security
Server Management
Boot Options
Boot Manager
[Internal EFI Shell]
<Boot device #1>
<Boot Option #x>
Figure 52. Setup Utility — Boot Manager Screen Display
Table 75. Setup Utility — Boot Manager Screen Fields
Setup Item
Internal EFI Shell
Help Text
Select this option to boot now.
Note: This list is not the system boot option order. Use
the Boot Options menu to view and configure the
system boot option order.
Boot Device #x
Select this option to boot now.
Note: This list is not the system boot option order. Use
the Boot Options menu to view and configure the
system boot option order.
128
Revision 1.2
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Intel® Workstation System SC5650SCWS TPS
6.3.2.8
BIOS Setup Utility
Error Manager Screen
The Error Manager screen displays any errors encountered during POST.
Error Manager
ERROR CODE
Exit
SEVERITY
INSTANCE
Figure 53. Setup Utility — Error Manager Screen Display
Table 76. Setup Utility — Error Manager Screen Fields
Setup Item
Displays System Errors
Comments
Information only. Displays errors that occurred during the
POST.
Revision 1.2
Intel order number: E81822-002
129
BIOS Setup Utility
6.3.2.9
Intel® Workstation System SC5650SCWS TPS
Exit Screen
The Exit screen allows the user to choose whether to save or discard the configuration changes
made on the other screens. It also allows the user to restore the server to the factory defaults or
to save or restore them to set of user-defined default values. If Load Default Values is selected,
the system applies the factory default settings (noted in bold in the tables in this chapter). If
Load User Default Values is selected, the system is restored to the previously-saved, userdefined default values.
Error Manager
Exit
Save Changes and Exit
Discard Changes and Exit
Save Changes
Discard Changes
Load Default Values
Save as User Default Values
Load User Default Values
Figure 54. Setup Utility — Exit Screen Display
Table 77. Setup Utility — Exit Screen Fields
Setup Item
Save Changes and Exit
Help Text
Exit the BIOS Setup utility after saving changes.
The system reboots if required.
Comments
User prompted for confirmation only if
any of the setup fields were modified.
The [F10] key can also be used.
Discard Changes and Exit
Exit the BIOS Setup utility without saving
changes.
User prompted for confirmation only if
any of the setup fields were modified.
The [Esc] key can also be used.
Save Changes
Save changes without exiting the BIOS Setup
Utility.
User prompted for confirmation only if
any of the setup fields were modified.
Note: Saved changes may require a system reboot
before taking effect.
Discard Changes
Discard changes made since the last Save
Changes operation was performed.
User prompted for confirmation only if
any of the setup fields were modified.
Load Default Values
Load factory default values for all BIOS Setup
utility options.
User prompted for confirmation.
The [F9] key can also be used.
130
Revision 1.2
Intel order number: E81822-002
Intel® Workstation System SC5650SCWS TPS
Setup Item
Save as User Default
Values
Help Text
Save current BIOS Setup utility values as custom
user default values. If needed, the user default
values can be restored via the Load User Default
Values option below.
BIOS Setup Utility
Comments
User prompted for confirmation.
Note: Clearing the CMOS or NVRAM does not
cause the User Default values to be reset to the
factory default values.
Load User Default Values
Load user default values.
Revision 1.2
Intel order number: E81822-002
User prompted for confirmation.
131
Connector/Header Locations and Pin-outs
Intel® Workstation System SC5650SCWS TPS
7.
Connector/Header Locations and Pin-outs
7.1
Board Connector Information
The following section provides detailed information regarding all connectors, headers, and
jumpers on the workstation board.
The following table lists all connector types available on the board and the corresponding
preference designators printed on the silkscreen.
Table 78. Board Connector Matrix
Connector
Quantity
Reference Designators
J1K3
Connector Type
Main power
Pin Count
24
J9A1
CPU 1 power
8
J9K1
CPU 2 Power
8
Power supply
4
J9K2
P/S aux / IPMB
5
CPU
2
U7J1, U7C1
CPU sockets
1366
Main memory
12
J4F1, J5F1, J5F2, J5F3, J6F1, J6F2, J8F1, J8F2, J8F3, J9F1,
J9F2, J9F3
DIMM sockets
240
PCI Express* x16
4
J3B1, J4B1
Card edge
PCI Express* x8
1
J2B1
PCI Express* x4
1
J2B2
Card edge
32bit PCI
1
J1B2
Card edge
Intel® RMM3
1
J1C1
Mezzanine
34
SAS Module
1
J2J1
Mezzanine
50
SATA Software
RAID 5 Key
1
J1F2
Key holder
3
System fans
4
J1K1, J1K2, J1K4, J1K5
Header
6
System fans
1
J5B1
Header
4
CPU fans
2
J7K1, J9A2
Header
4
Battery
1
BT5B1
Battery holder
3
Stacked RJ45 /
2xUSB
2
JA5A1, JA6A2
External LAN
built-in magnetic
and dual USB
22
Audio
1
J6A1
External audio
port
Audio
1
J8A1
Internal front
panel audio
header
10
S/PDIF
1
J4C1
Internal S/PDIF
header
3
1394
1
J1D2
Internal 1394
port
10
Stacked Serial port
A/1394
1
J8A2
External RJ45
Serial Port A and
6-pin 1394
132
Revision 1.2
Intel order number: E81822-002
Intel® Workstation System SC5650SCWS TPS
Connector
Serial port A
Configuration
Quantity
1
Connector/Header Locations and Pin-outs
Reference Designators
Connector Type
J4B2
Pin Count
Jumper
3
Serial port B
1
J1B1
Header
9
Front panel
1
J1B3
Header
24
Internal USB
2
J1D1, J1D4
Header
10
USB_SSD
1
J1D3
Low profile
header
10
Internal USB
1
J1H2
Header
4
Chassis Intrusion
1
J2D1
Header
2
Serial ATA
6
J1G1, J1G4, J1G5, J1E3, J1F1, J1F4
Header
7
HSBP
2
J1F5, J1G3
Header
4
SATA SGPIO
1
J1G2
Header
4
LCP/IPMB
1
J1G6
Header
4
Configuration
jumpers
4
J2C1 (CMOS Clear), J1E2 (ME Force Update), J1E4
(Password Clear), J1E5 (BIOS Recovery), J1H1 (BMC
Force Update),
Jumper
3
HDD Activity Led
1
J1E1
Header
2
Internal Video
Header
1
J3B2
Header
14
7.2
Power Connectors
The main power supply connection uses an SSI-compliant 2x12 pin connector (J1K3).
Three additional power-related connectors also exist:
ƒ
Two SSI-compliant 2x4 pin power connectors (J9A1, J9K1) to provide 12-V power to the
CPU voltage regulators and memory.
ƒ
One SSI-compliant 1x5 pin connector (J9K2) to provide I2C monitoring of the power
supply
The following tables define these connector pin-outs.
Table 79. Power Connector Pin-out (J1K3)
Pin
Signal
Color
Pin
1
+3.3 Vdc
Orange
13
+3.3 Vdc
Signal
Orange
2
+3.3 Vdc
Orange
14
-12 Vdc
Blue
3
GND
Black
15
GND
Black
4
+5 Vdc
Red
16
PS_ON#
Green
5
GND
Black
17
GND
Black
6
+5 Vdc
Red
18
GND
Black
7
GND
Black
19
GND
Black
8
PWR_OK
Gray
20
RSVD_(-5 V)
White
9
5 VSB
Purple
21
+5 Vdc
Red
Revision 1.2
Intel order number: E81822-002
Color
133
Connector/Header Locations and Pin-outs
Intel® Workstation System SC5650SCWS TPS
10
+12 Vdc
Yellow
22
+5 Vdc
Red
11
+12 Vdc
Yellow
23
+5 Vdc
Red
12
+3.3 Vdc
Orange
24
GND
Black
Table 80. CPU 1 Power Connector Pin-out (J9A1)
Pin
1
Signal
GND of Pin 5
Black
Color
2
GND of Pin 6
Black
3
GND of Pin 7
Black
4
GND of Pin 8
Black
5
+12 Vdc CPU1
Yellow / black
6
+12 Vdc CPU1
Yellow / black
7
+12 Vdc DDR3_CPU1
Yellow / black
8
+12 Vdc DDR3_CPU1
Yellow / black
Table 81. CPU 2 Power Connector Pin-out (J9K1)
Pin
1
Signal
GND of Pin 5
Black
Color
2
GND of Pin 6
Black
3
GND of Pin 7
Black
4
GND of Pin 8
Black
5
+12 Vdc CPU2
Yellow / black
6
+12 Vdc CPU2
Yellow / black
7
+12 Vdc DDR3_CPU2
Yellow / black
8
+12 Vdc DDR3_CPU2
Yellow / black
Table 82. Power Supply Signal Connector Pin-out (J9K2)
Pin
1
2
3
4
5
134
Signal
SMB_CLK_FP_PWR_R
SMB_DAT_FP_PWR_R
SMB_ALRT_3_ESB_R
3.3 V SENSE3.3 V SENSE+
Color
Orange
Black
Red
Yellow
Green
Revision 1.2
Intel order number: E81822-002
Intel® Workstation System SC5650SCWS TPS
7.3
Connector/Header Locations and Pin-outs
System Management Headers
7.3.1
Intel® Remote Management Module 3 (Intel® RMM3) Connector
A 34-pin Intel® RMM3 connector (J1C1) is included on the workstation board to support the
optional Intel® Remote Management Module 3. This workstation board does not support thirdparty management cards.
Note: This connector is not compatible with the Intel® Remote Management Module (Intel®
RMM) or the Intel® Remote Management Module 2 (Intel® RMM2)
Table 83. Intel® RMM3 Connector Pin-out (J1C1)
Pin
Signal Name
3V3_AUX
2
RMII_MDIO
3
3V3_AUX
4
RMII_MDC
5
GND
6
RMII_RXD1
7
GND
8
RMII_RXD0
9
GND
10
RMII_RX_DV
1
Pin
Signal Name
11
GND
12
RMII_REF_CLK
13
GND
14
RMII_RX_ER
15
GND
16
RMII_TX_EN
17
GND
18
KEY (pin removed)
19
GND
20
RMII_TXD0
21
GND
22
RMII_TXD1
23
3V3_AUX
24
SPI_CS_N
25
3V3_AUX
26
NC (spare)
27
3V3_AUX
28
SPI_DO
29
GND
30
SPI_CLK
31
GND
32
SPI_DI
33
GND
34
RMM3_Present_N (pulled high on baseboard and
shorted to ground on the plug-in module)
7.3.2
LCP / IPMB Header
Table 84. LPC / IPMB Header Pin-out (J1G6)
Pin
1
Signal Name
SMB_IPMB_5VSB_DAT
Description
BMC IMB 5V standby data line
2
GND
Ground
3
SMB_IPMB_5VSB_CLK
BMC IMB 5V standby clock line
4
P5V_STBY
+5 V standby power
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7.3.3
Intel® Workstation System SC5650SCWS TPS
HSBP Header
Table 85. HSBP Header Pin-out (J1F5, J1G3)
Pin
1
Signal Name
SMB_IPMB_5V_DAT
Description
BMC IMB 5V Data Line
2
GND
Ground
3
SMB_IPMB_5V_CLK
BMC IMB 5V Clock Line
P5V – HSBP_A
+5V for HSBP A
GND – HSBP_B
Ground for HSBP B
4
7.3.4
SGPIO Header
Table 86. SGPIO Header Pin-out (J1G2)
Pin
1
2
3
4
7.4
Signal Name
SGPIO_CLOCK
SGPIO_LOAD
SGPIO_DATAOUT0
SGPIO_DATAOUT1
Description
SGPIO Clock Signal
SGPIO Load Signal
SGPIO Data Out
SGPIO Data In
Front Panel Connector
The workstation board provides a 24-pin SSI front panel connector (J1B3) for use with Intel® and
third-party chassis. The following table provides the pin-out for this connector.
Table 87. Front Panel SSI Standard 24-pin Connector Pin-out (J1B3)
136
Pin
Signal Name
Description
Pin
Signal Name
Description
1
P3V3_STBY
(Power_LED_Anode)
Power LED +
2
P3V3_STBY
Front Panel
Power
3
Key
No Connection
4
P5V_STBY (ID
LED Anode)
ID LED +
5
FP_PWR_LED_N
Power LED -
6
FP_ID_LED_BUF_
N
ID LED -
7
P3V3
(HDD_ACTIVITY_Anode
)
HDD Activity
LED +
8
FP_LED_STATUS
_GREEN_N
Status LED
Green -
9
LED_HDD_ACTIVITY_N
HDD Activity
LED -
10
FP_LED_STATUS
_AMBER_N
Status LED
Amber -
11
FP_PWR_BTN_N
Power Button
12
NIC1_ACT_LED_N
NIC 1 Activity
LED -
13
GND (Power Button
GND)
Power Button
Ground
14
NIC1_LINK_LED_
N
NIC 1 Link LED -
15
BMC_RST_BTN_N
Reset Button
16
SMB_SENSOR_3V
3STB_DATA
SMB Sensor
DATA
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7.5
Connector/Header Locations and Pin-outs
Pin
Signal Name
Description
Pin
Signal Name
Description
17
BND (Reset GND)
Reset Button
Ground
18
SMB_SENSOR_3V
3STB_CLK
SMB Sensor
Clock
19
FP_ID_BTN_N
ID Button
20
FP_CHASSIS_INT
RU
Chassis
Intrusion
21
FM_SIO_TEMP_SENSO
R
Front Panel
Temperature
Sensor
22
NIC2_ACT_LED_N
NIC 2 Activity
LED -
23
FP_NMI_BTN_N
NMI Button
24
NIC2_LINK_LED_
N
NIC 2 Link LED -
I/O Connectors
7.5.1
NIC Connectors
The workstation board provides two stacked RJ-45 / 2xUSB connectors side-by-side on the
back edge of the board (JA5A1, JA6A2). The pin-out for NIC connectors is identical and defined
in the following table.
Table 88. RJ-45 10/100/1000 NIC Connector Pin-out (JA5A1, JA6A2)
Pin
1
2
3
4
5
6
7
8
9
10
11 (D1)
12 (D2)
13 (D3)
14
15
16
7.5.2
Signal Name
GND
P1V8_NIC
NIC_A_MDI3P
NIC_A_MDI3N
NIC_A_MDI2P
NIC_A_MDI2N
NIC_A_MDI1P
NIC_A_MDI1N
NIC_A_MDI0P
NIC_A_MDI0N
NIC_LINKA_1000_N (LED
NIC_LINKA_100_N (LED)
NIC_ACT_LED_N
NIC_LINK_LED_N
GND
GND
SATA Connectors
The workstation board provides up to six SATA connectors: SATA-0 (J1G5), SATA-1 (J1G4),
SATA-2 (J1G1), SATA-3 (J1F4), SATA-4 (J1F1), and SATA-5 (J1E3).
The pin configuration for each connector is identical and defined in the following table.
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Table 89. SATA / SAS Connector Pin-out (J1E3, J1G1, J1G4, J1G5, J1F1, J1F4)
Pin
1
7.5.3
Signal Name
GND
Description
Ground
2
SATA TX_P_C
Positive side of transmit differential pair
3
SATA TX_N_C
Negative side of transmit differential pair
4
GND
Ground
5
SATA _RX_N_C
Negative side of receive differential pair
6
SATA _RX_P_C
Positive side of receive differential pair
7
GND
Ground
SAS Module Slot
The workstation board provides one mezzanine slot (J2J1) to support the SAS Module card.
The following table defines the pin-out.
Table 90. SAS Module Slot Pin-out (J2J1)
Pin
1
138
Name
P3V3_AUX
Pin
2
Name
RST_LPC_SAS_N
3
SW_RAID_MODE
4
GND
5
PE_ICH10_SAS_SW_C_TP0
6
PE_ICH10_SAS_SW_C_TN0
7
GND
8
GND
9
PE_ICH10_SAS_SW_C_TP1
10
PE_ICH10_SAS_SW_C_TN1
11
GND
12
GND
13
PE_ICH10_SAS_SW_C_TN2
14
PE_ICH10_SAS_SW_C_TN2
15
GND
16
GND
17
PE_ICH10_SAS_SW_C_TN3
18
PE_ICH10_SAS_SW_C_TN3
19
GND
20
FM_SAS_PRSNT_N
21
PE_WAKE_N
22
FM_SAS_RST_N
23
P3V3
24
PE_RXN<2>
25
P3V3
26
P3V3_AUX
27
GND
28
PE_ICH10_SAS_SW_RXP0
29
PE_ICH10_SAS_SW_RXN0
30
GND
31
GND
32
PE_ICH10_SAS_SW_RXP1
33
PE_ICH10_SAS_SW_RXN1
34
GND
35
GND
36
PE_ICH10_SAS_SW_RXP2
37
PE_ICH10_SAS_SW_RXN2
38
GND
39
GND
40
PE_ICH10_SAS_SW_RXP3
41
PE_ICH10_SAS_SW_RXN3
42
GND
43
GND
44
CLK_100M_SAS_DP
45
CLK_100M_SAS_DN
46
GND
47
GND
48
P3V3
49
P3V3
50
P3V3
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7.5.4
Connector/Header Locations and Pin-outs
Serial Port Connectors
The workstation board provides one external RJ-45 Serial A port (J8A2) and one internal 9-pin
Serial B header (J1B1). The following tables define the pin-outs.
Table 91. External RJ45 Serial A Port Pin-out (J8A2)
RJ-45
Signal Name
Description
1
RTS
Request to Send
2
DTR
Data Terminal Ready
3
TD
Transmitted Data
4
SGND
Signal Ground
5
RI
Ring Indicator
6
RD
Received Data
7
DCD/DSR
DCD or DSR
8
CTS
Clear To Send
Table 92. Internal 9-pin Serial B Header Pin-out (J1B1)
Pin
1
7.5.5
Signal Name
SPB_DCD
Description
DCD (carrier detect)
2
SPB_DSR
DSR (data set ready)
3
SPB_SIN_L
RXD (receive data)
4
SPB_RTS
RTS (request to send)
5
SPB_SOUT_N
TXD (Transmit data)
6
SPB_CTS
CTS (clear to send)
7
SPB_DTR
DTR (Data terminal ready)
8
SPB_RI
RI (Ring indicate)
9
SPB_EN_N
Enable
USB Connector
The following table details the pin-out of the external USB connectors (JA5A1, JA6A2) found on
the back edge of the workstation board.
Table 93. External USB Connector Pin-out (JA5A1, JA6A2)
Pin
1
Signal Name
USB_OC
USB_PWR
Description
2
USB_PN
DATAL0 (Differential data line paired with DATAH0)
3
USB_PP
DATAH0 (Differential data line paired with DATAL0)
4
GND
Ground
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Intel® Workstation System SC5650SCWS TPS
Two 2x5 connectors on the workstation board (J1D1, J1D4) provide support for four additional
USB ports.
Table 94. Internal USB Connector Pin-out (J1D1)
Pin
1
Signal Name
USB2_VBUS4
Description
USB power (port 4)
2
USB2_VBUS5
USB power (port 5)
3
USB_ICH_P4N_CONN
USB port 4 negative signal
4
USB_ICH_P5N_CONN
USB port 5 negative signal
5
USB_ICH_P4P_CONN
USB port 4 positive signal
6
USB_ICH_P5P_CONN
USB port 5 positive signal
7
Ground
8
Ground
9
Key
No pin
10
TP_USB_ICH_NC
Test point
Table 95. Internal USB Connector Pin-out (J1D4)
Pin
1
Signal Name
USB2_VBUS6
Description
USB power (port 6)
2
USB2_VBUS8
USB power (port 8)
3
USB_ICH_P6N_CONN
USB port 6 negative signal
4
USB_ICH_P8N_CONN
USB port 8 negative signal
5
USB_ICH_P6P_CONN
USB port 6 positive signal
6
USB_ICH_P8P_CONN
USB port 8 positive signal
7
Ground
8
Ground
9
Key
No pin
10
TP_USB_ICH_NC
Test point
One low-profile 2x5 connector (J1D3) on the workstation board provides an option to support a
low-profile Solid State Drive.
Table 96. Pin-out of Internal USB Connector for Low-Profile Solid State Drive (J1D3)
Pin
1
140
+5V
Signal Name
Description
USB power
2
NC
Not Connect
3
USB Data -
USB port 11 negative signal
4
NC
Not Connect
5
USB Data +
USB port 11 positive signal
Revision 1.2
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Pin
6
7
Signal Name
NC
Connector/Header Locations and Pin-outs
Description
Not Connect
Ground
8
NC
Not Connect
9
Key
No pin
10
LED#
Activity LED
One additional Type A USB port (J1H2) is provided on the workstation board to support the
installation of a USB device inside the workstation chassis.
Table 97. Internal Type A USB Port Pin-out (J1H2)
7.5.6
Pin
1
Signal Name
USB_OC
USB_PWR
Description
2
USB_ICH_P7N
USB port 7 negative signal
3
USB_ICH_P7P
USB port 7 positive signal
4
GND
Ground
IEEE 1394a connectors
The following table details the pin-out of the external IEEE 1394a port (J8A2).
Table 98.External IEEE 1394a Port Pin-out (J8A2)
Pin
1
Power
Signal Name
Description
1394 Power
2
GND
Ground
3
TPB-
TPB negative signal
4
TPB+
TPB positive signal
5
TPA-
TPA negative signal
6
TPA+
TPA positive signal
The following table details the pin-out of the internal 1394 connector (J1D2).
Table 99. Internal 1394 Port Pin-out (J1D2)
Pin
1
GND
Signal Name
Description
2
Key
3
PWR
1394 Power
4
PWR
1394 Power
5
TPB-
TPB negative signal
6
TPB+
TPB positive signal
7
GND
Ground
8
GND
Ground
Ground
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7.6
Signal Name
Intel® Workstation System SC5650SCWS TPS
Pin
9
TPA-
Description
TPA negative signal
10
TPA+
TPA positive signal
Audio Connectors
The workstation board provides one stacked audio connector on the back edge of the board
(J6A1). This stacked connector provides six jacks for audio connections (Back Surround Out,
Center/LFE Out, Front Surround Out, Line-in, Microphone in, and Side Surround Out).
The following table details the pin out of the internal front panel audio header (J1D2).
Table 100. Internal Front Panel Audio Header Pin-out (J1D2)
Pin
1
Signal Name
Port 2 L
Description
Audio Port 2 Left Channel
2
AGND_AUD
Ground
3
Port 2 R
Audio Port 2 Right Channel
4
Presence Detect
Detect Presence of Front
Panel Audio Port
5
Port 1 R
Audio Port 1 Right Channel
6
Port 2 Sense Return
7
AGND_AUD
8
Key
9
Port 1 L
10
Port 1 Sense Return
Ground
Audio Port 1 Left Channel
The following table details the pin out of the internal S/PDIF header (J4C1).
Table 101. Internal S/PDIF Header Pin-out (J4C1)
Pin
1
7.7
Signal Name
PWR_P5V
Description
S/PDIF Power
2
AUD_SPDIF_OUT
S/PDIF output
3
GND
Ground
Onboard Video Header
The adapter cable accessory (FXXSCVDCBL) is required to convert the internal onboard video
header to a 15-pin D-Sub
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Connector/Header Locations and Pin-outs
Table 102. Onboard Video Header Pin-out (J3B2)
Pin
7.8
Signal Name
Description
1
V_IO_R_CONN
Red (analog color signal R)
2
GND
Ground
3
V_IO_G_CONN
Green (analog color signal G)
4
GND
Ground
5
V_IO_B_CONN
Blue (analog color signal B)
6
GND
Ground
7
V_IO_VSYNC_CONN
VSYNC (vertical sync)
8
GND
Ground
9
V_IO_HSYNC_CONN
HSYNC (horizontal sync)
10
Key
Key
11
V_IO_DDCDAT
DDC_DATA
12
GND
Ground
13
V_IO_DDCCLK
DDC_Clock
14
P5V_VID_CONN
P5V VID
Fan Headers
The workstation board provides three SSI-compliant 4-pin and four SSI-compliant 6-pin fan
headers to use as CPU and I/O cooling fans. 3-pin fans are supported on all fan headers. 6-pin
fans are supported on headers J1K1, J1K2, J1K4, and J1K5. 4-pin fans are supported on
headers J1K1, J1K2, J1K4, J1K5, J7K1, J9A2, and J9A3. The pin configuration for each of the
4-pin and 6-pin fan headers is identical and defined in the following tables.
ƒ
Two 4-pin fan headers are designated as processor cooling fans:
ƒ
- CPU1 fan (J9A2)
- CPU2 fan (J7K1)
Four 6-pin fan headers are designated as hot-swap system fans:
ƒ
- System fan 1 (J1K1)
- System fan 2 (J1K4)
- System fan 3 (J1K2)
- System fan 4 (J1K5)
One 4-pin fan headers is designated as a rear system fan:
System fan 5 (J5B1)
-
Table 103. SSI 4-pin Fan Header Pin-out (J7K1, J9A2, J5B1)
Pin
1
Signal Name
Ground
Type
GND
Description
Ground is the power supply ground
2
12V
Power
Power supply 12 V
3
Fan Tach
In
FAN_TACH signal is connected to the BMC to monitor the fan speed
4
Fan PWM
Out
FAN_PWM signal to control fan speed
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Intel® Workstation System SC5650SCWS TPS
Table 104. SSI 6-pin Fan Header Pin-out (J1K1, J1K2, J1K4, J1K5)
1
Pin
Signal Name
Ground
Type
GND
Description
Ground is the power supply ground
2
12V
Power
Power supply 12 V
3
Fan Tach
In
FAN_TACH signal is connected to the BMC to monitor the fan speed
4
Fan PWM
Out
FAN_PWM signal to control fan speed
5
Fan Presence
In
Indicates the fan is present
6
Fan Fault LED
Out
Lights the fan fault LED
Note: Intel Corporation server and workstation boards support peripheral components and
contain a number of high-density VLSI and power delivery components that need adequate
airflow to cool. Intel’s own chassis are designed and tested to meet the intended thermal
requirements of these components when the fully integrated system is used together. It is the
responsibility of the system integrator that chooses not to use Intel® developed server building
blocks to consult vendor datasheets and operating parameters to determine the amount of
airflow required for their specific application and environmental conditions. Intel Corporation
cannot be held responsible if components fail or the workstation board does not operate
correctly when used outside any of their published operating or non-operating limits.
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8.
Jumper Blocks
Jumper Blocks
The workstation board has several 3-pin jumper blocks that you can use to configure, protect, or
recover specific features of the workstation board.
Pin 1 on each jumper block is identified by the following symbol on the silkscreen: ▼
Figure 55. Jumper Blocks
Table 105. Workstation Board Jumpers (J1E2, J1E4, J1E5, J1H1, J2C1, J2C2, J4B2)
Jumper Name
J1E2:
ME
Update
Force
J1E4: Password Clear
J1E5: BIOS Recovery
Pins
1-2
System Results
ME Firmware Force Update Mode – Disabled (Default)
2-3
ME Firmware Force Update Mode – Enabled
1-2
These pins should have a jumper in place for normal system operation. (Default)
2-3
If these pins are connected, the administrator and user passwords are cleared 5 to 10
seconds after powering on the system. These pins should not be connected for normal
operation.
1-2
These pins should be connected for normal system operation. (Default)
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Intel® Workstation System SC5650SCWS TPS
Jumper Name
Pins
2-3
J1H1: Force
Update
BMC
J2C1: CMOS Clear
J4B2: Serial Port A
Configuration
8.1
System Results
The main system BIOS will not boot with pins 2-3 connected. When connected, the system
will only boot from EFI-bootable recovery media with a recovery BIOS image present.
1-2
BMC Firmware Force Update Mode – Disabled (Default)
2-3
BMC Firmware Force Update Mode – Enabled
1-2
These pins should be connected for normal system operation. (Default)
2-3
If connected and AC power unplugged, the CMOS settings will clear in 5 seconds. The 2-3
pins should not be connected for normal system operation.
1-2
Rear RJ-45 Serial A port is configured for DSR to DTR. (Default)
2-3
Rear RJ-45 Serial A port is configured for DCD to DTR.
CMOS Clear and Password Reset Usage Procedure
The CMOS Clear (J2C1) and Password Reset (J1E4) recovery features are designed so the
needed operation is achieved with minimum system down time. The usage procedure for these
two features has changed from previous generation Intel® workstation boards. The following
procedure outlines the new usage model.
8.1.1
Clearing the CMOS
1. Power down the workstation and unplug the power cord.
2. Open the workstation chassis. For instructions, refer your workstation chassis
documentation.
3. Move jumper (J2C1) from the default operating position (covering pins 1 and 2) to the
reset / clear position (covering pins 2 and 3).
4. Wait five seconds.
5. Move the jumper back to default position (covering pins 1 and 2).
6. Close the workstation chassis and reconnect the AC power cord.
7. Power up the workstation.
The CMOS is now cleared and you can reset it by going into the BIOS setup.
8.1.2
Clearing the Password
1. Power down the workstation. Do not unplug the power cord.
2. Open the chassis. For instructions, refer your workstation chassis documentation.
3. Move jumper (J1E4) from the default operating position (covering pins 1 and 2) to the
password clear position (covering pins 2 and 3).
4. Close the workstation chassis.
5. Power up the workstation and then press <F2> to enter the BIOS menu to check if the
password is cleared.
6. Power down the workstation.
7. Open the chassis and move the jumper (J1E4) back to its default position (covering pins
1 and 2).
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Jumper Blocks
8. Close the workstation chassis.
9. Power up the workstation.
The password is now cleared and you can reset it by going into the BIOS setup.
8.2
Force BMC Update Procedure
When performing a standard BMC (Baseboard Management Controller) firmware update
procedure, the update utility places the BMC into an update mode, allowing the firmware to load
safely onto the flash device. In the unlikely event the BMC firmware update process fails due to
the BMC not being in the proper update state, the workstation board provides a Force BMC
Update jumper (J1H1) which forces the BMC into the proper update state. In the event the
standard BMC firmware update process fails, you must complete the following procedure.
1. Power down and remove the AC power cord.
2. Open the workstation chassis. Refer your workstation chassis documentation for
instructions.
3. Move the jumper (J1H1) from the default operating position (covering pins 1 and 2) to
the enabled position (covering pins 2 and 3).
4. Close the workstation chassis.
5. Reconnect the AC cord and power up the workstation.
6. Perform the BMC firmware update procedure as documented in the README.TXT file
included in the given BMC firmware update package. After successful completion of the
firmware update process, the firmware update utility may generate an error stating the
BMC is still in update mode.
7. Power down and remove the AC power cord.
8. Open the workstation chassis.
9. Move jumper (J1H1) from the enabled position (covering pins 2 and 3) to the disabled
position (covering pins 1 and 2).
10. Close the workstation chassis.
11. Reconnect the AC power cord and power up the workstation.
Note: Normal BMC functionality is disabled when the Force BMC Update jumper is set to the
enabled position. You should never run the workstation with the Force BMC Update jumper set
in this position. You should only use this jumper setting when the standard firmware update
process fails. This jumper should remain in the default / disabled position when the workstation
is running normally.
8.3
BIOS Recovery
1. Power down the system and remove the AC power cord.
2. Open the workstation chassis. Refer your workstation chassis documentation for
instructions.
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3. Move the BIOS recovery jumper (J1E5) from the default operating position (covering
pins 1 and 2) to the enabled position (covering pins 2 and 3).
4. Close the workstation chassis.
5. Reconnect the AC power cord and power up the workstation.
6. Perform the BIOS Recovery procedure as documented in the BIOS Release Notes.
7. After successful completion of the BIOS recovery, the “BIOS has been updated
successfully” message displays.
8. Power down the system and remove the AC power cord.
9. Open the workstation chassis.
10. Move the BIOS recovery jumper (J1E5) from the enabled position (covering pins 2 and 3)
to the disabled position (covering pins 1 and 2).
11. Close the workstation chassis.
12. Reconnect the AC power cord and power up the workstation.
Warning: DO NOT interrupt the BIOS POST during the first boot after BIOS recovery.
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9.
Intel® Light Guided Diagnostics
Intel® Light Guided Diagnostics
The workstation board has several onboard diagnostic LEDs to assist in troubleshooting boardlevel issues. This section provides a description of the location and function of each LED on the
workstation board.
9.1
5-V Stand-by LED
Several workstation management features of this workstation board require a 5-V stand-by
voltage is supplied from the power supply. The features and components that require this
voltage must be present when the system is “Off” including the Integrated BMC, onboard NICs,
and optional Intel® RMM3 connector with Intel® RMM3 installed.
The 5-V Stand-by LED is located near the SAS module slot in the lower-left corner of the
workstation board and is labeled “5VSB_LED”. It is illuminated when AC power is applied to the
platform and 5-V stand-by voltage is supplied to the workstation board by the power supply.
Figure 56. 5V Stand-by Status LED Location
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9.2
Intel® Workstation System SC5650SCWS TPS
Fan Fault LEDs
Fan fault LEDs are present for the two CPU fans and the rear system fan 5. The fan fault LED
illuminates when the corresponding fan has fault
Figure 57. Fan Fault LED Locations
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9.3
Intel® Light Guided Diagnostics
System Status LED and System ID LED
The workstation board provides LEDs for both system ID and system status. These LEDs are
located in the rear I/O area of the workstation board as shown in the following figure.
A.
System Status LED
B.
System ID LED
Figure 58. System Status LED and ID LED Location
You can illuminate the blue System ID LED using either of the following two mechanisms:
ƒ
By pressing the System ID Button on the system front control panel, the ID LED displays
a solid blue color until the button is pressed again.
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By issuing the appropriate hex IPMI “Chassis Identify” value, the ID LED either blinks
blue for 15 seconds and turns off or blinks indefinitely until the appropriate hex IPMI
Chassis Identify value is issued to turn it off.
The bi-color (green / amber) System Status LED operates as follows:
Table 106. System Status LED
Color
State
Criticality
Description
Green
Solid on
System OK
System booted and ready.
Green
Blink
Degraded
System degraded
Amber
Amber
Blink
Solid on
Non-critical
Critical,
recoverable
–
Non-critical temperature threshold asserted
–
Non-critical voltage threshold asserted
–
Non-critical fan threshold asserted
–
Fan redundancy lost, sufficient system cooling maintained. This
does not apply to non-redundant systems.
–
Power supply predictive failure
–
Power supply redundancy lost. This does not apply to nonredundant systems.
–
Correctable errors over a threshold of 10 and migrating to a
mirrored DIMM (memory mirroring). This indicates the user no
longer has spare DIMMs indicating a redundancy lost condition.
The corresponding DIMM LED should light up.
Non-fatal alarm – system is likely to fail:
non-
–
Critical temperature threshold asserted
–
CATERR asserted
–
Critical voltage threshold asserted
–
VRD hot asserted
–
SMI Timeout asserted
Fatal alarm – system has failed or shut down
–
CPU Missing
–
Thermal Trip asserted
–
Non-recoverable temperature threshold asserted
–
Non-recoverable voltage threshold asserted
–
Power fault / Power Control Failure
–
Fan redundancy lost, insufficient system cooling. This does not
apply to non-redundant systems.
–
Power supply redundancy lost insufficient system power. This
does not apply to non-redundant systems.
Note: This state will also happen when AC power is first applied to the
system. This indicates the BMC is booting.
Off
152
N/A
Not ready
–
AC power off, if no degraded, non-critical, critical, or nonrecoverable conditions exist.
–
System is powered down or S5 states, if no degraded, non-critical,
critical, or non-recoverable conditions exist.
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Intel® Light Guided Diagnostics
* When the workstation is powered down (transitions to the DC-off state or S5), the BMC is still on standby power and
retains the sensor and front panel status LED state established before the power-down event. If the system status is
normal when the system is powered down (the LED is in a solid green state), the system status LED will be off.
9.4
DIMM Fault LEDs
The workstation board provides memory fault LED for each DIMM socket. The following figure
shows the location of these LEDs. The DIMM fault LED illuminates when the corresponding
DIMM slot has memory installed and a memory error occurs.
Figure 59. DIMM Fault LEDs Location
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9.5
Intel® Workstation System SC5650SCWS TPS
POST Code Diagnostic LEDs
Eight amber POST code diagnostic LEDs are located on the back edge of the workstation board
in the rear I/O area of the workstation board by the serial A connector.
During the system boot process, the BIOS executes a number of platform configuration
processes, each of which is assigned a specific hex POST code number. As each configuration
routine is started, the BIOS displays the given POST code to the POST code diagnostic LEDs
on the back edge of the workstation board. To assist in troubleshooting a system hang during
the POST process, you can use the diagnostic LEDs to identify the last POST process executed.
For a complete description of how these LEDs are read and a list of all supported POST codes,
refer to Appendix E.
A. Diagnostic LED #7 (MSB LED)
E. Diagnostic LED #3
B. Diagnostic LED #6
F. Diagnostic LED #2
C. Diagnostic LED #5
G. Diagnostic LED #1
D. Diagnostic LED #4
H. Diagnostic LED #0 (LSB LED)
A. Diagnostic LED #7 (MSB LED)
E. Diagnostic LED #3
B. Diagnostic LED #6
F. Diagnostic LED #2
C. Diagnostic LED #5
G. Diagnostic LED #1
D. Diagnostic LED #4
H. Diagnostic LED #0 (LSB LED)
Figure 60. POST Code Diagnostic LED Location
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Design and Environmental Specifications
10. Design and Environmental Specifications
10.1 Intel® Workstation System SC5650SCWS Design Specifications
Operation of the Intel® Workstation System SC5650SCWS at conditions beyond those listed in
the following table may cause permanent damage to the system. Exposure to absolute
maximum rating conditions for extended periods may affect system reliability.
Table 107. Workstation System Design Specifications
Operating Temperature
0º C to 55º C 1 (32º F to 131º F)
Non-Operating Temperature
-40º C to 70º C (-40º F to 158º F)
DC Voltage
± 5% of all nominal voltages
Shock (Unpackaged)
Trapezoidal, 50 G, 170 inches / sec
Shock (Packaged)
< 20 pounds
36 inches
20 to < 40 pounds
30 inches
40 to < 80 pounds
24 inches
80 to < 100 pounds
18 inches
100 to < 120 pounds
12 inches
120 pounds
9 inches
Vibration (Unpackaged)
5 Hz to 500 Hz 3.13 g RMS random
Note:
1
Chassis design must provide proper airflow to avoid exceeding the processor maximum case temperature.
Disclaimer Note: Intel Corporation server and workstation boards contain a number of highdensity VLSI and power delivery components that need adequate airflow to cool. Intel ensures
through its own chassis development and testing that when Intel® server/workstation building
blocks are used together, the fully integrated system will meet the intended thermal
requirements of these components. It is the responsibility of the system integrator who chooses
not to use Intel® developed server/workstation building blocks to consult vendor datasheets and
operating parameters to determine the amount of airflow required for their specific application
and environmental conditions. Intel Corporation cannot be held responsible, if components fail
or the server or workstation board does not operate correctly when used outside any of its
published operating or non-operating limits.
10.2 MTBF
The following is the calculated Mean Time Between Failures (MTBF) 30°C (ambient air). These
values are derived using a historical failure rate and multiplied by factors for application,
electrical and/or thermal stress and for device maturity. You should MTBF estimates as
“reference numbers” only.
•
Calculation Model: Telcordia Issue 1, method I case 3
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•
•
Operating Temperature: Workstation in 35 °C ambient air
Operating Environment: Ground Benign, Controlled
•
•
Duty Cycle: 100%
Quality Level: II
Table 108. MTBF Estimate
MTBF (hours)
Intel® Workstation System SC5650SCWS
10.2.1
39,200
Intel® Workstation Board S5520SC
114,000
1000-W Power Supply Unit
154,000
System Fans
100,000
Front Panel
7,000,000
Intrusion switch
25,000,000
Processor Power Support
The workstation System supports the Thermal Design Power (TDP) guideline for Intel® Xeon®
processors. The Flexible Motherboard Guidelines (FMB) were also followed to determine the
suggested thermal and current design values for anticipating future processor needs. The
following table provides maximum values for Icc, TDP power and TCASE for the Intel® Xeon®
Processor 5500 Series.
Table 109. Intel® Xeon® Processor Dual Processor TDP Guidelines
TDP Power
130 W
156
Max Tcase
67.0º C
Icc MAX
150 A
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Regulatory and Certification Information
11. Regulatory and Certification Information
To help ensure EMC compliance with your local regional rules and regulations, before computer
integration, make sure that the chassis, power supply, and other modules have passed EMC
testing using a workstation board with a microprocessor from the same family (or higher) and
operating at the same (or higher) speed as the microprocessor used on this workstation board.
The final configuration of your end system product may require additional EMC compliance
testing. For more information, please contact your local Intel Representative.
This is an FCC Class A device. Integration of it into a Class B chassis does not result in a Class
B device.
11.1 Product Regulatory Compliance
Intended Application – This product was evaluated as Information Technology Equipment (ITE),
which may be installed in offices, schools, computer rooms, and similar commercial type
locations. The suitability of this product for other product categories and environments (such as:
medical, industrial, telecommunications, NEBS, residential, alarm systems, test equipment, etc.),
other than an ITE application, may require further evaluation.
11.1.1
Product Safety Compliance
®
The Intel Workstation System SC5650SCWS complies with the following safety
requirements:
•
•
•
•
•
•
•
•
UL60950 - CSA 60950 (USA / Canada)
EN60950 (Europe)
IEC60950 (International)
CB Certificate & Report, IEC60950 (report to include all country national deviations) GS
License (Germany)
GOST R 50377-92 - License (Russia) – Listed on System License
Belarus License (Belarus) – Listed on System License
CE - Low Voltage Directive 73/23/EEE (Europe)
IRAM Certification (Argentina)
11.1.2
Product EMC Compliance – Class A Compliance
®
The Intel Workstation System SC5650SCWS has been tested and verified to comply with the
following electromagnetic compatibility (EMC) regulations when installed a compatible Intel®
host system. For information on compatible host system(s) refer to
http://support.intel.com/support/motherboards/server/S5520SC/ or contact your local Intel
representative.
• FCC /ICES-003 - Emissions (USA/Canada) Verification
• CISPR 22 – Emissions (International)
• EN55022 - Emissions (Europe)
• EN55024 - Immunity (Europe)
• CE – EMC Directive 89/336/EEC (Europe)
• AS/NZS 3548 Emissions (Australia / New Zealand)
• VCCI Emissions (Japan)
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•
•
•
•
•
11.1.3
•
•
•
•
•
•
•
•
•
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Intel® Workstation System SC5650SCWS TPS
BSMI CNS13438 Emissions (Taiwan)
RRL Notice No. 1997-41 (EMC) & 1997-42 (EMI) (Korea)
GOST R 29216-91 Emissions (Russia) – Listed on System License
GOST R 50628-95 Immunity (Russia) – Listed on System License
Belarus License (Belarus) – Listed on System License
Certifications / Registrations / Declarations
UL Certification or NRTL (US/Canada)
CB Certifications (International)
CE Declaration of Conformity (CENELEC Europe)
FCC/ICES-003 Class A Attestation (USA/Canada)
C-Tick Declaration of Conformity (Australia)
MED Declaration of Conformity (New Zealand)
BSMI Certification (Taiwan)
RRL KCC Certification (Korea)
Ecology Declaration (International)
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Regulatory and Certification Information
11.2 Product Regulatory Compliance Markings
Regulatory Compliance
Country
UL Mark
USA/Canada
CE Mark
Europe
EMC Marking (Class A)
Canada
Marking
CANADA ICES-003 CLASS A
CANADA NMB-003 CLASSE A
BSMI Marking (Class A)
Taiwan
C-tick Marking
Australia / New Zealand
RRL KCC Mark
Korea
EFUP Mark
China
Country of Origin
Exporting Requirements
Made in xxxxx
Model Designation
Regulatory
Identification
Examples (Workstation Board S5520SC) for boxed type
boards; or Board PB number for non-boxed boards
(typically high-end boards)
11.3 Electromagnetic Compatibility Notices
FCC (USA)
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two
conditions: (1) this device may not cause harmful interference, and (2) this device must accept
any interference received, including interference that may cause undesired operation.
For questions related to the EMC performance of this product, contact:
Intel Corporation
5200 N.E. Elam Young Parkway
Hillsboro, OR 97124-6497
1-800-628-8686
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Intel® Workstation System SC5650SCWS TPS
This equipment has been tested and found to comply with the limits for a Class A digital device,
pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable
protection against harmful interference in a residential installation. This equipment generates,
uses, and can radiate radio frequency energy and, if not installed and used in accordance with
the instructions, may cause harmful interference to radio communications. However, there is no
guarantee that interference will not occur in a particular installation. If this equipment does
cause harmful interference to radio or television reception, which can be determined by turning
the equipment off and on, the user is encouraged to try to correct the interference by one or
more of the following measures:
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and the receiver.
Connect the equipment to an outlet on a circuit other than the one to which the
receiver is connected.
• Consult the dealer or an experienced radio/TV technician for help.
Any changes or modifications not expressly approved by the grantee of this device could void
the user’s authority to operate the equipment. The customer is responsible for ensuring
compliance of the modified product.
Only peripherals (computer input/output devices, terminals, printers, etc.) that comply with FCC
Class A or B limits may be attached to this computer product. Operation with noncompliant
peripherals is likely to result in interference to radio and TV reception.
All cables used to connect to peripherals must be shielded and grounded. Operation with cables,
connected to peripherals that are not shielded and grounded may result in interference to radio
and TV reception.
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Regulatory and Certification Information
ICES-003 (Canada)
Cet appareil numérique respecte les limites bruits radioélectriques applicables aux
appareils numériques de Classe A prescrites dans lanorme sur le matériel brouilleur:
“Apparelis Numériques”, NMB-003 édictee par le Ministre Canadian des
Communications.
English translation of the notice above:
This digital apparatus does not exceed the Class A limits for radio noise emissions from digital
apparatus set out in the interference-causing equipment standard entitled: “Digital Apparatus,”
ICES-003 of the Canadian Department of Communications.
Europe (CE Declaration of Conformity)
This product has been tested in accordance too, and complies with the Low Voltage Directive
(73/23/EEC) and EMC Directive (89/336/EEC). The product has been marked with the CE Mark
to illustrate its compliance.
VCCI (Japan)
English translation of the notice above:
This is a Class B product based on the standard of the Voluntary Control Council for
Interference (VCCI) from Information Technology Equipment. If this is used near a radio or
television receiver in a domestic environment, it may cause radio interference. Install and use
the equipment according to the instruction manual.
BSMI (Taiwan)
The BSMI Certification Marking and EMC warning is located on the outside rear area of
the product.
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Intel® Workstation System SC5650SCWS TPS
RRL KCC (Korea)
11.4 Product Ecology Change (EU RoHS)
Intel has a system in place to restrict the use of banned substances in accordance with the
European Directive 2002/95/EC. Compliance is based on declaration that materials banned in
the RoHS Directive are either (1) below all applicable threshold limits or (2) an approved /
pending RoHS exemption applies.
RoHS implementation details are not fully defined and may change.
Threshold limits and banned substances are noted below:
•
Quantity limit of 0.1% by mass (1000PPM) for:
– Lead
– Mercury
– Hexavalent Chromium
– Polybrominated Biphenyls Diphenyl Ethers (PBDE)
• Quantity limit of 0.01% by mass (100 PPM) for:
– Cadmium
11.5 Product Ecology Change (CRoHS)
CRoHS (China RoHS, or Ministry of Information Industry Order #39, “Management
Methods for Controlling Pollution by Electronic Information Products.”):
•
•
•
•
China bans the same substances and limits as noted for EU RoHS; however require
product marking and controlled substance information Environmental Friendly Usage
Period (EFUP) Marking Is defined in number of years in which controlled listed
substances will not leak or chemically deteriorate while in the product. Intel
understands the end-seller (entity placing product into market place) is responsible for
providing EFUP marking.
Intel “retail” products are provided with EFUP marking
For “Business to Business” products, Intel intends to place EFUP marking on product
for customer convenience
EFUP for Intel server products has been determined as 20 years.
Below is an example of EFUP mark applied to Intel server products.
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CRoHS Substance Tables:
China CRoHS requires products to be provided with controlled substance information. Intel
understands the end-seller (entity placing product into market place) is responsible for providing
the controlled substance information. Controlled substance information is required to be in
Simplified Chinese. Substance table for this board product is as follows:
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Regulatory and Certification Information
11.6 China Packaging Recycle Marks (or GB18455-2001)
Intel EPSD has the following ecological compliances:
Cardboard and fiberboard packaging will be marked as recyclable in China.
China Packaging Recycling Marks is required on retail packaging to be marked as recyclable
using China’s recycling logo. Due to regional variances in mark acceptances, all three marks
accepted worldwide will be implemented on Intel’s cardboard and fiberboard. Examples of
marks are shown below.
11.7 CA Perchlorate Warning
CA Lithium Perchlorate Warning (California Code of Regulations, Title 22, Division 4.5,
Chapter 33: Best Management Practices for Perchlorate Materials):
The State of California requires a warning to be included for products containing a device using
Lithium Perchlorate.
Intel understands CA Lithium Perchlorate require a printed warning to be included with all
products containing a Lithium battery, either as an insert, in existing product literature, or as part
of the shipping memo wording.
Wording is as follows:
Perchlorate Material - special handling may apply. See
www.dtsc.ca.gov/hazardouswaste/perchlorate.
This notice is required by California Code of Regulations, Title 22, Division 4.5, Chapter 33:
Best Management Practices for Perchlorate Materials. This product/part includes a battery that
contains Perchlorate material.
11.8 End-of-Life / Product Recycling
Product recycling and end-of-life take-back systems and requirements vary by country.
Contact the retailer or distributor of this product for information about product recycling and / or
take-back.
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Appendix A: Integration and Usage Tips
Intel® Workstation System SC5650SCWS TPS
Appendix A: Integration and Usage Tips
ƒ
Prior to adding or removing components or peripherals from the workstation board, you
must remove the AC power cord. With AC power plugged into the workstation board, 5-V
standby is still present even though the workstation board is powered off.
ƒ
This workstation board supports the Intel® Xeon® Processor 5500 Series only. This
workstation board does not support previous generation Intel® Xeon® processors.
ƒ
You must install processors in order. CPU 1 socket is located near the back edge of the
workstation board and must be populated to operate the board and enable CPU 2 socket.
ƒ
On the back edge of the workstation board, there are eight diagnostic LEDs that display
a sequence of amber POST codes during the boot process. If the workstation board
hangs during POST, the LEDs display the last POST event run before the hang.
ƒ
Only Registered DDR3 DIMMs (RDIMMs) and Unbuffered DDR3 DIMMs (UDIMMs) are
supported on this workstation board. Mixing of RDIMMs and UDIMMs is not supported.
ƒ
Must always start populating DDR3 DIMMs in the first slot on each memory channel
(Memory slot A1, B1, C1, D1, E1, or F1)
ƒ
Must populate Quad-Rank RDIMM starting with the first slot (Memory slot A1, B1, C1,
D1, E1, or F1) on each memory channel.
ƒ
For the best performance, you should balance the number of DDR3 DIMMs installed
across both processor sockets and memory channels. For example: with two processors
installed, a 6-DIMM configuration with identical DIMMs in slot A1, B1, C1, D1, E1, and
F1 performs better than a 6-DIMM configuration with identical DIMMs at A1, A2, B1, B2,
C1, and C2.
ƒ
The Intel® RMM3 connector is not compatible with the Intel® Remote Management
Module (Product Code AXXRMM) or the Intel® Remote Management Module 2 (Product
Code AXXRMM2).
ƒ
Normal BMC functionality is disabled with the Force BMC Update jumper (J1H1) set to
the “enabled” position (pins 2-3). You should never run the workstation with the Force
BMC Update jumper set in this position and should only use the jumper in this position
when the standard BMC firmware update process fails. This jumper must remain in the
default (disabled) position (pins 1-2) when the workstation is running normally.
This workstation board no longer supports the Rolling BIOS (two BIOS banks). It
implements the BIOS Recovery mechanism instead.
When performing a normal BIOS update procedure, you must set the BIOS Recovery
jumper (J1E5) to its default position (pins 1-2).
Keep PCI Express* Slot 3 empty for optimal thermal airflow when a graphics card is
installed into PCI Express* Slot 4.
Locate the device that generates System Event Log (SEL) PCI device event: the SEL
PCI device event may not specify which PCI device in the system that generates the
event entry, users can follow below tips to locate the PCI device:
à Step1: Identify the PCI device location number: the SEL event entry in Hex code
(refer the SEL viewer utility help text instruction for read of Hex code) provides the
PCI device bus number, device number, and function number with last two bytes:
ED2 and ED3. The byte of ED2 provides the PCI device bus number; the higher four
bits of ED3 byte provides the device number, and the lower four bits of ED3 byte
provides the function number.
ƒ
ƒ
ƒ
ƒ
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à
à
Appendix A: Integration and Usage Tips
Step 2: Decide the PCI device with location number (Bus number, Device number,
and Function number) using PCI map dump from the system generating the PCI
device SEL event, There are multiple means to dump the PCI map. For example,
read the location number from the device general property page in device manager
under Microsoft Windows* Operating Systems, or type ‘PCI’ and execute under the
server board EFI shell
Example of deciding the PCI device that generates SEL event entry: 1) Provided a
PCI device SEL event entry in Hex code reads the ED2 as 01 and ED3 as 00, that is,
the PCI device has bus number=1, device number=0, and function number=0; 2) The
PCI dump from this system indicates the device with bus number=1, device
number=0, and function number=0 as “Network Controller - Ethernet controller” and
there is no add-in NIC inserted, thus the PCI device generate the SEL event entry is
onboard NIC controller.
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Appendix B: Processor Active Heat Sink Installation
Intel® Workstation System SC5650SCWS TPS
Appendix B: Processor Active Heat Sink Installation
ƒ
Active processor heat sink(s) is required
Table 110. Compatible Heatsink Matrix
Intel® Thermal Solution STS100C (w/
fan, Active mode)
Maximum CPU Power Support in
Intel®
Workstation
System
SC5650SCWS
Intel® Thermal Solution Product Code
Intel® Thermal Solution
STS100A (Active)
130 W (in Intel® Server Chassis
SC5650WS Chassis)
95 W (in Intel® Server Chassis
SC5650WS and Intel® Server Chassis
SC5600Base Chassis)
80 W
BXSTS100C
BXSTS100A
Note: You must install an active processor heatsink with the airflow direction as shown in the
following figure when installing in the Intel® Workstation System SC5650SCWS.
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Appendix B: Processor Active Heat Sink Installation
Figure 61. Active Processor Heatsink Installation
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Appendix C: BMC Sensor Tables
Intel® Workstation System SC5650SCWS TPS
Appendix C: BMC Sensor Tables
This appendix lists the sensor identification numbers and information about the sensor type,
name, supported thresholds, assertion and de-assertion information, and a brief description of
the sensor purpose. For sensor and event/reading-type table information, refer to the Intelligent
Platform Management Interface Specification, Version 2.0.
ƒ
Sensor Type
The Sensor Type references the values in the sensor type codes table in the Intelligent
Platform Management Interface Specification, Version 2.0 for sensor and event /
reading-type table information.
ƒ
Event / Reading Type
The event / reading type references values from the event / reading type code ranges
and the generic event / reading type code tables in the Intelligent Platform Management
Interface Specification Second Generation v2.0. Digital sensors are a specific type of
discrete sensors that only have two states.
ƒ
Event Offset/Triggers
Event Thresholds are event-generating thresholds for threshold type sensors.
[u,l][nr,c,nc] upper non-recoverable, upper critical, upper non-critical, lower nonrecoverable, lower critical, lower non-critical
uc, lc
upper critical, lower critical
Event triggers are supported, event-generating offsets for discrete type sensors. You
can find the offsets in the generic event / reading type code or sensor type code tables
in the Intelligent Platform Management Interface Specification Second Generation v2.0,
depending on whether the sensor event / reading type is generic or a sensor specific
response.
ƒ
Assertion / De-assertion Enables
Assertion and de-assertion indicators reveal the type of events the sensor generates:
ƒ
- As: Assertions
- De: De-assertion
Readable Value / Offsets
ƒ
Readable Values indicate the type of value returned for threshold and other nondiscrete type sensors.
- Readable Offsets indicate the offsets for discrete sensors that are readable with the
Get Sensor Reading command. Unless otherwise indicated, all event triggers are
readable; Readable Offsets consist of the reading type offsets that do not generate
events.
Event Data
-
Event data is the data included in an event message generated by the sensor. For
threshold-based sensors, the following abbreviations are used:
170
R: Reading value
T: Threshold value
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ƒ
Appendix C: BMC Sensor Tables
Rearm Sensors
The rearm is a request for the event status of a sensor to be rechecked and updated
upon a transition between good and bad states. You can rearm the sensors manually or
automatically. This column indicates the type supported by the sensor. These
abbreviations are used in the comment column to describe a sensor:
ƒ
- A: Auto-rearm
- M: Manual rearm
- I: Rearm by init agent
Default Hysteresis
The hysteresis setting applies to all thresholds of the sensor. This column provides the
count of hysteresis for the sensor, which is 1 or 2 (positive or negative hysteresis).
ƒ
Criticality
Criticality is a classification of the severity and nature of the condition. It also controls the
behavior of the Control Panel Status LED.
ƒ
Standby
Some sensors operate on standby power. You can access these sensors and / or
generate events when the main (system) power is off but AC power is present.
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Appendix C: BMC Sensor Tables
Intel® Workstation System SC5650SCWS TPS
Table 111. Integrated BMC Core Sensors
Full Sensor Name
(Sensor name in SDR)
Sensor #
Platform
Applicability
Sensor Type
Event Offset
Event /
Reading Type Triggers
00 - Power down
Power Unit Status
(Pwr Unit Status)
01h
All
Power Unit
09h
Sensor
Specific
6Fh
04 - A/C lost
05 - Soft power
control failure
06 - Power unit
failure
00 - Fully
Redundant
Power Unit Redundancy1
(Pwr Unit Redund)
02h
Chassisspecific
Power Unit
Generic
09h
0Bh
Fatal
Readable
Value /
Offsets
Event
Rearm
Data
Standby
As and
De
–
Trig Offset
A
X
As and
De
–
Trig Offset
A
X
OK
Degraded
02 - Redundancy
degraded
Degraded
03 - Nonredundant:
sufficient
resources.
Transition from
full redundant
state.
Degraded
04 – Nonredundant:
sufficient
resources.
Transition from
insufficient state.
Degraded
Intel order number: E81822-002
Assert /
De-assert
OK
01 - Redundancy
lost
05 - Nonredundant:
insufficient
resources
172
Contrib. To
System
Status
Fatal
Revision 1.2
Intel® Workstation System SC5650SCWS TPS
Full Sensor Name
(Sensor name in SDR)
Sensor #
Platform
Applicability
Appendix C: BMC Sensor Tables
Sensor Type
Event /
Event Offset
Reading Type Triggers
Contrib. To
System
Status
06 – Redundant:
degraded from
fully redundant
state.
Degraded
07 – Redundant:
Transition from
non-redundant
state.
Degraded
Assert /
De-assert
Readable
Value /
Offsets
Event
Data
Rearm
Standby
00 - Timer
expired, status
only
IPMI Watchdog
(IPMI Watchdog)
03h
All
Watchdog 2
23h
Sensor
Specific
6Fh
01 - Hard reset
02 - Power down
OK
As
–
Trig Offset
A
X
As and
De
–
Trig Offset
A
X
03 - Power cycle
08 - Timer
interrupt
Physical Security
(Physical Scrty)
FP Interrupt
(FP NMI Diag Int)
SMI Timeout
(SMI Timeout)
System Event Log
(System Event Log)
Revision 1.2
04h
05h
06h
07h
Chassis
Intrusion is
chassisspecific
Chassis specific
All
All
Physical
Security
Sensor
Specific
05h
6Fh
Critical
Interrupt
Sensor
Specific
13h
6Fh
SMI Timeout
Digital
Discrete
F3h
03h
Event Logging
Disabled
Sensor
Specific
10h
6Fh
00 - Chassis
intrusion
OK
04 - LAN leash
lost
OK
00 - Front panel
NMI / diagnostic
interrupt
OK
As
–
Trig Offset
A
–
01 – State
asserted
Fatal
As and
De
–
Trig Offset
A
–
02 - Log area
reset / cleared
OK
As
–
Trig Offset
A
X
Intel order number: E81822-002
173
Appendix C: BMC Sensor Tables
Full Sensor Name
(Sensor name in SDR)
System Event
(System Event)
BB +1.1V IOH
(BB +1.1V IOH)
BB +1.1V P1 Vccp
(BB +1.1V P1 Vccp)
BB +1.1V P2 Vccp
(BB +1.1V P2 Vccp)
BB +1.5V P1 DDR3
(BB +1.5V P1 DDR3)
BB +1.5V P2 DDR3
(BB +1.5V P2 DDR3)
BB +1.8V AUX
(BB +1.8V AUX)
BB +3.3V
(BB +3.3V)
BB +3.3V STBY
(BB +3.3V STBY)
174
Sensor #
08h
10h
11h
12h
13h
14h
15h
16h
17h
Intel® Workstation System SC5650SCWS TPS
Platform
Applicability
All
All
All
All
All
All
All
All
All
Sensor Type
System Event
12h
Event /
Event Offset
Reading Type Triggers
Sensor
Specific
Contrib. To
System
Status
04 – PEF action
OK
[u,l] [c,nc]
nc =
Degraded
Assert /
De-assert
Readable
Value /
Offsets
Event
Rearm
Data
Standby
As
-
Trig Offset
A,I
X
As and
De
Analog
R, T
A
–
As and
De
Analog
R, T
A
–
As and
De
Analog
R, T
A
–
As and
De
Analog
R, T
A
–
As and
De
Analog
R, T
A
–
As and
De
Analog
R, T
A
X
As and
De
Analog
R, T
A
–
As and
De
Analog
R, T
A
X
6Fh
Voltage
02h
Threshold
01h
Voltage
02h
Threshold
01h
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Voltage
02h
Threshold
01h
c = Non-fatal
[u,l] [c,nc]
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
[u,l] [c,nc]
Intel order number: E81822-002
nc =
Degraded
c = Non-fatal
Revision 1.2
Intel® Workstation System SC5650SCWS TPS
Full Sensor Name
(Sensor name in SDR)
BB +3.3V Vbat
(BB +3.3V Vbat)
BB +5.0V
(BB +5.0V)
BB +5.0V STBY
(BB +5.0V STBY)
BB +12.0V
(BB +12.0V)
BB -12.0V
(BB -12.0V)
Baseboard Temperature
(Baseboard Temp)
Front Panel Temperature
(Front Panel Temp)
IOH Thermal Margin
(IOH Therm Margin)
Processor 1 Memory
Thermal Margin
(Mem P1 Thrm Mrgn)
Revision 1.2
Sensor #
18h
19h
1Ah
1Bh
1Ch
20h
21h
Platform
Applicability
All
All
All
All
All
All
All
22h
All
23h
All
Appendix C: BMC Sensor Tables
Sensor Type
Event /
Event Offset
Reading Type Triggers
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Voltage
02h
Threshold
01h
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Temperature
Threshold
01h
01h
Temperature
Threshold
01h
01h
Temperature
Threshold
01h
01h
Temperature
Threshold
01h
01h
Contrib. To
System
Status
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
[u,l] [c,nc]
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
[u,l] [c,nc]
nc =
Degraded
c = Non-fatal
[u,l] [c,nc]
nc =
Degraded
c = Non-fatal
Assert /
De-assert
Readable
Value /
Offsets
Event
Rearm
Data
Standby
As and
De
Analog
R, T
A
–
As and
De
Analog
R, T
A
–
As and
De
Analog
R, T
A
X
As and
De
Analog
R, T
A
–
As and
De
Analog
R, T
A
–
As and
De
Analog
R, T
A
X
As and
De
Analog
R, T
A
X
–
–
–
Analog
–
–
–
–
–
–
Analog
–
–
–
Intel order number: E81822-002
175
Appendix C: BMC Sensor Tables
Full Sensor Name
(Sensor name in SDR)
Processor 2 Memory
Thermal Margin
Sensor #
(Fan x Present)
Fan Redundancy 1
(Fan Redundancy)
176
Sensor Type
Event /
Event Offset
Reading Type Triggers
Dual
processor
only
Temperature
Threshold
01h
01h
30h–39h
Chassisspecific
Fan
Threshold
04h
01h
40h–45h
Chassisspecific
Fan
04h
Generic
08h
Fan Tachometer Sensors
Fan Present Sensors
Platform
Applicability
24h
(Mem P2 Thrm Mrgn)
(Chassis specific
sensor names)
Intel® Workstation System SC5650SCWS TPS
46h
Chassisspecific
Fan
Generic
04h
0Bh
–
[l] [c,nc]
Contrib. To
System
Status
–
nc =
Degraded
c = Nonfatal2
01 - Device
inserted
OK
00 - Fully
redundant
OK
01 – Redundancy
lost
Degraded
02 - Redundancy
degraded
Degraded
03 - Nonredundant:
Sufficient
resources.
Transition from
redundant
Degraded
04 - Nonredundant:
Sufficient
resources.
Transition from
insufficient.
Degraded
Intel order number: E81822-002
Assert /
De-assert
Readable
Value /
Offsets
Event
Rearm
Data
Standby
–
Analog
–
–
As and
De
Analog
R, T
M
As and
De
-
Triggered
Offset
Auto
–
As and
De
–
Trig Offset
A
–
Revision 1.2
–
–
Intel® Workstation System SC5650SCWS TPS
Full Sensor Name
(Sensor name in SDR)
Power Supply 1 Status
(PS/1 Status)
Power Supply 2 Status
(PS/2 Status)
Revision 1.2
Sensor #
50h
51h
Platform
Applicability
Chassisspecific
Chassisspecific
Appendix C: BMC Sensor Tables
Sensor Type
Power Supply
08h
Power Supply
08h
Event /
Event Offset
Reading Type Triggers
Contrib. To
System
Status
05 - Nonredundant:
insufficient
resources.
Non-fatal
06 – NonRedundant:
degraded from
fully redundant.
Degraded
07 - Redundant
degraded from
non-redundant
Degraded
00 - Presence
OK
01 - Failure
Degraded
Sensor
Specific
02 – Predictive
Failure
Degraded
6Fh
03 - A/C lost
Degraded
06 –
Configuration
error
OK
00 - Presence
OK
01 - Failure
Degraded
Sensor
Specific
02 – Predictive
Failure
Degraded
6Fh
03 - A/C lost
Degraded
06 –
Configuration
error
OK
Intel order number: E81822-002
Assert /
De-assert
Readable
Value /
Offsets
Event
Data
Rearm
Standby
As and
De
–
Trig Offset
A
X
As and
De
–
Trig Offset
A
X
177
Appendix C: BMC Sensor Tables
Full Sensor Name
(Sensor name in SDR)
Power Supply 1
AC Power Input
Sensor #
52h
(PS/1 Power In)
Power Supply 2
AC Power Input
53h
(PS/2 Power In)
Power Supply 1 +12V % of
Maximum Current Output
54h
(PS/1 Curr Out %)
Power Supply 2 +12V % of
Maximum Current Output
55h
(PS/2 Curr Out %)
Power Supply 1
Temperature
56h
(PS/1 Temperature)
Power Supply 2
Temperature
57h
(PS/2 Temperature)
Processor 1 Status
(P1 Status)
Processor 2 Status
(P2 Status)
Processor 1 Thermal Margin
(P1 Therm Margin)
178
60h
61h
62h
Intel® Workstation System SC5650SCWS TPS
Platform
Applicability
Sensor Type
Event /
Event Offset
Reading Type Triggers
Chassisspecific
Other Units
Threshold
0Bh
01h
Chassisspecific
Other Units
Threshold
0Bh
01h
Chassisspecific
Current
Threshold
03h
01h
Chassisspecific
Current
Threshold
03h
01h
Chassisspecific
Temperature
Threshold
01h
01h
Chassisspecific
All
Dual
processor
only
All
Temperature
Processor
07h
Processor
07h
Threshold
01h
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Temperature
Threshold
01h
01h
[u] [c,nc]
Contrib. To
System
Status
nc =
Degraded
c = Non-fatal
[u] [c,nc]
nc =
Degraded
c = Non-fatal
[u] [c,nc]
nc =
Degraded
c = Non-fatal
[u] [c,nc]
nc =
Degraded
c = Non-fatal
[u] [c,nc]
nc =
Degraded
c = Non-fatal
[u] [c,nc]
nc =
Degraded
c = Non-fatal
Assert /
De-assert
Value /
Offsets
Event
Rearm
Data
Standby
As and
De
Analog
R, T
A
X
As and
De
Analog
R, T
A
X
As and
De
Analog
R, T
A
X
As and
De
Analog
R, T
A
X
As and
De
Analog
R, T
A
X
As and
De
Analog
R, T
A
X
As and
De
–
Trig Offset
M
–
Trig Offset
M
Analog
–
–
01 - Thermal trip
Fatal
07 - Presence
OK
01- Thermal trip
Fatal
07 - Presence
OK
As and
De
–
–
–
Intel order number: E81822-002
Readable
Revision 1.2
X
X
–
Intel® Workstation System SC5650SCWS TPS
Full Sensor Name
(Sensor name in SDR)
Processor 2 Thermal Margin
(P2 Therm Margin)
Processor 1 Thermal
Control %
Sensor #
Platform
Applicability
63h
Dual
processor
only
64h
All
65h
Dual
processor
only
66h
All
(P1 Therm Ctrl %)
Processor 2 Thermal
Control %
(P2 Therm Ctrl %)
Processor 1 VRD Temp
(P1 VRD Hot)
Processor 2 VRD Temp
(P2 VRD Hot)
Catastrophic Error
(CATERR)
CPU Missing
(CPU Missing)
IOH Thermal Trip
(IOH Thermal Trip)
67h
68h
69h
6Ah
Dual
processor
only
All
All
All
Appendix C: BMC Sensor Tables
Sensor Type
Event /
Event Offset
Reading Type Triggers
Temperature
Threshold
01h
01h
Temperature
Threshold
01h
01h
Temperature
Threshold
01h
01h
Temperature
Digital
Discrete
01h
Temperature
01h
Processor
07h
Processor
07h
Temperature
01h
05h
Digital
Discrete
05h
Digital
Discrete
03h
Digital
Discrete
03h
Digital
Discrete
03h
Contrib. To
System
Status
Assert /
De-assert
Readable
Value /
Offsets
Event
Rearm
Data
–
–
–
Analog
–
–
–
[u] [c,nc]
Non-fatal
As and
De
Analog
Trig Offset
A
–
[u] [c,nc]
Non-fatal
As and
De
Analog
Trig Offset
A
–
01 - Limit
exceeded
Fatal
As and
De
–
Trig Offset
M
–
01 - Limit
exceeded
Fatal
As and
De
–
Trig Offset
M
–
01 – State
Asserted
Non-fatal
As and
De
–
Trig Offset
M
–
01 – State
Asserted
Fatal
As and
De
–
Trig Offset
M
–
01 – State
Asserted
Fatal
As and
De
–
Trig Offset
M
–
Note 1: Sensor is only present on systems that have applicable redundancy (for example, a fan or power supply).
Revision 1.2
Standby
Intel order number: E81822-002
179
Appendix D: Platform Specific BMC Appendix
Intel® Workstation System SC5650SCWS TPS
Appendix D: Platform Specific BMC Appendix
Table 112. Platform Specific BMC Features
Y: Support
Intel® Server System
SC5650SCWS
N: Not Support
CPU 1 Fan Sensor #31
Y
Fan Tachometer
Sensors
Fan
Presence
Sensors
CPU 2 Fan Sensor #30
Y
System Fan 1 Sensor #37
Y
System Fan 2 Sensor #36
N
System Fan 3 Sensor #35
Y
System Fan 4 Sensor #34
N
System Fan 5 Sensor #33
Y
System Fan 1 Presence Sensor #40
N
System Fan 2 Presence Sensor #41
N
System Fan 3 Presence Sensor #42
N
System Fan 4 Presence Sensor #43
N
Fan
Domain
Fan Domain 0
CPU 1 Fan, CPU 2 Fan
Fan Domain 1
System Fan 5
Fan Domain 2
System Fan 1
Fan Domain 3
System Fan 3
Hot-Swap HDD Backplane (HSC) Availability
180
Y
Revision 1.2
Intel order number: E81822-002
Intel® Workstation System SC5650SCWS TPS
Appendix E: POST Code Diagnostic LED Decoder
Appendix E: POST Code Diagnostic LED Decoder
During the system boot process, the BIOS executes a number of platform configuration
processes, each of which is assigned a specific hex POST code number. As each configuration
routine is started, the BIOS displays the POST code to the POST Code Diagnostic LEDs on the
back edge of the workstation board. To assist in troubleshooting a system hang during the
POST process, you can use the Diagnostic LEDs to identify the last POST process executed.
Each POST code is represented by eight amber Diagnostic LEDs. The POST codes are divided
into two nibbles: an upper nibble and a lower nibble. The upper nibble bits are represented by
Diagnostic LEDs #4, #5, #6 and #7. The lower nibble bits are represented by Diagnostics LEDs
#0, #1, #2, and #3. If the bit is set in the upper and lower nibbles, the corresponding LED lights
up. If the bit is clear, the corresponding LED is off.
Diagnostic LED #7 is labeled “MSB” (Most Significant Bit), and Diagnostic LED #0 is labeled
“LSB” (Least Significant Bit).
A. Diagnostic LED #7 (MSB LED)
E. Diagnostic LED #3
B. Diagnostic LED #6
F. Diagnostic LED #2
C. Diagnostic LED #5
G. Diagnostic LED #1
D. Diagnostic LED #4
H. Diagnostic LED #0 (LSB LED)
Figure 62. Diagnostic LED Placement Diagram
In the following example, the BIOS sends a value of EDh to the diagnostic LED decoder. The
LEDs are decoded as follows:
Table 113. POST Progress Code LED Example
Upper Nibble LEDs
LEDs
Status
Results
Lower Nibble LEDs
LED
#7
LED
#6
LED
#5
LED
#4
LED
#3
LED
#2
LED
#1
LED
#0
8h
4h
2h
1h
8h
4h
2h
1h
ON
ON
ON
ON
ON
ON
OFF
ON
1
1
1
0
1
1
0
1
Eh
Dh
Revision 1.2
Intel order number: E81822-002
181
Appendix E: POST Code Diagnostic LED Decoder
Intel® Workstation System SC5650SCWS TPS
Upper nibble bits = 1110b = Eh; Lower nibble bits = 1101b = Dh; the two are concatenated as EDh. Find
the meaning of POST Code EDh in below table – Memory Population Error: RDIMMs and UDIMMs
cannot be mixed.
Table 114. POST Codes and Messages
Progress Code
Multi-use Code
Progress Code Definition
This POST Code is used in different contexts
Seen at the start of Memory Reference Code (MRC)
0xF2
Start of the very early platform initialization code
Very late in POST, it is the signal that the operating system has switched to virtual memory mode
Memory Error Codes (Accompanied by a beep code)
These codes are used in early POST by Memory Reference Code. Later in POST these same codes are used for other Progress Codes.
These progress codes are subject to change as per Memory Reference Code
0xE8
No Usable Memory Error: No memory in the system, or SPD bad so no memory could be detected, or
all memory failed Hardware BIST. System is halted.
0xEB
Memory Test Error: One or memory DIMMs/Channels failed Hardware BIST, but usable memory
remains. System continues POST.
0xED
Population Error: RDIMMs and UDIMMs cannot be mixed in the system.
0xEE
Mismatch Error: more than 2 Quad Ranked DIMMS in a channel.
Host Processor
0x04
Early processor initialization where system BSP is selected
0x10
Power-on initialization of the host processor (Boot Strap Processor)
0x11
Host processor cache initialization (including AP)
0x12
Starting application processor initialization
0x13
SMM initialization
Chipset
0x21
Initializing a chipset component
Memory
0x22
Reading configuration data from memory (SPD on DIMM)
0x23
Detecting presence of memory
0x24
Programming timing parameters in the memory controller
0x25
Configuring memory parameters in the memory controller
0x26
Optimizing memory controller settings
0x27
Initializing memory, such as ECC init
0x28
Testing memory
PCI Bus
0x50
Enumerating PCI buses
0x51
Allocating resources to PCI buses
0x52
Hot-plug PCI controller initialization
182
Revision 1.2
Intel order number: E81822-002
Intel® Workstation System SC5650SCWS TPS
Progress Code
0x53-0x57
Appendix E: POST Code Diagnostic LED Decoder
Progress Code Definition
Reserved for PCI Bus
USB
0x58
Resetting USB bus
0x59
Reserved for USB devices
ATA / ATAPI / SATA
0x5A
Resetting SATA bus and all devices
0x5B
Reserved for ATA
SMBUS
0x5C
Resetting SMBUS
0x5D
Reserved for SMBUS
Local Console
0x70
Resetting the video controller (VGA)
0x71
Disabling the video controller (VGA)
0x72
Enabling the video controller (VGA)
Remote Console
0x78
Resetting the console controller
0x79
Disabling the console controller
0x7A
Enabling the console controller
Keyboard (only USB)
0x90
Resetting the keyboard
0x91
Disabling the keyboard
0x92
Detecting the presence of the keyboard
0x93
Enabling the keyboard
0x94
Clearing keyboard input buffer
0x95
Instructing keyboard controller to run Self Test (PS/2 only)
Mouse (only USB)
0x98
Resetting the mouse
0x99
Detecting the mouse
0x9A
Detecting the presence of mouse
0x9B
Enabling the mouse
Fixed Media
0xB0
Resetting fixed media device
0xB1
Disabling fixed media device
0xB2
Detecting the presence of a fixed media device (hard drive detection, etc.)
0xB3
Enabling/configuring a fixed media device
Revision 1.2
Intel order number: E81822-002
183
Appendix E: POST Code Diagnostic LED Decoder
Progress Code
Intel® Workstation System SC5650SCWS TPS
Progress Code Definition
Removable Media
0xB8
Resetting the removable media device
0xB9
Disabling the removable media device
0xBA
Detecting the presence of a removable media device (CDROM detection, etc.)
0xBC
Enabling/configuring a removable media device
Boot Device Selection
0xDy
Trying boot selection y (where y = 0 to F)
Pre-EFI Initialization (PEI) Core (not accompanied by a beep code)
0xE0
Started dispatching early initialization modules (PEIM)
0xE2
Initial memory found, configured, and installed correctly
0xE1,0xE3
Reserved for initialization module use (PEIM)
Driver eXecution Environment (DXE) Core (not accompanied by a beep code)
0xE4
Entered EFI driver execution phase (DXE)
0xE5
Started dispatching drivers
0xE6
Started connecting drivers
DXE Drivers (not accompanied by a beep code)
0xE7
Waiting for user input
0xE8
Checking password
0xE9
Entering the BIOS Setup
0xEA
Flash Update
0xEE
Calling Int 19. One beep unless silent boot is enabled.
0xEF
Unrecoverable Boot failure
Runtime Phase / EFI Operating System Boot
0xF4
Entering the sleep state
0xF5
Exiting the sleep state
0xF8
Operating system has requested EFI to close boot services
0xF9
Operating system has switched to virtual address mode
ExitBootServices ( ) has been called
SetVirtualAddressMap ( ) has been called
0xFA
Operating system has requested the system to reset
ResetSystem () has been called
Pre-EFI Initialization Module (PEIM) / Recovery
0x30
Crisis recovery has been initiated because of a user request
0x31
Crisis recovery has been initiated by software (corrupt flash)
0x34
Loading crisis recovery capsule
0x35
Handing off control to the crisis recovery capsule
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Progress Code
0x3F
Appendix E: POST Code Diagnostic LED Decoder
Progress Code Definition
Unable to complete crisis recovery
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Appendix F: POST Error Messages and Handling
Intel® Workstation System SC5650SCWS TPS
Appendix F: POST Error Messages and Handling
Whenever possible, the BIOS outputs the current boot progress codes on the video screen.
Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class,
subclass, and operation information. The class and subclass fields point to the type of hardware
being initialized. The operation field represents the specific initialization activity. Based on the
data bit availability to display progress codes, you can customize a progress code to fit the data
width. The higher the data bit, the higher the granularity of information that can be sent on the
progress port. The system BIOS or option ROMs may report progress codes.
The Response section in the following table is divided into three types:
•
•
No Pause: The message is displayed on the screen or on the Error Manager screen.
The system continues booting in a degraded state. The user may want to replace the
erroneous unit. The POST Error Pause option setting in the BIOS setup does not have
any effect on this error.
Pause: The message is displayed on the Error Manager screen, and an error is logged
to the SEL. The POST Error Pause option setting in the BIOS setup determines
whether the system pauses to the Error Manager for this type of error so the user can
take immediate corrective action or the system continues booting.
Note that for 0048 “Password check failed”, the system will halt and then after the next
reset/reboot, it will display the error code in the Error Manager screen.
•
Halt: The system halts during post at a blank screen with the text “Unrecoverable fatal
error found. System will not boot until the error is resolved” and “Press <F2> to
enter setup” The POST Error Pause option setting in the BIOS setup does not have
any effect with this class of error.
After entering the BIOS setup, the error message displays on the Error Manager
screen, and an error is logged to the SEL with the error code. The system cannot boot
unless the error is resolved. The user must replace the faulty part and restart the
system.
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Appendix F: POST Error Messages and Handling
Table 115. POST Error Messages and Handling
Error Code
Error Message
Response
0012
CMOS date / time not set
Pause
0048
Password check failed
Pause
0108
Keyboard component encountered a locked error.
No Pause
0109
Keyboard component encountered a stuck key error.
No Pause
0113
Fixed Media The SAS RAID firmware can not run properly. The user should attempt to
Pause
reflash the firmware.
0140
PCI component encountered a PERR error.
Pause
0141
PCI resource conflict
Pause
0146
PCI out of resources error
Pause
0192
Processor 0x cache size mismatch detected.
Halt
0193
Processor 0x stepping mismatch.
No Pause
0194
Processor 0x family mismatch detected.
Halt
0195
Processor 0x Intel® QPI speed mismatch.
Pause
0196
Processor 0x model mismatch.
Halt
0197
Processor 0x speeds mismatched.
Halt
0198
Processor 0x family is not supported.
Halt
019F
Processor and chipset stepping configuration is unsupported.
Pause
5220
CMOS/NVRAM Configuration Cleared
Pause
5221
Passwords cleared by jumper
Pause
5224
Password clear Jumper is Set.
Pause
8160
Processor 01 unable to apply microcode update
Pause
8161
Processor 02 unable to apply microcode update
Pause
8180
Processor 0x microcode update not found.
No Pause
8190
Watchdog timer failed on last boot
Pause
8198
OS boot watchdog timer failure.
Pause
8300
Baseboard management controller failed self-test
Pause
84F2
Baseboard management controller failed to respond
Pause
84F3
Baseboard management controller in update mode
Pause
84F4
Sensor data record empty
Pause
84FF
System event log full
No Pause
8500
Memory component could not be configured in the selected RAS mode.
Pause
8520
DIMM_A1 failed Self Test (BIST).
Pause
8521
DIMM_A2 failed Self Test (BIST).
Pause
8522
DIMM_B1 failed Self Test (BIST).
Pause
8523
DIMM_B2 failed Self Test (BIST).
Pause
8524
DIMM_C1 failed Self Test (BIST).
Pause
8525
DIMM_C2 failed Self Test (BIST).
Pause
8526
DIMM_D1 failed Self Test (BIST).
Pause
8527
DIMM_D2 failed Self Test (BIST).
Pause
8528
DIMM_E1 failed Self Test (BIST).
Pause
8529
DIMM_E2 failed Self Test (BIST).
Pause
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Error Code
Error Message
Response
852A
DIMM_F1 failed Self Test (BIST).
Pause
852B
DIMM_F2 failed Self Test (BIST).
Pause
8540
DIMM_A1 Disabled.
Pause
8541
DIMM_A2 Disabled.
Pause
8542
DIMM_B1 Disabled.
Pause
8543
DIMM_B2 Disabled.
Pause
8544
DIMM_C1 Disabled.
Pause
8545
DIMM_C2 Disabled.
Pause
8546
DIMM_D1 Disabled.
Pause
8547
DIMM_D2 Disabled.
Pause
8548
DIMM_E1 Disabled.
Pause
8549
DIMM_E2 Disabled.
Pause
854A
DIMM_F1 Disabled.
Pause
854B
DIMM_F2 Disabled.
Pause
8560
DIMM_A1 Component encountered a Serial Presence Detection (SPD) fail error.
Pause
8561
DIMM_A2 Component encountered a Serial Presence Detection (SPD) fail error.
Pause
8562
DIMM_B1 Component encountered a Serial Presence Detection (SPD) fail error.
Pause
8563
DIMM_B2 Component encountered a Serial Presence Detection (SPD) fail error.
Pause
8564
DIMM_C1 Component encountered a Serial Presence Detection (SPD) fail error.
Pause
8565
DIMM_C2 Component encountered a Serial Presence Detection (SPD) fail error.
Pause
8566
DIMM_D1 Component encountered a Serial Presence Detection (SPD) fail error.
Pause
8567
DIMM_D2 Component encountered a Serial Presence Detection (SPD) fail error.
Pause
8568
DIMM_E1 Component encountered a Serial Presence Detection (SPD) fail error.
Pause
8569
DIMM_E2 Component encountered a Serial Presence Detection (SPD) fail error.
Pause
856A
DIMM_F1 Component encountered a Serial Presence Detection (SPD) fail error.
Pause
856B
DIMM_F2 Component encountered a Serial Presence Detection (SPD) fail error.
Pause
85A0
DIMM_A1 Uncorrectable ECC error encountered.
Pause
85A1
DIMM_A2 Uncorrectable ECC error encountered.
Pause
85A2
DIMM_B1 Uncorrectable ECC error encountered.
Pause
85A3
DIMM_B2 Uncorrectable ECC error encountered.
Pause
85A4
DIMM_C1 Uncorrectable ECC error encountered.
Pause
85A5
DIMM_C2 Uncorrectable ECC error encountered.
Pause
85A6
DIMM_D1 Uncorrectable ECC error encountered.
Pause
85A7
DIMM_D2 Uncorrectable ECC error encountered.
Pause
85A8
DIMM_E1 Uncorrectable ECC error encountered.
Pause
85A9
DIMM_E2 Uncorrectable ECC error encountered.
Pause
85AA
DIMM_F1 Uncorrectable ECC error encountered.
Pause
85AB
DIMM_F2 Uncorrectable ECC error encountered.
Pause
8604
Chipset Reclaim of non critical variables complete.
No Pause
9000
Unspecified processor component has encountered a non specific error.
Pause
9223
Keyboard component was not detected.
No Pause
9226
Keyboard component encountered a controller error.
No Pause
9243
Mouse component was not detected.
No Pause
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Appendix F: POST Error Messages and Handling
Error Code
Error Message
Response
9246
Mouse component encountered a controller error.
No Pause
9266
Local Console component encountered a controller error.
No Pause
9268
Local Console component encountered an output error.
No Pause
9269
Local Console component encountered a resource conflict error.
No Pause
9286
Remote Console component encountered a controller error.
No Pause
9287
Remote Console component encountered an input error.
No Pause
9288
Remote Console component encountered an output error.
No Pause
92A3
Serial port component was not detected
Pause
92A9
Serial port component encountered a resource conflict error
Pause
92C6
Serial Port controller error
No Pause
92C7
Serial Port component encountered an input error.
No Pause
92C8
Serial Port component encountered an output error.
No Pause
94C6
LPC component encountered a controller error.
No Pause
94C9
LPC component encountered a resource conflict error.
Pause
9506
ATA/ATPI component encountered a controller error.
No Pause
95A6
PCI component encountered a controller error.
No Pause
95A7
PCI component encountered a read error.
No Pause
95A8
PCI component encountered a write error.
No Pause
9609
Unspecified software component encountered a start error.
No Pause
9641
PEI Core component encountered a load error.
No Pause
9667
PEI module component encountered a illegal software state error.
Halt
9687
DXE core component encountered a illegal software state error.
Halt
96A7
DXE boot services driver component encountered a illegal software state error.
Halt
96AB
DXE boot services driver component encountered invalid configuration.
No Pause
96E7
SMM driver component encountered a illegal software state error.
Halt
0xA000
TPM device not detected.
No Pause
0xA001
TPM device missing or not responding.
No Pause
0xA002
TPM device failure.
No Pause
0xA003
TPM device failed self test.
No Pause
0xA022
Processor component encountered a mismatch error.
Pause
0xA027
Processor component encountered a low voltage error.
No Pause
0xA028
Processor component encountered a high voltage error.
No Pause
0xA421
PCI component encountered a SERR error.
Halt
0xA500
ATA/ATPI ATA bus SMART not supported.
No Pause
0xA501
ATA/ATPI ATA SMART is disabled.
No Pause
0xA5A0
PCI Express component encountered a PERR error.
No Pause
0xA5A1
PCI Express component encountered a SERR error.
Halt
0xA5A4
PCI Express IBIST error.
Pause
0xA6A0
DXE boot services driver Not enough memory available to shadow a legacy option
ROM.
No Pause
0xB6A3
DXE boot services driver Unrecognized.
Pause
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Intel® Workstation System SC5650SCWS TPS
POST Error Beep Codes
The following table lists the POST error beep codes. Prior to system video initialization, the
BIOS uses these beep codes to inform users of error conditions. The beep code is followed by a
user-visible code on the POST Progress LEDs.
Table 116. POST Error Beep Codes
Beeps
Error
Message
POST Progress Code
Description
3
Memory error
Multiple
System halted because a fatal error related to the memory was detected.
The BMC may generate beep codes upon detection of failure conditions. Beep codes are
sounded each time the problem is discovered, such as on each power-up attempt but are not
sounded continuously. Each digit in the code is represented by a sequence of beeps whose
count is equal to the digit.
Table 117. BMC Beep Codes
Code
1-5-2-1
Reason for Beep
CPU: Empty slot / Population error
Associated Sensors
CPU sockets are populated incorrectly – CPU1
must be populated before CPU2.
1-5-4-2
Power fault: DC power unexpectedly lost (power good dropout).
Power unit – power unit failure offset.
1-5-4-4
Power control fault (power good assertion timeout).
Power unit – soft power control failure offset.
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Appendix G: Installation Guidelines
Appendix G: Installation Guidelines
1. Drivers for Sun Solaris* 10 U5 (05/08)
Device
Description
Chipset
No driver required under Sun Solaris*
Enhanced SATA mode (Onboard SATA)
No driver required under Sun Solaris*
AHCI (Onboard SATA)
No driver required under Sun Solaris*
Onboard NIC (Intel® 82575EB)
No driver required under Sun Solaris*
AXX4SASMOD (Native SAS pass through mode)
No driver required under Sun Solaris*
AXXROMBSASMR
Driver is available from:
http://support.intel.com/support/motherboards/server/S5520SC/
ESRTII (Onboard SATA, AXX4SASMOD)
Not currently supported under Sun Solaris*
Onboard Video (ServerEngines*)
No driver required under Sun Solaris*
Onboard Audio (Realtek* ALC889)
Not currently supported under Sun Solaris*
Onboard 1394 (TI* TSB43AB22A)
Not currently supported under Sun Solaris*
Onboard TPM
Not currently supported under Sun Solaris*
Intel® Hot Swap Hard Drive back plane
No driver required under Sun Solaris*
2. Sun Solaris* 10 U5 (05/08) hangs during early boot when EHCI-2 is enabled
Description
Sun Solaris* 10 U5 may hang during early boot in the Intel® Workstation System SC5650SCWS when USB
2.0 is Enabled
Guideline
Disable “USB 2.0 Controller” option in BIOS Setup Menu, or follow the instructions listed at the following
website in order to accomplish this
http://bugs.opensolaris.org/view_bug.do?bug_id=6681221
3. Sun Solaris* 10 U5 (05/08) may fail to boot into graphics display
Description
Sun Solaris* 10 U5 may fail to boot into graphics display with Intel® Workstation System SC5650SCWS
onboard video controller
Guideline
Edit the script /usr/bin/X11/Xserver and modify arguments as following in order to accomplish graphics
display.
SERVERARGS=”-depth 16 –fbbpp 16”
4. System may experience high power consumption under Microsoft Windows* Server 2003
when the processor is idle
Description
Intel® Workstation System SC5650SCWS may experience high power consumption under Microsoft
Windows* Server 2003 when the processor is idle and there is a discontinuity in the C-states
Guideline
Follow the instructions listed at the following website to apply the hot fix only to systems that are
experience this problem.
http://support.microsoft.com/kb/941838
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5. System may experience high power consumption under Microsoft Windows* XP Service
Pack 2 when the processor is idle
Description
Intel® Workstation System SC5650SCWS may experience high power consumption under Microsoft
Windows* XP Service Pack 2 when the processor is idle and there is a discontinuity in the C-states
Guideline
Follow the instructions listed at the following website to apply the hot fix only to systems that are
experience this problem.
http://support.microsoft.com/kb/941837
6. When EFI Shell is selected as the first device on the BIOS boot option list, some RAID
adapters may not enter their configuration screen before the server board boots into EFI
Shell.
Description
In an Intel® Workstation System SC5650SCWS with EFI shell as first boot device, after users press hot keys
to enter RAID adapter configuration screen that hooks option ROM on INT 19h, the system may boot in to
EFI shell instead.
Guideline
Type ‘exit’ and execute under the EFI shell, the RAID adapter configuration screen will show up if
configuration screen hot keys were pressed during POST.
7. See 32MB video memory of onboard video controller after install onboard video driver
Description
After install driver of Intel® Workstation System SC5650SCWS onboard video controller, the video driver
will report 32MB video memory instead of 8MB
Guideline
The memory reported by onboard video driver is ‘attached memory’, which is accessed by the video
controller for internal operations. The graphic memory size for display fuction is still 8MB
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Glossary
Glossary
Term
Definition
ACPI
Advanced Configuration and Power Interface
ADC
Analogue to Digital Converter
AHCI
Advanced Host Controller Interface
AMT
Active Management Technology
AP
Application Processor
APIC
Advanced Programmable Interrupt Control
ARP
Address Resolution Protocol
ASIC
Application Specific Integrated Circuit
ATS
Address Translation Technology
BBS
BIOS Boot Specification
BEV
Boot Entry Vector
BIOS
Basic Input / Output System
BIST
Built-in Self Test
BMC
Baseboard Management Controller
bpp
Bits per pixel
bps
bit per second
BSP
Boot Strap Processor
Byte
8-bit quantity
CL
Controller Link
CLTT
Closed-Loop Thermal Throttling
CMOS
In terms of this specification, this describes the PC-AT compatible region of battery-backed 128
bytes of memory, which normally resides on the server/workstation board.
CRC
Critical Redundancy Check
DCA
Direct Cache Access
DAC
Digital to Analogue Converter
DDR3
Double Data Rate 3
DHCP
Dynamic Host Configuration Protocol
DIMM
Dual in-line memory module
DMA
Direct Memory Access
DPC
Direct Platform Control
DXE
Driver eXecution Environment
ECC
Error Correction Code
EEPROM
Electrically Erasable Programmable Read-Only Memory
EFUP
Environment Friendly Usage Period
EHCI
Enhanced Host Controller Interface
EIST
Enhanced Intel SpeedStep® Technology
EMC
Electromagnetic Compatibility
EMP
Emergency Management Port
EPS
External Product Specification
ESI
Enterprise South Bridge Interface
EVRD
Enterprise Voltage Regulator-Down
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Glossary
Intel® Workstation System SC5650SCWS TPS
Term
Definition
FMB
Flexible Mother Board
FRB
Fault Resilient Boot
FRU
Field Replaceable Unit
FW
Firmware
FWH
Firmware Hub
GB
1024 MB
GPA
Guest Physical Address
GPIO
General Purpose I/O
HPA
Host Physical Address
HSC
Hot-Swap Controller
HT
Hyper-Threading
Hz
Hertz (1 cycle / second)
I2 C
Inter-Integrated Circuit Bus
IA
Intel® Architecture
ICH
I/O Controller Hub
ILM
Independent Loading Mechanism
IMC
Integrated Memory Controller
INTR
Interrupt
IOH
I/O HUB
IPMB
Intelligent Platform Management Bus
IPMI
Intelligent Platform Management Interface
IRQ
Interrupt request
ITE
Information Technology Equipment
JBOD
Just Bunch of Disks
JRE
Java Runtime Environment
KB
1024 bytes
KVM
Keyboard, Video, and Mouse
LAN
Local Area Network
LCD
Liquid Crystal Display
LDAP
Local Directory Authentication Protocol
LED
Light Emitting Diode
LPC
Low-Pin Count
LSB
Least Significant Bit
LUN
Logical Unit Number
MAC
Media Access Control
MB
1024 KB
ME
Manageability Engine
MMU
Memory Management Unit
MRC
Memory Reference Code
ms
Milliseconds
MSB
Most Significant Bit
MTBF
Mean Time Between Failures
Mux
Multiplexer
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Term
Definition
NIC
Network Interface Controller
Nm
Nanometer
NMI
Non-maskable Interrupt
NUMA
Non-Uniform Memory Access
NVSRAM
Non-volatile Static Random Access Memory
OEM
Original Equipment Manufacturer
Ohm
Unit of electrical resistance
OLTT
Open-Loop Thermal Throttling
PAE
Physical Address Extension
PCB
Print Circuit Board
PCI
Peripheral Component Interconnect
PECI
Platform Environment Control Interface
PEF
Platform Event Filtering
PEP
Platform Event Paging
PMBus
Power Management Bus
PMI
Platform Management Interrupt
POST
Power-on Self Test
PWM
Pulse-Width Modulation
QPI
QuickPath Interconnect
RAID
Redundant Array of Independent Disks
RAS
Reliability, Availability, and Serviceability
RASUM
Reliability, Availability, Serviceability, Usability, and Manageability
RDIMM
Registered Dual In-Line Memory Module
RISC
Reduced Instruction Set Computing
RMII
Reduced Media Independent Interface
ROM
Read Only Memory
RTC
Real-Time Clock (Component of ICH peripheral chip on the server/workstation board)
SAS
Serial Attached SCSI
SATA
Serial ATA
SDR
Sensor Data Record
SEEPROM
Serial Electrically Erasable Programmable Read-Only Memory
SEL
System Event Log
SES
SCSI Enclosure Services
SGPIO
Serial General Purpose Input / Output
SMBus
System Management Bus
SMI
Server Management Interrupt (SMI is the highest priority non-maskable interrupt)
SMS
Server Management Software
SNMP
Simple Network Management Protocol
SOL
Serial Over LAN
SPD
Serial Presence Detect
S/PDIF
Sony*/Philips* Digital Interconnect Format
SPI
Serial Peripheral Interface
SPS
Server Platform Service
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Glossary
Intel® Workstation System SC5650SCWS TPS
Term
Definition
SSD
Solid State Drive
TBD
To Be Determined
TDP
Thermal Design Power
TIM
Thermal Interface Material
TPS
Technical Product Specification
UART
Universal Asynchronous Receiver / Transmitter
UDIMM
Unbuffered Dual In-Line Memory Module
UDP
User Datagram Protocol
UHCI
Universal Host Controller Interface
URS
Unified Retention System
USB
Universal Serial Bus
UTC
Universal time coordinate
VGA
Video Graphic Array
VID
Voltage Identification
VLSI
Very-large-scale integration
VRD
Voltage Regulator Down
VT
Virtualization Technology
VT-d
Virtualization Technology for Directed I/O
Word
16-bit quantity
WS-MAN
Web Service for Management
XD bit
Execute Disable Bit
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Reference Documents
Reference Documents
Refer to the following documents for additional information:
ƒ
Intel® Workstation Board S5520SC, Intel® Server System SC5650SCWS Specification
Update
ƒ
Intel® Server Chassis SC5650 Technical Product Specification
ƒ
Intel® Workstation Board S5520SC Technical Product Specification
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