Receiver Processor
MRP111
TECHNICAL
REFERENCE
M210620EN-B
August 2005
PUBLISHED BY
Vaisala Oyj
P.O. Box 26
FIN-00421 Helsinki
Finland
Phone (int.): +358 9 8949 1
Fax:
+358 9 8949 2227
Visit our Internet pages at http://www.vaisala.com/
© Vaisala 2005
No part of this manual may be reproduced in any form or by any means,
electronic or mechanical (including photocopying), nor may its contents be
communicated to a third party without prior written permission of the copyright
holder.
The contents are subject to change without prior notice.
Please observe that this manual does not create any legally binding obligations for
Vaisala towards the customer or end user. All legally binding commitments and
agreements are included exclusively in the applicable supply contract or
Conditions of Sale.
________________________________________________________________________________
Table of Contents
CHAPTER 1
GENERAL INFORMATION............................................................................ 3
About This Manual ................................................................... 3
Contents of This Manual ....................................................... 3
Feedback............................................................................... 4
Safety......................................................................................... 4
General Safety Considerations ............................................. 4
ESD Protection...................................................................... 4
Recycling .................................................................................. 5
Getting Help .............................................................................. 5
CHAPTER 2
PRODUCT OVERVIEW.................................................................................. 7
Introduction to Receiver Processor MRP111 ........................ 7
CHAPTER 3
FUNCTIONAL DESCRIPTION....................................................................... 9
Control Processor .................................................................... 9
CPU....................................................................................... 9
Flash Memory ..................................................................... 10
SDRAM Memory ................................................................. 11
ATA/IDE Disk Chip.............................................................. 11
Serial Channels................................................................... 11
Boot Code Resistors ........................................................... 12
Programmable Logic Device (PLD) ...................................... 12
General................................................................................ 12
Clock Dividers ..................................................................... 13
ISA Bus Interface ................................................................ 13
PLL Programmer and Serial DAC Interface........................ 13
DSP Control and Data Interface ......................................... 14
DSP Command Interface .................................................... 15
DDC Control Interface......................................................... 15
DDC Data Interface............................................................. 15
Frequency Meter ................................................................. 16
A/D Control Interface........................................................... 16
Dual D/A Interface............................................................... 16
ADC Dither Generator......................................................... 17
Receiver Control Interface .................................................. 17
MAS Control Interface......................................................... 18
Antenna Switch Control....................................................... 19
Boot Flash Write Protection ................................................ 19
Data Output Registers......................................................... 19
Ethernet Controller................................................................. 19
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Ethernet Switch ......................................................................20
Digital Signal Processor DSP................................................21
General................................................................................21
Boot Loading .......................................................................21
External SBSRAM ...............................................................21
Interrupts, Flags, and Timer ................................................22
Link Ports.............................................................................22
Serial Ports ..........................................................................22
JTAG Port............................................................................23
SERDES Receivers.................................................................23
Digital Down Converters (DDC).............................................23
Converter Circuits................................................................23
Data Inputs and Clock Selection .........................................24
Control Bus..........................................................................24
Data Output .........................................................................25
A/D Converter..........................................................................25
Input Selector and Buffer Amplifier......................................25
Converter Circuit..................................................................26
Dual D/A Converter.................................................................26
Support Logic .........................................................................27
Clock Oscillator....................................................................27
PLL Clock Multipliers ...........................................................27
Voltage Regulators ..............................................................28
Reset Circuit ........................................................................28
The LED Lamps...................................................................28
Temperature Sensor and Voltage Monitor ..........................29
Remote Start .......................................................................29
Rack Code...........................................................................29
Hardware Code ...................................................................29
Status Output.......................................................................30
Test Input.............................................................................30
CHAPTER 4
PARTS LIST .................................................................................................31
CHAPTER 5
TECHNICAL DATA ......................................................................................35
Connector Signal layout ........................................................37
COM1 Connector.................................................................37
Ethernet Connector .............................................................37
System Connector ...............................................................38
APPENDIX A
LIST OF SIGNALS .......................................................................................39
APPENDIX B
DIAGRAMS AND BOARD LAYOUTS .........................................................45
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Chapter 1 ________________________________________________________ General Information
CHAPTER 1
GENERAL INFORMATION
This chapter provides general notes for the product.
About This Manual
This manual provides information for installing, operating, and
maintaining the Receiver Processor MRP111.
Contents of This Manual
This manual consists of the following chapters:
- Chapter 1, General Information, provides general notes for the
product.
- Chapter 2, Product Overview, introduces the Receiver Processor
MRP111 features.
- Chapter 3, Functional Description, provides you detailed functional
information about the receiver processor.
- Chapter 4, Parts List, contains a list of the MRP111 parts.
- Chapter 5, Technical Data, contains technical data for MRP111.
- Appendix A, List of Signals.
- Appendix B, Diagrams and Board Layouts.
VAISALA ________________________________________________________________________ 3
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Feedback
Vaisala Customer Documentation Team welcomes your comments
and suggestions on the quality and usefulness of this publication. If
you find errors or have other suggestions for improvement, please
indicate the chapter, section, and page number. You can send
comments to us by e-mail: manuals@vaisala.com
Safety
General Safety Considerations
Throughout the manual, important safety considerations are
highlighted as follows:
WARNING
Warning alerts you to a serious hazard. If you do not read and follow
instructions very carefully at this point, there is a risk of injury or
even death.
CAUTION
Caution warns you of a potential hazard. If you do not read and
follow instructions carefully at this point, the product could be
damaged or important data could be lost.
NOTE
Note highlights important information on using the product.
ESD Protection
Electrostatic Discharge (ESD) can cause immediate or latent damage
to electronic circuits. Vaisala products are adequately protected
against ESD for their intended use. However, it is possible to damage
the product by delivering electrostatic discharges when touching,
removing, or inserting any objects inside the equipment housing.
To make sure you are not delivering high static voltages yourself:
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Chapter 1 ________________________________________________________ General Information
- Handle ESD sensitive components on a properly grounded and
protected ESD workbench. When this is not possible, ground
yourself to the equipment chassis before touching the boards.
Ground yourself with a wrist strap and a resistive connection cord.
When neither of the above is possible, touch a conductive part of
the equipment chassis with your other hand before touching the
boards.
- Always hold the boards by the edges and avoid touching the
component contacts.
Recycling
Recycle all applicable material.
Dispose of batteries and the unit according to statutory regulations.
Do not dispose of with regular household refuse.
Getting Help
Contact Vaisala technical support:
E-mail
helpdesk@vaisala.com
Telephone +358 9 8949 2789
Fax
+358 9 8949 2790
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Chapter 2 __________________________________________________________ Product Overview
CHAPTER 2
PRODUCT OVERVIEW
This chapter introduces the Receiver Processor MRP111 features.
Introduction to Receiver Processor MRP111
The Receiver Processor MRP111 is a plug-in E1-size Eurocard unit. It
is used with a 400 MHz receiver unit or with 1680 MHz Receiver
units to build up a digital radio receiver (Software Radio). The
Receiver Processor takes the digital IF data input from receiver units
at a rate of 64 Msamples / s and all further receiver functions are
performed digitally in Receiver Processor.
The Receiver Processor contains three Digital Down Converter (DDC)
chips, a Digital Signal Processor (DSP), a Control Processor, a
Programmable Logic Device (PLD), an ATA/IDE Flash disk, an
Ethernet line interface, two serial communication channels and
input/output signals for receiver controls.
Each DDC chip is a four channel device containing digital mixers, a
quadrature carrier Numerically Controlled Oscillator (NCO), digital
filters, a resampling filter, an Automatic Gain Control (AGC) loop and
a cartesian-to-polar coordinate converter providing magnitude and
phase output data at each channel.
The Digital Signal Processor is a complete 32-bit floating-point device
integrating data processing elements, a large high-speed memory
(SRAM) and I/O peripherals. In addition fast external synchronous
burst memory (SBSRAM) is provided.
The Control Processor is a 32-bit PC compatible microprocessor
system with floating-point math instructions and 64 MByte
synchronous dynamic system memory (SDRAM).
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The Programmable Logic Device (PLD) is an in-circuit-configurable
logic chip, which is used to handle control and data connections
between system blocks.
ATA Flash disk is a 64 MByte memory chip for program and data
storages.
Ethernet communication interface consists of Ethernet controller and
five channel Ethernet switch. Three switch channels are available for
external connections at 10 or 100 Mbits/s line speed.
Two asynchronous serial channels are provided for RS232 compatible
external connections.
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Chapter 3 ______________________________________________________ Functional Description
CHAPTER 3
FUNCTIONAL DESCRIPTION
This chapter provides you detailed functional information about the
receiver processor.
Control Processor
CPU
The MRP111 contains a ZFx86 type 32-bit microprocessor running at
a speed of 96 MHz. The microprocessor chip is PC compatible and
contains the following main parts:
- SDRAM controller
- PCI bus interface
- ISA bus interface
- IDE bus interface
- Serial channels COM1 and COM2.
The SDRAM controller is for connecting to the 32 bit synchronous
system memory.
PCI bus is used to connect to the10/100 MBits/s Ethernet controller.
ISA bus is used for flash type BIOS memory and system logic PLD
connections.
IDE bus connects to onboard ATA flash disk memory.
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Serial channel COM1 is for diagnostics and channel COM2 is used as
system interface.
In the circuit diagram the processor D7 is divided in six parts:
- D7-A contains common control signals, interrupt inputs, chip select
outputs, IDE interface, and floppy disk interface.
- D7-B contains PCI bus interface.
- D7-C contains ISA bus interface.
- D7-D contains SDRAM interface
- D7-E contains parallel port, serial ports COM1/2, USB bus,
keyboard, I2C bus and watchdog interfaces.
- D7-F contains power connections.
After reset the processor starts operation by executing the BIOS code
from the flash memory in ISA bus. The BIOS code verifies the correct
operation of main system components and later in operation the BIOS
code and further code execution are transferred to SDRAM system
memory.
After BIOS is complete the processor boots from onboard ATA flash
disk memory, loads logic code to PLD (Programmable Logic Device)
and starts the execution of the actual application program.
Flash Memory
The flash type program memory is for BIOS (Basic Input/Output
System) program. The memory consists of 512k x 8-bit circuit D34.
The flash type memory allows loading and modification of programs
via communication lines. In normal operation the Flash Memory is
working as read-only code memory. The first code byte, after reset, is
fetched from memory location 7FFF0 (hex) in a Boot Block. The chip
select MEMCS0# selects the device and the read control MEMRD#
activates the output data buffers of the memory.
During normal operation the write signal PMEMWR# to the D34
connects via PLD and is locked to the inactive high state. A special
unlock command sequence to PLD D8 is required to enable flash
programming.
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SDRAM Memory
The SDRAM (Synchronous Dynamic Random Access Memory) is the
main system memory for program code and data. The memory size is
64 MBytes (16 M x 32-bits) and it consist of four SDRAM circuits
each having 8M x 16 bits.
The SDRAM is divided in to two banks, chip select signal SDCS0#
selects the lower 32 MByte bank (D10, D14) and SDCS1# selects the
higher 32 MByte bank (D11, D15).
The operation of the memory is synchronous to the clock signals
SDCLK0 and SDCLK1. Column and row addresses are loaded by
SDCAS# and SDRAS# signals and SDWE# controls the write
operation. Byte mask signals SDQM0#, SDQM1#, SDQM2# and
SDQM3# are used to enable single byte wide writes, in a full 32 bit
write cycle all are active low.
ATA/IDE Disk Chip
The ATA/IDE flash disk chip (D8) is an embedded flash memory data
storage system. It has built-in ATA/IDE controller and built-in
embedded flash file system. It has a capacity of 64,028,672 bytes in
977 cylinders with 4 heads and 32 sectors.
The 16-bit IDE interface of the ZFx86 is directly connected to the
ATA/IDE standard interface of the disk chip D8.
Write protect input WP# is connected to the PLD for possible future
use.
Serial Channels
The ZFx86 has two serial channels for external serial communication.
Channel 1 is for testing and is connected to the front panel connector.
Channel 2 is the main system channel and is connected to the system
connector pins A30 (TXD2) and A31 (RXD2). This channel is
normally used for main external RS232 compatible connection.
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Boot Code Resistors
The ZFx86 processor reads the boot code from ISA bus address lines
after reset is released. The processor has weak internal resistors for
default values. In address lines SA06, SA17, SA18 and SA19 the
desired value is different from default and external resistors are
required.
In addition weak external pull-down resistors are required in lines
SA00-SA05 and SA09 which have default value 0 and are connected
to the PLD (D5), because the PLD connect week internal pull-ups to
the lines during reset. Resistors in lines SA07 and SA08 are for
possible future use.
The value of line SA23 selects the boot mode by TEST# signal input.
In normal operation TEST# is high, D46 does not drive SA23 and
normal boot is selected. If TEST# is active SA23 is driven high and
internal boot is selected.
Programmable Logic Device (PLD)
General
Programmable Logic Device (PLD) D5 is digital, user-configurable
Integrated Circuit (IC), which is used to implement custom logic
functions. The D5 is a SRAM-based PLD, which is in-circuit
configurable. Its configuration (program) code is stored in the disk
memory and the configuration takes place during the system powerup. The PLD D5 is used to implement various timing, control and
interface logic functions in the MRP111.
In the circuit diagram the PLD D5 is divided in six parts:
- D5-A contains common control signals, special I/O signals, and
five general purpose I/O signals.
- D5-B contains 76 general purpose I/O signals.
- D5-C contains 76 general purpose I/O signals.
- D5-D contains 76 general purpose I/O signals.
- D5-E contains 76 general purpose I/O signals.
- D5-F contains power connections.
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Chapter 3 ______________________________________________________ Functional Description
The main functional blocks are described closer in the following
sections.
Clock Dividers
25 MHz clock input is multiplied by fractional number
16384/12500000 to get 32768 Hz output for ZFx86 processor real
time clock. This clock signal overrides the RC oscillator D47/4 output
when PLD code is loaded.
ISA Bus Interface
ISA bus control, data and address signals are connected from ZFx86
ISA block to the PLD for DSP interface, serial channel and general
purpose I/O functions.
Address lines SA00-SA03 with chip select inputs IOCS0# and
IOCS1# are used to select desired control functions. Control lines
IORD# and IOWR# are used for read and write commands and data
lines SD0 to SD15 are used for data transfer.
Output ZWS# is activated in all IOCS0# / IOCS1# commands, output
IOCS16# is activated in IOCS1# commands and interrupt line
MZIRQ5 is used for interrupts.
Other connected lines are reserved for possible future use.
PLL Programmer and Serial DAC
Interface
PLL programmer sets the clock multiplier D27 for 40 MHz clock
output by loading a 24 bit serial control word 330C02 (hex) into D27
with 1 MHz data clock. MSB is sent first and data load signal PLLLD
is generated at the end. One programming cycle is automatically
generated after PLD configuration.
After PLL programming the same data and clock signals are used for
serial DAC A9 control. 12 bit DAC code 800 (hex) is automatically
sent after PLL programming and later on the interface runs under DSP
control. Clock rate is 3.125 MHz and signal DA4LD is used to load
the data.
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DSP Control and Data Interface
DSP control interface connects reset, clock, and clock mode control
signals to the DSP. The reset signal is released after the clock and
clock mode control signals are active.
The operation of the DSP is controlled by reset setting. After reset the
DSP starts reading boot code from link port 4.
Data flow from ZFx86 to DSP via link port 4:
Data to DSP is written from ISA bus as 16-bit words in two or four
byte packets . PLD logic writes the data in byte or nibble serial format
to DSP link port 4. In 16-bit mode four nibbles are written after each
ISA word and in 32-bit mode four bytes are written after every two
ISA words. The nibbles are written in lower four bits of link port data.
The PLD logic and link port receiver are fast enough to keep the ISA
port always ready for next word write. For special use and diagnostics
purposes port status can be checked by reading the status word.
Byte and nibble order at link port 4 are according to the following
tables (B1 and B3 are high bytes at ISA bus, N3 is the highest nibble):
Table 1
Byte Order in 32-bit Mode
Words Written by ZF
1. W1 (B1, B0)
2. W2 (B3, B2)
Table 2
Bytes Written to Link Port
1. B3
2. B2
3. B1
4. B0
Nibble Order in 16-bit Mode
Words Written by ZF
1. W1 (N3, N2, N1, N0)
Nibbles Written to Link Port
1. N3
2. N2
3. N1
4. N0
Data flow from DSP to ZFx86 via link port 5:
Data from DSP is written in four byte packets to four data registers in
PLD and further writes are inhibited until the registers are read as two
16-bit words by ZFx86 processor. The link port is fast enough to
provide data for continuous full speed read at ZFx86 ISA bus. Data
availability can also be checked by reading the status word. For
diagnostics purposes an empty read condition is indicated.
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Chapter 3 ______________________________________________________ Functional Description
Table 3
Byte Order in ZFx86 Read
Bytes from Link PortF
1. B0
2. B1
3. B2
4. B3
Words Read by ZF
1. W1 (B2, B3)
2. W2 (B0, B1)
DSP Command Interface
The command interface connects to serial port 0 of the DSP. The
rising edge of the transmit frame sync signal (DSTFS0) starts the
operation and a serial 32-bit command is clocked in from transmit
data line (DSDT0) and latched in parallel register at every 32 clocks
(DSTCLK0) as long as the frame sync signal stays high. After
reception each command is executed and required actions are
generated.
The 32-bit command word contains a direction bit, 7 device address
bits, 8 register address bits, and 16 data bits.
In a read command (direction bit = 1) frame sync signal (DSRFS0) for
input port is generated followed by 16 data bits to the serial input data
line (DSDR0).
The interface supplies a continuous 25 MHz external bit clock signals
for output (DSTCLK0) and input port (DSRCLK0) data clocks.
DDC Control Interface
DDC control interface generates control signals to the DDC chips,
SERDES receivers, and clock selectors and in addition transfers
control data to/from data bus of the DDC chips. See section Control
Bus on page 24 for bus signals.
The control interface is working under control of the DSP command
interface.
DDC Data Interface
The DDC data interface receives two serial data streams from output
ports of each DDC and converts both 224-bit serial data streams into
byte format (28 bytes each) and writes the bytes in two separate FIFO
memories. When complete data frames are received the interface starts
VAISALA _______________________________________________________________________ 15
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writing the data to the DSP link port and simultaneously the serial
inputs are ready to receive next data frames. The frame sync signal
starts the reception of a new data frame.
The frame rates depend on DDC processing parameters.
Serial bit burst rates are 2 x 32 Mbits/s and link port byte burst rates
are 16 Mbytes/s in each DDC connection.
DDC1, DDC2, and DDC3 are connected to link ports 1, 2, and 3,
respectively.
Frequency Meter
The programmable frequency meter supports cycle time
measurements of MUXFREQ and 1PPS input signals. Also cycle
times of all PLL frequencies can be measured. The frequency meter is
used by DSP command interface.
A/D Control Interface
The A/D control interface is used to set desired control outputs for the
A/D converter according to the control commands via DSP command
interface.
Serial output data and sync signals from A/D converter are passed via
PLD to the serial port 1 of the DSP.
Dual D/A Interface
The dual D/A interface connects DSP link port 0 or DDC3 output data
to the dual DAC A6. The converter has two operating modes:
- normal mode: DAC is connected to the Link Port 0.
- direct DDC3 mode: DAC is connected to the DDC3.
In normal mode link port data is written to DAC in four byte packets.
Bytes 0/1 are the DAC1 LSB/MSB and Bytes 2/3 are the DAC2
LSB/MSB. Bits 4 - 7 in the MSB bytes are not used.
Port output rate is externally controlled by LP0ACK according to the
rate setting.
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Chapter 3 ______________________________________________________ Functional Description
In direct DDC3 mode the 12 most significant bits of DDC3 serial data
stream A are converted in parallel and are directed to DAC1. Output
rate is the frame rate of the DDC3 output.
ADC Dither Generator
ADC dither generator is a pseudorandom digital noise generator
which output can be used to add dither signal to the input of an
external A/D converter.
The generator is a 15-bit linear feedback shift register operating at
3.125 MHz clock frequency. The generator can be enabled/disabled by
a DSP command.
Receiver Control Interface
This interface is addressed by the command interface of the DSP and
it writes control data to the serial synchronous control bus for the
receiver modules. The bus comprises the following signals:
- bus clock (GPOUT1)
- serial control data (GPOUT2)
- serial received data (GPIN1).
The following fixed length 21 bit format is used in bus commands:
Table 4
Bit
Signal
Start
0
STA
Bus Command Format
Dev. Addr.
bits 1 ... 4
DA0 ... 3
Reg. Addr.
bits 5 ... 9
RA0 ... 4
Data
bits 10 ... 17
D0 ... 7
Stop
bits 18... 20
STO 0 ... 2
A control command starts with a single start bit followed by device
address, register address, control data, and stop bit fields.
Device address is used to select a unit in the bus and register addresses
are used to select control functions inside a unit. Each unit has a
unique fixed device address.
In read command the 4-bit device address and a 8-bit data byte is
received from the addressed unit.
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Standard bit clock frequency is 100 kHz but some special commands
may use lower bit rates. Bus clock is running only during active
commands.
MRP111 is a bus master and only it can drive clock and control data
lines. Received data line has pull-down resistors (R3,R4) in MRP111
and each addressed unit can drive the line to a high level when
transmitting serial data in a read command.
MAS Control Interface
This interface is addressed by the command interface of the DSP and
it writes control data to the serial synchronous control bus for the
Vaisala MAS unit. The bus comprises the following signals:
- bus clock (GPOUT5)
- serial control data (GPOUT6)
- serial received data (GPIN2).
The following fixed length 33 bit format is used for control messages:
Table 5
Control Message Format
Start
Bit position
Signal name
bit 0
STA
Device
address
bits 1 ... 8
DA 0 ... 7
Register
address
bits 9 ... 16
RA 0 ... 7
Data
bits 17 ... 32
D 0 ... 16
A control message starts with a single start bit followed by device
address, register address, and control data word.
Register addresses are used to select control functions. The MAS unit
has a fixed device address 51[hex].
The MAS unit replies to every valid command by sending back a
fixed length message, which contains a start bit and a 512-bit data
block. The data block is received in the memory of the control
interface to be further read by DSP via command interface.
Standard bus clock frequency is 100 kHz and the clock is running
continuously.
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Antenna Switch Control
Antenna switch control provides reset and clock signals for an
external antenna switch. The interface has two operating modes:
In command mode the control signals are used under direct DSP
control.
In automatic rotation mode a repeated sequence of Reset signals
followed by 12 clock pulses are generated at programmable clock
pulse interval and the current antenna positions (clock pulse counts
after reset) are inserted in the data frame of the DDC2.
Reset signal is GPOUT3 (X1/D21) and clock signal is GPOUT4
(X1/E21).
Boot Flash Write Protection
Write signal PMEMWR# to Flash memory D13 is connected via PLD
and can be activated only with special unlock control sequence.
Data Output Registers
Control signals for LED lamps, status output, and general purpose I/O
lines are provided. The outputs are controlled by ZFx86 via ISA
interface.
Ethernet Controller
The AM79C793 (D3) is a single-chip Fast Ethernet controller. It
contains the following main functional blocks and features:
- 32-bit PCI host interface
- 10/100 Mbps Physical Layer Interface (PHY)
- Dual-speed CSMA/CD (10 Mbps and 100 Mbps) Media Access
Controller (MAC)
- internal TX and RX FIFOs
- EEPROM interface.
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In the circuit diagram the controller is divided in three parts: D3-A for
PCI bus connection, D3-B for Ethernet line connections and D3-C for
power connections.
The controller is directly connected to the PCI bus of the ZFx86
processor and the 25.0 MHz clock is connected through divider D44A from the 50 MHz output of the PLL clock multiplier D40.
The receive (TXP/M) and transmit (RXP/M) pairs of the Ethernet line
are directly connected to the port 1 of the Ethernet switch.
The EEPROM D18 is for programmable initialization parameters,
which are automatically loaded to the controller registers at system
reset or power up.
The power connections include extensive filtering of the analog
supply voltages.
Ethernet Switch
The KS8995 (D2) is a five port integrated Ethernet switch. It contains
five 10/100 physical layer transceivers, five MAC (Media Access
Control) units with an integrated layer 2 switch.
In the circuit diagram the D2 is divided in three parts: D2-A is for
common control and port five connections, D2-B is for port 1 to 4
connections and part D2-C is for power connections.
Port 1 is connected to the Ethernet controller. Ports 2 , 3, and 4 are for
external connections and are connected through transformers to the
front panel connector ETH (port 2) and to the system connector (port
3, 4). Port 5 is not used.
The operation of each port is identical and includes the transmit and
receive functions for a 100 Mbits/s (100BaseTX) and 10 Mbits/s
(10BaseT) Ethernet lines.
The PLL clock synthesizer in the KS8995 generates 125, 50 , 25 and
10 MHz clocks for internal system timing. All internal clocks are
generated from an external 25 MHz clock input.
The power connections include extensive filtering of the analog
supply voltages.
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Digital Signal Processor DSP
General
D12 (ADSP-21160) is a general purpose 32-bit Digital Signal
Processor (DSP). It contains a processor core, 524kByte internal
RAM, I/O processor and external port. I/O processor provides six 8bit link ports and two serial ports for external communication.
External port is used for 64-bit external memory connection.
External clock frequency is 40 MHz and the core is running at 80
MHz. During power-up a separate clock signal is supplied through a
resistor. The final 40 MHz clock overrides this clock when PLD code
is loaded.
In the circuit diagram the processor D12 is divided in four parts:
- D12-A contains common control signals.
- D12-B contains data bus interface.
- D12-C contains serial ports and link ports.
- D12-D contains power connections.
Boot Loading
The DSP has internal ROM based boot loader program. At power-up
the processor reset input signal (DSPRST#) is held active until the
control processor is ready to communicate with DSP. After the DSP
reset is released the internal boot loader program of the DSP is
directed (by setting inputs LBOOT=1, EBOOT=0 and BMS#=1) to
fetch an external program code from the link port 4. The control
processor is writing the code to the port in a half-byte serial format
and after the whole start code block is transferred it is executed by the
DSP and a response is sent back to the control processor.
External SBSRAM
High speed SBSRAM (Synchronous Burst Static Random Access
Memory) chips D51 and D13 are connected to the 64-bit external bus
of the DSP. The chip size is 524288 x 32 bits (2MBytes) and the total
memory size is 524288 x 64 bits (4MBytes). Standard system uses this
VAISALA _______________________________________________________________________ 21
Technical Reference ________________________________________________________________
memory as data storage. Address signals DSPA20 and DSPA21 are
connected for possible future use with larger capacity memory ships.
Interrupts, Flags, and Timer
The DSP has three external interrupt pins (DSPIRQ0# , DSPIRQ1#,
DSPIRQ2#), four flag pins (DSPFL0...3) and one timer pin
(DSPTIMER).
Interrupts are used in external communication. Flags and timer are for
special needs and for possible future use.
Link Ports
The DSP has six bi-directional link ports for external data transfer.
Each port has internal FIFO (First-In-First-Out) buffer memories for
input and output data. Each port have two control signals for data
transfer, port direction is set by DSP software. All port signals are
connected to the PLD, which includes the interface logic between the
port and destination connection.
The ports are used for the following data transfer channels:
- port 0 is for dual DAC data output.
- port 1 is for DDC1 data input.
- port 2 is for DDC2 data input.
- port 3 is for DDC3 data input.
- port 4 is for data input from the control processor.
- port 5 is for data output to the control processor.
Serial Ports
The DSP has two bi-directional high-speed serial ports for external
data transfer. Each port has internal FIFO (First-In-First-Out) buffer
memories for input and output data. Each port has three signals for
both directions: clock, frame sync and serial data.
Port 0 is used as command interface between PLD and DSP.
Port 1 is used for A/D converter data input. Bit clock frequency is
12.5 MHz.
22 __________________________________________________________________ M210620EN-B
Chapter 3 ______________________________________________________ Functional Description
JTAG Port
The serial JTAG test access port (TCK,TMS, TDI, TDO and TRST#)
and EMU# control signal are for product development and are not
used in normal operation.
SERDES Receivers
Sample data from external A/D converter(s) are connected to the
MRP111 with high speed SERDES (serializer/deserializer) data
link(s). Data from each converter is using three serial data streams and
a reference clock signal. At the transmitter end the parallel A/D
converter data is clocked in the serializer circuit as three 7 bit groups
and the circuit transmits these groups serially with a bit rate of seven
times the clock frequency.
In the MRP111 the deserializer circuit (D16, D22 or D28) multiplies
the clock signal by seven and samples the incoming data streams by
this multiplied clock rate to get the 7 bit groups back in the original
parallel format. The resulting 21 bit data word is clocked out at the
basic clock rate.
All data streams and clock signals are using low voltage differential
signaling (LVDS).
The standard basic clock rate is 64 MHz, which result to a 448 Mbits/s
rate at the data bit streams.
Data bits D0 ... 3, D5 ... 10 and D12 ... 17 are used for A/D data (bits
D0 ... 1 are permanently low level with 14-bit converter)
Bits D4, D11, and D18 are permanently high level (for diagnostics
purposes) and bit D19 indicates overrange signal at the converter.
Data bit D20 is not used.
Digital Down Converters (DDC)
Converter Circuits
Circuits D1, D4, and D6 are identical digital down converters
(HSP50216) each having four data input ports and four internal
converter channels. Each channel includes digital mixers, a quadrature
VAISALA _______________________________________________________________________ 23
Technical Reference ________________________________________________________________
carrier NCO, digital filters, a resampling filter, an AGC loop, and a
converter for phase and magnitude data output.
All converter channels have data selectors for connection to the
desired data input port.
Data Inputs and Clock Selection
Data outputs from SERDES receiver 1 (D16) and 2 (D22) are
connected to all DDC circuits, receiver 1 to A input ports and receiver
2 to B input ports. Data from receiver 3 (D28) is connected to C input
port of converter D4.
In addition for diagnostics purposes data from receiver 1 is connected
to the PLD. This connection can also be used to feed test data from
PLD to all converter circuits.
Clock selectors are provided for all down converters to allow
connection to a clock signal which corresponds to the selected data
connection.
Buffer circuits D26 and D29 are used to select clock signal for
converter 1: SERDES clock 1 is selected when D26 is active
(DC1SEL1 = 0) and clock 2 is selected when D29 is active. Test clock
signal from PLD is selected when both buffers are inactive.
By the same way buffers D30, D33, D53 are used to select clock for
converter 2 and buffers D36, D41 are selecting clock for converter 3.
Control Bus
DDC circuits are controlled via control bus from DSP via PLD. Chip
select signals (DC1CE#, DC2CE#, DC3CE#) select active converter,
address signals (DCA0...2) select internal registers, control strobes
(DCWR#, DCRD#) select write or read operation and data lines
(DCD00...15) carry the control data.
In addition, reset (DC1RST#, DC2RST#, DC3RST#) and synchronize
(DC1SYNC, DC2SYNC, DC3SYNC) inputs and interrupt outputs
(DC1INR#, DC2INR#, DC3INR#) are provided.
24 __________________________________________________________________ M210620EN-B
Chapter 3 ______________________________________________________ Functional Description
Data Output
The DDC circuit has four serial ports for data output. In MRP111
ports A and B from all converters are in use. Each port comprises data
and synchronizes signals (DC1SD1A and DC1SYNA for converter 1
port A) and each converter chip uses a common data clock signal
(DC1SLK for DDC 1). Standard bit rate is 32 Mbits/s.
All serial data streams are converted as 8-bit byte streams in PLD and
are further fed to the DSP via link ports.
A/D Converter
Input Selector and Buffer Amplifier
Input selector D19 is controlled by ADSEL0...2 signals. The
following input channels are available:
Table 6
Channel
0
1
2
3
4
5
6
7
Available Input Channels
Signal
ANTIN
GND
MRRMUX
+3.3VOSC
DA1T
DA2T
+2.5V
-12/+5V
Description
Antenna input for possible future use
Ground (0 V)
MRR111 multiplexer output
+3.3 V oscillator supply voltage
D/A converter 1 test output
D/A converter 2 test output
+2.5 V supply voltage
-12/+5 V test voltage (+3.45 V nom.)
The active input voltage range for all inputs is 0.0 to 4.75 V (limited
by the supply voltage of the selector).
Buffer op amp A5-B connects the selector output to the single-ended
differential input circuit A2, which further buffers the signal to the
A/D converter. The gain of the circuit is 2/3.
The output of A5-B is also fed to PLD (signal MUXFREQ) for direct
frequency measurements.
Converter active input voltage range is +0.5 ... +4.5V, which
corresponds to a range of -0.5 ... +5.5V at the selector input.
VAISALA _______________________________________________________________________ 25
Technical Reference ________________________________________________________________
NOTE
This description of input selector and buffer amplifier corresponds to
MRP111 units with HW revision 10 or higher. For earlier units
channels 1, 3, 6, and 7 are not connected and the A2 gain is 1
corresponding to an input range of +0.5 ... +4.5 V.
Converter Circuit
The A4 (AD7723) is a 16-bit, sigma-delta analog to digital converter
(ADC). The converter is used with 12.5 MHz clock signal (ADCLK)
resulting in 390 kHz sample rate.
The converter data interface is serial and connects through PLD to the
DSP. Signals serial clock output (ADCSCO), serial data output
(ADCSDO) and frame sync output (ADCFSO) are used in serial data
connection.
The output code is in twos complement binary format and the output
equation is:
Dout = (Vin - 2.5) / 0.000091552
where
Dout
Vin
NOTE
=
=
digital output code [twos complement binary]
analog voltage at selector input [V]
This equation corresponds to MRP111 units with HW revision 10 or
higher. For earlier units, replace divisor by figure 0.000061.
Dual D/A Converter
D/A converter A6 is a dual channel 12-bit digital to analog converter.
Converter output currents are set by 12-bit binary data from link port 0
of the DSP. Byte wide data from the link port are combined to proper
12-bit codes in the PLD.
In direct DDC mode data to converter 1 is taken from the serial output
of the DDC3 and converted to 12-bit parallel values in PLD.
26 __________________________________________________________________ M210620EN-B
Chapter 3 ______________________________________________________ Functional Description
Converter output current is converted to voltage output by op amp A3A and op amp A3-B for converter 1 and 2, respectively.
Voltage output equation is:
Vout = 4.22 * (DAC Code)/4096 V
The outputs of the op amps are connected via resistors to system
connector for external use. Test signals DA1T and DA2T are
connected to the A/D converter.
Support Logic
Clock Oscillator
TCXO type clock oscillator Z2 provides 10 MHz timing reference for
the MRP111. The oscillator frequency is fine-tuned by control voltage
from D/A converter A9 via amplifier A8-A to the VC input.
The oscillator output is amplified by A8-B and buffered by D23 to the
main 10 MHz reference.
Alternative clock oscillator Z1 is not installed.
Linear regulator A11 supplies +3.3V operating voltage to the clock
oscillator and PLL circuits.
PLL Clock Multipliers
PLL (Phase Locked Loop) clock multipliers are used to generate all
required system clock signals from the 10 MHz reference clock
source.
PLL circuits D35, D31 and D40 are pin programmed for desired
output frequency. Circuit D35 generates 14.3 MHz clock for ZFx86,
D31 generates 48 MHz for ZFx86 and D40 generates 50 MHz for
PLD logic and Ethernet clocking. The 25 MHz Ethernet clock is
divided from 50 MHz output by D44-A.
PLL circuit D27 is serially programmable for desired output
frequency. In standard MRP111 the output frequency is programmed
to 40 MHz for DSP clock.
VAISALA _______________________________________________________________________ 27
Technical Reference ________________________________________________________________
Voltage Regulators
Linear voltage regulators are used to generate required +2.5 V internal
operating voltages from +3.3 V system voltage.
Regulator A1 generates +2.5 V for Ethernet switch D2 and for core
voltages of ZFx86 and PLD.
Regulator A7 generates +2.5 V core voltage (+VDSP) for DSP.
Reset Circuit
The circuit A10 controls the reset signal RES#, which is forced to the
active low state if at least one of the following conditions appear:
- +5V operating voltage falls below +4.5 V
- +3.3V operating voltage falls below +3.0 V
- +2.5V operating voltage falls below +2.2 V
- internal reset line SELFRES# is in 0-state
- external reset line MRES# is in 0-state.
The reset output signal is held active typically 200 ms after the reset
condition is disappeared.
The LED Lamps
The Test lamp V1 is a red/green bi-color LED type lamp. The red and
green lamps are controlled by signals REDLED# and GRNLED# from
the PLD D5. Yellow color is produced when both lamps are on.
During system reset yellow color is shown. After reset red lamp
remains on during the boot sequence of the control processor. When
booting is complete the red lamp is switched off and the green lamp is
switched on to indicate normal device operation.
28 __________________________________________________________________ M210620EN-B
Chapter 3 ______________________________________________________ Functional Description
Temperature Sensor and Voltage
Monitor
The temperature sensor and voltage monitor circuit A12 measures the
circuit board temperature, three system voltages (+3.3V, +5V, +12V)
and internal voltage +VDSP.
The sensor is controlled serially via clock (SBCLK) and data line
(SBDATA). Control is performed by PC processor via chip interface
in PLD.
Remote Start
The signals STRTOUT (X1/A40) and STRTIN (X1/B40) are intended
for remote start or general purpose event marker input. In the external
circuit STRTOUT is looped back to STRTIN via a momentary switch,
and a closing (or opening) switch contact is used to indicate sounding
start or event mark. Minimum detectable pulse length is 0.1 s.
Alternatively a ground referenced TTL or RS232 level pulse
connected to the STRTIN input can be used.
The external switch or signal should be in the idle state during system
power up to allow correct idle reference to be read.
Rack Code
The rack code inputs R0IN#, R1IN#, R2IN#, R3IN# and R4IN# from
system connector pins A45 ... E45 are fed to control processor via
PLD for info about operating environment.
Hardware Code
The 4-bit HW code from PLD (D5-D) input pins H21, D20, E20 and
J21 are fed to control processor via PLD for info about operating
hardware environment of the MRP111.
VAISALA _______________________________________________________________________ 29
Technical Reference ________________________________________________________________
Status Output
The STAT_OK control output from PLD controls the D54 buffer
which drives the status signal output at system connector pin E37 to a
low level when STAT_OK = 0.
Status signal output line is used at system level to indicate the status
of internal units.
Test Input
Test input from system connector pin B39 is fed to control processor
via PLD for testing purposes. In normal operation the input should be
left unconnected.
30 __________________________________________________________________ M210620EN-B
Chapter 4 _________________________________________________________________Parts List
CHAPTER 4
PARTS LIST
This chapter contains a list of the MRP111 parts.
Table 7
Reference
Assembly ref. 001
Assembly ref. 002
Assembly ref. 003
Assembly ref. 004
Assembly ref. 005
Assembly ref. 006
Assembly ref. 007
Assembly ref. 008
Assembly ref. 009
Assembly ref. 011
Integrated Circuits
A1,7
A2, 3, 5, 8
A4
A6
A9
A10
A11
A12
D1,4,6
D2
D3
D5
D7
D8
D9, 32, 37, 42
D10,11,14,15
D12
D13,51
D16, 22, 28
D17, 25, 45, 47
MRP111 Parts List
Part
Number
DRW213148
210854
210853
210856
210855
210857
16097
210615
210616
211522
Description
Front Panel Machining, A MRP111
EMC Gasket A 3U, Schroff 21101-854
Injector/Ejector Handle A 4HP, IEL, Schroff
Board Holder A Schroff
Sleeve A M2.5x3,Schroff 21100-660
Collar Screw A M2.5x12.3,Schroff
ESD Warning Sticker A
License Sticker A EMBOS Dos 6.22 FULL RUN
License Sticker A WIN NT Embedded 4.0
MAC Address for A Embedded Network Contr.
27139
210452
010247
010032
25116
010148
25757
25815
27162
27132
27129
27133
27079
27128
26108
210862
27170
27182
010030
19568
IC, Voltage Regulator, LT1764EQ-2.5
IC, Op. Amp. (Dual) AD8042AR (SMD)
IC, Converter A/D, AD7723
IC, Converter D/ AD9765AST
IC, Converter D/AEx, LTC1453CS8
IC, Supervisor, MAX6355SYUT-T
IC, Voltage Reg, LT1521CST-3.3
IC, Converter A/D, AD7417ARU
IC, Dig. Down Converter, HSP50216
IC, Ethernet Switch, KS8995
IC, Ethernet Controller, AM79C973BVC/W
IC, SRAM based PLD, EP1K100FI484-2
IC, PC System-on-a-Chip, SOC-MZP-Q-01, ZFx86
IC, ATA Flash Disk, SST58LD064-80-I-P1H
IC, RS232C Transceiver, MAX208EEAG
IC, SDRAM, K4S281633D-RN75
IC, DSP, ADSP-21160
IC, SB SRAM 2 EA 15.04. B 512k x 32 Synchronous SR
IC, LVDS Serdes Receiver SN65LVDS96
IC, Inverter Tiny, NC7S14(SMD Reel)
VAISALA _______________________________________________________________________ 31
Technical Reference ________________________________________________________________
Reference
D18
D19
D20, 21, 23, 24, 26, 29,
30, 33, 36, 38, 39, 41, 43,
46, 48, 53, 54
D27
D31,35,40
D34
D44
D49, 50, 52
Z2
Diodes
V1
V2,V3
Resistors
R1, 2,10-12, 14, 15, 17,
18, 20, 31-34, 40, 42, 51,
60, 62, 67, 68, 71-73, 81,
82, 85, 87, 92, 93, 95-97,
109, 110, 125, 126, 185,
187, 188, 193, 194, 196,
203, 205, 208, 216, 220,
224, 226-229, 233, 235
R3, 4, 9, 13, 22, 27, 38,
39, 41, 45, 48, 50, 54, 64,
66, 75, 77-80,
83, 84, 86, 88-91, 99,
101-106, 112-115, 117,
118, 120-123,
127-129, 132-135, 137,
138, 140, 143, 144, 146147, 149-151, 153-156,
159, 160, 163, 164, 166171, 176, 178, 180-182,
184, 189, 190, 219, 230,
232, 234, 237
R5-8,16,23-26, 29, 30,
35-37, 44, 46, 47, 49, 52,
53, 55-59, 61, 63, 65, 70,
74, 76, 94, 98, 100, 111,
116, 124, 131, 136, 139,
142, 145, 148, 152, 157,
161, 162, 165, 172-174,
177, 179, 183, 191, 192,
195, 197, 199, 202, 204,
206, 207, 209, 211-215,
217, 218, 221-223, 225,
231, 236, 238, 240, 241
R19, 43, 69, 107, 130,
141, 158, 175, 186, 198,
200, 201, 210, 239
R21, 28
Part
Number
16734
25495
26570
Description
IC, EEPROM ,CAT93C46JI(SMD)
IC, Analog MUX 8ch, MAX4051ACSE
IC, Buffer Tiny, NC7SZ125M5
210412
27135
25022
212177
26249
210744
IC, Freq. Synthesizer, ICS307M-02I
IC, Freq. Synthesizer, ICS525R-02I
IC, FLASH Sectored, S29AL016DB-90EI
IC, Flip-Flop, 74AHC74PW
IC, Bus Tranceiver, 74LV245 (SMD)
IC, Clock Oscillator, VCTCXO 10MHz, SMD
010192
210575
Diode, LED, 591-3001
Diode, TVS-array 2 EA 13.02. A SMDA03LCC
26100
Resistor, Chip, 100R 1.0% 100ppm 0603
25262
Resistor, Chip, 10K0 1.0% 100ppm 0603
25263
Resistor, Chip, 1K0 1.0% 100ppm 0603
010014
Resistor, Chip, 21R5 1% 100ppm 0603
25208
Resistor, Chip, 1M01.0% 100ppm 0603
32 __________________________________________________________________ M210620EN-B
Chapter 4 _________________________________________________________________Parts List
Reference
Capacitors
C1
C2, 3, 5, 8, 14, 38, 40,
48, 54, 69, 70, 81
C4, 6, 7, 10-13
C9
C15-20, 23-25, 28-31,
33-37, 39, 41, 42, 45-47,
49-53, 55-57, 59, 61-68,
71-75, 77-80, 83-87, 8992, 94-114, 117
C21, 22, 93
C26, 27, 58, 60, 76, 88,
115, 116, 118
C32
C43,44
Connectors
TP1
X1
X2
X3
Miscellaneous
L1-L4,6-14,17-23
T1-3
Part
Number
Description
27140
19959
Cap., Chip Ceramic, 1nF 10% X7R 2kV 1808
Cap., Chip Tantalum ,10uF 10V 20% Case A
25560
18524
19941
Cap., Chip Tantalum, 100uF 16V 20% E LowESR
Cap., Chip Ceramic Ex 1 EA 13.02. A 1n 5% NP0 50V
0805
Cap., Chip Ceramic, 100nF 10% X7R 16V 0603
25186
19405
Cap., Chip Ceramic, 100p 5% NP0 50V 0603
Cap., Chip Ceramic, 10n 10% X7R 50V 0603
19915
15621
Cap., Chip Ceramic, 470nF 10% X7R 16V 0805
Cap., Chip Ceramic Ex, 100n 10% X7R 50V 0805
0172
210249
27134
25056
Connector PinEx, E-309/6
Connector, 2mm Metric5 x 44 socket, press-fit
Connector, RJ45, 95040-6885
Connector, D, DEJK9P4-1A7N
25097
27130
211738
212048
212049
5068
6779
7067
DRW213149
PCB210052
211284
15223
211741
16166
210849
Ferrite Bead Inductor Ex , 2250ohm @100MHz, 0R8
Transformer, Pulse, H0013
Screw, Crosshead, M2,5x6 DIN7985 PZ A4
Screw, Crosshead A M2,5x8 DIN7985 PZ A4
Screw, Crosshead A M2,5x8 DIN966 PZ A4
Screw-Lock Compound, Loctite 222
Nut, Hexagon, M 2,5 /A4m
Washer, Spring, B2,5 /A4
Front Panel Assembly for MRP111
Printed Circuit Board MRP111
SYM Ghost 7.5 License A VAR Corporate 7.5 SVLP
Sticker Set A, Type, barcode and serial number
Therm. Conductive Liquid
Plastic Label
Front Panel, Shielded A 3U,4HP,Schroff
VAISALA _______________________________________________________________________ 33
Technical Reference ________________________________________________________________
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34 __________________________________________________________________ M210620EN-B
Chapter 5 ____________________________________________________________ Technical Data
CHAPTER 5
TECHNICAL DATA
This chapter contains technical data for MRP111.
Digital Down Converters
Number of converters
Channels in a converter
Clock rate
Programmable Carrier NCO
FIR Out of Band Attenuation
Digital AGC
3
4
64 MHz
32-Bit
110dB
96dB Gain Range
Digital Signal Processor
Processor type
Clock rate
Internal memory
External memory
Link ports
Serial ports
ADSP-21160
80 MHz
524 kByte
4 MByte
6
2
Control Processor
Processor type
Clock rate
SDRAM
FLASH PROM
ATA/IDE flash disk
ZFx86
96 MHz
64 MByte
2 MByte
64 MByte
Communication channels
Ethernet port
Switch port outputs
10/100 Mbits/s
3 ports
Serial lines
RS232-C, two channels
Power requirements
VAISALA _______________________________________________________________________ 35
Technical Reference ________________________________________________________________
+3.3 V
+5 V
+12 V
-12 V
4500 mA
200 mA
2 mA
10 mA
Operating temperature
Storage temperature
-30 ... +55ºC
-55 ... +80ºC
Unit type
Length, width, height
Weight
E1-size circuit board
190 x 128 x 20.5 mm
350 g
System connector
220-pin female
Status indicators
Led lamp
36 __________________________________________________________________ M210620EN-B
Chapter 5 ____________________________________________________________ Technical Data
Connector Signal layout
COM1 Connector
Serial port 1 with handshake controls is for testing and maintenance.
Type of connector:
Table 8
Signal
DCD
RXD
TXD
DTR
GND
DSR
RTS
CTS
RI
9 pin male D connector.
COM1 Connector Signal List and Layout
Pin
1
2
3
4
5
6
7
8
9
Description
Carrier detect
Received serial data
Transmitted serial data
Data terminal ready
Common (signal ground)
Data set ready
Request to send
Clear to send
Ring indicator
Level
RS232
RS232
RS232
RS232
RS232
RS232
RS232
RS232
Ethernet Connector
Type of connector:
Table 9
Signal
E1TX+
E1TXE1RX+
E1RX-
RJ45
ETH Connector Signal List and Layout
Pin
1
2
3
4
5
6
7
8
Description
Transmit signal pair
Transmit signal pair
Receive signal pair
Receive signal pair
VAISALA _______________________________________________________________________ 37
Technical Reference ________________________________________________________________
System Connector
System connector is a 220-pin, 5-row female Euroconnector.
Table 10
System Connector Signal Layout
Pin/Row
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
A
GND
SPCTRL
TS1
ADDITH
FOUT+
GND
SR1SD0
GND
SR1SD2
GND
SR2SD0
GND
SR2SD2
GND
SR3SD0
GND
SR3SD2
GND
TXD4
RXD4
TXD3
RXD3
GND
E2RX+
GND
E1RX+
GND
B
GND
GND
TS2
C
GND
MRRMUX
TS3
D
GND
GND
TS4
E
GND
ANTIN
TS5
FOUTGND
SR1SD0#
GND
SR1SD2#
GND
SR2SD0#
GND
SR2SD2#
GND
SR3SD0#
GND
SR3SD2#
GND
GPOUT5
GPIN5
GPOUT1
GPIN1
GND
E2RXGND
E1RXGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GPOUT6
GPIN6
GPOUT2
GPIN2
GND
GND
GND
GND
GND
DSPEMU#
GND
SR1SD1
GND
SR1CLK
GND
SR2SD1
GND
SR2CLK
GND
SR3SD1
GND
SR3CLK
GND
GPOUT7
JTDIPLD
GND
SR1SD1#
GND
SR1CLK#
GND
SR2SD1#
GND
SR2CLK#
GND
SR3SD1#
GND
SR3CLK#
GND
GPOUT3
GPIN3
GND
E2TX+
GND
E1TX+
GND
GPOUT4
GPIN4
GND
E2TXGND
E1TXGND
37
38
39
40
41
42
43
44
45
46
47
DA1OUT
JTDO
1PPS
STRTOUT
Key area
GND
SYSRES#
JTCKIN
JTRIN#
TEST#
STRTIN
JTDIN
DA2OUT
STATUS
JTMSIN
GND
+3.3V
BTOUT0#
+5V
R0IN#
+12V
GND
+3.3V
BTOUT1#
+5V
R1IN3
+12V
GND
BTOUT5#
+3.3V
BTOUT3#
+5V
R3IN#
-12V
GND
BTOUT6#
+3.3V
BTOUT4#
+5V
R4IN#
-12V
GND
TXD2
RXD2
TXD1SC
RXD1SC
+3.3V
BTOUT2#
+5V
R2IN#
GND
GND
38 __________________________________________________________________ M210620EN-B
Appendix A ____________________________________________________________ List of Signals
APPENDIX A
LIST OF SIGNALS
The following signal names and abbreviations are used throughout the
text and drawings of the MRP111.
Signal
+12V
+2.5V
+3.3V
+3.3VOSC
+5V
+VDSP
10MHZ
10MHZ+
10MHZ12M5HZ
14.3MHZ
1PPS#
25MHZ
48MHZ
50MHZ
ADAOR
ADBOR
ADCCFMT
ADCCLK
ADCFSI
ADCFSO
ADCOR
ADCSCO
ADCSCR
ADCSDO
Description
+12 V operating voltage
+2.5 V operating voltage
+3.3 V operating voltage
+3.3 V oscillator operating voltage
+5 V operating voltage
+ V DSP operating voltage
10 MHz clock signal
10 MHz clock signal
10 MHz clock signal
12.5 MHz clock signal
14.3 MHz clock signal
1 pulse per second
25 MHz clock signal
48 MHz clock signal
50 MHz clock signal
Analog to digital converter A overrange
Analog to digital converter A overrange
Analog to digital converter serial clock format
Analog to digital converter clock
Analog to digital converter frame sync input
Analog to digital converter frame sync output
Analog to digital converter A overrange
Analog to digital converter serial clock output
Analog to digital converter serial clock rate select
Analog to digital converter serial data output
VAISALA _______________________________________________________________________ 39
Technical Reference ________________________________________________________________
ADCSFMT
ADCSLDR
ADCSLP
ADCUNI
ADDITH
ADSEL0 ... 2
AGND
ANTIN
BALE
BT0# ... 6#
BTOUT0# ... 6#
CS16#
CTS1ZF
DA1OUT
DA1T
DA2OUT
DA2T
DA4LD#
DAD00 ... 11
DC1(2,3)CE#
DC1(2,3)CLK
DC1(2,3)CSEL1
DC1(2,3)CSEL2
DC1(2,3)ENI#
DC1(2,3)INTR#
DC1(2,3)RST#
DC1(2,3)SCLK
DC1(2,3)SD1A
DC1(2,3)SD1B
DC1(2,3)SYNA
DC1(2,3)SYNB
DC1(2,3)SYNC
DC2CSEL3
DCA0 ... 2
DCD00 ... 15
DCD1
DCD1ZF
DCRD#
DCWR#
DD00 ... 15
DEVSEL#
DISKWP#
DRQ1 (5)
DSCDIS#
Analog to digital converter serial data format select
Analog to digital converter serial low data rate
Analog to digital converter serial mode low pass filter
Analog to digital converter unipolar input
Analog to digital converter dither
Analog to digital converter input select signals
Analog ground
Antenna input
Bus address latch enable
Boot signal
Boot signal out
Chip select 16-bit
Clear to send 1 to ZFx86 processor
Digital to analog converter 1 output
Digital to analog converter 1 test signal
Digital to analog converter 2 output
Digital to analog converter 2 test signal
Digital to analog converter data load
Digital to analog converter data 00 ... 11
Digital down converter 1 (2,3) chip enable
Digital down converter 1 (2,3) clock
Digital down converter 1 (2,3) clock select 1
Digital down converter 1 (2,3) clock select 2
Digital down converter 1 (2,3) enable
Digital down converter 1 (2,3) interrupt
Digital down converter 1 (2,3) reset
Digital down converter 1 (2,3) serial data clock
Digital down converter 1 (2,3) serial data 1 A
Digital down converter 1 (2,3) serial data 1 B
Digital down converter 1 (2,3) sync A
Digital down converter 1 (2,3) sync B
Digital down converter 1 (2,3) sync input
Digital down converter 2 clock select 3
Digital down converter address 0 ... 2
Digital down converter data 00 ... 15
Data carrier detect 1
Data carrier detect 1 to ZFx86
Digital down converter read
Digital down converter write
Disk data 00 ... 15
Device select
Disk write protect
Direct memory access request 1 (5)
DSP start clock disable
40 __________________________________________________________________ M210620EN-B
Appendix A ____________________________________________________________ List of Signals
DSDR0 (1)
DSDT0 (1)
DSP
DSPA01 ... 21
DSPBRST
DSPCLK
DSPCLKM0
DSPD00 ... 63
DSPEMU#
DSPFL0 ... 3
DSPIRQ0# ... 2#
DSPMS0#
DSPRDH#
DSPRDL#
DSPRST#
DSPTIMER
DSPWRH#
DSPWRL#
DSR1
DSR1ZF
DSRCLK0
DSRCLK1
DSRFS0
DSRFS1
DSTCLK0
DSTCLK1
DSTFS0
DSTFS1
DTR1
E1(2,3)RX+/E1(2,3)TX+/ET1(2,3,4)ADIS
FRAME#
FSA20
GND
GNT0#
GPIN1(#) ... 6(#)
GPIO5 ... 7
GPOUT1(#) ... 7(#)
GRNLED#
I/O
IOCHRDY
IOCS0# ... 3#
IOCS16#
DSP serial port data 0 (1) receive
DSP serial port data 0 (1) transmit
Digital signal processor
DSP address 00 ... 21
DSP burst
DSP clock
DSP clock mode
DSP data 00 ... 63
DSP emulator
DSP flag 0 ... 3
DSP interrupt request 0# ... 2#
DSP memory select 0
DSP read high end data
DSP read low end data
DSP reset
DSP timer
DSP write high end data
DSP write low end data
Data set ready 1
Data set ready 1 to ZFx86
DSP serial port receive clock 0
DSP serial port receive clock 1
DSP serial port receive frame sync 0
DSP serial port receive frame sync 1
DSP serial port transmit clock 0
DSP serial port transmit clock 0
DSP serial port transmit frame sync 0
DSP serial port transmit frame sync 1
Data terminal ready 1
Ethernet port 1 (2,3) receive signal pair
Ethernet port 1 (2,3) transmit signal pair
Ethernet port 1 (2,3,4) automatic configure disable
Cycle frame (PCI bus signal)
Flash address 20
Ground
Grant 0 (PCI bus signal)
General purpose input 1 ... 6
General purpose input/output 5 ... 7
General purpose output 1 ... 7
Green led lamp control
Input / output
I/O channel ready (ISA bus signal)
I/O chip select 0 ... 3 (ISA bus signal)
I/O chip select 16-bit (ISA bus signal)
VAISALA _______________________________________________________________________ 41
Technical Reference ________________________________________________________________
IORD#
IOWR#
IRDY#
ISA
ISACLK
ISAERR#
JTAG
JTCDIS
JTCK
JTCKIN
JTDI
JTDIN
JTDIPLD
JTDO
JTMS
JTMSIN
JTR#
JTRIN#
KSRES#
LP0(1,2,3,4,5)ACK
LP0(1,2,3,4,5)CLK
LP0(1,2,3,4,5)D0 ... 7
MEMCS0(1)#
MEMRD#
MEMWR#
MRRMUX
MUXFREQ
MZINTA#
MZIRQ10
MZIRQ12
MZIRQ14
MZIRQ15
MZIRQ5
MZIRQ7
PAR
PCAD00 ... 31
PCBE0# ... 3#
PCICLK
PCRES#
PERR#
PLD
PLLLD
PMEMWR#
R0(1,2,3,4)IN#
I/O bus read strobe (ISA bus signal)
I/O bus write strobe (ISA bus signal)
Initiator Ready (PCI bus signal)
Industry Standard Architecture
ISA bus clock
ISA bus error
Joint Test Action Group
JTAG test clock disable
JTAG Test clock
JTAG bus test clock input
JTAG test data input
JTAG bus test data input
JTAG test data input PLD
JTAG test data output
JTAG bus test mode select
JTAG test mode select
JTAG test reset input
JTAG bus test reset input
Ethernet switch reset
Link port 0 (1,2,3,4,5) acknowledge
Link port 0 (1,2,3,4,5) clock
Link port 0 (1,2,3,4,5) data 0 ... 7
Memory select 0 (1) (ISA bus signal)
Memory read strobe (ISA bus signal)
Memory write strobe (ISA bus signal)
Receiver board (MRR) multiplexer output signal
Multiplexer output signal frequency
ZFx86 processor interrupt acknowledge
ZFx86 processor interrupt request 10
ZFx86 processor interrupt request 12
ZFx86 processor interrupt request 14
ZFx86 processor interrupt request 15
ZFx86 processor interrupt request 5
ZFx86 processor interrupt request 7
PCI Parity
PCI address / data 00 ... 31
PCI byte enable 0 ... 3
PCI clock
PCI reset
PCI parity error
Programmable logic device
Phase locked loop load
Protected memory write
Rack code 0 (1,2,3,4) input
42 __________________________________________________________________ M210620EN-B
Appendix A ____________________________________________________________ List of Signals
RA0# ... 4#
RD1FP
RD1SC
RD1ZF
RD2ZF
RD3P
RD4P
RDA00 ... 15
RDB00 ... 15
RDC00 ... 15
REDLED#
REQ0#
RES#
RI1ZF
ROM
RSTDRV
RTCLK
RTS1
RXD1 ... 4
RXD1SC
SA00 ... 19
SBCLK
SBDATA
SBHE#
SD00 ... 15
SDRAM
SDA00
SDCAS#
SDCLK0 ... 1
SDCLKE
SDCS0# ... S1#
SDD00 ... 32
SDQM0# ... 3#
SDRAS#
SDWE#
SELFRES#
SERCCLK
SERCD
SERR#
SPCTRL
SPOUT1
SR1(2,3)CLK/CLK#
SR1(2,3)SD0/0#
SR1SD1/1#
Rack address 0 ... 4
Received data 1 from front panel
Received data 1 from system connector
Received data 1 to ZFx86
Received data 2 to ZFx86
Received data 3 to PLD
Received data 4 to PLD
Received data A 00 ... 15
Received data B 00 ... 15
Received data C 00 ... 15
Red led control
PCI bus request
Reset
Ring indicator to ZFx86
Read only memory
Reset drive
Real time clock
Request to send 1
Received data line 1 ... 4
Received data line 1 from system connector
ISA address 00 ... 19
Serial bus clock
Serial bus data
ISA bus high byte enable
ISA bus data 00 ... 15
Synchronous dynamic random access memory
SDRAM address 00 ... 13
SDRAM column address strobe
SDRAM clock 1 ... 2
SDRAM clock enable
SDRAM chip select 0 ... 1
SDRAM data 00 ... 31
SDRAM byte mask 0 ... 3
SDRAM row address strobe
SDRAM write enable strobe
Self reset
Serial control clock
Serial control data
PCI system error
Spare control
Spare output 1
SERDES 1 (2, 3) clock signal pair
SERDES 1 (2,3) data 0 signal pair
SERDES 1 (2,3) data 1 signal pair
VAISALA _______________________________________________________________________ 43
Technical Reference ________________________________________________________________
SR1SD2/2#
SR1(2,3)TD0 ... 2
SRSDN#
STAT_OK
STOP#
STRTIN#
STRTOUT#
SYSRES#
TD1(2)ZF
TD3P
TEST#
TRDY#
TS1 ... 5
TXD1 ... 4
TXD1SC
ZFWDI
ZFWDO
ZWS#
SERDES 1 (2,3) data 2 signal pair
SERDES 1 (2,3) test data 0 ... 2
SERDES shut down
Status OK
PCI stop
Start signal input
Start signal output
System reset
Transmitted data 1 (2) from ZFx86
Transmitted data 3 (4) from PLD
Test signal
PCI target ready
Test signal 1 ... 5
Transmitted data line 1 ... 4
Transmitted data line 1 system connector
ZFx86 watchdog input
ZFx86 watchdog output
Zero wait states
44 __________________________________________________________________ M210620EN-B
Appendix B ________________________________________________ Diagrams and Board Layouts
APPENDIX B
DIAGRAMS AND BOARD LAYOUTS
Table 11
Code
DRW216030
DRW211705
DRW211706
MRP111 Diagrams and Board Layouts
Description
Receiver Processor MRP111 Block Diagram
Receiver Processor MRP111 Circuit Diagram
Receiver Processor MRP111 Components Layout
VAISALA _______________________________________________________________________ 45
Technical Reference ________________________________________________________________
0409-019
Figure 1
MRP111 Block Diagram
46 __________________________________________________________________ M210620EN-B
Appendix B ________________________________________________ Diagrams and Board Layouts
0409-020
Figure 2
MRP111 Circuit Diagram 1/7
VAISALA _______________________________________________________________________ 47
Technical Reference ________________________________________________________________
0409-021
Figure 3
MRP111 Circuit Diagram 2/7
48 __________________________________________________________________ M210620EN-B
Appendix B ________________________________________________ Diagrams and Board Layouts
0409-022
Figure 4
MRP111 Circuit Diagram 3/7
VAISALA _______________________________________________________________________ 49
Technical Reference ________________________________________________________________
0409-023
Figure 5
MRP111 Circuit Diagram 4/7
50 __________________________________________________________________ M210620EN-B
Appendix B ________________________________________________ Diagrams and Board Layouts
0409-024
Figure 6
MRP111 Circuit Diagram 5/7
VAISALA _______________________________________________________________________ 51
Technical Reference ________________________________________________________________
0409-025
Figure 7
MRP111 Circuit Diagram 6/7
52 __________________________________________________________________ M210620EN-B
Appendix B ________________________________________________ Diagrams and Board Layouts
0409-026
Figure 8
MRP111 Circuit Diagram 7/7
VAISALA _______________________________________________________________________ 53
Technical Reference ________________________________________________________________
0409-027
Figure 9
MRP111 Components Layout 1/2
54 __________________________________________________________________ M210620EN-B
Appendix B ________________________________________________ Diagrams and Board Layouts
0409-028
Figure 10 MRP111 Components Layout 2/2
VAISALA _______________________________________________________________________ 55