DATASHEET
ISL55001
FN6200
Rev 3.00
Nov 3, 2009
High Supply Voltage 220MHz Unity-Gain Stable Operational Amplifier
The ISL55001 is a high speed, low power, low cost
monolithic operational amplifier. The ISL55001 is
unity-gain stable and features a 300V/µs slew rate and
220MHz bandwidth while requiring only 9mA of supply
current.
Features
The power supply operating range of the ISL55001 is
from ±15V down to ±2.5V. For single-supply operation,
the ISL55001 operates from 30V down to 5V.
• Wide Supply Range: ±2.5V to ±15V Dual-Supply
and 5V to 30V Single-Supply
The ISL55001 also features an extremely wide output
voltage swing of -12.75V/+13.4V with VS = ±15V and
RL = 1k.
At a gain of +1, the ISL55001 has a -3dB bandwidth of
220MHz with a phase margin of 50°. Because of its
conventional voltage-feedback topology, the ISL55001
allows the use of reactive or non-linear elements in its
feedback network. This versatility combined with low
cost and 140mA of output-current drive makes the
ISL55001 an ideal choice for price-sensitive
applications requiring low power and high speed.
• 220MHz -3dB Bandwidth
• Unity-gain Stable
• Low Supply Current: 9mA @ VS = ±15V
• High Slew Rate: 300V/µs
• Fast Settling: 75ns to 0.1% for a 10V Step
• Wide Output Voltage Swing: -12.75V/+13.6V with
VS = ±15V, RL = 1k
• Low Cost, Enhanced Replacement for the EL2044
• Pb-free (RoHS compliant)
Applications
• Video Amplifiers
• Single-supply Amplifiers
• Active Filters/Integrators
The ISL55001 is available in an 8 Ld SO package and
specified for operation over the full -40°C to +85°C
temperature range.
• High Speed Sample-and-Hold
Ordering Information
• Pulse/RF Amplifiers
PART NUMBER
PART
MARKING
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL55001IBZ
(Note 2)
55001 IBZ
8 Ld SO
M8.15E
ISL55001IBZ-T7
(Note 1, 2)
55001 IBZ
8 Ld SO
M8.15E
ISL55001IBZ-T13 55001 IBZ
(Notes 1, 2)
8 Ld SO
M8.15E
• High Speed Signal Processing
• ADC/DAC Buffers
• Pin Diode Receivers
• Log Amplifiers
• Photo Multiplier Amplifiers
• Difference Amplifier
Pin Configuration
ISL55001
(8 LD SO)
TOP VIEW
NOTES:
1. Please refer to TB347 for details on reel specifications.
NC 1
2. These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die
attach materials, and 100% matte tin plate plus anneal
(e3 termination finish, which is RoHS compliant and
compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD020.
IN- 2
IN+ 3
VS- 4
8 NC
+
7 VS+
6 OUT
5 NC
3. For Moisture Sensitivity Level (MSL), please see device
information page for ISL55001. For more information on
MSL please see techbrief TB363.
FN6200 Rev 3.00
Nov 3, 2009
Page 1 of 12
ISL55001
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage (VS) . . . . . . . . .
Input Voltage (VIN). . . . . . . . . .
Differential Input Voltage (dVIN)
ESD Rating
Human Body Model . . . . . . . .
Machine Model . . . . . . . . . . .
Continuous Output Current . . . . . . . . . . . . . . . . . . . 60mA
Power Dissipation (PD). . . . . . . . . . . . . . . . . . . . see Curves
Operating Temperature Range (TA) . . . . . . . -40°C to +85°C
Operating Junction Temperature (TJ) . . . . . . . . . . . . +150°C
Storage Temperature (TST) . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
. . . . . . . . . ±16.5V or 33V
. . . . . . . . . . . . . . . . . ±VS
. . . . . . . . . . . . . . . . ±10V
. . . . . . . . . . . . . . . . . 3kV
. . . . . . . . . . . . . . . . 250V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
DC Electrical Specifications VS = ±15V, RL = 1k, TA = +25°C, unless otherwise specified.
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
0.06
3
mV
VOS
Input Offset Voltage
TCVOS
Average Offset Voltage Drift
IB
Input Bias Current
1.72
3.5
µA
IOS
Input Offset Current
0.27
1.5
µA
TC-IOS
Average Offset Current Drift
(Note 4)
AVOL
Open-loop Gain
PSRR
Power Supply Rejection Ratio
CMRR
18
µV/°C
0.8
nA/°C
10
17
kV/V
VS = ±5V to ±15V
75
90
dB
Common-mode Rejection Ratio
VCM = ±10V, VOUT = 0V
70
90
dB
CMIR
Common-mode Input Range
VS = ±15V
±14
V
VOUT
Output Voltage Swing
VO+, RL = 1k
13.25
13.5
V
VO-, RL = 1k
-12.6
-12.8
V
VO+, RL = 150
10.7
11.5
V
VO-, RL = 150
-8.8
-9.9
V
120
145
mA
ISC
Output Short Circuit Current
IS
Supply Current
RIN
Input Resistance
CIN
Input Capacitance
ROUT
PSOR
VOUT = ±10V, RL = 1k
No load
8.3
2.0
9.25
mA
2.75
M
AV = +1
1
pF
Output Resistance
AV = +1
50
m
Power Supply Operating Range
Dual supply
Single supply
±2.25
±15
V
4.5
30
V
MAX
UNIT
NOTE:
4. Measured from TMIN to TMAX.
AC Electrical SpecificationsVS = ±15V, AV = +1, RL = 1k, unless otherwise specified.
PARAMETER
BW
DESCRIPTION
-3dB Bandwidth (VOUT = 0.4VP-P)
CONDITION
TYP
AV = +1
220
MHz
AV = -1
55
MHz
AV = +2
53
MHz
AV = +5
17
MHz
70
MHz
55
°
280
V/µs
GBWP
Gain Bandwidth Product
PM
Phase Margin
RL = 1k, CL = 5pF
SR
Slew Rate (Note 5)
RL = 100
FN6200 Rev 3.00
Nov 3, 2009
MIN
250
Page 2 of 12
ISL55001
AC Electrical SpecificationsVS = ±15V, AV = +1, RL = 1k, unless otherwise specified. (Continued)
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
FPBW
Full-power Bandwidth (Note 6)
VS = ±15V
9.5
MHz
tS
Settling to +0.1% (AV = +1)
VS = ±15V, 10V step
75
ns
dG
Differential Gain (Note 7)
NTSC/PAL
0.01
%
dP
Differential Phase
NTSC/PAL
0.05
°
eN
Input Noise Voltage
10kHz
12
nV/H
z
iN
Input Noise Current
10kHz
1.5
pA/H
z
NOTES:
5. Slew rate is measured on rising edge.
6. For VS = ±15V, VOUT = 10VP-P, for VS = ±5V, VOUT = 5VP-P. Full-power bandwidth is based on slew rate measurement using
FPBW = SR/(2*VPEAK).
7. Video performance measured at VS = ±15V, AV = +2 with two times normal video level across RL = 150. This corresponds
to standard video levels across a back-terminated 75 load. For other values or RL, see “Typical Performance Curves” on
page 4.
FN6200 Rev 3.00
Nov 3, 2009
Page 3 of 12
ISL55001
Typical Performance Curves
Vs=+/-15V
= ±15V
RVLS=1K
RL = 1k
Source
Power=-20dBm
SOURCE POWER = -20dBm
VS = ±15V
RL = 1k
SOURCE POWER = -20dBm
FIGURE 1. OPEN-LOOP GAIN vs FREQUENCY
VS = ±15V
CL = 5pF
SOURCE POWER = -20dBm
FIGURE 2. OPEN-LOOP PHASE vs FREQUENCY
VS = ±15V
CL = 5pF
SOURCE POWER = -20dBm
RL = 1k
RL = 1k
RL = 500
RL = 500
RL = 150
RL = 150
RL = 75
RL = 75
RL = -50
RL = 50
FIGURE 3. FREQUENCY RESPONSE FOR VARIOUS
RLOAD (AV = +1)
CL = 82pF
CL = 39pF
CL = 5pF
CL = 10pF
VS = ±15V
RL = 1k
SOURCE POWER = -20dBm
FIGURE 5. FREQUENCY RESPONSE FOR VARIOUS
CLOAD (AV = +1)
FN6200 Rev 3.00
Nov 3, 2009
FIGURE 4. FREQUENCY RESPONSE FOR VARIOUS RLOAD
(AV = +2)
VS = ±15V
RL = 1k
SOURCE POWER = -20dBm
CL = 82pF
CL = 39pF
CL = 10pF
CL = 5pF
FIGURE 6. FREQUENCYRESPONSE FOR VARIOUS CLOAD
(AV = +2)
Page 4 of 12
ISL55001
Typical Performance Curves
PHASE (°)
180
360
VS = ±15V
RF = 500
RL= 500
VS = ±15V
315 RF = 500
RL= 500
270
90
AV = +1
PHASE (°)
270
(Continued)
0
-90
GAIN BANDWIDTH PRODUCT (MHz)
AV = -5
90
AV = -2
45
NOTE: FOR AV = +1, RF = 0
0
1M
10M
FREQUENCY (Hz)
100M
FIGURE 7. PHASE vs FREQUENCY FOR VARIOUS
NON-INVERTING GAIN SETTINGS
100
135
AV = +2
100k
AV = -1
180
AV = +5
-180
-270
225
100k
350
RL = 500
AV = +2
AV = +2
= 500
RF
RF ==500
500
R
L
500
R
CLL ==5pF
CL = 5pF
SLEW RATE (V/µs)
300
60
40
20
250
NEGATIVE SLEW RATE
NEGATIVE
SLEW RATE
200
100
0
6
3
9
12
15
0
3
SUPPLY VOLTAGES (±V)
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
RF = 500
RF = 250
1
RF = 100
-1
9
12
15
FIGURE 10. SLEW RATE vs SUPPLY
5
VS = ±15V
AV = +1
RL = 500
CL = 5pF
6
SUPPLY VOLTAGES (±V)
FIGURE 9. GAIN BANDWIDTH PRODUCT vs SUPPLY
RF = 0
-3
-5
POSITIVE SLEW
SLEW RATE
POSITIVE
RATE
150
0
3
100M
FIGURE 8. PHASE vs FREQUENCY FOR VARIOUS
INVERTING GAIN SETTINGS
80
5
1M
10M
FREQUENCY (Hz)
3
VS = ±15V
AV = +2
RL = 500
CL = 5pF
= 1k
RFR=F 500
1
-1
RF = 250
-3
RF = 100
-5
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 11. GAIN vs FREQUENCY FOR VARIOUS
RFEEDBACK (AV = +1)
FN6200 Rev 3.00
Nov 3, 2009
100k
1M
10M
100M
100M
FREQUENCY (Hz)
FIGURE 12. GAIN vs FREQUENCY FOR VARIOUS
RFEEDBACK (AV = +2)
Page 5 of 12
ISL55001
Typical Performance Curves
(Continued)
5
VS = ±15V
AV = +2
RF = 500
3 R = 500
L
CL = 5pF
CIN = 6.8pF
CIN = 4.7pF
1
CIN = 2.2pF
-1
CIN = 0pF
-3
-5
AV = +1
RF = 0
RL = 500
CL = 5pF
CIN = 10pF
100k
1M
10M
3
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
5
1
VS = ±15V
-1
VS = ±10V
-3
-5
100k
100M
1M
FREQUENCY (Hz)
-10
VS = ±15V
-30
-40
-40
-50
-60
-70
-60
-90
-90
10M
100M
POS_PSRR
-70
-80
1M
NEG_PSRR
-50
-80
100k
VS = ±15V
-20
-30
-100
10k
-100
10k
100k
THD
3rd HD
2nd HD
FN6200 Rev 3.00
Nov 3, 2009
100M
-30
VS = ±15V
AV = +2
-40 RF = 500
RL = 500
-50 CL = 5pF
FIN = 2MHz
THD
-60
-70
2nd HD
3rd HD
-80
-90
-100
FIGURE 17. HARMONIC DISTORTION vs FREQUENCY
(AV = +1)
10M
FIGURE 16. POWER SUPPLY REJECTION RATIO (PSRR)
HARMONIC DISTORTION (dBc)
HARMONIC DISTORTION (dB)
FIGURE 15. COMMON-MODE REJECTION RATIO (CMRR)
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
VS = ±15V
RL = 500
VOUT = 2VP-P
1G
FIGURE 14. GAIN vs FREQUENCY FOR VARIOUS SUPPLY
SETTINGS
PSRR (dB)
CMRR (dB)
-20
100M
10M
FREQUENCY (Hz)
FIGURE 13. GAIN vs FREQUENCY FOR VARIOUS
INVERTING INPUT CAPACITANCE (CIN)
-10
VS = ±2.5V
VS = ±5V
0
2
4
6
8 10 12 14 16 18 20 22 24 26
OUTPUT VOLTAGE (V)
FIGURE 18. HARMONIC DISTORTION vs OUTPUT
VOLTAGE(AV = +2)
Page 6 of 12
ISL55001
Typical Performance Curves
(Continued)
25
VS = ±15V
OUTPUT VOLTAGE SWING (VP-P)
OUTPUT VOLTAGE SWING (V)
30
RL = 500
25
CL = 5pF
20
AV = +1
RF = 0
15
10
AV = +1
RF = 500
5
0
1M
10M
RL =R500
L = 500
CL =C5pF
L = 5pF
20
AV ==+2
+2
A
RF =V 500
RF = 500
15
10
5
0
100M
0
FREQUENCY (Hz)
3
6
9
tRISE =
2ns
20% to 80%
tRISE = 8.4ns
15
FIGURE 20. OUTPUT SWING vs SUPPLY VOLTAGE FOR
VARIOUS GAIN SETTINGS
VS = ±15V
AV = +1
RF = 0
RL = 500
CL = 5pF
VOUT = 4V
20% to 80%
12
SUPPLY VOLTAGES (±V)
FIGURE 19. OUTPUT SWING vs FREQUENCY FOR
VARIOUS GAIN SETTINGS
tFALL =
2.2ns
80% to 20%
VS = ±15V
AV = +1
RF = 0
RL = 500
CL = 5pF
VOUT = 400mV
tFALL = 7.2ns
80% to 20%
FIGURE 21. LARGE SIGNAL RISE AND FALL TIMES
FIGURE 22. SMALL SIGNAL RISE AND FALL TIMES
12.5
1.8
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.6
10.0
POWER DISSIPATION (W)
TOTAL SUPPLY CURRENT (mA)
AVV == +1
+1
75
5.0
AVV==+1+1
A
RFF==0
0
R
R
RLL==500
500
C
CLL==5pF
5pF
2.5
0
0
3
6
9
12
1.2
1.136W
1.0
0.8
SO8
JA = +120°C/W
0.6
0.4
0.2
15
SUPPLY VOLTAGES (±V)
FIGURE 23. SUPPLY CURRENT vs SUPPLY VOLTAGE
FN6200 Rev 3.00
Nov 3, 2009
1.4
0
0
25
50
75 85
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 24. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Page 7 of 12
ISL55001
Product Description
The ISL55001 is a wide bandwidth, low power, and low
offset voltage feedback operational amplifier. This device
is internally compensated for closed loop gain of +1 or
greater. Connected in voltage follower mode and driving
a 500 load, the -3dB bandwidth is around a 220MHz.
Driving a 150 load and a gain of 2, the bandwidth is
about 90MHz while maintaining a 300V/µs slew rate.
The ISL55001 is designed to operate with supply voltage
from +15V to -15V. That means for single supply
application, the supply voltage is from 0V to 30V. For split
supplies application, the supply voltage is from ±15V.
The amplifier has an input common-mode voltage range
from 1.5V above the negative supply (VS- pin) to 1.5V
below the positive supply (VS+ pin). If the input signal is
outside the above specified range, it will cause the output
signal to be distorted.
The outputs of the ISL55001 can swing from -12.75V to
+13.4V for VS = ±15V. As the load resistance becomes
lower, the output swing is lower.
Choice of Feedback Resistor and Gain
Bandwidth Product
For applications that require a gain of +1, no feedback
resistor is required. Just short the output pin to the
inverting input pin. For gains greater than +1, the
feedback resistor forms a pole with the parasitic
capacitance at the inverting input. As this pole becomes
smaller, the amplifier's phase margin is reduced. This
causes ringing in the time domain and peaking in the
frequency domain. Therefore, RF can't be very big for
optimum performance. If a large value of RF must be
used, a small capacitor in the few Pico Farad range in
parallel with RF can help to reduce the ringing and
peaking at the expense of reducing the bandwidth. For
gain of +1, RF = 0 is optimum. For the gains other than
+1, optimum response is obtained with RF with proper
selection of RF and RG (see Figures 15 and 16 for
selection).
Video Performance
For good video performance, an amplifier is required to
maintain the same output impedance and the same
frequency response as DC levels are changed at the
output. This is especially difficult when driving a standard
video load of 150, because of the change in output
current with DC level. The dG and dP of this device is
about 0.01% and 0.05°, while driving 150 at a gain
of 2. Driving high impedance loads would give a similar
or better dG and dP performance.
Driving Capacitive Loads and Cables
The ISL55001 can drive 47pF loads in parallel with 500
with less than 3dB of peaking at gain of +1 and as much
as 100pF at a gain of +2 with under 3db of peaking. If
less peaking is desired in applications, a small series
resistor (usually between 5 to 50) can be placed in
series with the output to eliminate most peaking.
However, this will reduce the gain slightly. If the gain
FN6200 Rev 3.00
Nov 3, 2009
setting is greater than 1, the gain resistor RG can then
be chosen to make up for any gain loss which may be
created by the additional series resistor at the output.
When used as a cable driver, double termination is
always recommended for reflection-free performance.
For those applications, a back-termination series resistor
at the amplifier's output will isolate the amplifier from the
cable and allow extensive capacitive drive. However,
other applications may have high capacitive loads
without a back-termination resistor. Again, a small series
resistor at the output can help to reduce peaking.
Output Drive Capability
The ISL55001 does not have internal short circuit
protection circuitry. It has a typical short circuit current of
140mA. If the output is shorted indefinitely, the power
dissipation could easily overheat the die or the current
could eventually compromise metal integrity. Maximum
reliability is maintained if the output current never
exceeds ±60mA. This limit is set by the design of the
internal metal interconnect. Note that in transient
applications, the part is robust.
Short circuit protection can be provided externally with a
back match resistor in series with the output placed close
as possible to the output pin. In video applications this
would be a 75 resistor and will provide adequate short
circuit protection to the device. Care should still be taken
not to stress the device with a short at the output.
Power Dissipation
With the high output drive capability of the ISL55001, it
is possible to exceed the +150°C absolute maximum
junction temperature under certain load current
conditions. Therefore, it is important to calculate the
maximum junction temperature for an application to
determine if load conditions or package types need to be
modified to assure operation of the amplifier in a safe
operating area.
The maximum power dissipation allowed in a package is
determined according to Equation 1:
T JMAX – T AMAX
PD MAX = -------------------------------------------- JA
(EQ. 1)
Where:
• TJMAX = Maximum junction temperature
• TAMAX = Maximum ambient temperature
• JA = Thermal resistance of the package
The maximum power dissipation actually produced by an
IC is the total quiescent supply current times the total
power supply voltage, plus the power in the IC due to the
load, or: For sourcing use Equation 2:
n
PD MAX = (V S + – V S -   I SMAX +
  VS +
i=1
V OUTi
– V OUTi   -------------------R LOADi
(EQ. 2)
Page 8 of 12
ISL55001
For sinking use Equation 3:
n
  VOUTi – VS -  
PD MAX = (V S + – V S -   I SMAX +
i=1
capacitor from VS+ to GND will suffice. This same
capacitor combination should be placed at each supply
pin to ground if split supplies are to be used. In this case,
the VS- pin becomes the negative supply rail.
V OUTi
-------------------R LOADi
(EQ. 3)
Where:
Printed Circuit Board Layout
• ILOAD = Load current
For good AC performance, parasitic capacitance should
be kept to minimum. Use of wire wound resistors should
be avoided because of their additional series inductance.
Use of sockets should also be avoided if possible. Sockets
add parasitic inductance and capacitance that can result
in compromised performance. Minimizing parasitic
capacitance at the amplifier's inverting input pin is very
important. The feedback resistor should be placed very
close to the inverting input pin. Strip line design
techniques are recommended for the signal traces.
• n = number of amplifiers (n = 1 for ISL55001)
Application Circuits
By setting the two PDMAX equations (Equations 1, 2 or 3)
equal to each other, we can solve the output current and
RLOAD to avoid the device overheat.
Sallen-Key Low Pass Filter
• VS+ = Positive supply voltage
• VS- = Negative supply voltage
• ISMAX = Maximum quiescent supply current
• VOUT = Average output voltage of the application
• RLOAD = Load resistance tied to ground
Power Supply Bypassing Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance.
Lead lengths should be as short as possible. The power
supply pin must be well bypassed to reduce the risk of
oscillation. For normal single supply operation, where the
VS- pin is connected to the ground plane, a single 4.7µF
tantalum capacitor in parallel with a 0.1µF ceramic
1k C2
1nF
1
Q 
(1  K )
1nF
1k
1
R 1C 1 R 2 C 2
1nF
C1
V1
Again this useful filter benefits from the characteristics of
the ISL55001. The transfer function is very similar to the
low pass so only the results are presented (see
Figure 26).
wo 
C5
R2
Sallen-Key High Pass Filter
Holp  K
V2
5V
R1
A common and easy to implement filter taking advantage
of the wide bandwidth, low offset and low power
demands of the ISL55001. A derivation of the transfer
function is provided for convenience (see Figure 25).
+
V+
-
V-
VOUT
R 1C 1

R 2C 2
R 1C 2

R 2C 1
R 2C 2
R 1C 1
R7
1k
RB
RA
1k
1k
C5
1nF
V3
5V
K
4K
2
wo 
RC
2
Q 
4K
Holp 
FIGURE 25. SALLEN-KEY LOW PASS FILTER
FN6200 Rev 3.00
Nov 3, 2009
Page 9 of 12
ISL55001
V2
5V
Holp
C5
wo 
 K
R
1nF
R1
C1
V1
C2
1nF
1
C 1 R 2C
1k
R 1C 1

R 2C 2
(1  K )
+
V+
-
V-
R 1C 2

R 2C 1
R 2C 2
R 1C 1
VOUT
R7
1k
Equations simplify if we let
all components be equal R = C
RB
RA
1k
2
1
Q 
R2
1k
1nF
1
K
4 K
2
wo 
RC
2
Q 
4  K
Holp
1k
C5
1nF
V3
5V

FIGURE 26. SALLEN-KEY HIGH PASS FILTER
Differential Output Instrumentation
Amplifier
The addition of a third amplifier to the conventional three
amplifier instrumentation amplifier introduces the
benefits of differential signal realization, specifically the
advantage of using common-mode rejection to remove
e1
A1
+
-
R3
R3
A3
R2
+
R3
R3
e2
+
+
R3
+
R3
e o3 = –  1 + 2R 2  R G   e 1 – e 2 
e o4 =  1 + 2R 2  R G   e 1 – e 2 
e o = – 2  1 + 2R 2  R G   e 1 – e 2 
R3
A4
R2
A2
eo
RE
RG
coupled noise and ground potential errors inherent in
remote transmission. This configuration also provides
enhanced bandwidth, wider output swing and faster slew
rate than conventional three amplifier solutions with only
the cost of an additional amplifier and few resistors (see
Figure 27).
eo
2f C1 2
BW = -----------------A Di
A Di = – 2  1 + 2R 2  R G 
eo
R3
FIGURE 27. DIFFERENTIAL OUTPUT INSTRUMENTATION AMPLIFIER
FN6200 Rev 3.00
Nov 3, 2009
Page 10 of 12
ISL55001
Strain Gauge
to increasing strain, its resistance changes, resulting in
an imbalance in the bridge. A voltage variation from
the referenced high accuracy source is generated and
translated to the difference amplifier through the buffer
stage. This voltage difference as a function of the strain
is converted into an output voltage (see Figure 28).
The strain gauge is an ideal application to take
advantage of the moderate bandwidth and high
accuracy of the ISL55001. The operation of the circuit
is very straightforward. As the strain variable
component resistor in the balanced bridge is subjected
+V
VARIABLE
SUBJECT TO
V5 +
0V
-
R15
1k
1k
R16
1k
2
5V
-
C6
1nF
R17
1k
R18
1k
1k
+
V+
-
V-
VOUT
RL
(V1+V2+V3+V4)
1k
RF
1k
C12
1nF
+
V4
- 5V
FIGURE 28. STRAIN GAUGE AMPLIFIER
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For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6200 Rev 3.00
Nov 3, 2009
Page 11 of 12
ISL55001
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(1.27)
(0.60)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
FN6200 Rev 3.00
Nov 3, 2009
Page 12 of 12