Intel® Core™2 Extreme Quad-Core Mobile Processor and Intel

Intel® Core™2 Extreme Quad-Core
Mobile Processor and Intel® Core™2
Quad Mobile Processor on 45-nm
Process
Datasheet
For platforms based on Mobile Intel® 4 Series Express Chipset
Family
January 2009
Document Number: 320390-002
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Φ 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications
enabled for IntelÆ 64 architecture. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for
more information.
Enhanced Intel SpeedStep® Technology for specified units of this processor are available. See the Processor Spec Finder at http://
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Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check
with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
Φ
Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and, for some
uses, certain platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations
and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor.
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Copyright © 2008-2009, Intel Corporation. All rights reserved.
2
Datasheet
Contents
1
Introduction .............................................................................................................. 7
1.1
Terminology ....................................................................................................... 7
1.2
References ......................................................................................................... 9
2
Low Power Features ................................................................................................ 11
2.1
Clock Control and Low Power States .................................................................... 11
2.1.1 Core Low Power State Descriptions ........................................................... 13
2.1.1.1 Core C0 State........................................................................... 13
2.1.1.2 Core C1/AutoHALT Powerdown State ........................................... 13
2.1.1.3 Core C1/MWAIT Powerdown State ............................................... 14
2.1.1.4 Core C2 State........................................................................... 14
2.1.1.5 Core C3 State........................................................................... 14
2.1.1.6 Core C4 State........................................................................... 14
2.1.2 Package Low Power State Descriptions ...................................................... 14
2.1.2.1 Normal State............................................................................ 14
2.1.2.2 Stop-Grant State ...................................................................... 15
2.1.2.3 Stop-Grant Snoop State............................................................. 15
2.1.2.4 Sleep State .............................................................................. 15
2.1.2.5 Deep Sleep State ...................................................................... 16
2.1.2.6 Deeper Sleep State ................................................................... 16
2.2
Enhanced Intel SpeedStep® Technology .............................................................. 17
2.3
Extended Low Power States ................................................................................ 17
2.4
FSB Low Power Enhancements ............................................................................ 18
2.4.1 Dual Intel Dynamic Acceleration ............................................................... 19
2.5
Processor Power Status Indicator (PSI-2) Signal .................................................... 19
3
Electrical Specifications ........................................................................................... 21
3.1
Power and Ground Pins ...................................................................................... 21
3.2
Decoupling Guidelines ........................................................................................ 21
3.2.1 VCC Decoupling...................................................................................... 21
3.2.2 FSB AGTL+ Decoupling ........................................................................... 21
3.2.3 FSB Clock (BCLK[1:0]) and Processor Clocking ........................................... 21
3.3
Voltage Identification and Power Sequencing ........................................................ 22
3.4
Catastrophic Thermal Protection .......................................................................... 26
3.5
Reserved and Unused Pins.................................................................................. 26
3.6
FSB Frequency Select Signals (BSEL[2:0])............................................................ 27
3.7
FSB Signal Groups............................................................................................. 27
3.8
CMOS Signals ................................................................................................... 29
3.9
Maximum Ratings.............................................................................................. 29
3.10 Processor DC Specifications ................................................................................ 30
4
Package Mechanical Specifications and Pin Information .......................................... 37
4.1
Package Mechanical Specifications ....................................................................... 37
4.2
Processor Pinout and Pin List .............................................................................. 40
5
Thermal Specifications and Design Considerations .................................................. 67
5.1
Monitoring Die Temperature ............................................................................... 68
5.1.1 Thermal Diode ....................................................................................... 68
5.1.2 Intel® Thermal Monitor........................................................................... 69
5.1.3 Digital Thermal Sensor............................................................................ 71
5.2
PROCHOT# Signal Pin ........................................................................................ 72
Datasheet
3
Figures
1
2
3
4
5
6
7
8
9
Core Low Power States..............................................................................................12
Package Low Power States.........................................................................................13
PSI-2 Functionality Logic Diagram ..............................................................................19
Active VCC and ICC Loadline for Quad-Core Extreme Mobile Processor.............................33
Deeper Sleep VCC and ICC Loadline for Quad-Core Extreme Mobile Processor...................34
Quad-Core Processor Micro-FCPGA Package Drawing (Sheet 1 of 2) ................................38
Quad-Core Processor Micro-FCPGA Package Drawing (Sheet 2 of 2) ................................39
Quad-Core Processor Pinout (Top Package View, Left Side) ............................................40
Quad-Core Processor Pinout (Top Package View, Right Side) ..........................................41
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
4
References ............................................................................................................... 9
Coordination of Core Low Power States at the Package Level ..........................................13
Voltage Identification Definition ..................................................................................23
BSEL[2:0] Encoding for BCLK Frequency......................................................................27
FSB Pin Groups ........................................................................................................28
Processor Absolute Maximum Ratings..........................................................................29
Voltage and Current Specifications for the Quad-Core Extreme Mobile Processors..............30
Voltage and Current Specifications for the Quad-Core Mobile Processors ..........................31
AGTL+ Signal Group DC Specifications ........................................................................34
CMOS Signal Group DC Specifications..........................................................................36
Open Drain Signal Group DC Specifications ..................................................................36
Pin Listing by Pin Name .............................................................................................42
Pin Listing by Pin Number ..........................................................................................49
Signal Description.....................................................................................................57
New Pins for the Quad-Core Mobile Processor ...............................................................66
Processor Power Specifications ...................................................................................67
Thermal Diode Interface ............................................................................................69
Thermal Diode Parameters Using Transistor Model ........................................................69
Datasheet
Revision History
Document
Number
Revision
Number
320390
-001
320390
-002
Description
Initial Release
•
•
Date
August 2008
Updated Table 8: Added Q9000 information
Updated Table 16: Added Q9000 information
January 2009
§
Datasheet
5
6
Datasheet
Introduction
1
Introduction
The Intel® CoreTM2 Extreme quad-core processor and Intel® CoreTM2 quad processor
on 45-nanometer process technology for platforms based on Mobile Intel® 4 Series
Express Chipset Family is the first low-power, mobile quad-core processor based on the
Intel® Core™ microarchitecture.
In this document, the Intel Core 2 Extreme quad-core processor and Intel Core 2 quad
processor are referred to as the processor or quad-core processor and the Mobile Intel
4 Series Express Chipset is referred to as the (G)MCH.
Key features of the processor include:
• Quad-core mobile processor for mobile with enhanced performance
• Supports Intel® architecture with Intel® Wide Dynamic Execution
• Supports L1 cache-to-cache (C2C) transfer
• On-die, primary 32-kB instruction cache and 32-kB write-back data cache in each
core
• 12-MB second-level shared cache with Advanced Transfer Cache architecture
• Streaming SIMD extensions 2 (SSE2), streaming SIMD extensions 3 (SSE3),
supplemental streaming SIMD extensions 3 (SSSE3) and SSE4.1 instruction sets
• Processors are offered at 1066-MHz source-synchronous front side bus (FSB)
• Advanced power management features including Enhanced Intel SpeedStep®
Technology
• Digital thermal sensor (DTS)
• Intel® 64 architecture
• Supports Enhanced Intel® Virtualization Technology
• Supports PSI2 functionality
• Execute Disable Bit support for enhanced security
• Half ratio support (N/2) for core to bus ratio
1.1
Terminology
Term
Datasheet
Definition
#
A “#” symbol after a signal name refers to an active low signal, indicating a
signal is in the active state when driven to a low level. For example, when
RESET# is low, a reset has been requested. Conversely, when NMI is high,
a nonmaskable interrupt has occurred. In the case of signals where the
name does not imply an active state but describes part of a binary
sequence (such as address or data), the “#” symbol implies that the signal
is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]#
= “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).
Front Side Bus
(FSB)
Refers to the interface between the processor and system core logic (also
known as the chipset components).
AGTL+
Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+
signaling technology on some Intel processors.
7
Introduction
Term
8
Definition
Storage
Conditions
Refers to a non-operational state. The processor may be installed in a
platform, in a tray, or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor landings should not
be connected to any supply voltages, have any I/Os biased or receive any
clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device
removed from packaging material) the processor must be handled in
accordance with moisture sensitivity labeling (MSL) as indicated on the
packaging material.
Enhanced Intel
SpeedStep®
Technology
Technology that provides power management capabilities to laptops.
Processor Core
Processor core die with integrated L1 and L2 cache. All AC timing and signal
integrity specifications are at the pads of the processor core.
Execute Disable
Bit
The Execute Disable bit allows memory to be marked as executable or nonexecutable, when combined with a supporting operating system. If code
attempts to run in non-executable memory the processor raises an error to
the operating system. This feature can prevent some classes of viruses or
worms that exploit buffer overrun vulnerabilities and can thus help improve
the overall security of the system. See the Intel® 64 and IA-32
Architectures Software Developer's Manuals for more detailed information.
Intel® 64
Technology
64-bit memory extensions to the IA-32 architecture.
Intel®
Virtualization
Technology
Processor virtualization which when used in conjunction with Virtual
Machine Monitor software enables multiple, robust independent software
environments inside a single platform.
Half ratio support
(N/2) for Core to
Bus ratio
Quad-core processor supports the N/2 feature which allows having
fractional core to bus ratios. This feature provides the flexibility of having
more frequency options and be able to have products with smaller
frequency steps.
TDP
Thermal Design Power
VCC
The processor core power supply
VSS
The processor ground
Datasheet
Introduction
1.2
References
Material and concepts available in the following documents may be beneficial when
reading this document.
Table 1.
References
Document
Number1
Document
Intel® Core™2 Extreme Quad-Core Mobile Processor, Intel® Core™2
Quad Mobile Processor, Intel® Core™2 Extreme Mobile Processor, Intel®
Core™2 Duo Mobile Processor, and Intel® Core™2 Solo Mobile
Processors on 45-nm Process Specification Update
320121
Mobile Intel® 4 Series Express Chipset Family Datasheet
320122
Mobile Intel® 4 Series Express Chipset Family Specification Update
320123
Intel® I/O Controller Hub 9 (ICH9)/ I/O Controller Hub 9M (ICH9M)
Datasheet
316972
Intel® I/O Controller Hub 9 (ICH9)/ I/O Controller Hub 9M (ICH9M)
Specification Update
316973
Intel® 64 and IA-32 Architectures Software Developer's Manuals
See http://
www.intel.com/
products/processor/
manuals/index.htm
Volume 1: Basic Architecture
253665
Volume 2A: Instruction Set Reference, A-M
253666
Volume 2B: Instruction Set Reference, N-Z
253667
Volume 3A: System Programming Guide
253668
Volume 3B: System Programming Guide
253669
NOTES:Contact your Intel representative for the latest revision and document number of this
document.
§
Datasheet
9
Introduction
10
Datasheet
Low Power Features
2
Low Power Features
2.1
Clock Control and Low Power States
The processor supports low power states both at the individual core level and the
package level for optimal power management.
A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, and C4 low
power states. When all cores coincide in a common core low power state, the central
power management logic ensures the entire processor enters the respective package
low power state by initiating a P_LVLx (P_LVL2, P_LVL3, P_LVL4) I/O read to the
(G)MCH.
The processor implements two software interfaces for requesting low power states:
MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI P_BLK
register block mapped in the processor’s I/O address space. The P_LVLx I/O reads are
converted to equivalent MWAIT C-state requests inside the processor and do not
directly result in I/O reads on the processor FSB. The P_LVLx I/O Monitor address does
not need to be set up before using the P_LVLx I/O read interface. The sub-state hints
used for each P_LVLx read can be configured through the IA32_MISC_ENABLES model
specific register (MSR).
If a core encounters a GMCH break event while STPCLK# is asserted, it asserts the
PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to system
logic that individual cores should return to the C0 state and the processor should return
to the Normal state.
Figure 1 shows the core low power states and Figure 2 shows the package low power
states for the processor. Table 2 maps the core low power states to package low power
states.
Datasheet
11
Low Power Features
Figure 1.
Core Low Power States
Stop
Grant
STPCLK#
deasserted
STPCLK#
asserted
STPCLK#
deasserted
C1/MWAIT
Core State
Break
STPCLK#
asserted
STPCLK#
STPCLK#
deasserted
deasserte
C1/Auto
STPCLK#
asserted
HLT instruction
Halt break
MWAIT(C1)
C0
P_LVL2 or
MWAIT(C2)
Core State
Break
P_LVL4 or
MWAIT(C4)
C4+
Halt
Core State
Break
Core State
Break
P_LVL3 or
MWAIT(C3)
C2+
C3+
Halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted)
+ __ STPCLK# assertion and de-assertion have no effect if a core is in C2, C3 or C4.
12
Datasheet
Low Power Features
Figure 2.
Package Low Power States
STPCLK# asserted
SLP# asserted
Stop
Grant
Normal
DPSLP# asserted
SLP# desserted
STPCLK# desserted
Snoop
serviced
DPRSTP# asserted
Deep
Sleep
Sleep
DPSLP# deasserted
Deeper
Sleep
DPRSTP# desserted
Snoop
occurs
Stop Grant
Snoop
Table 2.
Coordination of Core Low Power States at the Package Level
Package State
Core1 State
Core0 State
C0
C11
C2
C3
C4
C0
Normal
Normal
Normal
Normal
Normal
C1
Normal
Normal
Normal
Normal
Normal
C2
Normal
Normal
Stop-Grant
Stop-Grant
Stop-Grant
C3
Normal
Normal
Stop-Grant
Deep Sleep
Deep Sleep
C4
Normal
Normal
Stop-Grant
Deep Sleep
Deeper Sleep
1
NOTE:
1.
AutoHALT or MWAIT/C1.
2.1.1
Core Low Power State Descriptions
2.1.1.1
Core C0 State
This is the normal operating state for cores in the processor.
2.1.1.2
Core C1/AutoHALT Powerdown State
C1/AutoHALT is a low power state entered when a core executes the HALT instruction.
The processor core will transition to the C0 state upon occurrence of SMI#, INIT#,
LINT[1:0] (NMI, INTR), or FSB interrupt messages. RESET# will cause the processor to
immediately initialize itself.
A System Management Interrupt (SMI) handler will return execution to either Normal
state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Architectures
Software Developer's Manuals, Volume 3A/3B: System Programmer's Guide for more
information.
The system can generate a STPCLK# while the processor is in the AutoHALT
Powerdown state. When the system deasserts the STPCLK# interrupt, the processor
will return execution to the HALT state.
Datasheet
13
Low Power Features
While in AutoHALT Powerdown state, the due core processor will process bus snoops
and snoops from the other core. The processor core will enter a snoopable sub-state
(not shown in Figure 1) to process the snoop and then return to the AutoHALT
Powerdown state.
2.1.1.3
Core C1/MWAIT Powerdown State
C1/MWAIT is a low power state entered when the processor core executes the
MWAIT(C1) instruction. Processor behavior in the MWAIT state is identical to the
AutoHALT state except that Monitor events can cause the processor core to return to
the C0 state. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals,
Volume 2A: Instruction Set Reference, A-M and Volume 2B: Instruction Set Reference,
N-Z, for more information.
2.1.1.4
Core C2 State
Individual cores of the quad-core processor can enter the C2 state by initiating a
P_LVL2 I/O read to the P_BLK or an MWAIT(C2) instruction, but the processor will not
issue a Stop-Grant Acknowledge special bus cycle unless the STPCLK# pin is also
asserted.
While in the C2 state, the quad-core processor will process bus snoops and snoops
from the other core. The processor core will enter a snoopable sub-state (not shown in
Figure 1) to process the snoop and then return to the C2 state.
2.1.1.5
Core C3 State
Individual cores of the quad-core processor can enter the C3 state by initiating a
P_LVL3 I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering C3, the
processor core flushes the contents of its L1 caches into the processor’s L2 cache.
Except for the caches, the processor core maintains all its architectural states in the C3
state. The Monitor remains armed if it is configured. All of the clocks in the processor
core are stopped in the C3 state.
Because the core’s caches are flushed the processor keeps the core in the C3 state
when the processor detects a snoop on the FSB or when the other core of the dual-core
die of quad-core processor accesses cacheable memory. The processor core will
transition to the C0 state upon occurrence of a Monitor event, SMI#, INIT#, LINT[1:0]
(NMI, INTR), or FSB interrupt message. RESET# will cause the processor core to
immediately initialize itself.
2.1.1.6
Core C4 State
Individual cores of the quad-core processor can enter the C4 state by initiating a
P_LVL4 or P_LVL5 I/O read to the P_BLK or an MWAIT(C4) instruction. The processor
core behavior in the C4 state is nearly identical to the behavior in the C3 state. The
only difference is that if all processor cores are in C4, the central power management
logic will request that the entire processor enter the Deeper Sleep package low power
state (see Section 2.1.2.6).
2.1.2
Package Low Power State Descriptions
2.1.2.1
Normal State
This is the normal operating state for the processor. The processor remains in the
Normal state when at least one of its cores is in the C0, C1/AutoHALT, or C1/MWAIT
state.
14
Datasheet
Low Power Features
2.1.2.2
Stop-Grant State
When the STPCLK# pin is asserted, each core of the quad-core processor enters the
Stop-Grant state within 20 bus clocks after the response phase of the processor-issued
Stop-Grant Acknowledge special bus cycle. Processor cores that are already in the C2,
C3, or C4 state remain in their current low power state. When the STPCLK# pin is
deasserted, each core returns to its previous core low power state.
Since the AGTL+ signal pins receive power from the FSB, these pins should not be
driven (allowing the level to return to VCCP) for minimum power drawn by the
termination resistors in this state. In addition, all other input pins on the FSB should be
driven to the inactive state.
RESET# causes the processor to immediately initialize itself, but the processor will stay
in Stop-Grant state. When RESET# is asserted by the system, the STPCLK#, SLP#,
DPSLP#, and DPRSTP# pins must be deasserted prior to RESET# deassertion as per AC
Specification T45. When re-entering the Stop-Grant state from the Sleep state,
STPCLK# should be deasserted after the deassertion of SLP# as per AC Specification
T75.
While in Stop-Grant state, the processor will service snoops and latch interrupts
delivered on the FSB. The processor will latch SMI#, INIT# and LINT[1:0] interrupts
and will service only one of each upon return to the Normal state.
The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# will be
asserted if there is any pending interrupt or Monitor event latched within the processor.
Pending interrupts that are blocked by the EFLAGS. IF bit being clear will still cause
assertion of PBE#. Assertion of PBE# indicates to system logic that the entire processor
should return to the Normal state.
A transition to the Stop-Grant Snoop state occurs when the processor detects a snoop
on the FSB (see Section 2.1.2.3). A transition to the Sleep state (see Section 2.1.2.4)
occurs with the assertion of the SLP# signal.
2.1.2.3
Stop-Grant Snoop State
The processor responds to snoop or interrupt transactions on the FSB while in StopGrant state by entering the Stop-Grant Snoop state. The processor will stay in this
state until the snoop on the FSB has been serviced (whether by the processor or
another agent on the FSB) or the interrupt has been latched. The processor returns to
the Stop-Grant state once the snoop has been serviced or the interrupt has been
latched.
2.1.2.4
Sleep State
The Sleep state is a low power state in which the processor maintains its context,
maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is
entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP#
pin should only be asserted when the processor is in the Stop-Grant state. SLP#
assertions while the processor is not in the Stop-Grant state is out of specification and
may result in unapproved operation.
In the Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals (with the exception of
SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep
state. Snoop events that occur while in Sleep state or during a transition into or out of
Sleep state will cause unpredictable behavior. Any transition on an input signal before
the processor has returned to the Stop-Grant state will result in unpredictable behavior.
Datasheet
15
Low Power Features
If RESET# is driven active while the processor is in the Sleep state, and held active as
specified in the RESET# pin specification, then the processor will reset itself, ignoring
the transition through the Stop-Grant state. If RESET# is driven active while the
processor is in the Sleep state, the SLP# and STPCLK# signals should be deasserted
immediately after RESET# is asserted to ensure the processor correctly executes the
Reset sequence.
While in the Sleep state, the processor is capable of entering an even lower power
state, the Deep Sleep state, by asserting the DPSLP# pin (See Section 2.1.2.5). While
the processor is in the Sleep state, the SLP# pin must be deasserted if another
asynchronous FSB event needs to occur.
2.1.2.5
Deep Sleep State
The Deep Sleep state is entered through assertion of the DPSLP# pin while in the Sleep
state. BCLK may be stopped during the Deep Sleep state for additional platform-level
power savings. BCLK stop/restart timings on appropriate GMCH-based platforms with
the CK505 clock chip are as follows:
• Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs
of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.
• Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels
within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK
periods.
To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be restarted after DPSLP# deassertion as described above. A period of 15 microseconds (to
allow for PLL stabilization) must occur before the processor can be considered to be in
the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter
the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop
transactions or latching interrupt signals. No transitions of signals are allowed on the
FSB while the processor is in Deep Sleep state. When the processor is in Deep Sleep
state, it will not respond to interrupts or snoop transactions. Any transition on an input
signal before the processor has returned to Stop-Grant state will result in unpredictable
behavior.
2.1.2.6
Deeper Sleep State
The Deeper Sleep state is similar to the Deep Sleep state but further reduces core
voltage levels. One of the potential lower core voltage levels is achieved by entering the
base Deeper Sleep state. The Deeper Sleep state is entered through assertion of the
DPRSTP# pin while in the Deep Sleep state.
In response to entering Deeper Sleep, the processor drives the VID code corresponding
to the Deeper Sleep core voltage on the VID[6:0] pins.
Exit from Deeper Sleep state is initiated by DPRSTP# deassertion when either core
requests a core state other than C4 or either core requests a processor performance
state other than the lowest operating point.
16
Datasheet
Low Power Features
2.2
Enhanced Intel SpeedStep® Technology
The processor features Enhanced Intel SpeedStep Technology. Following are the key
features of Enhanced Intel SpeedStep Technology:
• Multiple voltage and frequency operating points provide optimal performance at the
lowest power.
• Voltage and frequency selection is software-controlled by writing to processor
MSRs:
— If the target frequency is higher than the current frequency, VCC is ramped up
in steps by placing new values on the VID pins, and the PLL then locks to the
new frequency.
— If the target frequency is lower than the current frequency, the PLL locks to the
new frequency and the VCC is changed through the VID pin mechanism.
— Software transitions are accepted at any time. If a previous transition is in
progress, the new transition is deferred until the previous transition completes.
• The processor controls voltage ramp rates internally to ensure glitch-free
transitions.
• Low transition latency and large number of transitions possible per second:
— Processor core (including L2 cache) is unavailable for up to 10 ms during the
frequency transition.
— The bus protocol (BNR# mechanism) is used to block snooping.
• Improved Intel® Thermal Monitor mode:
— When the on-die thermal sensor indicates that the die temperature is too high
the processor can automatically perform a transition to a lower frequency and
voltage specified in a software-programmable MSR.
— The processor waits for a fixed time period. If the die temperature is down to
acceptable levels, an up-transition to the previous frequency and voltage point
occurs.
— An interrupt is generated for the up and down Intel Thermal Monitor transitions
enabling better system-level thermal management.
• Enhanced thermal management features:
— Digital Thermal Sensor and Out of Specification detection.
— Intel Thermal Monitor 1 (TM1) in addition to Intel Thermal Monitor 2 (TM2) in
case of unsuccessful TM2 transition.
— Quad core thermal management synchronization.
Each core in the quad-core processor implements an independent MSR for controlling
Enhanced Intel SpeedStep Technology, but all cores must operate at the same voltage.
The processor has performance state coordination logic to resolve frequency and
voltage requests from the four cores into a single voltage request for the package as a
whole. If all cores request the same frequency and voltage, then the processor will
transition to the requested common frequency and voltage.
2.3
Extended Low Power States
Extended low power states (CXE) optimize for power by forcibly reducing the
performance state of the processor when it enters a package low power state. Instead
of directly transitioning into the package low power low power state, the enhanced
package low power state first reduces the performance state of the processor by
performing an Enhanced Intel SpeedStep Technology transition down to the lowest
Datasheet
17
Low Power Features
operating point. Upon receiving a break event from the package low power state,
control will be returned to software while an Enhanced Intel SpeedStep Technology
transition up to the initial operating point occurs. The advantage of this feature is that it
significantly reduces leakage while in the Stop-Grant and Deeper Sleep states.
Note:
Long-term reliability cannot be assured unless all the Extended Low Power States are
enabled.
The processor implements two software interfaces for requesting enhanced package
low power states: MWAIT instruction extensions with sub-state hints and via BIOS by
configuring IA32_MISC_ENABLES MSR bits to automatically promote package low
power states to enhanced package low power states.
Caution:
Extended Stop-Grant must be enabled via the BIOS for the processor to
remain within specification. As processor technology changes, enabling the
extended low power states becomes increasingly crucial when building computer
systems. Maintaining the proper BIOS configuration is key to reliable, long-term
system operation. Not complying to this guideline may affect the long-term reliability of
the processor.
Caution:
Enhanced Intel SpeedStep Technology transitions are multistep processes
that require clocked control. These transitions cannot occur when the processor is in
the Sleep or Deep Sleep package low power states since processor clocks are not active
in these states. Extended Deeper Sleep is an exception to this rule when the Hard C4E
configuration is enabled in the IA32_MISC_ENABLES MSR. This Extended Deeper Sleep
state configuration will lower core voltage to the Deeper Sleep level while in Deeper
Sleep and, upon exit, will automatically transition to the lowest operating voltage and
frequency to reduce snoop service latency. The transition to the lowest operating point
or back to the original software-requested point may not be instantaneous.
Furthermore, upon very frequent transitions between active and idle states, the
transitions may lag behind the idle state entry resulting in the processor either
executing for a longer time at the lowest operating point or running idle at a high
operating point. Observations and analyses show this behavior should not significantly
impact total power savings or performance score while providing power benefits in
most other cases.
2.4
FSB Low Power Enhancements
The processor incorporates FSB low power enhancements:
• BPRI# control for address and control input buffers
• Dynamic Bus Parking
• Dynamic On-Die Termination disabling
• Low VCCP (I/O termination voltage)
The processor incorporates the DPWR# signal that controls the data bus input buffers
on the processor. The DPWR# signal disables the buffers when not used and activates
them only when data bus activity occurs, resulting in significant power savings with no
performance impact. BPRI# control also allows the processor address and control input
buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows
a reciprocal power reduction in GMCH address and control input buffers when the
processor deasserts its BR0# pin. The On-Die Termination on the processor FSB buffers
is disabled when the signals are driven low, resulting in additional power savings. The
low I/O termination voltage is on a dedicated voltage plane independent of the core
voltage, enabling low I/O switching power at all times.
18
Datasheet
Low Power Features
2.4.1
Dual Intel Dynamic Acceleration
The processor supports Dual Intel Dynamic Acceleration. For any two cores in the
quad-core processor, the Dual Intel Dynamic Acceleration feature allows one core to
operate at a higher frequency point while the other core is inactive and the operating
system requests increased performance. Thus, quad-core processor could enter Dual
Intel Dynamic Acceleration when two cores are idle and the other two are active. This
higher frequency is called the opportunistic frequency and the maximum rated
operating frequency is the ensured frequency.
Dual Intel Dynamic Acceleration enabling requires exposure, via BIOS, of the
opportunistic frequency as the highest ACPI P state
2.5
Processor Power Status Indicator (PSI-2) Signal
The processor incorporates the PSI# signal that is asserted when the processor is in a
reduced power consumption state. PSI# can be used to improve intermediate and light
load efficiency of the voltage regulator, resulting in platform power savings and
extended battery life. The algorithm that the processor uses for determining when to
assert PSI# is different from the algorithm used in previous mobile processors.
PSI-2 functionality improves overall voltage regulator efficiency over a wide power
range based on the C-state and P-state of the four cores. The combined C-state of all
cores are used to dynamically predict processor power. The PSI-2 functionality logic
diagram is shown in Figure 3.
Figure 3.
PSI-2 Functionality Logic Diagram
§
Datasheet
19
Low Power Features
20
Datasheet
Electrical Specifications
3
Electrical Specifications
3.1
Power and Ground Pins
For clean, on-chip power distribution, the processor will have a large number of VCC
(power) and VSS (ground) inputs. All power pins must be connected to VCC power
planes while all VSS pins must be connected to system ground planes. Use of multiple
power and ground planes is recommended to reduce I*R drop. Refer to the platform
design guides for more details. The processor VCC pins must be supplied the voltage
determined by the VID (Voltage ID) pins.
3.2
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large average current swings between low and full power states.
This may cause voltages on power planes to sag below their minimum values if bulk
decoupling is not adequate. Larger bulk storage, such as electrolytic capacitors, supply
current during longer lasting changes in current demand by the component, such as
coming out of an idle condition. Similarly, they act as a storage well for current when
entering an idle condition from a running condition. Care must be taken in the board
design to ensure that the voltage provided to the processor remains within the
specifications listed in Table 3. Failure to do so may result in timing violations or
reduced lifetime of the component.
3.2.1
VCC Decoupling
VCC regulator solutions need to provide bulk capacitance with a low Effective Series
Resistance (ESR) and keep a low interconnect resistance from the regulator to the
socket. Bulk decoupling for the large current swings when the part is powering on, or
entering/exiting low-power states, should be provided by the voltage regulator solution
depending on the specific system design.
3.2.2
FSB AGTL+ Decoupling
The processors integrate signal termination on the die as well as incorporate high
frequency decoupling capacitance on the processor package. Decoupling must also be
provided by the system motherboard for proper AGTL+ bus operation.
3.2.3
FSB Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous-generation processors, the processor core frequency is a
multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its
default ratio at manufacturing.The processor uses a differential clocking
implementation.
Datasheet
21
Electrical Specifications
3.3
Voltage Identification and Power Sequencing
The processor uses seven voltage identification pins,VID[6:0], to support automatic
selection of power supply voltages. The VID pins for the processor are CMOS outputs
driven by the processor VID circuitry. Table 3 specifies the voltage level corresponding
to the state of VID[6:0]. A 1 in the table refers to a high-voltage level and a 0 refers to
a low-voltage level.
22
Datasheet
Electrical Specifications
Table 3.
Datasheet
Voltage Identification Definition (Sheet 1 of 4)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VCC (V)
0
0
0
0
0
0
0
1.5000
0
0
0
0
0
0
1
1.4875
0
0
0
0
0
1
0
1.4750
0
0
0
0
0
1
1
1.4625
0
0
0
0
1
0
0
1.4500
0
0
0
0
1
0
1
1.4375
0
0
0
0
1
1
0
1.4250
0
0
0
0
1
1
1
1.4125
0
0
0
1
0
0
0
1.4000
0
0
0
1
0
0
1
1.3875
0
0
0
1
0
1
0
1.3750
0
0
0
1
0
1
1
1.3625
0
0
0
1
1
0
0
1.3500
0
0
0
1
1
0
1
1.3375
0
0
0
1
1
1
0
1.3250
0
0
0
1
1
1
1
1.3125
0
0
1
0
0
0
0
1.3000
0
0
1
0
0
0
1
1.2875
0
0
1
0
0
1
0
1.2750
0
0
1
0
0
1
1
1.2625
0
0
1
0
1
0
0
1.2500
0
0
1
0
1
0
1
1.2375
0
0
1
0
1
1
0
1.2250
0
0
1
0
1
1
1
1.2125
0
0
1
1
0
0
0
1.2000
0
0
1
1
0
0
1
1.1875
0
0
1
1
0
1
0
1.1750
0
0
1
1
0
1
1
1.1625
0
0
1
1
1
0
0
1.1500
0
0
1
1
1
0
1
1.1375
0
0
1
1
1
1
0
1.1250
0
0
1
1
1
1
1
1.1125
0
1
0
0
0
0
0
1.1000
0
1
0
0
0
0
1
1.0875
0
1
0
0
0
1
0
1.0750
0
1
0
0
0
1
1
1.0625
0
1
0
0
1
0
0
1.0500
23
Electrical Specifications
Table 3.
24
Voltage Identification Definition (Sheet 2 of 4)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VCC (V)
0
1
0
0
1
0
1
1.0375
0
1
0
0
1
1
0
1.0250
0
1
0
0
1
1
1
1.0125
0
1
0
1
0
0
0
1.0000
0
1
0
1
0
0
1
0.9875
0
1
0
1
0
1
0
0.9750
0
1
0
1
0
1
1
0.9625
0
1
0
1
1
0
0
0.9500
0
1
0
1
1
0
1
0.9375
0
1
0
1
1
1
0
0.9250
0
1
0
1
1
1
1
0.9125
0
1
1
0
0
0
0
0.9000
0
1
1
0
0
0
1
0.8875
0
1
1
0
0
1
0
0.8750
0
1
1
0
0
1
1
0.8625
0
1
1
0
1
0
0
0.8500
0
1
1
0
1
0
1
0.8375
0
1
1
0
1
1
0
0.8250
0
1
1
0
1
1
1
0.8125
0
1
1
1
0
0
0
0.8000
0
1
1
1
0
0
1
0.7875
0
1
1
1
0
1
0
0.7750
0
1
1
1
0
1
1
0.7625
0
1
1
1
1
0
0
0.7500
0
1
1
1
1
0
1
0.7375
0
1
1
1
1
1
0
0.7250
0
1
1
1
1
1
1
0.7125
1
0
0
0
0
0
0
0.7000
1
0
0
0
0
0
1
0.6875
1
0
0
0
0
1
0
0.6750
1
0
0
0
0
1
1
0.6625
1
0
0
0
1
0
0
0.6500
1
0
0
0
1
0
1
0.6375
1
0
0
0
1
1
0
0.6250
1
0
0
0
1
1
1
0.6125
1
0
0
1
0
0
0
0.6000
1
0
0
1
0
0
1
0.5875
1
0
0
1
0
1
0
0.5750
Datasheet
Electrical Specifications
Table 3.
Datasheet
Voltage Identification Definition (Sheet 3 of 4)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VCC (V)
1
0
0
1
0
1
1
0.5625
1
0
0
1
1
0
0
0.5500
1
0
0
1
1
0
1
0.5375
1
0
0
1
1
1
0
0.5250
1
0
0
1
1
1
1
0.5125
1
0
1
0
0
0
0
0.5000
1
0
1
0
0
0
1
0.4875
1
0
1
0
0
1
0
0.4750
1
0
1
0
0
1
1
0.4625
1
0
1
0
1
0
0
0.4500
1
0
1
0
1
0
1
0.4375
1
0
1
0
1
1
0
0.4250
1
0
1
0
1
1
1
0.4125
1
0
1
1
0
0
0
0.4000
1
0
1
1
0
0
1
0.3875
1
0
1
1
0
1
0
0.3750
1
0
1
1
0
1
1
0.3625
1
0
1
1
1
0
0
0.3500
1
0
1
1
1
0
1
0.3375
1
0
1
1
1
1
0
0.3250
1
0
1
1
1
1
1
0.3125
1
1
0
0
0
0
0
0.3000
1
1
0
0
0
0
1
0.2875
1
1
0
0
0
1
0
0.2750
1
1
0
0
0
1
1
0.2625
1
1
0
0
1
0
0
0.2500
1
1
0
0
1
0
1
0.2375
1
1
0
0
1
1
0
0.2250
1
1
0
0
1
1
1
0.2125
1
1
0
1
0
0
0
0.2000
1
1
0
1
0
0
1
0.1875
1
1
0
1
0
1
0
0.1750
1
1
0
1
0
1
1
0.1625
1
1
0
1
1
0
0
0.1500
1
1
0
1
1
0
1
0.1375
1
1
0
1
1
1
0
0.1250
1
1
0
1
1
1
1
0.1125
1
1
1
0
0
0
0
0.1000
25
Electrical Specifications
Table 3.
3.4
Voltage Identification Definition (Sheet 4 of 4)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VCC (V)
1
1
1
0
0
0
1
0.0875
1
1
1
0
0
1
0
0.0750
1
1
1
0
0
1
1
0.0625
1
1
1
0
1
0
0
0.0500
1
1
1
0
1
0
1
0.0375
1
1
1
0
1
1
0
0.0250
1
1
1
0
1
1
1
0.0125
1
1
1
1
0
0
0
0.0000
1
1
1
1
0
0
1
0.0000
1
1
1
1
0
1
0
0.0000
1
1
1
1
0
1
1
0.0000
1
1
1
1
1
0
0
0.0000
1
1
1
1
1
0
1
0.0000
1
1
1
1
1
1
0
0.0000
1
1
1
1
1
1
1
0.0000
Catastrophic Thermal Protection
The processor supports the THERMTRIP# signal for catastrophic thermal protection. An
external thermal sensor should also be used to protect the processor and the system
against excessive temperatures. Even with the activation of THERMTRIP#, which halts
all processor internal clocks and activity, leakage current can be high enough that the
processor cannot be protected in all conditions without the removal of power to the
processor. If the external thermal sensor detects a catastrophic processor temperature
of 125°C (maximum), or if the THERMTRIP# signal is asserted, the VCC supply to the
processor must be turned off within 500 ms to prevent permanent silicon damage due
to thermal runaway of the processor. THERMTRIP# functionality is not ensured if the
PWRGOOD signal is not asserted.
3.5
Reserved and Unused Pins
All RESERVED (RSVD) pins must remain unconnected. Connection of these pins to VCC,
VSS, or to any other signal (including each other) can result in component malfunction
or incompatibility with future processors. See Section 4.2 for a pin listing of the
processor and the location of all RSVD pins.
For reliable operation, always connect unused inputs or bidirectional signals to an
appropriate signal level. Unused active low AGTL+ inputs may be left as no-connects if
AGTL+ termination is provided on the processor silicon. Unused active high inputs
should be connected through a resistor to ground (VSS). Unused outputs can be left
unconnected. The TEST1,TEST2,TEST3,TEST4,TEST5,TEST6,TEST7 pins are used for
test purposes internally and can be left as “No Connects”.
26
Datasheet
Electrical Specifications
3.6
FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]). These signals should be connected to the clock chip and the appropriate
chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in Table 4.
Table 4.
BSEL[2:0] Encoding for BCLK Frequency
BSEL[2]
3.7
BSEL[1]
BSEL[0]
BCLK Frequency
L
L
L
266 MHz
L
L
H
RESERVED
L
H
H
RESERVED
L
H
L
RESERVED
H
H
L
RESERVED
H
H
H
RESERVED
H
L
H
RESERVED
H
L
L
RESERVED
FSB Signal Groups
The FSB signals have been combined into groups by buffer type in the following
sections. AGTL+ input signals have differential input buffers that use GTLREF as a
reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input
group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers
to the AGTL+ output group as well as the AGTL+ I/O group when driving.
With the implementation of a source-synchronous data bus, two sets of timing
parameters need to be specified. One set is for common clock signals, which are
dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.), and the second
set is for the source-synchronous signals which are relative to their respective strobe
lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are
still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle. Table 5 identifies which signals are common clock, source synchronous,
and asynchronous.
Datasheet
27
Electrical Specifications
Table 5.
FSB Pin Groups
Signal Group
Signals1
Type
AGTL+ Common Clock
Input
Synchronous
to BCLK[1:0]
BPRI#, DEFER#, PREQ#5, RESET#, RS[2:0]#,
TRDY#
AGTL+ Common Clock I/O
Synchronous
to BCLK[1:0]
ADS#, BNR#, BPM[3:0]#3, BPM_2[3:0]#3, BR0#,
BR1#, DBSY#, DRDY#, HIT#, HITM#, LOCK#,
PRDY#3, DPWR#
Signals
AGTL+ Source
Synchronous I/O
Synchronous
to assoc.
strobe
Associated Strobe
REQ[4:0]#, A[16:3]#
ADSTB[0]#
A[35:17]#
ADSTB[1]#
D[15:0]#, DINV0#
DSTBP0#, DSTBN0#
D[31:16]#, DINV1#
DSTBP1#, DSTBN1#
D[47:32]#, DINV2#
DSTBP2#, DSTBN2#
D[63:48]#, DINV3#
DSTBP3#, DSTBN3#
AGTL+ Strobes
Synchronous
to BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
CMOS Input
Asynchronous
A20M#, DPRSTP#, DPSLP#, IGNNE#, INIT#,
LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#,
STPCLK#
Open Drain Output
Asynchronous
FERR#, IERR#, THERMTRIP#
Open Drain I/O
Asynchronous
PROCHOT#4
CMOS Output
Asynchronous
PSI#, VID[6:0], BSEL[2:0]
CMOS Input
Synchronous
to TCK
TCK, TDI, TDI_M, TMS, TRST#
Open Drain Output
Synchronous
to TCK
TDO, TDO_M
FSB Clock
Clock
Power/Other
BCLK[1:0]
COMP[3:0], DBR#2, GTLREF, GTLREF_2, RSVD,
TEST2, TEST1, THERMDA, THERMDA_2,
THERMDC, THERMDC_2, VCC, VCCA, VCCP,
VCC_SENSE, VSS, VSS_SENSE
NOTES:
1.
Refer to Chapter 4 for signal descriptions and termination requirements.
2.
In processor systems where there is no debug port implemented on the system board,
these signals are used to support a debug port interposer. In systems with the debug port
implemented on the system board, these signals are no connects.
3.
BPM[2:1]#,BPM_2[1]# and PRDY# are AGTL+ output-only signals.
4.
PROCHOT# signal type is open drain output and CMOS input.
5.
On-die termination differs from other AGTL+ signals.
28
Datasheet
Electrical Specifications
3.8
CMOS Signals
CMOS input signals are shown in Table 5. Legacy output FERR#, IERR# and other nonAGTL+ signals (THERMTRIP# and PROCHOT#) use Open Drain output buffers. These
signals do not have setup or hold time specifications in relation to BCLK[1:0]. However,
all of the CMOS signals are required to be asserted for more than four BCLKs for the
processor to recognize them. See Section 3.10 for DC specifications for the CMOS
signal groups.
3.9
Maximum Ratings
Table 6 specifies absolute maximum and minimum ratings only and these lie outside
the functional limits of the processor. Only within functional operation limits,
functionality and long-term reliability can be expected.
At conditions outside functional operation condition limits, but within absolute
maximum and minimum ratings, neither functionality nor long-term reliability can be
expected. If a device is returned to conditions within functional operation limits after
having been subjected to conditions outside these limits, but within the absolute
maximum and minimum ratings, the device may be functional, but with its lifetime
degraded.
At conditions exceeding the absolute maximum and minimum ratings, neither
functionality nor long-term reliability can be expected. Moreover, if a device is
subjected to these conditions for any length of time then, when returned to conditions
within the functional operating condition limits, it will either not function or its reliability
will be severely degraded.
Although the processor contains protective circuitry to resist damage from static
electric discharge, precautions should always be taken to avoid high static voltages or
electric fields.
Table 6.
Processor Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Notes1,5
-40
85
°C
2,3,4
TSTORAGE
Processor Storage Temperature
VCC
Any Processor Supply Voltage with Respect
to VSS
-0.3
1.45
V
VinAGTL+
AGTL+ Buffer DC Input Voltage with
Respect to VSS
-0.1
1.45
V
VinAsynch_CMOS
CMOS Buffer DC Input Voltage with Respect
to VSS
-0.1
1.45
V
NOTES:
1.
For functional operation, all processor electrical, signal quality, mechanical and thermal
specifications must be satisfied.
2.
Storage temperature is applicable to storage conditions only. In this scenario, the
processor must not receive a clock, and no lands can be connected to a voltage bias.
Storage within these limits will not affect the long-term reliability of the device. For
functional operation, please refer to the processor case temperature specifications.
3.
This rating applies to the processor and does not include any tray or packaging.
4.
Failure to adhere to this specification can affect the long-term reliability of the processor.
Datasheet
29
Electrical Specifications
3.10
Processor DC Specifications
The processor DC specifications in this section are defined at the processor
core (pads) unless noted otherwise. See Table 5 for the pin signal definitions and
signal pin assignments.
The table below lists the DC specifications for the processor and are valid only while
meeting specifications for junction temperature, clock frequency, and input voltages.
The Highest Frequency Mode (HFM) and Lowest Frequency Mode (LFM) refer to the
highest and lowest core operating frequencies supported on the processor. Active mode
load line specifications apply in all states except in the Deep Sleep and Deeper Sleep
states. VCC,BOOT is the default voltage driven by the voltage regulator at power up in
order to set the VID values. Unless specified otherwise, all specifications for the
processor are at TJ = 100°C. Read all notes associated with each parameter.
Table 7.
Voltage and Current Specifications for the Quad-Core Extreme Mobile
Processors (Sheet 1 of 2)
Symbol
Parameter
Typ
Max
Unit
Notes
VCCDAM
VCC in Intel Dynamic Acceleration
Technology Mode
0.90
—
1.30
V
1, 2
VCCHFM
VCC at Highest Frequency Mode (HFM)
0.90
—
1.25
V
1, 2
VCCLFM
VCC at Lowest Frequency Mode (LFM)
0.85
—
1.10
V
1, 2
VCC,BOOT
Default VCC Voltage for Initial Power
Up
—
1.20
V
2, 5, 6
VCCP
AGTL+ Termination Voltage
1.00
1.05
1.10
VCCA
PLL Supply Voltage
1.425
1.5
1.575
V
VCCDPRSLP
VCC at Deeper Sleep
0.65
—
0.85
V
1, 2
ICCDES
ICC for Processors Recommended
Design Target
—
—
64
A
5, 10
ICC for Processors
—
—
—
Processor
Number
Core Frequency/Voltage
—
—
—
2.53 GHz & VCCHFM
1.60 GHz & VCCLFM
—
—
64
47
A
3, 4
ICC
QX9300
30
Min
V
IAH,
ISGNT
ICC Auto-Halt & Stop-Grant
HFM
LFM
—
—
32.4
30.0
A
3, 4
ISLP
ICC Sleep
HFM
LFM
—
—
31.8
29.7
A
3, 4
IDSLP
ICC Deep Sleep
HFM
LFM
—
—
30.1
28.8
A
3, 4
IDPRSLP
ICC Deeper Sleep
—
—
20.5
A
3, 4
Datasheet
Electrical Specifications
Table 7.
Voltage and Current Specifications for the Quad-Core Extreme Mobile
Processors (Sheet 2 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
Notes
5, 7
dICC/DT
VCC Power Supply Current Slew Rate
at Processor Package Pin
—
—
600
A/µs
ICCA
ICC for VCCA Supply
—
—
130
mA
ICCP
ICC for VCCP Supply before VCC Stable
ICC for VCCP Supply after VCC Stable
—
—
4.5
2.5
A
A
8, 9
NOTES:
1.
Each processor is programmed with a maximum valid voltage identification value (VID),
which is set at manufacturing and cannot be altered. Individual maximum VID values are
calibrated during manufacturing such that two processors at the same frequency may have
different settings within the VID range. Note that this differs from the VID employed by
the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel
SpeedStep Technology, or Enhanced Halt State).
2.
The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE
pins at socket with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe
capacitance, and 1-MΩ minimum impedance. The maximum length of ground wire on the
probe should be less than 5 mm. Ensure external noise from the system is not coupled in
the scope probe.
3.
Specified at 100°C TJ.
4.
Specified at the nominal VCC.
5.
Measured at the bulk capacitors on the motherboard.
6.
VCC,BOOT tolerance shown in Figure 4 and Figure 5.
7.
Based on simulations and averaged over the duration of any change in current. Specified
by design/characterization at nominal VCC. Not 100% tested.
8.
This is a power-up peak current specification, which is applicable when VCCP is high and
VCC_CORE is low.
9.
This is a steady-state ICC current specification, which is applicable when both VCCP and
VCC_CORE are high.
10.
Instantaneous current ICC_CORE_INST of 85 A has to be sustained for short time (tINST) of
35µs. Average current will be less than maximum specified ICCDES. VR OCP threshold
should be high enough to support current levels described herein.
Table 8.
Voltage and Current Specifications for the Quad-Core Mobile Processors
(Sheet 1 of 2)
Symbol
Datasheet
Parameter
Min
Typ
Max
Unit
Notes
VCCDAM
VCC in Intel Dynamic Acceleration
Technology Mode
0.90
—
1.30
V
1, 2
VCCHFM
VCC at Highest Frequency Mode (HFM)
0.90
—
1.25
V
1, 2
VCCLFM
VCC at Lowest Frequency Mode (LFM)
0.85
—
1.10
V
1, 2
VCC,BOOT
Default VCC Voltage for Initial Power
Up
—
1.20
V
2, 5, 6
VCCP
AGTL+ Termination Voltage
1.00
1.05
1.10
VCCA
PLL Supply Voltage
1.425
1.5
1.575
V
VCCDPRSLP
VCC at Deeper Sleep
0.65
—
0.85
V
1, 2
ICCDES
ICC for Processors Recommended
Design Target
—
—
64
A
5, 10
V
31
Electrical Specifications
Table 8.
Voltage and Current Specifications for the Quad-Core Mobile Processors
(Sheet 2 of 2)
Symbol
ICC
Parameter
Min
Typ
Max
Unit
Notes
ICC for Processors
—
—
—
Processor
Number
Core Frequency/Voltage
—
—
—
Q9100
2.26 GHz & VCCHFM
1.60 GHz & VCCLFM
—
—
64
47
A
3, 4
Q9000
2.0 GHz & VCCHFM
1.60 GHz & VCCLFM
—
—
64
47
A
3, 4
IAH,
ISGNT
ICC Auto-Halt & Stop-Grant
HFM
LFM
—
—
32.4
30.0
A
3, 4
ISLP
ICC Sleep
HFM
LFM
—
—
31.8
29.7
A
3, 4
IDSLP
ICC Deep Sleep
HFM
LFM
—
—
30.1
28.8
A
3, 4
IDPRSLP
ICC Deeper Sleep
—
—
20.5
A
3, 4
dICC/DT
VCC Power Supply Current Slew Rate
at Processor Package Pin
—
—
600
A/µs
5, 7
ICCA
ICC for VCCA Supply
—
—
130
mA
ICCP
ICC for VCCP Supply before VCC Stable
ICC for VCCP Supply after VCC Stable
—
4.5
2.5
A
A
—
8,9
NOTES:
1.
Each processor is programmed with a maximum valid voltage identification value (VID),
which is set at manufacturing and cannot be altered. Individual maximum VID values are
calibrated during manufacturing such that two processors at the same frequency may have
different settings within the VID range. Note that this differs from the VID employed by
the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel
SpeedStep Technology, or Enhanced Halt State).
2.
The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE
pins at socket with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe
capacitance, and 1-MΩ minimum impedance. The maximum length of ground wire on the
probe should be less than 5 mm. Ensure external noise from the system is not coupled in
the scope probe.
3.
Specified at 100°C TJ.
4.
Specified at the nominal VCC.
5.
Measured at the bulk capacitors on the motherboard.
6.
VCC,BOOT tolerance shown in Figure 4 and Figure 5.
7.
Based on simulations and averaged over the duration of any change in current. Specified
by design/characterization at nominal VCC. Not 100% tested.
8.
This is a power-up peak current specification, which is applicable when VCCP is high and
VCC_CORE is low.
9.
This is a steady-state ICC current specification, which is applicable when both VCCP and
VCC_CORE are high.
10.
Instantaneous current ICC_CORE_INST of 85 A has to be sustained for short time (tINST) of
35µs. Average current will be less than maximum specified ICCDES. VR OCP threshold
should be high enough to support current levels described herein.
32
Datasheet
Electrical Specifications
Figure 4.
Active VCC and ICC Loadline for Quad-Core Extreme Mobile Processor
VCC-CORE [V]
Slope = -2.1 mV/A at package
VccSense, VssSense pins.
Differential Remote Sense required.
VCC-CORE max {HFM|LFM}
VCC-CORE, DC max {HFM|LFM}
10mV= RIPPLE
VCC-CORE nom {HFM|LFM}
VCC-CORE, DC min {HFM|LFM}
VCC-CORE min {HFM|LFM}
+/-VCC-CORE Tolerance
= VR St. Pt. Error 1/
0
ICC-CORE max
{HFM|LFM}
ICC-CORE
[A]
Note 1 / V C C - C O R E S et P oi n t Er ro r T o l er a nce i s pe r b el o w :
T ol e ra n c e
-- - - -- - - -- - -- - + / - 1. 5%
+ / - 11 .5 mV
Datasheet
V C C - C O R E V ID V ol t ag e R an ge
-- - - -- - - -- - -- - - -- - - -- - - -- - - -- - -- - - -- - - -- - - -- - - -- - -- - - -- V C C - C O R E > 0 .7 50 0 V
0 . 50 00 V < /= V c c _ c o r e </ = 0. 75 00 0 V
33
Electrical Specifications
Figure 5.
Deeper Sleep VCC and ICC Loadline for Quad-Core Extreme Mobile Processor
VCC-CORE [V]
Slope = -2.1 mV/A at package
VccSense, VssSense pins.
Differential Remote Sense required.
VCC-CORE max {HFM|LFM}
VCC-CORE, DC max {HFM|LFM}
13mV= RIPPLE
VCC-CORE nom {HFM|LFM}
VCC-CORE, DC min {HFM|LFM}
VCC-CORE min {HFM|LFM}
+/-VCC-CORE Tolerance
= VR St. Pt. Error 1/
0
ICC-CORE max
{HFM|LFM}
ICC-CORE
[A]
Note 1/ V C C - C O R E Set Point Error Tolerance is per below :
Tolerance
V C C - C O R E VID Voltage Range
--------------- -------------------------------------------------------+/-[(VID*1.5%)-3mV]
V C C - C O R E > 0.7500V
+/-(11.5mV-3mV)
0.5000V </= V C C - C O R E </= 0.7500V
0.3000V </= V C C - C O R E < 0.5000V
NOTE: Deeper Sleep mode tolerance depends on VID value.
Table 9.
AGTL+ Signal Group DC Specifications (Sheet 1 of 2)
Symbol
VCCP
Min
Typ
Max
Unit
Notes1
I/O Voltage
1.00
1.05
1.10
V
Reference Voltage
0.65
0.70
0.72
V
6
Reference Voltage_2
0.653
0.67
0.7
V
6
RCOMP
Compensation Resistor
24.75
25
25.25
Ω
10
RODT/A
Termination Resistor
Address
45
50
55
Ω
11, 12
RODT/D
Termination Resistor
Data
45
50
55
Ω
11, 13
RODT/Cntrl
Termination Resistor
Control
45
50
55
Ω
11, 14
GTLREF
GTLREF_2
34
Parameter
VIH
Input High Voltage
0.82
1.05
1.20
V
3,6
VIL
Input Low Voltage
-0.10
0
0.55
V
2,4
VOH
Output High Voltage
0.90
VCCP
1.10
V
6
Datasheet
Electrical Specifications
Table 9.
AGTL+ Signal Group DC Specifications (Sheet 2 of 2)
RTT/A
Termination Resistance
Address
45
50
55
Ω
7, 12
RTT/D
Termination Resistance
Data
45
50
55
Ω
7, 13
RTT/Cntrl
Termination Resistance
Control
45
50
55
Ω
7, 14
RON/A
Buffer On Resistance
Address
8.25
8.33
12.25
Ω
5, 12
RON/D
Buffer On Resistance
Data
8.25
8.33
12.25
Ω
5, 13
RON/Cntrl
Buffer On Resistance
Control
8.25
8.33
12.25
Ω
5, 14
—
—
± 100
µA
8
1.80
2.30
2.75
pF
9
ILI
Cpad
Input Leakage Current
Pad Capacitance
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as
a logical low value.
3.
VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as
a logical high value.
4.
VIH and VOH may experience excursions above VCCP. However, input signal drivers must
comply with the signal quality specifications.
5.
This is the pulldown driver resistance. Refer to processor I/O Buffer Models for I/V
characteristics. Measured at 0.31*VCCP. RON (min) = 0.418*RTT, RON (typ) = 0.455*RTT,
RON (max) = 0.527*RTT. RTT typical value of 55 Ω is used for RON typ/min/max
calculations.
6.
GTLREF/GTLREF_2 should be generated from VCCP with a 1% tolerance resistor divider.
The VCCP referred to in these specifications is the instantaneous VCCP.
7.
RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver.
Measured at 0.31*VCCP. RTT is connected to VCCP on die. Refer to processor I/O buffer
models for I/V characteristics.
8.
Specified with on-die RTT and RON turned off. Vin between 0 and VCCP.
9.
Cpad includes die capacitance only. No package parasitics are included.
10.
This is the external resistor on the comp pins.
11.
On-die termination resistance, measured at 0.33*VCCP.
12.
Applies to Signals A[35:3].
13.
Applies to Signals D[63:0].
14.
Applies to Signals BPRI#, DEFER#, PREQ#, PREST#, RS[2:0]#, TRDY#, ADS#, BNR#,
BPM[3:0], BR0#, DBSY#, DRDY#, HIT#, HITM#, LOCK#, PRDY#, DPWR#, DSTB[1:0]#,
DSTBP[3:0] and DSTBN[3:0]#.
Datasheet
35
Electrical Specifications
Table 10.
CMOS Signal Group DC Specifications
Symbol
VCCP
Parameter
I/O Voltage
Min
Typ
Max
Unit
1.00
1.05
1.10
V
Notes1
VIL
Input Low Voltage CMOS
-0.10
0.00
0.3*VCCP
V
2, 3
VIH
Input High Voltage
0.7*VCCP
VCCP
VCCP+0.1
V
2
VOL
Output Low Voltage
-0.10
0
0.1*VCCP
V
2
VOH
Output High Voltage
0.9*VCCP
VCCP
VCCP+0.1
V
2
IOL
Output Low Current
1.5
—
4.1
mA
4
IOH
Output High Current
1.5
—
4.1
mA
5
ILI
Input Leakage Current
—
—
±100
µA
6
Cpad1
Pad Capacitance
1.80
2.30
2.75
pF
7
Cpad2
Pad Capacitance for CMOS
Input
0.95
1.2
1.45
pF
8
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
The VCCP referred to in these specifications refers to instantaneous VCCP.
3.
Refer to the processor I/O Buffer Models for I/V characteristics.
4.
Measured at 0.1 *VCCP.
5.
Measured at 0.9 *VCCP.
6.
For Vin between 0 V and VCCP. Measured when the driver is tristated.
7.
Cpad1 includes die capacitance only for DPRSTP#, DPSLP#, PWRGOOD. No package
parasitics are included.
8.
Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics are
included.
Table 11.
Open Drain Signal Group DC Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Notes1
VCCP–5%
VCCP
VCCP+5%
V
3
VOH
Output High Voltage
VOL
Output Low Voltage
0
—
0.20
V
IOL
Output Low Current
16
—
50
mA
2
ILO
Output Leakage Current
—
—
±200
µA
4
1.80
2.30
2.75
pF
5
Cpad
Pad Capacitance
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Measured at 0.2 V.
3.
VOH is determined by value of the external pull-up resistor to VCCP. Refer to the appropriate
platform design guide for details.
4.
For Vin between 0 V and VOH.
5.
Cpad includes die capacitance only. No package parasitics are included.
§
36
Datasheet
Package Mechanical Specifications and Pin Information
4
Package Mechanical
Specifications and Pin
Information
4.1
Package Mechanical Specifications
The processor is available in a 478-pin Micro-FCPGA package. The package mechanical
dimensions are shown in Figure 6 and Figure 7.
The mechanical package pressure specifications are in a direction normal to the surface
of the processor. This requirement protects the processor die from fracture risk due to
uneven die pressure distribution under tilt, stack-up tolerances and other similar
conditions. These specifications assume that a mechanical attach is designed
specifically to load one type of processor.
The processor package substrate should not be used as a mechanical reference or loadbearing surface for the thermal or mechanical solution.
Datasheet
37
38
'
'
0.37 MAX
0.65 MAX
*+,*-. /0123*2.
45.36788
7.
' P
%
%
"
"
# !
$ !
!
)
$
$
D99017-1of1
$
& '
( '
( C A B
C
ø0.356 M
ø0.254 M
-
' ' '
''
''
&
#.974- 741
%
%
!
!
! 2.03±0.08
0.65 MAX
%
Figure 6.
! ( ( ! ( Package Mechanical Specifications and Pin Information
Quad-Core Processor Micro-FCPGA Package Drawing (Sheet 1 of 2)
Datasheet
Datasheet
#
EDGE KEEP OUT
ZONE 4X
4x 4.3
13.97
!
1.625
1.625
"
"
1.5 MAX ALLOWABLE
COMPONENT HEIGHT
"
$ #
% #
D99017-2of2
6.985
13.97
6.985
4 X 6.18
CORNER KEEP
OUT ZONE
ø0.305±0.25
ø0.406 M C A B
ø0.254 M C
#
Figure 7.
& % % & % Package Mechanical Specifications and Pin Information
Quad-Core Processor Micro-FCPGA Package Drawing (Sheet 2 of 2)
39
Package Mechanical Specifications and Pin Information
4.2
Processor Pinout and Pin List
Figure 8 and Figure 9 shows the processor pinout as viewed from the top of the
package. Table 12 provides the pin list, arranged numerically by pin name. Table 13
provides the pin list, arranged numerically by pin number. Table 14 is the signal
description for processor. Table 15 lists new quad-core processor pins compared to the
Intel Core 2 Duo processor.
Figure 8.
1
Quad-Core Processor Pinout (Top Package View, Left Side)
2
3
4
5
6
7
8
9
10
11
12
13
A
VSS
SMI#
VSS
FERR#
A20M#
VCC
VSS
VCC
VCC
VSS
VCC
VCC
A
B
BPM_2[
2]#
INIT#
LINT1
DPSLP#
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
B
VSS
TEST7
IGNNE
#
VSS
LINT0
THERM
TRIP#
VSS
VCC
VCC
VSS
VCC
VCC
C
PWRGO
OD
SLP#
RSVD
VCC
VCC
VSS
VCC
VSS
D
C
RESET#
D
VSS
RSVD
TDO_M
VSS
STPCLK
#
E
DBSY#
BNR#
VSS
HITM#
DPRSTP
#
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VCC
E
F
BR0#
VSS
RS[0]#
RS[1]#
VSS
TDI_M
VCC
GTLREF
_CONT
ROL
VCC
VCC
VSS
VCC
VSS
F
G
VSS
TRDY#
RS[2]#
VSS
BPRI#
HIT#
G
H
ADS#
REQ[1]
#
VSS
LOCK#
DEFER#
VSS
H
J
A[9]#
VSS
REQ[3]
#
A[3]#
VSS
VCCP
J
K
VSS
REQ[2]
#
REQ[0]
#
VSS
A[6]#
VCCP
K
L
REQ[4]#
A[13]#
VSS
A[5]#
A[4]#
VSS
L
M
ADSTB[0]
#
A[7]#
BPM_2[
1]#
VSS
VCCP
M
A[10]#
VSS
BPM_2[0
]#
VCCP
N
N
VSS
VSS
A[8]#
P
A[15]#
A[12]#
VSS
A[14]#
A[11]#
VSS
P
R
A[16]#
VSS
A[19]#
A[24]#
VSS
VCCP
R
T
VSS
THRMD
A_2
A[26]#
VSS
A[25]#
VCCP
T
U
A[23]#
A[30]#
VSS
A[21]#
A[18]#
VSS
U
V
ADSTB[1]
#
VSS
THRMD
C_2
A[31]#
VSS
VCCP
V
W
VSS
A[27]#
A[32]#
VSS
A[28]#
A[20]#
W
Y
COMP[3]
A[17]#
VSS
A[29]#
A[22]#
VSS
Y
AA
COMP[2]
VSS
A[35]#
A[33]#
VSS
TDI
BR1#
RSVD
VCC
VCC
VSS
VCC
VCC
A
A
AB
VSS
A[34]#
TDO
VSS
TMS
TRST#
VCC
VSS
VCC
VCC
VSS
VCC
VSS
A
B
AC
PREQ#
PRDY#
VSS
BPM[3]
#
TCK
VSS
VCC
RSVD
VCC
VCC
VSS
VCC
VCC
A
C
AD
BPM[2]#
VSS
BPM[1]
#
BPM[0]
#
VSS
VID[0]
VCC
VSS
VCC
VCC
VSS
VCC
VSS
A
D
AE
VSS
VID[6]
VID[4]
VSS
VID[2]
PSI#
VSS
SENSE
BPM_2[
3]#
VCC
VCC
VSS
VCC
VCC
A
E
AF
TEST5
VSS
VID[5]
VID[3]
VID[1]
VSS
VCC
SENSE
VSS
VCC
VCC
VSS
VCC
VSS
A
F
1
2
3
4
5
6
7
8
9
10
11
12
13
40
Datasheet
Package Mechanical Specifications and Pin Information
Figure 9.
14
Quad-Core Processor Pinout (Top Package View, Right Side)
15
16
17
18
19
20
21
22
23
24
25
26
A
VSS
VCC
VSS
VCC
VCC
VSS
VCC
BCLK[1]
BCLK[0]
VSS
THRMDA
VSS
TEST6
A
B
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VSS
BSEL[0]
BSEL[1]
VSS
THRMDC
VCCA
B
C
VSS
VCC
VSS
VCC
VCC
VSS
DBR#
BSEL[2]
VSS
TEST1
TEST3
VSS
VCCA
C
D
VCC
VCC
VSS
VCC
VCC
VSS
IERR#
PROCHOT
#
GTLREF_2
VSS
DPWR#
TEST2
VSS
D
E
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
D[0]#
D[7]#
VSS
D[6]#
D[2]#
E
F
VCC
VCC
VSS
VCC
VCC
VSS
VCC
DRDY#
VSS
D[4]#
D[1]#
VSS
D[13]#
F
G
VCCP
D[3]#
VSS
D[9]#
D[5]#
VSS
G
H
VSS
D[12]#
D[15]#
VSS
DINV[0]#
DSTBP[
0]#
H
DSTBN[
0]#
J
K
J
VCCP
VSS
D[11]#
D[10]#
VSS
K
VCCP
D[14]#
VSS
D[8]#
D[17]#
VSS
L
L
VSS
D[22]#
D[20]#
VSS
D[29]#
DSTBN[
1]#
M
VCCP
VSS
D[23]#
D[21]#
VSS
DSTBP[
1]#
M
N
VCCP
D[16]#
VSS
DINV[1]#
D[31]#
VSS
N
P
VSS
D[26]#
D[25]#
VSS
D[24]#
D[18]#
P
R
R
VCCP
VSS
D[19]#
D[28]#
VSS
COMP[0
]
T
VCCP
D[37]#
VSS
D[27]#
D[30]#
VSS
T
D[38]#
COMP[1
]
U
U
VSS
DINV[2]#
D[39]#
VSS
V
VCCP
VSS
D[36]#
D[34]#
VSS
D[35]#
V
W
VCCP
D[41]#
VSS
D[43]#
D[44]#
VSS
W
Y
VSS
D[32]#
D[42]#
VSS
D[40]#
DSTBN[
2]#
Y
AA
VSS
VCC
VSS
VCC
VCC
VSS
VCC
D[50]#
VSS
D[45]#
D[46]#
VSS
DSTBP[
2]#
A
A
AB
VCC
VCC
VSS
VCC
VCC
VSS
VCC
D[52]#
D[51]#
VSS
D[33]#
D[47]#
VSS
A
B
AC
VSS
VCC
VSS
VCC
VCC
VSS
DINV[3
]#
VSS
D[60]#
D[63]#
VSS
D[57]#
D[53]#
A
C
A
D
VCC
VCC
VSS
VCC
VCC
VSS
D[54]#
D[59]#
VSS
D[61]#
D[49]#
VSS
GTLREF
A
D
AE
VSS
VCC
VSS
VCC
VCC
VSS
VCC
D[58]#
D[55]#
VSS
D[48]#
DSTBN[3]
#
VSS
A
E
AF
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VSS
D[62]#
D[56]#
DSTBP[3]
#
VSS
TEST4
A
F
14
15
16
17
18
19
20
21
22
23
24
25
26
Datasheet
41
Package Mechanical Specifications and Pin Information
Table 12.
Pin
Name
Pin
#
Signal
Buffer Type
Direction
A20M#
A6
CMOS
Input
A[10]#
N3
Source Synch
Input/
Output
A[11]#
P5
Source Synch
Input/
Output
A[12]#
P2
Source Synch
Input/
Output
A[13]#
L2
Source Synch
Input/
Output
A[14]#
P4
Source Synch
Input/
Output
A[15]#
P1
Source Synch
Input/
Output
A[16]#
R1
Source Synch
Input/
Output
A[17]#
Y2
Source Synch
Input/
Output
A[18]#
U5
Source Synch
Input/
Output
A[19]#
R3
Source Synch
Input/
Output
A[20]#
W6
Source Synch
Input/
Output
Table 12.
Pin
Name
Pin Listing by Pin Name
Pin
#
Signal
Buffer Type
Direction
A[35]#
AA3
Source Synch
Input/
Output
A[3]#
J4
Source Synch
Input/
Output
A[4]#
L5
Source Synch
Input/
Output
A[5]#
L4
Source Synch
Input/
Output
A[6]#
K5
Source Synch
Input/
Output
A[7]#
M3
Source Synch
Input/
Output
A[8]#
N2
Source Synch
Input/
Output
A[9]#
J1
Source Synch
Input/
Output
ADS#
H1
Common Clock
Input/
Output
ADSTB[0]#
M1
Source Synch
Input/
Output
ADSTB[1]#
V1
Source Synch
Input/
Output
BCLK[0]
A22
Bus Clock
Input
BCLK[1]
A21
Bus Clock
Input
BNR#
E2
Common Clock
Input/
Output
BPM[0]#
AD4
Common Clock
Input/
Output
BPM[1]#
AD3
Common Clock
Output
BPM[2]#
AD1
Common Clock
Output
A[21]#
U4
Source Synch
Input/
Output
A[22]#
Y5
Source Synch
Input/
Output
A[23]#
U1
Source Synch
Input/
Output
A[24]#
R4
Source Synch
Input/
Output
A[25]#
T5
Source Synch
Input/
Output
BPM[3]#
AC4
Common Clock
Input/
Output
A[26]#
T3
Source Synch
Input/
Output
BPM_2[0]#
N5
Common Clock
Input/
Output
A[27]#
W2
Source Synch
Input/
Output
BPM_2[1]#
M4
Common Clock
Output
A[28]#
W5
Source Synch
Input/
Output
A[29]#
Y4
Source Synch
Input/
Output
A[30]#
U2
Source Synch
Input/
Output
A[31]#
V4
Source Synch
Input/
Output
A[32]#
W3
Source Synch
Input/
Output
A[33]#
A[34]#
42
Pin Listing by Pin Name
AA4
AB2
Source Synch
Input/
Output
Source Synch
Input/
Output
BPM_2[2]#
B2
Common Clock
Input/
Output
BPM_2[3]#
AE8
Common Clock
Input/
Output
BPRI#
G5
Common Clock
Input
BR0#
F1
Common Clock
Input/
Output
BR1#
AA7
Common Clock
Input/
Output
BSEL[0]
B22
CMOS
Output
BSEL[1]
B23
CMOS
Output
BSEL[2]
C21
CMOS
Output
Datasheet
Package Mechanical Specifications and Pin Information
Table 12.
Pin
Name
Datasheet
Pin Listing by Pin Name
Pin
#
Signal
Buffer Type
Direction
Table 12.
Pin
Name
Pin Listing by Pin Name
Pin
#
Signal
Buffer Type
Direction
COMP[0]
R26
Power/Other
Input/
Output
D[29]#
L25
Source Synch
Input/
Output
COMP[1]
U26
Power/Other
Input/
Output
D[2]#
E26
Source Synch
Input/
Output
COMP[2]
AA1
Power/Other
Input/
Output
D[30]#
T25
Source Synch
Input/
Output
COMP[3]
Y1
Power/Other
Input/
Output
D[31]#
N25
Source Synch
Input/
Output
D[0]#
E22
Source Synch
Input/
Output
D[32]#
Y22
Source Synch
Input/
Output
D[10]#
J24
Source Synch
Input/
Output
D[33]#
AB24
Source Synch
Input/
Output
D[11]#
J23
Source Synch
Input/
Output
D[34]#
V24
Source Synch
Input/
Output
D[12]#
H22
Source Synch
Input/
Output
D[35]#
V26
Source Synch
Input/
Output
D[13]#
F26
Source Synch
Input/
Output
D[36]#
V23
Source Synch
Input/
Output
D[14]#
K22
Source Synch
Input/
Output
D[37]#
T22
Source Synch
Input/
Output
D[15]#
H23
Source Synch
Input/
Output
D[38]#
U25
Source Synch
Input/
Output
D[16]#
N22
Source Synch
Input/
Output
D[39]#
U23
Source Synch
Input/
Output
D[17]#
K25
Source Synch
Input/
Output
D[3]#
G22
Source Synch
Input/
Output
D[18]#
P26
Source Synch
Input/
Output
D[40]#
Y25
Source Synch
Input/
Output
D[19]#
R23
Source Synch
Input/
Output
D[41]#
W22
Source Synch
Input/
Output
D[1]#
F24
Source Synch
Input/
Output
D[42]#
Y23
Source Synch
Input/
Output
D[20]#
L23
Source Synch
Input/
Output
D[43]#
W24
Source Synch
Input/
Output
D[21]#
M24
Source Synch
Input/
Output
D[44]#
W25
Source Synch
Input/
Output
D[22]#
L22
Source Synch
Input/
Output
D[45]#
AA23
Source Synch
Input/
Output
D[23]#
M23
Source Synch
Input/
Output
D[46]#
AA24
Source Synch
Input/
Output
D[24]#
P25
Source Synch
Input/
Output
D[47]#
AB25
Source Synch
Input/
Output
D[25]#
P23
Source Synch
Input/
Output
D[48]#
AE24
Source Synch
Input/
Output
D[26]#
P22
Source Synch
Input/
Output
D[49]#
AD24
Source Synch
Input/
Output
D[27]#
T24
Source Synch
Input/
Output
D[4]#
F23
Source Synch
Input/
Output
D[28]#
R24
Source Synch
Input/
Output
D[50]#
AA21
Source Synch
Input/
Output
43
Package Mechanical Specifications and Pin Information
Table 12.
Pin
Name
Pin
#
Signal
Buffer Type
Direction
Table 12.
Pin
Name
Pin Listing by Pin Name
Pin
#
Signal
Buffer Type
Direction
D[51]#
AB22
Source Synch
Input/
Output
DPWR#
D24
Common Clock
Input/
Output
D[52]#
AB21
Source Synch
Input/
Output
DRDY#
F21
Common Clock
Input/
Output
D[53]#
AC26
Source Synch
Input/
Output
DSTBN[0]#
J26
Source Synch
Input/
Output
D[54]#
AD20
Source Synch
Input/
Output
DSTBN[1]#
L26
Source Synch
Input/
Output
D[55]#
AE22
Source Synch
Input/
Output
DSTBN[2]#
Y26
Source Synch
Input/
Output
D[56]#
AF23
Source Synch
Input/
Output
DSTBN[3]#
AE25
Source Synch
Input/
Output
D[57]#
AC25
Source Synch
Input/
Output
DSTBP[0]#
H26
Source Synch
Input/
Output
D[58]#
AE21
Source Synch
Input/
Output
DSTBP[1]#
M26
Source Synch
Input/
Output
D[59]#
AD21
Source Synch
Input/
Output
DSTBP[2]#
AA26
Source Synch
Input/
Output
D[5]#
G25
Source Synch
Input/
Output
DSTBP[3]#
AF24
Source Synch
Input/
Output
D[60]#
AC22
Source Synch
Input/
Output
FERR#
A5
Open Drain
Output
AD26
Power/Other
Input
AD23
Source Synch
Input/
Output
GTLREF
D[61]#
GTLREF_2
D22
Power/Other
Input
D[62]#
AF22
Source Synch
Input/
Output
GTLREF_C
ONTROL
F8
CMOS
Input/
Output
D[63]#
AC23
Source Synch
Input/
Output
HIT#
G6
Common Clock
Input/
Output
D[6]#
E25
Source Synch
Input/
Output
HITM#
E4
Common Clock
Input/
Output
D[7]#
E23
Source Synch
Input/
Output
IERR#
D20
Open Drain
Output
D[8]#
K24
Source Synch
Input/
Output
D[9]#
G24
Source Synch
Input/
Output
DBR#
C20
CMOS
Output
IGNNE#
C4
CMOS
Input
INIT#
B3
CMOS
Input
LINT0
C6
CMOS
Input
LINT1
B4
CMOS
Input
LOCK#
H4
Common Clock
Input/
Output
DBSY#
E1
Common Clock
Input/
Output
PRDY#
AC2
Common Clock
Output
DEFER#
H5
Common Clock
Input
PREQ#
AC1
Common Clock
Input
PROCHOT#
D21
Open Drain
Input/
Output
PSI#
AE6
CMOS
Output
PWRGOOD
D6
CMOS
Input
REQ[0]#
K3
Source Synch
Input/
Output
REQ[1]#
H2
Source Synch
Input/
Output
REQ[2]#
K2
Source Synch
Input/
Output
DINV[0]#
H25
Source Synch
Input/
Output
DINV[1]#
N24
Source Synch
Input/
Output
Source Synch
Input/
Output
AC20
Source Synch
Input/
Output
DPRSTP#
E5
CMOS
Input
DPSLP#
B5
CMOS
Input
DINV[2]#
DINV[3]#
44
Pin Listing by Pin Name
U22
Datasheet
Package Mechanical Specifications and Pin Information
Table 12.
Pin
Name
REQ[3]#
REQ[4]#
Datasheet
Pin Listing by Pin Name
Pin
#
J3
L1
Signal
Buffer Type
Direction
Source Synch
Input/
Output
Source Synch
Input/
Output
Table 12.
Pin
Name
Pin Listing by Pin Name
Pin
#
Signal
Buffer Type
VCC
A15
Power/Other
VCC
A17
Power/Other
VCC
A18
Power/Other
A20
Power/Other
RESET#
C1
Common Clock
Input
VCC
RS[0]#
F3
Common Clock
Input
VCC
AA9
Power/Other
AA10
Power/Other
RS[1]#
F4
Common Clock
Input
VCC
RS[2]#
G3
Common Clock
Input
VCC
AA12
Power/Other
AA13
Power/Other
RSVD
D2
Reserved
VCC
RSVD
AA8
Reserved
VCC
AA15
Power/Other
AA17
Power/Other
RSVD
AC8
Reserved
VCC
RSVD
D8
Reserved
VCC
AA18
Power/Other
AA20
Power/Other
SLP#
D7
CMOS
Input
VCC
SMI#
A3
CMOS
Input
VCC
AB7
Power/Other
AB9
Power/Other
STPCLK#
D5
CMOS
Input
VCC
TCK
AC5
CMOS
Input
VCC
AB10
Power/Other
AB12
Power/Other
TDI
AA6
CMOS
Input
VCC
TDI_M
F6
CMOS
Input
VCC
AB14
Power/Other
AB15
Power/Other
TDO
AB3
Open Drain
Output
VCC
TDO_M
D3
Open Drain
Output
VCC
AB17
Power/Other
AB18
Power/Other
TEST1
C23
Test
VCC
TEST2
D25
Test
VCC
AB20
Power/Other
AC7
Power/Other
TEST3
C24
Test
VCC
TEST4
AF26
Test
VCC
AC9
Power/Other
AC10
Power/Other
TEST5
AF1
Test
VCC
TEST6
A26
Test
VCC
AC12
Power/Other
VCC
AC13
Power/Other
VCC
AC15
Power/Other
VCC
AC17
Power/Other
TEST7
C3
Test
THERMTRIP
#
C7
Open Drain
THRMDA
A24
Power/Other
VCC
AC18
Power/Other
THRMDA_2
T2
Power/Other
VCC
AD7
Power/Other
THRMDC
B25
Power/Other
VCC
AD9
Power/Other
THRMDC_2
V3
Power/Other
VCC
AD10
Power/Other
TMS
AB5
CMOS
Input
VCC
AD12
Power/Other
TRDY#
G2
Common Clock
Input
VCC
AD14
Power/Other
TRST#
AB6
CMOS
Input
VCC
AD15
Power/Other
VCC
A7
Power/Other
VCC
AD17
Power/Other
VCC
A9
Power/Other
VCC
AD18
Power/Other
VCC
A10
Power/Other
VCC
AE9
Power/Other
VCC
A12
Power/Other
VCC
AE10
Power/Other
VCC
A13
Power/Other
VCC
AE12
Power/Other
Output
Direction
45
Package Mechanical Specifications and Pin Information
Table 12.
Pin
Name
46
Pin Listing by Pin Name
Pin
#
Signal
Buffer Type
Direction
Table 12.
Pin
Name
Pin Listing by Pin Name
Pin
#
Signal
Buffer Type
Direction
VCC
AE13
Power/Other
VCC
E13
Power/Other
VCC
AE15
Power/Other
VCC
E15
Power/Other
VCC
AE17
Power/Other
VCC
E17
Power/Other
VCC
AE18
Power/Other
VCC
E18
Power/Other
VCC
AE20
Power/Other
VCC
E20
Power/Other
VCC
AF9
Power/Other
VCC
F7
Power/Other
VCC
AF10
Power/Other
VCC
F9
Power/Other
VCC
AF12
Power/Other
VCC
F10
Power/Other
VCC
AF14
Power/Other
VCC
F12
Power/Other
VCC
AF15
Power/Other
VCC
F14
Power/Other
VCC
AF17
Power/Other
VCC
F15
Power/Other
VCC
AF18
Power/Other
VCC
F17
Power/Other
VCC
AF20
Power/Other
VCC
F18
Power/Other
VCC
B7
Power/Other
VCC
F20
Power/Other
VCC
B9
Power/Other
VCCA
B26
Power/Other
VCC
B10
Power/Other
VCCA
C26
Power/Other
VCC
B12
Power/Other
VCCP
G21
Power/Other
VCC
B14
Power/Other
VCCP
J6
Power/Other
VCC
B15
Power/Other
VCCP
J21
Power/Other
VCC
B17
Power/Other
VCCP
K6
Power/Other
VCC
B18
Power/Other
VCCP
K21
Power/Other
VCC
B20
Power/Other
VCCP
M6
Power/Other
VCC
C9
Power/Other
VCCP
M21
Power/Other
VCC
C10
Power/Other
VCCP
N6
Power/Other
VCC
C12
Power/Other
VCCP
N21
Power/Other
VCC
C13
Power/Other
VCCP
R6
Power/Other
VCC
C15
Power/Other
VCCP
R21
Power/Other
VCC
C17
Power/Other
VCCP
T6
Power/Other
VCC
C18
Power/Other
VCCP
T21
Power/Other
VCC
D9
Power/Other
VCCP
V6
Power/Other
VCC
D10
Power/Other
VCCP
V21
Power/Other
VCC
D12
Power/Other
VCCP
W21
Power/Other
VCC
D14
Power/Other
VCCSENSE
AF7
Power/Other
VCC
D15
Power/Other
VID[0]
AD6
CMOS
Output
VCC
D17
Power/Other
VID[1]
AF5
CMOS
Output
VCC
D18
Power/Other
VID[2]
AE5
CMOS
Output
VCC
E7
Power/Other
VID[3]
AF4
CMOS
Output
VCC
E9
Power/Other
VID[4]
AE3
CMOS
Output
VCC
E10
Power/Other
VID[5]
AF3
CMOS
Output
VCC
E12
Power/Other
VID[6]
AE2
CMOS
Output
Datasheet
Package Mechanical Specifications and Pin Information
Table 12.
Pin
Name
Datasheet
Pin Listing by Pin Name
Pin
#
Signal
Buffer Type
Direction
Table 12.
Pin
Name
Pin Listing by Pin Name
Pin
#
Signal
Buffer Type
VSS
A2
Power/Other
VSS
AD19
Power/Other
VSS
A4
Power/Other
VSS
AD22
Power/Other
VSS
A8
Power/Other
VSS
AD25
Power/Other
VSS
A11
Power/Other
VSS
AE1
Power/Other
VSS
A14
Power/Other
VSS
AE4
Power/Other
VSS
A16
Power/Other
VSS
AE11
Power/Other
VSS
A19
Power/Other
VSS
AE14
Power/Other
VSS
A23
Power/Other
VSS
AE16
Power/Other
VSS
A25
Power/Other
VSS
AE19
Power/Other
VSS
AA2
Power/Other
VSS
AE23
Power/Other
VSS
AA5
Power/Other
VSS
AE26
Power/Other
VSS
AA11
Power/Other
VSS
AF2
Power/Other
VSS
AA14
Power/Other
VSS
AF6
Power/Other
VSS
AA16
Power/Other
VSS
AF8
Power/Other
VSS
AA19
Power/Other
VSS
AF11
Power/Other
VSS
AA22
Power/Other
VSS
AF13
Power/Other
VSS
AA25
Power/Other
VSS
AF16
Power/Other
VSS
AB1
Power/Other
VSS
AF19
Power/Other
VSS
AB4
Power/Other
VSS
AF21
Power/Other
VSS
AB8
Power/Other
VSS
AF25
Power/Other
VSS
AB11
Power/Other
VSS
B6
Power/Other
VSS
AB13
Power/Other
VSS
B8
Power/Other
VSS
AB16
Power/Other
VSS
B11
Power/Other
VSS
AB19
Power/Other
VSS
B13
Power/Other
VSS
AB23
Power/Other
VSS
B16
Power/Other
VSS
AB26
Power/Other
VSS
B19
Power/Other
VSS
AC3
Power/Other
VSS
B21
Power/Other
VSS
AC6
Power/Other
VSS
B24
Power/Other
VSS
AC11
Power/Other
VSS
C2
Power/Other
VSS
AC14
Power/Other
VSS
C5
Power/Other
VSS
AC16
Power/Other
VSS
C8
Power/Other
VSS
AC19
Power/Other
VSS
C11
Power/Other
VSS
AC21
Power/Other
VSS
C14
Power/Other
VSS
AC24
Power/Other
VSS
C16
Power/Other
VSS
AD2
Power/Other
VSS
C19
Power/Other
VSS
AD5
Power/Other
VSS
C22
Power/Other
VSS
AD8
Power/Other
VSS
C25
Power/Other
VSS
AD11
Power/Other
VSS
D1
Power/Other
VSS
AD13
Power/Other
VSS
D4
Power/Other
VSS
AD16
Power/Other
VSS
D11
Power/Other
Direction
47
Package Mechanical Specifications and Pin Information
Table 12.
Pin
Name
48
Pin Listing by Pin Name
Pin
#
Signal
Buffer Type
Direction
Table 12.
Pin
Name
Pin Listing by Pin Name
Pin
#
Signal
Buffer Type
VSS
D13
Power/Other
VSS
L21
VSS
D16
Power/Other
VSS
L24
Power/Other
VSS
D19
Power/Other
VSS
M2
Power/Other
VSS
D23
Power/Other
VSS
M5
Power/Other
VSS
D26
Power/Other
VSS
M22
Power/Other
VSS
E3
Power/Other
VSS
M25
Power/Other
VSS
E6
Power/Other
VSS
N1
Power/Other
VSS
E8
Power/Other
VSS
N4
Power/Other
VSS
E11
Power/Other
VSS
N23
Power/Other
VSS
E14
Power/Other
VSS
N26
Power/Other
VSS
E16
Power/Other
VSS
P3
Power/Other
VSS
E19
Power/Other
VSS
P6
Power/Other
VSS
E21
Power/Other
VSS
P21
Power/Other
VSS
E24
Power/Other
VSS
P24
Power/Other
VSS
F2
Power/Other
VSS
R2
Power/Other
VSS
F5
Power/Other
VSS
R5
Power/Other
VSS
F11
Power/Other
VSS
R22
Power/Other
VSS
F13
Power/Other
VSS
R25
Power/Other
VSS
F16
Power/Other
VSS
T1
Power/Other
VSS
F19
Power/Other
VSS
T4
Power/Other
VSS
F22
Power/Other
VSS
T23
Power/Other
VSS
F25
Power/Other
VSS
T26
Power/Other
VSS
G1
Power/Other
VSS
U3
Power/Other
VSS
G4
Power/Other
VSS
U6
Power/Other
VSS
G23
Power/Other
VSS
U21
Power/Other
VSS
G26
Power/Other
VSS
U24
Power/Other
VSS
H3
Power/Other
VSS
V2
Power/Other
VSS
H6
Power/Other
VSS
V5
Power/Other
VSS
H21
Power/Other
VSS
V22
Power/Other
VSS
H24
Power/Other
VSS
V25
Power/Other
VSS
J2
Power/Other
VSS
W1
Power/Other
VSS
J5
Power/Other
VSS
W4
Power/Other
VSS
J22
Power/Other
VSS
W23
Power/Other
VSS
J25
Power/Other
VSS
W26
Power/Other
VSS
K1
Power/Other
VSS
Y3
Power/Other
VSS
K4
Power/Other
VSS
Y6
Power/Other
VSS
K23
Power/Other
VSS
Y21
Power/Other
VSS
K26
Power/Other
VSS
Y24
Power/Other
VSS
L3
Power/Other
VSSSENSE
AE7
Power/Other
VSS
L6
Power/Other
Direction
Power/Other
Output
Datasheet
Package Mechanical Specifications and Pin Information
Table 13.
Pin
#
Pin Name
Signal
Buffer
Type
Direction
A2
VSS
Power/Other
A3
SMI#
CMOS
A4
VSS
Power/Other
A5
FERR#
Open Drain
Output
A6
A20M#
CMOS
Input
A7
VCC
Power/Other
Input
Table 13.
Pin
#
Pin Listing by Pin
Number
Pin Name
Signal
Buffer
Type
AA12
VCC
Power/Other
AA13
VCC
Power/Other
AA14
VSS
Power/Other
AA15
VCC
Power/Other
AA16
VSS
Power/Other
AA17
VCC
Power/Other
Direction
A8
VSS
Power/Other
AA18
VCC
Power/Other
A9
VCC
Power/Other
AA19
VSS
Power/Other
A10
VCC
Power/Other
AA20
VCC
Power/Other
A11
VSS
Power/Other
AA21
D[50]#
Source Synch
A12
VCC
Power/Other
A13
VCC
Power/Other
AA22
VSS
Power/Other
A14
VSS
Power/Other
AA23
D[45]#
Source Synch
Input/
Output
A15
VCC
Power/Other
A16
VSS
Power/Other
AA24
D[46]#
Source Synch
Input/
Output
A17
VCC
Power/Other
AA25
VSS
Power/Other
A18
VCC
Power/Other
AA26
DSTBP[2]#
Source Synch
A19
VSS
Power/Other
AB1
VSS
Power/Other
A20
VCC
Power/Other
A21
BCLK[1]
Bus Clock
Input
AB2
A[34]#
Source Synch
Input/
Output
A22
BCLK[0]
Bus Clock
Input
AB3
TDO
Open Drain
Output
A23
VSS
Power/Other
AB4
VSS
Power/Other
TMS
CMOS
Input
Input
A24
THRMDA
Power/Other
AB5
A25
VSS
Power/Other
AB6
TRST#
CMOS
AB7
VCC
Power/Other
A26
TEST6
Test
AA1
COMP[2]
Power/Other
AA2
VSS
Power/Other
AA3
A[35]#
Source Synch
Input/
Output
AA4
A[33]#
Source Synch
Input/
Output
AA5
VSS
Power/Other
AA6
TDI
CMOS
Input
BR1#
Common
Clock
Input/
Output
AA7
Datasheet
Pin Listing by Pin
Number
AA8
RSVD
Reserved
AA9
VCC
Power/Other
AA10
VCC
Power/Other
AA11
VSS
Power/Other
Input/
Output
AB8
VSS
Power/Other
AB9
VCC
Power/Other
AB10
VCC
Power/Other
AB11
VSS
Power/Other
AB12
VCC
Power/Other
AB13
VSS
Power/Other
AB14
VCC
Power/Other
AB15
VCC
Power/Other
AB16
VSS
Power/Other
AB17
VCC
Power/Other
AB18
VCC
Power/Other
AB19
VSS
Power/Other
AB20
VCC
Power/Other
Input/
Output
Input/
Output
49
Package Mechanical Specifications and Pin Information
Table 13.
Pin
#
Pin Name
Signal
Buffer
Type
Direction
AB21
D[52]#
Source Synch
Input/
Output
AB22
D[51]#
Source Synch
Input/
Output
AB23
VSS
Power/Other
AB24
D[33]#
Source Synch
Input/
Output
AB25
D[47]#
Source Synch
Input/
Output
AB26
VSS
Power/Other
AC1
PREQ#
Common
Clock
AC2
PRDY#
Common
Clock
AC3
VSS
Power/Other
BPM[3]#
Common
Clock
AC4
50
Pin Listing by Pin
Number
AC5
TCK
CMOS
AC6
VSS
Power/Other
AC7
VCC
Power/Other
AC8
RSVD
Reserved
AC9
VCC
Power/Other
AC10
VCC
Power/Other
Input
Output
Input/
Output
Input
Table 13.
Pin
#
Pin Listing by Pin
Number
Pin Name
Signal
Buffer
Type
Common
Clock
Direction
Output
AD1
BPM[2]#
AD2
VSS
Power/Other
AD3
BPM[1]#
Common
Clock
Output
AD4
BPM[0]#
Common
Clock
Input/
Output
AD5
VSS
Power/Other
AD6
VID[0]
CMOS
AD7
VCC
Power/Other
AD8
VSS
Power/Other
AD9
VCC
Power/Other
AD10
VCC
Power/Other
AD11
VSS
Power/Other
AD12
VCC
Power/Other
AD13
VSS
Power/Other
AD14
VCC
Power/Other
AD15
VCC
Power/Other
AD16
VSS
Power/Other
AD17
VCC
Power/Other
AD18
VCC
Power/Other
AD19
VSS
Power/Other
AD20
D[54]#
Source Synch
Input/
Output
AD21
D[59]#
Source Synch
Input/
Output
Output
AC11
VSS
Power/Other
AC12
VCC
Power/Other
AC13
VCC
Power/Other
AC14
VSS
Power/Other
AC15
VCC
Power/Other
AD22
VSS
Power/Other
AC16
VSS
Power/Other
AD23
D[61]#
Source Synch
AC17
VCC
Power/Other
Input/
Output
AC18
VCC
Power/Other
AD24
D[49]#
Source Synch
Input/
Output
AC19
VSS
Power/Other
AD25
VSS
Power/Other
AC20
DINV[3]#
Source Synch
AD26
GTLREF
Power/Other
AE1
VSS
Power/Other
AE2
VID[6]
CMOS
Output
AE3
VID[4]
CMOS
Output
Input/
Output
AC21
VSS
Power/Other
AC22
D[60]#
Source Synch
Input/
Output
AC23
D[63]#
Source Synch
Input/
Output
AC24
VSS
Power/Other
AC25
D[57]#
Source Synch
Input/
Output
AC26
D[53]#
Source Synch
Input/
Output
Input
AE4
VSS
Power/Other
AE5
VID[2]
CMOS
Output
AE6
PSI#
CMOS
Output
AE7
VSSSENSE
Power/Other
Output
AE8
BPM_2[3]#
Common
Clock
Input/
Output
Datasheet
Package Mechanical Specifications and Pin Information
Table 13.
Pin
#
Pin Name
Signal
Buffer
Type
Direction
Table 13.
Pin
#
Pin Listing by Pin
Number
Pin Name
Signal
Buffer
Type
Direction
AE9
VCC
Power/Other
AF19
VSS
Power/Other
AE10
VCC
Power/Other
AF20
VCC
Power/Other
AE11
VSS
Power/Other
AF21
VSS
Power/Other
AE12
VCC
Power/Other
AF22
D[62]#
Source Synch
Input/
Output
AF23
D[56]#
Source Synch
Input/
Output
AF24
DSTBP[3]#
Source Synch
Input/
Output
AF25
VSS
Power/Other
AF26
TEST4
Test
B2
BPM_2[2]#
Common
Clock
Input/
Output
B3
INIT#
CMOS
Input
AE13
VCC
Power/Other
AE14
VSS
Power/Other
AE15
VCC
Power/Other
AE16
VSS
Power/Other
AE17
VCC
Power/Other
AE18
VCC
Power/Other
AE19
VSS
Power/Other
AE20
VCC
Power/Other
AE21
Datasheet
Pin Listing by Pin
Number
D[58]#
Source Synch
AE22
D[55]#
Source Synch
AE23
VSS
Power/Other
AE24
D[48]#
Source Synch
Input/
Output
Input/
Output
Input/
Output
Input/
Output
B4
LINT1
CMOS
Input
B5
DPSLP#
CMOS
Input
B6
VSS
Power/Other
B7
VCC
Power/Other
B8
VSS
Power/Other
B9
VCC
Power/Other
AE25
DSTBN[3]#
Source Synch
B10
VCC
Power/Other
AE26
VSS
Power/Other
B11
VSS
Power/Other
AF1
TEST5
Test
B12
VCC
Power/Other
AF2
VSS
Power/Other
B13
VSS
Power/Other
AF3
VID[5]
CMOS
Output
B14
VCC
Power/Other
AF4
VID[3]
CMOS
Output
B15
VCC
Power/Other
Output
AF5
VID[1]
CMOS
B16
VSS
Power/Other
AF6
VSS
Power/Other
B17
VCC
Power/Other
AF7
VCCSENSE
Power/Other
B18
VCC
Power/Other
AF8
VSS
Power/Other
B19
VSS
Power/Other
AF9
VCC
Power/Other
B20
VCC
Power/Other
AF10
VCC
Power/Other
B21
VSS
Power/Other
AF11
VSS
Power/Other
B22
BSEL[0]
CMOS
Output
AF12
VCC
Power/Other
B23
BSEL[1]
CMOS
Output
AF13
VSS
Power/Other
B24
VSS
Power/Other
AF14
VCC
Power/Other
B25
THRMDC
Power/Other
B26
VCCA
Power/Other
C1
RESET#
Common
Clock
C2
VSS
Power/Other
AF15
VCC
Power/Other
AF16
VSS
Power/Other
AF17
VCC
Power/Other
AF18
VCC
Power/Other
Input
51
Package Mechanical Specifications and Pin Information
Table 13.
Pin
#
52
Pin Listing by Pin
Number
Pin Name
Signal
Buffer
Type
Direction
Table 13.
Pin
#
Pin Listing by Pin
Number
Pin Name
Signal
Buffer
Type
Direction
C3
TEST7
Test
C4
IGNNE#
CMOS
C5
VSS
Power/Other
C6
LINT0
CMOS
C7
THERMTRIP
#
Open Drain
C8
VSS
Power/Other
C9
VCC
Power/Other
C10
VCC
Power/Other
D22
C11
VSS
Power/Other
D23
C12
VCC
Power/Other
D24
DPWR#
C13
VCC
Power/Other
Common
Clock
C14
VSS
Power/Other
D25
TEST2
Test
C15
VCC
Power/Other
D26
VSS
Power/Other
C16
VSS
Power/Other
E1
DBSY#
Common
Clock
Input/
Output
C17
VCC
Power/Other
C18
VCC
Power/Other
E2
BNR#
Common
Clock
Input/
Output
C19
VSS
Power/Other
E3
VSS
Power/Other
C20
DBR#
CMOS
Output
E4
HITM#
Common
Clock
Input/
Output
C21
BSEL[2]
CMOS
Output
E5
DPRSTP#
CMOS
Input
C22
VSS
Power/Other
C23
TEST1
Test
C24
TEST3
Test
C25
VSS
Power/Other
Input
Input
Output
VCCA
Power/Other
D1
VSS
Power/Other
D2
RSVD
Reserved
D3
TDO_M
Open Drain
D4
VSS
Power/Other
D5
STPCLK#
CMOS
D6
PWRGOOD
CMOS
Input
D7
SLP#
CMOS
Input
RSVD
Reserved
D9
VCC
Power/Other
D10
VCC
Power/Other
D11
VSS
Power/Other
D12
VCC
Power/Other
D13
VSS
Power/Other
D14
VCC
Power/Other
VCC
D16
VSS
Power/Other
D17
VCC
Power/Other
D18
VCC
Power/Other
D19
VSS
Power/Other
D20
IERR#
Open Drain
Output
Open Drain
Input/
Output
GTLREF_2
Power/Other
Input
VSS
Power/Other
D21
C26
D8
D15
Output
Input
PROCHOT#
Power/Other
E6
VSS
Power/Other
E7
VCC
Power/Other
E8
VSS
Power/Other
E9
VCC
Power/Other
E10
VCC
Power/Other
E11
VSS
Power/Other
E12
VCC
Power/Other
E13
VCC
Power/Other
E14
VSS
Power/Other
E15
VCC
Power/Other
E16
VSS
Power/Other
E17
VCC
Power/Other
E18
VCC
Power/Other
E19
VSS
Power/Other
E20
VCC
Power/Other
E21
VSS
Power/Other
E22
D[0]#
Source Synch
Input/
Output
Input/
Output
Datasheet
Package Mechanical Specifications and Pin Information
Table 13.
Pin
#
Pin Name
Signal
Buffer
Type
E23
D[7]#
Source Synch
E24
VSS
Power/Other
E25
Datasheet
Pin Listing by Pin
Number
D[6]#
Direction
Input/
Output
Table 13.
Pin
#
Pin Listing by Pin
Number
Pin Name
Signal
Buffer
Type
Direction
G2
TRDY#
Common
Clock
Input
G3
RS[2]#
Common
Clock
Input
G4
VSS
Power/Other
Input
Input/
Output
Source Synch
Input/
Output
G5
BPRI#
Common
Clock
G6
HIT#
Common
Clock
G21
VCCP
Power/Other
G22
D[3]#
Source Synch
G23
VSS
Power/Other
G24
D[9]#
Source Synch
Input/
Output
G25
D[5]#
Source Synch
Input/
Output
G26
VSS
Power/Other
H1
ADS#
Common
Clock
Input/
Output
Input/
Output
E26
D[2]#
Source Synch
Input/
Output
F1
BR0#
Common
Clock
Input/
Output
F2
VSS
Power/Other
F3
RS[0]#
Common
Clock
Input
F4
RS[1]#
Common
Clock
Input
F5
VSS
Power/Other
F6
TDI_M
CMOS
F7
VCC
Power/Other
F8
GTLREF_CO
NTROL
CMOS
F9
VCC
Power/Other
F10
VCC
Power/Other
H2
REQ[1]#
Source Synch
H3
VSS
Power/Other
H4
LOCK#
Common
Clock
Input/
Output
H5
DEFER#
Common
Clock
Input
H6
VSS
Power/Other
H21
VSS
Power/Other
H22
D[12]#
Source Synch
Input/
Output
H23
D[15]#
Source Synch
Input/
Output
H24
VSS
Power/Other
H25
DINV[0]#
Source Synch
Input/
Output
H26
DSTBP[0]#
Source Synch
Input/
Output
J1
A[9]#
Source Synch
Input/
Output
J2
VSS
Power/Other
J3
REQ[3]#
Source Synch
Input/
Output
J4
A[3]#
Source Synch
Input/
Output
J5
VSS
Power/Other
Input
Input/
Output
F11
VSS
Power/Other
F12
VCC
Power/Other
F13
VSS
Power/Other
F14
VCC
Power/Other
F15
VCC
Power/Other
F16
VSS
Power/Other
F17
VCC
Power/Other
F18
VCC
Power/Other
F19
VSS
Power/Other
F20
VCC
Power/Other
F21
DRDY#
Common
Clock
F22
VSS
Power/Other
F23
D[4]#
Source Synch
Input/
Output
F24
D[1]#
Source Synch
Input/
Output
F25
VSS
Power/Other
F26
D[13]#
Source Synch
G1
VSS
Power/Other
Input/
Output
Input/
Output
Input/
Output
53
Package Mechanical Specifications and Pin Information
Table 13.
Pin
#
Pin Name
Signal
Buffer
Type
J6
VCCP
Power/Other
J21
VCCP
Power/Other
J22
VSS
Power/Other
J23
D[11]#
Source Synch
J24
D[10]#
Source Synch
J25
VSS
Power/Other
J26
DSTBN[0]#
Source Synch
K1
VSS
Power/Other
K2
54
Pin Listing by Pin
Number
REQ[2]#
Source Synch
Direction
Table 13.
Pin
#
Pin Listing by Pin
Number
Pin Name
Signal
Buffer
Type
Direction
L25
D[29]#
Source Synch
Input/
Output
L26
DSTBN[1]#
Source Synch
Input/
Output
Input/
Output
M1
ADSTB[0]#
Source Synch
Input/
Output
Input/
Output
M2
VSS
Power/Other
M3
A[7]#
Source Synch
Input/
Output
M4
BPM_2[1]#
Common
Clock
Output
M5
VSS
Power/Other
Input/
Output
Input/
Output
M6
VCCP
Power/Other
M21
VCCP
Power/Other
M22
VSS
Power/Other
M23
D[23]#
Source Synch
Input/
Output
M24
D[21]#
Source Synch
Input/
Output
M25
VSS
Power/Other
Input/
Output
M26
DSTBP[1]#
Source Synch
N1
VSS
Power/Other
Input/
Output
K3
REQ[0]#
Source Synch
K4
VSS
Power/Other
K5
A[6]#
Source Synch
K6
VCCP
Power/Other
K21
VCCP
Power/Other
K22
D[14]#
Source Synch
K23
VSS
Power/Other
K24
D[8]#
Source Synch
Input/
Output
N2
A[8]#
Source Synch
Input/
Output
K25
D[17]#
Source Synch
Input/
Output
N3
A[10]#
Source Synch
Input/
Output
K26
VSS
Power/Other
N4
VSS
Power/Other
L1
REQ[4]#
Source Synch
Input/
Output
N5
BPM_2[0]#
Common
Clock
VCCP
Power/Other
A[13]#
Source Synch
Input/
Output
N6
L2
N21
VCCP
Power/Other
L3
VSS
Power/Other
N22
D[16]#
Source Synch
N23
VSS
Power/Other
N24
DINV[1]#
Source Synch
Input/
Output
N25
D[31]#
Source Synch
Input/
Output
N26
VSS
Power/Other
P1
A[15]#
Source Synch
Input/
Output
P2
A[12]#
Source Synch
Input/
Output
P3
VSS
Power/Other
Input/
Output
L4
A[5]#
Source Synch
Input/
Output
L5
A[4]#
Source Synch
Input/
Output
L6
VSS
Power/Other
L21
VSS
Power/Other
L22
D[22]#
Source Synch
Input/
Output
L23
D[20]#
Source Synch
Input/
Output
L24
VSS
Power/Other
Input/
Output
Input/
Output
Input/
Output
Datasheet
Package Mechanical Specifications and Pin Information
Table 13.
Pin
#
Pin Name
Signal
Buffer
Type
Direction
Table 13.
Pin
#
Pin Listing by Pin
Number
Pin Name
Signal
Buffer
Type
Direction
P4
A[14]#
Source Synch
Input/
Output
T24
D[27]#
Source Synch
Input/
Output
P5
A[11]#
Source Synch
Input/
Output
T25
D[30]#
Source Synch
Input/
Output
T26
VSS
Power/Other
U1
A[23]#
Source Synch
Input/
Output
U2
A[30]#
Source Synch
Input/
Output
U3
VSS
Power/Other
U4
A[21]#
Source Synch
Input/
Output
U5
A[18]#
Source Synch
Input/
Output
U6
VSS
Power/Other
U21
VSS
Power/Other
U22
DINV[2]#
Source Synch
Input/
Output
U23
D[39]#
Source Synch
Input/
Output
U24
VSS
Power/Other
U25
D[38]#
Source Synch
Input/
Output
U26
COMP[1]
Power/Other
Input/
Output
V1
ADSTB[1]#
Source Synch
Input/
Output
V2
VSS
Power/Other
V3
THRMDC_2
Power/Other
V4
A[31]#
Source Synch
V5
VSS
Power/Other
V6
VCCP
Power/Other
V21
VCCP
Power/Other
V22
VSS
Power/Other
V23
D[36]#
Source Synch
Input/
Output
V24
D[34]#
Source Synch
Input/
Output
V25
VSS
Power/Other
V26
D[35]#
Source Synch
W1
VSS
Power/Other
W2
A[27]#
Source Synch
P6
VSS
Power/Other
P21
VSS
Power/Other
P22
D[26]#
Source Synch
Input/
Output
Input/
Output
P23
D[25]#
Source Synch
P24
VSS
Power/Other
P25
D[24]#
Source Synch
Input/
Output
P26
D[18]#
Source Synch
Input/
Output
Input/
Output
R1
A[16]#
Source Synch
R2
VSS
Power/Other
R3
A[19]#
Source Synch
Input/
Output
R4
A[24]#
Source Synch
Input/
Output
R5
VSS
Power/Other
R6
VCCP
Power/Other
R21
VCCP
Power/Other
R22
VSS
Power/Other
R23
D[19]#
Source Synch
R24
D[28]#
Source Synch
R25
VSS
Power/Other
R26
COMP[0]
Power/Other
T1
VSS
Power/Other
T2
THRMDA_2
Power/Other
T3
A[26]#
Source Synch
T4
VSS
Power/Other
T5
Datasheet
Pin Listing by Pin
Number
A[25]#
Source Synch
T6
VCCP
Power/Other
T21
VCCP
Power/Other
T22
D[37]#
Source Synch
T23
VSS
Power/Other
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
55
Package Mechanical Specifications and Pin Information
Table 13.
Pin
#
56
Pin Listing by Pin
Number
Pin Name
Signal
Buffer
Type
Direction
Input/
Output
W3
A[32]#
Source Synch
W4
VSS
Power/Other
W5
A[28]#
Source Synch
Input/
Output
W6
A[20]#
Source Synch
Input/
Output
W21
VCCP
Power/Other
W22
D[41]#
Source Synch
W23
VSS
Power/Other
W24
D[43]#
Source Synch
Input/
Output
W25
D[44]#
Source Synch
Input/
Output
W26
VSS
Power/Other
Y1
COMP[3]
Power/Other
Input/
Output
Y2
A[17]#
Source Synch
Input/
Output
Y3
VSS
Power/Other
Y4
A[29]#
Source Synch
Input/
Output
Y5
A[22]#
Source Synch
Input/
Output
Y6
VSS
Power/Other
Y21
VSS
Power/Other
Y22
D[32]#
Source Synch
Input/
Output
Y23
D[42]#
Source Synch
Input/
Output
Y24
VSS
Power/Other
Y25
D[40]#
Source Synch
Input/
Output
Y26
DSTBN[2]#
Source Synch
Input/
Output
Input/
Output
Datasheet
Package Mechanical Specifications and Pin Information
Table 14.
Signal Description (Sheet 1 of 9)
Name
A20M#
Type
Input
Description
If A20M# (Address-20 Mask) is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any
internal cache and before driving a read/write transaction on the
bus. Asserting A20M# emulates the 8086 processor's address
wrap-around at the 1-MB boundary. Assertion of A20M# is only
supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition
of this signal following an input/output write instruction, it must be
valid along with the TRDY# assertion of the corresponding input/
output Write bus transaction.
A[35:3]#
ADS#
Input/
Output
A[35:3]# (Address) define a 236-byte physical memory address
space. In sub-phase 1 of the address phase, these pins transmit
the address of a transaction. In sub-phase 2, these pins transmit
transaction type information. These signals must connect the
appropriate pins of both agents on the processor FSB. A[35:3]#
are source-synchronous signals and are latched into the receiving
buffers by ADSTB[1:0]#. Address signals are used as straps, which
are sampled before RESET# is deasserted.
Input/
Output
ADS# (Address Strobe) is asserted to indicate the validity of the
transaction address on the A[35:3]# and REQ[4:0]# pins. All bus
agents observe the ADS# activation to begin parity checking,
protocol checking, address decode, internal snoop, or deferred
reply ID match operations associated with the new transaction.
Address strobes are used to latch A[35:3]# and REQ[4:0]# on
their rising and falling edges. Strobes are associated with signals
as shown below.
ADSTB[1:0]#
BCLK[1:0]
Input/
Output
Input
Signals
Associated Strobe
REQ[4:0]#, A[16:3]#
ADSTB[0]#
A[35:17]#
ADSTB[1]#
The differential pair BCLK (Bus Clock) determines the FSB
frequency. All FSB agents must receive these signals to drive their
outputs and latch their inputs.
All external timing parameters are specified with respect to the
rising edge of BCLK0 crossing VCROSS.
BNR#
BPM[2:1]#
BPM[3,0]#
Datasheet
Input/
Output
Output
Input/
Output
BNR# (Block Next Request) is used to assert a bus stall by any bus
agent who is unable to accept new bus transactions. During a bus
stall, the current bus owner cannot issue any new transactions.
BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance
monitor signals. They are outputs from the processor that indicate
the status of breakpoints and programmable counters used for
monitoring processor performance. BPM[3:0]# should connect the
appropriate pins of all processor FSB agents.This includes debug or
performance monitoring tools.
57
Package Mechanical Specifications and Pin Information
Table 14.
Signal Description (Sheet 2 of 9)
Name
Type
BPM_2[1]#
Output
BPM_2[0;3:2]
#
Input/
Output
Description
BPM_2[3:0]# (Breakpoint Monitor) are breakpoint and
performance monitor signals of the second die. They are outputs
from the processor that indicate the status of breakpoints and
programmable counters used for monitoring processor
performance. BPM_2[3:0]# should connect the appropriate pins of
all processor FSB agents.This includes debug or performance
monitoring tools.
BPRI#
Input
BPRI# (Bus Priority Request) is used to arbitrate for ownership of
the FSB. It must connect the appropriate pins of both FSB agents.
Observing BPRI# active (as asserted by the priority agent) causes
the other agent to stop issuing new requests, unless such requests
are part of an ongoing locked operation. The priority agent keeps
BPRI# asserted until all of its requests are completed, then
releases the bus by deasserting BPRI#.
BR0#
Input/
Output
BR0# is used by the processor to request the bus. The arbitration
is done between the processor (Symmetric Agent) and GMCH (High
Priority Agent).
Arbitration Request signal for the second die.
BR1#
58
Input/
Output
BR1# is connected to the first die within the package, allowing two
dies within quad-core parts to artitrite for the bus. This pin is
fundamentally provided for debug capabilities and should be left as
NC.
BSEL[2:0]
Output
BSEL[2:0] (Bus Select) are used to select the processor input clock
frequency. Table 4 defines the possible combinations of the signals
and the frequency associated with each combination. The required
frequency is determined by the processor, chipset and clock
synthesizer. All agents must operate at the same frequency.
COMP[3:0]
Analog
COMP[3:0] must be terminated on the system board using
precision (1% tolerance) resistors.
Datasheet
Package Mechanical Specifications and Pin Information
Table 14.
Signal Description (Sheet 3 of 9)
Name
Type
Description
D[63:0]# (Data) are the data signals. These signals provide a
64-bit data path between the FSB agents, and must connect the
appropriate pins on both agents. The data driver asserts DRDY# to
indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will thus be driven four
times in a common clock period. D[63:0]# are latched off the
falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group
of 16 data signals correspond to a pair of one DSTBP# and one
DSTBN#. The following table shows the grouping of data signals to
data strobes and DINV#.
Quad-Pumped Signal Groups
D[63:0]#
Input/
Output
Data Group
DSTBN#/
DSTBP#
DINV#
D[15:0]#
0
0
D[31:16]#
1
1
D[47:32]#
2
2
D[63:48]#
3
3
Furthermore, the DINV# pins determine the polarity of the data
signals. Each group of 16 data signals corresponds to one DINV#
signal. When the DINV# signal is active, the corresponding data
group is inverted and therefore sampled active high.
DBR#
Output
DBR# (Data Bus Reset) is used only in processor systems where
no debug port is implemented on the system board. DBR# is used
by a debug port interposer so that an in-target probe can drive
system reset. If a debug port is implemented in the system, DBR#
is a no connect in the system. DBR# is not a processor signal.
DBSY#
Input/
Output
DBSY# (Data Bus Busy) is asserted by the agent responsible for
driving data on the FSB to indicate that the data bus is in use. The
data bus is released after DBSY# is deasserted. This signal must
connect the appropriate pins on both FSB agents.
Input
DEFER# is asserted by an agent to indicate that a transaction
cannot be ensured in-order completion. Assertion of DEFER# is
normally the responsibility of the addressed memory or input/
output agent. This signal must connect the appropriate pins of both
FSB agents.
DEFER#
Datasheet
59
Package Mechanical Specifications and Pin Information
Table 14.
Signal Description (Sheet 4 of 9)
Name
Type
Description
DINV[3:0]# (Data Bus Inversion) are source synchronous and
indicate the polarity of the D[63:0]# signals. The DINV[3:0]#
signals are activated when the data on the data bus is inverted.
The bus agent will invert the data bus signals if more than half the
bits, within the covered group, would change level in the next
cycle.
DINV[3:0]#
Input/
Output
DINV[3:0]# Assignment To Data Bus
Bus Signal
Data Bus Signals
DINV[3]#
D[63:48]#
DINV[2]#
D[47:32]#
DINV[1]#
D[31:16]#
DINV[0]#
D[15:0]#
DPRSTP#
Input
DPRSTP#, when asserted on the platform, causes the processor to
transition from the Deep Sleep State to the Deeper Sleep state or
C6 state. To return to the Deep Sleep State, DPRSTP# must be
deasserted. DPRSTP# is driven by the ICH9M chipset.
DPSLP#
Input
DPSLP# when asserted on the platform causes the processor to
transition from the Sleep State to the Deep Sleep state. To return
to the Sleep State, DPSLP# must be deasserted. DPSLP# is driven
by the ICH9M chipset.
DPWR#
Input/
Output
DPWR# is a control signal used by the chipset to reduce power on
the processor data bus input buffers. The processor drives this pin
during dynamic FSB frequency switching.
DRDY#
Input/
Output
DRDY# (Data Ready) is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-common
clock data transfer, DRDY# may be deasserted to insert idle clocks.
This signal must connect the appropriate pins of both FSB agents.
Data strobe used to latch in D[63:0]#.
DSTBN[3:0]#
Input/
Output
Signals
Associated Strobe
D[15:0]#, DINV[0]#
DSTBN[0]#
D[31:16]#, DINV[1]#
DSTBN[1]#
D[47:32]#, DINV[2]#
DSTBN[2]#
D[63:48]#, DINV[3]#
DSTBN[3]#
Data strobe used to latch in D[63:0]#.
DSTBP[3:0]#
60
Input/
Output
Signals
Associated Strobe
D[15:0]#, DINV[0]#
DSTBP[0]#
D[31:16]#, DINV[1]#
DSTBP[1]#
D[47:32]#, DINV[2]#
DSTBP[2]#
D[63:48]#, DINV[3]#
DSTBP[3]#
Datasheet
Package Mechanical Specifications and Pin Information
Table 14.
Signal Description (Sheet 5 of 9)
Name
FERR#/PBE#
Type
Output
Description
FERR# (Floating-point Error)/PBE# (Pending Break Event) is a
multiplexed signal and its meaning is qualified with STPCLK#.
When STPCLK# is not asserted, FERR#/PBE# indicates a floating
point when the processor detects an unmasked floating-point error.
FERR# is similar to the ERROR# signal on the Intel® 387
coprocessor, and is included for compatibility with systems using
Microsoft MS-DOS*-type floating-point error reporting. When
STPCLK# is asserted, an assertion of FERR#/PBE# indicates that
the processor has a pending break event waiting for service. The
assertion of FERR#/PBE# indicates that the processor should be
returned to the Normal state. When FERR#/PBE# is asserted,
indicating a break event, it will remain asserted until STPCLK# is
deasserted. Assertion of PREQ# when STPCLK# is active will also
cause an FERR# break event.
For additional information on the pending break event functionality,
including identification of support of the feature and enable/disable
information, refer to Volumes 3A and 3B of the Intel® 64 and IA32 Architectures Software Developer's Manuals and the Intel®
Processor Identification and CPUID Instruction application note.
GTLREF
Input
GTLREF determines the signal reference level for AGTL+ input pins.
GTLREF should be set at 2/3 VCCP. GTLREF is used by the AGTL+
receivers to determine if a signal is a logical 0 or logical 1.
Refer to the appropriate platform design guide for details on
GTLREF implementation.
GTL reference level for AGTL+ input pins of the second die.
GTLREF_2
Input
Refer to the appropriate platform design guide for details on
GTLREF implementation.
This pin can be used as GTLREF_2 disconnect circuit control signal.
GTLREF_CONT
ROL
Input/
Output
HIT#
Input/
Output
HITM#
Input/
Output
IERR#
Datasheet
Output
GTLREF_2 maps out to a reserved pin on Intel® CoreTM2 Duo
Processor, for Dual Core and quad-core interchangeable
motherboard, GTLREF_CONTROL can be used as a control signal
for a circuit that will automaticlly switch between Dual Core and
quad-core modes.
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction
snoop operation results. Either FSB agent may assert both HIT#
and HITM# together to indicate that it requires a snoop stall that
can be continued by reasserting HIT# and HITM# together.
IERR# (Internal Error) is asserted by the processor as the result of
an internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the FSB. This transaction may
optionally be converted to an external error signal (e.g., NMI) by
system core logic. The processor will keep IERR# asserted until the
assertion of RESET#, BINIT#, or INIT#.
61
Package Mechanical Specifications and Pin Information
Table 14.
Signal Description (Sheet 6 of 9)
Name
IGNNE#
Type
Description
Input
IGNNE# (Ignore Numeric Error) is asserted to force the processor
to ignore a numeric error and continue to execute non-control
floating-point instructions. If IGNNE# is deasserted, the processor
generates an exception on a non-control floating-point instruction
if a previous floating-point instruction caused an error. IGNNE# has
no effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition
of this signal following an input/output write instruction, it must be
valid along with the TRDY# assertion of the corresponding input/
output Write bus transaction.
INIT#
Input
INIT# (Initialization), when asserted, resets integer registers
inside the processor without affecting its internal caches or
floating-point registers. The processor then begins execution at the
power-on Reset vector configured during power-on configuration.
The processor continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal. However, to ensure
recognition of this signal following an input/output write
instruction, it must be valid along with the TRDY# assertion of the
corresponding input/output write bus transaction. INIT# must
connect the appropriate pins of both FSB agents.
If INIT# is sampled active on the active-to-inactive transition of
RESET#, then the processor executes its Built-in Self-Test (BIST).
LINT[1:0]
Input
LINT[1:0] (Local APIC Interrupt) must connect the appropriate
pins of all APIC Bus agents. When the APIC is disabled, the LINT0
signal becomes INTR, a maskable interrupt request signal, and
LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are
backward-compatible with the signals of those names on the
Pentium processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS
programming of the APIC register space to be used either as NMI/
INTR or LINT[1:0]. Because the APIC is enabled by default after
Reset, operation of these pins as LINT[1:0] is the default
configuration.
62
LOCK#
Input/
Output
PRDY#
Output
PREQ#
Input
LOCK# indicates to the system that a transaction must occur
atomically. This signal must connect the appropriate pins of both
FSB agents. For a locked sequence of transactions, LOCK# is
asserted from the beginning of the first transaction to the end of
the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of
the FSB, it will wait until it observes LOCK# deasserted. This
enables symmetric agents to retain ownership of the FSB
throughout the bus locked operation and ensure the atomicity of
lock.
Probe Ready signal used by debug tools to determine processor
debug readiness.
Probe Request signal used by debug tools to request debug
operation of the processor.
Datasheet
Package Mechanical Specifications and Pin Information
Table 14.
Signal Description (Sheet 7 of 9)
Name
PROCHOT#
Type
Input/
Output
Description
As an output, PROCHOT# (Processor Hot) will go active when the
processor temperature monitoring sensor detects that the
processor has reached its maximum safe operating temperature.
This indicates that the processor Thermal Control Circuit (TCC) has
been activated, if enabled. As an input, assertion of PROCHOT# by
the system will activate the TCC, if enabled. The TCC will remain
active until the system deasserts PROCHOT#.
By default PROCHOT# is configured as an output. The processor
must be enabled via the BIOS for PROCHOT# to be configured as
bidirectional.
Refer to the appropriate platform design guide for termination
requirements.
This signal may require voltage translation on the motherboard.
PSI#
PWRGOOD
Output
Input
Processor Power Status Indicator signal. This signal is asserted
when the processor is both in the normal state (HFM to LFM) and in
lower power states (Deep Sleep and Deeper Sleep).
PWRGOOD (Power Good) is a processor input. The processor
requires this signal to be a clean indication that the clocks and
power supplies are stable and within their specifications. ‘Clean’
implies that the signal remains low (capable of sinking leakage
current), without glitches, from the time that the power supplies
are turned on until they come within specification. The signal must
then transition monotonically to a high state. Rise time and
monotonicity requirements are shown in Table 29. Figure 21
illustrates the relationship of PWRGOOD to the RESET# signal.
PWRGOOD can be driven inactive at any time, but clocks and
power must again be stable before a subsequent rising edge of
PWRGOOD. It must also meet the minimum pulse width
specification in Table 29, and be followed by a 2 ms (minimum)
RESET# pulse.
The PWRGOOD signal must be supplied to the processor; it is used
to protect internal circuits against voltage sequencing issues. It
should be driven high throughout boundary scan operation.
REQ[4:0]#
RESET#
Input/
Output
Input
REQ[4:0]# (Request Command) must connect the appropriate pins
of both FSB agents. They are asserted by the current bus owner to
define the currently active transaction type. These signals are
source synchronous to ADSTB[0]#.
Asserting the RESET# signal resets the processor to a known state
and invalidates its internal caches without writing back any of their
contents. For a power-on Reset, RESET# must stay active for at
least two milliseconds after VCC and BCLK have reached their
proper specifications. On observing active RESET#, both FSB
agents will deassert their outputs within two clocks. All processor
straps must be valid within the specified setup time before RESET#
is deasserted.
Refer to the appropriate platform design guide for termination
requirements and implementation details. There is a 55 Ω
(nominal) on die pull-up resistor on this signal.
RS[2:0]#
Datasheet
Input
RS[2:0]# (Response Status) are driven by the response agent (the
agent responsible for completion of the current transaction), and
must connect the appropriate pins of both FSB agents.
63
Package Mechanical Specifications and Pin Information
Table 14.
Signal Description (Sheet 8 of 9)
Name
RSVD
SLP#
SMI#
Type
Description
Reserved/
No
Connect
These pins are RESERVED and must be left unconnected on the
board. However, it is recommended that routing channels to these
pins on the board be kept open for possible future use.
Input
SLP# (Sleep), when asserted in Stop-Grant state, causes the
processor to enter the Sleep state. During Sleep state, the
processor stops providing internal clock signals to all units, leaving
only the Phase-Locked Loop (PLL) still operating. Processors in this
state will not recognize snoops or interrupts. The processor will
recognize only assertion of the RESET# signal, deassertion of
SLP#, and removal of the BCLK input while in Sleep state. If SLP#
is deasserted, the processor exits Sleep state and returns to StopGrant state, restarting its internal clock signals to the bus and
processor core units. If DPSLP# is asserted while in the Sleep
state, the processor will exit the Sleep state and transition to the
Deep Sleep state.
Input
SMI# (System Management Interrupt) is asserted asynchronously
by system logic. On accepting a System Management Interrupt,
the processor saves the current state and enters System
Management Mode (SMM). An SMI Acknowledge transaction is
issued and the processor begins program execution from the SMM
handler.
If an SMI# is asserted during the deassertion of RESET#, then the
processor will tristate its outputs.
64
STPCLK#
Input
STPCLK# (Stop Clock), when asserted, causes the processor to
enter a low power Stop-Grant state. The processor issues a StopGrant Acknowledge transaction, and stops providing internal clock
signals to all processor core units except the FSB and APIC units.
The processor continues to snoop bus transactions and service
interrupts while in Stop-Grant state. When STPCLK# is deasserted,
the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus
clock; STPCLK# is an asynchronous input.
TCK
Input
TCK (Test Clock) provides the clock input for the processor Test Bus
(also known as the Test Access Port).
TDI
Input
TDI (Test Data In) transfers serial test data into the first die. TDI
provides the serial input needed for JTAG specification support.
TDI_M
Input
TDI_M (Test Data In) transfers serial test data into the second die.
TDI_M provides the serial input needed for JTAG specification
support. Connect to TDO_M on the platform.
TDO
Output
TDO (Test Data Out) transfers serial test data out of the second
die. TDO provides the serial output needed for JTAG specification
support.
TDO_M
Output
TDO_M (Test Data Out) transfers serial test data out of the first
die. TDO_M provides the serial output needed for JTAG
specification support. Connect to TDI_M on the platform.
Datasheet
Package Mechanical Specifications and Pin Information
Table 14.
Signal Description (Sheet 9 of 9)
Name
Type
Description
TEST1,
TEST2,
TEST3,
TEST4,
Input
Refer to the appropriate platform design guide for further TEST1,
TEST2, TEST3, TEST4, TEST5, TEST6 and TEST7 termination
requirements and implementation details.
Output
The processor protects itself from catastrophic overheating by use
of an internal thermal sensor. This sensor is set well above the
normal operating temperature to ensure that there are no false
trips. The processor will stop all execution when the junction
temperature exceeds approximately 125 °C. This is signalled to the
system by the THERMTRIP# (Thermal Trip) pin.
TEST5,
TEST6
TEST7
THERMTRIP#
THRMDA
Other
Thermal Diode Anode.
THRMDA_2
Other
Thermal Diode Anode of the second die.
THRMDC
Other
Thermal Diode Cathode.
THRMDC_2
Other
Thermal Diode Cathode of the second die.
TMS
Input
TMS (Test Mode Select) is a JTAG specification support signal used
by debug tools.
TRDY#
Input
TRDY# (Target Ready) is asserted by the target to indicate that it
is ready to receive a write or implicit writeback data transfer.
TRDY# must connect the appropriate pins of both FSB agents.
TRST#
Input
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset.
VCC
Input
Processor core power supply.
VCCA
Input
VCCA provides isolated power for the internal processor core PLLs.
VCCP
Input
VCCSENSE
VID[6:0]
VSS
VSSSENSE
Datasheet
Processor I/O Power Supply.
Output
VCCSENSE together with VSSSENSE are voltage feedback signals
that control the 2.1 mΩ loadline at the processor die. It should be
used to sense voltage near the silicon with little noise.
Output
VID[6:0] (Voltage ID) pins are used to support automatic selection
of power supply voltages (VCC). Unlike some previous generations
of processors, these are CMOS signals that are driven by the
processor. The voltage supply for these pins must be valid before
the VR can supply VCC to the processor. Conversely, the VR output
must be disabled until the voltage supply for the VID pins becomes
valid. The VID pins are needed to support the processor voltage
specification variations. See Table 3 for definitions of these pins.
The VR must supply the voltage that is requested by the pins, or
disable itself.
Input
Output
Processor core ground node.
VSSSENSE together with VCCSENSE are voltage feedback signals
that control the 2.1-mΩ loadline at the processor die. It should be
used to sense ground near the silicon with little noise.
65
Package Mechanical Specifications and Pin Information
Table 15.
New Pins for the Quad-Core Mobile Processor
Pin Name
Pin#
Description
BPM_2[0]#
N5
BPM_2[1]#
M4
BPM_2[2]#
B2
BPM_2[3]#
AE8
BPM_2[3:0]# (Breakpoint Monitor) are breakpoint and performance
monitor signals of the second die. They are outputs from the
processor that indicate the status of breakpoints and programmable
counters used for monitoring processor performance. BPM_2[3:0]#
should connect the appropriate pins of all processor FSB agents.This
includes debug or performance monitoring tools.
Arbitration Request signal for the second die.
BR1#
AA7
GTLREF_2
D22
BR1# is connected to the first die within the package, allowing two
dies within quad-core parts to artitrite for the bus. This pin is
fundamentally provided for debug capabilities and should be left as a
NC.
GTL reference level for AGTL+ input pins of the second die.
This pin can be used as GTLREF_2 disconnect circuit control signal.
GTLREF_CONTROL
F8
GTLREF_2 maps out to a reserved pin on Intel Core 2 Duo mobile
processor, for dual-core and quad-core interchangeable
motherboard,GTLREF_CONTROL can be used as a control signal for a
circuit that will automaticlly switch between Dual Core and quadcore modes.
RSVD
AC8
RSVD
AA8
RSVD
D8
TDI_M
F6
TDI_M (Test Data In) transfers serial test data into the second die.
TDI_M provides the serial input needed for JTAG specification
support. Connect to TDO_M on the platform.
TDO_M
D3
TDO_M (Test Data Out) transfers serial test data out of the first die.
TDO_M provides the serial output needed for JTAG specification
support. Connect to TDI_M on the platform.
THRMDA_2
T2
Thermal Diode Anode of the second die.
THRMDC_2
V3
Thermal Diode Cathode of the second die.
These pins are RESERVED and must be left unconnected on the
board. However, it is recommended that routing channels to these
pins on the board be kept open for possible future use.
§
66
Datasheet
Thermal Specifications and Design Considerations
5
Thermal Specifications and
Design Considerations
The processor requires a thermal solution to maintain temperatures within operating
limits.
Caution:
Operating the processor outside these operating limits may result in permanent
damage to the processor and potentially other components in the system.
Maintaining the proper thermal environment is key to reliable, long-term system
operation. A complete thermal solution includes both component and system-level
thermal management features. To allow for the optimal operation and long-term
reliability of Intel processor-based systems, the system/processor thermal solution
should be designed so the processor remains within the minimum and maximum
junction temperature (TJ) specifications at the corresponding thermal design power
(TDP) value listed in Table 16. Analysis indicates that real applications are unlikely to
cause the processor to consume the theoretical maximum power dissipation for
sustained time periods.
Table 16.
Processor Power Specifications
Symbol
Processor
Number
QX9300
TDP
Q9100
Q9000
Symbol
PAH,
PSGNT
Core Frequency & Voltage
Thermal Design
Power
Notes
W
1, 4,
5, 6
45
2.53 GHz & VCCHFM
2.26 GHz & VCCHFM
2.0 GHz & VCCHFM
1.60 GHz & VCCLFM
Parameter
Unit
45
45
35
Min
Typ
Max
Unit
Notes
—
—
19.4
W
2, 5, 7
W
2, 5, 7
W
2, 5, 8
Auto Halt, Stop Grant Power
at HFM VCC
at LFM VCC
14.5
Sleep Power
PSLP
at HFM VCC
—
—
at LFM VCC
18.6
14.1
Deep Sleep Power
PDSLP
at HFM VCC
—
—
at LFM VCC
7.9
7.1
PDPRSLP
Deeper Sleep Power
—
—
4.0
W
2, 8
TJ
Junction Temperature
0
—
100
°C
3, 4
NOTES:
1.
The TDP specification should be used to design the processor thermal solution. The TDP is
not the maximum theoretical power the processor can generate.
2.
Not 100% tested. These power specifications are determined by characterization of the
processor currents at higher temperatures and extrapolating the values for the
temperature indicated.
3.
As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal
Monitor’s automatic mode is used to indicate that the maximum TJ has been reached.
Refer to Section 5.1 for details.
4.
The Intel Thermal Monitor automatic mode must be enabled for the processor to operate
within specifications.
Datasheet
67
Thermal Specifications and Design Considerations
5.
6.
7.
8.
5.1
Processor TDP requirements in Intel Dynamic Acceleration mode are lesser than TDP in
HFM.
At Tj of 100oC
At Tj of 50oC
At Tj of 35oC
Monitoring Die Temperature
The processor incorporates three methods of monitoring die temperature:
• Thermal Diode
• Intel® Thermal Monitor
• Digital Thermal Sensor
Note:
The Intel Thermal Monitor (detailed in Section 5.1.2) must be used to determine when
the maximum specified processor junction temperature has been reached.
5.1.1
Thermal Diode
Intel’s processors utilize an SMBus thermal sensor to read back the voltage/current
characteristics of a substrate PNP transistor. Since these characteristics are a function
of temperature, in principle one can use these parameters to calculate silicon
temperature values. For older silicon process technologies (i.e., Intel® Core™2 Duo
mobile processors on 65nm process), it is possible to simplify the voltage/current and
temperature relationships by treating the substrate transistor as though it were a
simple diffusion diode. In this case, the assumption is that the beta of the transistor
does not impact the calculated temperature values. The resultant “diode” model
essentially predicts a quasi linear relationship between the base/emitter voltage
differential of the PNP transistor and the applied temperature (one of the
proportionality constants in this relationship is processor specific, and is known as the
diode ideality factor). Realization of this relationship is accomplished with the SMBus
thermal sensor that is connected to the transistor.
The quad-core processor, however, is built on Intel’s advanced 45-nm processor
technology. Due to this new highly advanced processor technology, it is no longer
possible to model the substrate transistor as a simple diode. To accurately calculate
silicon temperature one must use a full bi-polar junction transistor-type model. In this
model, the voltage/current and temperature characteristics include an additional
process dependant parameter which is known as the transistor “beta”. System
designers should be aware that the current thermal sensors on Santa Rosa platforms
may not be configured to account for “beta” and should work with their SMB thermal
sensor vendors to ensure they have a part capable of reading the thermal diode in BJT
model.
Offset between the thermal diode-based temperature reading and the Intel Thermal
Monitor reading may be characterized using the Intel Thermal Monitor’s automatic
mode activation of the thermal control circuit. This temperature offset must be taken
into account when using the processor thermal diode to implement power management
events. This offset is different than the diode Toffset value programmed into the
processor Model-Specific Register (MSR).
Table 17 to Table 18 provide the diode interface and transistor model specifications.
68
Datasheet
Thermal Specifications and Design Considerations
Table 17.
Table 18.
Thermal Diode Interface
Signal Name
Pin/Ball Number
Signal Description
THERMDA
A24
Thermal diode anode
THERMDC
B25
Thermal diode cathode
THERMDA_2
T2
Thermal diode anode of the second die
THERMDC_2
V3
Thermal diode cathode of the second die
Thermal Diode Parameters Using Transistor Model
Symbol
Parameter
Min
Typ
Max
Unit
Notes
IFW
Forward Bias Current
5
—
200
μA
1
IE
Emitter Current
5
—
200
μA
1
nQ
Transistor Ideality
0.997
1.001
1.008
0.1
0.4
0.5
Series Resistance
3.0
4.5
7.0
Beta
RT
2, 3, 4
2, 3
Ω
2
NOTES:
1.
Intel does not support or recommend operation of the thermal diode under reverse bias.
2.
Characterized across a temperature range of 50-100°C.
3.
Not 100% tested. Specified by design characterization.
4.
The ideality factor, nQ, represents the deviation from ideal transistor model behavior as
exemplified by the equation for the collector current:
IC = IS * (e qVBE/nQkT –1)
where IS = saturation current, q = electronic charge, VBE = voltage across the transistor
base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute
temperature (Kelvin).
5.1.2
Intel® Thermal Monitor
The Intel® Thermal Monitor helps control the processor temperature by activating the
TCC (Thermal Control Circuit) when the processor silicon reaches its maximum
operating temperature. The temperature at which the Intel Thermal Monitor activates
the TCC is not user configurable. Bus traffic is snooped in the normal manner and
interrupt requests are latched (and serviced during the time that the clocks are on)
while the TCC is active.
With a properly designed and characterized thermal solution, it is anticipated that the
TCC would only be activated for very short periods of time when running the most
power-intensive applications. The processor performance impact due to these brief
periods of TCC activation is expected to be minor and hence not detectable. An underdesigned thermal solution that is not able to prevent excessive activation of the TCC in
the anticipated ambient environment may cause a noticeable performance loss and
may affect the long-term reliability of the processor. In addition, a thermal solution that
is significantly under designed may not be capable of cooling the processor even when
the TCC is active continuously.
The Intel Thermal Monitor controls the processor temperature by modulating (starting
and stopping) the processor core clocks or by initiating an Enhanced Intel SpeedStep
Technology transition when the processor silicon reaches its maximum operating
Datasheet
69
Thermal Specifications and Design Considerations
temperature. The Intel Thermal Monitor uses two modes to activate the TCC: automatic
mode and on-demand mode. If both modes are activated, automatic mode takes
precedence.
There are two automatic modes called Intel Thermal Monitor 1 (TM1) and Intel Thermal
Monitor 2 (TM2). These modes are selected by writing values to the MSRs of the
processor. After automatic mode is enabled, the TCC will activate only when the
internal die temperature reaches the maximum allowed value for operation.
When TM1 is enabled and a high temperature situation exists, the clocks will be
modulated by alternately turning the clocks off and on at a 50% duty cycle. Cycle times
are processor speed-dependent and will decrease linearly as processor core frequencies
increase. Once the temperature has returned to a non-critical level, modulation ceases
and TCC goes inactive. A small amount of hysteresis has been included to prevent rapid
active/inactive transitions of the TCC when the processor temperature is near the trip
point. The duty cycle is factory configured and cannot be modified. Also, automatic
mode does not require any additional hardware, software drivers, or interrupt handling
routines. Processor performance will be decreased by the same amount as the duty
cycle when the TCC is active.
When TM2 is enabled and a high temperature situation exists, the processor will
perform an Enhanced Intel SpeedStep Technology transition to the LFM. When the
processor temperature drops below the critical level, the processor will make an
Enhanced Intel SpeedStep Technology transition to the last requested operating point.
Intel recommends TM1 and TM2 be enabled on the processors.
TM1 and TM2 can co-exist within the processor. If both TM1 and TM2 bits are enabled in
the auto-throttle MSR, TM2 takes precedence over TM1. However, if Force TM1 over
TM2 is enabled in MSRs via BIOS and TM2 is not sufficient to cool the processor below
the maximum operating temperature, then TM1 will also activate to help cool down the
processor.
If a processor load-based Enhanced Intel SpeedStep Technology transition (through
MSR write) is initiated when a TM2 period is active, there are two possible results:
1. If the processor load-based Enhanced Intel SpeedStep Technology transition target
frequency is higher than the TM2 transition-based target frequency, the processor
load-based transition will be deferred until the TM2 event has been completed.
2. If the processor load-based Enhanced Intel SpeedStep Technology transition target
frequency is lower than the TM2 transition-based target frequency, the processor
will transition to the processor load-based Enhanced Intel SpeedStep Technology
target frequency point.
The TCC may also be activated via on-demand mode. If bit 4 of the ACPI Intel Thermal
Monitor control register is written to a 1, the TCC will be activated immediately
independent of the processor temperature. When using on-demand mode to activate
the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the
same ACPI Intel Thermal Monitor control register. In automatic mode, the duty cycle is
fixed at 50% on, 50% off, however in on-demand mode, the duty cycle can be
programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments.
On-demand mode may be used at the same time automatic mode is enabled, however,
if the system tries to enable the TCC via on-demand mode at the same time automatic
mode is enabled and a high temperature condition exists, automatic mode will take
precedence.
An external signal, PROCHOT# (processor hot) is asserted when the processor detects
that its temperature is above the thermal trip point. Bus snooping and interrupt
latching are also active while the TCC is active.
70
Datasheet
Thermal Specifications and Design Considerations
Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also
includes one ACPI register, one performance counter register, three MSR, and one I/O
pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal
Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt
upon the assertion or deassertion of PROCHOT#.
PROCHOT# will not be asserted when the processor is in the Stop Grant,
Sleep, and Deep Sleep low power states, hence the thermal diode reading
must be used as a safeguard to maintain the processor junction temperature
within maximum specification. If the platform thermal solution is not able to
maintain the processor junction temperature within the maximum specification, the
system must initiate an orderly shutdown to prevent damage. If the processor enters
one of the above low power states with PROCHOT# already asserted, PROCHOT# will
remain asserted until the processor exits the low power state and the processor
junction temperature drops below the thermal trip point.
If Thermal Monitor automatic mode is disabled, the processor will be operating out of
specification. Regardless of enabling the automatic or on-demand modes, in the event
of a catastrophic cooling failure, the processor will automatically shut down when the
silicon has reached a temperature of approximately 125 °C. At this point the
THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor
activity and does not generate any bus cycles. When THERMTRIP# is asserted, the
processor core voltage must be shut down within the time specified in Chapter 3.
In all cases the Intel Thermal Monitor feature must be enabled for the processor to
remain within specification.
5.1.3
Digital Thermal Sensor
The processor also contains an on-die Digital Thermal Sensor (DTS) that can be read
via an MSR (no I/O interface). Each core of the processor will have a unique digital
thermal sensor whose temperature is accessible via the processor MSRs. The DTS is the
preferred method of reading the processor die temperature since it can be located
much closer to the hottest portions of the die and can thus more accurately track the
die temperature and potential activation of processor core clock modulation via the
Thermal Monitor. The DTS is only valid while the processor is in the normal operating
state (the Normal package level low power state).
Unlike traditional thermal devices, the DTS outputs a temperature relative to the
maximum supported operating temperature of the processor (TJ,max). It is the
responsibility of software to convert the relative temperature to an absolute
temperature. The temperature returned by the DTS will always be at or below TJ,max.
Catastrophic temperature conditions are detectable via an Out Of Specification status
bit. This bit is also part of the DTS MSR. When this bit is set, the processor is operating
out of specification and immediate shutdown of the system should occur. The processor
operation and code execution is not ensured once the activation of the Out of
Specification status bit is set.
The DTS-relative temperature readout corresponds to the Thermal Monitor (TM1/TM2)
trigger point. When the DTS indicates maximum processor core temperature has been
reached, the TM1 or TM2 hardware thermal control mechanism will activate. The DTS
and TM1/TM2 temperature may not correspond to the thermal diode reading since the
thermal diode is located in a separate portion of the die and there is a thermal gradient
between the individual core DTS. Additionally, the thermal gradient from DTS to
thermal diode can vary substantially due to changes in processor power, mechanical
and thermal attach, and software application. The system designer is required to use
the DTS to ensure proper operation of the processor within its temperature operating
specifications.
Datasheet
71
Thermal Specifications and Design Considerations
Changes to the temperature can be detected via two programmable thresholds located
in the processor MSRs. These thresholds have the capability of generating interrupts
via the core's local APIC. Refer to the Intel® 64 and IA-32 Architectures Software
Developer's Manuals for specific register and programming details.
5.2
PROCHOT# Signal Pin
An external signal, PROCHOT# (processor hot), is asserted when the processor die
temperature has reached its maximum operating temperature. If TM1 or TM2 is
enabled, then the TCC will be active when PROCHOT# is asserted. The processor can
be configured to generate an interrupt upon the assertion or deassertion of
PROCHOT#. Refer to the an interrupt upon the assertion or deassertion of PROCHOT#.
Refer to the Intel® 64 and IA-32 Architectures Software Developer's Manuals for
specific register and programming details.
The processor implements a bi-directional PROCHOT# capability to allow system
designs to protect various components from overheating situations. The PROCHOT#
signal is bi-directional in that it can either signal when the processor has reached its
maximum operating temperature or be driven from an external source to activate the
TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal
protection of system components.
Only a single PROCHOT# pin exists at a package level of the processor. When any
core's thermal sensor trips, PROCHOT# signal will be driven by the processor package.
If only TM1 is enabled, PROCHOT# will be asserted regardless of which core is above its
TCC temperature trip point, and all cores will have their core clocks modulated. If TM2
is enabled then, regardless of which core(s) are above the TCC temperature trip point,
all cores will enter the lowest programmed TM2 performance state. It is important to
note that Intel recommends both TM1 and TM2 to be enabled.
When PROCHOT# is driven by an external agent, if only TM1 is enabled on all cores,
then all processor cores will have their core clocks modulated. If TM2 is enabled on all
cores, then all processor cores will enter the lowest programmed TM2 performance
state. It should be noted that Force TM1 on TM2, enabled via BIOS, does not have any
effect on external PROCHOT#. If PROCHOT# is driven by an external agent when TM1,
TM2, and Force TM1 on TM2 are all enabled, then the processor will still apply only
TM2.
PROCHOT# may be used for thermal protection of voltage regulators (VR). System
designers can create a circuit to monitor the VR temperature and activate the TCC
when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low)
and activating the TCC, the VR will cool down as a result of reduced processor power
consumption. Bi-directional PROCHOT# can allow VR thermal designs to target
maximum sustained current instead of maximum current. Systems should still provide
proper cooling for the VR and rely on bi-directional PROCHOT# only as a backup in case
of system cooling failure. The system thermal design should allow the power delivery
circuitry to operate within its temperature specification even while the processor is
operating at its TDP. With a properly designed and characterized thermal solution, it is
anticipated that bi-directional PROCHOT# would only be asserted for very short periods
of time when running the most power-intensive applications. An under-designed
thermal solution that is not able to prevent excessive assertion of PROCHOT# in the
anticipated ambient environment may cause a noticeable performance loss.
§
72
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