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WM8997
Audio Hub CODEC for Mobile Applications
DESCRIPTION
[1]
The WM8997 is a compact, high-performance audio hub
CODEC with SLIMbus interfacing, for smartphones, tablets
and other portable audio devices.
The WM8997 digital core combines fixed-function signal
processing blocks with a fully-flexible, all-digital audio mixing
and routing engine, for tremendous use-case flexibility.
Signal processing blocks include filters, EQ, dynamics
processors and sample rate converters.
A SLIMbus interface supports multi-channel audio paths and
host control register access. Multiple sample rates are
supported concurrently via the SLIMbus interface. Two
further digital audio interfaces are provided, each supporting
a wide range of standard audio sample rates and serial
interface formats. Automatic sample rate detection enables
seamless wideband/narrowband voice call handover.
A stereo headphone driver provides stereo groundreferenced or mono BTL outputs, with noise levels as low as
3.2μVRMS for hi-fi quality line or headphone output. The
CODEC also features a mono 2W Class-D speaker output,
a dedicated BTL earpiece output and PDM for external
speaker amplifiers. A signal generator for controlling haptics
devices is included; vibe actuators can connect directly to
the Class-D speaker output, or else via an external driver on
the PDM output interface. All inputs, outputs and system
interfaces can function concurrently.
The WM8997 supports up to four microphone inputs, each
either analogue or PDM digital. Microphone activity
detection with interrupt is available. A smart accessory
interface supports most standard 3.5mm accessories.
Impedance sensing and measurement is provided for
external accessory and push-button detection.
The WM8997 power, clocking and output driver
architectures are all designed to maximise battery life in
voice, music and standby modes. Low-power ‘Sleep’ is
supported, with configurable wake-up events. The WM8997
is powered from a 1.8V external supply. A separate supply is
required for the Class D speaker driver (typically direct
connection to 4.2V battery).
Two integrated FLLs provide support for a wide range of
system clock frequencies. The WM8997 is configured using
the I2S or SLIMbus interfaces. The fully-differential internal
analogue architecture, minimal analogue signal paths and
on-chip RF noise filters ensure a very high degree of noise
immunity.
FEATURES



Audio hub CODEC for mobile applications
Digital audio processing core
-
Fully-flexible digital signal routing and mixing
-
Dynamic Range Control (compressor, limiter)
-
Fully parametric EQs
-
Low-pass / High-pass filters
- Multi-channel sample rate conversion
Integrated 4 channel 24-bit hi-fi audio hub CODEC
-



96dB SNR microphone input (48kHz)
- 102dB SNR headphone playback (48kHz)
Audio inputs
Up to 4 analogue or digital microphone inputs
- Single-ended or differential mic/line inputs
Multi-purpose headphone / earpiece / line output driver
-
Ground-referenced stereo output path
-
29mW into 32Ω load at 1% THD+N
-
100mW into 16Ω BTL load at 5% THD+N
-
6.5mW typical headphone playback power consumption
-
Pop suppression functions
- 3.2µVRMS noise floor (A-weighted)
Mono BTL earpiece output driver

2W mono Class D speaker output driver

- Direct drive of external haptics vibe actuators
Two-channel digital speaker (PDM) interface

SLIMbus® audio and control interface

2 full digital audio interfaces
-

Standard sample rates from 4kHz up to 192kHz
-
Ultrasonic accessory function support
-
TDM support on both AIFs
- 8 channel input and output on AIF1
Flexible clocking, derived from MCLKn, BCLKn or SLIMbus

2 low-power FLLs support reference clocks down to 32kHz

Advanced accessory detection functions

- Low-power standby mode and configurable wake-up
Configurable functions on 5 GPIO pins

Integrated LDO regulators and charge pumps

Support for single 1.8V supply operation

Small W-CSP package, 0.4mm pitch
APPLICATIONS

Smartphones and Multimedia handsets

Tablets and Mobile Internet Devices (MID)

General-purpose low-power audio CODEC hub
WOLFSON MICROELECTRONICS plc
Product Brief, April 2013, Rev 2.1
[1] This product is protected by Patents US 7,622,984, US 7,626,445, US 7,765,019 and GB 2,432,765
Copyright 2013 Wolfson Microelectronics plc
WM8997
Preliminary Technical Data
BLOCK DIAGRAM
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Product Brief, April 2013, Rev 2.1
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WM8997
Preliminary Technical Data
TABLE OF CONTENTS
DESCRIPTION ....................................................................................................... 1 FEATURES ............................................................................................................ 1 APPLICATIONS..................................................................................................... 1 BLOCK DIAGRAM ................................................................................................ 2 TABLE OF CONTENTS ......................................................................................... 3 PIN CONFIGURATION .......................................................................................... 4 ORDERING INFORMATION .................................................................................. 5 PIN DESCRIPTION ................................................................................................ 5 ABSOLUTE MAXIMUM RATINGS ........................................................................ 7 RECOMMENDED OPERATING CONDITIONS ..................................................... 8 ELECTRICAL CHARACTERISTICS ..................................................................... 9 TERMINOLOGY ............................................................................................................. 19 DEVICE DESCRIPTION ...................................................................................... 20 INTRODUCTION ............................................................................................................ 20 HI-FI AUDIO CODEC ..................................................................................................... 20 DIGITAL AUDIO CORE .................................................................................................. 21 DIGITAL INTERFACES .................................................................................................. 21 OTHER FEATURES ....................................................................................................... 22 RECOMMENDED EXTERNAL COMPONENTS.................................................. 23 PACKAGE DIMENSIONS .................................................................................... 24 IMPORTANT NOTICE ......................................................................................... 25 ADDRESS: ..................................................................................................................... 25 REVISION HISTORY ........................................................................................... 26 w
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WM8997
Preliminary Technical Data
PIN CONFIGURATION
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WM8997
Preliminary Technical Data
ORDERING INFORMATION
ORDER CODE
TEMPERATURE
RANGE
WM8997ECS/R
-40C to +85C
PACKAGE
MOISTURE
SENSITIVITY LEVEL
W-CSP
(Pb-free, Tape and reel)
PEAK SOLDERING
TEMPERATURE
MSL1
260C
Note:
Reel quantity = 5000
PIN DESCRIPTION
A description of each pin on the WM8997 is provided below.
Note that, where multiple pins share a common name, these pins should be tied together on the PCB.
PIN NO
NAME
TYPE
DESCRIPTION
H7
ADDR
Digital Input
Control interface (I2C) address select
A3, B3, B5,
C3, C4, C5,
C6, D4, D5,
D6, E1, E2,
E3, E4, E5,
F3, F4, H3
AGND
Supply
Analogue ground (Return path for AVDD)
G8
AIF1BCLK
Digital Input / Output
Audio interface 1 bit clock
H10
AIF1LRCLK
Digital Input / Output
Audio interface 1 left / right clock
J11
AIF1RXDAT
Digital Input
Audio interface 1 RX digital audio data
H9
AIF1TXDAT
Digital Output
Audio interface 1 TX digital audio data
J6
AIF2BCLK
Digital Input / Output
Audio interface 2 bit clock
G4
AIF2LRCLK
Digital Input / Output
Audio interface 2 left / right clock
H4
AIF2RXDAT
Digital Input
Audio interface 2 RX digital audio data
J5
AIF2TXDAT
Digital Output
Audio interface 2 TX digital audio data
B4, J3
AVDD
Supply
Analogue supply
B7
CP1CA
Analogue Output
Charge pump 1 fly-back capacitor pin
B8
CP1CB
Analogue Output
Charge pump 1 fly-back capacitor pin
A8
CP1VOUTN
Analogue Output
Charge pump 1 negative output decoupling pin
Charge pump 1 positive output decoupling pin
A7
CP1VOUTP
Analogue Output
C9
CP2CA
Analogue Output
Charge pump 2 fly-back capacitor pin
B9
CP2CB
Analogue Output
Charge pump 2 fly-back capacitor pin
A9
CP2VOUT
Analogue Output
Charge pump 2 output decoupling pin / Supply for LDO2
C8
CPGND
Supply
Charge pump 1 & 2 ground (Return path for CPVDD)
C7
CPVDD
Supply
Supply for Charge Pump 1 & 2
F6, F7, F8,
G5
DBVDD1
Supply
Digital buffer (I/O) supply (core functions and Audio Interface 1)
J4
DBVDD2
Supply
Digital buffer (I/O) supply (for Audio Interface 2)
J7
DCVDD
Supply
Digital core supply
G11, H5
DGND
Supply
Digital ground
(Return path for DCVDD, DBVDD1 and DBVDD2)
A5
EPOUTN
Analogue Output
Earpiece negative output
A4
EPOUTP
Analogue Output
Earpiece positive output
G7
GPIO1
Digital Input / Output
General Purpose pin GPIO1
G3
GPIO2
Digital Input / Output
General Purpose pin GPIO2
J9
GPIO3
Digital Input / Output
General Purpose pin GPIO3
General Purpose pin GPIO4
G6
GPIO4
Digital Input / Output
F10
GPIO5
Digital Input / Output
General Purpose pin GPIO5
B10
HPDETL
Analogue Input
Headphone left (HPOUTL) sense input
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WM8997
PIN NO
Preliminary Technical Data
NAME
TYPE
DESCRIPTION
A10
HPDETR
Analogue Input
Headphone right (HPOUTR) sense input
A11
HPOUTFB1/
Analogue Input
HPOUTL and HPOUTR ground feedback pin 1/
Microphone & accessory sense input 2
MICDET2
B6
HPOUTL
Analogue Output
A6
HPOUTR
Analogue Output
Right headphone output
C1
IN1LN/
Left channel negative differential MIC input /
DMICCLK1
Analogue Input /
Digital Output
IN1LP
Analogue Input
Left channel single-ended MIC input /
C2
Left headphone output
Digital MIC clock output 1
Left channel line input /
Left channel positive differential MIC input
D2
D3
Right channel negative differential MIC input /
DMICDAT1
Analogue input /
Digital Input
IN1RP
Analogue Input
Right channel single-ended MIC input /
IN1RN/
Digital MIC data input 1
Right channel line input /
Right channel positive differential MIC input
A1
A2
Left channel negative differential MIC input /
DMICCLK2
Analogue Input /
Digital Output
IN2LP
Analogue Input
Left channel single-ended MIC input /
IN2LN/
Digital MIC clock output 2
Left channel line input /
Left channel positive differential MIC input
B1
B2
Right channel negative differential MIC input /
DMICDAT2
Analogue input /
Digital Input
IN2RP
Analogue Input
Right channel single-ended MIC input /
IN2RN/
Digital MIC data input 2
Right channel line input /
Right channel positive differential MIC input
F11
IRQ
¯¯¯
Digital Output
Interrupt Request (IRQ) output (default is active low)
D9
JACKDET
Analogue Input
Jack detect input
E11
LDOENA
Digital Input
Enable pin for LDO1
D11
LDOVDD
Supply
Supply for LDO1
E10
LDOVOUT
Analogue Output
LDO1 output
G10
MCLK1
Digital Input
Master clock 1
F9
MCLK2
Digital Input
Master clock 2
C10
MICBIAS1
Analogue Output
Microphone bias 1
D10
MICBIAS2
Analogue Output
Microphone bias 2
C11
MICBIAS3
Analogue Output
Microphone bias 3
B11
MICDET1/
Analogue Input
Microphone & accessory sense input 1/
HPOUTL and HPOUTR ground feedback pin 2
HPOUTFB2
D1, E7, E8
MICVDD
Analogue Output
LDO2 output decoupling pin (generated internally by WM8997)
E9
RESET
¯¯¯¯¯¯
Digital Input
Digital Reset input (active low)
J10
SCLK
Digital Input
Control interface clock input
H8
SDA
Digital Input / Output
Control interface data input and output / acknowledge output
G9
SLIMCLK
Digital Input / Output
SLIM Bus Clock input / output
H11
SLIMDAT
Digital Input / Output
SLIM Bus Data input / output
J8
SPKCLK
Digital Output
Digital speaker (PDM) clock output
H6
SPKDAT
Digital Output
Digital speaker (PDM) data output
J1, J2
SPKGND
Supply
Speaker driver ground (Return path for SPKVDD)
G2, H2
SPKOUTN
Analogue Output
Speaker negative output
G1, H1
SPKOUTP
Analogue Output
Seaker positive output
F1, F2
SPKVDD
Supply
Speaker driver supply
D8
VREFC
Analogue Output
Bandgap reference decoupling capacitor connection
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WM8997
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020 for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
MIN
MAX
Supply voltages (DBVDD1, LDOVDD, AVDD, DCVDD, CPVDD)
CONDITION
-0.3V
+2.0V
Supply voltages (DBVDD2, MICVDD)
-0.3V
+4.0V
Supply voltages (SPKVDD)
-0.3V
+6.0V
Voltage range digital inputs (DBVDD1 domain)
AGND - 0.3V
DBVDD1 + 0.3V
Voltage range digital inputs (DBVDD2 domain)
AGND - 0.3V
DBVDD2 + 0.3V
Voltage range digital inputs (DMICDATn)
AGND - 3.3V
MICVDD + 0.3V
Voltage range analogue inputs (INnLN)
AGND - 0.3V
MICVDD + 0.3V
Voltage range analogue inputs (INnLP, INnRN, INnRP)
AGND - 3.3V
MICVDD + 0.3V
Ground (DGND, CPGND, SPKGND)
AGND - 0.3V
AGND + 0.3V
Operating temperature range, TA
-40ºC
+85ºC
Operating junction temperature, TJ
-40ºC
+125ºC
Storage temperature after soldering
-65ºC
+150ºC
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WM8997
Preliminary Technical Data
RECOMMENDED OPERATING CONDITIONS
PARAMETER
TYP
MAX
DCVDD
(≤24.576MHz clocking)
1.14
1.2
1.9
DCVDD
(>24.576MHz clocking)
1.71
1.8
1.9
Digital supply range (I/O)
DBVDD1
1.7
1.9
V
Digital supply range (I/O)
DBVDD2
1.7
3.47
V
LDO supply range
LDOVDD
1.7
1.8
1.9
V
CPVDD
1.7
1.8
SPKVDD
2.4
Digital supply range (Core)
See notes 3, 4, 5
Charge Pump supply range
Speaker supply range
SYMBOL
MIN
UNIT
V
1.9
V
5.5
V
Analogue supply range
AVDD
1.7
1.8
1.9
V
Microphone Bias supply
MICVDD
2.375
3.0
3.6
V
See note 6
Ground
Power supply rise time
DGND, AGND, CPGND,
SPKGND
0
All supplies
1
TA
-40
V
µs
See notes 7, 8, 9
Operating temperature range
85
°C
Notes:
1.
The grounds must always be within 0.3V of AGND.
2.
AVDD must be supplied before or simultaneously to DCVDD. DCVDD must not be powered if AVDD is not present.
There are no other power sequencing requirements.
3.
An internal LDO (powered by LDOVDD) can be used to provide the DCVDD supply.
4.
‘Sleep’ mode is supported when DCVDD is below the limits noted, provided AVDD and DBVDD1 are present.
5.
Under default conditions, digital core clocking rates above 24.576MHz are inhibited. The register-controlled clocking
limit should only be raised when the applicable DCVDD voltage is present.
6.
An internal Charge Pump and LDO (powered by CPVDD) provide the Microphone Bias supply; the MICVDD pin should
not be connected to an external supply.
7.
DCVDD and MICVDD minimum rise times do not apply when these domains are powered using the internal LDOs.
8.
The specified minimum power supply rise times assume a minimum decoupling capacitance of 100nF per pin.
However, Wolfson strongly advises that the recommended decoupling capacitors are present on the PCB and that
appropriate layout guidelines are observed.
9.
The specified minimum power supply rise times also assume a maximum PCB inductance of 10nH between
decoupling capacitor and pin.
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Product Brief, April 2013, Rev 2.1
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WM8997
Preliminary Technical Data
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = 1.8V,
With the exception of the condition(s) noted above, the following electrical characteristics are valid across the full range of
recommended operating conditions.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analogue Input Signal Level (IN1L, IN1R, IN2L, IN2R)
Full-scale input signal level
VINFS
Single-ended PGA input
Differential PGA input
0.5
VRMS
-6
dBV
1
VRMS
0
dBV
Notes:
1. The full-scale input signal level changes in proportion with AVDD. For differential input, it is calculated as AVDD / 1.8.
2. A 1.0VRMS differential signal equates to 0.5VRMS/-6dBV per input.
3. A sinusoidal input signal is assumed.
Test Conditions
º
TA = +25 C
With the exception of the condition(s) noted above, the following electrical characteristics are valid across the full range of
recommended operating conditions.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analogue Input Pin Characteristics (IN1LP, IN1LN, IN1RP, IN1RN, IN2LP, IN2LN, IN2RP, IN2RN)
Input resistance
RIN
Input capacitance
CIN
All PGA gain settings
10
12
k
5
pF
Test Conditions
The following electrical characteristics are valid across the full range of recommended operating conditions.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input Programmable Gain Amplifiers (PGAs)
Minimum programmable gain
0
dB
Maximum programmable gain
31
dB
1
dB
-12
dB
0
dB
1
dB
Programmable gain step size
Guaranteed monotonic
Headphone Output Programmable Gain Amplifiers (PGAs)
Minimum programmable gain
Maximum programmable gain
Programmable gain step size
Guaranteed monotonic
Earpiece Output Programmable Gain Amplifiers (PGAs)
Minimum programmable gain
-6
dB
Maximum programmable gain
+6
dB
1
dB
Programmable gain step size
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Guaranteed monotonic
Product Brief, April 2013, Rev 2.1
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WM8997
Preliminary Technical Data
Test Conditions
The following electrical characteristics are valid across the full range of recommended operating conditions.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Line / Headphone / Earpiece Output Driver (HPOUTL, HPOUTR)
Load resistance
Load capacitance
Normal operation
15
Device survival with load
applied indefinitely
0.1
Ω
Load = 10kΩ,
Normal Mode
500
Load = 10kΩ,
Mono Mode (BTL)
200
Load = 16Ω
DC offset at Load
pF
2
nF
Single-ended mode
0.1
0.2
mV
Differential (BTL) mode
0.2
0.5
Earpiece Output Driver (EPOUTP+EPOUTN)
Load resistance
Load capacitance
Normal operation
15
Device survival with load
applied indefinitely
0.1
Ω
Load = 10kΩ
200
Load = 16Ω
2
nF
0.5
mV
Load capacitance
200
pF
DC offset at Load
5
mV
SPKVDD leakage current
1
µA
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Product Brief, April 2013, Rev 2.1
DC offset at Load
0.2
pF
Speaker Output Driver (SPKOUTP+SPKOUTN)
Load resistance
3
Ω
10
WM8997
Preliminary Technical Data
Test Conditions
DBVDD1 = DBVDD2 = LDOVDD = CPVDD = AVDD = 1.8V,
DCVDD = 1.2V (powered from LDO1), MICVDD = 3.0V (powered from LDO2), SPKVDD = 4.2V,
TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analogue Input Paths (INnL, INnR) to ADC (Differential Input Mode, INn_MODE = 00)
Signal to Noise Ratio
SNR
(A-weighted)
High performance mode
TBD
96
TBD
93
dB
(INn_OSR = 1)
Normal mode
(INn_OSR = 0)
Total Harmonic Distortion
Total Harmonic Distortion Plus
Noise
THD
-1dBV input
-83
TBD
dB
THD+N
-1dBV input
-81
TBD
dB
TBD
µVRMS
Channel separation (Left/Right)
TBD
Input noise floor
A-weighted,
100
3.2
dB
PGA gain = +18dB
Common mode rejection ratio
CMRR
PSRR (DBVDDn, LDOVDD,
CPVDD, AVDD)
PSRR
PSRR (SPKVDD)
PSRR
PGA gain = +30dB
TBD
60
PGA gain = 0dB
TBD
70
100mV (peak-peak) 217Hz
80
100mV(peak-peak) 10kHz
70
100mV (peak-peak) 217Hz
80
100mV(peak-peak) 10kHz
70
dB
dB
dB
Analogue Input Paths (INnL, INnR) to ADC (Single-Ended Input Mode, INn_MODE = 01)
PGA Gain = +6dB unless otherwise stated.
Signal to Noise Ratio
SNR
(A-weighted)
High performance mode
96
dB
(INn_OSR = 1)
Normal mode
93
(INn_OSR = 0)
Total Harmonic Distortion
Total Harmonic Distortion Plus
Noise
THD
-7dBV input
-83
dB
THD+N
-7dBV input
-81
dB
Channel separation (Left/Right)
Input noise floor
100
dB
3.2
µVRMS
100mV (peak-peak) 217Hz
80
dB
100mV(peak-peak) 10kHz
70
A-weighted,
PGA gain = +18dB
PSRR (DBVDDn, LDOVDD,
CPVDD, AVDD)
PSRR
PSRR (SPKVDD)
PSRR
100mV (peak-peak) 217Hz
80
100mV(peak-peak) 10kHz
70
dB
DAC to Line Output (HPOUTL, HPOUTR; Load = 10k, 50pF)
Full-scale output signal level
VOUT
0dBFS input
1
Vrms
0
dBV
Signal to Noise Ratio
SNR
A-weighted
Total Harmonic Distortion
THD
0dBFS input
-80
TBD
dB
THD+N
0dBFS input
-78
TBD
dB
TBD
µVRMS
Total Harmonic Distortion Plus
Noise
Channel separation (Left/Right)
TBD
TBD
Output noise floor
A-weighted,
102
dB
95
7.9
dB
PGA gain = 0dB
PSRR (DBVDDn, LDOVDD,
CPVDD, AVDD)
PSRR
PSRR (SPKVDD)
PSRR
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100mV (peak-peak) 217Hz
80
100mV (peak-peak) 10kHz
65
100mV (peak-peak) 217Hz
80
100mV (peak-peak) 10kHz
65
dB
dB
Product Brief, April 2013, Rev 2.1
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WM8997
Preliminary Technical Data
Test Conditions
DBVDD1 = DBVDD2 = LDOVDD = CPVDD = AVDD = 1.8V,
DCVDD = 1.2V (powered from LDO1), MICVDD = 3.0V (powered from LDO2), SPKVDD = 4.2V,
TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC to Headphone Output (HPOUTL, HPOUTR; RL = 32)
Maximum output power
Signal to Noise Ratio
PO
0.1% THD
SNR
High performance mode
(A-weighted)
30
mW
TBD
102
dB
TBD
99
(HPOUT_OSR = 1)
Normal mode
(HPOUT_OSR = 0)
Total Harmonic Distortion
Total Harmonic Distortion Plus
Noise
Total Harmonic Distortion
Total Harmonic Distortion Plus
Noise
THD
PO = 20mW
-80
TBD
dB
THD+N
PO = 20mW
-78
TBD
dB
THD
PO = 5mW
-80
TBD
dB
THD+N
PO = 5mW
-78
TBD
dB
TBD
µVRMS
Channel separation (Left/Right)
TBD
Output noise floor
A-weighted,
95
3.2
dB
PGA gain = -12dB
PSRR (DBVDDn, LDOVDD,
CPVDD, AVDD)
PSRR
PSRR (SPKVDD)
PSRR
100mV (peak-peak) 217Hz
80
100mV (peak-peak) 10kHz
65
100mV (peak-peak) 217Hz
80
100mV (peak-peak) 10kHz
65
dB
dB
DAC to Headphone Output (HPOUTL, HPOUTR; RL = 16)
Maximum output power
Signal to Noise Ratio
PO
0.1% THD
SNR
High performance mode
(A-weighted)
30
mW
TBD
102
dB
TBD
98
(HPOUT_OSR = 1)
Normal mode
(HPOUTOSR = 0)
Total Harmonic Distortion
Total Harmonic Distortion Plus
Noise
Total Harmonic Distortion
Total Harmonic Distortion Plus
Noise
THD
PO = 20mW
-82
TBD
dB
THD+N
PO = 20mW
-80
TBD
dB
THD
PO = 5mW
-83
TBD
dB
THD+N
PO = 5mW
-81
TBD
dB
TBD
µVRMS
Channel separation (Left/Right)
TBD
Output noise floor
A-weighted,
TBD
3.2
dB
PGA gain = -12dB
PSRR (DBVDDn, LDOVDD,
CPVDD, AVDD)
PSRR
PSRR (SPKVDD)
PSRR
w
100mV (peak-peak) 217Hz
80
100mV (peak-peak) 10kHz
65
100mV (peak-peak) 217Hz
80
100mV (peak-peak) 10kHz
65
dB
dB
Product Brief, April 2013, Rev 2.1
12
WM8997
Preliminary Technical Data
Test Conditions
DBVDD1 = DBVDD2 = LDOVDD = CPVDD = AVDD = 1.8V,
DCVDD = 1.2V (powered from LDO1), MICVDD = 3.0V (powered from LDO2), SPKVDD = 4.2V,
TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC to Mono Headphone Output (HPOUTL, HPOUTR, Mono Mode, RL = 32 BTL)
Maximum output power
Signal to Noise Ratio
PO
SNR
(A-weighted)
Total Harmonic Distortion
0.1% THD
60
5% THD
100
mW
High performance mode
100
dB
(HPOUT_OSR = 1)
THD
PO = 50mW
-71
dB
THD+N
PO = 50mW
-69
dB
THD
PO = 5mW
-77
dB
THD+N
PO = 5mW
-75
dB
A-weighted
TBD
µVRMS
PSRR (DBVDDn, LDOVDD,
CPVDD, AVDD)
PSRR
100mV (peak-peak) 217Hz
80
dB
100mV (peak-peak) 10kHz
65
PSRR (SPKVDD)
PSRR
Total Harmonic Distortion Plus
Noise
Total Harmonic Distortion
Total Harmonic Distortion Plus
Noise
Output noise floor
100mV (peak-peak) 217Hz
80
100mV (peak-peak) 10kHz
65
dB
DAC to Earpiece Output (EPOUTP+EPOUTN, RL = 32 BTL)
Maximum output power
Signal to Noise Ratio
PO
SNR
(A-weighted)
Total Harmonic Distortion
Total Harmonic Distortion Plus
Noise
Total Harmonic Distortion
0.1% THD
60
5% THD
100
High performance mode
TBD
mW
100
dB
(EPOUT_OSR = 1)
THD
PO = 50mW
-71
TBD
dB
THD+N
PO = 50mW
-69
TBD
dB
THD
PO = 5mW
-77
TBD
dB
THD+N
PO = 5mW
-75
TBD
dB
A-weighted
TBD
TBD
µVRMS
PSRR (DBVDDn, LDOVDD,
CPVDD, AVDD)
PSRR
100mV (peak-peak) 217Hz
80
100mV (peak-peak) 10kHz
65
PSRR (SPKVDD)
PSRR
Total Harmonic Distortion Plus
Noise
Output noise floor
100mV (peak-peak) 217Hz
80
100mV (peak-peak) 10kHz
65
dB
dB
DAC to Earpiece Output (EPOUTP+EPOUTN, RL = 16 BTL)
Maximum output power
Signal to Noise Ratio
PO
SNR
(A-weighted)
Total Harmonic Distortion
0.1% THD
60
10% THD
115
High performance mode
TBD
mW
102
dB
(EPOUT_OSR = 1)
THD
PO = 5mW
-77
TBD
dB
THD+N
PO = 5mW
-75
TBD
dB
A-weighted
TBD
TBD
µVRMS
PSRR (DBVDDn, LDOVDD,
CPVDD, AVDD)
PSRR
100mV (peak-peak) 217Hz
80
100mV (peak-peak) 10kHz
65
PSRR (SPKVDD)
PSRR
100mV (peak-peak) 217Hz
80
100mV (peak-peak) 10kHz
65
Total Harmonic Distortion Plus
Noise
Output noise floor
w
dB
dB
Product Brief, April 2013, Rev 2.1
13
WM8997
Preliminary Technical Data
Test Conditions
DBVDD1 = DBVDD2 = LDOVDD = CPVDD = AVDD = 1.8V,
DCVDD = 1.2V (powered from LDO1), MICVDD = 3.0V (powered from LDO2), SPKVDD = 4.2V,
TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC to Speaker Output (SPKOUTP+SPKOUTN, Load = 8, 22µH, BTL)
Maximum output power
Signal to Noise Ratio
PO
SNR
(A-weighted)
Total Harmonic Distortion
Total Harmonic Distortion Plus
Noise
Total Harmonic Distortion
SPKVDD = 5.0V,
1% THD
1.2
SPKVDD = 4.2V,
1% THD
1.0
SPKVDD = 3.6V,
1% THD
0.7
High performance mode
TBD
W
95
dB
(SPKOUT_OSR = 1)
THD
PO = 1.0W
-45
dB
THD+N
PO = 1.0W
-43
dB
THD
PO = 0.5W
-65
TBD
dB
THD+N
PO = 0.5W
-63
TBD
dB
A-weighted
71
TBD
µVRMS
PSRR (DBVDDn, LDOVDD,
CPVDD, AVDD)
PSRR
100mV (peak-peak) 217Hz
75
100mV (peak-peak) 10kHz
65
PSRR (SPKVDD)
PSRR
100mV (peak-peak) 217Hz
75
100mV (peak-peak) 10kHz
65
Total Harmonic Distortion Plus
Noise
Output noise floor
dB
dB
DAC to Speaker Output (SPKOUTP+SPKOUTN, Load = 4, 15µH, BTL)
Maximum output power
Signal to Noise Ratio
PO
SNR
(A-weighted)
Total Harmonic Distortion
Total Harmonic Distortion Plus
Noise
Total Harmonic Distortion
SPKVDD = 5.0V,
1% THD
2
W
SPKVDD = 4.2V,
1% THD
1.8
SPKVDD = 3.6V,
1% THD
TBD
High performance mode
95
dB
(SPKOUT_OSR = 1)
THD
PO = 1.0W
TBD
dB
THD+N
PO = 1.0W
TBD
dB
THD
PO = 0.5W
TBD
dB
THD+N
PO = 0.5W
TBD
dB
A-weighted
71
µVRMS
PSRR (DBVDDn, LDOVDD,
CPVDD, AVDD)
PSRR
100mV (peak-peak) 217Hz
75
dB
100mV (peak-peak) 10kHz
65
PSRR (SPKVDD)
PSRR
Total Harmonic Distortion Plus
Noise
Output noise floor
w
100mV (peak-peak) 217Hz
75
100mV (peak-peak) 10kHz
65
dB
Product Brief, April 2013, Rev 2.1
14
WM8997
Preliminary Technical Data
Test Conditions
The following electrical characteristics are valid across the full range of recommended operating conditions.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Input / Output (except DMICDATn and DMICCLKn)
Digital I/O is referenced to DBVDD1 or DBVDD2.
See “Recommended Operating Conditions” for the valid operating voltage range of each DBVDDn domain.
Input HIGH Level
Input LOW Level
VIH
VIL
VDBVDDn =1.8V ±10%
0.65 
VDBVDDn
VDBVDDn =3.3V ±10%
0.7 
VDBVDDn
V
VDBVDDn =1.8V ±10%
0.35 
VDBVDDn
VDBVDDn =3.3V ±10%
0.3 
VDBVDDn
V
Note that digital input pins should not be left unconnected or floating.
Output HIGH Level
VOH
IOH = 1mA
Output LOW Level
VOL
IOL = -1mA
0.9 
VDBVDDn
Input capacitance
V
0.1 
VDBVDDn
V
1
µA
45
kΩ
10
Input leakage
-1
Pull-up / pull-down resistance
28
36
pF
(where applicable)
Digital Microphone Input / Output (DMICDATn and DMICCLKn)
DMICDATn and DMICCLKn are each referenced to a selectable supply, VSUP, according to the INn_DMIC_SUP registers
0.65  VSUP
DMICDATn input HIGH Level
VIH
DMICDATn input LOW Level
VIL
DMICCLKn output HIGH Level
VOH
IOH = 1mA
DMICCLKn output LOW Level
VOL
IOL = -1mA
V
0.35  VSUP
V
0.2  VSUP
V
1
µA
TBD
V
0.8  VSUP
Input capacitance
V
10
Input leakage
-1
pF
SLIMbus Digital Input / Output (SLIMCLK and SLIMDAT)
1.8V I/O Signalling (ie. 1.65V ≤ DBVDD1 ≤1.95V)
Input LOW Level
VIL
Input HIGH Level
VIH
Output LOW Level
VOL
IOL = -1mA
Output HIGH Level
VOH
IOH = 1mA
TBD
Pin capacitance
V
TBD
TBD
V
V
TBD
pF
26.5
MHz
General Purpose Input / Output (GPIOn)
Clock output frequency
w
GPIO pin configured as
OPCLK or FLL output
Product Brief, April 2013, Rev 2.1
15
WM8997
Preliminary Technical Data
Test Conditions
fs ≤ 48kHz
With the exception of the condition(s) noted above, the following electrical characteristics are valid across the full range of
recommended operating conditions.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC Decimation Filters
Passband
+/- 0.05dB
0
-6dB
0.454 fs
0.5 fs
Passband ripple
+/- 0.05
Stopband
Stopband attenuation
Signal path delay
dB
0.546 fs
f > 0.546 fs
85
dB
Analogue input to
Digital AIF output
2
ms
DAC Interpolation Filters
Passband
+/- 0.05dB
0
-6dB
0.5 fs
Passband ripple
Stopband
Stopband attenuation
Signal path delay
w
0.454 fs
+/- 0.05
dB
1.5
ms
0.546 fs
f > 0.546 fs
Digital AIF input to
Analogue output
85
dB
Product Brief, April 2013, Rev 2.1
16
WM8997
Preliminary Technical Data
Test Conditions
DBVDD1 = DBVDD2 = LDOVDD = CPVDD = AVDD = 1.8V,
DCVDD = 1.2V (powered from LDO1), MICVDD = 3.0V (powered from LDO2), SPKVDD = 4.2V,
TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Microphone Bias (MICBIAS1, MICBIAS2, MICBIAS3)
Note - No capacitor on MICBIASn
Note - In regulator mode, it is required that VMICVDD - VMICBIASn > 200mV
Minimum Bias Voltage
Maximum Bias Voltage
Regulator mode
(MICBn_BYPASS=0)
Bias Voltage output step size
Load current ≤ 1.0mA
VMICBIAS
Bias Voltage accuracy
1.5
V
2.8
V
0.1
-5%
Bias Current
Regulator mode
(MICBn_BYPASS=0),
V
+5%
V
2.4
mA
VMICVDD - VMICBIAS >200mV
Bypass mode
(MICBn_BYPASS=1)
Output Noise Density
Integrated noise voltage
Power Supply Rejection Ratio
(CPVDD)
PSRR
Load capacitance
5.0
Regulator mode
(MICBn_BYPASS=0),
MICBn_LVL = 4h,
Load current = 1mA,
Measured at 1kHz
100
nV/Hz
Regulator mode
(MICBn_BYPASS=0),
MICBn_LVL = 4h,
Load current = 1mA,
100Hz to 7kHz, A-weighted
5
µVrms
100mV (peak-peak) 217Hz
100
100mV (peak-peak) 10kHz
80
dB
50
Regulator mode
(MICBn_BYPASS=0),
MICBn_EXT_CAP=0
Regulator mode
(MICBn_BYPASS=0),
MICBn_EXT_CAP=1
Output discharge resistance
1.8
MICBn_ENA=0,
pF
4.7
µF
5
kΩ
MICBn_DISCH=1
External Accessory Detect
Load impedance detection range
8
128
Ω
-30
+30
%
Ω
(HPDETL or HPDETR)
Load impedance detection
accuracy
(HPDETL or HPDETR)
Load impedance detection range
for MICD_LVL[0] = 1
0
3
(MICDET1 or MICDET2)
for MICD_LVL[1] = 1
17
21
2.2kΩ (2%) MICBIAS resistor.
for MICD_LVL[2] = 1
36
44
Note these characteristics assume
no other component is connected
to MICDETn.
for MICD_LVL[3] = 1
62
88
for MICD_LVL[4] = 1
115
160
for MICD_LVL[5] = 1
207
381
for MICD_LVL[8] = 1
475
30000
Jack Detection input threshold
voltage (JACKDET)
w
VJACKDET
Jack insertion
0.5 x AVDD
Jack removal
0.85 x AVDD
V
Product Brief, April 2013, Rev 2.1
17
WM8997
Preliminary Technical Data
Test Conditions
DBVDD1 = DBVDD2 = LDOVDD = CPVDD = AVDD = 1.8V,
DCVDD = 1.2V (powered from LDO1), MICVDD = 3.0V (powered from LDO2), SPKVDD = 4.2V,
TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.7
3.0
3.3
UNIT
MICVDD Charge Pump and Regulator (CP2 and LDO2)
Output voltage
VMICVDD
V
Programmable output voltage step
size
50
mV
Maximum output current
8
mA
Start-up time
4.7µF on MICVDD
1.5
3
ms
52
MHz
Frequency Locked Loop (FLL1, FLL2)
Output frequency
13
Lock Time
FREF = 32kHz,
FOUT = 24.576MHz
TBD
FREF = 12MHz,
FOUT = 24.576MHz
TBD
ms
RESET pin Input
RESET input pulse width
1
µs
(To trigger a Hardware Reset, the
RESET input must be asserted for
longer than this duration)
Test Conditions
The following electrical characteristics are valid across the full range of recommended operating conditions.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Device Reset Thresholds
AVDD Reset Threshold
VAVDD
0.50
1.51
V
DCVDD Reset Threshold
VDCVDD
0.59
0.81
V
DBVDD1 Reset Threshold
VDBVDD1
0.50
1.51
V
Note that the reset thresholds are derived from simulations only, across all operational and process corners.
Device performance is not assured outside the voltage ranges defined in the “Recommended Operating Conditions” section. Refer
to this section for the WM8997 power-up sequencing requirements.
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Product Brief, April 2013, Rev 2.1
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Preliminary Technical Data
WM8997
TERMINOLOGY
1.
Signal-to-Noise Ratio (dB) – SNR is a measure of the difference in level between the maximum full scale output signal
and the output with no input signal applied. (Note that this is measured without any mute function enabled.)
2.
Total Harmonic Distortion (dB) – THD is the ratio of the RMS sum of the harmonic distortion products in the specified
bandwidth (see note below) relative to the RMS amplitude of the fundamental (ie. test frequency) output.
3.
Total Harmonic Distortion plus Noise (dB) – THD+N is the ratio of the RMS sum of the harmonic distortion products
plus noise in the specified bandwidth (see note below) relative to the RMS amplitude of the fundamental (ie. test
frequency) output.
4.
Power Supply Rejection Ratio (dB) - PSRR is the ratio of a specified power supply variation relative to the output
signal that results from it. PSRR is measured under quiescent signal path conditions.
5.
Common Mode Rejection Ratio (dB) – CMRR is the ratio of a specified input signal (applied to both sides of a
differential input), relative to the output signal that results from it.
6.
Channel Separation (L/R) (dB) – left-to-right and right-to-left channel separation is the difference in level between the
active channel (driven to maximum full scale output) and the measured signal level in the idle channel at the test
signal frequency. The active channel is configured and supplied with an appropriate input signal to drive a full scale
output, with signal measured at the output of the associated idle channel.
7.
Multi-Path Crosstalk (dB) – is the difference in level between the output of the active path and the measured signal
level in the idle path at the test signal frequency. The active path is configured and supplied with an appropriate input
signal to drive a full scale output, with signal measured at the output of the specified idle path.
8.
Mute Attenuation – This is a measure of the difference in level between the full scale output signal and the output with
mute applied.
9.
All performance measurements are specified with a 20kHz low pass ‘brick-wall’ filter and, where noted, an A-weighted
filter. Failure to use these filters will result in higher THD and lower SNR readings than are found in the Electrical
Characteristics. The low pass filter removes out of band noise.
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Product Brief, April 2013, Rev 2.1
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WM8997
Preliminary Technical Data
DEVICE DESCRIPTION
INTRODUCTION
The WM8997 is a high-performance audio hub CODEC optimised for mobile telephony and portable
devices. It provides flexible, high-performance audio interfacing for handheld devices in a small and
cost-effective package. It is optimised for the needs of multimedia phones using SLIMbus application
processors.
The WM8997 digital core provides configurable capability for signal processing algorithms, including
parametric equalisation (EQ) and dynamic range control (DRC). Highly flexible digital mixing,
including stereo full-duplex isochronous sample rate conversion, provides use-case flexibility across a
broad range of system architectures. A signal generator for controlling haptics vibe actuators is
included.
The WM8997 provides multiple digital audio interfaces, including SLIMbus, in order to provide fully
independent connections to different processors (eg. application processor, baseband processor and
wireless transceiver).
A flexible clocking arrangement supports a wide variety of external clock references, including
clocking derived from the digital audio interface. Two integrated Frequency Locked Loop (FLL)
circuits provide additional flexibility.
Unused circuitry can be disabled under software control, in order to save power; low leakage currents
enable extended standby/off time in portable battery-powered applications. Configurable ‘Wake-Up’
actions can be associated with the low-power standby (Sleep) mode.
Versatile GPIO functionality is provided, and support for external accessory / push-button detection
inputs. Comprehensive Interrupt (IRQ) logic and status readback are also provided.
HI-FI AUDIO CODEC
The WM8997 is a high-performance low-power audio CODEC which uses a simple analogue
architecture. 4 ADCs and 4 DACs are incorporated, providing a dedicated ADC for each input and a
dedicated DAC for each output channel.
The analogue outputs comprise a 30mW (102dB SNR) stereo headphone amplifier with groundreferenced output, a 100mW differential (BTL) earpiece driver, and a Class D mono speaker driver
capable of delivering 2W into a 4Ω load. Four analogue inputs are provided, each supporting singleended or differential input modes. In differential mode, the input path SNR is 96dB. The ADC input
paths can be bypassed, supporting up to 4 channels of digital microphone input.
The audio CODEC is controlled directly via register access. The simple analogue architecture,
combined with the integrated tone generator, enables simple device configuration and testing,
minimising debug time and reducing software effort.
The WM8997 output drivers are designed to support as many different system architectures as
possible. Each output has a dedicated DAC which allows mixing, equalisation, filtering, gain and other
audio processing to be configured independently for each channel. This allows each signal path to be
individually tailored for the load characteristics. All outputs have integrated pop and click suppression
features.
The headphone output drivers are ground-referenced, powered from an integrated charge pump,
enabling high quality, power efficient headphone playback without any requirement for DC blocking
capacitors. Ground loop feedback is incorporated, providing rejection of noise on the ground
connections. A mono mode is available on the headphone outputs; this configures the drivers as
differential (BTL) outputs, suitable for an earpiece or hearing aid coil.
The Class D speaker driver delivers excellent power efficiency. High PSRR, low leakage and
optimised supply voltage ranges enable powering from switching regulators or directly from the
battery. Battery current consumption is minimised across a wide variety of voice communication and
multimedia playback use cases.
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Product Brief, April 2013, Rev 2.1
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WM8997
Preliminary Technical Data
The WM8997 is cost-optimised for a wide range of mobile phone applications, and features a single
channel of Class D power amplification. For applications requiring more than one channel of power
amplification (or when using the integrated Class D path to drive a haptics actuator), the PDM output
channels can be used to drive two external PDM-input speaker drivers. In applications where stereo
loudspeakers are physically widely separated, the PDM outputs can ease layout and EMC by
avoiding the need to run the Class-D speaker outputs over long distances and interconnects.
DIGITAL AUDIO CORE
The WM8997 uses a core architecture based on all-digital signal routing, making digital audio effects
available on all signal paths, regardless of whether the source data input is analogue or digital. The
digital mixing desk allows different audio effects to be applied simultaneously on many independent
paths, whilst also supporting a variety of sample rates concurrently. This helps support many new
audio use-cases. Soft mute and un-mute control allows smooth transitions between use-cases
without interrupting existing audio streams elsewhere.
Highly flexible digital mixing, including mixing between audio interfaces, is possible. The WM8997
performs stereo full-duplex isochronous sample rate conversion, providing use-case flexibility across
a broad range of system architectures. Automatic sample rate detection is provided, enabling
seamless wideband/narrowband voice call handover.
Dynamic Range Controller (DRC) functions are available for optimising audio signal levels. In
playback modes, the DRC can be used to maximise loudness, while limiting the signal level to avoid
distortion, clipping or battery droop, in particular for high-power output drivers such as speaker
amplifiers. In record modes, the DRC assists in applications where the signal level is unpredictable.
The 5-band parametric equaliser (EQ) functions can be used to compensate for the frequency
characteristics of the output transducers. EQ functions can be cascaded to provide additional
frequency control. Programmable high-pass and low-pass filters are also available for general filtering
applications such as removal of wind and other low-frequency noise.
DIGITAL INTERFACES
Two serial digital audio interfaces (AIFs) each support PCM, TDM and I2S data formats for
compatibility with most industry-standard chipsets. AIF1 supports eight input/output channels; AIF2
supports two input/output channels. Bidirectional operation at sample rates up to 192kHz is
supported.
Four digital PDM input channels are available (two stereo interfaces); these are typically used for
digital microphones, powered from the integrated MICBIAS power supply regulators. Two PDM output
channels are also available (one stereo interface); these are typically used for external power
amplifiers. Embedded mute codes provide a control mechanism for external PDM-input devices.
The WM8997 features a MIPI-compliant SLIMbus interface, providing eight channels of audio
input/output. Mixed audio sample rates are supported on the SLIMbus interface. The SLIMbus
interface also supports read/write access to the WM8997 control registers.
The WM8997 is equipped with an I2C slave port (at up to 1MHz). Full access to the register map is
also provided via the SLIMbus port.
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WM8997
Preliminary Technical Data
OTHER FEATURES
The WM8997 incorporates two 1kHz tone generators which can be used for ‘beep’ functions through
any of the audio signal paths. The phase relationship between the two generators is configurable,
providing flexibility in creating differential signals, or for test scenarios.
A white noise generator is provided, which can be routed within the digital core. The noise generator
can provide ‘comfort noise’ in cases where silence (digital mute) is not desirable.
Two Pulse Width Modulation (PWM) signal generators are incorporated. The duty cycle of each PWM
signal can be modulated by an audio source, or can be set to a fixed value using a control register
setting. The PWM signal generators can be output directly on a GPIO pin.
The WM8997 provides 5 GPIO pins, supporting selectable input/output functions for interfacing,
detection of external hardware, and to provide logic outputs to other devices. Comprehensive
Interrupt (IRQ) functionality is also provided for monitoring internal and external event conditions.
A signal generator for controlling haptics devices is included, compatible with both Eccentric Rotating
Motor (ERM) and Linear Resonant Actuator (LRA) haptic devices. The haptics signal generator is
highly configurable, and can execute programmable drive event profiles, including reverse drive
control. An external vibe actuator can be driven directly by the Class D speaker output.
The WM8997 can be powered from a 1.8V external supply. A separate supply (4.2V) is typically
required for the Class D speaker driver. Integrated Charge Pump and LDO Regulators circuits are
used to generate supply rails for internal functions and to support powering or biasing of external
microphones.
A smart accessory interface is included, supporting most standard 3.5mm accessories. Jack
detection, accessory sensing and impedance measurement is provided, for external accessory and
push-button detection. Accessory detection can be used as a ‘Wake-Up’ trigger from low-power
standby. Microphone activity detection with interrupt is also available.
System clocking can be derived from the MCLK1 or MCLK2 input pins. Alternatively, the SLIMbus
interface, or the audio interfaces (configured in Slave mode), can be used to provide a clock
reference. Two integrated Frequency Locked Loop (FLL) circuits provide support for a wide range of
clocking configurations, including the use of a 32kHz input clock reference.
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Preliminary Technical Data
WM8997
RECOMMENDED EXTERNAL COMPONENTS
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WM8997
Preliminary Technical Data
PACKAGE DIMENSIONS
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Preliminary Technical Data
WM8997
IMPORTANT NOTICE
Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale,
delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the
right to make changes to its products and specifications or to discontinue any product or service without notice. Customers
should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.
Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating
safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer
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such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
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EH11 2QB
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Product Brief, April 2013, Rev 2.1
25
WM8997
Preliminary Technical Data
REVISION HISTORY
DATE
REV
DESCRIPTION OF CHANGES
PAGE
CHANGED BY
15/09/11
1.0
Customer preview under NDA
MP
19/10/11
1.1
Detailed description of haptics capabilities added,
MP
Pin names corrected
24/10/11
1.2
I/O feature set updated,
MP
Pin names updated
11/11/11
1.3
Removed DACVDD
MP
7/12/11
1.4
Updated power pins to reflect implementation, and block diagram to
match.
MP
Updated filter spec delay wording
17/02/12
1.5
Updates to all sections, and alignment with datasheet standards.
PH
04/07/12
1.5
Review feedback incorporated; Package Diagram updated.
PH
06/08/12
1.6
Package Diagram updated to DM122C - dimensions showing at top
of Package Diagram corrected.
JMacD
08/08/12
1.6
Pin Descriptions updated to show single-ended analogue input is on
the INxP pins (not INxN).
PH
24/09/12
2.0
Product status updated to Preliminary Technical Data
24/09/12
2.0
Updates made to Electrical Characteristics
PH
14/12/12
2.1
Block diagram update, showing gain in AEC Loopback path
PH
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JMacD
Product Brief, April 2013, Rev 2.1
26