EE 561 Digital Circuit Design

DMA and Bus Arbitration

Read pages 285-287, 237-238

Why DMA?

• When consider the concept of virtual memory a page of data/instructions bring in from the secondary disk storage where there is page fault

• The fastest way to do it is through Direct Memory Access

(DMA)

• What will the operating system do?

– Suspends the program that needs the data

– Starts another program so that time is not wasted waiting

– Activates a DMA transfer that causes data to go directly from the disk to main memory

– Wait for an interrupt to continue with the original program

Data Transfer Methods - General

• Polling – processor loops while looking at a device status flag; then transfer the data – much time lost while waiting

• Interrupt – processor waits an external signal to determine when the device is ready for a transfer

– Considerable overhead. Several program instructions must be executed for each data/word transferred

– For block transfer, instructions needed to increment the memory address and keep track of the word count

– Saving and restoring PC plus other registers is needed

– Can cause considerable delay even with most effective scheme

• DMA – processor initiates a block transfer; while waiting, executes other programs; DMA controller completes the transfer without processor intervention (directly between disk and memory)

DMA Controller

• DMA controller is a required unit to allow transfer of a block of data directly between an external device and the main memory

– It is a control circuit associated with I/O device

– Performs functions (I/O) normally performed by processor

• Memory access

• Bus signals – read/write, etc

.

– Increment memory address

– Keep track of the number of transfers (word count)

– ECE5465 Advanced Microcomputers covers more details

CPU

DMA architecture

PCI Bus

Bridge

Arbiter

BG

BR

DMA controller

Disk

Disk

Disk

Main memory

DMA controller

Other peripheral device

Registers in a DMA Controller

Interrupt Enable - IE

31 30

1 0

Status and control

Interrupt Request - IRQ

R/W

Done

Starting address

Word count

A Real Hardware Design for DMA

- memory and peripheral uses the same bus

Bus Arbitration

• Several DMA controllers may exist in a computer

• Need “Bus Arbiter”

– Implements priority system for gaining access to the bus

– Processor and DMA transfer – interwoven

• DMA transfers to high-speed peripheral devices given top priority

– Two interweaving techniques

:

• Cycle stealing – DMA controller gets a memory cycle slot from processor

• Block mode – DMA controller has exclusive access to main memory

Timing diagram of bus arbitration

BR1

BG1

BR2

BG2

BR3

BG3

Bus Arbitration (continued)

• Allow only one bus master

• Bus arbiter – performs scheduling of bus master

• A simple arrangement for bus arbitration using a daisy chain

– 3 new lines on interface bus for arbitration

• BR – low true bus request – using open collector for a logic OR

• BG – bus grant, asserted when bus request granted

• BBSY – low true indicating bus busy – using open collector

• See Figs. 7.8 and 7.9 on pages 237-238

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