42PD6700U - Driver Dll service manual user guide

42PD6700U - Driver Dll service manual user guide
SM012
42PD6700U
SERVICE MANUAL
MANUEL D'ENTRETIEN
WARTUNGSHANDBUCH
CAUTION:
Before servicing this chassis, it is important that the service technician read the “Safety
Precautions” and “Product Safety Notices” in this service manual.
Data contained within this Service
manual is subject to alteration for
improvement.
ATTENTION:
Avant d’effectuer l’entretien du châassis, le technicien doit lire les «Précautions de sécurité»
et les «Notices de sécurité du produit» présentés dans le présent manuel.
Les données fournies dans le présent
manuel d’entretien peuvent faire l’objet
de modifications en vue de perfectionner
le produit.
VORSICHT:
Die in diesem Wartungshandbuch
enthaltenen Spezifikationen können sich
zwecks Verbesserungen ändern.
Vor Öffnen des Gehäuses hat der Service-Ingenieur die „Sicherheitshinweise“ und „Hinweise
zur Produktsicherheit“ in diesem Wartungshandbuch zu lesen.
SPECIFICATIONS AND PARTS ARE SUBJECT TO CHANGE FOR IMPROVEMENT
Plasma TV
June 2006
TABLE OF CONTENTS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SERVICE MENU ITEMS
2.1.
SOUND 1
2.2.
SOUND 2
2.3.
Options
2.4.
Features
2.5.
Teletext
2.6.
Tuner Options
SOFTWARE UPDATE DESCRIPTION
3.1.
ANALOG SOFTWARE UPDATE via SCART
2
3.2.
ANALOG SOFTWARE UPDATE via I C
3.3.
EEPROM UPDATE via SCART
INTRODUCTION
TUNER
IF PART (TDA9886)
MULTI-STANDARD SOUND PROCESSOR
VIDEO SWITCH TEA6415
AUDIO AMPLIFIER STAGE WITH TPA3004D2
POWER SUPPLY (SMPS)
MICRO-CONTROLLER
SERIAL ACCESS CMOS 4Kx8 (32KBit) EEPROM 24C32A
CLASS AB STEREO HEADPHONE DRIVER TDA1308
SAW FILTERS
IC DESCRIPTIONS
TEA6415C
15.1. 24LC02
15.1.1.
Description
15.1.2.
Features
15.1.3.
Pinning
15.2. 24C32
15.2.1.
General Description
15.2.2.
Features
15.2.3.
Pinning
15.2.4.
PIN Function Table
15.3. 74LVC14A
15.3.1.
Description
15.3.2.
Features
15.3.3.
Pinning
15.4. TEA6420
15.4.1.
Features
15.4.2.
Description
15.4.3.
Pin Connections
15.5. CS4334
15.5.1.
Features
15.5.2.
General Description
15.5.3.
Pin Descriptions
15.6. GAL16LV8
15.6.1.
Description
15.6.2.
Features
15.6.3.
Pin connections
15.8. K6R4008V1D
15.8.1.
Description
15.8.2.
Features
15.8.3.
Pin Description
15.9. KA278R33
15.9.1.
Features
15.9.2.
Description
15.10. LM1117
15.10.1.
General Description
15.10.2.
Features
15.10.3.
Applications
i
1
1
1
2
2
3
3
4
4
5
6
7
7
7
8
8
8
9
9
9
9
9
10
10
12
12
12
12
13
13
13
13
14
14
14
14
14
15
15
15
15
15
15
16
16
16
16
16
17
17
17
17
18
18
18
18
19
19
19
19
15.11. LM317
15.11.1.
General Description
15.11.2.
Features
15.11.3.
Pin Description
15.12. LM809
15.12.1.
General Description
15.12.2.
Features
15.12.3.
Pinning
15.13. MSP34X1G (MSP3411G)
15.13.1.
Introduction
15.13.2.
Features
15.14. M29W040B
15.14.1.
Description
15.14.2.
Features
15.14.3.
Pin Descriptions
15.15. MC33202
15.15.1.
General Description
15.15.2.
Features
15.15.3.
Pin Connections
15.16. PCF8574
15.16.1.
General Description
15.16.2.
Features
15.16.3.
Pinning
15.17. TSOP1836
15.17.1.
Description
15.17.2.
Features
15.18. PI5V330
15.18.1.
General Description
15.19. SDA55XX (SDA5550)
15.19.1.
General description
15.20. Sil 9993
15.20.1.
General Description
15.20.2.
Features
15.21. SN74CB3Q3305
15.21.1.
General Description
15.21.2.
Features
15.21.3.
Pin Connections
15.22. ST24LC21
15.22.1.
Description
15.22.2.
Features
15.22.3.
Pin connections
15.23. LM2576
15.23.1.
General Description
15.23.2.
Features
15.23.3.
Pin description
15.24. MC34063
15.24.1.
Description
15.24.2.
Features
15.24.3.
Pin connections
15.25. TDA1308
15.25.1.
General Description
15.25.2.
Features
15.25.3.
Pinning
15.26. TDA9886
15.26.1.
General Description
15.26.2.
Features
15.26.3.
Pinning
15.27. TPA3004D2
15.27.1.
General Description
15.27.2.
Features
15.27.3.
Pinning
ii
19
19
19
20
20
20
20
20
20
21
21
23
23
23
24
24
24
24
25
25
25
25
25
26
26
26
26
26
27
27
27
27
27
28
28
28
28
28
28
29
29
29
29
29
30
30
30
30
30
31
31
31
31
31
31
31
32
32
32
32
33
16
17
15.29. μPA672T
15.29.1.
General Description
15.29.2.
Features
15.29.3.
Pin Connection
15.30. VPC3230D
15.30.1.
General Description
15.30.2.
Pin Connections and Short Descriptions
15.31. MAD4868A
15.31.1.
General Description
15.31.2.
Features
15.31.3.
Interfaces
15.31.4.
Pinning
15.32. SVP-EX 59B
SERVICE MENU SETTINGS
16.1. Picture Adjust
16.2. SOUND 1
16.3. SOUND 2
16.4. Options
IC DESCRIPTIONS (FOR DIGITAL)
17.1. STI5518
17.1.1.
General Description
17.2. MAX232_SMD
17.2.1.
General Description
17.2.2.
Features
17.3. 74HCU04
17.3.1.
General Description
17.3.2.
Pin Description
17.4. TSH22
17.4.1.
General Description
17.4.2.
Pin Connections
17.5. CS4334
17.5.1.
General Description
17.5.2.
Features
17.6. AMIC A43L2616
17.6.1.
General Description
17.6.2.
Features
17.6.3.
Pin Description
17.7. MX29LV160T
17.7.1.
General Description
17.7.2.
Features
17.7.3.
Pin Description
17.8. 24C32
17.8.1.
General Description
17.8.2.
Features
17.8.3.
Pin Description
17.9. STV0360
17.9.1.
General Description
17.9.2.
Features
17.9.3.
Pin Description
17.10. MAX809
17.10.1.
General Description
17.10.2.
Features
17.10.3.
Pin Description
17.11. TDCC2345TV39A
17.11.1.
General Description
17.11.2.
Pin Description
17.12. STV0700
17.12.1.
General description
17.12.2.
Features
17.12.3.
Pin Description
iii
34
34
34
34
34
34
34
36
36
36
36
37
37
37
38
38
38
38
39
39
39
40
40
40
40
40
40
41
41
41
41
41
41
41
41
41
42
43
43
43
43
44
44
44
44
45
45
45
45
47
47
47
48
48
48
48
49
49
49
49
18
19
APPENDIX A
18.1.
APPENDIX B
19.1.
19.2.
19.3.
19.4.
19.4.
20
APPENDIX C
20.1.
EXPLODED VIEW
53
73
BLOCK DIAGRAM
SCHEMATIC DIAGRAMS
19.2.1. Power Board
19.2.2. Main Board
19.2.3. Amplifier Board
19.2.4. Front AV Board
CIRCUIT BOARDS
PCB LAYOUTS
CONNECTOR DIAGRAM
54
54
55
55
60
68
69
70
71
72
SPARES PARTLIST
73
73
iv
2. SERVICE MENU ITEMS
2.1.
SOUND 1
a) Menu Subwoofer
=> If ON, Subwoofer option is available in TV set, and the item is
visible in sound menu, else Subwoofer is not available. Default “ON”.
b) Subwoofer Level (dB) => This value is gain value of Subwoofer output in dB.
-30...12. Default “0” dB.
c) Subwoofer Corner Freq. (x10Hz) => Last low frequency value that is amplified. 5...40.
Default “22” x 10Hz = 220Hz.
d) Menu Equalizer
=> If ON, visible in sound menu, else invisible. Default “ON”.
e) Menu Headphone
=> If ON, visible in sound menu, else invisible. Default “ON”.
f) Menu Effect
=> If ON, visible in sound menu, else invisible. Default “ON”.
g) Menu Wide Sound
=> If ON, visible in sound menu, else invisible. Default “OFF”.
h) Menu Dynamic Bass
=> If ON, visible in sound menu, else invisible. Default “ON”.
i)
Menu Virtual Dolby
=> If ON, visible in sound menu, else invisible. Default “ON”.
j)
Carrier Mute
Default “ON”.
=> If ON, in the absence of an FM carrier the output is muted, else not.
k) Virtual Dolby Text
=> Active if VIRTUAL DOLBY is ON.According to the selection; seen
in sound menu as 3DS or VIRTUAL DOLBY. Default “3DS”.
2.2. SOUND 2
a) AVL
=> AVL is controlled from this menu by service user. ON/OFF. Default “ON”.
b) Menu AVL
=> If ON, AVL item is visible in sound menu, and AVL can be controlled from
sound menu by normal user, else AVL is invisible to normal user. ON/OFF. Default “ON”.
c) FM PRESCALE AVL ON
=> If AVL ON, set value in this item is used as prescale value
for the related standard. 0...127. Default “29”.
d) NICAM PRESCALE AVL ON => If AVL ON, set value in this item is used as prescale value
for the related standard. 0...127. Default “62”.
e) SCART PRESCALE AVL ON => If AVL ON, set value in this item is used as prescale value
for scart outputs. 0...127. Default “28”.
f) SCART VOLUME AVL ON => If AVL ON, set value in this item is used as volume value
for scart1 and scart2. 0...127. Default “116”.
1
g) FM PRESCALE AVL OFF
=> If AVL OFF, set value in this item is used as prescale value
for the related standard. 0...127. Default “15”.
h) NICAM PRESCALE AVL OFF
=> If AVL OFF, set value in this item is used as
prescale value for the related standard. 0...127. Default “35”.
i)
SCART PRESCALE AVL OFF
=> If AVL OFF, set value in this item is used as
prescale value for scart outputs. 0...127. Default “14”.
j)
SCART VOLOUME AVL OFF
=> If AVL OFF, set value in this item is used as volume
value for scart1 and scart2. 0...127. Default “122”.
2.3. Options
a) Burn-In Mode
=> If ON, full screen flashes in RED, GREEN, BLUE colors unless
“Menu” button on Remote Control or Keypad is pressed. This property is used to protect the TV
set from burning on the assembly lines in factory. This item becomes automatically OFF, when
First APS item is ON or Factory Reset is pressed. ON/OFF. Default OFF.
b) First APS
=> This bit is set “ON” in the factory. When the TV set is opened for
the first time it directs the user to make automatic search in both digital and analog modes.
c) APS Volume
Default “10”.
=> After First APS function finishes, the volume of the TV is that value.
d) AGC (dB)
=> Tuner AGC value. Default “15”.
e) Power-Up Mode
=>Normal, Last State, Stand-by. Default “Last State”
f) PDP Working Hour
=>Displays Panel Run time in decimal.
g) Factory Reset
loaded.
=> OK to activate. When OK pressed on this item, factory defaults
h) Enter Flash Mode
=>OK to activate. When OK pressed on this item, flash mode is entered,
SW starts to wait for uploading the new SW.
2.4. Features
a) Blue Background
Default “ON”.
=> If ON, Blue Background is visible in Features Menu else not.
b) Menu Transparency
Default “ON”.
=> If ON, Menu Transparency is visible in Features Menu else not.
c) Menu Timeout
“ON”.
d) Backlight
=> If ON, Menu Timeout is visible in Features Menu else not. Default
=> If ON, Backlight is visible in Features Menu else not.Default “OFF”.
e) Single Tuner
=> If OFF, two tuners are available on the chassis. Fixed “ON”.
f) Dynamic WB
=> Default
2
2.5. Teletext
a) TOP TXT
=> ON/OFF
b) Fast TXT
=> ON/OFF
c) Teletext Language
user.
=> Teletext Language may be controlled from this menu by service
d) Txt Start RF
e) Txt Start Ext
f) Txt Start Mix
g) Menu Teletext Language => If ON, Teletext Language item is visible in Features Menu, and
Teletext Language can be controlled from Features Menu by normal user, else Teletext
Language is invisible to normal user.
2.6. Tuner Options
a) Switch Low Band
b) Switch Mid Band
c) Switch High Band
d) Boundry1 Low Byte
e) Boundry1 High Byte
f) Boundry2 Low Byte
g) Boundry2 High Byte
h) Control Byte
These values need to be filled in the factory acording to the tuner used on the chassis.
i) Store => OK to store; when the values are entered correctly OK needs to be pressed on this
item to store the values.
3
3. SOFTWARE UPDATE DESCRIPTION
3.1. ANALOG SOFTWARE UPDATE via SCART
STEP.1
Enter service menu by pressing the buttons “MENU”,”4”,”7”,”2”,”5” respectively.
STEP.2
Select “OPTIONS” from the service menu and “ENTER FLASH MODE”
STEP.3
Connect the Software Update Tool (17tr15-3) to parellel port of your PC.
STEP.4
Connect scart-end of the cable to Scart-1 (Ext-1).
STEP.5
Connect other-end of cable to “PL 2” socket on the Update Tool (17tr15-3)
STEP.6
Run IAPWriter.exe.
STEP.7
Click “load file” and load the required software.
4
3.2. ANALOG SOFTWARE UPDATE via I2C
STEP.1
Enter service menu by pressing the buttons “MENU”,”4”,”7”,”2”,”5” respectively.
STEP.2
Select “OPTIONS” from the service menu and “ENTER FLASH MODE”
STEP.3
Connect the Software Update Tool (17tr15-3) to parellel port of your PC.
STEP.4
Connect one-end of cable to “PL604” socket on the chassis socket MB15
STEP.5
Connect other-end of cable to “PL 2” socket on the Update Tool (17tr15-3)
STEP.6
Run IAPWriter.exe.
STEP.7
Click “load file” and load the required software.
5
3.3. EEPROM UPDATE via SCART
STEP.1.
Insert the EEROM tool(TR16) to SCART-1
STEP.2.
Enter service menu by pressing the buttons “MENU”,”4”,”7”,”2”,”5” respectively
STEP.3.
Press “YELLOW” colour button on the remote controller.
Then you will have two options
STEP.3.a
Press “RED” colour button to copy data of external EEPROM into internal one
STEP.3.b
Press “GREEN” colour button to copy data of internal EEPROM into external one
6
4. INTRODUCTION
42” Plasma TV is a progressive TV control system with built-in de-interlacer and scaler. It uses a 1024x1024
panel with 16:9 aspect ratio.The TV is capable of operation in PAL, SECAM, NTSC (playback) colour standards
and multiple transmission standards as B/G, D/K, I/I’, and L/L’ including German and NICAM stereo. Sound
system output is supplying 2x10W (10%THD) for stereo 8ȍ speakers. The chassis is equipped with many inputs
and outputs allowing it to be used as a center of a media system.
It supports following peripherals:
2 SCART sockets
1 AV input (CVBS + Stereo Audio)
1 SVHS input
1 Stereo Headphone input
1 Component input (YPbPr + Stereo Audio)
1 D-Sub 15 PC input
1 HDMI input
1 Stereo audio input for PC
1 Stereo audio output
1 Subwoofer output
5. TUNER
The tuners used in the design are combined VHF, UHF tuners suitable for CCIR systems B/G, H, L, L’, I/I’, and
D/K. The tuning is available through the digitally controlled I2C bus (PLL). Below you will find info on one of the
Tuners in use.
General description of UV1316:
The UV1316 tuner belongs to the UV 1300 family of tuners, which are designed to meet a wide range of
applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L’, I and I’. The low IF output
impedance has been designed for direct drive of a wide variety of SAW filters with sufficient suppression of triple
transient.
Features of UV1316:
1. Member of the UV1300 family small sized UHF/VHF tuners
2. Systems CCIR: B/G, H, L, L’, I and I’; OIRT: D/K
3. Digitally controlled (PLL) tuning via I2C-bus
4. Off-air channels, S-cable channels and Hyperband
5. World standardised mechanical dimensions and world standard pinning
6. Compact size
7. Complies to “CENELEC EN55020” and “EN55013”
Pinning:
1.
Gain control voltage (AGC)
2.
Tuning voltage
3.
I²C-bus address select
4.
I²C-bus serial clock
5.
I²C-bus serial data
6.
Not connected
7.
PLL supply voltage
8.
ADC input
9.
Tuner supply voltage
10.
Symmetrical IF output 1
11.
Symmetrical IF output 2
:
4.0V, Max: 4.5V
:
:
:
Max: 5.5V
Min:-0.3V, Max: 5.5V
Min:-0.3V, Max: 5.5V
:
5.0V, Min: 4.75V, Max: 5.5V
:
33V, Min: 30V, Max: 35V
6. IF PART (TDA9886)
The TDA9886 is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound IF signal PLL. The
following figure shows the simplified block diagram of the integrated circuit.
The integrated circuit comprises the following functional blocks:
7
VIF amplifier, Tuner and VIF-AGC, VIF-AGC detector, Frequency Phase-Locked Loop (FPLL) detector, VCO and
divider, Digital acquisition help and AFC, Video demodulator and amplifier, Sound carrier trap, SIF amplifier, SIF-AGC
detector, Single reference QSS mixer, AM demodulator, FM demodulator and acquisition help, Audio amplifier and
mute time constant, I²C-bus transceivers and MAD (module address), Internal voltage stabilizer.
7. MULTI STANDARD SOUND PROCESSOR
The MSP34x0G family of single-chip Multistandard Sound Processors covers the sound processing of all analogue TVStandards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analogue
sound IF signal-in, down to processed analogue AF-out, is performed on a single chip.
These TV sound processing ICs include versions for processing the multichannel television sound (MTS) signal
conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX
noise reduction, or alternatively, Micronas Noise Reduction (MNR) is performed alignment free. Other processed
standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard.
Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA-J. The
MSP 34x1G has optimum stereo performance without any adjustments.
8. VIDEO SWITCH TEA6415
In case of three or more external sources are used, the video switch IC TEA6415 is used. The main function of this device is
to switch 8 video-input sources on the 6 outputs.
Each output can be switched on only one of each input. On each input an alignment of the lowest level of the
signal is made (bottom of sync. top for CVBS or black level for RGB signals).
Each nominal gain between any input and output is 6.5dB.For D2MAC or Chroma signal the alignment is switched off by
forcing, with an external resistor bridge, 5VDC on the input. Each input can be used as a normal input or as a MAC or
Chroma input (with external Resistor Bridge). All the switching possibilities are changed through the BUS. Driving 75ohm
load needs an external resistor. It is possible to have the same input connected to several outputs.
9.
AUDIO AMPLIFIER STAGE WITH TPA3004D2
The TPA3004D2 is a 12-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied stereo speakers. The
TPA3004D2 can drive stereo speakers as low as 4 Ÿ. The high efficiency of the TPA3004D2 eliminates the need for
external heatsinks when playing music.
Stereo speaker volume is controlled with a dc voltage applied to the volume control terminal offering a range of gain from –
40 dB to 36 dB. Line outputs, for driving external headphone amplifier inputs, are also dc voltage controlled with a range
of gain from –56 dB to 20 dB.
An integrated 5-V regulated supply is provided for powering an external headphone amplifier.
8
10. POWER SUPPLY (SMPS)
The DC voltages required at various parts of the chassis are provided by an SMPS transformer controlled by the IC
MC44608, which is designed for driving, controlling and protecting switching transistor of SMPS. The transformer
generates 145V for FBT input, +/-14V for audio amplifier, 5V and 3.3V stand by voltage and 8V, 12V and 5V supplies for
other different parts of the chassis.
An optocoupler is used to control the regulation of line voltage and stand-by power consumption. There is a regulation
circuit in secondary side. This circuit produces a control voltage according to the changes in 145V DC voltage, via an
optocoupler (TCET1102G) to pin3 of the IC.
During the switch on period of the transistor, energy is stored in the transformer. During the switch off period
energy is fed to the load via secondary winding. By varying switch-on time of the power transistor, it controls
each portion of energy transferred to the second side such that the output voltage remains nearly independent
of load variations.
11.
MICROCONTROLLER
The Micronas SDA 55xx TV microcontroller is dedicated to 8 bit applications for TV control and provides dedicated
graphic features designed for modern low class to mid range TV sets. The SDA 55xx provides also an integrated
general purposefully 8051-compatible microcontroller with specific hardware features especially suitable in TV sets.
The microcontroller core has been enhanced to provide powerful features such as memory banking, data pointers and
additional interrupts, etc. The internal XRAM consists of up to 16 kBytes. The microcontroller provides an internal
ROM of up to 128 kBytes. ROMless versions can access up to 1 MByte of external RAM and ROM. The 8-bit
microcontroller runs at 33.33 MHz internal clock. SDA 55xx is realized in 0.25 micron technology with 2.5 V supply
voltage for the core and 3.3 V for the I/O port pins to make them TTL compatible. Based on the SDA 55xx
microcontroller the MINTS software package was developed and provides dedicated device drivers for many Micronas
video & audio products and includes a full blown TV control SW for the PEPER application chassis. The SDA 55xx is
also supported with powerful design tools like emulators from Hitex, Kleinhenz, iSystems, the Keil C51 Compiler and
TEDIpro OSD development SW by Tara Systems.
12.
SERIAL ACCESS CMOS 4Kx8(32KBit)EEPROM 24C32A
The Microchip Technology Inc. 24AA32A/24LC32A(24XX32A*) is a 32 Kbit Electrically Erasable PROM. The device is
organized as four blocks of 8K x 8-bitmemory with a 2-wire serial interface. Low-voltage design permits operation
down to 1.8V, with standby and active currents of only 1μA and 1mA, respectively. It has been developed for
advanced, low-power applications such as personal communications or data acquisition. The 24XX32A also has a
page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for
up to 256Kbits address space.
13.
CLASS AB STEREO HEADPHONE DRIVER TDA1308
The TDA1308 is an integrated class AB stereo headphone driver contained in a DIP8 plastic package. The
device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio
applications.
14.
SAW FILTERS
K9656M:
Standard:
• B/G
• D/K
•I
• L/L’
Features
• TV IF audio filter with two channels
• Channel 1 (L’) with one pass band for sound carriers at 40.40 MHz (L’) and 39.75 MHz (L’- NICAM)
• Channel 2 (B/G, D/K, L, I) with one pass band for sound carriers between 32.35 MHz and 33.40 MHz
Terminals
• Tinned CuFe alloy
Pin configuration
1 Input
2 Switching input
3 Chip carrier - ground
4 Output
5 Output
9
K3958M:
Standard:
• B/G
• D/K
•I
• L/L’
Features
• TV IF video filter with Nyquist slopes at 33.90 MHz and 38.90 MHz
• Constant group delay
Terminals
Tinned CuFe alloy
Pin configuration
1 Input
2 Input - ground
3 Chip carrier - ground
4 Output
5 Output
15. IC DESCRIPTIONS
TEA6415C
24LC02
24C32
74LVC14A
TEA6420D
CS4334
GAL16LV8
K6R4008V1
KA278R33
LM1117
LM317T
LM809
MSP3411G
M29W040B
MC33202
PCF8574
TSOP1836
PI5V330
SDA5550
SII9993
SN74CB3Q3305
ST24LC21
LM2576
MC34063
TDA1308
TDA9886T
TPA3004D2
μPA672T
VPC3230D
MAD4868A
SVP EX-59B
TEA6415C
General Description
The main function of the IC is to switch 8 video input sources on 6 outputs. Each output can be switched on only
one of each input. On each input an alignment of the lowest level of the signal is made (bottom of synch. top for
CVBS or black level for RGB signals). Each nominal gain between any input and output is 6.5dB. For D2MAC or
Chroma signal the alignment is switched off by forcing, with an external resistor bridge, 5 VDC on the input. Each
input can be used as a normal input or as a MAC or Chroma input (with external resistor bridge). All the
switching possibilities are changed through the BUS. Driving 75Ÿ load needs an external transistor. It is possible
10
to have the same input connected to several outputs. The starting configuration upon power on (power supply: 0
to 10V) is undetermined. In this case, 6 words of 16 bits are necessary to determine one configuration. In other
case, 1 word of 16 bits is necessary to determine one configuration.
Features
• 20MHz Bandwidth
• Cascadable with another TEA6415C (Internal address can be changed by pin 7 voltage)
• 8 Inputs (CVBS, RGB, MAC, CHROMA,...)
• 6 Outputs
• Possibility of MAC or chroma signal for each input by switching-off the clamp with an external resistor bridge
• Bus controlled
• 6.5dB gain between any input and output
• 55dB crosstalk at 5mHz
• Fully ESD protected
Pinning
1.
Input
:
Max
: 2Vpp, Input Current: 1mA, Max
: 3mA
2.
Data
:
Low level
: -0.3V Max: 1.5V,
High level
: 3.0V Max
: Vcc+0.5V
3.
Input
:
Max
: 2Vpp, Input Current: 1mA,
Max
: 3mA
4.
Clock
:
Low level
: -0.3V Max: 1.5V,
High level
: 3.0V Max
: Vcc+0.5V
5.
Input
:
Max
: 2Vpp, Input Current: 1mA, Max
: 3mA
6.
Input
:
Max
: 2Vpp, Input Current: 1mA, Max
: 3mA
7.
Prog
8.
Input
:
Max
: 2Vpp, Input Current: 1mA, Max: 3mA
9.
Vcc
:
12V
10.
Input
:
Max
: 2Vpp, Input Current: 1mA, Max
: 3mA
11.
Input
:
Max
: 2Vpp, Input Current: 1mA, Max
: 3mA
12.
Ground
13.
Output
:
5.5Vpp,
Min : 4.5Vpp
14.
Output
:
5.5Vpp,
Min : 4.5Vpp
15.
Output
:
5.5Vpp,
Min : 4.5Vpp
16.
Output
:
5.5Vpp,
Min : 4.5Vpp
17.
Output
:
5.5Vpp,
Min : 4.5Vpp
18.
Output
:
5.5Vpp,
Min : 4.5Vpp
19.
Ground
20.
Input
:
Max : 2Vpp, Input Current
: 1mA, Max
: 3mA
11
15.1. 24LC02
15.1.1. Description
The Microchip Technology Inc. 24AA02/24LC02B (24XX02*) is a 2 Kbit Electrically Erasable PROM. The device
is organized as one block of 256 x 8-bit memory with a 2-wire serial interface. Low-voltage design permits
operation down to 1.8V, with standby and active currents of only 1μA and 1mA, respectively. The 24XX02 also
has a page write capability for up to 8 bytes of data.
15.1.2. Features
• Single supply with operation down to 1.8V
• Low-power CMOS technology
-1mA active current typical
-1μA standby current typical (I-temp)
• Organized as 1 block of 256 bytes (1 x 256 x 8)
• 2-wire serial interface bus, I2C™ compatible
• Schmitt Trigger inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz (24AA02) and 400 kHz (24LC02B) compatibility
• Self-timed write cycle (including auto-erase)
• Page write buffer for up to 8 bytes
• 2ms typical write cycle time for page write
• Hardware write-protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
• 1,000,000 erase/write cycles
• Data retention > 200 years
• 8-lead PDIP, SOIC, TSSOP and MSOP packages
• 5-lead SOT-23 package
• Pb-free finish available
• Available for extended temperature ranges:
-Industrial (I): -40°C to +85°C
-Automotive (E): -40°C to +125°C
15.1.3. Pinning
12
15.2. 24C32
15.2.1. General Description
The Microchip Technology Inc. 24C32 is a 4K x 8 (32K bit) Serial Electrically Erasable PROM. This device has
been developed for advanced, low power applications such as personal communications or data acquisition.
The 24C32 features an input cache for fast write loads with a capacity of eight 8-byte pages, or 64 bytes. It also
features a fixed 4K-bit block of ultra-high endurance memory for data that changes frequently. The 24C32 is
capable of both random and sequential reads up to the 32K boundary. Functional address lines allow up to 8 24C32 devices on the same bus, for up to 256K bits address space. Advanced CMOS technology makes this
device ideal for low-power non-volatile code and data applications.
15.2.2. Features
• Voltage operating range: 4.5V to 5.5V
- Peak write current 3 mA at 5.5V
- Maximum read current 150μA at 5.5V
- Standby current 1μA typical
• Industry standard two-wire bus protocol, I2C™ compatible
-Including 100 kHz and 400 kHz modes
• Self-timed write cycle (including auto-erase)
• Power on/off data protection circuitry
• Endurance:
- 10,000,000 Erase/Write cycles guaranteed for High Endurance Block
- 10,000,000 E/W cycles guaranteed for Standard Endurance Block
• 8 byte page, or byte modes available
• 1 page x 8 line input cache (64 bytes) for fast write
loads
• Schmitt trigger, filtered inputs for noise suppression
• Output slope control to eliminate ground bounce
• 2 ms typical write cycle time, byte or page
• Up to 8 chips may be connected to the same bus for up to 256K bits total memory
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• Temperature ranges:
-Commercial (C): 0°C to +70°C
-Industrial (I): -40°C to +85°C
15.2.3. Pinning
13
15.2.4. PIN Function Table
PIN DESCRIPTIONS
A0, A1, A2 Chip Address Inputs
The A0...A2 inputs are used by the 24C32 for multiple device operation and conform to the two-wire bus standard. The levels applied to these pins define the address block occupied by the device in the address map. A
particular device is selected by transmitting the corresponding bits (A2, A1, and A0) in the control byte.
SDA Serial Address/Data Input/Output
This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open drain
terminal; therefore the SDA bus requires a pull-up resistor to VCC (typical 10KQ for 100 kHz, 1KQ for 400 kHz).
For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved
for indicating the START and STOP conditions.
SCL Serial Clock
This input is used to synchronize the data transfer from and to the device.
15.3. 74LVC14A
15.3.1. Description
The 74LVC14A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced
CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5V devices. This feature allows the use of
these devices as translators in a mixed 3.3 and 5V environment. The 74LVC14A provides six inverting buffers with
Schmitt-trigger action. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output
signals.
15.3.2. Features
• Wide supply voltage range from 1.2 to 3.6 V
• CMOS low power consumption
• Direct interface with TTL levels
• Inputs accept voltages up to 5.5 V
• Complies with JEDEC standard no.8-1A
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000V
MM EIA/JESD22-A115-A exceeds 200V.
• Specified from -40 to +85C and -40 to +125C.
15.3.3. Pinning
14
15.4. TEA6420
15.4.1. Features
• 5 Stereo Inputs
• 4 Stereo Outputs
• Gain Control 0/2/4/6dB/Mute for each Output
• Cascadable (2 different addresses)
• Serial Bus Controlled
• Very low Noise
• Very low Distortion
15.4.2. Description
The TEA6420 switches 5 stereo audio inputs on4stereo outputs. All the switching possibilities are changed
through the I2C bus.
15.4.3. Pin Connections
15.5. CS4334
15.5.1. Features
• Complete Stereo DAC System: Interpolation, D/A, Output Analog Filtering
• 24-Bit Conversion
15
• 96 dB Dynamic Range
• -88 dB THD+N
• Low Clock Jitter Sensitivity
• Single +5V Power Supply
• Filtered Line Level Outputs
• On-Chip Digital De-emphasis
• Popgaurd® Technology
• Functionally Compatible with CS4330/31/33
15.5.2. General Description
The CS4334 family members are complete, stereo digital-to-analog output systems including interpolation, 1bitD/A conversion and output analog filtering in an 8-pinpackage. The CS4334/5/6/7/8/9 support all major audio
data interface formats, and the individual devices differ only in the supported interface format. The CS4334
family is based on delta-sigma modulation, where the modulator output controls the reference voltage input to
an ultra-linear analog low-pass filter. This architecture allows for infinite adjustment of sample rate between 2
kHz and 100 kHz simply by changing the master clock frequency. The CS4334 family contains on-chip digital
de-emphasis, operates from a single +5V power supply, and requires minimal support circuitry. These features
are ideal for set-top boxes, DVD players, SVCD players, and A/V receivers.
15.5.3. Pin Descriptions
15.6. GAL16LV8
15.6.1. Description
The GAL16LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance available
in the PLD market. The GAL16LV8C can interface with both 3.3V and 5Vsignal levels. The GAL16LV8 is
manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with
Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be
reprogrammed quickly and efficiently.
The 3.3V GAL16LV8 uses the same industry standard 16V8 architecture as its 5V counterpart and supports all
architectural features such as combinatorial or registered macrocell operations.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during
manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all
GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
15.6.2. Features
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
- 3.5 ns Maximum Propagation Delay
- Fmax = 250 MHz
16
- 2.5 ns Maximum from Clock Input to Data Output
- UltraMOS® Advanced CMOS Technology
• 3.3V LOW VOLTAGE 16V8 ARCHITECTURE
- JEDEC-Compatible 3.3V Interface Standard
- 5V Compatible Inputs
- I/O Interfaces with Standard 5V TTL Devices (GAL16LV8C)
• ACTIVE PULL-UPS ON ALL PINS (GAL16LV8D Only)
• E2 CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
- 100% Tested/100% Yields
- High Speed Electrical Erasure (<100ms)
- 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
- Programmable Output Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
- 100% Functional Testability
• APPLICATIONS INCLUDE:
- Glue Logic for 3.3V Systems
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONS
15.6.3. Pin connections
15.7.
15.8. K6R4008V1D
15.8.1. Description
The K6R4008V1D is a 4,194,304-bit high-speed Static Random Access Memory organized as 524,288 words by
8 bits. TheK6R4008V1D uses 8 common input and output lines and has an output enable pin which operates
faster than address access time at read cycle. The device is fabricated using SAMSUNGƍs advanced CMOS
process and designed for high-speed circuit technology. It is particularly well suited for use in high-density highspeed system applications. The K6R4008V1D is packaged in a 400 mil 36-pin plastic SOJ and 44-pin plastic
TSOP type II.
15.8.2. Features
• Fast Access Time 8, 10ns(Max.)
• Low Power Dissipation
- Standby (TTL) : 20mA(Max.)
(CMOS) : 5mA(Max.)
- Operating K6R4008V1D-08 : 80mA(Max.)
17
K6R4008V1D-10 : 65mA(Max.)
• Single 3.3 ±0.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
K6R4008V1D-J : 36-SOJ-400
K6R4008V1D-K : 36-SOJ-400(Lead-Free)
K6R4008V1D-T : 44-TSOP2-400BF
K6R4008V1D-U : 44-TSOP2-400BF(Lead-Free)
• Operating in Commercial and Industrial Temperature range.
15.8.3. Pin Description
15.9. KA278R33
15.9.1. Features
• 2A / 3.3V Output low dropout voltage regulator
• TO220 Full-Mold package (4PIN)
• Overcurrent protection, Thermal shutdown
• Overvoltage protection, Short-Circuit protection
• With output disable function
15.9.2. Description
The KA278R33 is a low-dropout voltage regulator suitable for various electronic equipments. It provides
constant voltage power source with TO-220 4 lead full mold package. Dropout voltage of KA278R33 is below
18
0.5V in full rated current (2A). This regulator has various function such as peak current protection, thermal shut
down, overvoltage protection and output disable function.
15.10.
LM1117
15.10.1. General Description
The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA of load current. It has the same
pin-out as National Semiconductor’s industry standard LM317. The LM1117 is available in an adjustable version, which
can set the output voltage from 1.25V to 13.8V with only two external resistors. In addition, it is also available in five fixed
voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V.
The LM1117 offers current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap
reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is available in SOT-223, TO220, and TO-252 D-PAK packages. A minimum of 10μF tantalum capacitor is required at the output to improve
the transient response and stability.
15.10.2. Features
• Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions
• Space Saving SOT-223 Package
• Current Limiting and Thermal Protection
• Output Current 800mA
• Line Regulation 0.2% (Max)
• Load Regulation 0.4% (Max)
• Temperature Range
— LM1117 0°C to 125°C
— LM1117I -40°C to 125°C
15.10.3. Applications
• 2.85V Model for SCSI-2 Active Termination
• Post Regulator for Switching DC/DC Converter
• High Efficiency Linear Regulators
• Battery Charger
• Battery Powered Instrumentation
Connection Diagrams
15.11.
LM317
15.11.1. General Description
This monolithic integrated circuit is an adjustable 3-terminal positive voltage regulator designed to supply more
than 1.5A of load current with an output voltage adjustable over a 1.2 to 37V. It employs internal current limiting,
thermal shut-down and safe area compensation.
15.11.2. Features
• Output Current In Excess of 1.5A
• Output Adjustable Between 1.2V and 37V
• Internal Thermal Overload Protection
• Internal Short Circuit Current Limiting
• Output Transistor Safe Operating Area Compensation
• TO-220 Package
19
15.11.3. Pin Description
15.12.
LM809
15.12.1. General Description
The LM809/810 microprocessor supervisory circuits can be used to monitor the power supplies in microprocessor and
digital systems. They provide a reset to the microprocessor during power-up, power-down and brown-out conditions.
The function of the LM809/810 is to monitor the VCC supply voltage, and assert a reset signal whenever this voltage
declines below the factory-programmed reset threshold. The reset signal remains asserted for 240 ms after VCC rises
above the threshold. The LM809 has an active-low RESET output, while the LM810 has an active-high RESET output.
Seven standard reset voltage options are available, suitable for monitoring 5V, 3.3V, and 3V supply voltages. With a
low supply current of only 15μA, the LM809/810 are ideal for use in portable equipment.
15.12.2. Features
• Precise monitoring of 3V, 3.3V, and 5V supply voltages
• Superior upgrade to MAX809/810
• Fully specified overtemperature
• 140 ms min. Power-On Reset pulse width, 240 ms typical
Active-low RESET Output(LM809)
Active-high RESET Output(LM810)
• Guaranteed RESET Output valid for VCC•1V
• Low Supply Current, 15μAtyp
• Power supply transient immunity
15.12.3. Pinning
15.13.
MSP34X1G (MSP3411G)
Multistandard Sound Processor Family
20
15.13.1. Introduction
The MSP 34x1G family of single-chip Multistandard Sound Processors covers the sound processing of all
analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing,
starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip. Figure
shows a simplified functional block diagram of the MSP 34x1G.
The MSP 34x1G has all functions of the MSP 34x0G with the addition of a virtual surround sound feature.
Surround sound can be reproduced to a certain extent with two loudspeakers. The MSP 34x1G includes the
Micronas virtualizer algorithm “3D-PANORAMA” which has been approved by the Dolby 1) Laboratories for with
the "Virtual Dolby Surround" technology. In addition, the MSP 34x1G includes the “PAN-ORAMA” algorithm.
These TV sound processing ICs include versions for processing the multichannel television sound (MTS) signal conforming
to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or
alternatively, Micronas Noise Reduction (MNR) is performed alignment free.
Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio
standard.
Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and
EIA-J. The MSP 34x1G has optimum stereo performance without any adjustments.
The MSP 34x1G has built-in automatic functions: The IC is able to detect the actual sound standard automatically (Automatic Standard Detection). Furthermore, pilot levels and identification signals can be evaluated
internally with subsequent switching between mono/stereo/bilingual; no I 2 C interaction is necessary (Automatic
Sound Selection).
Source Select
I2S bus interface consists of five pins:
1. I2S_DA_IN1, I2S_DA_IN2: For input, four channels (two channels per line, 2*16 bits) per sampling cycle (32
kHz) are transmitted.
2. I2S_DA_OUT: For output, two channels (2*16 bits) per sampling cycle (32 kHz) are transmitted.
3. I2S_CL: Gives the timing for the transmission of I2S serial data (1.024 MHz).
4. I2S_WS: The I2S_WS word strobe line defines the left and right sample.
15.13.2. Features
• Standard Selection with single I2C transmission
• Automatic Standard Detection of terrestrial TV standards
• Automatic Sound Selection (mono/stereo/bilingual), new registers MODUS, STATUS
• Two selectable sound IF (SIF) inputs
• Automatic Carrier Mute function
• Interrupt output programmable (indicating status change)
• Loudspeaker / Headphone channel with volume, balance, bass, treble, loudness
• AVC: Automatic Volume Correction
• Subwoofer output with programmable low-pass and complementary high-pass filter
• 5-band graphic equalizer for loudspeaker channel
• Spatial effect for loudspeaker channel
• Four Stereo SCART (line) inputs, one Mono input; two Stereo SCART outputs
21
• Complete SCART in/out switching matrix
• Two I2S inputs; one I2S output
• Dolby Pro Logic with DPL 351xA coprocessor
• All analog FM-Stereo A2 and satellite standards; AM-SECAM L standard
• Simultaneous demodulation of (very) high-deviation FM-Mono and NICAM
• Adaptive deemphasis for satellite (Wegener-Panda, acc. to ASTRA specification)
• ASTRA Digital Radio (ADR) together with DRP 3510A
• All NICAM standards
• Korean FM-Stereo A2 standard
Pin connections
NC = not connected; leave vacant
LV = if not used, leave vacant
OBL = obligatory; connect as described in circuit diagram
DVSS: if not used, connect to DVSS
AHVSS: connect to AHVSS
Pin No.
Pin Name
Type
OUT
Connection
(if not used)
PLCC
68-pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
PSDIP
64-pin
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
-
PSDIP
52-pin
14
13
12
11
10
9
8
7
6
5
4
3
-
PQFP
80-pin
9
8
7
6
5
4
3
2
1
80
79
78
77
76
75
-
PLQFP
64-pin
8
7
6
5
4
3
2
1
64
63
62
61
60
59
58
-
ADR_WS
NC
ADR_DA
I2S_DA_IN1
I2S_DA_OUT
I2S_WS
I2S_CL
I2C_DA
I2C_CL
NC
STANDBYQ
ADR_SEL
D_CTR_I/O_0
D_CTR_I/O_1
NC
NC
NC
18
1
2
74
57
AUD_CL_OUT
OUT
LV
19
20
21
22
64
63
62
61
1
52
51
50
73
72
71
70
56
55
54
53
TP
XTAL_OUT
XTAL_IN
TESTEN
OUT
IN
IN
LV
OBL
OBL
OBL
23
60
49
69
52
ANA_IN2+
IN
AVSS via
56 pF/LV
24
59
48
68
51
ANA_IN-
IN
AVSS via
56 pF/LV
25
26
27
28
-
58
57
56
55
-
47
46
45
44
-
67
66
65
64
63
62
61
60
59
50
49
48
47
-
ANA_IN1+
AVSUP
AVSUP
NC
NC
AVSS
AVSS
MONO_IN
NC
IN
29
54
43
58
46
VREFTOP
30
31
32
33
34
35
36
53
52
51
50
49
48
47
42
41
40
39
38
57
56
55
54
53
52
51
45
44
43
42
41
40
39
SC1_IN_R
SC1_IN_L
ASG1
SC2_IN_R
SC2_IN_L
ASG2
SC3_IN_R
OUT
IN
OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN
IN
IN/OUT
IN/OUT
IN
LV
LV
LV
LV
LV
LV
LV
OBL
OBL
LV
OBL
OBL
LV
LV
LV
LV
LV
LV
OBL
OBL
LV
LV
OBL
OBL
LV
LV
OBL
IN
IN
IN
IN
IN
22
LV
LV
AHVSS
LV
LV
AHVSS
LV
Short Description
ADR word strobe
Not connected
ADR Data Output
2
I S1 data input
2
I S data output
2
I S word strobe
2
I S clock
2
I C data
2
I C clock
Not connected
Stand-by (low-active)
2
I C bus address select
D_CTR_I/O_0
D_CTR_I/O_1
Not connected
Not connected
Not connected
Audio clock output
(18.432 MHz)
Test pin
Crystal oscillator
Crystal oscillator
Test pin
IF Input 2 (can be left
vacant, only if IF input 1 is
also not in use)
IF common (can be left
vacant, only if IF input 1 is
also not in use)
IF input 1
Analog power supply 5V
Analog power supply 5V
Not connected
Not connected
Analog ground
Analog ground
Mono input
Not connected
Reference voltage IF A/D
converter
SCART 1 input, right
SCART 1 input, left
Analog Shield Ground 1
SCART 2 input, right
SCART 2 input, left
Analog Shield Ground 2
SCART 3 input, right
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
15.14.
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
SC3_IN_L
ASG4
SC4_IN_R
SC4_IN_L
NC
AGNDC
AHVSS
AHVSS
NC
NC
CAPL_M
AHVSUP
CAPL_A
SC1_OUT_L
SC1_OUT_R
VREF1
SC2_OUT_L
SC2_OUT_R
NC
NC
DACM_SUB
NC
DACM_L
DACM_R
VREF2
DACA_L
DACA_R
NC
NC
RESETQ
NC
NC
NC
I2S_DA_IN2
DVSS
DVSS
DVSS
DVSUP
DVSUP
DVSUP
ADR_CL
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
LV
AHVSS
LV
LV
LV or AHVSS
OBL
OBL
OBL
LV
LV
OBL
OBL
OBL
LV
LV
OBL
LV
LV
LV
LV
LV
LV
LV
LV
OBL
LV
LV
LV
LV
OBL
LV
LV
LV
LV
OBL
OBL
OBL
OBL
OBL
OBL
LV
SCART 3 input, left
Analog Shield Ground 4
SCART 4 input, right
SCART 4 input, left
Not connected
Analog reference voltage
Analog ground
Analog ground
Not connected
Not connected
Volume capacitor MAIN
Analog power supply 8V
Volume capacitor AUX
SCART output 1, left
SCART output 1, right
Reference ground 1
SCART output 2, left
SCART output 2, right
Not connected
Not connected
Subwoofer output
Not connected
Loudspeaker out, left
Loudspeaker out, right
Reference ground 2
Headphone out, left
Headphone out, right
Not connected
Not connected
Power-on-reset
Not connected
Not connected
Not connected
2
I S2-data input
Digital ground
Digital ground
Digital ground
Digital power supply 5V
Digital power supply 5V
Digital power supply 5V
ADR clock
M29W040B
15.14.1. Description
The M29W040B is a 4 Mbit (512Kb x8) non-volatile memory that can be read, erased and reprogrammed. These operations
can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode
where it can be read in the same way as a ROM or EPROM. The M29W040B is fully backward compatible with the
M29W040.The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while
old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from
modifying the memory. Program and Erase commands are writ-ten to the Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special
operations that are required to update the memory contents. The end of a program or erase operation can be detected and
any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. Chip
Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to
most microprocessors, often without additional logic.
15.14.2. Features
• SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS
• ACCESS TIME: 55ns
• PROGRAMMING TIME
- 10μs per Byte typical8
• UNIFORM 64 Kbytes MEMORY BLOCKS
• PROGRAM/ERASE CONTROLLER
- Embedded Byte Program algorithm
- Embedded Multi-Block/Chip Erase algorithm
- Status Register Polling and Toggle Bits
23
• ERASE SUSPEND and RESUME MODES
- Read and Program another Block during Erase Suspend
• UNLOCK BYPASS PROGRAM COMMAND
- Faster Production/Batch Programming
• LOW POWER CONSUMPTION
- Standby and Automatic Standby
• 100,000 PROGRAM/ERASE CYCLES per BLOCK
• 20 YEARS DATA RETENTION
- Defectivity below 1 ppm/year
• ELECTRONIC SIGNATURE
- Manufacturer Code: 20h
- Device Code: E3h
15.14.3. Pin Descriptions
15.15.
MC33202
15.15.1. General Description
The MC33201/2/4 family of operational amplifiers provide railítoírail operation on both the input and output.
The inputs can be driven as high as 200mV beyond the supply rails without phase reversal on the outputs, and
the output can swing within 50 mV of each rail. This railítoírail operation enables the user to make full use of
the supply voltage range available. It is designed to work at very low supply voltages (±0.9 V) yet can operate
with a supply of up to +12V and ground. Output current boosting techniques provide a high output current
capability while keeping the drain current of the amplifier to a minimum. Also, the combination of low noise and
distortion with a high slew rate and drive capability make this an ideal amplifier for audio applications.
15.15.2. Features
• Low Voltage, Single Supply Operation (+1.8 V and Ground to +12 V and Ground)
• Input Voltage Range Includes both Supply Rails
• Output Voltage Swings within 50 mV of both Rails
• No Phase Reversal on the Output for Overídriven Input Signals
• High Output Current (ISC = 80 mA, Typ)
• Low Supply Current (ID = 0.9 mA, Typ)
• 600 Ÿ Output Drive Capability
• Extended Operating Temperature Ranges (í40° to +105°C and í55° to +125°C)
• Typical Gain Bandwidth Product = 2.2 MHz
• PbíFree Packages are Available
24
15.15.3. Pin Connections
15.16.
PCF8574
15.16.1. General Description
The PCF8574 is a silicon CMOS circuit. It provides general purpose remote I/O expansion for most microcontroller
families via the two-line bidirectional bus (I2C).The device consists of an 8-bit quasi-bidirectional port and an I2C-bus
interface. The PCF8574 has a low current consumption and includes latched outputs with high current drive capability for
directly driving LEDs. It also possesses an interrupt line (INT) which can be connected to the interrupt logic of the
microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is
incoming data on its ports without having to communicate via the I2C-bus. This means that the PCF8574 can remain a
simple slave device.
15.16.2. Features
• Operating supply voltage 2.5 to 6V
• Low standby current consumption of 10 μA maximum
• I2C to parallel port expander
• Open-drain interrupt output
• 8-bit remote I/O port for the I2C-bus
• Compatible with most microcontrollers
• Latched outputs with high current drive capability for directly driving LEDs
• Address by 3 hardware address pins for use of up to 8 devices (up to 16 with PCF8574A)
• DIP16, or space-saving SO16 or SSOP20 packages.
15.16.3. Pinning
25
15.17.
TSOP1836
15.17.1. Description
The TSOP18.– series are miniaturized receivers for infrared remote control systems. PIN diode and preamplifier
are assembled on lead frame, the epoxy package is designed as IR filter. Carrier frequency for TSOP1836 is 36
kHz.
The demodulated output signal can directly be decoded by a microprocessor. The main benefit is the reliable
function even in disturbed ambient and the protection against uncontrolled output pulses.
15.17.2. Features
• Photo detector and preamplifier in one package
• Internal filter for PCM frequency
• TTL and CMOS compatibility
• Output active low
• Improved shielding against electrical field disturbance
• Suitable burst length .6 cycles/burst
Special Features
• Small size package
• Enhanced immunity against all kinds of disturbance light
• No occurrence of disturbance pulses at the output
• Short settling time after power on (<200_s)
15.18.
PI5V330
15.18.1. General Description
The PI5V330 is well suited for video applications when switching composite or RGB analogue. A picture-inpicture application will be described in this brief. The pixel-rate creates video overlays so two or more pictures
can be viewed at the same time. An inexpensive NTSC titler can be implemented by superimposing the output
of a character generator on a standard composite video background.
26
15.19.
SDA55XX (SDA5550)
15.19.1. General description
The SDA55XX is a single chip teletext decoder for decoding World System Teletext data as well as Video
Programming System (VPS), Program Delivery Control (PDC), and Wide Screen Signalling (WSS) data used for
PAL plus transmissions (Line 23). The device also supports Closed caption acquisition and decoding. The
device provides an integrated general-purpose, fully 8051-compatible Microcontroller with television specific
hardware features. Microcontroller has been enhanced to provide powerful features such as memory banking,
data pointers, and additional interrupts etc. The on-chip display unit for displaying Level 1.5 teletext data can
also be used for customer defined on screen displays. Internal XRAM consists of up to16 Kbytes. Device has an
internal ROM of up to 128 KBytes. ROMless versions can access up to 1 MByte of external RAM and ROM. The
SDA 55XX supports a wide range of standards including PAL, NTSC and contains a digital slicer for VPS, WSS,
PDC, TTX and Closed Caption, an accelerating acquisition hardware module, a display generator for Level 1.5
TTX data and powerful On screen Display capabilities based on parallel attributes, and Pixel oriented characters
(DRCS).
The 8-bit Microcontroller runs at 360 ns. cycle time (min.). Controller with dedicated hardware does most of the
internal TTX acquisition processing, transfers data to/from external memory interface and receives/ transmits
data via I2C-firmware user-interface. The slicer combined with dedicated hardware stores TTX data in a VBI
buffer of 1 Kilobyte. The Microcontroller firmware performs all the acquisition tasks (hamming and parity-checks,
page search and evaluation of header control bits) once per field. Additionally, the firmware can provide highend Teletext features like Packet-26-handling, FLOF, TOP and list-pages. The interface to user software is
optimized for minimal overhead. SDA 55XX is realized in 0.25 micron technology with 2.5 V supply voltage and
3.3 V I/O (TTL compatible). The software and hardware development environment (TEAM) is available to
simplify and speed up the development of the software and On Screen Display. TEAM stands for TVT Expert
Application Maker. It improves the TV controller software quality in following aspects:
– Shorter time to market
– Re-usability
– Target independent development
– Verification and validation before targeting
– General test concept
– Graphical interface design requiring minimum programming and controller know how.
– Modular and open tool chain, configurable by customer.
15.20.
Sil 9993
15.20.1. General Description
The SiI 9993 is the first generation of PanelLink receivers that are designed for the HDMI 1.0 (High Definition Multimedia
Interface) specification. DTVs, plasma displays, LCD TVs and projectors can now provide the purest level of protected
digital audio/video over a simple, low cost cable. Backwards compatibility with DVI 1.0 allows HDMI systems to connect
to any DVI 1.0 host (DVD players, HD set top boxes, D-VHS players and receivers, PC). The SiI 9993 incorporates a
flexible audio and video interface. The receiver can connect to RGB input and output YCbCr using an integrated color
space converter. This allows full backward compatibility to DVI, and interfaces to all major video processors. A S/PDIF
port can output PCM encoded data as well as Dolby Digital, DTS and all other formats capable of being sent over S/PDIF.
A 2-channel I2S port outputs data converted from S/PDIF. The SiI 9993 comes pre-programmed with HDCP keys, greatly
simplifying the manufacturing process, lowering costs, all the while providing the highest level of HDCP key security.
Silicon Image’s PanelLink receivers use the latest generation of PanelLink TMDS core technology. These PanelLink cores
pass all HDMI compliancy tests.
15.20.2. Features
• HDMI 1.0 and DVI 1.0 compliant receiver
• Integrated PanelLink core supports DTV resolutions (480i/576i/480p/576p/720p/1080i)
• Digital video interface supports video processors:
o 24-bit RGB 4:4:4
o 24-bit YCbCr 4:4:4
o 16/20/24-bit YCbCr 4:2:2
o 8/10/12-bit YCbCr 4:2:2 embedded syncs
• Analog RGB and YPbPr output:
o 10-bit DAC
o Separate or Composite Syncs (Sync on G)
27
• S/PDIF output supports PCM, Dolby Digital, DTS digital audio transmission (32-48kHz Fs) using IEC 60958
and IEC 61937.
• Programmable I2S interface for connection to low-cost audio DACs.
• Integrated HDCP decryption engine for receiving protected audio and video content
• Pre-programmed HDCP keys provide highest level of key security, simplifies manufacturing
• Programmable registers via slave I2C interface
• 3.3V operation in 100-pin TQFP package
• Flexible power management
15.21.
SN74CB3Q3305
15.21.1. General Description
The SN74CB3Q3305 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of
the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance
allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The
device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data
bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3305 provides an optimized
interface solution ideally suited for broadband communications, networking, and data-intensive computing
systems.
15.21.2. Features
• High-Bandwidth Data Path (Up To 500 MHz)
• 5-V Tolerant I/Os with Device Powered-Up or Powered-Down
• Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 3 Ÿ Typical)
• Rail-to-Rail Switching on Data I/O Ports
í 0- to 5-V Switching With 3.3-V VCC
í 0- to 3.3-V Switching With 2.5-V VCC
• Bidirectional Data Flow, With Near-Zero Propagation Delay
• Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 3.5 pF Typical)
• Fast Switching Frequency (fOE = 20 MHz Max)
• Data and Control Inputs Provide Undershoot Clamp Diodes
• Low Power Consumption (ICC = 0.25 mA Typical)
• VCC Operating Range From 2.3 V to 3.6 V
• Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
• Control Inputs Can be Driven by TTL or 5-V/3.3-V CMOS Outputs
• Ioff Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II
• ESD Performance Tested Per JESD 22
í 2000-V Human-Body Model (A114-B, Class II)
í 1000-V Charged-Device Model (C101)
• Supports Both Digital and Analog Applications: USB Interface, Differential Signal Interface, Bus Isolation, LowDistortion Signal Gating
15.21.3. Pin Connections
15.22.
ST24LC21
15.22.1. Description
The ST24LC21 is a 1K bit electrically erasable programmable memory (EEPROM), organized by 8 bits. This
device can operate in two modes: Transmit Only mode and I2C bidirectional mode. When powered, the device is
in Transmit Only mode with EEPROM data clocked out from the rising edge of the signal applied on VCLK. The
device will switch to the I2C bidirectional mode upon the falling edge of the signal applied on SCL pin. The
28
ST24LC21 can not switch from the I2C bidirectional mode to the Transmit Only mode (except when the power
supply is removed). The device operates with a power supply value as low as 2.5V. Both Plastic Dual-in-Line
and Plastic Small Outline packages are available.
15.22.2. Features
• 1 million Erase/Write cycles
• 40 years data retention
• 2.5V to 5.5V single supply voltage
• 400k Hz compatibility over the full range of supply voltage
• Two wire serial interface I2C bus compatible
• Page Write (Up To 8 Bytes)
• Byte, random and sequential read modes
• Self timed programming cycle
• Automatic address incrementing
• Enhanced ESD/Latch up
• Performances
15.22.3. Pin connections
DIP Pin connections
CO Pin connections
NC: Not connected
Signal names
SDA
SCL
Vcc
Vss
VCLK
Serial data Address Input/Output
2
Serial Clock (I C mode)
Supply voltage
Ground
Clock transmit only mode
15.23.
LM2576
15.23.1. General Description
The LM2576 series of regulators are monolithic integrated circuits ideally suited for easy and convenient design of a step–
down switching regulator (buck converter). All circuits of this series are capable of driving a 3.0 A load with excellent line
and load regulation.
These devices are available in fixed output voltages of 3.3 V, 5.0 V, 12 V, 15 V, and an adjustable output
version. These regulators were designed to minimize the number of external components to simplify the power
supply design. Standard series of inductors optimized for use with the LM2576 are offered by several different
inductor manufacturers.
Since the LM2576 converter is a switch–mode power supply, its efficiency is significantly higher in comparison
with popular three–terminal linear regulators, especially with higher input voltages. In many cases, the power
dissipated is so low that no heatsink is required or its size could be reduced dramatically.
A standard series of inductors optimized for use with the LM2576 are available from several different
manufacturers. This feature greatly simplifies the design of switch–mode power supplies.
The LM2576 features include a guaranteed ±4% tolerance on output voltage within specified input voltages and
output load conditions, and ±10% on the oscillator frequency (±2% over 0°C to 125°C). External shutdown is
included, featuring 80 mA (typical) standby current. The output switch includes cycle–by–cycle current limiting,
as well as thermal shutdown for full protection under fault conditions.
15.23.2. Features
• 3.3 V, 5.0 V, 12 V, 15 V, and Adjustable Output Versions
29
• Adjustable Version Output Voltage Range, 1.23 to 37 V ±4% Maximum Over Line and Load Conditions
• Guaranteed 3.0 A Output Current
• Wide Input Voltage Range
• Requires Only 4 External Components
• 52 kHz Fixed Frequency Internal Oscillator
• TTL Shutdown Capability, Low Power Standby Mode
• High Efficiency
• Uses Readily Available Standard Inductors
• Thermal Shutdown and Current Limit Protection
• Moisture Sensitivity Level (MSL) Equals 1
15.23.3. Pin description
15.24.
MC34063
15.24.1. Description
The MC34063A Series is a monolithic control circuit containing the primary functions required for DC–to–DC converters.
These devices consist of an internal temperature compensated reference, comparator, controlled duty cycle oscillator with
an active current limit circuit, driver and high current output switch. This series was specifically designed to be
incorporated in Step–Down and Step–Up and Voltage–Inverting applications with a minimum number of external
components.
15.24.2. Features
• Operation from 3.0 V to 40 V Input
• Low Standby Current
• Current Limiting
• Output Switch Current to 1.5 A
• Output Voltage Adjustable
• Frequency Operation to 100 kHz
• Precision 2% Reference
15.24.3. Pin connections
30
15.25.
TDA1308
15.25.1. General Description
The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8 or a DIP8 plastic
package. The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable
digital audio applications.
15.25.2. Features
• Wide temperature range
• No switch ON/OFF clicks
• Excellent power supply ripple rejection
• Low power consumption
• Short-circuit resistant
• High performance
• high signal-to-noise ratio
• High slew rate
• Low distortion
• Large output voltage swing.
15.25.3. Pinning
SYMBOL
OUTA
INA(neg)
INA(pos)
VSS
INB(pos)
INB(neg)
OUTB
VDD
15.26.
PIN
1
2
3
4
5
6
7
8
DESCRIPTION
Output A (Voltage swing)
Inverting input A
Non-inverting input A
Negative supply
Non-inverting input B
Inverting input B
Output B (Voltage swing)
Positive supply
PIN VALUE
Min : 0.75V, Max : 4.25V
Vo(clip) : Min : 1400mVrms
2.5V
0V
2.5V
Vo(clip) : Min : 1400mVrms
Min : 0.75V, Max : 4.25V
5V, Min : 3.0V, Max : 7.0V
TDA9886
15.26.1. General Description
The TDA9886 is an alignment-free single standard (without positive modulation) vision and sound IF signal PLL.
15.26.2. Features
• 5 V supply voltage
• Gain controlled wide-band Vision Intermediate Frequency (VIF) amplifier (AC-coupled)
• Multistandard true synchronous demodulation with active carrier regeneration (very linear demodulation, good
intermodulation figures, reduced harmonics, excellent pulse response)
• Gated phase detector for L/L accent standard
• Fully integrated VIF Voltage Controlled Oscillator (VCO), alignment-free; frequencies switchable for all negative and
positive modulated standards via I2C-bus
• Digital acquisition help, VIF frequencies of 33.4, 33.9, 38.0, 38.9, 45.75 and 58.75 MHz
• 4 MHz reference frequency input [signal from Phase-Locked Loop (PLL) tuning system] or operating as crystal
oscillator
• VIF Automatic Gain Control (AGC) detector for gain control, operating as peak sync detector for negative modulated
signals and as a peak white detector for positive modulated signals
• Precise fully digital Automatic Frequency Control (AFC) detector with 4-bit digital-to-analogue converter; AFC bits via
I2C -bus readable
• TakeOver Point (TOP) adjustable via I2C-bus or alternatively with potentiometer
• Fully integrated sound carrier trap for 4.5, 5.5, 6.0 and 6.5 MHz, controlled by FM-PLL oscillator
• Sound IF (SIF) input for single reference Quasi Split Sound (QSS) mode (PLL controlled)
• SIF AGC for gain controlled SIF amplifier; single reference QSS mixer able to operate in high performance single
reference QSS mode and in intercarrier mode, switchable via I2C-bus
31
• AM demodulator without extra reference circuit
• Alignment-free selective FM-PLL demodulator with high linearity and low noise
• I2C-bus control for all functions
• I2C-bus transceiver with pin programmable Module Address (MAD).
15.26.3. Pinning
SYMBOL
VIF1
VIF2
OP1
FMPLL
DEEM
AFD
DGND
AUD
TOP
SDA
SCL
SIOMA
n.c.
TAGC
REF
VAGC
CVBS
AGND
VPLL
VP
AFC
OP2
SIF1
SIF2
15.27.
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DESCRIPTION
VIF differential input 1
VIF differential input 2
output 1 (open-collector)
FM-PLL for loop filter
de-emphasis output for capacitor
AF decoupling input for capacitor
digital ground
audio output
tuner AGC TakeOver Point (TOP)
I2C-bus data input/output
I2C-bus clock input
sound intercarrier output and MAD select
not connected
tuner AGC output
4 MHz crystal or reference input
VIF-AGC for capacitor; note 1
video output
analog ground
VIF-PLL for loop filter
supply voltage (+5 V)
AFC output
output 2 (open-collector)
SIF differential input 1
SIF differential input 2
TPA3004D2
15.27.1. General Description
The TPA3004D2 is a 12-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied stereo speakers. The
TPA3004D2 can drive stereo speakers as low as 4 Ÿ. The high efficiency of the TPA3004D2 eliminates the need for
external heatsinks when playing music.
Stereo speaker volume is controlled with a dc voltage applied to the volume control terminal offering a range of gain from –
40 dB to 36 dB. Line outputs, for driving external headphone amplifier inputs, are also dc voltage controlled with a range
of gain from –56 dB to 20 dB.
An integrated 5-V regulated supply is provided for powering an external headphone amplifier.
15.27.2. Features
• 12-W/Ch Into an 8-Ÿ Load From 15-V Supply
• Efficient, Class-D Operation Eliminates Heatsinks and Reduces Power Supply Requirements
• 32-Step DC Volume Control From í40 dB to 36 dB
• Line Outputs For External Headphone Amplifier With Volume Control
• Regulated 5-V Supply Output for Powering TPA6110A2
• Space-Saving, Thermally-Enhanced PowerPADTM Packaging
• Thermal and Short-Circuit Protection.
32
15.27.3. Pinning
33
15.28.
15.29.
µPA672T
15.29.1. General Description
The μPA672T is a super-mini-mold device provided with two MOS FET elements. It achieves high-density
mounting and saves mounting costs.
15.29.2. Features
• Two MOS FET circuits in package the same size as SC-70
• Automatic mounting supported
15.29.3. Pin Connection
15.30.
VPC3230D
15.30.1. General Description
The VPC 323xD is a high-quality, single-chip video front-end, which is targeted for 4:3 and 16:9, 50/60-Hz and
100/120 Hz TV sets. It can be combined with other members of the DIGIT3000 IC family (such as DDP 331x)
and/or it can be used with 3rd-party products.
The main features of the VPC 323xD are
• high-performance adaptive 4H comb filter Y/C separator with adjustable vertical peaking
• multi-standard colour decoder PAL/NTSC/SECAM including all substandards
• four CVBS, one S-VHS input, one CVBS output
• two RGB/YCr Cb component inputs, one Fast Blank (FB) input
• integrated high-quality A/D converters and associated clamp and AGC circuits
• multi-standard sync processing
• linear horizontal scaling (0.25 ... 4), as well as non-linear horizontal scaling ‘Panorama-vision’
• PAL+ preprocessing
• line-locked clock, data and sync, or 656-output interface
• peaking, contrast, brightness, color saturation and tint for RGB/ YC r C b and CVBS/ S-VHS
• high-quality soft mixer controlled by Fast Blank
• PIP processing for four picture sizes (1/4, 1/9, 1/16 or 1/36 of normal size) with 8-bit resolution
• 15 predefined PIP display configurations and expert mode (fully programmable)
• control interface for external field memory
• I2C-bus interface
• one 20.25-MHz crystal, few external components
• 80-pin PQFP package
15.30.2. Pin Connections and Short Descriptions
NC = not connected
LV = if not used, leave vacant
X = obligatory; connect as described in circuit diagram
SUPPLYA = 4.75...5.25 V, SUPPLYD = 3.15...3.45 V
34
Pin No.
PQFP
80-pin
1
2
3
4
5
6
7
8
9
10
Pin Name
Type
Connection
(if not used)
Short Description
B1/CB1IN
G1/Y1IN
R1/CR1IN
B2/CB2IN
G2/Y2IN
R2/CR2IN
ASGF
FFRSTWIN
VSUPCAP
VSUPD
IN
IN
IN
IN
IN
IN
IN
OUT
SUPPLYD
VREF
VREF
VREF
VREF
VREF
VREF
X
LV or GNDD
X
X
Blue1/Cb1 Analog Component Input
Green1/Y1 Analog Component Input
Read1/Cr1 Analog Component Input
Blue2/Cb2 Analog Component Input
Green2/Y2 Analog Component Input
Read2/Cr2 Analog Component Input
Analog Shield GNDF
FIFO Reset Write Input
Digital Decoupling Circuitry Supply Voltage
Supply Voltage, Digital Circuitry
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
GNDD
GNDCAP
SCL
SDA
RESQ
TEST
VGAV
YCOEQ
FFIE
FFWE
FFRSTW
FFRE
FFOE
CLK20
GNDPA
VSUPPA
LLC2
LLC1
VSUPLLC
GNDLLC
Y7
Y6
Y5
Y4
GNDY
VSUPY
Y3
Y2
Y1
Y0
C7
C6
C5
C4
VSUPC
GNDC
C3
C2
C1
C0
GNDSY
VSUPSY
INTLC
AVO
FSY/HC/HSYA
SUPPLYD
OUT
IN/OUT
IN/OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
IN/OUT
OUT
OUT
OUT
IN/OUT
SUPPLYD
SUPPLYD
OUT
OUT
OUT
OUT
SUPPLYD
SUPPLYD
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
SUPPLYD
SUPPLYD
OUT
OUT
OUT
OUT
SUPPLYD
SUPPLYD
OUT
OUT
OUT
X
X
X
X
X
GNDD
GNDD
GNDD
LV
LV
LV
LV
LV
LV
X
X
LV
LV
X
X
GNDY
GNDY
GNDY
GNDY
X
X
GNDY
GNDY
GNDY
GNDY
GNDC
GNDC
GNDC
GNDC
X
X
GNDC
GNDC
GNDC
GNDC
X
X
LV
LV
LV
56
57
58
MSY/HS
VS
FPDAT/VSYA
IN/OUT
OUT
IN/OUT
LV
LV
LV
59
60
VSTBYY
CLK5
SUPPLYA
OUT
X
LV
Ground, Digital Circuitry
Digital Decoupling Circuitry GND
2
I C Bus Clock
2
I C Bus Data
Reset Input, Active Low
Test Pin, connect to GNDD
VGAV Input
Y/C Output Enable Input, Active Low
FIFO Input Enable
FIFO Write Enable
FIFO Reset Write/Read
FIFO Read Enable
FIFO Output Enable
Main Clock output 20.25 MHz
Pad Decoupling Circuitry GND
Pad Decoupling Circuitry Supply Voltage
Double Clock Output
Clock Output
Supply Voltage, LLC Circuitry
Ground, LLC Circuitry
Picture Bus Luma (MSB)
Picture Bus Luma
Picture Bus Luma
Picture Bus Luma
Ground, Luma Output Circuitry
Supply Voltage, Luma Output Circuitry
Picture Bus Luma
Picture Bus Luma
Picture Bus Luma
Picture Bus Luma (LSB)
Picture Bus Chroma (MSB)
Picture Bus Chroma
Picture Bus Chroma
Picture Bus Chroma
Supply Voltage, Chroma Output Circuitry
Ground, Chroma Output Circuitry
Picture Bus Chroma
Picture Bus Chroma
Picture Bus Chroma
Picture Bus Chroma (LSB)
Ground Sync Pad Circuitry
Supply Voltage, Sync Pad Circuitry
Interlace Output
Active Video Output
Front Sync/ Horizontal Clamp Pulse/Front-End
Horizontal Sync Output
Main Sync/Horizontal Sync Pulse
Vertical Sync Pulse
Front End/Back-End Data/Front-End Vertical Sync
Output
Standby Supply Voltage
CCU 5 MHz Clock Output
35
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
NC
XTAL1
XTAL2
ASGF
GNDF
VRT
I2CSEL
ISGND
VSUPF
VOUT
CIN
VIN1
VIN2
VIN3
VIN4
76
77
78
79
80
15.31.
IN
OUT
SUPPLYA
OUTPUT
IN
SUPPLYA
SUPPLYA
OUT
IN
IN
IN
IN
IN
LV or GNDD
X
X
X
X
X
X
X
X
LV
LV
VRT
VRT
VRT
VRT
Not Connected
Analog Crystal Input
Analog Crystal Output
Analog Shield GNDF
Ground, Analog Front-End
Reference Voltage Top, Analog
I2C Bus Address Select
Signal Ground for Analog Input, connect to GNDF
Supply Voltage, Analog Front-End
Analog Video Output
Chroma/Analog Video 5 Input
Video 1 Analog Input
Video 2 Analog Input
Video 3 Analog Input
Video 4 Analog Input
VSUPAI
GNDAI
VREF
SUPPLYA
SUPPLYA
OUTPUT
X
X
X
FB1IN
AISGND
IN
SUPPLYA
VREF
X
Supply Voltage, Analog Component Inputs Front-End
Ground, Analog Component Inputs Front-End
Reference Voltage Top, Analog Component Inputs
Front-End
Fast Blank Input
Signal Ground for Analog Component Inputs, connect
to GNDAI
MAD4868A
15.31.1. General Description
The Micronas Audio Delay IC MAD 4868A acts as a delay line for TV audio and consumer audio applications.
The IC is designed for synchronizing audio and video signals ensuring "Lip Sync" by delaying the audio signal
with the same amount of time as the video signal is delayed in a TV's video processing.
For TV designs, independent signals for loudspeakers, headphones, and line-out or S/PDIF out must be provided, resulting in the need to delay six independent audio channels.
15.31.2. Features
x
x
x
x
x
x
x
32 k audio samples RAM:
Total delay time of 680 ms at 48 kHz or 1020 ms at 32 kHz sampling rate
32/18-bit word width:
32-bit High-Resolution mode or 18-bit Standard mode
Sampling rates from 32 kHz to 48 kHz for
serial 8-channel mode are supported
Sampling rates from 4 kHz to 192 kHz for
parallel 2-channel mode are supported
Memory allocation:
MAD 4868A's memory can be allocated for 1... 8 audio channels. Delay time can be programmed for
each channel individually.
15.31.3. Interfaces
x
x
x
x
x
8-channel Micronas I2S input and output:
In combination with Micronas ICs (serial mode) (e.g. MSP 44/46xyK, MAS 35xyH), eight audio channels
can be routed through MAD 4868A by using four lines only.
4x2-channel standard I2S inputs and outputs (paral
lel mode) allow routing eight audio channels with
sampling rates of 4... 192 kHz through MAD 4868A
I2C control for delay time programming
Address select to set one out of two available I2C addresses.
36
15.31.4. Pinning
15.32.
SVP-EX 59B
General Description
To improve the video quality of the PAL CVBS and HD video input, the all layer changed EX59 improve video sharpness
function in HD channel and enhance the 3D PAL quality compared to EX52 Rev. D chips.
16. SERVICE MENU SETTINGS
To enter the service menu, first enter the MENU by pressing “
respectively.
37
” button and then press the digits 4, 7, 2 and 5
Service Menu Items
16.1. Picture Adjust
x
Source
=> All possible sources given with the chasis as a list.
x
Mode
=> Three items as a list; NATURAL, DYNAMIC, CINEMA
x
Colour Temp
=> Three items as a list; COOL, NORMAL, WARM
x
Contrast
=> Slider Bar. Changing value between 0 to 63.
x
Brightness
=> Slider Bar. Changing value between 0 to 63.
x
Sharpness
=> Slider Bar. Changing value between 0 to 16.
x
Colour
=> Slider Bar. Changing value between 0 to 99.
x
R
=> Slider Bar. Changing value between 0 to 100.
x
G
=> Slider Bar. Changing value between 0 to 100.
x
B
=> Slider Bar. Changing value between 0 to 100.
In this menu preset values for each Mode (Contrast, Brightness, Sharpness, Colour values for each ModeNATURAL, DYNAMIC, CINEMA) and for each Colour Temp. (R, G, B values for each Colour Temp- COOL,
NORMAL, WARM) are determined for each source.
16.2. SOUND1
x
Menu Subwoofer
=> If ON, Subwoofer option is available in TV set, and the item is visible
in sound menu, else Subwoofer is not available.
x
Subwoofer Level (dB) => This value is gain value of Subwoofer output in dB. -30...12
x
Subwoofer Corner Freq. (x10Hz) => Last low frequency value that is amplified. 5...40
x
Menu Dolby Prologic => No functionality now.
x
Menu Equalizer
=> If ON, visible in sound menu, else invisible.
x
Menu Lineout
=> No functionality now.
x
Menu Headphone
=> If ON, visible in sound menu, else invisible.
x
Menu Hyper Sound
=> If ON, visible in sound menu, else invisible.
x
Menu Wide Sound
=> If ON, visible in sound menu, else invisible.
x
Menu Dynamic Bass => If ON, visible in sound menu, else invisible.
x
Menu Virtual Dolby
=> If ON, visible in sound menu, else invisible.
x
Carrier Mute
=> If ON, in the absence of an FM carrier the output is muted, else not.
x
Virtual Dolby Text
=> Active if VIRTUAL DOLBY is ON. According to the selection; seen in
sound menu as 3D PANORAMA or VIRTUAL DOLBY.
16.3. SOUND 2
x
AVL
=> AVL is controlled from this menu by service user. ON/OFF
x
Menu AVL
=> If ON, AVL item is visible in sound menu, and AVL can be controlled from
sound menu by normal user, else AVL is invisible to normal user.
x
FM PRESCALE AVL ON
=> If AVL ON, set value in this item is used as prescale value
for the related standard. 0...127
x
NICAM PRESCALE AVL ON => If AVL ON, set value in this item is used as prescale value
for the related standard. 0...127
x
SCART PRESCALE AVL ON => If AVL ON, set value in this item is used as prescale value
for scart outputs. 0...127
x
SCART VOLUME AVL ON
=> If AVL ON, set value in this item is used as volume value for
scart1 and scart2. 0...127
x
FM PRESCALE AVL OFF
=> If AVL OFF, set value in this item is used as prescale value
for the related standard. 0...127
x
NICAM PRESCALE AVL OFF => If AVL OFF, set value in this item is used as prescale value
for the related standard. 0...127
x
SCART PRESCALE AVL OFF => If AVL OFF, set value in this item is used as prescale value
for scart outputs. 0...127
x
SCART VOLOUME AVL OFF => If AVL OFF, set value in this item is used as volume value for
scart1 and scart2. 0...127
16.4. Options
x
Screen Saver
x
FIRST APS
factory default settings.
=>
=> If ON, first APS menu is opened when the TV opened with the
38
x
APS VOLUME
=> After First APS function finishes, the volume of the TV is that value.
x
AGC
=> Tuner AGC value.
x
Factory Reset
=> OK to activate. When OK pressed on this item, factory defaults
loaded.
x
Enter Flash Mode
=>
TV Norm
x
BG
=> If ON, supported, else not supported
x
DK
=> If ON, supported, else not supported.
x
I
=> If ON, supported, else not supported.
x
L
=> If ON, supported, else not supported.
x
LP
=> If ON, supported, else not supported.
x
M
=> If ON, supported, else not supported.
Features
x
PIP/PAP
=> If ON, PIP/PAP available else not.
x
Blue Background
=> If ON, Blue Background is visible in Features Menu else not.
x
Menu Transparency
=> If ON, Menu Transparency is visible in Features Menu else not.
x
Menu Timeout
=> If ON, Menu Timeout is visible in Features Menu else not.
x
Backlight
=> If ON, Backlight is visible in Features Menu else not.
x
Single Tuner
=>
Teletext
x
Teletext Language
=> Teletext Language may be controlled from this menu by service
user.
x
Menu Teletext Language => If ON, Teletext Language item is visible in Features Menu, and
Teletext Language can be controlled from Features Menu by normal user, else Teletext Language is
invisible to normal user.
Source
x
TV
x
SC1
x
SC2
x
SC2 SVHS
x
SC3
x
SC3 SVHS
x
YPBPR
x
FAV
x
SVHS
x
HDMI
x
PC
This menu is related with the options of the chassis. These items may be ON or OFF. If ON, the source is
available in TV set, and the item is visible in source menu, else the source may be available but invisible to user.
17. IC DESCRIPTIONS (FOR DIGITAL)
STI5518
MAX232_SMD
74HCU04
TSH22
CS4334
AMIC A43L2616
MX29LV160T
24C32
STV0360
MAX809
TDCC2345TV39A
STV0700
17.1. STI5518
17.1.1. General Description
The STi5518 is a highly integrated single-chip decoder, designed for use in feature-rich mass-market set-top boxes. It
integrates a high-performance 32-bit CPU, a dedicated block for DVB/DirecTV transport demultiplexing and descrambling,
modules for MPEG-2 video and audio decoding with 3D-surround and MP3 support, advanced display and graphics
features, a digital video encoder and all of the system peripherals required in a typical low-cost interactive receiver.
39
To cover the needs of DVD-capable set-top boxes, STi5518 integration options include a CSS decryption block, a Dolby
Digital audio decoder and Macrovision copy protection.
An ATAPI interface is built-in, supporting the glueless connection of standard Hard Disk Drives. In this way, the STi5518
is ideal for set-top boxes featuring trick modes such as live TV recording, pausing and time-shifting.
The STi5518 is backward compatible with the popular STi5500 set-top box decoder, allowing easy migration from the
previous generation.
The high level of integration in a single PQFP-208 package makes the STi5518 ideally suited for low-cost, high-volume
set-top box applications.
17.2. MAX232_SMD
17.2.1. General Description
The MAX220–MAX249 family of line drivers/receivers is intended for all EIA/TIA-232E and V.28/V.24 communications
interfaces, particularly applications where ±12V is not available.
These parts are especially useful in battery-powered systems, since their low-power shutdown mode reduces power
dissipation to less than 5μW. The MAX225, MAX233, MAX235, and MAX245/MAX246/MAX247 use no external
components and are recommended for applications where printed circuit board space is critical.
17.2.2. Features
x
x
x
x
x
x
Operate from Single +5V Power Supply (+5V and +12V—MAX231/MAX239)
Low-Power Receive Mode in Shutdown (MAX223/MAX242)
Meet All EIA/TIA-232E and V.28 Specifications
Multiple Drivers and Receivers
3-State Driver and Receiver Outputs
Open-Line Detection (MAX243)
17.3. 74HCU04
17.3.1. General Description
The M54/74HCU04 is a high speed CMOS HEX INVERTER (SINGLE STAGE) fabricated in silicon gate C2MOS
technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption.
As the internal circuit is composed of a single stage inverter, it can be used in crystal oscillator.
All inputs are equipped with circuits against static discharge and transient excess voltage.
17.3.2. Pin Description
40
17.4. TSH22
17.4.1. General Description
The TSH22 is a dual bipolar operational amplifier offering a single supply operation from 3V to 30V with very good
performances: medium speed (25MHz), unity gain stability and low noise.
The TSH 22 is therefore an enhanced replacement of standard dual operational amplifiers.
17.4.2. Pin Connections
17.5. CS4334
17.5.1. General Description
The CS4334 family members are complete, stereo digital-to-analogue output systems including interpolation, 1-bit D/A
conversion and output analogue filtering in an 8-pin package. The CS4334/5/6/7/8/9 support all major audio data interface
formats and the individual devices differ only in the supported interface format.
The CS4334 family is based on delta-sigma modulation, where the modulator output controls the reference voltage input to
an ultra-linear analogue low-pass filter. This architecture allows for infinite adjustment of sample rate between 2 kHz and
100 kHz simply by changing the master clock frequency.
The CS4334 family contains on-chip digital de-emphasis, operates from a single +5V power supply, and requires minimal
support circuitry. These features are ideal for portable CD players and other portable playback systems.
17.5.2. Features
x
x
x
x
x
x
x
x
x
x
Complete Stereo DAC System: Interpolation, D/A, Output Analogue Filtering
24-Bit Conversion
96 dB Dynamic Range
Low Distortion
Low Clock Jitter Sensitivity
Single 5 V Power Supply
Filtered Line Level Outputs
On-Chip Digital De-emphasis
Soft Ramp to Quiescent Output Voltage
Functionally Compatible with CS4330/31/33
17.6. AMIC A43L2616
17.6.1. General Description
The A43L2616-PH is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 X 1,048,576
words by 16 bits, fabricated with AMIC’s high performance CMOS technology. Synchronous design allows
precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of
operating frequencies, programmable latencies allows the same device to be useful for a variety of high
bandwidth, high performance memory system applications.
17.6.2. Features
x
x
x
x
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks / Pulse RAS
MRS cycle with address key programs
41
x
x
x
x
x
x
x
All inputs are sampled at the positive going edge of the system clock
Clock Frequency: 166MHz @ CL=3
143MHz @ CL=3
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
54 Pin TSOP (II)
17.6.3. Pin Description
42
17.7. MX29LV160T
17.7.1. General Description
The MX29LV160T/B & MX29LV160AT/AB is a 16-megabit Flash memory organized as 2M bytes of 8 bits or 1M words
of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access
memory. The MX29LV160T/B & MX29LV160AT/AB is packaged in 44-pin SOP, 48-pin TSOP and 48-ball CSP. It is
designed to be reprogrammed and erased in system or in standard EPROM programmers.
The standard MX29LV160T/B & MX29LV160AT/AB offers access time as fast as 70ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention, the MX29LV160T/B &MX29LV160AT/AB has separate
chip enable (CE) and output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The
MX29LV160T/B & MX29LV160AT/AB uses a command register to manage this functionality. The command register
allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining
maximum EPROM compatibility.
MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is
designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide
processing and low internal electric fields for erase and program operations produces reliable cycling. The
MX29LV160T/B & MX29LV160AT/AB uses a 2.7V~3.6V VCC supply to perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is
proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.
17.7.2. Features
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Extended single - supply voltage range 2.7V to 3.6V
2,097,152 x 8/1,048,576 x 16 switchable
Single power supply operation
Fast access time: 70/90ns
Low power consumption
Command register architecture
Auto Erase (chip & sector) and Auto Program
Erase Suspend/Erase Resume
Status Reply
Ready/Busy pin (RY/BY)
Sector protection
CFI (Common Flash Interface) compliant (for MX29LV160AT/AB)
100,000 minimum erase/program cycles
Latch-up protected to 100mA from -1V to VCC+1V
Boot Sector Architecture
Low VCC write inhibit is equal to or less than 1.4V
Compatibility with JEDEC standard
17.7.3. Pin Description
43
17.8. 24C32
17.8.1. General Description
The AT24C32/64 provides 32,768/65,536 bits of serial electrically erasable and programmable read only
memory (EEPROM) organized as 4096/8192 words of 8 bits each. The device’s cascadable feature allows up to
8 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial
applications where low power and low voltage operation are essential. The AT24C32/64 is available in space
saving 8-pin JEDEC PDIP, 8-pin JEDEC SOIC, 8-pin EIAJ SOIC, and 8-pin TSSOP (AT24C64) packages and is
accessed via a 2-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V
(1.8V to 5.5V) versions.
17.8.2. Features
x
x
x
x
x
x
x
x
x
x
x
x
x
Low-Voltage and Standard-Voltage Operation
Low-Power Devices (ISB= 2 μA at 5.5V) Available
Internally Organized 4096 x 8, 8192 x 8
2-Wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Clock Rate
Write Protect Pin for Hardware Data Protection
32-Byte Page Write Mode (Partial Page Writes Allowed)
Self-Timed Write Cycle (10 ms max)
High Reliability
Automotive Grade and Extended Temperature Devices Available
8-Pin JEDEC PDIP, 8-Pin JEDEC SOIC, 8-Pin EIAJ SOIC, and 8-pin TSSOP Packages
17.8.3. Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge
clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be
wire-ORed with any number of other open-drain or open collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired or left
not connected for hardware compatibility with AT24C16. When the pins are hardwired, as many as eight 32K/64K devices
may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section).
When the pins are not hardwired, the default A2, A1, and A0 are zero.
WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write operations. When WP is tied
high to VCC, all write operations to the upper quadrant (8/16K bits) of memory are inhibited. If left unconnected, WP is
internally pulled down to GND.
44
17.9. STV0360
17.9.1. General Description
The STV0360 is a single-chip COFDM (coded orthogonal frequency division multiplex) demodulator that performs IF to
MPEG-2 block processing of OFDM carriers. It is intended for digital terrestrial receivers for compressed video, sound and
data services.
The chip implements all the functions from the tuner IF output up to the MPEG-2 transport stream input.
The STV0360 is fully compliant with the DVB-T specification (ETS 300 744) and handles 2K/8K modes.
The STV0360 integrates an A/D converter that delivers the required performance to handle up to 64 QAM carriers in a
direct IF sampling architecture, thus eliminating the need for an external down-converter. The chip also integrates an
internal programmable gain amplifier (PGA) to compensate for SAW filter level degradation, thus eliminating the need for
external IF amplifiers. A 10-bit ADC, intended for RF signal strength indication, eliminates the need for external
components when using wide-band AGC tuners.
In addition to all the demodulation and FEC (forward error correction) functions required for recovery of the QAM
modulated bit streams with very low BER, it also includes several features that give easy and immediate access to various
quality monitoring parameters or lock status. The STV0360 also provides output such as delayed AGC or noise-free I²C bus
dedicated to tuner control, which facilitates the design of high quality integrated receiver decoders.
The STV0360 outputs error-corrected MPEG-2 transport streams and complies with the DVB common interface format,
with programmable data clock frequency. It also interfaces seamlessly with the packet de-multiplexers embedded in the
STi55xx Omega family of single-chip decoders.
17.9.2. Features
x
x
x
x
x
x
x
x
Decodes DVB-T (ETS300744) and NorDig II
TPS decoded or automatic FEC mode detection
Embeds PGA for IF level adaptation
Generates system clock on-chip from 20 to 27-MHz crystal quartz
Four I²C addresses available
Low power consumption (< 500 mW)
Small footprint: TQFP64 (10 X 10 mm)
1.8 V operation, CMOS technology
17.9.3. Pin Description
45
46
17.10.
MAX809
17.10.1. General Description
The MAX803/MAX809/MAX810 are microprocessor (μP) supervisory circuits used to monitor the power supplies in μP
and digital systems. They provide excellent circuit reliability and low cost by eliminating external components and
adjustments when used with +5V, +3.3V,+3.0V, or +2.5V powered circuits. These circuits perform a single function: they
assert a reset signal whenever the VCC supply voltage declines below a preset threshold, keeping it asserted for at least
140ms after VCC has risen above the reset threshold. Reset thresholds suitable for operation with a variety of supply
voltages are available. The MAX803 has an open-drain output stage, while the MAX809/MAX810 have push-pull outputs.
The MAX803’s open-drain RESET output requires a pull-up resistor that can be connected to a voltage higher than VCC.
The MAX803/MAX809 have an active-low RESET output, while the MAX810 has an active-high RESET output. The
reset comparator is designed to ignore fast transients on VCC, and the outputs are guaranteed to be in the correct logic state
for VCC down to 1V. Low supply current makes the MAX803/MAX809/MAX810 ideal for use in portable equipment. The
MAX803 is available in a 3-pin SC70 package, and the MAX809/MAX810 are available in 3-pin SC70 or SOT23
packages.
17.10.2. Features
x
x
x
x
x
x
x
x
x
1 Precision M onitorin g of +2.5V, +3V,.3V,
+3 and +5V Power-Su ppl y Voltages
Fully Specifie d Over Tem peratu re
Available in T hree Output Config uratio ns
Open-Drain RESET Output (MAX803)
Pus h-Pull RESET Output (MAX809)
Pus h-Pull RESET Output (MAX810)
140ms min Pow er-On Reset Pulse Wid th
12μA Supply Current
Guarantee d Reset Valid to VCC= +1V
Powe r Suppl y Transi ent Immunity
No External Comp one nts
3-Pin SC7 0 and SOT23 Pa ckage s
47
17.10.3. Pin Description
17.11.
TDCC2345TV39A
17.11.1. General Description
x
x
x
x
x
x
x
Receiving System : Designed to cover all bands in VHF and UHF including digital terrestrial channels
system.
Receiving Channel : 47 MHz ~ 862 MHz
Intermediate Frequency : Digital (center) 36.125 MHz
Input Impedance : 75Ÿ, Unbalanced.
IF Output Impedance : 75Ÿ, Balanced.
Loop through RF output Impedance : 75Ÿ, Unbalanced.
Band Change-Over System : PLL system
x
x
Tuning System : PLL system
Pin-out for the port to control the switchable saw
17.11.2. Pin Description
48
for DVB-T
17.12.
STV0700
17.12.1. General description
The STV0700 controller contributes to offer an optimized, homogeneous and complete solution for digital TV receiver and
Set Top Box manufacturers that want to quickly implement the Common Interface. The STV0700 includes the necessary
I/Os to interface to the MPEG Transport stream generated by the receiver demodulator and daisy chain it through two
independent Common Interface modules and back to the demultiplexer. The STV0700 interfaces with major digital TV
receiver microprocessors. An I2C bus is used for initialization and module selection, while a Universal Control Signal
Generator (UCSG) maps CPU control bus into Command Interface control signals. To minimize pin count, host address and
data buses transit through external buffers that are driven by the STV0700. The STV0700 includes a memory mode that
allows the use any of the Common Interface slots to read and write an 8-bit PC Card Memory card. This feature gives the
receiver memory extension capability for software upgrade or better performance.
17.12.2. Features
x
x
x
x
x
x
x
x
x
x
Module Interface
2 independent module capability
Common Interface Standard compliant
o DVB_CI (CENELEC EN-50221)
o NRSS-B (SCTE IS-679 Part B)
o DAVIC v1.2 (CA0 interface)
Memory PCMCIA compliance (R2)
o 8-bit data access
o 26-bit address Memory Card
Attribute Memory access (CIS, Tupple)
High speed capability
o Up to 20Mbits/s on Command Interface
o Up to 100Mbits/s on Transport Stream
Polling and Interrupt modes
Hot Insertion (Automatic and Reset VCC handling)
3.3V (5V tolerant) I/O buffers
IEEE 1149.1 Boundary Scan Compliant
Test Access Port
x
Host microprocessor Interface
Universal Control Signal Generator(UCSG)
o PC Card control signals generation
o Supports PowerPC, ARM, ST20,68xxx, TMS,
LSI 64008, TC81220F & IDTR3041
x I2C port
o STV0700 Set-up
o Slot selection
o Cascade mode management (up to 4STV0700)
x Chip Select bank and Interrupt facilities
x 3.3V (5V tolerant) I/O buffers
Digital Video Stream Interface
MPEG II Transport Stream compliant
(serial/parallel configurable interface)
x
x
x
x
17.12.3. Pin Description
49
3.3V (5V tolerant) I/O buffer for direct interface
with FEC and DEMUX ICs
50
51
52
18.
APPENDIX A
18.1. EXPLODED VIEW
MAIN BOARD ASSEMBLY
43
V4
AV BOARD ASSEMBLY
44
V1
V4
V4
48
V4
V1
V2
V4
V1
V1
39
V2
V1
V2
V3
V1
V2
V3
V1
V2
V1
V3
V3
V5
23
V2
35
V2
V0
V1
V1
V1
V3
V8
V1
V2
V6
34
33
V3
V7
V5
V2
V9
V1
LED BOARD
ASSEMBLY
V4
PANEL CONNECTION SCREWS
SM012
ASSEMBLY DIAGRAM (EXPLODED VIEW)
53
19.
APPENDIX B
19.1. BLOCK DIAGRAM
MAIN BOARD
AUDIO / VIDEO / GRAPHICS IN / OUT
AUDIO
DECODING
MSP3411G
MICRONAS
MAIN_L, MAIN_R
AUDIO
AMPLIFIER
D-CLASS
IDTV, SVHS,MMC(RGB), PC IN
SVP-EX59
LVDS OUT
8-BIT YUV
VPC3230D
VIDEO PROCESSOR
PIP PICTURE
MICRONAS
HDMI DECODER
SIL9993
SDA5550
MCU
MICRONAS
24-BIT RGB
PSU
SM012
AUDIO AMP BOARD
BLOCK DIAGRAM
54
19.1. SCHEMATIC DIAGRAMS
SM012
POWER BOARD - SHEET 1
55
SM012
POWER BOARD - SHEET 2
56
SM012
POWER BOARD - SHEET 3
57
SM012
POWER BOARD - SHEET 4
58
SM012
POWER BOARD - SHEET 5
59
8V_FILTERED
QSS_TUN2
L1003
C1206
C1205
50V
100n
C1200
50V
100n
C1199
50V
100n
100n
50V
50V
100n
C1198
5
VCC_5V
9
ADR_CL
10
DVSUP
50V
C1081
50V
C1086
11
C1079
1n5
50V
12
12S_DA_IN2
13
16
1k
R2009
1k
R2006
1k
R2008
1k
C1152
49
AVSUP
1n5
50
ANA_ I N 1 +
10u
51
ANA_ I N -
C1144
52
ANA_ I N 2 +
RESETQ
AHVSS
L1021
R1108
AUDIO_R
1k
1n
C1171
S2011
1k
1n
AUDIO_L
S2008
SC3_AUDIO_R_IN
L1025
R1111
C1164
S2007
IDTV/MMC/DVD_R_IN
1k
1n
C1147
AUDIO_R2
L1024
R1110
C1153
330n
AV_AUDIO_L_IN
1k
C1170
330n
L1023
R1107
C1158
L1026
R1109
C1175
S2005
IDTV/MMC/DVD_L_IN
1k
1n
330n
S2006
SC3_AUDIO_L_IN
33
S C 2_OUT_R
S C 2_OUT_L
VREF 1
S C 1_OUT_R
C 1_OUT_L
CA P L_A
AHVSUP
CA P L_M
26
27
28
29
S
30
31
32
DACM _S
24
25
DACM _SUB
23
DACM_C
22
C1145
C1149
S2010
C295
50V
100n
16V
C300
10u
A
1
50V
1n5
L1029
R1103
C1165
22u
L1028
1n
L1027
4R7
C1136
VCC5V_FILTERED
22u
100u
C1172
IC209
C1180
100u
AUDIO_L_OUT
100u
C1178
R1129
5
L2
R2
24
6
L3
R3
23
R2012
PC_AUDIO_L_IN
1k
7
NC1
3
2n2
C1168
INB+
C1181
1u
R1112
47k
R1102
10k
R1101
8V_FILTERED
C1159
5
47k
INA+
TDA1308
VSS
4
10k
R1113
C2023
C247
R2204
100R
L216
L2018
22u
50V
22u
L2019
C254
50V
22u
C2037
L5
R5
C2036
R2023
1k
19
DAC_AOR
ROUT4
18
12
ROUT1
LOUT4
17
13
LOUT2
ROUT3
16
C1127
14
ROUT2
LOUT3
22u
50V
22u
50V
15
C1139
C251
R1091
100R
AUDIO_R_LINE_OUT
R1097
100R
AUDIO_L_LINE_OUT
MAIN BOARD - TUNER/IF/AUDIO CIRCUIT
60
4k7
R102
Q100
BC848B
4k7
L219
L218
L0UT1
R101
S107
MUTE_AMP
PC_AUDIO_L_IN
330n
11
4k7
R100
C255
PC_AUDIO_R_IN
YPBPR_AUDIO_R_IN
S108
MUTE_AMP
S2010 & R2208 are for mute option
Mute is active high
4k7
1k
C2024
BLM21B201S
C249
AUDIO_R2
R2022
330n
R103
C2034
22u
L2002
1n
50V
1u
16V
C1186
20
C2022
BLM21B201S
R2203
100R
R1115
1n
C2019
C2021
AUDIO_L2
10k
1k
R1117
R1116
C1188
L2001
1n
AUDIO_R
10n
50V
16V
100n
R4
330n
BLM21B201S
R2016
100R
C1187
VCC5V_FILTERED
L4
10
1n
L1031
BA782
D1002
D1006
AUDIO_L
100R
9
C2020
1k
R2015
100R
Q1013
IF
21
1n
50V
16V
100n
BC848B
47k
R1118
NC3
330n
DAC_AOL
C1189
S1005
Q1014
NC2
C2033
1k
R2014
BC848B
8
C2018
C257
SW01=L BG,DK,I,L
YPBPR_AUDIO_L_IN
C2017
BZT55C5V1
50V
D1004
4n7
10k
R1119
10k
R1120
SAW_SW1
R2013
50V
4n7
4
1n
OUT1
22
INB-
TEA6420
5
BZT55C5V1
Z1002
IN1
NC4
C1173
6
C1179
220p
STBY_3V3
D1005
1
OUT2
12 3
IN2
JK200
JACK-AK16
IF
GND
2
K9356M
SW01=H L'
50V
1u
24
1n
50V
SIF2
PC_AUDIO_R_IN
1k
C1001
VIF1
R2021
330n
1n
50V
1
SC3_AUDIO_R_IN
C2032
C2031
C2016
330n
16V
4
S2003
330n
330n
SIF1 23
2
IDTV/MMC/DVD_R_IN
1k
C1000
VIF2
R2020
50V
1n
2
5
IC201
BA591
S2009
C2029
INA-
HP_L
C2030
C2014
C2013
1
SC2_AUDIO_R_IN
1k
50V
1k
OUTB
OUTA
22u
R2011
S2001
SC3_AUDIO_L_IN
7
220p
50V
4k7
R1100
R2019
330n
C1132
IDTV/MMC/DVD_L_IN
SAW_SW1
C2027
VDD
SC2_AUDIO_L_OUT
C2028
50V
25
L1017
BC848B
Q1011
22u
R1
C2015
OUT2
OUT1
IN1
L1
1n
1
4
C2012
1n
GND
26
330n
S2002
50V
1n
IN2
ADDR
C1124
47R
C2011
VS
22u
1k
BC848B
Q1009
47p
50V
1n
50V
10n
22k
1k
3
R1096
1k
SCL
C2026
S2000
8
100n
SC2_AUDIO_R_OUT
22
SC2_AUDIO_L_IN
27
50V
1n
OP2
100n
25V
R1027
6k8
OP1
R2201
50V
1n5
22k
R2010
VCC_5V
SCL
8V_FILTERED
100n
16V
21
CAPACITANCE
22u
50V
C2010
C1162
R1092
1
C1185
2n2
50V
4k7
HP_R
C1151
SDA
R2018
100R
K
2
C1183
1n
C1133
1n
50V
16V
100u
100R
R1098
50V
1u
C1150
50V
470p
K
2
C1182
2n2
50V
R2017
100R
28
47p
C2025
2
VCC5V_FILTERED
50V
1n
AFC
SDA
C2009
50V
1n
FMPLL
C1043
150R
C1041
GND
D1000
C1184
2n2
50V
C1134
10u
C1126
50V
1n
C1121
50V
1n
C1119
SUBW
50V
1n
C1106
MAIN_L
C1154
50V
1n
R2202
220R
C1097
8V_FILTERED
4R7
R1130
HEADPHONE
10u
100R
R1093
100R
R1089
MAIN_R
4
VCC_8V
C1118
1n
C1116
1n
50V
1n
C1114
1n
50V
50V
1n
C1117
1
10u
16V
20
AUDIO_L2
100n
3u3
100R
R1095
75R
R1044
47k
R2007
50V
C1122
1p8
C1125
56p
330n
AV_AUDIO_R_IN
1k
1n
C1176
C1163
50V
100u
P L1001
22n
50V
C1054
R1039
3
3
SM012
X1002
34
C1196
100n
C1047
VP
DEEM
K3953M
Z1001
11
53
35
AGNDC
IDTV/MMC/DVD_R_IN
3
3
2
1n
50V
54
SC4_IN_L
NC3
MUTE_AMP
C2201
R1041
C1049
19
390p
50V
S1007
S1006
L1000
1u
IF1
VPLL
10n
50V
C1027
3
C1004
AFD
R1023
4
5k6
9
10
T EST EN
NC2
15
2
BC848B
Q1002
C1040
10n
50V
C1026
2k2
IF2
XT AL _ I N
14
L1020
R1106
330n
330n
1
50V
47u
R1024
VST
50V
36
2k2
220n
16V
5
33V_FILTERED
R1001
18.432MHz
SC4_IN_R
R1035
18
470n
63V
C1031
C1009
50V
10u
8
AGND
TDA9885T
VCC_5V
R1012
NC/ADC
55
NC1
IDTV/MMC/DVD_L_IN
1
47R
R1026
17
56
37
SC1_AUDIO_L_IN
1k
1n
38
ASG3
4
33p
25V
C1008
10u
7
C1003
VS
DGND
C1030
6
C1012
6
33p
25V
C1015
NC
CVBS
XTAL _ O UT
SC3_IN_L
DVSS
L1022
R1105
C1174
C1177
IC2000
7
5
100n
CTF5543_HOR
SDA
AUD
330n
C1157
C1140
AUDIO_R_OUT
8
4
C1138
1n
100R
R1094
VAGC 16
470n 63V
SCL
57
39
470p
100R
R1090
TOP
4MHz
TP
40
270p
C2202
R1052
560R
9
3
22p
25V
C1039
AUD_CL_OUT
ASG2
SC3_IN_R
5
PL1003
15
SC1_AUDIO_R_IN
1k
HP_R
R1040
REF
R1034
SDA
10k
33p
25V
10
X1001
L1019
R1104
C1148
MSP3452G
IC208
C1087
470p
1kV
TUN1_CVBS
C1038
58
41
22n
50V
100R
S1000
AS
TAGC 14
33p
25V
2
SCL
NC4
42
SC2_IN_L
2
VCC_5V
R1009
100R
C1023
TU
11
C1022
SCL
1
4k7
R104
SC2_IN_R
ADR_WS
ESD
R1030
SDA
AGC
R1005
100R
12k
2k2
1N4148
13
IC205
NC
59
ADR_DA
8
DACM _L
S1010
47u
50V
C1010
TU1001
SIOMAD
60
7
C1112
12
NC5
61
43
HP_L
L1001
R1010
100R
R1114
D_ CT R_ I/O_ 1
62
C_ CT R_ I/O_0
44
ASG1
21
100n
16V
63
SC1_IN_L
12S_DA_IN1
75R
10k
ADR_ SEL
12S_DA_OUT
6
10p
25V
R1051
R1122
10k
64
5
I2S_DA_IN1
RESETQ_MSP
Q1005
BC848B
10u
C1156
22u
C1078
10u
50V
C1052
BC848B
4k7
R1121
Q1016
R1049
SAW_SW2
C1191
47k
NC6
I2S_DA_OUT
QSS_TUN1
R1123
STANDBYQ
45
IC207
2k4
R1050
15k
R1048
BA591
D1007
D1003
BA782
L1032
Q1015
46
SC1_IN_R
C1055
BC848B
VREFTOP
1N4148
4
VCC5V_FILTERED
C1193
C2008
C1169
L1008
S1003
OUT1
12S_CL
DACM _R
Z1003
IN1
1
3
20
OUT2
47
12S_WS
C1080
100u
K9356M
100n
16V
C1194
1k
10k
R1125
16V
1u
50V
10n
IF1
R1126
R1124
C1192
VCC5V_FILTERED
IN2
48
C1166
470R
470R
R1067
3
2
C2007
22u
100n
N.C
C1167
C1197
50V
10u
IF1
IC200
S1009
100R
QSS_TUN2
QSS_TUN1
VCC5V_FILTERED
4R7
560p
330n
2
K
R1127
24
GND
VCC_5V
22u
AVSS
VREF 2
SIF2
22u
SC1_AUDIO_R_OUT
Q2004
BC848B
L1018
MONO_IN
19
VIF1
C1120
1p8
39p
C1085
Q1007
1
A
1
R2005
100R
C1137
4
BC858B
VCC_5V
4
AUDIO_R_OUT
Q2003
BC848B
SC3_AUDIO_R_OUT
I2S_WS
R1069
OUT1
IN1
R2004
100R
50V
12C_DA
DACA_R
1
C1204
23
SF_63962
Z1000
11
AUDIO_L_OUT
50V
12C_CL
DACA_L
SIF1
C2006
56p
2
18
VIF2
C1128
56p
C1123
56p
47R
C1048
1k
R1068
2
5
22u
SC3_AUDIO_L_OUT
1
17
OUT2
50V
1n
IC206
1n
50V
GND
I2S_CL
BZT55C3V6
IN2
33V_FILTERED
4R7
SAW_SW2
3
2
100R
VCC5V_FILTERED
22k
R1028
22
390p
50V
C1005
50V
39p
C1084
50V
10n
21
C1203
50V
100n
OP2
R2200
50V
1n5
C1035
R1071
SDA
R1128
50V
10u
OP1
100R
VCC5V_FILTERED
R1022
AFC
R1070
SCL
20
100n
25V
3
L1002
FMPLL
16V
100n
C1195
6k8
33V_FILTERED
10
1u
IF1
VP
10n
50V
C1025
2k2
S1008
IF2
5k6
330R
R1031
9
4
C1006
50V
10u
R1000
VST
DEEM
10n
50V
C1024
22k
C1011
25V
100n
C1002
50V
10u
5
R1038
19
100n
25V
7
8
VPLL
470n
63V
C1029
R1011
NC/ADC
AFD
C2200
10u
16V
6
C1037
C2005
Q2001
BC848B
C1130
C1113
100n
25V
R1078
100R
18
33p
25V
AGND
C1045
DGND
TDA9885T
6
VCC_5V
VS
BC848B
Q1003
50V
47u
47R
C1042
7
C1028
NC
R1025
17
100n
50V
50V
100n
CVBS
33p
25V
5
C1013
CTF5543_HOR
SDA
AUD
220R
C1202
8
4
C1007
SCL
R1043
R1042
470n
63V
VCCA_3V3
16
C1201
VAGC
VCC_33V
TOP
FB_CONTROL
C1036
9
3
R1037
4MHz
15
75R
REF
47k
22p
25V
10k
SDA
R1032
X1000
VCC_5V
10
C1021
R1008
100R
2
C1034
VCC_5V
AS
22u
SC1_AUDIO_L_OUT
TUN2_CVBS
100R
33p
25V
C1020
SDA
TU
50V
R1029
P L1002
14
2
TAGC
Q2002
BC848B
3
R1004
100R
1
33p
25V
SCL
AGC
C2004
470p
50V
HEADPHONE
L1030
SCL
13
12k
11
NC
22u
L2000
R1036
SIOMAD
IC204
12
TU1000
1N4148
47u
50V
R1013
100R
N. C
C1014
26R_100MHZ_1.5A
D1001
A
1
10
12
5
7
9
11
13
16
15
1
3
L2114
L2125
L2006
6
7
L2004
9
10
11
C270
BZT55C10
2
1
K D2101 A
C301
50V
150p
50V
1n
12
C258
15
L206
SVHSfromSC2_C
S205
C293
100n
150p
16V
150p
C248
16
17
18
19
BZT55C10
2
1
K D2500 A
150p
C278
50V
C253
SC1_AUDIO_R_IN
150p
SC1_AUDIO_R_OUT
SC1_AUDIO_L_OUT
BZT55C10
BZT55C10
150p
50V
A D213 K
1
2
20
SC2_V_IN
C286
1
2
A D224 K
SC1_AUDIO_L_IN
SC1_B
75R
R276
2
1
K D218 A
2
1
K D211 A
21
C269
SC2_FB
R275
SC2_V_OUT
K D2102 A
2
1
330R
R254
C267
330R
R252
50V
1n
L210
L205
R287
1n
BZT55C10
PIN8_SC1
SCSDA
SC1_G
75R
D202
K
2
1
2
A D204 K
50V
4n7
K
2
SCSCL
SC1_R
SC1_FB
SC1_V_OUT
SC1_V_IN
SC2_R
S204
VCC_5V
NC1
2
NC2
3
NC3
4
VSS
VCC
8
VCLK
7
ST24LC21
SCL
6
SDA
5
VCC_5V
1
S644
S651
6
5
4
3
C_SELECTED
Q206
BC848C
2
100n
16V
R269
47k
S645
MMC_G
MMC_R
MMC_B
S633
4k7
R271
C2050
CHROMA_SW
IC215
SDA2
S213
R274
1k
1n
50V
C272
SC2_G
2
1
K D208 A
SDA_PANEL
SCL2
SCL_PANEL
S652
VCCA_3V3
SEL
STBY_3V3
8
7
RGB_SW2
6
P2
P6 11
RGB_SW1
7
P3
P5 10
RGB_SW3
6
gnd
8P VSS
4
3
75R
R208
2
75R
R209
1
75R
R210
SM012
VGA_BIN
VGA_RIN
VGA_GIN
100n
OE 13
74HC595D
5Q 5
STOP 12
8
VCC
6Q 6
SHCP 11
7
VCLK
5Y 10
7Q 7
MR 10
VGA_VSIN
R214
22R
22R
R238
63 Y
4A
9
7
4Y
8
VCCA_3V3
NC1 1
NC2 2
ST24LC21
DDC_CLK_PC
100R
R218
6
SCL
DDC_DATA_PC
100R
R219
5
SDA
NC3 3
VSS 4
8
GND
Q7OUT 9
PC_STBY
Q207
BC848C
GND
Q208
BC848C
PGAGND
PL200
PORT EXPANDER
100n
C281
4Q 4
R279
10k
VGA_HSIN
VGA_VSIN
DDC_5V
VCC_5V
100n
16V
C302
IC212
C2053
DSERIAL 14
100n
3Q 3
R280
150k
100n
Q0 15
5A 11
VGA_VSIN
53 A
4
PANEL_VCC_ON/OFF
D201
74LVC14A
SW_ENABLE
9
D200
1N4148
6Y 12
42 Y
VGA_HSIN
5
32 A
2Q 2
R283
10k
9
LG_1/IRQPDP
R213
22R
VCC 16
R282
10k
P7 12
6A 13
1Q 1
R284
47k
P1
DDC_5V
5
DISP_EN/PDWN
10
PGAGND
PCF8574
4k7
R259
INT 13
R258
4k7
P0
R257
4k7
11
4
CHROMA_SW
21 Y
DDC_DATA_PC
12
R217
10k
13
1N4148
R216
10k
SCL2
VCC 14
VCCA_3V3
330R
R256
1A
100n
16V
SCL 14
1
C289
A2
R215
22R
14
BZT55C12
3
IC211
15
VCCA_3V3
A D2502K
1
2
330R
R255
BZT55C12
SDA 15
A D2501K
1
2
A1
DDC_CLK_PC
S649
R248
4k7
R246
4k7
SDA2
2
STBY_3V3
VDD 16
S223
A0
R211
2k
STBY_3V3
1
R212
2k
100n
16V
C2052
C2051
gnd
VCC_5V
R281
10k
IC213
gnd
S637
C290
STBY_5V
IC214
VCCA_3V3
R265
4k7
R290
C2049
C296
S634
S650
TV_LINK
75R
R289
75R
DIMMING SELECTION
DVD_12V_SENSE
220n
16V
SVHSfromSC2_C
EXTERNAL INPUT
R277
4k7
K
2D207
21
L208
2
1
K D220 A
D206
MMC/DVD
VIDEO INPUTS
Q205
BC848C
MMC_CVBS
220n
16V
AV_AUDIO_L_IN
L201
BZT55C5V1 D2100
I2C BUFFER FOR PANEL
Q204
C246
BC848C
R268
47k
1n
C271
AV_AUDIO_R_IN
R270
100R
1
CIN
PL1
L202
R273
10k
C245
6
8
20
19
A
1
R266
18k
R267
10k
CIN
C262
7
PIN8_SC2
R288
S635
SVHS_Y_IN
220n
R232
75R
1
A
A
1
75R
42
18
A
1
2
K
1
A
D219
N.C
150p
50V
C261
N.C
CHROMA SWITCH
4
1
2
A D216 K
40
17
V8
5
4n7 C266
D203
2
K
K
2
D205
N.C
A
1
D210
S220BZT55C10
R286
75R
2
K
D209
IDTV/MMC/DVD_CVBS
AV1_V_IN
1
2
A D217 K
BZT55C10
2
1
K D223 A
75R
S221
BZT55C10
BZT55C5V1
3
SC3_AUDIO_R_IN
2
14
75R
C263
39p
BZT55C10
2
1
K D2103 A
SC2_AUDIO_L_IN
8
8
150p
C250
1
2
A D214 K
1
SC2_AUDIO_L_OUT
150p
C277
L214
14
3
SC3_V_OUT
S212
R253
330R
1n
50V
13
6
MMC_CVBS
2
330R
R2025
38
BZT55C10
36
41
50V
4n7
34
39
PL205
32
37
2
1
K D222 A
4
1
R2003
1k
A D215 K
1
2
330R
R2024
BZT55C10
K D2002 A
2
1
L2005
35
SC1_V_OUT
220n
16V
L209
C264
S647
28
30
26
TXOUT0-
S646
TXOUT0+
22
TXOUT1-
24
20
TXOUT1+
K
2
S636
A
1
L2003
S641
29
27
25
23
21
19
15
13
17
18
12
16
33
30
R261
PL201
SC3_AUDIO_R_OUT
SC3_AUDIO_L_OUT
SC3_AUDIO_L_IN
PIN8_SC3
SVHSfromSC2_C
SC3_V_OUT
VCCA_3V3
SC3_V_IN
R250
4k7
SDA_PANEL
SCL_PANEL
R251
4k7
S638
S639
S648
S109
6
TXOUT2-
28
31
1
A
39p
C276
R2002
75R
R231
75R
39p
50V
C268
TUN2_CVBS
220n
16V
29
R285
75R
INPUT7 11
SC2_AUDIO_R_IN
4n7
C2045
L204
Q2000
BC848B
C275
10 INPUT6
R202
75R
2
GND1 12
C291
SC3_V_IN
LVDS OUTPUT
R1045
1k
R2001
100R
26
A
1
VCC
220n
16V
C273
C299
50V
22u
C283
16V
100u
9
27
R260
75R
L200
VCC_8V
R1046
75R
BC848B
V8
10k
R225
BZT55C10
C2042
1n
L2008
4n7
50V
L207
2
K
OUTPUT1 13
SELECTABLE VIDEO OUT
FOR SCART 2
50V
1n
C2040
L213
1
A
INPUT5
220n
16V
4n7
C2044
L2007
25
24
D212
8
39p
N.C
50V
C297
R201
75R
22
SC2_V_OUT
1k
R242
Q1004
R1033
100R
R249
SC2_B
23
50V
150p
C252
10k
R224
CONNECT C288
330R
L203
C284
2
1
K D2104A
PARITY
S200
VCC_8V
SVHS_Y_IN
R237
75R
14
Q202
BC848B
10k
R223
TXOUT2+
OUTPUT2 14
8
PROG
10
7
TXCLKOUT-
OUTPUT3 15
TXCLKOUT+
INPUT4
4
6
220n
16V
N.C
S201
R230
100R
TXOUT3-
TEA6415C
2
OUTPUT4 16
V8
INPUT3
TXOUT3+
N.C
5
220n
16V
C279
V8
39p
50V
N.C
39p
50V
R205
75R
AV1_V_IN
C280
R200
75R
C259
C265
K
2
10k
R222
TUN1_CVBS
GOES TO VPC3230
FOR PIP PICTURE
D2001
1k
R241
150p
OUTPUT5 17
BZT55C10
2
1
K D2105 A
BZT55C10
BZT55C10
VxtoVPC
BZT55C10
K D2004A
2
1
A D2000K
1
2
C2039
CLOCK
R227
100R
K D2003 A
2
1
50V
150p
C2038
47p
25V
C287
SCL
4
PANEL_VCC
S640
R240
75R
10k
R221
BZT55C10
VCC_12V
11
OUTPUT6 18
A D221 K
1
2
PL203
Q203
BC848B
9
39p
50V
INPUT2
220n
16V
R207
100R
R226
100R
VCCA_3V3
SC2_AUDIO_R_OUT
PDP_GO/BL_ON_OFFCPU_GO
7
3
N.C
1k
R239
10k
R220
C260
CVBS_SVP
S643
GND2 19
DISP_EN/PDWN
5
DATA
V8
2
MAIN PICTURE
TO SVP
3
SDA
47p
25V
R206
100R
C303
39p
50V
R235
75R
220n
16V
S642
INPUT8 20
220n
16V
SC2_V_IN
R204
75R
C292
INPUT1
Q200
BC848B
1
1
N.C
R203
75R
C285
C282
PL103
C274
SC1_V_IN
S113
IC210
VCCA_3V3
S111
5V
S112
LG_1/IRQPDP
PANEL_VCC
VCC_12V
VCCA_3V3
100n
16V
C294
10u
IDTV/MMC/DVD_CVBS
V8
75R
R264
V8
4R7
R229
C298
VCC_8V
39p
C304
N.C
VIDEO SWITCH TEA6415C
D-SUB 15 PC INPUT & DDC CIRDUIT
PC STAND-BY
MAIN BOARD - IN/OUT CIRCUITS
61
3
NC3
NC23 31
4
NC4
NC22 30
5
NC5
L313
22R
R317
22R
R316
O 15
SC2_R
3C
N 14
4D
M 13
6F
K 11
SC1_B
7G
J 10
SC2_B
8H
I
L314
50V
68n
C321
47
46
45
C3
GNDC
VSUPC
49
48
C2
50
51
GNDSY
C1
52
VSUPSY
C0
53
54
AVO
INTLC
58
FPDAT
55
59
VSTBY
FSY/HC
60
57
61
NC2
CLK5
56
62
XTAL1
VS
63
XTAL2
MSY/HS
64
68 ISGND
Y3 37
C361
7
R3
6
R4
5
DIN[3]
4
VSUPY 36
C344
70 VOUT
GNDY 35
100n
16V
1n
C322
680n
75R
R307
74 VIN3
75R
75 VIN4
GNDLLC 30
VSUPLLC 29
10u
50V
47n
25V
C316
C305
R3
6
R4
5
L315
VCCD2_3V3
R321
22R
CLK_2EX
50V
330p
C311
N.C
50V
330p
C312
N.C
2B
O 15
3C
N 14
VCC_5V
S309
S314
4D
5E
RCA_Y
M 13
PI5V330_SOIC
6F
K 11
7G
J 10
8H
I
FFRE
FFOE
CLK20
22
24
R2029
10k
C347
25V
47n
50V
1n5
17
23
VGAV
16
FFWE
TEST
15
FFRSTW
RESQ
14
20
SDA
13
21
SCL
12
YCOEQ
GNDCAP
11
FFIE
GNDD
10
19
VSUPD
9
18
NC1
VSUPCAP
8
R2/CR2IN
ASGF1
7
G2/Y2IN
6
B2/CB2IN
MMC_G
330p
50V
N.C
R310
75R
220n
16V
100R
R320
100R
R319
100R
R318
220n
16V
N.C
RGB_SW1
N.C
R325
1k
1A
R 16
SC1_R
2B
O 15
SC2_R
3C
N 14
4D
M 13
C335
C338
16V
100n
16V
220n
C336
C339
100n
16V
IC317
50V
1n5
S310
PI5V330_SOIC
VCC_5V
SC1_FB
SC2_FB
L 12
SC1_G
5E
SC2_G
6F
K 11
7G
J 10
8H
I
SC1_B
SC2_B
S311
C325
220n
16V
R311
75R
25V
560p
C342
S340
C324
C337
RX1_RST#
330p
50V
R309
75R
C309
MMC_B
N.C
C334
SCL3
C329
50V
390p
SDA3
D106
BAV99
50V
270p
RGB_GIN
C326
9
S312
RGB_RIN
220n
16V
S308
VGA_GIN
5
16V
220n
L312
bu caplerin yerine tek 100nf takabilirsin.
BLM21B201S
N.C
RGB_R_VPC
MMC_R
L 12
4
C328
C308
R 16
R1/CR1IN
16V
220n
C310
C353
1A
100n
R326
1k
G1/Y1IN
C327
RGB_G_VPC
MMC RGB INPUTS
IC318
S301
330p
50V
75R
R333
D104
BAV99
16V
220n
RGB_B_VPC
50V
330p
C313
D102
BAV99
GNDPA 25
VCCD2_3V3
VCC_5V
75R
R332
C357
220p
220p
50V
RCA_PR
C365
3
C364
SCART RGB
C363
RCA_PB
75R
R331
220p
C356
50V
123
123
220n
C358
50V
Pr
123
A
A
Pb
30032234
A
Y
30032233
JK302
JK301
JK300
1P_RED_FAVWHITE_FAV WHITE_FAV
220n
R313
1k
220n
RCA_Y
AUDIO_L_LINE_OUT
SUBW
2
S316
B1/CB1IN
R312
4k
80 AISGND
FB_VPC
1
AUDIO_R_LINE_OUT
C345
VSUPPA 26
C352
1n8
50V
390p
220n
16V
C349
C348
C350
16V
100u
C306
LLC2 27
7
BLM21B201S
LLC1 28
78 VREF
R2
DIN[7]
4
Y7 31
77 GNDAI
SVP ENTEGRESINE
DIN[6]
3
Y6 32
R300
N.C
DIN[4]
DIN[5]
2
Y5 33
76 VSUPAI
VCC_5V
R323
33R
18 R1
Y4 34
IC216
VPC323XD
73 VIN2
75R
R306
VCCD2_3V3
BLM21B201S
1n
72 VINI
75R
R305
S326
RIN2
RGB_B_VPC
DIN[2]
69 VSUPF
71 CIN
75R
R304
NC14
NC13
Y2 38
R2
DIN[0-23]
JK304
22
21
67 I2CSEL
3
R AUDIO FAV
S325
VGA_RIN
9
DIN[0]
L2011
NC15 23
2
RCA_PR
FB_VPC
DIN[1]
2
Y1 39
C346
JK303
L AUDIO FAV
R322
33R
18 R1
Y0 40
79 FB1IN
RGB_SW2
L 12
RGB SWITCHING FOR VPC
PL301
4
PI5V330_SOIC
5E
RGB_G_VPC
66 VRT
L300
3
SC1_FB
SC2_FB
SC2_G
C341
65 GNDF
C323
CIN
1
VxtoVPC
23
SVHSfromSC2_C
1
ASGF2
BZT55C10
A D226 K
1
2
L317
BLM21A601S
25V
47n
C360
470p
50V
C359
470p
50V
10u
50V
VCC_5V
1
VCC_5V
SC1_G
BLM21B201S
L311
BLM21B201S
C332
2B
VCCD2_3V3
C340
10k
R315
S324
S302
C333
25V
2n2
10u
50V
C331
50V
3p3
C330
50V
3p3
BLM21B201S
AUDIO_L_LINE_OUT
AUDIO_R_LINE_OUT
S323
SC1_R
RGB_R_VPC
16V
100n
I2S_DEL_IN4
NC16 24
20
I2S_DEL_IN3
19
I2S_DEL_IN2
18
DVSS2
17
DVSUP2
16
15
I2S_DEL_OUT4
NC17 25
I2S_DEL_OUT3
NC9
14
C317
BACK RIGHT
9
23
BACK LEFT
NC18 26
I2S_DEL_OUT2
25V
47n
50V
1n5
50V
390p
NC19 27
NC8
13
L316
BZT55C10
BLM21A601S
A D225 K
1
2
NC20 28
8
NC12
20.25MHz
50V
1n5
R 16
C343
NC21 29
12
C318
1A
C320
NC24 32
IC2001
MAD4868A
11 NC11
S330
S331
NC2
10 NC10
R2031
33R
16V
220n
BLM21B201S
NC25 33
NC1
NC7
L308
VCC_5V
X300
2
7
R2032
33R
VCC_5V
C362
R2030
1k
VCCD2_3V3
C319
1
NC6
YPBPR_AUDIO_R_IN
YPBPR_AUDIO_L_IN
34
35
TEST
DVSS1
RESETQ
36
37
DVSUP1
38
I2S_DEL_WS
I2S_DEL_CL
39
40
I2S_DEL_IN1
41
42
ADR_SEL
100n
25V
BLM21B201S
RGB_SW3
DHS_2EX
RESETQ_MSP
C2048
STBY_5V
VCCD_3V3
100n
BLM21B201S
I2S_WS
I2S_CL
L2009
R4 5
C2047
I2S_DEL_OUT1
L2010
10u
50V
4
I2S_DA_IN1
I2S_DA_OUT
R3 6
3
R2 7
2
R2028
10R
18 R1
R2027
100R
43
SDA
44
SCL
DVS_2EX
A
R2026
100R
C2046
10n
50V
6
IC316
S303
VCCD2_3V3
A
SCL SDA
VCC_5V
RCA_PB
RGB_BIN
GIN2
S337
9
VGA_BIN
S336
S307
FB
BIN2
RGB SWITCHING FOR SVP
VGA&YPbPr SWITCHING
SM012
MAIN BOARD - VPC3230 CIRCUIT
62
CS0#
RAS#
CAS#
100n
C435
VD1_8
VCC
GND
5
3
21 B
11 A
5
VDDMQ_2V5
6
R4
ODD_PINK
R434
1k
C470
C471
100n
16V
100n
16V
DVS_2EX
VCCA_3V3
R4 5
R3 6
MCLK0
MCLK0#
MVREF
MD[16]
MD[17]
MD[18]
MD[19]
DQS[2]
DQM[2]
MD[20]
MD[21]
MD[22]
MD[23]
MD[24]
MD[25]
MD[26]
MD[27]
DQS[3]
DQM[3]
MD[28]
MD[29]
MD[30]
7
R3
4
R2 7
3
R2213
R2216
33R
2
100n
18 R1
100n
16V
4
R2
41 Y
CLKE
BA0
BA1
C428
16V
100n
C424
MD[31]
12
11
10
9
8
7
6
5
4
3
2
1
WE#
100n
C434
VD1_8
VDDMQ_2V5
VD1_8
VD1_8
DIN[0]
DIN[1]
DIN[2]
C425
R2215
33R
C459
MD[0]
MD[1]
MD[2]
C437
MD[3]
MD[4]
MCA[14]
100n
16V
S413
MD[5]
MD[6]
MCA[15]
R440
1R
SC2_FB_SVP
LVDS OUT
MA[0-11]
MD[24]
MA[6]
C446
MA[7]
100n 16V
MD[25]
MD[26]
MD[27]
MD[28]
MD[29]
MA[8]
MD[30]
VD1_8
MD[31]
MA[9]
MA[10]
MD[15]
DQM[1]
VD1_8
C448
MD[13]
100n
16V
DQM[2]
DQM[3]
DQS[0-3]
MD[14]
DQM[0-3]
DQM[0]
MA[11]
DQS[0]
MD[12]
16V
100n
DQS[1]
C456
DQS[1]
DQS[2]
DQS[3]
VDDMQ_2V5 DIN[0]
DIN[1]
DQM[1]
DIN[2]
MD[11]
DIN[3]
DIN[4]
MD[10]
MD[9]
C449
MD[8]
100n
16V
DIN[5]
DIN[6]
DIN[7]
MD[7]
DIN[8]
VD1_8
DIN[9]
MD[6]
DIN[0-23]
DIN[10]
DIN[11]
DIN[12]
MD[5]
DIN[13]
DIN[14]
MD[4]
DIN[15]
DIN[16]
DQS[0]
DIN[17]
DIN[18]
DIN[19]
DQM[0]
DIN[20]
MD[3]
DIN[21]
VDDMQ_2V5
MD[1]
DIN[22]
100n
16V
MD[2]
DIN[23]
MD[0]
DIN[21]
DIN[22]
DIN[23]
100n
C452
DIN[20]
VD1_8
VREFN_3
VREFP_3
VREFN_2
VREFP_2
VDDH
S445
100n
16V
26R_100MHZ_1.5A
L408
PAVDD
VL1_8
C469
100n
10u
100n
C466
C2238
100n
C2237
100n
100n
C2236
C2235
C432
C445
16V
10u
100n
16V
100n
16V
C442
VA1_8
100n
16V
10u
C458
L409
AVDD_ADC2
L402
16V
10u
100n
16V
L406
VA1_8
26R_100MHZ_1.5A
150R 600mA lik ferit
100n
16V
C2234
100n
16V
C2233
C2231
26R_100MHZ_1.5A
AVDD_ADC1
C454
VCCA_3V3
100n
16V
100n
100n
16V
C2232
100n
100n
16V
C467
100n
16V
100n
16V
C462
100n
16V
C460
100n
16V
L404
VA1_8
100n
16V
C429
MAIN BOARD - VIDEO DECODER CIRCUIT
63
C457
AVDD_ADC3
C426
C427
100n
16V
C430
100n
16V
C2226
100n
16V
C2225
100n
16V
C2224
C2223
AVDD3_AVSP2
100n
16V
C450
DIN[0]
DIN[1]
DIN[2]
DIN[4]
DIN[5]
DIN[3]
2u2
R2218
33R
VCCA_3V3
SM012
MD[23]
C436
VCCA_3V3
Q402
BC848B
Q401
BC848B
10p
FB
C473
68p
68p
C412
S442
C410
100n
R439
1k
C423
16V
10u
100n
16V
100n
16V
C421
100n
16V
C2222
SCL3
100n
16V
C2254
R414
68R
100n
16V
C2221
SDA3
SCL_EX
C2220
SDA_EX
R413
68R
VCCA_3V3
C472
L400
VDDH
MD[22]
MA[5]
100n
16V
C2242
R428
1k
150R 600mA lik ferit
MD[21]
100n 16V
100n
16V
C2241
VD1_8
FB_CONTROL
STBY_5V
R426
10k
STBY_3V3
MD[20]
MA[4]
C447
100n
16V
C2240
C2404
100n
16V
16V
10u
100n
16V
C2403
C2402
100n
16V
C2401
100n
16V
C2400
C433
16V
10u
100n
16V
100n
16V
C431
100n
16V
C2215
100n
16V
C2214
100n
16V
C2213
VD1_8
R425
10k
R423
10k
C2212
L401
MPUGPIO4
R424
1k
MPUCSON
MD[19]
MA[3]
C2239
VDDL
MD[18]
MA[2]
C468
26R_100MHZ_1.5A
16V
10u
VCCA_3V3
VCCA_3V3
MAIN RGB INPUT
DIN[6]
C415
100n
16V
50V
20p
100n
16V C408
PAVDD1
R405
75R
RGB_BIN
DIN[7]
PB_B1
DIN[9]
X400
C414
S427
MD[17]
MA[1]
VREFN_1
50V
20p
MD[16]
MA[0]
VREFP_1
100n
16V C407
14.31818MHz
R404
75R
RGB_RIN
DIN[10]
PR_R1
R2217 DIN[8]
33R
PAVDD
S426
MD[15]
VDDL
CLK_2EX
PDVDD
100n
16V
C465
VD1_8
DIN[11]
100n
C409
100n
16V
C2230
Y_G2
DIN[12]
100n
16V
C420
R403
75R
RGB_GIN
Y_G1
DIN[13]
Y_G1
VDDH
C406
S425
100n
16V
C2229
S438
CVBS3
DIN[14]
CVBS2
DIN[15]
S439
DIN[16]
VREFP_1
DIN[17]
VREFN_1
DIN[18]
S441
DIN[19]
75R
R418
R402
75R
R427
AVDD_ADC1
100n
16V
C2228
AVDD3_AVSP2
100n
16V
VD1_8
PB_B2
PLF2
CVBS_SVP
PB_B1
C2227
CVBS3
C
SVP_EX_51
PAVDD2
S431
VREFP_2
100n
16V
R400
75R
C402
VREFN_2
MD[14]
VDDMQ_2V5
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
R422
10k
CVBS2
VCCA_3V3
C400
CVBS_SVP
TXOUT0-
AVDD_ADC2
TXOUT0+
MAIN PICTURE
MD[13]
VDDL
VSSL
MA0
MA1
VDDM8
MA2
MA3
VSSM8
MA4
VDDM7
MA5
MA6
VSSM7
MA7
MA8
VDDC6
MA9
MA10
VSSC6
MA11
MD15
VDDC5
MD14
VSSM6
MD13
VDDM6
MD12
VSSM5
DQS1
VDDM5
VSSM4
DQM1
MD11
VDDM4
MD10
MD9
VSSC5
MD8
MD7
VDDC4
MD6
VSSM3
MD5
VDDM3
MD4
VSSM2
DQS0
VDDM2
VSSM1
DQM0
MD3
VDDM1
MD2
MD1
VSSC4
MD0
DIN20
DIN21
DIN22
DIN23
VSSC3
VDDC3
VSSH3
VDDH3
IC224
TXOUT1-
PR_R2
TXOUT1+
PR_R1
16V
100n
R401
75R
VREFP_3
100n
TXOUT2-
VREFN_3
TXOUT2+
C
TXCLKOUT-
S430
R2212
10k
R244 AVDD_ADC3
TXCLKOUT-
5
R4
MD[12]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
C_SELECTED
4
MPUCSON
C401
100R
TXCLKOUT-
INT#
TXCLKOUT+
6
TXOUT3-
R3
C411
TXCLKOUT+
7
TXCLKOUT+
3
ALE_EMU
R2
TXOUT3+
2
WR_EMU
100n
VD1_8
S440
R243
100R
18 R1
RD_EMU
S415 DVS_2EX
5
DE_2EX
6
R4
DIGITAL SINC
R3
SC2_FB_SVP
4
R2211
10k
3
MCA[7]
DHS_2EX
MCA[6]
100n
16V
R2
PWM2
PR_R2
7
1N4148
2
VDDH
MCA[5]
PARITY
R228
100R
18 R1
100n
16V
4
PC&YPbPr INPUT
SDA_EX
STBY_3V3
SCL_EX
5
D101
R4
R419
MCAD[7]
22R
C413
6
22R
5
R3
RST_H
R4
7
VGA_VSIN
6
R2
VGA_HSIN
3
100n
16V
VD1_8
MPUGPIO0
A_D0
A_D1
A_D2
A_D3
VDDC12
VSSC12
A_D4
A_D5
A_D6
A_D7
VDDH5
VSSH5
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
VDDC11
VSSC11
RD
WR
ALE
MPUCSON
INT
AVDD_ADC3
AVSS_ADC3
VREFN_3
VREFP_3
PR_R1
PR_R2
AVDD_ADC2
AVSS_ADC2
VREFN_2
VREFP_2
C
PB_B1
PB_B2
AVDD3_AVSP2
AVSS3_BG_ASS
CVBS_OUTP
CVBS_OUTN
AVDD_ADC1
AVSS_ADC1
VREFN_1
VREFP_1
CVBS1
CVBS2
CVBS3
AIN_N1
Y_G1
AIN_N2
Y_G2
AIN_N3
VSSC13
VDDC13
PDVDD
PDVSS
PAVDD
PAVSS
XTALI
4k7
MCAD[6]
R3
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
MLF1
R407
75R
R4
5
MCA[3]
C405
R408
75R
2
4
3
6
MCAD[5]
MCA[2]
100n
16V
MCA[4]
RIN2
MCAD[4]
7
R2
R3
R420
2
PB_B2
R2
R234
100R
18 R1
MCA[1]
C404
BIN2
4
R233
100R
18 R1
MCA[0]
3
MCAD[3]
C422
MCAD[0-7]
100n
16V
MCA[0-19]
R406
75R
Y_G2
MD[9]
MD[11]
XTALO
PAVDD1
MLF1
PAVSS1
PAVDD2
PLF2
PAVSS2
VSSC1
VDDC1
AIN_HS
AIN_VS
TESTMODE
RESET
SCL
V5SF
SDA
PWM
FLD_IO
VDDH1
VSSH1
H
V
DE
PLL_VCC
PLL_GND
TD1+
TD1TCLK+
TCLKTC1+
TC1LVDSGND
LVDSVCC
TB1+
TB1TA1+
TA1LVDSVDDP
GPO
VDDC2
VSSC2
DIN19
DIN18
DIN17
DIN16
DIN15
DIN14
DIN13
DIN12
VDDH2
VSSH2
DIN11
DIN10
DIN9
DIN8
CLK
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
MCAD[2]
C403
GIN2
7
MD[10]
C451
MCAD[1]
2
MD[8]
NC
MPUGPIO1
MPUGPIO2
MPUGPIO3
MPUGPIO4
VSSH4
VDDH4
VSSC10
VDDC10
MD31
VSSC9
MD30
MD29
VDDM16
MD28
DQM3
VSSM16
VDDM15
DQS3
VSSM15
MD27
VDDM14
MD26
VSSM14
MD25
VDDC9
MD24
MD23
VSSC8
MD22
MD21
VDDM13
MD20
DQM2
VSSM13
VDDM12
DQS2
VSSM12
MD19
VDDM11
MD18
VSSM11
MD17
VDDC8
MD16
BA1
VSSC7
BA0
CLKE
VDDC7
WE
VSSR
MVREF
VDDR
CAS
RAS
VDDM10
CS1
VDDM9
CS0_
VSSM10
MCK0_
MCK0
VSSM9
R236
100R
18 R1
MCAD[0]
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
MD[7]
S411
C463
16V
10u
100n
16V
C455
100n
16V
100n
16V
C2219
100n
16V
C2218
100n
16V
C2217
C2216
DIGITAL IDTV INPUTS [ITU 601]
VL1_8
3
100n
16V
MPUGPIO4
L407
R2214
18 R1
S437
PL104
26R_100MHZ_1.5A
IC107
74LX1G86STR
2
C418
R433
10k
PDVDD
VDDMQ_2V5
STBY_3V3
DIN[0]
DIN[1]
DIN[2]
DIN[3]
DIN[4]
DIN[6]
DIN[5]
DIN[3]
DIN[4]
R432
10k
2n7
50V
DIN[6]
S110
C443
16V
10u
100n
16V
100n
16V
C2211
100n
16V
C2210
100n
16V
C2209
C439
PLF2
100n
16V
C2208
C2207
R436
22R
DIN[7]
2n7
50V
PAVDD2
DIN[5]
R2210
10k
DIN[7]
CLK_2EX
C438
DHS_2EX
ODD_PINK
16V
10u
C444
100n
16V
100n
16V
C2205
100n
16V
C2204
100n
16V
C2203
VL1_8
22R
R430R431
22R
MLF1
100n
16V
C440
C2206
R435
22R
R429
22R
PAVDD1
MD[31]
1
C505
C517
100n
R510
1k
C501
10R
1u R508
2
MD[30]
6
7
MD[29]
4
5
100n
R516
15R
DDQS3
MCLK01
BA0
R518
33R
5
MA[11]
BA1
MA[10]
R519
33R
MA[9]
MA[0-11]
R521
33R
R520
33R
MA[8]
MA[7]
MA[6]
MA[5]
MA[4]
MA[3]
MA[2]
MA[1]
DDQS3
DQ27_B12
DQ26_C11
DQ25_C12
DQ24_D12
DQ15_E11
DQ14_E12
DQ13_F11
DQ12_F12
DQ11_H11
DQ10_H12
DQ9_J11
DQ8_J12
DM3_A11
DM1_G11
DQS3_A12
DQS1_G12
VREF_M12
VDDQ_B2
VDDQ_B4
VDDQ_B6
VDDQ_B7
VDDQ_B9
VDDQ_B11
VDDQ_D2
VDDQ_D11
VDDQ_E3
VDDQ_F3
VDDQ_H3
VDDQ_J3
VDDQ_E10
VDDQ_F10
VDDQ_H10
VDDQ_J10
VDD_C7
VDD_C6
VDD_D10
DQM[1]
DQM[2]
C524
50V
4n7
C529
16V
100n
C528
16V
100n
C508
25V
10n
C527
16V
100n
C509
25V
10n
C515
16V
100n
C510
25V
10n
C504
16V
100n
C511
25V
10n
C503
16V
100n
C512
25V
10n
C2253
16V
100n
C513
25V
10n
C2252
16V
100n
C514
25V
10n
R504
47R
R505
47R
C2250
16V
100n
10n
25V
L501
C520
R2208
10R
MCLK0#
C2251
16V
100n
C519
25V
10n
MCLK01
R2209
10R
R4 5
MD[0]
4
R3 6
MD[1]
3
R2 7
MD[2]
2
C530
16V
100n
C507
25V
10n
R4 5
MD[8]
C531
16V
100n
C506
50V
4n7
C500
4
R3 6
R2 7
2
MD[10]
MD[11]
R507
10R
18 R1
C532
16V
100n
C521
50V
4n7
BLM21B201S
DDQS0
DDQS1
DQM[0]
DQM[1]
R4 5
R3 6
MD[12]
16V
100n
C522
50V
4n7
39
VDD_D3
118
VDD_K10
115
VDD_K7
114
VDD_K6
111
VDD_K3
92
VSS_H8
91
VSS_H7
90
VSS_H6
89
VSS_H5
80
VSS_G8
79
VSS_G7
78
VSS_G6
77
VSS_G5
68
VSS_F8
67
VSS_F7
66
VSS_F6
65
VSS_F5
56
VSS_E8
55
VSS_E7
54
VSS_E6
53
VSS_E5
45
VSS_D9
43
VSS_D7
42
VSS_D6
40
VSS_D4
104
VSS_J8
103
VSS_J7
102
VSS_J6
101
VSS_J5
117
VSS_K9
112
VSS_K4
105
VSQ_J9
93
VSSQ_H9
100
VSSQ_J4
88
VSSQ_H4
81
VSSQ_G9
MCLK0
VDDMQ_2V5
MCLK01#
MAIN BOARD - DDR RAM CIRCUIT
64
100u
16V
C523
50V
4n7
4
R2 7
2
3
MD[13]
MD[14]
VCCA_2V5_FLT
C525
50V
4n7
6
17
5
4
13
26
25
37
50
49
62
61
86
85
97
98
2
74
1
73
132
3
10
27
28
29
32
33
34
41
44
52
57
64
69
76
DQM[3]
MD[15]
SM012
DQ0_A6
DQ1_B5
DQ2_A5
DQ3_A4
DQ4_B1
DQ5_C2
DQ6_C1
DQ7_D1
DQ16_E2
DQ17_E1
DQ18_F2
DQ19_F1
DQ20_H2
DQ21_H1
DQ22_J1
DQ23_J2
DM0_A2
DM2_G2
DQS0_A1
DQS2_G1
NC_L12
VSSQ_A3
VSSQ_A10
VSSQ_C3
VSSQ_C4
VSSQ_C5
VSSQ_C8
VSSQ_C9
VSSQ_C10
VSSQ_D5
VSSQ_D8
VSSQ_E4
VSSQ_E9
VSSQ_F4
VSSQ_F9
VSSQ_G4
DQM[0]
R506
10R
18 R1
DQM[0-3]
MA[0]
R511
MD[3]
10R
18 R1
R4
6
R4 5
R3
CLKE
7
MD[4]
4
4
CS0#
R2
1u
50V
EM6A9320
IC1
R3 6
3
RAS#
R1
R517
33R
R2 7
2
50V
4n7
C502
BLM21B201S
DDQS2
3
WE#
100u
16V
C526
L500
R515
15R
R503
CAS#
DDQS2
8
DDQS1
MCLK01#
18
DQM[3]
DQM[2]
R514
15R
MD[5]
3
DQS[3]
DDQS0
DQ28_A9
DQ29_A8
DQ30_B8
DQ31_A7
NC_B10
NC_G10
NC_K12
NC_K11
NC_L3
NC_M2
NC_L2
NC_G3
NC_B3
NC_K8
NC_L9
CK-_L11
CK_L10
CKE_M11
WE-_K2
CAS-_K1
RAS-_L1
CS-_M1
BA0_M3
BA1_L4
A11_L6
A10_K5
A9_L7
A8/AP_M10
A7_M9
A6_M8
A5_L8
A4_M7
A3_M6
A2_L5
A1_M5
A0_M4
MD[6]
2
DQS[2]
R513
15R
MD[9]
DQS[0-3]
DQS[1]
5
9
8
20
7
22
82
120
119
123
134
122
75
15
116
129
131
130
143
110
109
121
133
135
124
126
113
127
142
141
140
128
139
138
125
137
136
R509
MD[7]
10R
18 R1
DQS[0]
VCCA_2V5_FLT
24
35
36
48
59
60
71
72
95
96
107
108
11
83
12
84
144
14
16
18
19
21
23
38
47
51
63
87
99
58
70
94
106
31
30
46
MD[16]
R4
C518
R512
1k
C516
R502
MD[19] 10R
18
R1
MD[18]
2
7
R2
MD[17]
3
R3 6
4
VDDMQ_2V5_FLT
MVREF
5
R501
MD[23] 10R
18
R1
MD[22]
2
7
R2
MD[21]
3
6
R3
MD[20]
4
5
R4
VDDMQ_2V5_FLT
VDDMQ_2V5_FLT
R1
R3
R4
R4
MD[24]
4
R2
R500
MD[27] 10R
18
R1
MD[26]
2
7
R2
MD[25]
3
R3 6
3
MD[28]
MD[0-31]
VCCA_2V5
LED2
S414
Q400
BC337
PWM2
SM012
R417
22R
BRT_CNTL
VCC_5V
BRIGHTNESS CONTROL
FL_A14
STBY_5V
R604
4k7
R6015
220R
R6016
220R
SCL
LEVEL SHIFTER
SDA
E2
65
STBY_3V3
VCCA_3V3
PDP_GO1/BL_ON_OFF
BC848B
D600
LOC_KEY
BZT55C5V1
2
1
PDP_GO/BL_ON_OFF
1
2
PL604
PL606
3
MAIN BOARD - MCU INTERFACE CIRCUIT
UP_RXD
UP_IRQ
C604
Q6009
PL308
S629
UP_TXD
S628
S627
1
2
3
4
R653
3k9
C625
3k9
R660
PIN8_SC3
C626
C621
P1_6
47
2
85 A11
P1_5
46
3
86 A4
P1_4
45
87 ALE
P1_3
44
88 PSEN
P1_2
43
P1_1
42
P1_0
41
VSS1
39
93 A2
P3_7
38
94 A1
P3_6
37
95 FL_CE
P3_5
36
96 D7
P3_4
35
SDA5550M
VDD3_3_1 40
6
34
P3_2
33
99 D0
P3_1
32
100 D5
P3_0
31
LOC_KEY
UART SOCKET FOR IDTV
PL605
1
R2306
100R
R6014
4k7
Q6010
BC848B
CPU_GO
IR
Q6008
BC848B
CPU_GO1/STBY
STBY_5V
4k7
R681
4k7
R680
R679
4k7
VCCD3.3V_FLT
VCCA_2V5
S6314
84 A5
SC2_FB
2
TV-LINK
SDA_TVLINK
R6044
4k7
R6041
4k7
R6017
4k7
R682
4k7
UP_IRQ
1
25V
100n
MCA[3]
48
C630
MCA[5]
P4_2
R6040
4k7
MCA[11]
83 A9
69
68
67
66
65
A18
A19
NC5
RD
NC4
NC3
P1_7
55
54
53
52
51
VSSA1
NC2
XTAL1
XTAL2
NC1
56
61
62
63
WR 64
70
A17
A16
VDDA2_5_1
R693
4k7
R6039
100R
25V
100n
HDMI_CEC
VS
HS_SSC
MCA[4]
4
IC220
49
S613
S614
30
NC
P2_3
P2_2
P2_1
89 A3
50
VCCD_3V3
R691
4k7
100n
STBY_3V3
R692
2k7
R2300
MMC_IR GIRISI
VCC_8V
R2303
10k
STBY_3V3
C622
25V
100n
29
28
27
26
VSSA
P2_0
4k7
P3_3
98 D6
VDDA2_5
CVBS
EXTIF
OCF
STOP
ENE
P0_7
P0_6
P0_5
P0_4
71
72
A15
73
FL_PGM
74
VDD2_5_1
VSS2
75
76
VDD3_3_2
77
A14
4
3
2
R4 5
R3 6
MCA[19]
33p
50V
C627
C624
50V
33p
100k
R687
R686
75R
R685
75R
R684
75R
4k7
R676
C631
25V
100n
L604
MCA[15]
MCA[14]
MCA[12]
MCA[13]
R6042
1k
STBY_2V5
100n
C615
STBY_3V3
MCA[19]
MCA[18]
MCA[16]
MCA[17]
STBY_2V5
VCCD3.3V_FLT
MCA[15]
MCA[14]
MCA[12]
MCA[13]
R640
4k7
MCA[18]
MCA[16]
MCA[17]
RD_EMU
R4 5
R3 6
R2 7
R639
10R
18 R1
4
3
R2 7
MCA[18]
MCA[12]
R648
4k7
STBY_3V3
S601
BLM21B201S
R2302
47k
BLM21B201S
25
24
23
22
21
20
19
18
17
16
15
14
13
P0_3
P0_2
MCA[9]
LM809 2
IC221
BC848B
25V
100n
1k
R661
C620
3k9
R657
S615
S610
4k7
4k7
25V
100n
STBY_2V5
15k
R656
22u
50V
15k
R655
L603
R697
PIN8_SC2
C613
15k
R654
100n
STBY_2V5
DVD_12V_SENSE
15k
R698
3k9
PDP_GO1/BL_ON_OFF
RST
P4_3
3
R2301
47k
Q2300
C611
22u
STBY_3V3
L601
STBY_3V3
PIN8_SC1
STBY_2V5
CPU_GO1/STBY
22u
50V
VCCD3.3V_FLT
BC848B
R6038
1k
C608
STBY_3V3
Q2301
S600
C607
R6043
4k7
STBY_3V3
RST_H
R2304
100R
R6037
1k
78
C612
Q2299
SW_ENABLE
25V
100n
12
90 A10
R696
SCL3
RX1_INT
S608
R695
SDA3
11
7
97 A0
VDD3_3
92 VDD3_3_3
RX1_RST#
S607
4k7
5
4k7
R4
R6013
R3
91 VSS3
R694
4
2
R629
10R
18 R1
MCA[12]
MCAD[4]
MCAD[5]
MCAD[6]
MCAD[7]
R632
4k7
BC848B
16V
100n
3
R690
R6031
47R
MCAD[5]
MUTE_AMP
MCAD[5]
AC_INFO
MCAD[0]
P0_1
MCAD[0]
R2
10
2
A13
25V
100n
4k7
MCAD[6]
P0_0
MCAD[7]
9
MCAD[6]
2
8
MCAD[7]
1
10R
R625
R624
10R
18
R1
A12
FL_WE
4k7
8
79
100n
25V
R6030
47R
SCL2
7
C609
SCL2
MCA[0]
R688
4k7
MCA[0]
3
A7
80
30
A17
S604
R689
MCA[1]
6
VSS
MCA[1]
7
MCA[2]
4
VDD2_5
MCA[10]
6
MCA[2]
5
XROM
ALE_EMU
5
MCA[10]
R4 4
R626
10R
STBY_3V3
SDA2
5
FL_RST
31
W
MCA[10]
MCA[11]
MCA[12]
MCA[13]
MCA[14]
FL_A15
SDA2
L600
PSEN_UP
R3
4D 3
MCA[3]
R2
3D 2
MCAD[7]
6
1
E 22
7
2
MCA[5]
3
MCA[11]
7
MCA[10]
R1
8
MCAD[0]
8
82 A6
MCAD[3]
MCA[4]
R4
81 A8
3
MCAD[2]
MCA[6]
2
MCAD[3]
MCA[10]
5
R3
MCAD[2]
MCA[9]
R2
STBY_3V3
FL_OE
6
2D 4
MCA[6]
R627
10R
1
R1
1D 1
MCA[11]
7
6
MCA[9]
8
MCAD[4]
MCA[8]
MCAD[4]
MCA[7]
4
MCA[11]
5
MCA[8]
MCAD[1]
MCA[8]
R6036
4k7
FL_A16
MCAD[1]
MCA[9]
10R
R628
MCA[7]
R6035
1
2
32
A16
VCC
3
A15
A18
4
A12
MCA[10]
MCA[11]
MCA[12]
MCA[13]
MCA[14]
MCAD[4]
MCAD[5]
MCAD[6]
MCAD[7]
MCA[16]
MCA[17]
MCA[18]
MCA[19]
WR_EMU
TV_LINK
R610
10k
STBY_3V3
A10 23
25V
100n
MCA[13]
C606
A11 25
4k7
MCAD[7]
VCCD3.3V_FLT
S623
MCA[16]
MCA[17]
MCA[18]
MCA[19]
STBY_3V3
R2305
10k
R6010
10k
1
FL_A14
MCA[13]
C610
100n
16V
SDA SCL
BSN20
Q603
A0
A9 26
IC218
DQ7 21
8 VCC
SDA3
C603
100u
16V
SDA3
2
DQ6
20
13 DQ0
G 24
A1
DQ5
19
MCA[1]
7WP
DQ4
18
CORRESPONDS TO
Winbound W27E040 EPROM &
ST M29F040 Flash
3
DQ3
17
IC219
M29W040B
24LC32A
VSS
16
A8 27
4
MCAD[6]
MCAD[5]
MCAD[4]
MCAD[3]
5
A2
MCAD[6]
MCAD[5]
MCAD[4]
MCAD[3]
7A
VSS
ALE_EMU
DQ2
15
MCA[4]
S602
BSN20
Q602
59 60
DQ1
14
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
A13 28
S603
R607
10k
MCAD[2]
MCAD[1]
SRAM_WE
MCAD[2]
MCAD[1]
12 A0
RST#
11 A1
STBY_3V3
10 A2
57 58
S6317
NC5
NC6
NC7
A10
IC217
3
55 56
MCA[0]
53 54
51 52
RD_EMU
NC4
NC3
A9
A8
A11
A12
A13
A14
I/O5
I/O6
VCC1
VSS1
I/O7
I/O8
OE
A15
MCA[8]
A14 29
6
NVM_WP
R601
4k7
SCL
SCL3
WR_EMU
MCA[0]
S6318
SRAM_OE
MCAD[0]
SRAM_WE
22
21
20
19
A7
A6
A5
9A
49 50
S6319
PSEN_UP
FL_OE
MCA[15]
MCA[14]
MCA[13]
MCA[12]
MCA[11]
MCA[9]
MCA[1]
47 48
MCA[9]
MCA[10]
MCA[9]
MCA[8]
18
17
16
WE
I/O4
I/O3
VSS
MCA[2]
45 46
S6320
MCA[15]
MCA[14]
MCA[13]
MCA[12]
MCA[11]
MCA[8]
MCAD[7]
MCAD[6]
MCAD[5]
MCAD[4]
MCAD[3]
MCAD[2]
MCAD[1]
MCAD[0]
MCA[16]
MCA[17]
MCA[8]
MCA[7]
MCA[6]
15
14
13
12
VCC
I/O2
I/O1
CS
A4
MCA[2]
6
42
43 44
41
39 40
37 38
35 36
33 34
31 32
29 30
MCA[10]
MCA[9]
MCA[8]
MCAD[7]
MCAD[6]
MCAD[5]
MCAD[4]
MCAD[3]
MCAD[2]
MCAD[1]
MCAD[0]
S624
MCA[5]
MCAD[3]
MCAD[2]
11
10
9
8
7
A16
A17
A18
NC8
NC9
MCA[5]
7
6A
SCL2
26
27 28
25
23 24
21 22
19 20
17 18
MCA[16]
MCA[18]
MCAD[1]
MCAD[0]
MCA[15]
A3
A2
A1
0
MCA[3]
4
SDA2
Q601
8A
VCCA_3V3
MCA[7]
MCA[6]
MCA[5]
15 16
13 14
11 12
9 10
8
MCA[17]
MCA[18]
MCA[7]
MCA[6]
MCA[5]
MCA[15]
MCA[4]
6
5
4
3
NC2
MCA[3]
SDA
Q605
S6316
STBY_3V3
MCA[7]
MCA[6]
MCA[5]
MCA[4]
MCA[3]
MCA[2]
MCA[1]
7
56
4
MCA[19]
MCAD[3]
MCAD[2]
MCAD[1]
MCAD[0]
MCA[14]
MCA[15]
MCA[16]
MCA[4]
MCA[3]
MCA[2]
MCA[1]
2
NC10
MCA[6]
5A
5
R6007
10k
MCA[4]
100R
R611
Q600
MCA[5]
STBY_5V
4k7
R600
S606
Q604
100R
R606
100R
R6011
SCL3
SCSDA
FL_A15
R6005
47k
S622
3
19
Q7
MCA[19]
20
1
MCA[14]
2
MCA[15]
MCA[3]
MCA[2]
MCA[1]
MCA[0]
MCA[0]
NC1
K6R4008V1C-I/C-P
STBY_5V
FL_A17
MCA[4]
15
MCA[3]
Q3
MCA[2]
I5
100R
R6006
7
MCA[0]
S621
SCSCL
SRAM_OE
MCA[1]
MCA[0]
16
S6315
Q4
12
MCA[16]
3
VCC
CLK
I0
I1
FL_WE
S605
I4
CIRCUIT OF SW UPDATE FROM SCART2
6
PL607
MCA[19]
STBY_3V3
SRAM_WE
S6311
FL_OE
17
S6312
18
Q5
1
Q6
I3
PL600
I2
5
2
3
4
4
MCA[18]
STBY_5V
PSEN_UP
5
Q1
Q0
14
S6310
IR
S6300
BC848B
Q6006
13
12
Q2
BC848B
Q6007
R6018
22k
GND
I7
11 OE
10
9
I6
LED1
100n
16V
C419
C417
R416
4k7
R415
1k2
MCA[17]
IC622
GAL16LV8
R6019
22k
R412
22R
16V
100u
C416
PWM
50V
10u
S412
STBY_3V3
MCA[7]
R1
VCCA_2V5
100n
16V
MCA[6]
R2
GAL_IAP
STBY_3V3
MCA[7]
R3
C600
FL_A16
R1
8
C601
MCA[18]
R2
S620
16V
100n
100n
25V
R3
WR_EMU
SRAM_OE
C605
R4
RD_EMU
STBY_3V3
R4
1
STBY_3V3
Q6011
BC848B
L609
VCCD_3V3
1
RST#
25V
100n
6MHz
FL_A17
C623
X600
RST#
GAL_IAP
INT#
NVM_WP
SDA3
SCL3
PORT
PWM
STBY_3V3
LED1
UP_RXD
SDA_TVLINK
PROTECT
LED2
C633
UP_TXD
IR
FB
C628
100n
25V
S6313
PC_STBY
IC3000
LM1117
P1_5V
AMP_PIN7
AUDIO_AVCC5
AMP_PIN6
R4 5
4
R3 6
3
Q13 51
AUDIO_AGND
AGND_SII
90 AGND3
2
Q21 38
3
Q22 37
4
Q23 36
R2
7
R3
6
R4
5
R2045
33R
DE_2EX
92 RX1+
VSYNC 34
R2044
33R
DVS_2EX
AVCC_SII
93 AVCC2
HSYNC 33
R2043
33R
DHS_2EX
4
AGND_SII
94 AGND4
3
AVCC_SII
95 AVCC3
S812
6
S811
5
S810
SCK 32
WS 31
96 RX2-
2
SDO 30
97 RX2+
1
PL2001
SPDIF 29
98 AGND5
AGND_SII
OGND1 28
99 GND4
MCLKIN 27
2
3
4
AUDIO_AGND
DAC_SCK
R2
7
DAC_WS
R3
6
DAC_SD0
R4
C2089
2n7
50V
5
OGND_SII
R2040
33R
R2041
33R
R2073
270k
AUDIO_AGND
S801
P1_5V
GND_SII
OGND_SII
SM012
2OE 7
31 B
2B 6
4A
2A
Q1
2N7002
4
5
HDMI_3V3_PLL
SN74CB3Q3305
P1_EVCC5
S806
1N5817
MAIN BOARD - HDMI/DAC CIRCUIT
66
CEC
AOUTL
5
6
F
AMP_PIN3
C
D
4
3
4
DAC_WS
DAC_MCLK
SDATA
2
S808
S809
S807
HDMI_CEC
DAC_SCK
HDMI_3V3
VCC_5V
21 A
1
IC2006
24
HDMI_3V3
PLLIN
23
25
PGND2
PVCC2
22
OVCC
21
0VCC_SII
RSVDO1
RSVDO2
20
17
RSVDL1
VCC1
16
GND_SII
19
GND1
15
18
ANBPB
14
NC3
8
D2023
S804
D2021
R2071
10R
BZT55C5V6
1n
50V
1n
50V
C2087
100n
25V
C2086
100n
25V
C2085
C2084
C2083
16V
10u
0VCC_SII
A D2020K
1
2
P1_CBL5V
S803
HDMI_3V3
C2065
pin8
D2022
S802
close to
100n
25V
1N5817
1n
50V
1n
50V
C2082
100n
25V
C2081
100n
25V
C2080
C2079
C2078
VCC_SII
16V
10u
HDMI_3V3
A8
BZT55C5V6
VCC_5V
330R_100MHZ_3A
AUDIO_AGND
2n7
50V
DAC_SD0
10u
16V
Place cap.s
L2017
AGND_SII
C2064
1OE
R2095
10k
AUDIO_AGND
S800
TOCOMP
1
R2096
27k
10n
25V
C2061
IC2014
R2097
330k
AUDIO_AVCC5
C2067
C2066
60R_100MHZ_3A
330R_100MHZ_3A
25V
10u
25V
47n
C2063
50V
10u
L2013
1n
50V
100n
25V
C2077
100n
25V
C2076
C2075
VCC_5V
3k9
R2039
10u
50V
25V
100n
C2094
Place PLL circuit as
chip as possible
C2097
26
compact and as close to
50V
1n
C2062
25V
100n
Place close to pins 22&23
L2016
AVCC_SII
C2074
L2015
16V
10u
C2073
100n
25V
60R_100MHZ_3A
R2038
4k7
DACVCCB
13
C2060
VCC_SII
ANGY
DACGNDB
12
DACVCCG
11
COMP
8
DACGNDG
ANRPR
7
TOCOMP
10
DACVCCR
6
RSET
DACGNDR
5
9
NC2
4
1n
C2059
S805
Close to pin9
HDMI_3V3
MCLKOUT
R2035
100R
NC1
DACGND
3
DACVCC
2
1n
100n
C2058
100n
C2057
C2056
10u
C2054
L2012
C2055
60R_100MHZ_3A
HDMI_3V3
100n
25V
RX1_AVCC3
1
100 VCC4
VCC_SII
AUDIO_AGND
2n7
50V
C2095
DAC_MCLK
8
GND_SII
R2042
33R
18 R1
2n7
50V
2k32
R2075
91 RX1-
C2098
C2090
AUDIO_AGND
DE 35
S813
7
AMP_PIN7
8
IC2002
SII9993
4k7
R2084
89 AVCC1
5
R2083
2k32
88 AGND2
AVCC_SII
AOUTR
AGND_SII
MCLK
10
9
3u3
50V
R2046
33R
18 R1
Q20 39
AUDIO_AGND
87 RX0+
AMP_PIN3
VCC_SII
S814
11
AUDIO_AGND
AMP_PIN6
GND_SII
VCC2 40
AUDIO_AGND
GND2 41
86 RX0-
270p
50V
2k32
R2076
85 AGND1
AGND_SII
S815
12
C2093
C2092
R2086
5k6
S816
CEC
50V
10u
R2081
560R
DAC_AOL
5
R2085
1k2
R4
6
C2091
Q19 42
7
3u3
50V
84 RXC+
14
4
R3
AUDIO_AVCC5
S817
R2
R2079
1k2
3
R2078
5k6
2
R2077
4k7
Q18 43
C2088
Q17 44
83 RXC-
R2080
100k
82 AVCC
AUDIO_AGND
AVCC_SII
2n7
50V
P1_DDC_SCL
3
R2047
33R
18 R1
OGND_SII
1
OGND2 45
R2048
33R
LRCK AGND
81 EXT_RES
MC33202
IC2008
R2082
2k32
ODCK 46
AUDIO_AVCC5
0VCC_SII
C2096
80 PVCC1
P1_DDC_SDA
R2090
47k
6
P1_CBL5V
R2089
47k
E
H
8
18
15
100n
25V
270p
50V
A
19
OVCC2 47
13
2n7
50V
C2100
DIN[23]
DIN[22]
DIN[21]
DIN[20]
DIN[19]
DIN[18]
DIN[17]
DIN[16]
DIN[7]
DIN[6]
DIN[5]
DIN[4]
R2 7
2
R2049
33R
18 R1
Q11 53
Q10 54
Q9 55
OGND_SII
0VCC_SII
OVCC3 56
OGND3 57
Q12 52
DIN[2]
DIN[1]
DIN[3]
R4 5
4
R3 6
R2 7
2
R2050
33R
18 R1
R4 5
4
Q7 59
Q8 58
R3 6
60
Q6
3
DIN[0]
DIN[15]
DIN[14]
DIN[13]
61
3
R2 7
2
Q5
DIN[9]
DIN[12]
DIN[11]
R4 5
4
R2051
33R
18 R1
62
Q4
VCC_SII
64
63
Q3
VCC3
DIN[8]
DIN[10]
R3 6
3
R2 7
2
GND_SII
65
GND3
R2052
33R
18 R1
OGND_SII
66
0VCC_SII
OVCC4
OGND4
68
67
69
Q1
Q2
72
RESET
70
R2053
4k7
73
RSVDL2
75
Q16 48
79 PGND1
16
AUDIO_AGND
R2094
33R
Q15 49
AUDIO_AGND
10u
50V
C2104
Q14 50
P1_HPD
RX1_AVCC3
100n
16V
C3007
C2103
C2102
C2099
78 OGND5
OGND_SII
R2091
20k
10u
50V
25V
100n
77 DSCL
DSCL
1n
50V
17
560R
R2087
AUDIO_AGND
76 DSDA
DSDA
C3006
100u
16V
C3008
100n
16V
C3009
100u
16V
IN OUT 2
GNDVOUT
1
4
C2101
DAC_AOR
CLK_2EX
100n
25V
C2071
TP100
S819
S818
10u
50V
C2070
CSDA
L2014
Place close to pins 79&80
C2069
74
C2068
CSCL
60R_100MHZ_3A
25V
100n
RX1_INT
SCL3
R2065
56R
SDA3
P1_DDC_SDA
7
R2063
47k
R2064
56R
C3004
100u
16V
R2069
10k
R2062
4k7
HDMI_3V3_PLL
P1_DDC_SCL
G
5
DIN[0-23]
B
SDA
C3005
100n
16V
S2 4
2
VSS
D2
S2 4
Q0
4
3
VCC_5V
7
6
3
HDMI_3V3_PLL
C3003
100n
16V
IC3001
LM1117
RX1_RST#
VA
SCL
G2 5
CS4334
A2
D2
3
G1
UPA672T
UPA672T
SW_ENABLE
RX1_RST#
3
2
4k7
R2068
DSCL
DEM/SCLK
7
R2098
100R
Q2
BC848B
G2 5
AUDIO_AGND
WP
IC2003
24LC02
VCC_5V
G1
2
71
A1
D1 6
100n
16V
C3002
P1_HPD
IC2013
IC2012
INT
2
S1
1
D1 6
C3001
100u
16V
IN OUT 2
GNDVOUT
1
4
R2088
100k
8
C3000
100n
16V
AUDIO_AGND
VCC
100n
25V
C2072
A0
3
DSDA
1 S1
1
VCC_5V
R2070
1k
R2067
470k
R2066
470k
P1_EVCC5
HDMI_3V3
R2074
270k
AUDIO_AGND
HDMI_3V3
L918
S908
1
2
3
4
STBY_5V
STBY_3V3
D905
L923
L913
L907
IC902
C916
100n
16V
C914
16V
220u
100n
50V
C908
16V
1000u
L920
3
C906
3
1N4007
2
1
10u
STBY_2V5
D906
C920
+12V
16V
220u
IC904
1N4007
R918
100n
4
1N4007
100p
D912
STBY_2V5
34
D913
47u
50V
C921
1N4148
ON/OFF
C939
100n
16V
16V
100u
100n
16V
VA1_8
C941
16V
100u
100n
16V
C938
C930
22u
C929
100u
22u
100n
16V
L916
C926
C913
C911
22u
1_8VMAIN
10u
16V
Q903
C940
100n
16V
16V
100u
VL1_8
S912
C927
16V
100u
100n
16V
C936
C937
C928
L910
VD1_8
16V
100u
22u
100n
16V
5
C925
L914
1_8VMAIN
C924
FEEDBACK
4
3
2
C947
1_8VMAIN
22uH_3.9A_SMD
16V
1000u
DIG_DIM_PWM
BLM21B201S
S902
R904
330R
L911
STPS745
D904
BRT_CNTL
S901
GND
VIN
1
S900
A_DIM_PWM
R905
160R
22u
22u
S911
L908
VCC_12V
SS33
10
D911
9
C923
100n
16V
L915
1_8VMAIN
1.8V_ON/OFF
C905
D915
S913
VCCA_2V5
L922
PANEL_VCC
S907
SAP 30030067 ADJ TYPE
S905
16V
100u
8
VCC_12V
1
PANEL_VCC1
10u
C946
BLM21B201S
IC903
3 LD1117 2
LM2576
OUTPUT
1N4007
7
VCC_33V
PORT
6
VCCD_3V3
D914
D903
IC223
22u
L924
R915
470R
N.C
1R
R913
SOT 223
VCCA_3V3
CPU_GO1/STBY
5
R919
2k2
R910
10k
120R
R911
L921
PROTECT
VCC_12V
C944
VDDMQ_2V5
C922
100n
16V
Q902
SEL
C919
100u
16V
C943
6
D902
VCC_8V
1N4148
1
3
D910
5
DIG_DIM_PWM
56p
2
1N4007
22u
D909
330R
R923
2
C945
VCCA_3V3
1N4148
FDC642P
A_DIM_PWM
56k
R921
10k
R924
D901
6
COMP. 5
R925
10k
1
GND
VCC_33V
1N4007
PDP_GO/BL_ON_OFF
3 VIN VOUT2
GND
1
R909
120R
C915
100n
16V
16V
100n
PL901
C931
16V
100u
D900
N.C
4
VCC
MC34063A
1N4148
C918
100n
C935
100n
C934
C933
C912
L912
C902
CAP.
D908
1.8V_ON/OFF
CS52015-3
IC901
47u
R901
470R
3
SENSE 7
VCCD_3V3
50V
22u C917
STBY_3V3
C932
N.C
R900
470R
100n
VCC_5V
22u
16V
1000u
100n
R922
3k3
R914
10k
R907
10k
L919
C903
VCC_5V
1N4148
R908
10k
Q900
BC848B
12
D907
R912
10k
BC858B
Q901
PROTECT
EMITTER
56p
1N4148
11
2
DRI.COL. 8
C942
STBY_2V5
5k6
R903
10
C910
100n
16V
47u
50V
9
VCC_8V
C909
8
47u
50V
C901
L904
STBY_3V3
3I N OUT 2
ADJ
1
C904
100n
16V
R902
1k
L903
SW.COLL.
PANEL_VCC_ON/OFF
SM012
R917
100R
LM317
IC900
L902
6
1
R916
100R
5
R920
6k8
S904
S903
L909
N.C
L905
7
MMC
SUPPLY
AC_INFO
2
L901
STBY_5V
4
LG_1/IRQPDP
PDP_GO1/BL_ON_OFF
FAN1616AS-3.3
SOT 223
L900
S910
3
STBY_5V
4
S909
STBY_3V3
VCC_12V
C900
16V
100u
5V
PL900
VCCA_3V3
2
7
6
5
4
3
2
VCC_5V
1
L906
5V
1
1
L917
VCCA_3V3
PL902
PANEL_VCC1
PL904
PL903
VCC_12V
MAIN BOARD - POWER SUPPLY CIRCUIT
67
SM012
S737
2 LM809
68
1
S734
S732
3
S738
S733
vcc 5v
PL707
RESET OUT
MODE_OUT
VCLAMPR
35
36
ROUTN1
44
PGNDL1
PGNDR2
43
19
PGNDL2
PGNDR1
42
20
LOUTP1
ROUTP2
41
21
LOUTP2
ROUTP1
40
9k1
R768
Q710
BC848B
S735
MUTE_3V3
S736
L722
50R_100MHZ_3A
L719
40uH
L724
15V_AUD
15V_AUD
R772
4k
25V
100n
C825
MUTE
Q603
BSN20
IC703
Q604
BSN20
AMPLIFIER BOARD - D-CLASS AMPLIFIER CIRCUIT
470n
63V
C806
470n
63V
C805
C785
50V
1n
L718
C786
50V
1n
3
2
1
RINP
RINN
SD_NOT
C787
1u
C791
1u
100n
25V
C823
3k3
R773
1u
C790
S739
C784
C780
4
V2P5
HIGH=ON
100n
25V
100n
25V 25V
220u
5
LINP
LOW=OFF
C814
6
LINN
C788
1u
C789
1u
18k
R746
12k
R765
Q715
C781
LOUTN2
18
50V
10n
45
C782
C813
46
C783
PVCCR3
ROUTN2
50V
10n
PVCCR4
50V
100n
48
47
50V
100n
17
TPA3004D2
IC702
BSRN
C775
MODE
34
8
7
AVDDREF
9
VREF
33k
R745
L904
C777
25V
220u
50V
100n
1u
16V
C776
AVCC
37
33
38
BSRP
VAROUTR
PVCCR1
BSLP
32
PVCCL4
24
VAROUTL
23
31
39
AGND2
PVCCR2
30
PVCCL3
AVDD
22
29
VARMAX 10
VARDIFF
15V_AUD
15V_AUD
MUTE
50V
C778
100n
COSC
28
L727
C811
25V
100u
ROSC
27
REFGND 12
VOLUME 11
R755
22k
R770
1k
100n
25V
C824
Q709
BC848B
C779
50V
LOUTN1
220p
16
120k
PVCCL2
R756
100k
15V_AUD
15
R742
VCLAMPL
40uH
PVCCL1
AGND1
C793
50V
10n
R754
1k8
C822
25V
1000u
SS33
22uH_3.9A_SMD
26
25
100n
50V
50R_100MHZ_3A
BSLN
14
C792
1u
16V
100n
50V
50R_100MHZ_3A
13
22n
50V
1
2
15V_AUD
C817
R767
3k3
C801
220u
25V
L721
R766
12k
50R_100MHZ_3A
C802
40uH
C803
C795
L725
C796
50V
1n
100n
25V
N.C
C794
L726
50V
1n
100n
25V
1
C816
2
C815
100n
25V
C826
22u
22n
50V
C818
50V
10n
PL702
470n
63V
22u
STPS745 D904
D901
22u
470n
63V
C807
L729
4
C808
3
C820
S730
25V
1000u
2
C821
L109
MAIN_OUT_R
PL700
5
4
3
2
1
1
2
3
FEEDBACK
ON/OFF
4
5
GND
VIN
OUTPUT
IC708
MAIN_OUT_L
1
35V
470u
LM2576
PL701
S724
MUTE_3V3
S723
R771
1k
15V_AUD
BC848B
15V_AUD
40uH
L723
PL703
1
2
SM012
69
1
2
3
4
1
2
3
4
HP_L
HEADPHONE
HP_R
4n7
50V
3
BZT55C10
100p
50V
FRONT AV BOARD CIRCUIT
1
D107
C108
2
C109
100p
50V
L119
A
100p
50V
L120
BZT55C10
2
R106
4n7
50V
JK105
WHITE_FAV
JK106
WHITE_FAV
1
D108
D109
BZT55C10
BZT55C10
LINE_OUT_R
3
L117
4
PHJACK
L118
D106
R105
D105
L115
1
2
3
7
BZT55C10
L116
L113
L111
5
6
JK104
LINE_OUT_L
C107
R104
C106
LINE_OUT_SUB
L114
L112
A
HEADPHONE
HP_L
R103
R102
8
9
JK103
WHITE_FAV
HP_L
HP_R
HP_R
100p
50V
PL101
LINE_OUT_SUB
4
C105
PL105
LINE_OUT_L
BZT55C10
3
L110
D104
12
HEADPHONE
1
LINE_OUT_SUB
2
11
LINE_OUT_L
LINE_OUT_R
100p
50V
1
100p
50V
10
2
LINE_OUT_R
3
PL102
L108
A
9
FRONT_AUDIO_L
33p
50V
8
C104
L109
C103
8
R101
C102
FRONT_AUDIO_L
FRONT_AUDIO_L
1
7
FRONT_AUDIO_R
JK102
1P_RED_FAV
FRONT_AUDIO_R
7
6
5
D103
6
5
SVHS_Y
BZT55C10
FRONT_VIDEO
4
SVHS_C
2
4
R108
L106
1
3
L107
3
3
R107
R100
A
R110
2
FRONT_AUDIO_R
D102
2
JK101
YELLOW_FAV
SVHS_Y
SVHS_C
R109
FRONT_VIDEO
33p
50V
1
2
1
BZT55C10
L104
3
PL100
33p
50V
L105
4
PL104
C101
FRONT_VIDEO
C100
S101
S100
D101
1
PL103
BZT55C10
L102
D100
L103
1
600R_100MHZ_200mA
L100
BZT55C10
L101
2
SVHS_C
SVHS_Y
JK100
JK107
1P_RED_FAV
4P
A
A
3
2
3
1
C110
19.3. CIRCUIT BOARDS
1
3
2
6. IDTV Board 17DB23 (VS20252456)
1. Y-SUS Board (TS06288)
2. Power Board (VS30043468)
8
7
6
4&5
7. Main Board 17MB15-E5 (VS20251818)
4. Audio Board 18AMP05 (VS20217003)
8. Joint Board 17DB21 (VS20252456)
3. X-SUS Board (TS06287)
SM012
5. Filter Board 17FL2-02 (VS20225622)
CIRCUIT BOARDS
70
PCB LAYOUTS
PL101
X100
R122
IC102
R114
R112
R113
151R
601LP
KCT
603R
844R
744R
001X
201R
101R
814R 294C
TSRT
4203C
103C
8L
311C
632C
914R
034C
731C
531C
212C
L221
274C
PL202
484C
112C
004Z
014C
354C
004UT
L215
L218
L214
L222
L213
L212
L211
L210
L209
L208
004L
184C
C459
L216
L204
C406
R139
C255
C212
C211
R203
R204
R205
C203
R202
474C
334C
TSRCATJ
7L
654R
534C
11L
403C
211C
L220
L219
C200
C205
L205
634C
R125
531R
C252
Q120
C295
C236
R221
C202
D401
S513
C135
C137
R201 R290 L206 C205
R431 R432
103PT
ODT
303C
003C
584C
JOT
9L
121C
513C
R222 Q121
IC201
C116
C104
R231
604C
394C
C207
L217
L605
C457
C255
R213
D200
C275 C254
R214
R223 Q122
302LP
PL105
104C
C147
C109 C146
C204
L203
402C
501LP
D202
R216
R219
R225
R228
C225
R227
R230
C229
R220
R218
C221
TOP (COMPONENT) SIDE
PL103
PL103
17FAV15-2
PL100
PL102
PL102
R108
PL100
PL102
PL101
230805
R103
PL105
R104
L116 R105
L115
JK100
D107
JK101
R106 L120
L118
C109 L119
D108
L114
C105
PL105
R102
L110
L112
L111
L113
D106
D109
C110
C108 L117
104
R107
PL101
PL104
32-37XX
BOTTOM (SOLDER) SIDE
IDTV BOARD
R101 L109
L108
R100
L106
C106
D104
L103
L101
L100
C100
L104
D103
C101
L102
D100
C103 D102
C104
C107
S100
S103
L105
L107
C102
D101
JK104
JK105
UA
JK106
JK107
D105
JKI03
BOTTOM (SOLDER) SIDE
TOP (COMPONENT) SIDE
FRONT AV BOARD
PCB LAYOUTS
71
JK102
JK101
JK100
DNG
TUOVT
102LP
EULB
DNG
PL200
DNG
002LP
PL201
R210
R239
S400
504L
144R
C145
C213
Q207 Q204 Q205
R238 Q201
084C
NEERG
R262
R238
D206
R224
C214
R206
R215
R217 C223
C201
R295
Q203
PL203
C148
DER
C227
UA
854C
IC101
DNG
R212
R206
R263
C401
PL702
AMPLIFIER BOARD
SM012
503R
101LP
C122
R120
L112
C120
R740
R741
R742
R743
C22
D402
R452
R338 R339
C218
S514
C220
R232
C125
R307
R308
R403 Q400 R402
C491
L101
R450
C459
R405
R404
C102
L207
C405
D400
R104
Z400
L401
C414
R408
C402
R409
R401
C460
5MT
601R
001R
603C
L102
NIREGGIRT
303CI
251R
254C
R108
L103
R105 C131
L726
L725
R118
R119 C118
C305
C310
C307
C308
C312
C305
202LP
C257
L13
IC103
S301
R148
R159
C488
C408
R410
L411
C462
R413
C409
S515
C493
R400 Q403
C415
C412
R428
R470
S406 C464
R475
S402
L402
C446
C421
C489
R415 C463
R451
TUOREGGIRT
841R
321C
511C
301R
IC300
R550
R569
R553
C440
C473
Q402
733R
701L
R144
C404
Q401
633R
231C
684C
R115
784C
R407
L412
001X
301C
R127
R161
R449
C461
C464
C426
C416
R411 C420
413C
574C
PL100
R747
R102
S734
C807
C25
S1
L10
L113
V5.2
TU400
C808
R767 Q709
C818 S737
R766 C817
R756
D101
DNG
V33
71L
431C
D180
C114
C117
DNG
V21
35C
674C
C403
C802
C410
C776
S738
C778
C779
R742
C792
C411
C414
C831
C811
L722
C481
C472
C824
S736
S735
Q603
C794
C814
C813
IC902
C129
R510 R658
SDA C1
SDA C2
R459
R645 C601
S401
C456
C479
L719
C771
C783
C816
L404
C53
313C
R310
R300
R160
C127
C469
C491 IC401
R467
C429 C428
L400 C445
C37
C110
C132
C509
R146
R237
IC703
IC702
C781
Q710
S732
PL707
C438
R466 C439
R468
C423
R110 S2
R236 L826
R260
S733
IC708
C793
L721
C834
L718
C780
S725
L729
C826
C801
C821
PL700
C815
C788
C791
C789
C790
R746
R745
C825
R772
R754
C795
C786
Q715
S739
C787
C785 C786
04
Q6
R754
R500 Q600
R771
S7
24
R777
R776
C823
R773
R765
C820
R774
PL703
331C
C50
C124
C470
C782
R775
3.3V
L413
R660
SDA
R444
R443 C608 C651 R652
C422
X400 C434
L724
C806
C835
R755
L723
C437
L15
R128
R319
2.5V
R411
IC402
L727
C822
C714
R771
D904
D901
L610
121205
LF
C103
C128
C126
R662
R661
C119
C707
IC100
PL701
18AMP05-2
L727
L109
L904
C476
C485
R318
R137 C130
L105
L106
R747R746R745R744R312R311
C486
L623
L723
L724
PL741
C134
R631
R603
C510
C805
R532
L904
C835
R502
C806
C831
C828
C830
C832
D901
BOTTOM (SOLDER) SIDE
TOP (COMPONENT) SIDE
L16
C311
V5
C51
C111
R136
R657
V3.3
C52
R123
IC600
R659
L12
IC501
IC545
R604
C133
R530
IC648
C475
R59
R19
C603
C606
C605
C601
R775
C837
PL703
IC647
PL106
R121
S304
S302
C600
C602
R774
C811
C820
5V
101LP
14C
L111
L110
L119
L108
S305
C315
PL702
C805
C834
C877
C833
C829
C836
C821
PL700
L729
PL600
C604
006LP
VpRxD
L14 C256R136
IC5
R126
S303
C452
C822
VER:E2
18/06/04
L725
C61
R241
C807
PL707
17PING08
L726
19.4
FRONT AV BOARD
KEYPAD
INFRARED BOARD
19.4. CONNECTOR DIAGRAM
PL100
PL101
PL102
PL1
PL1
PL201
PL1002
PL301
PL606
PL600
PL203
MAIN BOARD
PL904
PL4
PL104
PL3
PL1
PL2
PL1
DAUGHTER BOARD
PL1001
PL701
PL702
PL903
PL707
PL703
PL700
PL902
PL103
PL901
PL1003
PL202
PL803
PL802
PL101
PL803
PL804
PL106
PL805
PL800
PL801
PL102
CN2
CN11
CN10
AMPLIFIER
BOARD
PL101
CN69
CN64
CN23
ON-OFF
SWITCH
PANEL
CONTROL UNIT
FILTER BOARD
CN32
SM012
IDTV MODULE
BOARD
POWER (SMPS)
BOARD
RIGHT
SPEAKER
PL100
DAUGHTER
BOARD
PANEL
CN24
AC INPUT
PL101
PL900
CN61
LEFT
SPEAKER
PL308
CONNECTOR DIAGRAM
72
CN26
PANEL DRIVER
CIRCUIT1
XSUS BOARD
PANEL DRIVER
CIRCUIT2
YSUS BOARD
CN42
ABUS-L
BOARD
THE UPDATED PARTS LIST
FOR THIS MODEL IS
AVAILABLE ON ESTA
Hitachi, Ltd. Tokyo, Japan
International Sales Division
THE HITACHI ATAGO BUILDING,
No. 15 –12 Nishi Shinbashi, 2 – Chome,
Minato – Ku, Tokyo 105-8430, Japan.
Tel: 03 35022111
HITACHI EUROPE LTD,
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire
SL6 8YA
UNITED KINGDOM
Tel: 01628 643000
Fax: 01628 643400
Email: consumer [email protected]
HITACHI EUROPE S.A.
364 Kifissias Ave. & 1, Delfon Str.
152 33 Chalandri
Athens
GREECE
Tel: 1-6837200
Fax: 1-6835964
Email: [email protected]
HITACHI EUROPE GmbH
Munich Office
Dornacher Strasse 3
D-85622 Feldkirchen bei München
GERMANY
Tel: +49-89-991 80-0
Fax: +49- 89-991 80-224
Hotline: +49-180-551 25 51 (12ct/min)
Email: HSE- [email protected]
HITACHI EUROPE S.A.
Gran Via Carlos III, 86, planta 5
Edificios Trade - Torre Este
08028 Barcelona
SPAIN
Tel: +34 93 409 2550
Fax: +34 93 491 3513
Email: [email protected]
HITACHI EUROPE srl
Via Tommaso Gulli N.39, 20147
Milano, Italia
ITALY
Tel: +39 02 487861
Tel: +39 02 38073415 Servizio Clienti
Fax: +39 02 48786381/2
Email: [email protected]
HITACHI Europe AB
Box 77 S-164 94 Kista
SWEDEN
Tel: +46 (0) 8 562 711 00
Fax: +46 (0) 8 562 711 13
Email: [email protected]
HITACHI EUROPE S.A.S
Lyon Office
B.P. 45, 69671 BRON CEDEX
FRANCE
Tel: +33 04 72 14 29 70
Fax: +33 04 72 14 29 99
Email: [email protected]
HITACHI EUROPE LTD (Norway) AB
STRANDVEIEN 18
1366 Lysaker
NORWAY
Tel: 67 5190 30
Fax: 67 5190 32
Email: [email protected]
HITACH EUROPE AB
Egebækgård
Egebækvej 98
DK-2850 Nærum
DENMARK
Tel: +45 43 43 6050
Fax: +45 43 60 51
Email: [email protected]
HITACHI EUROPE AB
Neopoli / Niemenkatu 73
FIN-15140 Lahti
FINLAND
Tel : +358 3 8858 271
Fax: +358 3 8858 272
Email: [email protected]
Hitachi Europe Ltd
Bergensesteenweg 421
1600 Sint- Pieters-Leeuw
BELGIUM
Tel: +32 2 363 99 01
Fax: +32 2 363 99 00
Email: [email protected]
HITACHI EUROPE LTD
Na Sychrove 975/8
101 27 Pr aha 10 – Bohdalec
CZECH REPUBLIC
Tel: +420 267 212 383
Fax: +420 267 212 385
Email: [email protected]
www.hitachidigitalmedia.com
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