MC33345 Datasheet From IC-ON-LINE.CN
 (M) MOTOROLA
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Lithium Battery Protection
Circuit for One to Four Cell
Battery Packs
The MC33345 is a monolithic lithium battery protection circuit that is
designed to enhance the useful operating life of one to four cell rechargeable
battery packs. Cell protection features consist of independently
programmable charge and discharge limits for both voltage and current with
a delayed current shutdown, cell voltage balancing with on-chip balancing
resistors, and a virtually zero current sieepmode state when the cells are
discharged. Additional features include an on—chip charge pump for reduced
MOSFET losses while charging or discharging a low cell voltage battery
pack, and the programmability for a one to four cell battery pack. This
protection circuit requires a minimum number of external components and is
targeted for inclusion within the battery pack. The MC33345 is available in
standard and low profile 20 lead surface mount packages.
e independently Programmable Charge and Discharge Limits for Both
Voltage and Current
Charge and Discharge Current Limit Detection with Delayed Shutdown
Cell Voltage Balancing
On-Chip Balancing Resistors
Virtually Zero Current Sleepmode State when Cells are Discharged
Charge Pump for Reduced Losses with a Low Cell Voltage Battery Pack
Programmable for One, Two, Three or Four Cell Applications
Minimum External Components for Inclusion within the Battery Pack
Available in Low Profile Surface Mount Packages
Typical F Four Cell Smart t Battery | Pack
r ” —
(+ |
Самос, Current Sense
| Current Limit [- Limit - — common Cure Limit |
| Cell Voltage
| Discharge Voltage $ À
| Threshold
4
Charge Voltage $
| Threshold
7
<
MC33345 жа
O 5 L
18) | Cell Voltage <
я Retum
Ground | | 1
|
16 | Test Input
Program 1 |
— | |"
11
Program 2 | Faulk Output
4
ML -———— —— д”
Charge Pump Y 14 Discharge} 13 8 9 Charge
Output Gate Drive Gate Drive
1 Qutput Common
This device contains 1808 active transistors.
MC33345
LITHIUM BATTERY
PROTECTION CIRCUIT
FOR
ONE TO FOUR CELL
SMART BATTERY PACKS
SEMICONDUCTOR
TECHNICAL DATA
DW SUFFIX
PLASTIC PACKAGE
CASE 751D
(SO-20L)
DTB SUFFIX
PLASTIC PACKAGE
CASE 948E
(TSSOP-20)
PIN CONNECTIONS
o
Cell Voltage Return | 1 20] Cell 3
Cell 4VC0/ | 2 19| Cell
Discharge Current Limit E Ce
Cell Voltage | 3 118] Cell INC
Discharge Voltage =
Threshold 4 17) Fault Output
Charge Voltage
Threshold L? 16] round
Current Sense В
Common 6 15) Test Input
Charge Current Limit [7 14] Charge Pump Output
Charge Discharge
Gate Drive Common В 13 Gate Dive Output
Charge
Gate Drive Output 12] No Connection
Program 2 [10 11] Program 1
(Top View)
ORDERING INFORMATION
Operating
Device Temperature Range | Package
MC33345DW SO-20L
Tp = —25° to +85°C
MC33345DTB TSSOP-20
3-316 ES 6367253 0100936 440 ME
MOTOROLA ANALOG IC DEVICE DATA
MC33345
MAXIMUM RATINGS
Ratings Symbol Value Unit
Input Voltage (Measured with Respect to Ground, Pin 16) VIR \
Cell Voltage Divider (Pins 1, 3, 4 and 5) 18
Cell 1/V (Pin 18) 75
Cell 2 (Pin 19) 10
Cell 3 (Pin 20) 18
Cell 4/Vco/Discharge Current Limit (Pin 2) 20
Current Sense Common (Pin 6) 30
Charge Current Limit (Pin 7) 30
Charge Gate Drive Common (Pin 8) +20
Charge Gate Drive Output (Pin 9) 18 to —20
Program 1 (Pin 11) 7.5
Program 2 (Pin 10) 7.5
Discharge Gate Drive Output (Pin 13) 18
Charge Pump Output (Pin 14) 12
Test (Pin 15) 7.5
Fault Output (Pin 17) 20
Cell Voltage Divider Current Idiv MA
Source Current (Pin 4 to 6) 0.5
Sink Current (Pin 5 to 16) 0.5
Fault Output Sink Current (Pin 17) Hit 10 mA
Thermal Resistance, Junction to Air ReJA °C/W
ОТВ Suffix, TSSOP—20 Plastic Package, Case 948E 135
DW Suffix, 50-20 Plastic Package, Case 751D 105
Operating Junction Temperature (Notes 1, 2 and 3) TJ —40 to +150 | °C
Storage Temperature Tstg —55 to +150 °C
NOTE: ESD data available upon request.
ELECTRICAL CHARACTERISTICS (Vcc (Pin 2) = 8.0 V, VC (Pin 18) = 4.0 V, Ta = 25°C, for min/max values Ta is the
operating junction temperature range that applies (Notes 2 and 3), unless otherwise noted.)
Characteristic Symbol | Min | Typ | Max | Unit |
VOLTAGE SENSING
Charge or Discharge Voltage Inputs (Pin 4 or 5 to Pin 1) |
Threshold Voltage Vth — 1.23 — \
Input Bias Current Bs - 20 — ПА
Input Hysteresis Source Current (Pin 5) IH - 2.0 - HA
Cell Charge or Discharge Programmable Input Voltage Range (Pin 4 or 5) VIR(pgm) — Vihto 7.5 — V
Cell Selector Series Resistance ©
Cell Positive to Top of Divider (Pin 2, 20, 19, or 18 to Pin 3} Rs — 100 —
Cell Negative to Bottom of Divider (Pin 20, 19, 18 or 16 to Pin 1) HS- - 100 —
Cell Voltage Sampling Rate '(smpl) - 1.0 — $
Test Input Threshold Voltage (Pin 15) Ут — VCell 12.0 - V
CELL VOLTAGE BALANCING
| Internal Balancing Resistance (Pins 2, 20, 19 and 18) Rbal | - | 140 | — | Q |
CURRENT SENSING
Charge Current Limit (Pin 7 to Pin 6}
Threshold Voltage Vth{chg) - 18 - my
Input Bias Current NB(chg) — 200 - nA
Delay ldly(chg) - 1.0 — s
NOTES: 1. Maximum package power dissipation limits must be observed.
2. Low duty cycle pulse techniques are used during test to maintain the junction temperature as close to ambient as possible.
3. Tested ambient temperature range for the MC33345:
Tow = 25°C Thigh = +85°С
MOTOROLA ANALOG IC DEVICE DATA ES 65367253 0100937 387 MA 3-317
MC33345
ELECTRICAL CHARACTERISTICS (continued) (Vcc (Pin 2) = 8.0 V, Vi (Pin 18) = 4.0 V, Ta = 25°C, for min/max values T is the
operating junction temperature range that applies (Notes 2 and 3), unless otherwise noted.)
Characteristic | Symbol | Min | Typ | Max | Unit |
CURRENT SENSING
Discharge Current Limit {Pin 2 to Pin 6)
Threshold Voltage Veh(dschg) - 50 — mV
Input Bias Current IIB(dschg) - 200 — na
Delay lly (dschg) - 3.0 = ms
CHARGE PUMP
| Output Voltage (Pin 14, Ry > 1010 9) vo | - | 102 | - | У |
TOTAL DEVICE
Average Cell Current Ice
Operating (Vo = 8.0 V) — 15 - LA
Sleepmode (Vec = 5.0 V) - 5.0 - nA
Minimum Operating Cell Voltage for Logic and Gate Drivers Vee V
Programmed for One Cell Operation
Cell 1 Voltage — 2.2 -
Programmed for Two, Three, or Four Cell Operation
Cell 1 Voltage — 1.5 —
Cell 2, Cell 3, or Cell 4 Voltage, Sum Voltage of Cells — 0.7 -
NOTES: 1. Maximum package power dissipation limits must be observed.
2. Low duty cycle pulse techniques are used during test to maintain the junction temperature as close to ambient as possible.
3. Tested ambient temperature range for the MC33345:
Tlow = -25%C Thigh = +85°C
3-318 EN 1367253 0100538 213: NN MOTOROLA ANALOG IC DEVICE DATA
MC33345
PIN FUNCTION DESCRIPTION
Pin Symbol Description
1 Cell Voitage Return The bottom side of a three resistor divider string connects to this pin. The Cell Selector internally
switches this point to the negative terminal of the cell that is to be monitored.
2 | Cel 4Ncg/ This is a multifunction pin that connects to a high impedance node of the Cell Selector where it is used to
Discharge Current Limit | monitor the positive terminal of Cell 4 and to provide positive supply voltage for the protection IC. This pin
is also used to monitor the voltage drop across the discharge current limit resistor and it provides a
discharge path for the internal balancing of Cell 4.
3 Cell Voltage The top side of a three resistor divider string connects to this pin. The Cell Selector internally switches
this point to the positive terminal of the cell that is to be monitored.
4 Discharge Voltage The upper tap of a three resistor divider string connects to this pin. The Cell Voltage Detector compares
Threshold the divided down cell voltage to an internal reference. If the comparator detects that the cell voltage has
fallen below the programmed level, discharge switch Q2 is disabled, and the protection circuit enters into
a low current sleepmode state. This prevents further discharging of the battery pack.
5 Charge Voltage The lower tap of a three resistor divider string connects to this pin. The Cell Voltage Detector compares
Threshold the divided down cell voltage to an internal reference. if the comparator detects that the cell voltage has
risen above the programmed level, charge switch Q1 is disabled, preventing further charging of the
battery pack. A 2.0 pA current source pull-up is internally applied to this pin creating input hysteresis.
6 Current Sense Common | This pin is a common point that is used to monitor the voltage drop across the charge and discharge
current limit resistors.
Charge Current Limit This pin is used to monitor the voltage drop across the charge current limit resistor.
8 Charge Gate Drive This pin provides a gate turn—off path for charge switch Q1. The charge switch source and the baitery
Common pack negative terminal connect to this point.
9 Charge Gate Drive This output connects to the gate of charge switch Q1 allowing it to enable or disable battery pack
Output charging.
10 | Program 2 This pin is used in conjunction with Pin 11 to program the number of cells.
11 Program 1 This pin is used in conjunction with Pin 10 to program the number of ceils.
12 | No Connection This pin is not internally connected.
13 | Discharge Gate Drive This output connects to the gate of discharge switch Q2 allowing it to enable or disable battery pack
Output discharging.
14 | Charge Pump Output This is the charge pump output. A reservoir capacitor is connected from this pin to ground.
15 | Test Input This input is used to facilitate circuit testing and is normally not connected. It has an internal 2.0 k pull-up
resistor.
16 | Ground This is the protection IC ground and all voltage ratings are with respect to this pin.
17 | Fault Qutput This is on open drain output that is active low when a charging fault limit has been exceeded. The limits
sensed are both charge voltage and current.
18 | Cell 1VG This is a multifunction pin that connects to a high impedance node of the Cell Selector where it is used to
monitor the positive terminal of Cell 1 and the negative terminal of Cell 2. This pin also provides logic
biasing and a discharge path for the internal balancing of Cell 1,
19 | Cell 2 This pin connects to a high impedance node of the Cell Selector where it is used to monitor the positive
terminal of Cell 2 and the negative terminal of Cell 3. This pin also provides a discharge path for the
internal balancing of Cell 2.
20 | Cell 3 This pin connects to a high impedance node of the Cell Selector where it is used to monitor the positive
terminal of Cell 3 and the negative terminal of Cell 4. This pin also provides a discharge path for the
internal balancing of Cell 3.
MOTOROLA ANALOG IC DEVICE DATA
EN 6367253 0100939 157 EM 3-319
MC33345
INTRODUCTION
The insatiable demand for smaller lightweight portable
electronic equipment has dramatically increased the
requirements of battery performance. Batteries are expected
to have higher energy densities, superior cycle life, be safe in
operation and environmentally friendly. To address these high
expectations, battery manufacturers have invested heavily in
developing rechargeable lithium-based cells. Today's most
attractive chemistries include lithium—polymer, lithium—ion,
and lithium-metal. Each of these chemistries require
electronic protection in order to constrain cell operation to
within the manufacturers limits.
Rechargeable lithium-based cells require precise charge
and discharge termination limits for both voltage and current
in order to maximize cell capacity, cycle life, and to protect
the end user from a catastrophic event. The termination limits
are not as well defined as with older non—lithium chemistries.
These limits are dependent upon a manufacturer's particular
lithium chemistry, construction technique, and intended
application. Battery pack assemblers may also choose to
enhance cell capacity at the expense of cycle life. In order to
address these requirements the MC33345 was developed.
This device features programmable voltage and current
limits, cell voltage balancing, low operating current, a virtually
zero current sleepmode state, and requires few external
components to implement a complete one to four cell smart
battery pack.
OPERATING DESCRIPTION
The MC33345 is specifically designed to be placed in the
battery pack where it is continuously powered from either one,
two, three, or four lithium cells. In order to maintain cell
operation within specified limits, the protection circuit senses
both cell voltage and current, and correspondingly controls the
state of two N-channel MOSFET switches. These switches,
Q1 and Q2, are placed in series with the negative terminal of
Cell 1 and the negative terminal of the battery pack.
Figure 1. Simplified Four Cell Smart Battery Pack
— - —
| "еее Рот) ;
——— 9 AN
Cell 4 |
+
| RI
Cell 3 го! |
i |
o R2
a ol |
: | MC33345
T 5
x — je
18 |
Т
= | 1
+ à |
el ho
| > 115
Discharge
- Charge
A MosfETO2
MOSFET Qf
8-320 EN 6367253 0100940
This configuration allows the protection circuit to interrupt
the appropriate charge or discharge path FET in the event
that a programmed voltage or current limit for any cell has
been exceeded.
A functional description of the protection circuit blocks
follows. Refer to the detailed block diagram shown in
Figure 6.
Voltage Sensing
Individual cell voltage sensing is accomplished by the use
of the Cell Selector in conjunction with the Floating
Over/Under Voltage Detector and Reference block. The Cell
Selector applies the voltage of each cell across an external
resistor divider string that connects from Pins 3 to 1. The
voltage at each of the tap points is sequentially polled and
compared to an internal reference. If a limit has been
exceeded, the result is stored in the Over/Under Data Latch
and Control Logic block. The Cell Selector is gated on for an
8.0 ms period at a one second repetition rate. This low duty
cycle sampling technique reduces the average load current
that the divider presents across each cell, thus extending the
useful battery pack capacity. The cells are sensed in the
following sequence:
Figure 2. Cell Sensing Sequence
971 E
Polling Time Cell Tested
Sequence (ms) Sensed Limit
1 1.0 Cell 4 Overvoltage
2 1.0 Cell 3 Overvoltage
3 1.0 Cell 2 Overvoltage
4 1.0 Cell 1 Overvoltage
5 1.0 Cell 4 Undervoitage
6 1.0 Cell 3 Undervoltage
7 1.0 Cell 2 Undervoltage
8 1.0 Cell 1 Undervoltage
By incorporating this polling technique with a single
floating comparator and voltage divider, a significant
reduction of circuitry and trim elements is achieved. This
results in a smaller die size, lower cost, and reduced
operating current.
Figure 3. Cell Voltage Limit Programming
on |
fom Cell Volta
Cell age
Selector | 3
, Discharge Voltages A1
Floating Threshold +
Over/Under 4
Cell Voltage | Cell
Charge Voltage R2
Detector | Threshold Voltage
Reference 5 =
| Cell Voltage R3
To | Retum
Cell /
Selector 1
The cell charge and discharge voltage limits are controlled
by the values selected for the resistor divider string and the
1.23 V input threshold of Pins 4 and 5. As the battery pack
reaches full charge, the Cell Voltage Detector will sense an
overvoltage fault condition on the first cell that exceeds the
programmed overvoltage limit. The fault information is stored
MOTOROLA ANALOG IC DEVICE DATA
MC33345
in a data latch and charge MOSFET Q1 is turned off,
disconnecting the battery pack from the charging source. An
internal 2.0 LA current source pull-up is then applied to Pin 5
creating an input hysteresis voltage. As a result of an
overvoltage fault, the battery pack is available for
discharging oniy.
The overvoltage fault is reset by applying a load to the
battery pack. As the voltage across each cell falls below the
input hysteresis level, charge MOSFET Q1 will turn on. The
battery pack will now be available for charging or
discharging. The over voltage limit and hysteresis voltage are
given by:
V a1- Rs Ps)
ov = Vth (Pin 5) R3
Vy = IH (Pin 5)(R1 + R2)
As the load eventually depletes the battery pack charge,
the Cell Voltage Detector will sense an undervoltage fault
condition on the first cell that falls below the programmed
undervoltage limit. After an undervoltage cell is detected,
discharge MOSFET Q2 is turned off, disconnecting the
battery pack from the load. The protection circuit will now
enter a low current sleepmode state drawing just 5.0 nA
typically, thus preventing any further cell discharging. As a
result of the undervoltage fault, the battery pack is available
for charging only. The undervoltage limit is given by:
(E! + R2 + na)
UV th (Pin 4) RZ + R3
The undervoltage fault is reset by applying charge current
to the battery pack. When the voltage on Pin 16 exceeds
Pin 8 by 0.6 V, discharge MOSFET Q2 will turned on. The
battery pack will now be available for charging or discharging.
Since the thresholds of Pins 4 and 5 are equal, the above
equations can be rewritten to directly solve for specific
resistor values as shown in the example below.
Let the desired limits be:
Voy = 4.2 V, VH = 0.4 V, and Vyy = 2.5 V
With nominal values for:
Vih = 1.23 V, and iH = 2.0 нА
(3) >)
Vin, =V
ва = _ = 82,828 ©
3 V (22 _
_OV _ 4 1.23
Vin
Vov 4.2
re = 63 | 2 _ 1) = 82808 (42 _ 1) = 56,323 Q
V 25
UV
Vy 0.4
в1 = | |-вг = (— 24— |-56,323 = 143,077 ©
H 2,0 x 1076
Note that the Cell Selector has a typical total series
resistance of 200 Q. This will have a minimal effect on the
programmed limits if the total divider resistance is in excess
of 100 ka.
Cell Voltage Balancing
With series connected cells, successive charge and
discharge cycles can result in a significant difference in cell
voltage with a corresponding degradation of battery pack
MOTOROLA ANALOG IC DEVICE DATA
capacity. Figure 4 illustrates the operation of an unbalanced
two cell pack. As the cells become unbalanced, the full
battery pack capacity is not realized. This is due to the
requirement that charging must terminate when Cell 2
reaches the overvoltage limit, and discharging must
terminate when Cell 1 reaches the undervoltage limit. By
employing a method of keeping the cell voltages equal, both
cells can be charged and discharged to their specified limits,
thus attaining the maximum possible capacity .
Figure 4. Unbalanced Battery Pack Operation
+1 | 4 42V 1
—T | 4 Overvoltage < Charge 27 VE
\ | 4 Limit 1
+1 4 25V 1
-T | j40v Dag Undervoltage $
— 1 Limit 1
Charged Discharged
The MC33345 contains a Cell Voltage Balancing Logic
circuit that controls four N—channel MOSFETs. The circuit
samples the voltage of each cell during the polling period. If
all of the cells are below the programmed overvoltage fault
limit, no cell balancing takes place. If one or more cells
reach the overvoltage fault limit, a specific latch is set for
each cell. At the end of the polling period, charge
MOSFET Q1 is turned off and the latches are interrogated. If
all of the latches were set, no cell balancing takes place. If
one, two, or three latches were set, the required cell
balancing MOSFETs are then activated. The overvoltage
cells are discharged to the programmed level of Voy - VH.
As each cell attains this level, the discharge MOSFETs
successively turn off. Upon completion of cell balancing,
charge MOSFET Q1 is turned on. Cell voltage balancing is
active during charge and discharge, but disabled during the
low current sieepmode state.
Cell Programming and Test
The protection circuit can be programmed for operation
with either one, two, three, or four cell battery packs.
Programming inputs 1 and 2 are used to set up the internal
logic for the number of cells to be monitored. If less than
four cells are required, the input for each empty cell position
must be connected to Voi. This process starts with Cell 4
decending down to Celi 2 if required. Refer to the Cell
Programming table shown below and the specific
application figure.
Figure 5. Cell Sensing Sequence
Number of Program 1 Program 2 Application
Cells (Pin 11) (Pin 10) Figure
1 Ground Cell 1Vc 16
2 Cell 17VC Ground 15
3 Cell 1NC Cell 1/7VC 14
4 Ground Ground 13
EN 6367253 0100941 808 MM 3-321
MC33345
A test option is provided to speed up device and battery
pack testing. By connecting Pin 15 to ground, the internal
logic is held in a reset state and both MOSFET switches are
turned on. Upon release, the Control Logic becomes active
and the cells are polled within 8.0 ms.
Current Sensing
Charge and discharge current limit protection can be
selectively added to the battery pack with the addition of a
sense resistor. The resistors are placed in series with the
positive terminal of the battery pack and the cells. Refer to
Figure 1.
As the battery pack charges, Pins 6 and 7 sense the
voltage drop across RLim(chg) A charge current limit fault is
detected If the voltage at Pin 7 exceeds Pin 6 by 18 mV for
the entire delay period of 1.0 second. The fault information is
stored in a data latch and charge MOSFET Q1 is turned off,
disconnecting the battery pack from the charging source. As
a result of the charge current fault, the battery pack is
available for discharging only. The charge current limit is
given by:
Vinchg) _ 18 mv
Rlimichg) PLim(chg)
The charge current fault is reset by either disconnecting
the battery pack from the charger, or by connecting a load to
the battery pack. When the voltage on Pin 16 no longer
exceeds Pin 8 by approximately 2.0 V, the Sense Enable
circuit will turn on charge MOSFET Q1. Charge current
sensing can be disabled by connecting Pin 7 to Pin 6.
The discharge current limiting operates in a similar
manner. As the battery pack discharges, Pins 2 and 6 sense
the voltage drop across R|_im(dschg)- A discharge current limit
fault is detected if the voltage at Pin 2 is less than Pin 6 by
50 mV for more than 3.0 ms. The fault information is stored in
a data latch and discharge MOSFET Q2 is turned off,
disconnecting the battery pack from the load. As a result of
the discharge current fault, the battery pack is available for
charging only. The discharge current limit is given by:
Lim(chg) =
The discharge current fault is reset by either disconnecting
the load from the battery pack, or by connecting the battery
pack to the charger. When the voltage on Pin 8 no longer
exceeds Pin 16 by approximately 2.0 V, the Sense Enable
circuit will turn on discharge MOSFET Q2. Discharge current
sensing can be disabled by connecting Pin 2 to Pin 6.
The charge and discharge current protection circuits
contain a built in response delay of 1.0 s and 3.0 ms
respectively. This helps to prevent fault activation when the
battery pack is subjected to pulsed currents during charging
or discharging.
Charge Pump and MOSFET Switches
The MC33345 contains an on chip Charge Pump to
ensure that the MOSFET switches are fully enhanced for
reduced power losses. An external reservoir capacitor
normally connects from the Charge Pump output to ground,
Pins 14 and 16. The capacitor value is not critical and is
usually within the range of 10 nF to 100 nF. The Charge
Pump output is regulated at 10.2 V allowing the use of
economical logic level MOSFETs in one and two cell
applications. The main requirement in selecting a particular
type of MOSFET switch is to consider the desired
on-resistance at the lowest anticipated operating voltage of
the battery pack. A table of small outline surface mount
devices is given in Figure 6. When using extremsly low
threshold MOSFETs, it may be desirable to disable the
Charge Pump so that the maximum gate to source voltage is
not exceeded. This is accomplished by connecting Pin 14 to
Pin 19 with two, three, or four cell battery packs.
Battery Pack Application
Upon assembly of the battery pack, it is imperative that
Cell 1 be connected first so that V¢ is properly biased. The
remaining cells can then he connected in any order. This
assembly method prevents forward biasing the protection IC
substrata which can result in overheating and
non-functionality.
Each of the application figures show a capacitor labeled
CEsp. This capacitor provides a path around the MOSFET
овен _ ‘мазо - 50 mV Switches in the event of an electrostatic discharge.
Lim(dschg) Lim(dschg)
Figure 6. Small Outline Surface Mount MOSFET Switches
Device On-Resistance (£) versus Gate to Source Voltage (V)
Type 25V 3.0 V 4.0 V 5.0 V 6.0 V 7.5 \ 9.0 V
MMFT3055VL — - - 0.120 0.1150 0.108 Q 0.100 M
MMDFSNOSHD - 0,525 Q 0.080 © 0.065 © 0.063 Q 0.062 Q 0.060 Q
MMOF4N01HD 0.047 © 0.042 © 0.037 Q 0.035 Q 0.034 Q 0.033 @ See Note
MMSF5NO2HD - 0.065 @ 0.023 Q 0.021 © 0.020 Q 0.018 © 0.018 2
MMDF6N02HD 0.043 Q 0.035 Q 0.028 Q 0.028 Q 0,026 N 0.025 © 0.023 €
NOTE: Exceeds maximum Vas voltage rating.
3-322
EN 65367053 0100942 744 MM
MOTOROLA ANALOG IC DEVICE DATA
MC33345
PROTECTION CIRCUIT OPERATING MODE TABLE
Outputs
MOSFET Switches Function
Cell
Input Conditions Circuit Operation Charge | Discharge | Charge | Balancing
Cell Status Battery Pack Status Q1 Q2 Pump | (See Note)
CELL CHARGING/DISCHARGING
Storage or Nominal Operation: Both Charge MOSFET Q1 and Discharge MOSFET On On Active Active
No current or voltage faults Q2 are on. The battery pack is available for charging
or discharging.
CELL CHARGING FAULT/RESET
Charge Current Limit Fault: Charge MOSFET Q1 is fatched off and the cells are On to Off On Active Active
VPin 7 2 (pin 6 + 18 mV) disconnected from the charging source. Q1 will remain
for1.0s in the off state as long as Vpin 1g exceeds Vpjn 11 by
= 2.0 V. The battery pack is available for discharging.
Charge Current Limit Reset: The Sense Enable circuit will reset and turn on charge | Off to On On Active Active
VPin 16 - VPin 8 < 2.0 V MOSFET Q1 when Vpin 16 no longer exceeds Vpin 11
by = 2.0 V. This can be accomplished by either dis-
connecting the charger from the battery pack, or by
connecting a load to the battery pack.
Charge Voltage Limit Fault: Charge MOSFET Q1 is latched off and the cells are On to Off On Active Active
VPin 5 = 1.23 V for 1.05 disconnected from the charging source. An internal
current source pull-up of 2.0 pA is applied to Pin 8
creating an input hysteresis voltage of VH with divider
resistors R1 and R2. The battery pack is available for
discharging.
Charge Voltage Limit Reset: Charge MOSFET Q1 will turn on when the voltage Off to On On Active Active
Vpins<1.23Vfor1.0s across each cell fails sufficiently to overcome the in-
put hysteresis voltage. This can be accomplished by
applying a load to the battery pack.
CELL DISCHARGING FAULT/RESET
Discharge Current Limit Fault: Discharge MOSFET Q2 is latched off and the cells On On to Off Active Active
VPin 6 € (VPin 2 - 50 mV) are disconnected from the load. Q2 will remain in the
for 3.0 ms off state as long as Vpin 41 exceeds Vpin 16 by = 2.0 Y.
The battery pack is available for charging.
Discharge Current Limit Reset: | The Sense Enable circuit will reset and turn on dis- On Off to On Active Active
VPin 8 - VPin 16 < 2.0V charge MOSFET Q2 when Vpin 11 no longer exceeds
VPin 16 by = 2.0 V. This can be accomplished by sither
disconnecting the load from the battery pack, or by
connecting the battery pack to the charger.
Discharge Voltage Limit Fault: Discharge MOSFET Q2 is latched off, the cells are On Onto Off | Disabled | Disabled
Vpin4< 1.23 V tor 1.0s disconnected from the load, and the protection circuit
enters a low current sleepmode state. The battery
pack is available for charging.
Discharge Voltage Limit Reset: | The Sense Enable circuit will reset and turn on dis- On Off to On Active Active
Vein 16 > (VPing + 0.6 V) charge MOSFET Q2 when Vpjn 1g exceeds Vpjn g by
0.6 V. This can be accomplished by connecting the
battery pack to the charger.
FAULTY CELL
Simultaneous Charge and This condition can happen if there is a defective cell in | Cycles Cycles Cycles Cycles
Discharge Voltage Limit Faults: | the battery pack, The protection circuit will remain in Cell 1 Cell 1 Cell 1 Cell 1
VPin 5 2 1.23 V for 1.0 s and the slespmode state until the battery pack is con- Good Good Good Good
Vpin 4< 1.23 V far 1.0s nected to a charger. If Cell 2, 3, or 4 is faulty anda
charger is connected, the protection circuit will cycle | Disabled | Disabled | Disabled | Disabled
in and out of sleepmode. If Cell 1 is fauity (<1.5 V), Cell 1 Cell 1 Cell 1 Cell 1
the protection circuit logic will not function and the Faulty Faulty Faulty Faulty
battery pack cannot be charged.
NOTE: Cell balancing is not active when programmed for one ceil operation.
Ea
MOTOROLA ANALOG IC DEVICE DATA 6367253 0100943 680 MA 3-323
MC33345
Figure 7. Four Cell Smart Battery Pack
ALim(dsch RLim(eh
( y 9) E me 9.
Current Sense Charge Current
E Common 9 6 — _ 79 Limit __,
Cell 4/V | |
Dish Charge/Discharge |
Current Limit | Overcurrent Detector |
| |
2
| 140 A _ Col Voltage
cala! a : D parge Votage Êr1 |
OT scharge Voltage $ R1 $
20 Floating hreshold 1 4
| wg Over/Under [= 4
| < Cell Voltage 4 e 1
Cell 2 F Cell Detactor Charge Voltage SR2 $
© « Selector & Threshold 1
19] 4 Reference 5 dd
x Cell Voltage SR3 §
Call ING | < Return ;
ml A |
18 wg Me |
Y
20k
Ground e | ii» e jeans Input
16| = 7 MT Over/Under 115
Program 1 | | Peta Latah | Fault Output
mi Cell Voltage Control Logic | | Ш
Program 2 | Balancing |e = |
al Logic
10 | 9 ) |
| | Sense | |
or] Ck | En Enable | |
| Charge/Discharge T |
| Oscillator —» Charge Pump Gate Drivers = |
| |
Las es as — — — — — —— —— = — 4 — — od
Charge Pump Ÿ 14 Discharge 8 Charge
Output Gate Drive Gate Drive
+ Output Common
Co Charge |
Discharge Switch
Switch Q2 Q1
if
TX
С
\ “ESD
EN 63672053 0100944 517 IM
3-324 MOTOROLA ANALOG IC DEVICE DATA
MC33345
Figure 8. Three Cell Smart Battery Pack
(
1 ALim(dschg) RLim(chg)
AA «il AA di.
Current Sense Charge Current
_ MESS command 6 _ 70 Limit _
| 1
Cell 4/V
Disco | Charge/Discharge |
Current Limit | Overcurrent Detector |
€
2 : |
| чо N _ | Cell Voltage
сз! E | y |3 1
—o | | Discharge Voltage 3 R1 $
oo Over/Under [= 1
Cell 3| | | Cell Voltage 4 1
; Cell 2 | o Cell Detector | Charge Voltage R2 4
© Selector & | Threshold 1
= 19] 4 3 Reference | Is 1
Cell 2] tL. | | Cell Voltage R3 4
To | g 1
о Cell ING | а 1 < | Return 1
— "8 | wg Go| |
Cell 1 + | | . ОК | |
o Ground р _ Ls <— * 1 Test Input
16 | = x TT™ Over/Under | 15 |
| Program 1 | | Data Latch | Fault Output |
"| Cell Voltage Control Logic | | " f
Program 2 | Balancing = |
nl Logic À
ю | : 1 |
| Sense | | E
| Ck Pr | Enable | | i
| Charge/Discharge | | ; }
| Oscillator Charge Pump Gate Drivers < = | |
- = — as Jr te ve ve co pm es rs fs me
Charge Pump Ÿ 14 Discharge 9 13 Charge? 9 8 Charge
Output Gate Drive Gate Drive Gate Drive
+ Output Output Common
Co Charge
Discharge Switch
Switch Q2/ T X AT \_Q1 _
IL
a
E 6367253 0100945 453 IN
MOTOROLA ANALOG IC DEVICE DATA 3-325
MC33345
Figure 9. Two Cell Smart Battery Pack
RLim(dschg) ~~ BLim(chg)
Current Sense Charga Current
— Common 9 6 70 Umit _
се! Ус)! |
AE | Charge/Discharge |
Current Limit | Overcurrent Detector |
‹ |
| Й _ | Cell Voltage
Cell 3 Р | y la | E
© Floating | Discharge Voltage sn
hreshold
| < Cell Voltage 4
Cell 2 7 Cel Detector | Charge Voltage R2 §
© Selector 8 + | Threshold I
19 U Reference | 5 |
Ceil 2 + | | Cell Voltage R3
—J caw! E ir. Return |
Ш 1
18 wg vo |
Cell 1 | | ок |
Ground р. +> fed, Input
16 = x ; 1” OverUnder [15
Program 1 Dele catch | Fault Output
N Cell Voltage | Control Logic |__| | 17
Program 2 | Balancing =
10 | Logic |
| |
| | | Sense | |
| | Ck E Enable | |
| Charge/Discharge T |
| Oscillator |-# Charge Pump | Gate Drivers = |
| |
| — — _— — a —]—— — m a)
Charge Pump 6 14 Discharge 8 © Charge
Output Gate Drive Gate Drive
+ Output Common
бо 7 Charge
Discharge Switch
Switch Q2/ T F AT) ©! (_
If
JA
\, CESD
ES 6367253 0100946 397 IM
3-326 MOTOROLA ANALOG IC DEVICE DATA
MC33345
Figure 10. One Cell Smart Battery Pack
(
RLim(dschg) BLim{chg)
A v a : AAA ”
Current Sense Charge Current
ee Commn9 6 —_ 76m _
Cell 4g | |
Discharge Charge/Discharge |
Current Limit | Overcurrent Detector |
|
| |
| . _ | Cell Voltage
ca3l E | y |3 |
o | Discharge Voltage 3 Ai À
200 140 Floating | Threshold 1
| Over/Under |3 E
Cell Voltage E
Cell 2 | | Cel Detector | Charge Voltage R2
> | Selector & _ | Threshold
19] 4 к Reference | 5 {
| Cell Voltage R3 $
Cell ic | (а | {| Return 1
oH |,
18 wg vo |
| | |
La 2.0k
Ground | р + jo apa
16 | = X f 11 OverUnder [15
Program 1 | | Data aten | Fault Output
"| Cell Voltage Control Logic 5 | 17
Program 2 | Balancing = |
al Logic
| Sense | |
| Ck | Ck [En ÿ Enable | |
| Charge/Discharge |, 1 |
| Oscillator | Charge Pump IN Gate Drivers < = |
| |
RR — = —— + — —
Charge Pump § 14 Discharge Charge? 9 89 Charge
Output Gate Drive Gate Drive
+ Qutput Common
CO Charge
Discharge Switch
Switch Q2/ T 4 Q1
If
It
EN 6357053 0100947 ccb IN
MOTOROLA ANALOG IC DEVICE DATA 3-327
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