Wireless Power Transmitter for ≤3W
Applications
Description
Features
The P9235A-R is a 3W, magnetic induction, wireless power
transmitter for low power applications. The system-on-chip
operates with an input voltage range of 4.5 – 5.5V while
integrating micro-controller, voltage regulation, over-current
protection, full bridge power stage drivers and on-chip
simultaneous voltage and current demodulation.
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The transmitter includes industry-leading 32bit ARM® Cortex®M0 processor offering a high level of programmability, while
consuming extremely low standby power. The device features
two LED outputs with pre-defined user programmable blinking
patterns, buzzer and programmable over-current protection
supporting wide range of applications. The I2C serial
communication allows the user to read back information such as
voltage, current, frequency and fault conditions. Together with the
P9027LP-R receiver, the P9235A-R is a complete wireless power
system solution.
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The P9235A-R is available in a Pb-free, space-saving VFQFN 5
mm X 5 mm, 40 pin package. The product is rated over an
operating temperature range of -40ºC to +85ºC.

P9235A-R
Datasheet
VIN range: 4.5 - 5.5 V
Supports receiver for up to 3W of power transfer
80% peak efficiency (when coupled with P9027LP receiver)
Integrated power stage drivers
Low standby power
Simultaneous voltage and current demodulation
Integrated 32 bit ARM® Cortex®-M0 Processor
Supports I2C interface for field programmability
Programmable current limit
Over-Current and Over-Temperature protection
Active low enable pin for electrical on/off
Pre-defined programmable LED patterns
Dedicated remote temperature sensing
-40ºC to +85ºC ambient operating temperature range
VFQFN 5mm X 5mm, 40 pin package
Typical Applications
Smart Watches
 Headsets
 Health and Fitness monitors


Portable Medical applications
Figure 1. Application Diagram
VIN
RSENSE
V_BRIDGE
4.5V -5.5V
LED_RED
LED_GRN
ISNS_IN
EN
ISNS_L
ISNS_OUT
On
VIN
Off
Discrete
R,C Filter 1
ISNS_H
LDO33
GH_BRG1
GL_BRG1
VO_5
GH_BRG2
SW_B
VIN_LDO
P9235A-R
GL_BRG2
LDO33
LDO18
Resistor
dividers
© 2016 Integrated Device Technology, Inc
LDO18
VSNS
SDA
SCL
ILIM
LED_PAT
RSVD1
RSVD2
Discrete
R,C Filter 2
LDO18
TS
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May 17, 2016
P9235A-R Datasheet
Absolute Maximum Ratings
These absolute maximum ratings are stress ratings only. Stresses greater than those listed in Table 3, 4 and 5 may cause permanent
damage to the device. Functional operation of the P9235A-R at absolute maximum ratings is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect long-term reliability.
Table 1. Absolute Maximum Ratings Summary (All voltages are referred to ground.)
Pins
EN
¯¯ , VIN, SW_B, VBRG_IN, SW_BRG1, SW_BRG2, ISNS_H, ISNS_L, BST_BRG1, BST_BRG2, GH_BRG1,
GH_BRG2
VO_5, VO_33, VIN_LDO, LED_GRN, LED_RED, VDDIO, GPIO_A4, GPIO_B2, GPIO_B3, RSVD1, RSVD2,
SCL, SDA, ILIM, LED_PAT, TS, BUZ, GL_BRG1, GL_BRG2, VSNS_IN, ISNS_IN, ISNS_OUT, VDRV_IN
GND_S, GND_BRG, VSNS_GND, GND_B, EPGND
Rating
Units
-0.3 to 28
V
-0.3 to 6
V
+0.3
V
-0.3 to 2
V
LDO18
Thermal Characteristics
Table 21,2,3. Package Thermal Characteristics
Symbol
Description
QFN Rating
Units
ΘJA
Thermal Resistance Junction to Ambient
28.5
C/W
ΘJC
Thermal Resistance Junction to Case
21.87
C/W
ΘJB
Thermal Resistance Junction to Board
1.27
C/W
TJ
Operating Junction Temperature
-40 to +125
C
TA
Ambient Operating Temperature
-40 to +85
C
TSTG
Storage Temperature
-55 to +150
C
TLEAD
Lead Temperature (soldering, 10s)
+300
C
Notes:
1.
The maximum power dissipation is PD(MAX) = (TJ(MAX) - TA) / θJA where TJ(MAX) is 85°C. Exceeding the maximum allowable power
dissipation will result in excessive die temperature, and the device will enter thermal shutdown.
2.
This thermal rating was calculated on JEDEC 51 standard 4-layer board with dimensions 3” x 4.5” in still air conditions.
3.
Actual thermal resistance is affected by PCB size, solder joint quality, layer count, copper thickness, air flow, altitude, and other
unlisted variables.
Table 3. ESD Information
Test Model
HBM
CDM
Pins
All pins
All pins.
© 2016 Integrated Device Technology, Inc
2
Ratings
Units
+/- 2000
+/- 500
V
V
May 17, 2016
P9235A-R Datasheet
Electrical Characteristics
Table 4. Device Characteristics
VIN = 5 V, VDDIO = 3.3 V, EN
¯¯ = 0V, LP= 6.5 µH, CP = 400 nF TA = -40C to +85C. Typical values are at 25°C, unless otherwise noted.
Symbol
Description
Conditions/Notes
Min
Typical Max
Units
Input Supplies and UVLO
VIN
Input Operating Range
4.5
5.0
5.5
VIN_UVLO_FW
Firmware Controlled UnderVoltage Lockout.
VIN Rising
4.3
V
ISTD_BY2
ISHD
Standby Mode Current
Shutdown Current
Periodic ping
ENB = VIN
12
25
mA
µA
80
V
Enable - EN
¯¯
VOH_ENB
Output logic high
VOL_ENB
Output logic low
2.0
V
0.25
V
Buck Converter1,2 - COUT=10µF; L=4.7µH
VOUT
IOUT
Buck Output Voltage
Output Current
VIN>5.5V
5
50
V
mA
CL= 3nF; 10 – 90%, 90 – 10%
50
150
ns
CL= 3nF; 10 – 90%, 90 – 10%
150
300
ns
N-Channel MOSFET Drivers
TLS_ON_OFF
THS_ON_OFF
Low Side Gate Drive Rise & Fall
times
High Side Gate Drive rise & Fall
times
Input Current Sense
VSEN_OFST
Amplifier offset voltage
Measured at ISNS_OUT pin;
ISNS_H=ISNS_L
0.6
ISENACC_TYP
Measured Current sense
accuracy
VR_ISEN=25mV, I=1.25A
±3.5
V
%
Analog to Digital Converter
N
Channel
VIN,FS
LDO181,2
Resolution
Number of channels
Full scale Input voltage
12
10
2.4
Bit
V
- COUT=1µF;
VOUT18
ΔVOUT/VOUT
IOUT18_MAX
Output voltage
Output voltage accuracy
Maximum load current
1.71
1.8
±5
10
1.89
V
%
mA
3.15
3.3
3.45
±5
V
%
20
mA
140
120
°C
°C
LDO331,2 - COUT=1µF;
VOUT33
Output voltage
ΔVOUT/VOUT
Output voltage accuracy
IOUT33_MAX
Maximum Output Current
Thermal Shutdown
TSD
Thermal shutdown
© 2016 Integrated Device Technology, Inc
Threshold Rising
Threshold Falling
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May 17, 2016
P9235A-R Datasheet
Table 5. Device Characteristic (Continued)
VIN = 5 V, VDDIO = 3.3 V, EN
¯¯ = 0V, LP = 6.5 µH, CP = 400 nF TA = -40C to +85C. Typical values are at 25°C, unless otherwise noted.
Description
Conditions/Notes
Min
Typical Max
Units
Symbol
Clock Oscillators
FLSOSC
Low speed clock
50
kHz
FCLOCK
OSC clock frequency
6
MHz
FCENTER2
PLL VCO frequency
120
MHz
General Purpose Inputs/Outputs (GPIO)
VIH
Input high voltage
0.7*VDDIO
VIL
Input low voltage
ILKG
Leakage Current
VOH
Output logic high
I=8mA
VOL
Output logic low
I=8mA
V
-1.0
0.3*VDDIO
V
1 .0
µA
2.4
V
0.5
V
SCL, SDA (I2C Interface)
fSCL_MSTR
Clock Frequency
As I2C master
400
kHz
fSCL_SLV
Clock Frequency
As I2C slave
400
kHz
CB
Capacitive load
For each bus line
CBIN
SCL, SDA Input Capacitance
ILKG
Leakage Current
100
5.0
1.0
pF
pF
1.0
µA
NOTES:
1.
Do not externally load. For internal biasing only.
2.
Guaranteed by design and not subject to 100% production testing
© 2016 Integrated Device Technology, Inc
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May 17, 2016
P9235A-R Datasheet
Typical Performance Characteristics
Figure 2. Typical Performance Characteristics – 3W
Efficiency vs Current - 3W
Load Regulation vs Current - 3W
Vin=5V, Vout=5V, Tx=P9235A-R, Tx coil=760308101103, Gap=1.5mm,
Rx coil=760308102213, Rx=P9027LP-R, No air flow, Room temperature
Vin=5V, Vout=5V, Tx=P9235A-R, Tx coil=760308101104, Gap=1.5mm,
Rx coil=760308101220, Rx=P9027LP-R, No air flow, Room
temperature
85
0.5
80
0.4
0.3
Load Regulation (%)
Efficiency (%)
75
70
65
60
55
50
0.2
0.1
0
-0.1
0
40
80
120
160
200
240
280
320
360
400
-0.2
-0.3
45
-0.4
60
120
180
240
300
360
420
480
540
600
-0.5
Iout (mA)
Iout (mA)
Figure 3. Typical Performance Characteristics – 2W
Efficiency vs Current - 2W
Load Regulation vs Current - 2W
Vin=5V, Vout=5V, Tx=P9235A-R, Tx coil=760308101104, Gap=1.5mm,
Rx coil=760308101220, Rx=P9027LP-R, No air flow, Room temperature
Vin=5V, Vout=5V, Tx=P9235A-R, Tx coil=760308101104, Gap=1.5mm,
Rx coil=760308101220, Rx=P9027LP-R, No air flow, Room
temperature
70
0.5
65
0.4
60
0.3
Load Regulation (%)
Efficiency (%)
75
55
50
45
40
35
30
25
40
80
120
160
200
240
280
320
360
0.2
0.1
0
-0.1
0
40
80
120
160
200
240
280
320
360
400
-0.2
-0.3
-0.4
400
-0.5
Iout (mA)
Iout (mA)
Figure 4. Typical Performance Characteristics – 1W
Efficiency vs Current - 1W
Load Regulation vs Current -1W
Vin=5V, Vout=5V, Tx=P9235A-R, Tx coil=WT151512-21F2, Gap=1.5mm,
Rx coil=WR121220-27M8, Rx=P9027LP-R, No air flow, Room
temperature
Vin=5V, Vout=5V, Tx=P9235A-R, Tx coil=WT151512-21F2,
Gap=1.5mm, Rx coil=WR121220-27M8, Rx=P9027LP-R, No air flow,
Room temperature
60
0.5
0.4
0.3
LoadRegulation (%)
Efficiency (%)
50
40
30
20
10
0.2
0.1
0
-0.1
0
20
40
60
80
100
120
140
160
180
200
-0.2
-0.3
0
20
40
60
80
100
120
140
160
180
-0.4
200
-0.5
Iout (mA)
© 2016 Integrated Device Technology, Inc
Iout (mA)
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May 17, 2016
P9235A-R Datasheet
Pin Configuration
40
39
38
37
36
35
34
33
32
31
ISNS_H
ISNS_L
ISNS_OUT
ISNS_IN
VSNS_IN
VSNS_GND
VBRG_IN
VIN_DRV
GH_BRG1
BST_BRG1
Figure 5. QFN-40 5 mm x 5 mm – Top View
1
EN
SW_BRG1
30
2
GND_S
GL_BRG1
29
3
VO_5
GND_BRG
28
4
VIN
GL_BRG2
27
5
SW_B
SW_BRG2
26
6
GND_B
BST_BRG2
25
EP (Center Exposed Pad)
GPIO_B2
22
10
RSVD1
LED_GRN
21
LED_RED
VO_18
BUZ
9
TS
23
GPIO_A4
GPIO_B3
LED_PAT
VIN_LDO
ILIM
8
SDA
24
SCL
GH_BRG2
VDDIO
VO_33
RSVD2
7
11
12
13
14
15
16
17
18
19
20
© 2016 Integrated Device Technology, Inc
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May 17, 2016
P9235A-R Datasheet
Pin Description
Table 6. Pin Descriptions
Pin(s)
Name
Type
Description
Active low enable pin. When connected to logic high, the device shuts down and
consumes less than 25 µA of current. When connected to logic low, the device is in
normal operation.
1
EN
¯¯
I
2
GND_S
-
Ground connection.
3
VO_5
O
Regulated output voltage used for the internal device biasing. Connect a 1 µF capacitor
from this pin to ground. This pin should not be externally loaded.
4
VIN
I
Input power supply. Connect a 10 µF capacitor from this pin to ground.
5
SW_B
O
Step-down regulator switch node. Connect one of the terminals of a 4.7 µH inductor to this
pin.
6
GND_B
-
Ground connection.
7
VO_33
O
Regulated 3.3 V output voltage used for internal device biasing. Connect a 1 µF capacitor
from this pin to ground. This pin should not be externally loaded.
8
VIN_LDO
I
Low Dropout input power supply. Connect this pin to a 5 V source, either to the output of
the 5 V output step-down regulator or to the input power supply pin, VIN.
9
VO_18
O
Regulated 1.8 V output voltage used for internal device biasing. Connect a 1 µF capacitor
from this pin to ground. This pin should not be externally loaded.
10
RSVD1
I
This pin is reserved for internal use only. Pull down to ground with an external 47 kΩ
resistor.
11
RSVD2
I
This pin is reserved for internal use only. Pull down to ground with an external 47 kΩ
resistor.
12
VDDIO
I
Input power supply for all GPIOs. Can be connected to a power supply ranging from 1.8 –
5.0 V.
13
SCL
I
Clock for I2C communication. Connect a 5.1 K resistor from this pin to VO_5
14
SDA
I/O
Data for I2C communication. Connect a 5.1 K resistor from this pin to VO_5
15
ILIM
I
Programmable over-current limit pin. Connect a resistor from this pin to GND to set the
current-limit threshold. To disable the current-limit, connect the pin directly to GND. For
more information, see current limit application section.
16
LED_PAT
I
Programmable LED pattern selection. Connect the center tap of the resistor divider to this
pin. For more information on various LED blinking pattern, see LED pattern application
section.
17
GPIO_A4
I/O
General purpose input/output. The GPIO’s power is supplied from the VDDIO pin. This pin
is configured as an output. If it is not used then it may be left floating.
18
TS
I
Remote temperature sensing. Connect a 10 k NTC via a voltage divider to this pin.
19
BUZ
O
Buzzer pin output.
© 2016 Integrated Device Technology, Inc
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May 17, 2016
P9235A-R Datasheet
Table 7. Pin Descriptions (continued)
Pin(s)
Name
Type
Description
Open drain output. Connect a red LED to this pin. This pin can sink a maximum current of
25 mA (typical)
20
LED_RED
O
21
LED_GRN
O
Open drain output. Connect a green LED to this pin. This pin can sink a maximum current
of 25 mA (typical)
22
GPIO_B2
I/O
General purpose input/output. The GPIO’s power is supplied from the VDDIO pin. This pin
is configured as an output. If it is not used then it may be left floating.
23
GPIO_B3
I/O
General purpose input/output. The GPIO’s power is supplied from the VDDIO pin. This pin
is configured as an output. If it is not used then it may be left floating.
24
GH_BRG2
O
Gate driver output for the high-side half bridge 2.
25
BST_BRG2
I
Bootstrap pin for the half bridge 2. Tie an external capacitor from this pin to the SW_BRG2
to generate a drive voltage, which is higher than the input voltage.
26
SW_BRG2
O
Switch node for half bridge 2.
27
GL_BRG2
O
Gate driver output for the low-side half bridge 2.
28
GND_BRG
-
Ground return connection for half bridge 1 and half bridge 2 external FETs and associated
components.
29
GL_BRG1
O
Gate driver output for the low-side half bridge 1.
30
SW_BRG1
O
Switch node for half bridge 1.
31
BST_BRG1
I
Bootstrap pin for half bridge 1. Tie an external capacitor from this pin to the SW_BRG1 to
generate a drive voltage higher than the input voltage.
32
GH_BRG1
O
Gate driver output for the high-side half bridge 1.
33
VIN_DRV
I
Input power supply for the internal gate drivers. Connect a 10 µF capacitor from this pin to
ground.
34
VBRG_IN
I
Bridge voltage input voltage sense.
35
VSNS_GND
-
Ground connection for voltage sense signals.
36
VSNS_IN
I
Voltage modulation signal input.
37
ISNS_IN
I
38
ISNS_OUT
O
Differential (ISNS_H - ISNS_L) current sense buffered output.
39
ISNS_L
I
Input current sense negative input
40
ISNS_H
I
Input current sense positive input
EPGND
-
Expose pad. Thermal pad for heat sinking purposes. Connect EPGND to GND plane.
Current modulation signal input.
ISNS_OUT is fed into this pin after external conditioning
© 2016 Integrated Device Technology, Inc
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May 17, 2016
P9235A-R Datasheet
GND_S
Demodulation
(Isense)
Demodulation
(Vsense)
Buck
Controller
VIN
Half/Full
Bridge
PWM
Controller
SW_B
32-Bit ARM M0
Processor
LDO33
LDO
1.8V
LDO18
GPIO_A4
RSVD1
RSVD2
SDA
Low Side
Driver 1
GL_BRG1
SW_BRG1
BST_BRG2
GH_BRG2
SW_BRG2
GL_BRG2
GND_BRG
LDO
3.3V
SCL
GH_BRG1
Low Side
Driver 2
VIN_LDO
VIN_DRV
BST_BRG1
High Side
Driver 1
High Side
Driver 2
GND_B
VSNS_GND
ISNS_OUT
ISNS_H
ISNS_L
Current
Sense
Amplifier
VSNS_IN
VO_5
PreReg
Bridge
Voltage
Sense
ISNS_IN
Reference
VBRG_IN
EN
Figure 6. P9235A-R Block Diagram
32KB
4KB
OTP
SRAM
12-Bit
ADC
120MHz
PLL
MUX
6MHz
OSC
VDDIO
I/O
Module
LED
Driver
BUZ
Driver
LED_GRN
LED_RED
BUZ
GPIO_B2
GPIO_B3
LED_PAT
I2C
© 2016 Integrated Device Technology, Inc
TS
ILIM
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May 17, 2016
P9235A-R Datasheet
Theory of Operation
General System Architecture
A wireless power transfer system has two sub-systems: the wireless power transmitter (Tx) and the wireless power receiver (Rx). The
transmitter makes power available through a full bridge/half bridge driven LC resonant tank. It transmits power through the generation of an
AC magnetic field. Once the receiver coil is placed near the magnetic field, the field will induce an AC current through the receiving coil
where it is converted into a DC current.
High Level Control Scheme
Wireless power systems adopt a set of pre-defined in-band communication commands as the close loop control strategy. The amount of
power transferred is controlled by the receiver. The receiver sends out Control Error Packets (CEP) to the transmitter to increase power,
decrease power, or maintain the power level. The transmitter responds by adjusting the switching frequency and/or duty ratio. The receiver
requests more power by sending out a CEP, which includes a positive numerical value. The communication is digital. The communication 1’s
and 0’s ride on top of the power link that exists between the two coils.
Wireless Power Communication
When the transmitter is not transferring power to the receiver, it is in the low power Standby Mode. While in this mode, in order to detect a
receiver, the transmitter sends out periodic analog and digital pings.
Analog pings are very short AC detection pulses. These short pulses do not transmit enough energy to wake up the receiver, only to detect its
presence. Digital pings, on the other hand, do transmit enough power to enable the receiver to wake up and begin communication. The
transmitter uses digital pings to listen for a response from a receiver. After the transmitter detects a receiver, it may extend the digital ping.
This causes the system to proceed to the Identification and Configuration phase.
Once the receiver is detected and powered up, it will send out communications packets to handshake with the transmitter. The first
communication packet the receiver sends out is the Signal Strength packet, followed by Identification packets and Configuration packets.
Once the handshake process is done, the receiver will send out periodic Control Error packets and Received Power packets to adjust the
power.
If the receiver needs to stop the power transfer, it will send out an End of Power Transfer (EPT) communication packet. The transmitter stops
transmitting power immediately, and starts pre-defined routines according to the information decoded from the EPT packet.
System Fault Protection
The wireless power transfer system implements system level protection. These include over voltage, under voltage, over current, and over
temperature protection. On the transmitter side, whenever a fault condition is detected, it shuts down the whole system immediately and
protects itself. If the receiver detects a fault condition, it will send the End of Power Transfer packets to shut down the system. The transmitter
will continue to transmit power from the time of the receiver fault detection to the reception of the End of Power Transfer packet.
Over voltage protection: If the transmitter VIN is greater than 5.5 V, and the system is not in the Power Transfer mode, then the transmitter will
shut down until the VIN is in the range of 4.5 V to 5.5 V. If the system is already in the Power Transfer mode, then the transmitter takes no
action.
Under voltage protection: If the transmitter VIN is less than 4.5 V, the transmitter will shut down for five minutes, or until the VIN is cycled. off/on.
Over current protection: The transmitter uses a 20 mΩ sense resistor (RSENSE, R6) to monitor the current. If the transmitter detects a current
greater than the programmed current limit, it will shut down for five minutes, or until VIN is cycled off/on.
Over temperature protection: If the TS pin (pin 18) voltage falls below 600 mV (typical) then the transmitter will shut down. It will restart once
the TS voltage rises above 800 mV (200 mV hysteresis).
© 2016 Integrated Device Technology, Inc
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P9235A-R Datasheet
Applications Information
LDOs
There are three internal LDOs, which supply the P9235A-R internal voltage rails. Do not externally load any of the LDOs. VO_5 is the output
of a high voltage LDO, which serves as the pre-regulator. VO_5 initially supplies the input voltage to the other two LDOs until the buck
regulator output voltage powers up.
The other two LDOs, VO_33 and VO_18, have output voltages of 3.3 V and 1.8 V, respectively. The analog circuitry is power by the 3.3 V
LDO. The digital circuitry is powered by the 1.8 V LDO.
LDO Input and Output Capacitors
For proper load voltage regulation and operational stability, low ESR ceramic capacitors are required on the input and output of each LDO. A
10 µF low ESR ceramic cap is recommended for both the input (C19) and output (C14, C27, C29) capacitors. The capacitor’s connection to
the ground pin should be as short as possible for optimal device performance.
Buck Regulator
The buck regulator is the power supply for the 3.3 V and 1.8 V LDOs, and thus for all the internal analog and digital circuitry, excluding the
pre-regulator only. Do not externally load any of the LDOs. The current sourcing capability of this internal buck regulator is 50 mA maximum.
The two half bridge gate driver circuits are directly power by the buck regulator.
The P9235A-R buck regulator operates in hysteretic pulse mode to set the output voltage and will regulate the output voltage at 5 V (typical)
when VIN is greater than 5.5 VDC. For operation with VIN less than 5.5 V, the buck output will decrease below 5 V. When the VIN is less than
5 V, the regulator will switch to a linear mode that is similar to a LDO.
The input (C18, C19) and output (C20, C21) capacitors must be connected directly between each power rail pins and power GND pin (and
placed as close as possible to the respective IC pins). The output capacitors should be selected based on the typical reference schematic to
guarantee control loop stability. A 10 µF low ESR ceramic cap is recommended for both the bulk input (C19) and bulk output (C21) capacitor.
The buck regulator output voltage is connected to the VIN_LDO pin; therefore, the connection from the buck output to the VIN_LDO pin
should be made as wide and short as possible to minimize output voltage errors.
Buck Inductor Selection
A 4.7 µH inductor (L1) is used for the P9235A-R buck regulator. Select the inductor saturation current rating to exceed the value of peak
inductor current (during normal operation and start up). The inductor included in the Bill of Materials is recommended. Keep the inductor DCR
to a minimum to improve the efficiency of the regulator.
Decoupling Capacitors
As with any high-performance mixed-signal IC, P9235A-R must be isolated from the system power supply noise. A decoupling capacitor of
0.1 μF should be connected between each power supply pin (includes VIN, the buck regulator, LDOs, VBRG_IN, V_BRIDGE: C18, C20, C28,
C9, C12, C31) and the PCB ground plane. It must be placed as close as possible to these pins. The decoupling capacitor must be mounted
on the component side of the PCB.
Note: The VO_33 does not need this decoupling capacitor if the user follows the IDT recommended, optimized layout.
Full Bridge Input Capacitor
At least one 10 μF capacitor (C19) must be placed at the VIN pin. At least three 10 μF capacitors (C10, C11, C30) must be placed across the
full bridge voltage source (the V_BRIDGE node in the schematic) to minimize voltage ripple and voltage drop due to the large current
requirements. The full-bridge is used to convert DC voltage to AC voltage for power transfer. These 10 μF capacitors must be placed as close
as possible to the respective pins.
Note: If the half bridge FETs are not physically close together then two 10 μF capacitors per half bridge are needed. Follow the IDT optimized
layout in order to minimize these capacitors
© 2016 Integrated Device Technology, Inc
11
May 17, 2016
P9235A-R Datasheet
Enable Function (EN Pin)
When voltage on the EN
¯¯ pin is greater than 2.5 V, the P9235A-R shuts down the buck regulator. It goes onto Shutdown Mode, which
disables all the analog and digital modules. Current consumption in Shutdown Mode is less than 25 µA. When EN
¯¯ is less than 1.0 V, the
P9235A-R is fully functional, and all the blocks are enabled. Figure 7 shows EN thresholds.
V_EN (V)
Figure 7. EN pin threshold
2.5V
VEN_H
VEN_L
1.0V
Normal
Operating
mode
Shutdown
Mode
Normal
Operating
mode
Time
When EN
¯¯ is less than 1.0 V and a receiver is not yet detected, the P9235A-R is in the low power Standby Mode. The P9235A-R periodically
comes out of Standby Mode to generate digital and analog pings to detect the presence of a receiver. Between these pings, the P9235A-R
continues in the Standby Mode to maintain low power consumption.
Input Current Sense
The P9235A-R monitors its input current by using an external sense resistor (R6), in series with the input voltage rail of the full bridge LC tank
driver circuit (Q2, Q3). The voltage across the sense resistor is fed into the ISNS_H and ISNS_L pin via an RC filter (R4,R5,C2). The
differential signal of ISNS_H and ISNS_L is processed by the internal ADC and associated firmware.
The current sense resistor is sensitive to noise, as well as to circuit board conditions. On the layout of PCB, it is necessary to use Kelvin
sensing when routing the ISNS_H and ISNS_L connections. Incorrect current reporting may also occur when a re-worked board has residue
(e.g. flux) around the sense resistor. More details are available in the P9235A-R layout guide, AN936.
For 2W/3W applications, use a 20mΩ sense resistor (R6). For 1W applications use a 50 mΩ sense resistor. Adjust the resistor divider (R27,
R31) value on the LED_PAT pin according to the sense resistor used.
Communication and Modulation
The wireless power system uses an in-band communication, such that the current and voltage on the transmitter’s power coil assume two
states, namely a HI state and a LO state. For a valid state, the amplitude is constant, within a certain variation Δ, for at least ts ms. If the
wireless power receiver is properly aligned to the transmitter’s power coil, and for all appropriate loads, at least one of the following two
conditions shall apply, as shown in Figure 8.
Difference of the amplitude of the transmitter current in the HI and LO state: ≥ 15 mA.
Difference of the amplitude of the transmitter voltage in the HI and LO state: ≥ 200 mV.
The minimum hold time for a valid HI or LO state: ≥ 0.15 ms
Figure 8. Modulation
ts
ts
ts
HI State
HI State
ts
Modulation
Depth
LO State
Δ
LO State
The receiver uses a 2 kHz, differential, bi-phase encoding scheme to modulate data bits onto the power signal. A logic ONE bit is encoded
© 2016 Integrated Device Technology, Inc
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May 17, 2016
P9235A-R Datasheet
using two narrow transitions. A logic ZERO bit is encoded using two wider transitions as shown in Figure 9.
Figure 9. Bit encoding scheme.
t CLK
ONE
ZERO
ONE
ONE
ZERO
ONE
ZERO
ZERO
Each byte in the communication packet comprises 11 bits in an asynchronous serial format. The start bit is always LO. This is followed by 8
bits of data. The final two bits are parity and stop, as shown in Figure 10.
Figure 10. Byte encoding scheme.
Start
b0
b1
b2
b3
b4
b5
b6
b7
Parity
Stop
The wireless power receiver communicates with the wireless power transmitter via communication packets. Each communication packet has
the following structure:
Figure 11. Communication packet structure
Preamble
Header
Message
Checksum
LED Pattern Selection
A green LED and a red LED indicate status. The LED Patterns depend on the selected LED mode. The voltage applied through resistor
divider to the LED_PAT pin selects the desired LED mode. Table 8 shows the available selections. Note that the LED pin selection is
combined with the input current sense resistor. Pulling the LED_PAT pin to GND via a 47 kΩ resistor will set the LED pattern to the default
Mode 1.
© 2016 Integrated Device Technology, Inc
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May 17, 2016
P9235A-R Datasheet
Table 8. LEDs indication table pattern
Current
Sense
Resistor
Option
Number
Voltage
on
LED_PA
T pin[V]
Resistor Divider Values
(Input voltage: LDO18)
RTOP
RBOTTOM
[R27]
[R31]
20 mΩ
1
Pull down
<0.037 V
NP
47 kΩ,1%
20 mΩ
2
0.11 V
715 kΩ,1%
47 kΩ,1%
20 mΩ
3
0.18 V
422 kΩ,1%
47 kΩ,1%
20 mΩ
4
0.26 V
280 kΩ,1%
47 kΩ,1%
20 mΩ
5
0.33 V
210 kΩ,1%
47 kΩ,1%
20 mΩ
6
0.41 V
160 kΩ,1%
47 kΩ,1%
50 mΩ
7
0.63 V
86.6 kΩ,1%
47 kΩ,1%
50 mΩ
8
0.71 V
71.5 kΩ,1%
47 kΩ,1%
50 mΩ
9
0.78 V
61. kΩ,1%
47 kΩ,1%
50 mΩ
10
0.86 V
51.1 kΩ,1%
47 kΩ,1%
50 mΩ
11
0.93 V
44.2 kΩ,1%
47 kΩ,1%
50 mΩ
12
1.01 V
36.5 kΩ,1%
47 kΩ,1%
Operational Status
LED #/Color
Standby
Transfer
Complete Fault
LED1-Green
Off
On
Off
LED2-Red
Off
Off
Off
LED1-Green
On
Off
Off
LED2-Red
On
Off
Off
LED1-Green
LED2-Red
Off
-
Blink 1 Hz
-
On
-
LED1-Green
Off
On
Off
LED2-Red
LED1-Green
On
Blink 1Hz
On
LED2-Red
On
Off
Off
LED1-Green
Off
Off
On
LED2-Red
Off
On
Off
LED1-Green
Off
On
Off
LED2-Red
Off
Off
Off
LED1-Green
On
Off
Off
LED2-Red
On
Off
Off
LED1-Green
Off
Blink 1 Hz
On
LED2-Red
-
-
-
LED1-Green
Off
On
Off
LED2-Red
LED1-Green
On
Blink 1Hz
On
LED2-Red
On
Off
Off
LED1-Green
Off
Off
On
LED2-Red
Off
On
Off
Off
Blink 4
Hz
Off
Blink 4
Hz
Blink 4Hz
Blink 4
Hz
Off
Blink 4
Hz
Off
Blink 4
Hz
Off
Blink 4
Hz
Off
Blink 4
Hz
Blink 4
Hz
Blink 4
Hz
Off
Blink 4
Hz
Off
Blink 4
Hz
Input Over Current Protection
Input over current protection protects the transmitter half-bridge and receiver from exposure to conditions that may cause damage or
unexpected behavior from the system. While the P9235A-R is in the power transfer stage, it monitors the input current, through the voltage
across the input current sense resistor. If the input current goes above the programmed threshold, the P9235A-R will shut down for 5 minutes,
and then re-try through digital pings. If the receiver condition remains the same for 5 more minutes, the P9235A-R will continue the periodic
analog pings only (no digital pings). If the receiver is removed, or the input power is cycled, the P9235A-R will restart digital pings immediately.
The ILIM pin voltage selects the input current limit through a voltage divider connected to LDO18. Table 9 shows options for 1, 2, and 3W
systems, given minimum expected efficiencies. The default value input current limit is 1.25A. The default value occurs when ILIM pin is
connected to GND via a 47 kΩ resistor.
© 2016 Integrated Device Technology, Inc
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May 17, 2016
P9235A-R Datasheet
Table 9. ILIM programmable thresholds
Resistor Divider Values
(Input voltage: LDO18)
RTOP
RBOTTOM
[R26]
[R30]
130 kΩ,1%
47 kΩ,1%
Max Power
Vout
/Max Iout
1W
5 V/200 mA
0.75 A
0.48 V
2W
5 V/400 mA
1.25 A
0.78 V
NP
47 kΩ,1%
3W
5 V/600 mA
2.0 A
1.23 V
22 kΩ,1%
47 kΩ,1%
Input current Limit
threshold
Voltage on ILIM
pin
Remote Temperature Sensing and Over Temperature Protection
The P9235A-R uses a NTC thermistor connected to the TS pin to monitor the remote temperature during the power transfer phase. Connect
the NTC thermistor to a voltage divider as shown in Figure 15. If the voltage on the TS pin decreases below 0.6 V, the transmitter shuts off
the power, and will resume the wireless power transfer once the TS pin voltage rises above 0.8 V.
Figure 12. NTC connection
LDO33
RBIAS
TS
RTHM
VTS =
LDO33 × R THM,TRIP
= 600mV
(R THM,TRIP + R BIAS )
Where:


VTS (V) = Trip voltage at the desired trip temperature
RTHM,TRIP (kΩ) = Resistance of the thermistor at the desired trip temperature
Given LDO33 = 3.3V and RBIAS=10kΩ, then RTHM,TRIP = 2.22 kΩ at the trip temperature
The basic characteristic of an NTC thermistor is:
  1 1 
R  R 0exp B    
  T T0 
Where:



T (Kelvin) = The trip temperature.
R0 (kΩ) = The known resistance at calibration temperature T0 (Kelvin).
B (beta, Kelvin) = The material constant .
With RBIAS=10kΩ, RTHM =2.2kΩ, and VTS=600mV at a trip temperature T, the desired R0 and B can be calculated, and the appropriate
thermistor chosen.
© 2016 Integrated Device Technology, Inc
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May 17, 2016
P9235A-R Datasheet
Buzzer Function
The BUZ pin is able to drive a piezoelectric type transducer without amplification. As shown on the reference schematic, a series current
limiting resistor (R20) must be included if a buzzer is used. The buzzer signal is a 2 kHz square wave. It is recommended to use a buzzer with
a 2 kHz resonant frequency for best results.
End of Power Transfer Response
The P9235A-R will shut down and stop the power transfer once it receives an End of Power Transfer (EPT) packet. The P9235A-R will
behave differently based on the reason for the EPT request. Table 10 shows the different EPT behaviors.
Table 10. End of Power Transfer Response
EPT Reason
P9235A-R Behavior
End of Power Transfer:
Over-Current
The P9235A-R will shut down the system, keeping the analog ping and digital ping. If the over-current
condition is not removed, the system will enter into a hiccup mode. In hiccup mode the following sequence
is repeated while the over current condition exists: the system starts up and applies the receiver voltage to
the load, the receiver detects an over current condition and reports it to the transmitter, the transmitter
shuts down.
End of Power Transfer:
Over-Temperature
The P9235A-R will shut down the system, keeping the analog ping but muting the digital ping for 5
minutes. If the P9027LP-R is removed within 5 minutes, the P9235A-R will restart the digital ping. After 5
minutes, the P9235A-R will send out one digital ping to check if the fault condition has been removed.
End of Power Transfer:
Charge Complete.
The P9235A-R will shut down the system, keeping the analog ping but muting the digital ping for 5
minutes. If the P9027LP-R is removed within 5 minutes, the P9235A-R will restart the digital ping. After 5
minutes, the P9235A-R will send out one digital ping to check if the battery needs to start charging again.
End of Power Transfer:
Internal Fault
The P9235A-R will shut down the system, keeping the analog ping and digital ping.
© 2016 Integrated Device Technology, Inc
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May 17, 2016
P9235A-R Datasheet
Transmitter Resonant Tank Capacitors
For optimum performance, and to keep the characteristics of the resonant tank constant, the resonant frequency and quality factor must not
change due to variations in the associated capacitors or inductors. The capacitors of the resonant tank (C15, C17, C23, C25) must be
COG/NPO type only. COG/NPO capacitors have no temperature variation, less voltage related de-rating, and better accuracy than other
types of capacitors such at the X7R. Do not mix capacitor types when populating the resonant capacitors, use COG/NPO types only. All the
resonant capacitors must be rated for 50V. See the Bill of Materials for the recommended values.
Transmitter Resonant Tank Coils
Each half-bridge output connects to a series-resonance LC tank. The inductor serves as the primary coil of a loosely-coupled transformer; the
secondary is the receiver coil connected to the P9027LP-R.
The transmitter coils are mounted on a ferrite base acting as a shield to concentrate the field on the top side of the coil and to reduce EMI.
The coil assembly can be mounted next to the P9235A-R PCB or on the back of PCB. Either a ground plane or grounded metal shielding
(preferably copper) can be added beneath the ferrite shield for added reduction in radiated electrical field emissions. The coil ground
plane/shield must be connected to the ground plane by a single trace leading back independently to the board input power connector.
For optimum performance, the following coils are recommended for use with the P9235A-R transmitter for 1, 2 and 3 W applications. The
recommended coil vendors have been tested and verified to guarantee their performance.
Table 11. Coils Recommended with receiver for 1, 2 and 3 W Applications
Output
Power
1W
2W
3W
Vendor
Part number
Inductance
DCR
Dimension
TDK
WT151512-22F2-ID
6.49 uH
0.17 Ω
Ø15 mm
SunLord
SWA15T15H20C01B
6.30 uH
0.12 Ω
Ø15 mm
TDK
WT202012-15F2-ID
6.20 uH
0.10 Ω
Ø20 mm
Wurth Electronics
760308101104
6.30 uH
0.11 Ω
Ø20 mm
SunLord
SWA20N20H20C01B
6.30 uH
0.15 Ω
Ø20 mm
TDK
WT303012-13F2-ID
6.30 uH
0.12 Ω
Ø30 mm
Wurth Electronics
760308101103
6.50 uH
0.15 Ω
Ø30 mm
SunLord
SWA30N30H20C01B
6.25 uH
0.14 Ω
Ø30 mm
PCB Layout Considerations
Layout and PCB design have a significant influence on the system performance. The power dissipation capabilities of the P9235A-R surface
mount packaged power management IC rely heavily on thermally conductive traces and pads to transfer heat away from the package. The
regulator or full bridge inverter could show instability, as well as cause EMI problems, if the PCB layout is not designed properly. The following
general guidelines will be helpful in designing a board layout for low noise and EMI, as well as, the lowest thermal resistance:
1.
2.
3.
PC board traces with large cross-sectional areas remove more heat. For optimal results, use large-area PCB patterns with wide
copper traces, placed on the component side of the PCB.
In cases where maximum heat dissipation is required, use double-sided copper planes connected with multiple vias.
Thermal vias provide a thermal path from the bridge FETs to inner and/or bottom layers of the PCB to remove the heat
generated by device power dissipation.
For more details, please refer to the application note AN936, “P9235A-R Layout Guidelines” for the layout details.
© 2016 Integrated Device Technology, Inc
17
May 17, 2016
P9235A-R Datasheet
Power Dissipation and Thermal Requirements
The P9235A-R is offered in a QFN-40 package which has a maximum power dissipation capability of approximately 1.2W. The number of
thermal vias between the package and the printed circuit board determines the maximum power dissipation. The maximum power dissipation
of the package is limited by the die’s specified maximum operating junction temperature, TJ(MAX), of 125°C, the maximum ambient operating
temperature, TA, of 85°C,and the package thermal resistance, ΘJA. The junction temperature rises when the heat generated by the device’s
power dissipation flows through the package thermal resistance. The QFN package offers a typical thermal resistance, junction to ambient
(ΘJA), of 28.5°C/W when the PCB layout guideline and surrounding devices are optimized.
The techniques as noted in the PCB layout section must be followed when designing the printed circuit board layout. Attention to the
placement of the P9235A-R IC and bridge FET packages, in proximity to other heat-generating devices in a given application design, should
also be considered. The ambient temperature around the power IC will also have an effect on the thermal limits of an application. The main
factors influencing ΘJA (in the order of decreasing influence) are PCB characteristics, die/package attach thermal pad size (QFN) and thermal
vias, and final system hardware construction. Board designers should keep in mind that the package thermal metric ΘJA is impacted by the
characteristics of the PCB itself upon which the IC is mounted. Changing the design or configuration of the PCB changes the overall thermal
resistivity and the board’s heat-sinking efficiency.
The use of integrated circuits in low-profile and fine-pitch surface-mount packages requires special attention to power dissipation. Many
system-dependent issues such as thermal coupling, airflow, added heat sinks, convection surfaces, and the presence of other heatgenerating components affect the power-dissipation limits of a given component.
In summary, the three basic approaches for enhancing thermal performance are:
1.
2.
3.
Improve the power dissipation capability of the PCB design
Improve the thermal coupling of the component to the PCB
Introduce airflow into the system
First, the maximum power dissipation for a given situation should be calculated:
PD(MAX) = (TJ(MAX) - TA)/θJA
In which




PD(MAX) = Maximum Power Dissipation
θJA = Package Thermal Resistance (°C/W)
TJ(MAX) = Maximum Device Junction Temperature (°C)
TA = Ambient Temperature (°C)
The maximum recommended operating junction temperature (TJ(MAX)) for the P9235A-R device is 120°C. The thermal resistance of the 40-pin
QFN package is optimally θJA=28.5°C/W. Operation is specified to a maximum steady-state ambient temperature (TA) of 85°C. Therefore, the
maximum recommended power dissipation is:
PD(Max) = (120°C - 85°C) / 28.5°C/W ≅ 1.2 Watt.
Thermal Protection
To allow the maximum load current, and to prevent thermal overload, he heat generated by the P9235A-R solution must be dissipated into the
PCB. All the available pins must be soldered to the PCB. GND pins (exposed paddle, EP) and bridge FET GND pins should be soldered to
the PCB ground plane to improve thermal performance, with multiple vias connected to all layers of the PCB.
Special Notes
NDG QFN-40 Package Assembly
Note 1: Unopened Dry Packaged Parts have a one-year shelf life.
Note 2: The HIC indicator card for newly-opened Dry Packaged Parts should be checked. If there is any moisture content, the parts must be
baked for a minimum of 8 hours at 125˚C within 24 hours prior to the assembly reflow process.
© 2016 Integrated Device Technology, Inc
18
May 17, 2016
LDO33
BUZ
LDO33
OPTIONAL FEATURS
VCC
J1
10k
R20
RSVD2
D3
GREEN
LED
R23
R22
RED
ILIM
680
1K
THERMISTOR 2
t
0.1uF
RT1
LDO33
LED_GRN
LED_PAT
LDO18
Solder_Jumper
0.1uF
C20
C29
1uF
C28
LDO18
Q1
VIN_USB
1uF 0.1uF
C27
LDO33
GND_TS
LED_RED
10uF
C34
C19
0.1uF
VIN_5V
INRUSH CURRENT LIMIT
C18
C13
0.1uF
BUZ_TP
D2 LED
100
R21
5
4
3
2
1
TS1
usb_micro_ab
ZX62D-AB-5P8
SLD
D+
D-
R8
ISNS_IN
ENB
TS
GND
GND1
LDO18
A4
BUZ_TP
B2
B3
LDO18
A4
BUZ
B2
B3
GND3
GND2
VSNS_IN
LDO33
LDO33
SDA
RSVD1
RSVD2
VDDIO
VO_33
VO_18
VIN_LDO
GND_B
VIN
SW_B
GND_S
VO_5
ENB
SCL
VIN_USB
10
11
12
7
9
8
6
4
5
2
3
ENB 1
RSVD1
RSVD2
LDO33
4.7uH
1uF
C14
U1
VIN_5V
C21
10uF
L1
1k
ISNS_H
ISNS_L
C4
220pF
VIN_5V
VIN_USB
TESTING POINTS
VIN_LDO
1uF/10V
C7
R7 100K
ID
FDC654P/SOT23-6
SS1
40
39
ISNS_H
ISNS_L
6.8nF
C6
1k
C3
220pF
P9235A-R
R2
VSNS_IN
36
35
GND
TS
ENB
ISNS_IN
VSNS_IN
SCL
SDA
EPGND
GND_BRG
GL_BRG2
BST_BRG2
SW_BRG2
GH_BRG2
GL_BRG1
BST_BRG1
SW_BRG1
GH_BRG1
R1
41
28
R16
27
12
C26
R14
R9
12
R12 12
100nF
12
220k
R3
VSNS
V_BRIDGE
C5
5.6nF
C16 100nF
0.1uF
25
26
24
29
31
30
10k
VIN_LDO
C9
10uF/10V
C8
32
22nF
C1
NP
R15
NP
R10
NP
C36
NP
C35
R6
10
R4
C2
C12
3
6
0.1uF
10uF/10V
C11
C30
V_BRIDGE
10uF
10uF/10V
C10
V_BRIDGE
VIN_5V
ISNS_H
R13
100k
ISNS_IN
38
37
ISNS_OUT
ISNS_IN
13
14
15
16
17
18
19
SCL
SDA
ILIM
LED_PAT
GPIOA4
TS
BUZ
33
VIN_DRV
34
VBRG_IN
SCL
SDA
ILIM
LED_PAT
A4
TS
BUZ
0.1uF
3
6
C31
0.02
1uF
1
2
SLD
R19 100k
VSNS_IN
VSNS_GND
LED_RED
LED_GRN
GPIOB2
GPIOB3
20
21
22
23
LED_RED
LED_GRN
B2
B3
C22
NP
11
10
8
RSVD1
NP
47k
NP
47k
C32
9
7
6
R25
R29
NP
47k
R24
R28
R27
TS
R26
R30
NP
47k
19
R31
5
4
C33
22nF/25V
AON7810
Q3
5
4
ISNS_L
AON7810
Q2
10
R5
1
2
© 2016 Integrated Device Technology, Inc
NP
P9235 A-R Low Power Mass Market Schematics V1P9
0
R18
C24
22nF/25V
R11
0
L2_1
VSNS
Monday , March 14, 2016
<Doc>
Docum ent Num ber
IDTP9235A-R LP MM EV V1P9
R17
5.1k
D1
CMOD3003
Sheet
1
Table 12. P9235A-R Schematic
Dat e:
C
L2_2
100nF/50V
100nF/50V
100nF/50V
100nF/50V
of
1
Rev
Detailed System Diagram
Size
Tit le
C25
C23
C17
C15
1_0
P9235A-R Datasheet
May 17, 2016
P9235A-R Datasheet
Components Selection
Table 13. Component List
Item
Reference
Description
PCB Footprint
MFG Part Number
1
Qty
3
C1,C24,C33
22 nF/50 V
0402
C0402C223K5RACTU
2
1
C2
1 uF/10 V
0402
C0402C105M8PACTU
3
2
C3,C4
220 pF/50 V
0402
CL05B221KB5NNNC
4
1
C5
5.6 nF/50 V
0402
CL05B562KB5NNNC
5
1
C6
6.8 nF/50 V
0402
CL05B682JB5NNNC
6
5
C9,C12,C13,C18,C31
0.1 uF/25 V
0402
TMK105BJ104KV-F
7
1
C8
10 uF/10 V
0402
CL05A106MP5NUNC
8
5
C10,C11,C19,C21,C30
10 uF/25 V
0603
CL10A106MA8NRNC
9
4
C7,C14,C27,C29
1 uF/10 V
0402
CL05A105KP5NNNC
10
11
12
13
14
4
2
3
4
1
C15,C17,C23,C25
C16,C26
C20,C34,C28
C22,C32,C35,C36
D1
100 nF/50 V
100 nF
0.1 uF/10 V
NP
DIODE
1206
0402
0402
0402
SOD523PD
C3216C0G1H104J160AA
C1005X6S1V104K050BB
C0402C104K8RACTU
15
1
D2
Red LED
0603
150 060 RS7 500 0
16
1
D3
Green LED
060
150 060 GS7 500 0
17
1
J1
5P
usb_micro_ab
10104111-0001LF
18
1
L1
4.7 uH
0603
CIG10W4R7MNC
19
1
L2
Transmitter coil
20
1
Q1
80 mOhm/4.5 V
21
2
Q2,Q3
N-Channel MOSFETs
22
1
R1
23
3
24
CMOD3003
7650308101104
FDC654P
10 K/%1
SOT23-6
DFN
3 mm X 3 mm
402
R2,R8,R22
1k
0402
RC0402FR-071KL
1
R3
220 k
0402
RC0402FR-07220KL
25
2
R4,R5
10
0402
RT0402DRE0710RL
26
1
R6
0.02
0603
WSL0805R0200FEA
27
3
R7,R13,R19
100 k
0402
ERJ-2GEJ104X
28
4
12
0402
ERJ-2GEJ120X
29
6
NP
0402
30
2
R9,R12,R14,R16
R10,R15,R24.R25,R26,R2
7
R11,R18
0 OHMS RESISTOR
0402
RC0402JR-070RL
31
1
R17
5.1 k
0402
MCR01MRTJ512
32
1
R20
10 k
0402
CRCW040210K0JNED
33
1
R21
100
0402
RC0402JR-07100RL
34
1
R23
680
0402
RC0402JR-07680RL
35
4
R28,R29,R30,R31
47 k
0402
ERJ-2GEJ473X
36
1
RT1
THERMISTOR
0603
ERT-J1VG103FA
37
1
U1
IDTP9235
QFN_5 x 5 mm
P9235A-R
© 2016 Integrated Device Technology, Inc
20
AON7810
RCG040210K0FKED
May 17, 2016
P9235A-R Datasheet
Package Drawing
Figure 13. QFN-40 NDG40 Package Outline Drawing
© 2016 Integrated Device Technology, Inc
21
May 17, 2016
P9235A-R Datasheet
Landing Pattern Drawing
Figure 14. QFN-40 NDG40 Landing Pattern Drawing
© 2016 Integrated Device Technology, Inc
22
May 17, 2016
P9235A-R Datasheet
Ordering Information
Orderable Part Number
Package
MSL Rating
Shipping Packaging
Temperature
P9235A-RNDGI
NDG40 - QFN-40 5x5x0.40
3
Tray
-40° to +85°C
P9235A-RNDGI8
NDG40 - QFN-40 5x5x0.40
3
Tape and Reel
-40° to +85°C
Marking Diagram
1.
2.
3.
“IDT” Company code, “P9235A-R” Part number.
“NDG” Package type: QFN, “I” Industrial
“#” Device stepping, “YY” Last 2 digits of the year, “WW” Work
week that the part was assembled, “$” Assembly location code
Revision History
[Insert the revision history entries in reverse chronological order.]
Revision Date
Description of Change
May 16, 2016
Final
May 2, 2016
This is the first preliminary release of this datasheet..
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DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specificat ions and
operating parameters of the described products are determined in an independent state and are not guaranteed to perform th e same way when installed in customer products. The information contained herein is provided
without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of
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P9235A-RNDGI8 P9235A-RNDGI
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