Intel®Server System H2000LP Family

Intel®Server System H2000LP
Family
Technical Product Specification
Intel order number: G59328-001
Revision 1.0
April, 2012
Enterprise Platforms and Services Division
Revision History
Intel® Server System H2000LP Family TPS
Revision History
Date
Revision Number
April 2012
1.0
Modifications
Initial release.
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Disclaimers
Disclaimers
Information in this document is provided in connection with Intel® products. No license, express
or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel®
assumes no liability whatsoever, and Intel® disclaims any express or implied warranty, relating
to sale and/or use of Intel® products including liability or warranties relating to fitness for a
particular purpose, merchantability, or infringement of any patent, copyright or other intellectual
property right. Intel® products are not intended for use in medical, lifesaving, or life sustaining
applications. Intel® may make changes to specifications and product descriptions at any time,
without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked
“reserved” or “undefined”. Intel® reserves these for future definition and shall have no
responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® Server System H2000LP Family may contain design defects or errors known as
errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
This document and the software described in it is furnished under license and may only be used
or copied in accordance with the terms of the license. The information in this manual is
furnished for informational use only, is subject to change without notice, and should not be
construed as a commitment by Intel Corporation. Intel Corporation assumes no responsibility or
liability for any errors or inaccuracies that may appear in this document or any software that may
be provided in association with this document.
Except as permitted by such license, no part of this document may be reproduced, stored in a
retrieval system, or transmitted in any form or by any means without the express written consent
of Intel Corporation.
Intel, Pentium and Xeon are trademarks or registered trademarks of Intel Corporation.
*Other brands and names may be claimed as the property of others.
Copyright © Intel Corporation 2012. Portions Copyright © 2012 by LSI* Corporation and
Mellanox* Corporation.
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Table of Contents
Intel®Server System H2000LP Family TPS
Table of Contents
1. Introduction ........................................................................................................................ 1
1.1
Chapter Outline ...................................................................................................... 1
1.2
Server Board Use Disclaimer ................................................................................. 2
2. Product Overview ............................................................................................................... 3
2.1
System Views......................................................................................................... 5
2.2
System Dimensions................................................................................................ 5
2.3
System Level Environmental Limits ........................................................................ 6
2.4
Hard Drive and Peripheral Bays ............................................................................. 7
2.5
Server Board Overview .......................................................................................... 8
2.6
Front Bezel Support ............................................................................................. 10
2.7
Rack and Cabinet Mounting Options .................................................................... 10
3. Power Sub-System ........................................................................................................... 12
3.1
Mechanical Overview ........................................................................................... 12
3.1.1
AC Power Supply Unit Dimension Overview ........................................................ 12
3.1.2
AC Power Supply Unit General Data .................................................................... 12
3.1.3
AC input connector ............................................................................................... 13
3.1.4
AC Power Cord Specification Requirements ........................................................ 13
3.1.5
Power Supply Unit DC Output Connector ............................................................. 13
3.1.6
Handle Retention ................................................................................................. 14
3.1.7
LED Marking and Identification ............................................................................. 14
3.1.8
Power Cage with Power Distribution Board .......................................................... 14
3.1.9
Power Cage Output Pin Assignment .................................................................... 15
3.2
AC Input Specification .......................................................................................... 17
3.2.1
Input Voltage And Frequency ............................................................................... 17
3.2.2
AC input Power Factor ......................................................................................... 17
3.2.3
Efficiency.............................................................................................................. 17
3.2.4
AC Line Fuse ....................................................................................................... 18
3.2.5
AC Line Inrush ..................................................................................................... 18
3.2.6
AC Line Dropout/Holdup ...................................................................................... 18
3.2.7
AC Line Fast Transient (EFT) Specification.......................................................... 19
3.2.8
Hot Plug ............................................................................................................... 19
3.2.9
Susceptability Requirements ................................................................................ 19
3.2.10 Electrostatic Discharge Susceptibility ................................................................... 19
3.2.11 Fast Transient/Burst ............................................................................................. 19
3.2.12 Radiated Immunity ............................................................................................... 19
3.2.13 Surge Immunity .................................................................................................... 19
3.2.14 AC Line Transient Specification ........................................................................... 20
3.2.15 Power recovery .................................................................................................... 20
3.2.16 Voltage Interruptions ............................................................................................ 20
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3.2.17 AC Line Isolation .................................................................................................. 20
3.2.18 AC Power Inlet ..................................................................................................... 21
3.3
DC Ouput Specification ........................................................................................ 21
3.3.1
Output Power/Currents......................................................................................... 21
3.3.2
Standby Output .................................................................................................... 22
3.3.3
Voltage Regulation ............................................................................................... 22
3.3.4
Dynamic Loading ................................................................................................. 22
3.3.5
Capacitive Loading ............................................................................................... 22
3.3.6
Ripple/Noise ......................................................................................................... 23
3.3.7
Grounding ............................................................................................................ 23
3.3.8
Closed Loop Stability............................................................................................ 23
3.3.9
Residual Voltage Immunity in Standby Mode ....................................................... 23
3.3.10 Common Mode Noise........................................................................................... 23
3.3.11 Soft Starting ......................................................................................................... 23
3.3.12 Zero Load Stability Requirement .......................................................................... 24
3.3.13 Hot Swap Requirement ........................................................................................ 24
3.3.14 Forced Load Sharing ............................................................................................ 24
3.3.15 Timing Requirement ............................................................................................. 24
3.5
Power Supply Cold Redundancy Support............................................................. 25
3.5.1
1200W CRPS Cold Redundancy .......................................................................... 26
3.5.2
1600W CRPS Cold Redundancy .......................................................................... 26
3.6
Control And Indicator Functions ........................................................................... 26
3.6.1
PSON# Input Signal ............................................................................................. 26
3.6.2
PWOK(power good) Output Signal ....................................................................... 27
3.6.3
SMBAlert# Signal ................................................................................................. 27
3.7
Protection circuits ................................................................................................. 28
3.7.1
Current Limit (OCP).............................................................................................. 28
3.7.2
Over Voltage Protection (OVP) ............................................................................ 28
3.7.3
Over Thermal protection ....................................................................................... 28
3.8
PMBus* ................................................................................................................ 29
3.8.1
PSU Address Lines A0 ......................................................................................... 29
3.8.2
Accuracy .............................................................................................................. 30
4. Cooling Sub-System......................................................................................................... 31
4.1
Processor Heatsink .............................................................................................. 31
4.2
Node cooling Fans ............................................................................................... 32
4.3
Power Supply Fan ................................................................................................ 33
4.4
Air Duct Module .................................................................................................... 33
4.5
Drive Bay Population Requirement....................................................................... 34
5. System Boards in the Node Tray ..................................................................................... 35
5.1
Node Docking Board ............................................................................................ 35
5.1.1
Overview of Node Docking Board......................................................................... 35
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5.1.2
Pinout definition on Node Docking Board ............................................................. 36
5.2
Bridge Board ........................................................................................................ 37
5.2.1
Overview of Bridge Board .................................................................................... 37
5.2.2
Pinout definition on Bridge Board ......................................................................... 38
6. Hard Disk Drive Support .................................................................................................. 40
6.1
Hard Disk Drive Bays Scheme ............................................................................. 40
6.2
Hard Drive Carrier ................................................................................................ 40
6.3
Hot-Swap Hard Drive Support .............................................................................. 41
6.3.1
Backplane Feature set: ........................................................................................ 42
6.3.2
Backplane Block Diagram .................................................................................... 43
6.3.3
3.5” Hot Swap Backplane Connector scheme ...................................................... 43
6.3.4
2.5" Hot Swap Backplane Connector scheme ...................................................... 44
6.3.5
Backplane LED Support ....................................................................................... 45
6.3.6
Backplane Connector Definition ........................................................................... 46
7. Front Panel Control and Indicators ................................................................................. 50
7.1
Control Panel Button ............................................................................................ 51
7.2
Control Panel LED Indicators ............................................................................... 51
7.2.1
Power/Sleep LED ................................................................................................. 52
7.2.2
System Status LED .............................................................................................. 52
7.2.3
System Status LED – BMC Initialization ............................................................... 53
8. Configuration Jumpers .................................................................................................... 54
8.1
Force BMC Update (J9C2) ................................................................................... 55
8.2
BIOS Recovery Mode (J9F2) ............................................................................... 55
8.3
Password Clear (J6E1) ........................................................................................ 56
8.4
Force ME Update (J6E1) ...................................................................................... 57
8.5
Password Clear (J6E1) ........................................................................................ 58
8.6
Force ME Update (J6E1) ...................................................................................... 58
8.7
Reset BIOS Settings (J6E1) ................................................................................. 59
9. PCI Express* Riser Card and Assembly ......................................................................... 61
9.1
PCI Express* Riser for Slot 1 ............................................................................... 61
9.1.1
Overview of PCI-Express Riser ............................................................................ 61
9.1.2
Pinout definition on Slot 1 Riser ........................................................................... 61
9.2
PCI Express* Riser with IOM Carrier for Slot 2 (Optional) .................................... 66
9.2.1
Overview of PCI-E Riser with IOM Carrier ............................................................ 66
9.2.2
Pinout definition on Slot 2 Riser and IOM Carrier ................................................. 67
Appendix A: Integration and Usage Tips .............................................................................. 73
Appendix B: POST Code LED Decoder ................................................................................. 74
Appendix C: Video POST Code Errors .................................................................................. 78
Glossary .................................................................................................................................. 83
Reference Documents ............................................................................................................ 86
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List of Figures
List of Figures
Figure 1. System Overview (Air Duct is removed) ....................................................................... 5
Figure 2. Compute Node Scheme (Rear View) ........................................................................... 5
Figure 3. Intel® Server System H2312LP Drive Bay Overview..................................................... 7
Figure 4. Intel® Server System H2216LP Drive Bay Overview..................................................... 7
Figure 5. Intel® Server Board S2400LP ....................................................................................... 8
Figure 6. Intel® Server Board S2400LP Components .................................................................. 9
Figure 7. Back Panel Feature Overview ...................................................................................... 9
Figure 8. Light-Guided Diagnostic LED Locations ..................................................................... 10
Figure 9. System Bezel Front View ........................................................................................... 10
Figure 10. AC Power Supply Unit Dimension Overview ............................................................ 12
Figure 11. Power Cage Overview.............................................................................................. 15
Figure 12. Power distribution board........................................................................................... 16
Figure 13. AC Power Cord Specification ................................................................................... 21
Figure 14. Turn On/Off Timing (Power Supply Signals) ............................................................. 25
Figure 15. Power Supply Device Address ................................................................................. 29
Figure 16. PMBus* Monitoring Accuracy ................................................................................... 30
Figure 17. Processor Heatsink Overview .................................................................................. 31
Figure 18. Node Fan Set and power/control Connection ........................................................... 33
Figure 19. Compute Node Air Duct ........................................................................................... 33
Figure 20. Compute Node Tray Overview ................................................................................. 35
Figure 21. Node Docking Board ................................................................................................ 35
Figure 22. Bridge Board Overview ............................................................................................ 37
Figure 23. Connectors on Bridge Board .................................................................................... 38
Figure 24. HDD Scheme for H2312LPJR .................................................................................. 40
Figure 25. HDD Scheme for H2216LPJR .................................................................................. 40
Figure 26. 3.5-inch HDD Assembly Overview ........................................................................... 41
Figure 27. 2.5-inch HDD Assembly Overview ........................................................................... 41
Figure 28. Passive Backplane Block Diagram (for one node) .................................................... 43
Figure 29. 3.5" Backplane Component and Connectors (Front View) ........................................ 43
Figure 30. 3.5" Backplane Component and Connectors (Back View) ........................................ 44
Figure 31. 2.5" Backplane Component and Connectors (Front View) ........................................ 45
Figure 32. 2.5" Backplane Component and Connectors (Back View) ........................................ 45
Figure 33. Hard Drive Carrier LED ............................................................................................ 46
Figure 34. Front Control Panel .................................................................................................. 50
Figure 35.Jumper Locations and Functions............................................................................... 54
Figure 36. PCI Express* Riser for Riser Slot 1 .......................................................................... 61
Figure 37. PCI Express* Riser with bracket for Riser Slot 2 ...................................................... 66
Figure 38. IOM Carrier .............................................................................................................. 67
Figure 39. Diagnostic LED location ........................................................................................... 74
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List of Tables
Intel®Server System H2000LP Family TPS
List of Tables
Table 1. System Feature Set....................................................................................................... 3
Table 2. System SKU matrix ....................................................................................................... 4
Table 3. Chassis Dimension (SKU: H2312LPJR) ........................................................................ 5
Table 4. Chassis Dimension (SKU: H2216LPJR) ........................................................................ 6
Table 5. System Environmental Limits Summary ........................................................................ 6
Table 6. Specification Data for AC Power Supply Unit .............................................................. 13
Table 7. AC power cord specification ........................................................................................ 13
Table 8. DC Output Power Connector ....................................................................................... 13
Table 9. Power Supply Status LED ........................................................................................... 14
Table 10. Pin assignment of power ouput connector ................................................................. 16
Table 11. Pin assignment of control signal connector................................................................ 16
Table 12. AC input rating .......................................................................................................... 17
Table 13. Typical power factor .................................................................................................. 17
Table 14. Platinum Efficiency Requirement ............................................................................... 18
Table 15. AC Power Holdup Reuqirement................................................................................. 18
Table 16. Performance Criteria ................................................................................................. 19
Table 17. AC Line Sag Transient Performance ......................................................................... 20
Table 18. AC Line Surge Transient Performance ...................................................................... 20
Table 19. Load Ratings for single power supply unit ................................................................. 21
Table 20. Voltage Regulation Limits .......................................................................................... 22
Table 21 Transient Load Requirements .................................................................................... 22
Table 22. Capacitive Loading Conditions .................................................................................. 22
Table 23. Ripple and Noise ....................................................................................................... 23
Table 24. Timing Requirement .................................................................................................. 24
Table 25. 1200W CRPS Cold Redundancy Threshold .............................................................. 26
Table 26. 1600W CRPS Cold Redundancy Threshold. ............................................................. 26
Table 27. PSON# Signal Characteristics ................................................................................... 26
Table 28. PWOK Signal Characteristics .................................................................................... 27
Table 29. SMBAlert# Signal Characteristics .............................................................................. 27
Table 30. Over Current Protection............................................................................................. 28
Table 31. Over Voltage Protection (OVP) Limits ....................................................................... 28
Table 32. PSU addressing ........................................................................................................ 29
Table 33. PMBus* Accuracy...................................................................................................... 30
Table 34. 8-pin Connector Pin-Out for Node Dual Rotor Fans................................................... 33
Table 35. Main Power Input Connector ..................................................................................... 36
Table 36. Fan Control Signal Connector ................................................................................... 36
Table 37. Node Fan Connector ................................................................................................. 36
Table 38. Main Power Output Connector .................................................................................. 37
Table 39. Card Edge Connector Pinout ..................................................................................... 38
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List of Tables
Table 40. 5V_AUX Power Connector Pinout ............................................................................. 39
Table 41. Hard Drive Carrier Status LED Functions .................................................................. 46
Table 42. Hard Drive Carrier Activity LED Functions ................................................................. 46
Table 43. Backplane Input Power Connector Pin-out ................................................................ 46
Table 44. 2-Blade Compute Node Power Connector Pin-out..................................................... 47
Table 45. 2x40 Pin Connector Pin-out for Node Bridge Board................................................... 47
Table 46. Front Panel Connector Pin-out .................................................................................. 48
Table 47. Power Supply Control Connector Pin-out .................................................................. 49
Table 48. Front Control Button Function.................................................................................... 51
Table 49. Front LED Indicator Functions ................................................................................... 51
Table 50. Power LED Operation ............................................................................................... 52
Table 51. System Status LED Operation ................................................................................... 52
Table 52. Force Integrated BMC Update Jumper ...................................................................... 54
Table 53. Force Integrated BMC Update Jumper ...................................................................... 55
Table 54. BIOS Recovery Mode Jumper ................................................................................... 56
Table 55. Password Clear Jumper ............................................................................................ 57
Table 56. Force ME Update Jumper ......................................................................................... 57
Table 57. BIOS Password Clear Jumper ................................................................................... 58
Table 58. Force ME Update Jumper ......................................................................................... 58
Table 59. Reset BIOS Jumper .................................................................................................. 59
Table 60. Riser Card Edge Pinout ............................................................................................. 61
Table 61. PCI Express* Slot Pinout on Riser Card .................................................................... 64
Table 62. Dedicated NIC Port LED Functionality ....................................................................... 67
Table 63. Riser Card Edge Pinout ............................................................................................. 67
Table 64. PCI Express* Slot Pinout on Riser Card .................................................................... 69
Table 65. IO Module Slot on Carrier .......................................................................................... 71
Table 66. POST Code Diagnostic LED Location ....................................................................... 74
Table 67. POST Progress Code LED Example ......................................................................... 75
Table 68. Diagnostic LED POST Code Decoder ....................................................................... 75
Table 69. POST Error Message and Handling .......................................................................... 78
Table 70. POST Error Beep Codes ........................................................................................... 81
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1.
Introduction
Introduction
This Technical Product Specification (TPS) provides system specific information detailing the
features, functionality, and high-level architecture of the Intel® Server System H2000LP family.
You should also reference the Intel® Server Board S2400LP Family Technical Product
Specification to obtain greater detail of functionality and architecture of the server board
integrated in this server system.
In addition, you can obtain design-level information for specific sub-systems by ordering the
External Product Specifications (EPS) or External Design Specifications (EDS) for a given subsystem. EPS and EDS documents are not publicly available. They are only made available
under NDA with Intel and must be ordered through your local Intel representative. For a
complete list of available documents, refer to the Reference Documents section at the end of
this document.
The Intel® Server System H2000LP may contain design defects or errors known as errata which
may cause the product to deviate from published specifications. Refer to the Intel® Server Board
S2400LP/Intel® Server System H2000LP Specification Update for published errata.
1.1
Chapter Outline
This document is divided into the following chapters:














Chapter 1 – Introduction
Chapter 2 – Product Overview
Chapter 3 – Power Sub-System
Chapter 4 – Cooling Sub-System
Chapter 5 – System Boards in the Node Tray
Chapter 6 – Hard Disk Drive Support
Chapter 7 – Front Panel Control and Indicators
Chapter 8 – Configuration Jumpers
Chapter 9 – PCI Express* Riser Card and Assembly
Appendix A – Integration and Usage Tips
Appendix B – POST code LED Decoder
Appendix C – Video POST Code Errors
Glossary
Reference Documents
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Introduction
1.2
Intel®Server System H2000LP Family TPS
Server Board Use Disclaimer
Intel Corporation server boards support add-in peripherals and contain a number of high-density
VLSI and power delivery components that need adequate airflow to cool. Intel ensures through
its own chassis development and testing that when Intel server building blocks are used
together, the fully integrated system will meet the intended thermal requirements of these
components. It is the responsibility of the system integrator who chooses not to use Intel
developed server building blocks to consult vendor datasheets and operating parameters to
determine the amount of air flow required for their specific application and environmental
conditions. Intel Corporation cannot be held responsible if components fail or the server board
does not operate correctly when used outside any of their published operating or non-operating
limits.
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2.
Product Overview
Product Overview
The Intel® Server System H2000LP family includes two major SKUs: H2312LP and H2216LP,
which are rack mount 2U 4-node server systems, purpose-built for high-density and lowest total
cost of ownership in dense computing applications, such as HPC and IPDC. The system is
integrated with four units of Intel® Server Board S2400LP, supports up to twelve 3.5" or sixteen
2.5" hot-swap SAS or SATA hard drives, with Common Redundant Power Supply(CRPS)
capability.
This chapter provides a high-level overview of the system features. The following chapters
provide greater detail for each major system component or feature.
Table 1. System Feature Set
Feature
Processor
Memory
Chipset
System
Connectors
/Headers
System Fan
Support
Description
®
®
Support Intel Xeon Processor E5-2400 series processors.
®
®

Up to 8 GT/s Intel QuickPath Interconnect (Intel QPI).

LGA 1356 Socket R

Thermal Design Power (TDP) up to 95 Watt (6-core or 8-core), or 80W (4-core) and
below.

Unbuffered DDR3 and registered DDR3 with ECC DIMMs.

Memory DDR3 data transfer rates of 800/1066/1333/1600 MT/s.

Load Reduced DDR3 DIMM.

DDR3 standard I/O voltage of 1.5V(all speed) and DDR3 Low Voltage of
1.35V(1333MT/s or below)
®
Intel C600 Platform Controller Hub(PCH) with support for optional Storage Upgrade Key
External I/O connectors:

DB-15 Video connectors.

Two RJ-45 Network Interface for 10/100/1000 LAN.

One stacked two port USB 2.0 (Port 0/1) connectors.

One dedicated 1GbE management port on rIOM carrier (Optional).

One InfiniBand* QDR QSFP port (Board SKU: S2400LPQ)

One InfiniBand* FDR QSFP port (Board SKU: S2400LPF)
Internal connectors/headers:

Bridge Slot to extend board I/O
SCU0 (Four SAS 3Gb/s ports) to backplane
One SATA(Port 0) 6Gb/s port for DOM
Front control panel signals

One 2x7pin header for system FAN module

One DH-10 serial Port A connector
®

One 2x4 pin header for Intel RMM4 Lite

One 1x4 pin header for Storage Upgrade Key
Three sets of dual rotor fan for each node.
Add-in Adapter
Support
Two PCIe Gen III x16 riser slots:

Riser slot 1 support PCIe Gen III x16 Riser with LP PCIe add-in card
®

Riser slot 2 supports PCIe Gen III x8 Riser (PCIe Gen II for Intel rIOM)
One Bridge Slot for board I/O expansion.
On-board Video
On-board Server Engines* LLC Pilot III Controller

Integrated 2D Video Controller

128 MB DDR3 Memory
12x 3.5-inch SATA/SAS HDD bays (SKU: H2312LP)
Hard Disk Drive
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Product Overview
Intel®Server System H2000LP Family TPS
Feature
Description
Supported
16x 2.5-inch SATA/SAS HDD bays (SKU: H2216LP)
RAID Support

Intel RSTe SW RAID 0/1/10/5 for SATA mode

LSI SW RAID 0/1/10/5
For each node

One Gigabit Ethernet device i350 connect to PCI-E x4interfaces on the PCH, providing
2 GbE ports for each node.

One QSFP port from Mellanox* ConnectX3 to support QDR Infiniband* based on board
SKU.

One dedicated 1GbE management port with RMM4 Lite and rIOM carrier installed
1200w AC Common Redundant Power Supply (CRPS), 80 plus Platinum with PFC, supporting
CRPS configuration. Chassis SKU: H2312LPJR, H2216LPJR
LAN
System Power
1600w AC Common Redundant Power Supply (CRPS), 80 plus Platinum with PFC, supporting
CRPS configuration. Chassis SKU: H2312LPKR, H2216LPKR
Server
Management





Onboard ServerEngines* LLC Pilot III* Controller
®
Support for Intel Remote Management Module 4 Lite solutions.
®
Intel Light-Guided Diagnostics on field replaceable units.
®
Support for Intel System Management Software.
®
Support for Intel Intelligent Power Node Manager (Need PMBus*-compliant power
supply).
Table 2. System SKU matrix
Board SKU vs Chassis
S2400LP
S2400LPQ
S2400LPF
3.5” HDD with 1200W
CRPS
H2312LPJR
H2312LPQJR
H2312LPFJR
2.5” HDD with 1200W
CRPS
H2216LPJR
H2216LPQJR
H2216LPFJR
3.5” HDD with 1600W
CRPS
H2312LPKR
H2312LPQKR
H2312LPFKR
2.5” HDD with
1600W CRPS
H2216LPKR
H2216LPQKR
H2216LPFKR
The Intel® Server System H2000LP family are supporting all Intel® Xeon® processor E5-2400
series with TDP 95W (8-core, 6-core), or 80W (4-core) and below. You can find a full list of
supported processors at the Intel Support Website:
http://www.intel.com/p/en_US/support/highlights/server/H2000LP.
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2.1
Product Overview
System Views
A
B
C
Compute Node 3 Tray (upper left)
Compute Node 1 Tray (lower left)
Compute Node 4 Tray (upper right)
E
F
G
D
Compute Node 2 Tray (lower right)
H
Common Redundant Power Supply
HDD bays with Hot Swap Backplane
Upper and Lower Power Distribution
Boards
Front Control Panel
Figure 1. System Overview (Air Duct is removed)
Figure 2. Compute Node Scheme (Rear View)
2.2
System Dimensions
Table 3. Chassis Dimension (SKU: H2312LPJR)
Height
87.9mm
3.46"
Width
438mm
17.24"
Depth
Weight
771mm
Kg.
30
30.35"
Lbs.
66.14
Chassis – basic configured (2 PSU, 0 drives)
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Chassis – fully configured (2 PSU, 12 drives)
38
83.78
Table 4. Chassis Dimension (SKU: H2216LPJR)
Height
87.9mm
3.46"
Width
438mm
17.24"
Depth
Weight
733mm
Kg.
29
32
28.86"
Lbs.
63.93
70.55
Chassis – basic configured (2 PSU, 0 drives)
Chassis – fully configured (2 PSU, 16 drives)
2.3
System Level Environmental Limits
The following table defines the system level operating and non-operating environmental limits.
Table 5. System Environmental Limits Summary
Parameter
Limits
Temperature
Operating
10ºC to 35ºC (50ºF to 95ºF) with the maximum rate of change not to exceed
10°C per hour
Non-Operating
-40ºC to 70ºC (-40ºF to 149ºF)
Non-Operating
50% to 90%, non-condensing with a maximum wet bulb of 28°C (at temperatures
from 25°C to 35°C)
Operating
Half sine, 2g, 11 mSec
Unpackaged
Trapezoidal, 25 g, velocity change is based on packaged weight
Packaged
Product Weight: ≥ 40 to < 80
Non-palletized Free Fall Height = 18 inches
Palletized (single product) Free Fall Height = NA
Unpackaged
5 Hz to 500 Hz
2.20 g RMS random
Packaged
5 Hz to 500 Hz
1.09 g RMS random
Voltage
90 V to 132 V and 180 V to 264 V
Frequency
47 Hz to 63 Hz
Source
Interrupt
No loss of data for power line drop-out of 12 mSec
Surge Nonoperating and
operating
Unidirectional
Line to earth
Only
AC Leads
I/O Leads
DC Leads
Air Discharged
8.0 kV
Humidity
Shock
Vibration
AC-DC
2.0 kV
1.0 kV
0.5 kV
ESD
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Intel®Server System H2000LP Family TPS
Product Overview
Contact
Discharge
8.0 kV
Operating
-16 to 3048 m (-50 to 10,000 ft) Note: For altitudes above 2950 feet, the
maximum operating temperature is de-rated 1°F/550 ft.
Storage
-16 to 10,600 m (-50 to 35,000 ft)
Power in
Watts
All range
Servers/Rack
Mount BA
- 3.5” HDD SKU: 6.9BA at idle and 7.4BA at active mode;
- 2.5” HDD SKU: 6.5BA at idle and 7.07BA at active mode.
Altitude
Acoustics
Sound
Power
Measured
2.4
Hard Drive and Peripheral Bays
Slim-line SATA Optical Drive
Internal USB Floppy Drive
Intel®Server System H2312LP
Not Supported
Intel®Server System H2216LP
Not Supported
Not Supported
Not Supported
SATA/SAS Hard Disk Drives (3.5")
Up to Twelve
Not Supported
SATA/SAS Hard Disk Drives (2.5")
Not Supported
Up to Sixteen
Support
Support
SATA DOM
®
Figure 3. Intel Server System H2312LP Drive Bay Overview
®
Figure 4. Intel Server System H2216LP Drive Bay Overview
Revision 1.0
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Product Overview
2.5
Intel®Server System H2000LP Family TPS
Server Board Overview
The chassis is mechanically and functionally designed to support half-width server board,
including Intel® Server Board S2400LP. The following sections provide an overview of the
server board feature sets.
®
Figure 5. Intel Server Board S2400LP
The following figure shows the layout of the server board. Each connector and major component
is identified by a number or letter, and a description is given below the figure.
Description
Description
A
CPU2 VR
I
USB x 2
Q
B
CPU1 DIMM(6 Total)
J
Status and ID LED
R
Description
Storage Upgrade
Key
BIOS Recovery
8
Description
Y
ME Firmware Update
Z
Reset BIOS
Configuration
Revision 1.0
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Intel®Server System H2000LP Family TPS
C
Description
Bridge Board
Connector
Product Overview
Description
Description
Description
K
BMC
S
Serial Port A
AA
CPU1
D
PCH C600-A
L
VGA Out
T
TPM
AB
CPU1 VR
E
Riser Slot2 (PCIe
Gen3x16 with x8
Electrical)
M
Dual Port 1Gbe
NIC
U
RMM4 Lite
AC
CPU2 DIMM(6 Total)
F
Infiniband QDR
N
NIC Port 2
V
Battery
AD
2x3 PWR Connector
G
POST and QSFP
LED
O
NIC Port 1
W
SATA DOM
AE
CPU2
H
QSFP Port
P
Riser Slot 1(PCIe
Gen3x16 with x8
Electical)
X
Clear Password
AF
2x7 Fan Control
Connector
®
Figure 6. Intel Server Board S2400LP Components
A
Description
NIC port 1 (RJ45)
E
Description
Status LED
B
NIC port 2 (RJ45)
F
Dual port USB connector
C
DB15 video out
G
QSFP Connector
D
ID LED
H
QSFP status and Diagnostic
LED
Figure 7. Back Panel Feature Overview
Note: The Intel® Server System H2312LP and H2216LP requires the use of shielded LAN cable
to comply with Emission/Immunity regulatory requirements. Use of non shield cables may
result in product non-compliance.
Revision 1.0
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Product Overview
A
Intel®Server System H2000LP Family TPS
Diagnostic LED Group
B
QSFP Link/Activity LED
Figure 8. Light-Guided Diagnostic LED Locations
2.6
Front Bezel Support
Intel® Server System H2000LP family provides front panel bezel. The bezel provides protection
to system HDD bays with a lock to chassis. The front view of the bezel is as below.
Figure 9. System Bezel Front View
2.7
Rack and Cabinet Mounting Options
The chassis was designed to support 19 inches wide by up to 30 inches deep server cabinets.
The system bundles with the following Intel rack mount option.
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Product Overview
A basic slide rail kit (Product order code – AXXELVRAIL) is designed to mount the chassis into
a standard (19 inches by up to 30 inches deep) EIA-310D compatible server cabinet.
Revision 1.0
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Power Sub-System
3.
Intel®Server System H2000LP Family TPS
Power Sub-System
The system supports AC 1+1 hot swap power supply module and two power distribution board
which can support 2U rack high density server system. Two different power supply units are
supported: 1200W and 1600W. The single power supply module has Platinum level energy
efficiency, demonstrating climate saver with silver rating.
3.1
Mechanical Overview
The power supply module has a simple retention mechanism to retain the module self once it is
inserted. This mechanism shall withstand the specified mechanical shock and vibration
requirements. The power distribution board will be fixed in the chassis with screws. This
specification defines a 1+1 hot swap redundancy power supply that supports 2U server system.
Using existing power supply module provided by vendor with updated PMBus* and custommade power connector board to support four nodes of Intel® server board S2400LP. The power
supply shall have two outputs: 12V and 12VSB. The input shall be auto ranging and power
factor corrected. The PMBus* features included in this specification are requirements for AC
silver rated box power supply for use in server systems based on Intel® Server System
H2000LP Family. This specification is based on the PMBus* Specifications part I and II, revision
1.1.
3.1.1
AC Power Supply Unit Dimension Overview
The casing dimension is W 73.5mm x L 265.0mm x H 39/40mm. The power supply contains a
single 40mm fan. The power supply has a card edge output that interfaces with a 2x25 card
edge connector in the system. The AC plugs directly into the external face of the power supply.
Figure 10. AC Power Supply Unit Dimension Overview
3.1.2
AC Power Supply Unit General Data
Below is general specification data for AC Power Supply Unit.
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Power Sub-System
Table 6. Specification Data for AC Power Supply Unit
Wattage
Voltage
Heat Dissipation
Maximum Inrush Current
80 Plus rating
Climate Saver (CS) rating
3.1.3
1200W/1600W (Energy Smart)
90 – 264 VAC, auto-ranging, 47 Hz-63 Hz
2560 BTU/hr
Under typical line conditions and over the entire system ambient operating
range, the inrush current may reach 65 A per power supply for 5 ms
Platinum
Platinum
AC input connector
The power supply has an internal IEC320 C14 power inlet. The inlet is rated for a minimum of
10A at 250VAC.
3.1.4
AC Power Cord Specification Requirements
The AC power cord used must meet the following specification requirements:
Table 7. AC power cord specification
Cable Type
Wire Size
Temperature Rating
Amperage Rating
Cable Type
3.1.5
SJT
16 AWG
105ºC
13A
SJT
Power Supply Unit DC Output Connector
The DC output connector pin-out is defined as follows:
Table 8. DC Output Power Connector
PSU Output Connector
B1 GND
A1
GND
A2
GND
B2
GND
A3
GND
B3
GND
A4
GND
B4
GND
A5
GND
B5
GND
A6
GND
B6
GND
A7
GND
B7
GND
A8
GND
B8
GND
A9
GND
B9
GND
A10 +12V
B10 +12V
A11 +12V
B11 +12V
A12 +12V
B12 +12V
A13 +12V
B13 +12V
A14 +12V
B14 +12V
A15 +12V
B15 +12V
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Power Sub-System
Intel®Server System H2000LP Family TPS
A16 +12V
PSU Output Connector
B16 +12V
A17 +12V
B17 +12V
A18 +12V
B18 +12V
A19 PMBus* SDA*
B19 A0* (SMBus* address)
A20 PMBus* SCL*
B20 A1* (SMBus* address)
A21 PSON
B21 12V STBY
A22 SMBAlert#
B22 Cold Redundancy Bus*
A23 Return Sense
B23 12V load share bus
A24 +12V Remote Sense
B24 No Connect
A25 PWOK
B25 CRPS Compatibility Check pin*
Note: *Refer to CRPS Common Requirements Specification.
3.1.6
Handle Retention
The power supply has a handle to assist extraction. The module is able to be inserted and
extracted without the assistance of tools. The power supply also has a latch which retains the
power supply into the system and prevents the power supply from being inserted or extracted
from the system when the AC power cord is pulled into the power supply.
The handle protects the operator from any burn hazard through the use of industrial designed
plastic handle or equivalent material.
3.1.7
LED Marking and Identification
The power supply is using a bi-color LED: Amber and Green for status indication. Below are
table showing the LED states for each power supply operating state.
Table 9. Power Supply Status LED
Power Supply Condition
Output ON and OK
No AC power to all power supplies
AC present/Only 12VSB on (PS off) or PS in Cold
redundant state
AC cord unplugged or AC power lost; with a second
power supply in parallel still with AC input power.
Power supply warning events where the power supply
continues to operate; high temp, high power, high
current, slow fan.
Power supply critical event causing a shutdown; failure,
OCP, OVP, Fan Fail
Power supply FW updating
3.1.8
LED State
Solid GREEN
OFF
1Hz Blink GREEN
Solid AMBER
1Hz Blink Amber
Solid AMBER
2Hz Blink GREEN
Power Cage with Power Distribution Board
The power cage is at the middle of the chassis, consists of two Power Distribution Boards (PDB)
to support Common Redundant Power Supplies (CRPS).
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Intel®Server System H2000LP Family TPS
Power Sub-System
Following is the power system overview:
A
Power Distribution Board 1
B
Power Distribution Board 2
C
Power Supply Unit #2(upper) and #1(lower)
Figure 11. Power Cage Overview
3.1.9
Power Cage Output Pin Assignment
The power cage provides +12V and +12VSTB output to the system. Each PDB has two 2x9
power output cable to system backplane, together with one 2x8 signal control cable for power
management. Refer to below table for PDB pin assignment.
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Intel®Server System H2000LP Family TPS
A
Main Power Output Connector P1
B
Power Supply Unit Connector
C
Control Signal Connector
D
Main Power Output Connector P2
Figure 12. Power distribution board
Table 10. Pin assignment of power ouput connector
Pin
Description
Pin
Description
1
GND
2
+12V
3
GND
4
+12V
5
GND
6
+12V
7
GND
8
+12V
9
GND
10
+12V
11
GND
12
+12V
13
GND
14
+12V
15
GND
16
+12V
17
GND
18
+12V
Table 11. Pin assignment of control signal connector
Pin
1
Description
PMBus* SDA
Pin
2
Description
A0 (SMBus* Address)
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Intel®Server System H2000LP Family TPS
Pin
3.2
Power Sub-System
Description
Pin
Description
3
PMBus* SCL
4
A1 (SMBus* Address)
5
PSON#
6
12V Load Share Bus
7
SMBAlert#
8
Cold Redundancy Bus
9
Return Sense
10
PWOK
11
+12V Remote Sense
12
Compatibility Bus
13
Reserved
14
+12VSB
15
+12VSB
16
Key Pin (removed)
AC Input Specification
3.2.1
Input Voltage And Frequency
The power supply must operate within all specified limits over the following input voltage range.
Harmonic distortion of up to 10% THD must not cause the power supply to go out of specific
limits. The power supply shall be capable of start-up (power-on) with full rated power load, at
line voltage as low as 90VAC.
Table 12. AC input rating
Parameter
Min
Rated
Max
Start up VAC
Power Off VAC
110VAC
220VAC
Frequency
90 Vrms
180 Vrms
47 Hz
100-127 Vrms
200-240 Vrms
50/60 Hz
140 Vrms
264 Vrms
63 Hz
85 VAC± 4VAC
70VAC±5VAC
Note:
1. Maximum input current at low input voltage range shall be measured at 90VAC, at max load.
2. Maximum input current at high input voltage range shall be measured at 180VAC, at max load.
3. This requirement is not to be used for determining agency input current markings.
3.2.2
AC input Power Factor
The power supply must meet the power factor requirements stated in the Energy Star® Program
Requirements for Computer Servers. These requirements are stated below.
Table 13. Typical power factor
Output power
Power factor
10% load
> 0.80
20% load
> 0.90
50% load
> 0.90
100% load
> 0.95
Note: Tested at 230Vac, 50Hz and 60Hz and 115VAC, 60Hz. Tested according to Generalized
Internal Power Supply Efficiency Testing Protocol Rev 6.4.3. This is posted at
http://efficientpowersupplies.epri.com/methods.asp.
3.2.3
Efficiency
The following table provides the required minimum efficiency level at various loading conditions.
These are provided at three different load levels; 100%, 50%, 20%, and 10%. Output shall be
Revision 1.0
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Power Sub-System
Intel®Server System H2000LP Family TPS
load according to the proportional loading method defined by 80 Plus in Generalized Internal
Power Supply Efficiency Testing Protocol Rev 6.4.3. This is posted at:
http://efficientpowersupplies.epri.com/methods.asp.
Table 14. Platinum Efficiency Requirement
Loading
Minimum Efficiency
100% of maximum
50% of maximum
20% of maximum
10% of maximum
91%
94%
90%
82%
The power supply must pass with enough margin to make sure in production all power supplies
meet these efficiency requirements.
3.2.4
AC Line Fuse
The power supply shall have one line fused in the single line fuse on the line (Hot) wire of the
AC input. The line fusing shall be acceptable for all safety agency requirements. The input fuse
shall be a slow blow type. AC inrush current shall not cause the AC line fuse to blow under any
conditions. All protection circuits in the power supply shall not cause the AC fuse to blow unless
a component in the power supply has failed. This includes DC output load short conditions.
3.2.5
AC Line Inrush
AC line inrush current shall not exceed 65A peak, for up to one-quarter of the AC cycle, after
which, the input current should be no more than the specified maximum input current. The peak
inrush current shall be less than the ratings of its critical components (including input fuse, bulk
rectifiers, and surge limiting device).
The power supply must meet the inrush requirements for any rated AC voltage, during turn on at
any phase of AC voltage, during a single cycle AC dropout condition as well as upon recovery
after AC dropout of any duration, and over the specified temperature range (Top).
3.2.6
AC Line Dropout/Holdup
An AC line dropout is defined to be when the AC input drops to 0VAC at any phase of the AC
line for any length of time. During an AC dropout the power supply must meet dynamic voltage
regulation requirements. An AC line dropout of any duration shall not cause tripping of control
signals or protection circuits. If the AC dropout lasts longer than the holdup time the power
supply should recover and meet all turn on requirements. The power supply shall meet the AC
dropout requirement over rated AC voltages and frequencies. A dropout of the AC line for any
duration shall not cause damage to the power supply.
Table 15. AC Power Holdup Reuqirement
Loading
70%
Holdup time
10.6msec
The 12VSTB output voltage should stay in regulation under its full load (static or dynamic) during
an AC dropout of 70ms min (=12VSB holdup time) whether the power supply is in ON or OFF
state (PSON asserted or de-asserted).
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3.2.7
Power Sub-System
AC Line Fast Transient (EFT) Specification
The power supply shall meet the EN61000-4-5 directive and any additional requirements in
IEC1000-4-5: 1995 and the Level 3 requirements for surge-withstand capability, with the
following conditions and exceptions:
 These input transients must not cause any out-of-regulation conditions, such as overshoot and
undershoot, nor must it cause any nuisance trips of any of the power supply protection circuits.
 The surge-withstand test must not produce damage to the power supply.
The supply must meet surge-withstand test conditions under maximum and minimum DC-output
load conditions.
3.2.8
Hot Plug
Power supply shall be designed to allow connection into and removal from the system without
removing power to the system. During any phase of insertion, start-up, shutdown, or removal,
the power supply shall not cause any other like modules in the system to deviate outside of their
specifications. When AC power is applied, the auxiliary supply shall turn on providing bias
power internal to the supply and the 5VSB standby output.
3.2.9
Susceptability Requirements
The power supply shall meet the following electrical immunity requirements when connected to
a cage with an external EMI filter, which meets the criteria, defined in the SSI document EPS
Power Supply Specification. For further information on customer standards please request a
copy of the customer Environmental Standards Handbook.
Table 16. Performance Criteria
Level
A
B
C
3.2.10
Description
The apparatus shall continue to operate as intended. No degradation of performance.
The apparatus shall continue to operate as intended. No degradation of performance beyond
spec limits.
Temporary loss of function is allowed provided the function is self-recoverable or can be restored
by the operation of the controls.
Electrostatic Discharge Susceptibility
The power supply shall comply with the limits defined in EN 55024: 1998 using the IEC 610004-2:1995 test standard and performance criteria B defined in Annex B of CISPR 24.
3.2.11
Fast Transient/Burst
The power supply shall comply with the limits defined in EN55024: 1998 using the IEC 61000-44:1995 test standard and performance criteria B defined in Annex B of CISPR 24.
3.2.12
Radiated Immunity
The power supply shall comply with the limits defined in EN55024: 1998 using the IEC 61000-43:1995 test standard and performance criteria A defined in Annex B of CISPR 24.
3.2.13
Surge Immunity
The power supply shall be tested with the system for immunity to AC Ring wave and AC
Unidirectional wave, both up to 2kV, per EN 55024:1998, EN 61000-4-5:1995 and ANSI
C62.45: 1992.
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Intel®Server System H2000LP Family TPS
The pass criteria include: No unsafe operation is allowed under any condition; All power supply
output voltage levels to stay within proper spec levels; No change in operating state or loss of
data during and after the test profile; No component damage under any condition.
The power supply shall comply with the limits defined in EN55024: 1998 using the IEC 61000-45:1995 test standard and performance criteria B defined in Annex B of CISPR 24.
3.2.14
AC Line Transient Specification
AC line transient conditions shall be defined as “sag” and “surge” conditions. “Sag” conditions
are also commonly referred to as “brownout”, these conditions will be defined as the AC line
voltage dropping below nominal voltage conditions. “Surge” will be defined to refer to conditions
when the AC line voltage rises above nominal voltage.
The power supply shall meet the requirements under the following AC line sag and
surge conditions.
Table 17. AC Line Sag Transient Performance
AC Line Sag (10 sec interval between each sagging)
Duration
Sag
0 to ½ AC
cycle
95%
> 1 AC cycle
>30%
Operating AC Voltage
Nominal AC Voltage
ranges
Nominal AC Voltage
ranges
Line
Frequency
Performance Criteria.
50/60Hz
No loss of function or performance.
50/60Hz
Loss of function acceptable, selfrecoverable.
Table 18. AC Line Surge Transient Performance
AC Line Surge
Duration
Surge
Operating AC Voltage
Line Frequency
Continuous
10%
Nominal AC Voltages
50/60Hz
0 to ½ AC
cycle
30%
Mid-point of nominal AC
Voltages
50/60Hz
3.2.15
Performance Criteria
No loss of function or
performance
No loss of function or
performance
Power recovery
The power supply shall recover automatically after an AC power failure. AC power failure is
defined to be any loss of AC power that exceeds the dropout criteria.
3.2.16
Voltage Interruptions
The power supply shall comply with the limits defined in EN55024: 1998/A1: 2001/A2: 2003
using the IEC 61000-4-11: Second Edition: 2004-03 test standard and performance criteria C
defined in Annex B of CISPR 24.
3.2.17
AC Line Isolation
The power supply shall meet all safety agency requirements for dielectric strength.
Transformers’ isolation between primary and secondary windings must comply with the
3000Vac (4242Vdc) dielectric strength criteria. If the working voltage between primary and
secondary dictates a higher dielectric strength test voltage the highest test voltage should be
used. In addition the insulation system must comply with reinforced insulation per safety
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Power Sub-System
standard IEC 950. Separation between the primary and secondary circuits, and primary to
ground circuits, must comply with the IEC 950 spacing requirements.
3.2.18
AC Power Inlet
The AC input connector should be an IEC 320 C-14 power inlet. This inlet is rated for
10A/250 VAC.
The AC power cord must meet the following specification requirements:
Cable Type
Wire Size
SJT
16 AWG
Temperature Rating
105ºC
Amperage Rating
13 A
Voltage Rating
125 V
Figure 13. AC Power Cord Specification
3.3
DC Ouput Specification
3.3.1
Output Power/Currents
The following table defines the minimum power and current ratings. The power supply must
meet both static and dynamic voltage regulation requirements for all conditions.
Table 19. Load Ratings for single power supply unit
Parameter
Min
PSU SKU
Max
Peak 2,3
Unit
1200W
1600W
1200W
1600W
+12V main (200-240VAC)
0.0
100
133
133
175
A
+12V main (100-127VAC)
0.0
83
83
110
110
A
+12VSTB
0.0
3.0
3.5
3.5
2.4
A
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Notes:
1.
2.
3.
12VSTB must provide 4.0A with two power supplies in parallel. The power supply fan is allowed to run in
standby mode for loads > 1.5A.
Peak combined power for all outputs shall not exceed 1600W (for 1200W PSU) and 2100W (for 1600W PSU)
Length of time peak power can be supported is based on thermal sensor and assertion of the SMBAlert#
signal. Minimum peak power duration shall be 20 seconds without asserting the SMBAlert# signal.
3.3.2
Standby Output
The 12VSB output shall be present when an AC input greater than the power supply turn on
voltage is applied.
3.3.3
Voltage Regulation
The power supply output voltages must stay within the following voltage limits when operating at
steady state and dynamic loading conditions. These limits include the peak-peak ripple/noise.
These shall be measured at the output connectors.
Table 20. Voltage Regulation Limits
Parameter
Min
Nom
Max
Unit
Tolerance
+12VSTB
+11.40V
+12.000V
+12.60V
Vrms
±5%
+12V
+11.40V
+12.000V
+12.60V
Vrms
±5%
The combined output continuous power of all outputs shall not exceed 3200W (1600W from
each power supply unit). Each output has a maximum and minimum current rating shown in
below table. The power supply shall meet both static and dynamic voltage regulation
requirements for the minimum dynamic loading conditions. The power supply shall meet only
the static load voltage regulation requirements for the minimum static load conditions.
3.3.4
Dynamic Loading
The output voltages shall remain within limits specified for the step loading and capacitive
loading specified in the table below. The load transient repetition rate shall be tested between
50Hz and 5kHz at duty cycles ranging from 10%-90%. The load transient repetition rate is only
a test specification. The  step load may occur anywhere within the MIN load to the MAX
load conditions.
Table 21 Transient Load Requirements
Output
+12VSTB
+12V
 Step Load Size
1.0A
60% of max load
Load Slew Rate
0.25 A/sec
0.25 A/sec
Test capacitive Load
20 F
2000 F
Note: For dynamic condition +12V min loading is 1A.
3.3.5
Capacitive Loading
The power supply must be stable and meet all requirements, with the following capacitive loading
conditions.
Table 22. Capacitive Loading Conditions
Output
+12V
Min
500
Max
25,000
Units
F
+12VSTB
20
3100
F
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3.3.6
Power Sub-System
Ripple/Noise
The maximum allowed ripple/noise output of the power supply is defined in below table. This is
measured over a bandwidth of 10Hz to 20MHz at the power supply output connectors. A 10F
tantalum capacitor in parallel with a 0.1F ceramic capacitor is placed at the point
of measurement.
Table 23. Ripple and Noise
+12V
120mVp-p
3.3.7
+12VSTB
120mVp-p
Grounding
The output ground of the pins of the power supply provides the output power return path. The
output connector ground pins shall be connected to the safety ground (power supply enclosure).
This grounding should be well designed to ensure passing the max allowed Common Mode
Noise levels.
The power supply shall be provided with a reliable protective earth ground. All secondary
circuits shall be connected to protective earth ground. Resistance of the ground returns to
chassis shall not exceed 1.0 m. This path may be used to carry DC current.
3.3.8
Closed Loop Stability
The power supply shall be unconditionally stable under all line/load/transient load conditions
including capacitive load ranges specified in Section 4.6. A minimum of: 45 degrees phase
margin and -10dB-gain margin is required. The power supply manufacturer shall provide proof
of the unit’s closed-loop stability with local sensing through the submission of Bode plots.
Closed-loop stability must be ensured at the maximum and minimum loads as applicable.
3.3.9
Residual Voltage Immunity in Standby Mode
The power supply should be immune to any residual voltage placed on its outputs (Typically a
leakage voltage through the system from standby output) up to 500mV. There shall be no
additional heat generated, nor stressing of any internal components with this voltage applied to
any individual or all outputs simultaneously. It also should not trip the protection circuits during
turn on.
The residual voltage at the power supply outputs for no load condition shall not exceed 100mV
when AC voltage is applied and the PSON# signal is de-asserted.
3.3.10
Common Mode Noise
The Common Mode noise on any output shall not exceed 350mVp-p over the frequency band
of 10Hz to 20MHz.
1. The measurement shall be made across a 100Ω resistor between each of DC outputs,
including ground at the DC power connector and chassis ground (power subsystem
enclosure).
2. The test set-up shall use a FET probe such as Tektronix model P6046 or equivalent.
3.3.11
Soft Starting
The Power Supply shall contain control circuit which provides monotonic soft start for its outputs
without overstress of the AC line or any power supply components at any specified AC line or
load conditions.
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3.3.12
Intel®Server System H2000LP Family TPS
Zero Load Stability Requirement
When the power subsystem operates in a no load condition, it does not need to meet the output
regulation specification, but it must operate without any tripping of over-voltage or other fault
circuitry. When the power subsystem is subsequently loaded, it must begin to regulate and
source current without fault.
3.3.13
Hot Swap Requirement
Hot swapping a power supply is the process of inserting and extracting a power supply from an
operating power system. During this process the output voltages shall remain within the limits
with the capacitive load specified. The hot swap test must be conducted when the system is
operating under static, dynamic, and zero loading conditions. The power supply shall use a
latching mechanism to prevent insertion and extraction of the power supply when the AC power
cord is inserted into the power supply.
3.3.14
Forced Load Sharing
The +12V output will have active load sharing. The output will share within 10% at full load. The
failure of a power supply should not affect the load sharing or output voltages of the other
supplies still operating. The supplies must be able to load share in parallel and operate in a hotswap/redundant 1+1 configurations. The 12VSBoutput is not required to actively share current
between power supplies (passive sharing). The 12VSBoutput of the power supplies are
connected together in the system so that a failure or hot swap of a redundant power supply
does not cause these outputs to go out of regulation in the system.
3.3.15
Timing Requirement
These are the timing requirements for the power supply operation. The output voltages must
rise from 10% to within regulation limits (Tvout_rise) within 5 to 70ms. For 12VSB, it is allowed to
rise from 1.0 to 25ms. All outputs must rise monotonically. Table below shows the timing
requirements for the power supply being turned on and off from the AC input, with PSON held
low and the PSON signal, with the AC input applied.
Table 24. Timing Requirement
Item
Tvout_rise
Output voltage rise time
MAX
70 *
UNITS
ms
T sb_on_delay
Delay from AC being applied to 12VSBbeing within regulation.
1500
ms
T ac_on_delay
Delay from AC being applied to all output voltages being within
regulation.
3000
ms
T vout_holdup
Time 12Vl output voltage stay within regulation after loss of
AC.
Delay from loss of AC to de-assertion of PWOK
Delay from PSON# active to output voltages within regulation
limits.
Delay from PSON# deactivate to PWOK being de-asserted.
T pwok_holdup
T
pson_on_delay
T pson_pwok
T pwok_on
T pwok_off
T pwok_low
Description
Delay from output voltages within regulation limits to PWOK
asserted at turn on.
Delay from PWOK de-asserted to output voltages dropping out
of regulation limits.
Duration of PWOK being in the de-asserted state during an
off/on cycle using AC or the PSON signal.
24
MIN
5.0 *
13
ms
10.6
5
3.4
100
ms
ms
400
5
500
ms
ms
1
ms
100
ms
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Intel®Server System H2000LP Family TPS
Item
T sb_vout
T
12VSB_holdup
Power Sub-System
Description
Delay from 12VSBbeing in regulation to O/Ps being in
regulation at AC turn on.
Time the 12VSBoutput voltage stays within regulation after loss
of AC.
MIN
50
MAX
1000
70
UNITS
ms
ms
Note: * The 12VSTB output voltage rise time shall be from 1.0ms to 25ms.
AC Input
Tvout_holdup
Vout
Tpwok_low
TAC_on_delay
Tsb_on_delay
Tpwok_off
Tpwok_on
PWOK
Tsb_on_delay
Tpwok_on
Tpwok_holdup
12Vsb
Tsb_vout
Tpwok_off
Tpson_pwok
T5Vsb_holdup
Tpson_on_delay
PSON
AC turn on/off cycle
PSON turn on/off cycle
Figure 14. Turn On/Off Timing (Power Supply Signals)
3.5
Power Supply Cold Redundancy Support
Power supplies that support cold redundancy can be enabled to go into a low-power state (that
is, cold redundant state) in order to provide increased power usage efficiency when system
loads are such that both power supplies are not needed. When the power subsystem is in Cold
Redundant mode, only the needed power supply to support the best power delivery efficiency is
ON. Any additional power supplies; including the redundant power supply, is in Cold
Standby state.
Each power supply has an additional signal that is dedicated to supporting Cold Redundancy;
CR_BUS. This signal is a common bus between all power supplies in the system. CR_BUS is
asserted when there is a fault in any power supply OR the power supplies output voltage falls
below the Vfault threshold. Asserting the CR_BUS signal causes all power supplies in Cold
Standby state to power ON.
Enabling power supplies to maintain best efficiency is achieved by looking at the Load Share
bus voltage and comparing it to a programmed voltage level from a PMBus* command.
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Whenever there is no active power supply on the Cold Redundancy bus driving a HIGH level on
the bus all power supplies are ON no matter their defined Cold Redundant roll (active or Cold
Standby). This guarantees that incorrect programming of the Cold Redundancy states of the
power supply will never cause the power subsystem to shut down or become over loaded. The
default state of the power subsystem is all power supplies ON. There needs to be at least one
power supply in Cold Redundant Active state or Standard Redundant state to allow the Cold
Standby state power supplies to go into Cold Standby state.
3.5.1
1200W CRPS Cold Redundancy
If the output power is less than 480W (40%). the Cold redundant function will be enable. Thus
you will see one PSU working normal. The second PSU will be CR mode. The Power Supply
LED is green blinking.
Table 25. 1200W CRPS Cold Redundancy Threshold
Cold
Standby 1
(02h)
3.5.2
Enable (V)
percent
power (W)
Disable (V)
percent
power (W)
3.2
40.00%
480(±5%)
1.44
18.00%
432(±5%)
1600W CRPS Cold Redundancy
If the output power is less than 640W (40%). the Cold redundant function will be enable. Thus
you will see one PSU working normal. The second PSU will be CR mode. The Power Supply
LED is green blinking.
Table 26. 1600W CRPS Cold Redundancy Threshold.
Cold
Standby 1
(02h)
3.6
Enable (V)
percent
power (W)
Disable (V)
percent
power (W)
3.2
40.00%
640(±5%)
1.44
18.00%
576(±5%)
Control And Indicator Functions
The following sections define the input and output signals from the power supply.
Signals that can be defined as low true use the following convention: Signal# = low true
3.6.1
PSON# Input Signal
#
The PSON signal is required to remotely turn on/off the power supply. PSON# is an active low
signal that turns on the +12V power rail. When this signal is not pulled low by the system, or left
open, the outputs (except the +12VSB) turn off. This signal is pulled to a standby voltage by a
pull-up resistor internal to the power supply. Refer to below table for the timing diagram.
Table 27. PSON# Signal Characteristics
Signal Type
#
PSON = Low
#
PSON = High or Open
Accepts an open collector/drain input from the system. Pull-up
to VSB located in power supply.
ON
OFF
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Power Sub-System
Signal Type
Accepts an open collector/drain input from the system. Pull-up
to VSB located in power supply.
MIN
MAX
0V
1.0V
2.0V
3.46V
4mA
5msec
400msec
50msec
Logic level low (power supply ON)
Logic level high (power supply OFF)
Source current, Vpson = low
Power up delay: Tpson_on_delay
PWOK delay: T pson_pwok
3.6.2
PWOK(power good) Output Signal
PWOK is a power OK signal and will be pulled HIGH by the power supply to indicate that all the
outputs are within the regulation limits of the power supply. When any output voltage falls below
regulation limits or when AC power has been removed for a time sufficiently long so that power
supply operation is no longer guaranteed, PWOK will be de-asserted to a LOW state. See the
table below for a representation of the timing characteristics of PWOK. The start of the PWOK
delay time shall inhibited as long as any power supply output is in current limit.
Table 28. PWOK Signal Characteristics
Signal Type
PWOK = High
PWOK = Low
Power OK
Power Not OK
Logic level low voltage, Isink=400uA
Logic level high voltage, Isource=200A
Sink current, PWOK = low
Source current, PWOK = high
PWOK delay: Tpwok_on
PWOK rise and fall time
Power down delay: T pwok_off
3.6.3
MIN
0V
2.4V
100ms
1ms
MAX
0.4V
3.46V
400uA
2mA
1000ms
100sec
200msec
SMBAlert# Signal
This signal indicates that the power supply is experiencing a problem that the user should
investigate. This shall be asserted due to Critical events or Warning events. The signal shall
activate in the case of critical component temperature reached a warning threshold, general
failure, over-current, over-voltage, under-voltage, failed fan. This signal may also indicate the
power supply is reaching its end of life or is operating in an environment exceeding the
specified limits.
This signal is to be asserted in parallel with LED turning solid Amber or blink Amber.
Table 29. SMBAlert# Signal Characteristics
Signal Type (Active Low)
Open collector/drain output from power supply. Pull-
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up to VSB located in system.
Alert# = High
OK
Alert# = Low
MIN
0V
Logic level low voltage, Isink=4 mA
Logic level high voltage, Isink=50 A
Sink current, Alert# = low
Sink current, Alert# = high
Alert# rise and fall time
3.7
Power Alert to system
MAX
0.4 V
3.46 V
4 mA
50 A
100 s
Protection circuits
Protection circuits inside the power supply shall cause only the power supply’s main outputs to
shut down. If the power supply latches off due to a protection circuit tripping, an AC cycle OFF
for 15sec and a PSON# cycle HIGH for 1sec shall be able to reset the power supply.
3.7.1
Current Limit (OCP)
The power supply shall have current limit to prevent the outputs from exceeding the values
shown in table below. If the current limits are exceeded the power supply shall shutdown and
latch off. The latch will be cleared by toggling the PSON# signal or by an AC power interruption.
The power supply shall not be damaged from repeated power cycling in this condition. 12VSB
will be auto-recovered after removing OCP limit.
Table 30. Over Current Protection
Output VOLTAGE
PSU SKU
+12V
+12VSTB
3.7.2
Input voltage range
90 – 264VAC
90 – 264VAC
OVER CURRENT LIMITS
1200W
1600W
140A min; 170A max
180A min; 200A max
2.5A min; 3A max
2.5A min; 3A max
Over Voltage Protection (OVP)
The power supply over voltage protection shall be locally sensed. The power supply shall
shutdown and latch off after an over voltage condition occurs. This latch shall be cleared by
toggling the PSON# signal or by an AC power interruption. The values are measured at the
output of the power supply’s connectors. The voltage shall never exceed the maximum levels
when measured at the power connectors of the power supply connector during any single point
of fail. The voltage shall never trip any lower than the minimum levels when measured at the
power connector. 12VSBwill be auto-recovered after removing OVP limit.
Table 31. Over Voltage Protection (OVP) Limits
Output Voltage
+12V
+12VSB
3.7.3
MIN (V)
13.3
13.3
MAX (V)
14.5
14.5
Over Thermal protection
The power supply will be protected against over temperature conditions caused by loss of fan
cooling or excessive ambient temperature. In an OTP condition the PSU will shut down. When
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Power Sub-System
the power supply temperature drops to within specified limits, the power supply shall restore
power automatically, while the 12VSB remains always on. The OTP circuit must have built in
margin such that the power supply will not oscillate on and off due to temperature recovering
condition. The OTP trip level shall have a minimum of 4C of ambient temperature margin.
3.8
PMBus*
The PMBus* features are requirements for power supply unit for use in server systems. This
specification is based on the PMBus* Specifications part I and II, revision 1.1. The power supply
device address locations are shown below:
Figure 15. Power Supply Device Address
The PMBus* from PDB is connected to BMC of all four nodes. Only one board BMC is assigned
to be the master BMC and communicate with PSU as single point. Other board BMCs receive
PSU data from the master BMC. In case the master BMC is down, one of the slave board BMC
will be promoted automatically as master BMC and maintain the communication.
3.8.1
PSU Address Lines A0
Address pins A0 is used by end use system to allocate unit address to a power supply in
particular slot position.
For redundant systems there are two signals to set the address location of the power supply
once it is installed in the system; Address0 and Address1. For non-redundant systems the
power supply device address locations should align with the Address0/Address1 location of 0/0.
Table 32. PSU addressing
PDB addressing Address0
0
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Intel®Server System H2000LP Family TPS
*
Power supply PMBus device
3.8.2
B0h
B2h
Accuracy
The sensor commands shall meet the following accuracy requirements. The accuracies shall be
met over the specified ambient temperature and the full range of rated input voltage.
Table 33. PMBus* Accuracy
Output Loading
10% - 20%
READ_PIN and READ_EIN
> 20% - 50%
See graphs below
READ_IOUT
+/-5%
+/-2%
READ_TEMPERATURE
+/-2%
+/- 3ºC
Accuracy, +/-W
Accuracy, +/-%
PMBus Input power monitoring accuracy
6.0%
25
5.0%
20
4.0%
15
3.0%
10
2.0%
Accuracy, +/- W
Accuracy, +/-%
> 50% - 100%
5
1.0%
950
1000
900
850
800
750
700
650
600
550
500
450
400
350
300
250
200
150
50
100
0
37.5
0.0%
Input power, W
Figure 16. PMBus* Monitoring Accuracy
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4.
Cooling Sub-System
Cooling Sub-System
The chassis cooling system contains the fan cooling sub-system of each node and common fan
cooling in the power supply units. Both node fans and PSU fans work together as thermal
solution to the chassis.
For each node, several components and configuration requirements make up the cooling subsystem. These include processors, chipsets, VR heatsinks, system fan module, CPU air duct,
and drive bay population. All are necessary to provide and regulate the air flow and air pressure
needed to maintain the system’s thermals when operating at or below the maximum specified
thermal limits.
In order to maintain the necessary airflow within the system, you must properly install the air
duct, HDD dummy carrier, PSU dummy filler and the top cover.
Each node uses a variable fan speed control engine to provide adequate cooling for the node
and whole system at various ambient temperature conditions, under various server workloads,
and with the least amount of acoustic noise possible. The fans operate at the lowest speed for
any given condition to minimize acoustics.
Note: The server system does not support redundant cooling fans. If any of the node fans fail,
you must power down the respective node as soon as possible to replace the fan.
4.1
Processor Heatsink
A heatsink is included in the system package. This heatsink is designed for optimal cooling and
performance. To achieve better cooling performance, you must properly attach the heatsink
bottom base with TIM (thermal interface material). ShinEtsu* G-751 or 7783D or Honeywell*
PCM45F TIM is recommended. The mechanical performance of the heatsink must satisfy
mechanical requirement of Intel® Xeon® E5-2400 series processors. To keep chipsets and VR
temperature at or below maximum temperature limit, the heatsink is required if necessary.
Figure 17. Processor Heatsink Overview
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Intel®Server System H2000LP Family TPS
Note: The passive heatsink is Intel® standard thermal solution for 1U/2U rack chassis.
4.2
Node cooling Fans
The cooling subsystem for each node consists of three 40 x 40 x 56 dual rotor fan, and CPU air
duct. These components provide the necessary cooling and airflow to the system node.
To maintain the necessary airflow within the system, the air duct and the top cover must be
properly installed.
Note: The Intel® Server System H2000LP Family does not support redundant cooling. If one of
the node fan fails, the respective node should be powered down as soon as possible to replace
the failed fan.
Each fan within the node is capable of supporting multiple speeds. Fan speed changes
automatically when internal ambient temperature of the system or processor temperature
changes. The fan speed control algorithm is programmed into the server board’s BIOS.
Each fan connector within the module supplies a tachometer signal that allows the BMC to
monitor the status of each fan. If one of the fans should fail, the system fault LED on front panel
will light.
The fan control signal is from BMC on mother board to Node Docking Board and then distribute
to three sets of dual rotor fans. See below for detail.
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Cooling Sub-System
Yellow Lines: fan cable connection
Red line: base board power cable connection
Blue line: fan control signal cable connection
Figure 18. Node Fan Set and power/control Connection
The fan connector pin-out definition is as follows:
Table 34. 8-pin Connector Pin-Out for Node Dual Rotor Fans
4.3
Pin
1
GND
Signal Name
Ground
Description
2
P12V
Power Supply +12 V
3
Tach1 Out
FAN_TACH1 signal output
4
PWM1 In
PWM1 signal input
5
GND
Ground
6
P12V
Power Supply +12 V
7
Tach2 Out
FAN_TACH2 signal output
8
PWM1 In
PWM1 signal input
Power Supply Fan
Each power supply module supports one non-redundant dual rotor 40 mm fan. The fans control
the cooling of the power supply and some drive bays. These fans are not replaceable. Therefore,
if a power supply fan fails, you must replace the power supply module.
4.4
Air Duct Module
Each node requires the use of an air duct module to direct airflow over critical areas within the
node. Before slide the node tray into chassis, make sure the air duct is installed properly.
Figure 19. Compute Node Air Duct
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4.5
Intel®Server System H2000LP Family TPS
Drive Bay Population Requirement
In order to maintain system thermal requirements, you must fully populate all hard drive bays.
Hard drive trays used for hot-swap drives must either have a hard drive installed or not have a
hard drive installed.
If only one power supply unit is used, a PSU dummy filler must be used to match the airflow
requirement.
IMPORTANT: If the drive bay is missing or not fully populated, the system will not meet the
thermal cooling requirements of the processor, which will most likely result in degraded
performance as a result of throttling or thermal shutdown of the system. It is recommended to
keep/apply the dummy plastic blocker(as shipped with HDD carrier) on any blank HDD carrier.
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5.
System Boards in the Node Tray
System Boards in the Node Tray
The Node tray includes mother board, node docking board, bridge board, and node fan set.
A
B
C
D
Node Docking Board
Node Fan Set
Bridge board
Baseboard
Figure 20. Compute Node Tray Overview
5.1
Node Docking Board
5.1.1
Overview of Node Docking Board
The Node Docking Board provides hot swap docking of 12V main power between the compute
node and the server. It supports three dual rotor fan connections, 12V main power hot swap
controller and current sensing. The HW Power Docking Board is intended to support the usage
of compute node of Intel® Server Board S2400LP family.
A
B
C
D
E
F
2x6 pin Minifit Jr main power output connector
8 pin connector for node fan 2
12 pin connector for main power input
8 pin connector for node fan 3
8 pin connector for node fan 1
2x7 pin fan control connector
Figure 21. Node Docking Board
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Intel®Server System H2000LP Family TPS
The Node Docking Board implements the below features:

Main 12V hot swap connectivity between compute node and chassis power.

Current sensing of 12V main power for use with node manager.

One 2x6pin mini-fit jr high current connectors for cabling to either the HW baseboard or
a GPGPU card. Different cable lengths will be needed for the different depth HW
baseboards.

2x7pin fan single connector, discrete cabled to the HW baseboard.

Three 8pin dual rotor fan connectors.

Four loose screws used to secure board to the compute node.
5.1.2
Pinout definition on Node Docking Board
Below is a list of connector type and pin definition on Node Docking Board.
Table 35. Main Power Input Connector
Pin
1
3
5
7
9
11
Signal Description
Pin
Lower Blade (Circuit 1)
GND
2
GND
4
GND
6
Upper Blade (Circuit 2)
P12V
8
P12V
10
P12V
12
Signal Description
GND
GND
GND
P12V
P12V
P12V
Table 36. Fan Control Signal Connector
Pin
1
3
5
7
9
11
13
Signal Description
PWM1
Tach0
Tach2
Tach4
NODE_ON
SMBUS_R4 CLK
NODE_ADR0
Pin
2
4
6
8
10
12
14
Signal Description
Reserved
Tach1
Tach3
Tach5
GND
SMBUS_R4 DAT
NODE_PWRGD
Table 37. Node Fan Connector
Pin
1
2
3
4
5
6
7
8
Signal Description
GND
P12V
TACH1
PWM1
GND
P12V
TACH2
PWM1
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System Boards in the Node Tray
Table 38. Main Power Output Connector
Pin
1
2
3
4
5
6
5.2
Signal Description
GND
GND
GND
GND
GND
GND
Pin
7
8
9
10
11
12
Signal Description
P12V_HS
P12V_HS
P12V_HS
P12V_HS
P12V_HS
P12V_HS
Bridge Board
5.2.1
Overview of Bridge Board
The Bridge Board is a common board across all baseboards going into the H2000LP serials
server chassis. The Bridge Board provides hot swap interconnect of all electrical signals to the
backplane of the server chassis (except for main 12V power). It supports up to 4x lanes of
SAS/SATA. One Bridge Board is used per one compute node. The Bridge Board is secured with
three loose screws to the compute node tray.
Figure 22. Bridge Board Overview
Bridge board passes all electrical connectivity through a 2x40pin card edge hot swap
interconnects between compute node and chassis backplane. The bridge board passes the
follow features (per compute node) to the backplane of the server:

4x 3Gb SAS/SATA ports for HSBP drives.

Four chassis ID signals to determine the physical location of the compute node.

One SGPIO SFF-8485 interface to the HSBP microcontroller.

5V_AUX power generated on HSBP and provided to the compute node.

3.3V power generated on HSBP and provided to bridge board to run SAS/SATA
re-drivers.

Global PMBus* alert signal for CLST support.
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
Intel®Server System H2000LP Family TPS
Four SMB bus interfaces:
o
SMBUS* R1 - For chassis temp sensor and chassis FRU EEPROM
device
o
SMBUS* R5 - Connectivity to up to two HSBP controllers and one
shared .12V current monitoring device.
o
SMBUS* R7 - Connectivity to up to two common redundant power supply
(CRPS) module PMBus*
o
IPMB - For OEM requirement not used on EPSD HW servers.
o
Front panel button signals: Power, reset, NMI, and ID.
o
Front panel LEDs signals: Power, fault, status, fabric activity, ID, HDD
activity
A
B
2x40 pin card edge connector (to backplane)
2x40 pin card edge connector (to baseboard slot))
Figure 23. Connectors on Bridge Board
5.2.2
Pinout definition on Bridge Board
The table below lists the connector type and pin definition for a Bridge Board.
Table 39. Card Edge Connector Pinout
Pin
1
3
5
7
9
11
13
15
17
19
21
Signal Description
5V Aux
GND
NODE_PRESENT_N
(GND)
ALL_NODE_OFF
spare
GND
IPMB-Data
IPMB-Clk
GND
Pin
2
4
6
8
10
12
14
16
18
20
22
Signal Description
5V Aux
GND
GND
GND
FP HDD_ACT_LED_N
FP Activity LED_N
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Pin
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
System Boards in the Node Tray
Signal Description
SMBUS_R1 DATA
SMBUS_R1 CLK
GND
SMBUS_R5 DATA
SMBUS_R5 CLK
GND
SMBUS_R7 DATA
SMBUS_R7 CLK
GND
PMBUS Alert_N
NODEx_ON_N
SGPIO DATA IN
SGPIO Data Out
SGPIO LD
SPKR
GND
SAS3_RX
SAS3_RX
GND
SAS2_TX
SAS2_TX
GND
SAS1_RX
SAS1_RX
GND
SAS0_TX
SAS0_TX
GND
P3V3 (HSBP Side) and
GND (HW Baseboard
Side)
Pin
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
Signal Description
FP Health LEDA_N
FP Health LEDG_N
FP PWR LED_N
FP ID LED_N
FP ID BTN_N
FP RST BTN_N
FP PWR BTN_N
FP NMI BTN_N
SPA_SOUT_N
SPA_SIN_N
ID3
ID2
ID1
ID0
SGPIO CLK
GND
SAS3_TX
SAS3_TX
GND
SAS2_RX
SAS2_RX
GND
SAS1_TX
SAS1_TX
GND
SAS0_RX
SAS0_RX
GND
P3V3 (HSBP Side) and
SATA_SAS_N (HW
Baseboard Side)
Table 40. 5V_AUX Power Connector Pinout
Pin
1
2
Signal Description
GND
P5V
Revision 1.0
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Hard Disk Drive Support
6.
Intel®Server System H2000LP Family TPS
Hard Disk Drive Support
The server system provides two SKUs to support different types of Hard Disk Drives (HDD):

H2312LP : Supports 12x 3.5" HDD

H2216LP : Supports 16x 2.5" HDD
6.1
Hard Disk Drive Bays Scheme
The server system H2000 chassis can support up to twelve carrier-mounted SATA/SAS 3.5-inch
hard disk drives, or sixteen carrier-mounted SATA/SAS 2.5-inch hard disk drives. The drives
may be “electrically” hot-swapped while the system power is applied, but you must take caution
before hot-swapping while the system is functioning under operating system/application control
or data may be lost.
Below are hard disk drive distribution schemes on different SKUs of H2000 chassis family.
Figure 24. HDD Scheme for H2312LPJR
Figure 25. HDD Scheme for H2216LPJR
Note: If a failed drive needs replacing, it is recommended you replace it with the same
manufacturer, model, and capacity.
6.2
Hard Drive Carrier
There are two types of HDD carriers for two chassis SKUs respectively:
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Hard Disk Drive Support
Figure 26. 3.5-inch HDD Assembly Overview
Figure 27. 2.5-inch HDD Assembly Overview
Hot-swap drive carriers make insertion and extraction of the drive from the system very simple.
Each type of drive carrier has its own latching mechanism, which is used to both insert and
extract drives from the chassis and lock the carrier in place. Each type of drive carrier supports
two light pipes to direct light from the drive status LEDs on the backplane to the carrier’s face
allowing it to be viewable from the front of the system.
6.3
Hot-Swap Hard Drive Support
Both the Intel® Server System H2312LPJR and H2216LPJR can support hot-swap SATA/SAS
hard drives. Hard drives interface with the passive backplane through a blind mate connection
when drives are installed into a hard drive bay using hot-swap drive carriers.
The passive backplane acts as an intermediate pass-through interface board where SATA/SAS
ports of SCU0 from server board are hard wired to the backplane. The on board Intel® C600
Chipset (PCH) provides the necessary drive interface.
Each compute node in the system has dedicated Hot Swap Controller (HSC) to manage three
or four HDDs. There are totally four sets of independent Programmable System On Chip (PSOC)
on the backplane, to function as HSC respectively to four compute nodes.
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Intel®Server System H2000LP Family TPS
The following sections describe the feature and connections between the backplane and server
board.
6.3.1





Backplane Feature set:
Common HSBP Microcontroller Cypress* PSoC 1 part
H2312LPJR: 12x SAS/SATA 3.5" HDDs at 3Gb/s SAS/SATA or slower speeds, divided
into 4 groups of three hot swap hard drives. Each HDD group is associated with one of
the four compute nodes respectively in the 2U chassis.
H2216LPJR: 16x SAS/SATA 2.5" HDDs at 3Gb/s SAS/SATA or slower speeds, divided
into 4 groups of four hot swap hard drives. Each HDD group is associated with one of
the four compute nodes respectively in the 2U chassis.
One SGPIO SFF-8485 interface per compute node, total of four SGPIO on the
backplane.
Three SMB interfaces supported on the HSBP:
o
SMBUS* R1 - For chassis temp sensor and chassis FRU EEPROM
device.
o
SMBUS* R5 - Connectivity to up to two HSBP controllers and one shared
12V current monitoring device.
o










SMBUS* R7 - Connectivity to up to two common redundant power supply
(CRPS) module PMBus*.
Integrated front panel control connectors
Status LED and Activity LED for each hard disk drive.
5V_AUX switcher regulator (from 12V and 12VSB) for HDD power and for compute
nodes.
Each grouping of HDD slots has switches for 5V and 12V power, only when
corresponding compute node is plugged in and operating will power be provided to the
HDDs.
3.3V switcher regulator (from 12V) to power microcontroller, SAS/SATA re-drivers on the
bridge board and various other components.
3.3V_AUX linear regulator (from 5V_AUX) for temp sensor, and chassis FRU EEPROM
located on the HSBP.
Four 80-pin bridge board connectors, one per compute node.
Four compute node main power connectors, one per compute node.
Four 2x9pin power cable connections and one 2x9pin power control cable connections.
These cables are routing to two power distribution boards (PDB).
Shared speaker for all compute nodes.
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6.3.2
Hard Disk Drive Support
Backplane Block Diagram
Figure 28. Passive Backplane Block Diagram (for one node)
6.3.3
3.5” Hot Swap Backplane Connector scheme
The following diagrams show the layout of major components and connectors for 3.5" Hot
Swap backplane.
A
SATA/SAS connectors for Node 1
B
SATA/SAS connectors for Node 2
C
SATA/SAS connectors for Node 3
D
SATA/SAS connectors for Node 4
Figure 29. 3.5" Backplane Component and Connectors (Front View)
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Intel®Server System H2000LP Family TPS
A
20-pin Front Panel cable connector for Node 2, 4
B
2Blade Compute Node Power connector for Node 4
C
2x40 pin Bridge Board connector for Node 4
D
2x9 pin Power supply input connector
E
2x9 pin Power supply input connector
F
2x7 pin Power Control cable connector
G
2Blade Compute Node Power connector for Node 3
H
2x40 pin Bridge Board connector for Node 3
I
2x40 pin Bridge Board connector for Node 1
J
20-pin Front Panel cable connector for Node 1, 3
K
2Blade Compute Node Power connector for Node 1
L
2x9 pin Power supply input connector
M
2x9 pin Power supply input connector
N
2x40 pin Bridge Board connector for Node 2
O
2Blade Compute Node Power connector for Node 2
Figure 30. 3.5" Backplane Component and Connectors (Back View)
6.3.4
2.5" Hot Swap Backplane Connector scheme
The following diagrams show the layout of major components and connectors for 2.5" Hot Swap
backplane.
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Hard Disk Drive Support
A
SATA/SAS connectors for Node 1
B
SATA/SAS connectors for Node 2
C
SATA/SAS connectors for Node 3
D
SATA/SAS connectors for Node 4
Figure 31. 2.5" Backplane Component and Connectors (Front View)
A
2Blade Compute Node Power connector for Node 4
B
2x40 pin Bridge Board connector for Node 4
C
2x9 pin Power supply input connector
D
2x7 pin Power Control cable connector
E
2x9 pin Power supply input connector
F
2Blade Compute Node Power connector for Node 3
G
2x40 pin Bridge Board connector for Node 3
H
2x40 pin Bridge Board connector for Node 1
I
20-pin Front Panel cable connector for Node 1, 3
J
2Blade Compute Node Power connector for Node 1
K
2x9 pin Power supply input connector
L
2x9 pin Power supply input connector
M
2x40 pin Bridge Board connector for Node 2
N
2Blade Compute Node Power connector for Node 2
O
20-pin Front Panel cable connector for Node 2, 4
Figure 32. 2.5" Backplane Component and Connectors (Back View)
6.3.5
Backplane LED Support
The backplanes support both HDD online and activity/fault LEDs for each of the hard drive
connectors. A light duct in HDD tray is used to conduct LED light to front panel. The following
lists LED functionality.
Revision 1.0
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Hard Disk Drive Support
Intel®Server System H2000LP Family TPS
Figure 33. Hard Drive Carrier LED
General HDD LED functionality is displayed below:
Table 41. Hard Drive Carrier Status LED Functions
Amber
Off
Solid On
Blink
No access and no fault
Hard Drive Fault has occurred
Raid rebuild in progress (1hz) Identify (2hz)
Table 42. Hard Drive Carrier Activity LED Functions
Condition
Power on with no drive activity.
Power on with drive activity.
Green
Power on and drive spun down.
Power on and drive spinning up.
6.3.6
Drive Type
SAS
SATA
SAS
SATA
SAS
SATA
SAS
SATA
Behavior
LED stays on
LED stays off
LED blinks off when processing a command
LED blinks off when processing a command
LED stays off
LED stays off
LED blinks
LED stays off
Backplane Connector Definition
The backplanes include several different connectors. This section defines the purpose and pin
out associated with each.
1.
2x9 Pin Power Input Connector
The backplane is powered by +12V and +12VSTB from PDB of CRPS. The input power is
distributed by backplane to all four nodes.
Table 43. Backplane Input Power Connector Pin-out
Pin
2
4
6
8
10
12
Signal Description
P12V
P12V
P12V
P12V
P12V
P12V
Pin
1
3
5
7
9
11
46
Signal Description
GND
GND
GND
GND
GND
GND
Revision 1.0
Intel order number: G59328-001
Intel®Server System H2000LP Family TPS
Pin
14
16
18
2.
Hard Disk Drive Support
Signal Description
P12V
P12V
P12V
Pin
13
15
17
Signal Description
GND
GND
GND
2-Blade Compute Node Power Connector
The backplane provides main power to compute node through 2Blade power connector.
Table 44. 2-Blade Compute Node Power Connector Pin-out
Pin
1
3
5
7
9
11
13
15
3.
Signal Description
Pin
Lower Blade (Circuit 1)
GND
2
GND
4
GND
6
GND
8
Upper Blade (Circuit 2)
P12V
10
P12V
12
P12V
14
P12V
16
Signal Description
GND
GND
GND
GND
P12V
P12V
P12V
P12V
2x40 Pin Bridge Board Connector
The Compute Node provides four SATA/SAS ports (in SCU0) to backplane, together with front
panel control signals and SMBus*.
Table 45. 2x40 Pin Connector Pin-out for Node Bridge Board
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
Signal Description
5V_AUX
GND
NODE_Present_N (GND)
ALL_NODE_OFF
spare
GND
IPMB-Data
IPMB-Clk
GND
SMBUS_R1 DATA
SMBUS_R1 CLK
GND
SMBUS_R5 DATA
SMBUS_R5 CLK
GND
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
Signal Description
5V_AUX
GND
GND
GND
FP HDD_ACT_LED_N
FP Activity LED_N
FP Health LEDA_N
FP Health LEDG_N
FP PWR LED_N
FP ID LED_N
FP ID BTN_N
FP RST BTN_N
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Pin
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
4.
Intel®Server System H2000LP Family TPS
Signal Description
SMBUS_R7 DATA
SMBUS_R7 CLK
GND
PMBUS Alert_N
NODEx_ON_N
SGPIO DATA IN
SGPIO Data Out
SGPIO LD
SPKR
GND
SAS3_RX
SAS3_RX
GND
SAS2_TX
SAS2_TX
GND
SAS1_RX
SAS1_RX
GND
SAS0_TX
SAS0_TX
GND
3.3V
Pin
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
Signal Description
FP PWR BTN_N
FP NMI BTN_N
SPA_SOUT_N
SPA_SIN_N
ID3
ID2
ID1
ID0
SGPIO CLK
GND
SAS3_TX
SAS3_TX
GND
SAS2_RX
SAS2_RX
GND
SAS1_TX
SAS1_TX
GND
SAS0_RX
SAS0_RX
GND
3.3V
20-Pin Front Panel Connector
The backplanes provide connectors for front panel control signals. Each connector integrates
the control signals of two compute nodes.
Table 46. Front Panel Connector Pin-out
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal Description
GND
FP1_PWR_BTN_N
FP1_RST_BTN_N
FP1_ID_BTN_N
P5VSB
FP1_PWR_LED_N
FP1_HEALTH_LEDG_N
FP1_HEALTH_LEDA_N
FP1_ACTIVITY_LED_N
FP1_ID_LED_N
GND
FP2_PWR_BTN_N
FP2_RST_BTN_N
FP2_ID_BTN_N
P3V3SB
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Hard Disk Drive Support
Pin
16
17
18
19
20
5.
Signal Description
FP2_PWR_LED_N
FP2_HEALTH_LEDG_N
FP2_HEALTH_LEDA_N
FP2_ACTIVITY_LED_N
FP2_ID_LED_N
2x7 Pin Power Supply Control Signal Connector
The backplanes provide power supply control signals, together with PMBus* functionality
integrated.
Table 47. Power Supply Control Connector Pin-out
Pin
1
3
5
7
9
11
13
Signal Description
SMBUS_R7_DATA
SMBUS_R7_CLK
PMBUS_ALERT_N
PWROK
Reserved
PDU1-12VSB
PDU2-12VSB
Pin
2
4
6
8
10
12
14
Revision 1.0
Signal Description
A0
PSON_N
12V RS_RTN
12V RS
PDU1-12VSB
PDU2-12VSB
Reserved
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7.
Front Panel Control and Indicators
Front Panel Control and Indicators
The Intel® Server System H2000LP family Front Control Panel is integrated with rack handles at
the both sides of the chassis. Each control panel contains two sets of node control buttons and
status LEDs. The control panel assembly is pre-assembled and fixed with the rack handles.
A
B
C
D
System Power Button with LED
System ID LED Button
System Status LED
Network Link/Activity LED
Figure 34. Front Control Panel
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Front Panel Control and Indicators
7.1
Intel®Server System H2000LP Family TPS
Control Panel Button
The following table lists the control panel features and functions. The control panels features a
system power button.
Table 48. Front Control Button Function
Feature
Power Button with Power LED
System ID Button with ID LED
7.2
Function
Toggles the system power on/off. This button also integrates the power
LED.
Toggles between ID LED on and off
Control Panel LED Indicators
The control panel houses independent two LEDs and two button integrated LEDs for each node,
which are viewable to display the system’s operating status. The following table identifies each
LED and describes their functionality.
Table 49. Front LED Indicator Functions
LED Indicator
Power
Network LED
System Status
Color
Condition
Green
Green
Green
Green
Green
Green
On
Blink
Off
On
Blink
Off
On
Blink
Amber
On
Amber
Blink
-
Off
What it describes
Power On/ACPI S0 state
Sleep /ACPI S1 state
Power Off /ACPI S5 state
LAN Link no Access
LAN Activity
No Link or no access
System Ready/No Alarm
System ready, but degraded: redundancy lost such
as the power supply or fan failure; non-critical
temp/voltage threshold; battery failure; or predictive
power supply failure.
Critical Alarm: Critical power modules failure, critical
fans failure, voltage (power supply), critical
temperature and voltage
Non-Critical Alarm: Redundant fan failure, redundant
power module failure, non-critical temperature and
voltage
Power off: System unplugged
Power on: System powered off and in standby, no
prior degraded\non-critical\critical state
Notes:
1.
2.
3.
4.
Blink rate is ~1 Hz at 50% duty cycle.
It is also off when the system is powered off (S5) or in a sleep state (S1).
The power LED sleep indication is maintained on standby by the chipset. If the system is powered down
without going through the BIOS, the LED state in effect at the time of power off is restored when the system
is powered on until the BIOS clear it.
If the system is not powered down normally, it is possible the Power LED will blink at the same time the
system status LED is off due to a failure or configuration change that prevents the BIOS from running.
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7.2.1
Front Panel Control and Indicators
Power/Sleep LED
Table 50. Power LED Operation
State
Power Off
Power On
Power Mode
Non-ACPI
Non-ACPI
LED
Off
Solid On
S5
ACPI
Off
S1 Sleep
ACPI
Blink
S0
ACPI
Solid On
Description
System power is off and the BIOS has not initialized the chipset.
System power is on but the BIOS has not yet initialized the
chipset.
Mechanical is off and the operating system has not saved any
context to the hard disk.
DC power is still on. The operating system has saved context and
gone into a level of low-power state.
System and the operating system are up and running.
Note: Blink rate is ~ 1Hz at 50% duty cycle.
7.2.2
System Status LED
Table 51. System Status LED Operation
Color
Off
State
N/A
Criticality
Not ready
Description
Power off or BMC initialization completes if no degraded, noncritical, critical, or non-recoverable conditions exist after power cable
plug in
Green/
Amber
Both Solid
On
Not ready
Pre DC Power On – 15-20 second BMC Initialization when AC is
applied to the server. The system will not POST until BMC
initialization completes.
Green
Solid on
Ok
System ready
Green
Blink
Degraded
BIOS detected
1. Unable to use all of the installed memory (more than one DIMM
1
installed).
2. In a mirrored configuration, when memory mirroring takes place
and system loses memory redundancy. This is not covered by
1
(2).
3. PCI Express* correctable link errors.
Integrated BMC detected
1. One of redundant power supplies not present.
2. CPU disabled – if there are two CPUs and one CPU is disabled.
3. Fan alarm – Fan failure. Number of operational fans should be
more than minimum number needed to cool the system.
4. Non-critical threshold crossed – Temperature, voltage, power
nozzle, power gauge, and PROCHOT2 (Therm Ctrl) sensors.
5. Battery failure.
6. Predictive failure when the system has redundant power
supplies.
Amber
Blink
Non-critical
Non-fatal alarm – system is likely to fail
BIOS Detected
1.
2.
In non-mirroring mode, if the threshold of ten correctable errors
1
is crossed within the window.
PCI Express* uncorrectable link errors.
Integrated BMC Detected
1.
Critical threshold crossed – Voltage, temperature, power nozzle,
power gauge, and PROCHOT (Therm Ctrl) sensors.
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Front Panel Control and Indicators
Color
State
Intel®Server System H2000LP Family TPS
Criticality
2.
3.
4.
Amber
Solid on
Description
VRD Hot asserted.
One of the redundant power supplies failed.
Minimum number of fans to cool the system are not present or
have failed.
Fatal alarm – system has failed or shutdown
Critical, nonrecoverable
BIOS Detected
1.
DIMM failure when there is one DIMM present and no good
1
memory is present.
1
2. Run-time memory uncorrectable error in non-redundant mode.
3. CPU configuration error (for instance, processor stepping
mismatch).
Integrated BMC Detected
1.
2.
3.
4.
5.
CPU CATERR signal asserted.
CPU 1 is missing.
CPU THERMTRIP.
System cooling fan failure.
No power good – redundant power fault.
- Power Unit Redundancy sensor – Insufficient resources
offset (indicates not enough power supplies are present).
Notes:
1.
The BIOS detects these conditions and sends a Set Fault Indication command to the Integrated BMC to
provide the contribution to the system status LED.
2. Blink rate is ~ 1Hz at 50% duty cycle.
7.2.3
System Status LED – BMC Initialization
When power is first applied to the system and 5V-STBY is present, the BMC controller on the
server board requires 15-20 seconds to initialize. During this time, the system status LED will be
solid on, both amber and green. Once BMC initialization has completed, the status LED will stay
green solid on. If power button is pressed before BMC initialization completes, the system will
not boot to POST.
Revision 1.0
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8.
Configuration Jumpers
Configuration Jumpers
The following table provides a summary and description of configuration, test, and debug
jumpers on the Intel® Server Board S2400LP, which is used in Intel® Server System H2000LP
Family as Compute Node.
Figure 35.Jumper Locations and Functions
Table 52. Force Integrated BMC Update Jumper
Jumper Name
J9C2: BMC Force
Update jumper
Jumper Position
1-2
Mode of Operation
Normal
Normal mode
Note
2-3
Update
BMC in force update mode
J9F2: BIOS Recovery
Mode
1-2
Normal
Normal mode, password in protection
2-3
Recovery
BIOS in recovery mode
J6E1: Password Clear
2-4
Normal
Normal mode
4-6
Update
ME in force update mode
10-12
Normal
Normal mode
8-10
Recovery
BIOS in recovery mode
1-3
Normal
Normal mode
3-5
Clear BIOS
Settings
BIOS settings are reset to factory default
J6E1: ME Force Update
J6E1: BIOS Default
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Configuration Jumpers
8.1
Intel®Server System H2000LP Family TPS
Force BMC Update (J9C2)
When performing a standard BMC firmware update procedure, the update utility places the
BMC into an update mode, allowing the firmware to load safely onto the flash device. In the
unlikely event the BMC firmware update process fails due to the BMC not being in the proper
update state, the server board provides a BMC Force Update jumper (J9C2) which will force the
BMC into the proper update state. The following procedure should be followed in the event the
standard BMC firmware update process fails.
Table 53. Force Integrated BMC Update Jumper
Jumper Position
1-2
2-3
Mode of Operation
Normal
Update
Note
Normal Operation
BMC in force update mode
Steps to perform the Force Integrated BMC Update:
1. Power down and remove the AC power cord.
2. Open the server chassis. See your server chassis documentation for instructions.
3. Move jumper from the default operating position, covering pins1 and 2, to the enabled
position, covering pins 2 and 3.
4. Close the server chassis.
5. Reconnect the AC cord and power up the server.
6. Perform the BMC firmware update procedure as documented in the ReleaseNote.TXT
file included in the given BMC firmware update package. After successful completion of
the firmware update process, the firmware update utility may generate an error stating
the BMC is still in update mode.
7. Power down and remove the AC power cord.
8. Open the server chassis.
9. Move the jumper from the enabled position, covering pins 2 and 3 to the disabled
position, covering pins 1 and 2.
10. Close the server chassis.
11. Reconnect the AC cord and power up the server.
Note: Normal BMC functionality is disabled with the Force BMC Update jumper is set to the
enabled position. You should never run the server with the BMC Force Update jumper set in this
position. You should only use this jumper setting when the standard firmware update process
fails. This jumper should remain in the default/disabled position when the server is
running normally.
The server board has several 3-pin jumper blocks that can be used to configure, protect, or
recover specific features of the server board.
8.2
BIOS Recovery Mode (J9F2)
The Intel® Server Board S2400LP uses BIOS recovery to repair the system BIOS from flash
corruption in the main BIOS and Boot Block. This 3-pin jumper is used to reload the BIOS when
the image is suspected to be corrupted. For directions on how to recover the BIOS, refer to the
specific BIOS release notes.
Revision 1.0
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Configuration Jumpers
Table 54. BIOS Recovery Mode Jumper
Jumper
Position
1-2
2-3
Mode of
Operation
Normal
Normal mode
Recovery
BIOS in recovery mode
Note
You can accomplish a BIOS recovery from the SATA CD and USB Mass Storage device.
Please note that this platform does not support recovery from a USB floppy.
The recovery media must contain the following files under the root directory:
1.
2.
3.
4.
RML.ROM
UEFI iFlash32 11.0 Build 2 (including iFlash32.efi and ipmi.efi)
*Rec.CAP
Startup.nsh (update accordingly to use proper *Rec.CAP file)
The BIOS starts the recovery process by first loading and booting to the recovery image file
(RML.ROM) on the root directory of the recovery media (USB disk). This process takes place
before any video or console is available. Once the system boots to this recovery image file
(FVMAIN.FV), it boots automatically into the EFI Shell to invoke the Startup.nsh script and start
the flash update application (IFlash32.efi). IFlash32.efi requires the supporting BIOS Capsule
image file (*Rec.CAP).
After the update is complete, a message displays, stating the “BIOS has been updated
successfully”. This indicates the recovery process is finished.
The user should then switch the recovery jumper back to normal operation and restart the
system by performing a power cycle.
The following steps demonstrate this recovery process:
1. Power OFF the system.
2. Insert recovery media.
3. Switch the recovery jumper. Details regarding the jumper ID and location can be obtained
from the Board EPS for that Platform.
4. Power ON the system.
5. The BIOS POST screen will appear displaying the progress, and the system automatically
boots to the EFI SHELL.
6. The Startup.nsh file executes, and initiates the flash update (IFlash32.efi) with a new
capsule file (*Rec.CAP). The regular iFlash message displays at the end of the process—
once the flash update succeeds.
7. Power OFF the system, and revert the recovery jumper position to "normal operation".
8. Power ON the system.
Do NOT interrupt the BIOS POST during the first boot.
8.3
Password Clear (J6E1)
The user sets this 3-pin jumper to clear the password.
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Revision 1.0
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Configuration Jumpers
Intel®Server System H2000LP Family TPS
Table 55. Password Clear Jumper
Jumper Position
2-4
4-6
Mode of Operation
Normal
Note
Normal mode, password in protection
Clear Password
BIOS password is cleared
Steps to clear the BIOS password:
1. Power down server. Do not unplug the power cord.
2. Open the chassis. For instructions, see your server chassis documentation.
3. Move jumper (J6E1) from the default operating position, covering pins 1 and 2, to the
password clear position, covering pins 2 and 3.
4. Close the server chassis.
5. Power up the server, wait 10 seconds or POST completes.
6. Power down the server.
7. Open the chassis and move the jumper back to default position, covering pins 1 and 2.
8. Close the server chassis.
9. Power up the server.
8.4
Force ME Update (J6E1)
When this 3-pin jumper is set, it manually puts the ME firmware in update mode, which enables the user
to update ME firmware code when necessary.
Table 56. Force ME Update Jumper
Jumper Position
10-12
8-10
Mode of
Operation
Normal
Normal operation
Update
ME in force update mode
Note
Note: Normal ME functionality is disabled with the Force ME Update jumper is set to the
enabled position. You should never run the server with the ME Force Update jumper set in this
position. You should only use this jumper setting when the standard firmware update process
fails. This jumper should remain in the default/disabled position when the server is
running normally.
Steps to perform the Force ME Update:
1.
Power down and remove the AC power cord.
2.
Open the server chassis. For instructions, see your server chassis documentation.
3.
Move jumper from the default operating position (covering pins 1 and 2) to the enabled
position (covering pins 2 and 3).
4.
Close the server chassis.
5.
Reconnect the AC cord and power up the server.
6.
Perform the ME firmware update procedure as documented in the README.TXT file
that is included in the given ME firmware update package (same package as BIOS).
7.
Power down and remove the AC power cord.
8.
Open the server chassis.
Revision 1.0
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Intel order number: G59328-001
Intel®Server System H2000LP FamilyTPS
9.
Configuration Jumpers
Move jumper from the enabled position (covering pins 2 and 3) to the disabled position
(covering pins 1 and 2).
10. Close the server chassis.
8.5
Password Clear (J6E1)
This 3-pin jumper is used to clear the BIOS password.
Table 57. BIOS Password Clear Jumper
Jumper Position
2-4
4-6
Mode of Operation
Normal
Clear Password
Note
Normal mode, password in protection
BIOS password is cleared
Steps to perform the password clear:
1.
2.
3.
4.
5.
6.
7.
8.
9.
8.6
Power down server. Do not unplug the power cord.
Open the chassis. For instructions, see your server chassis documentation.
Move jumper (J6E1) from the default operating position, covering pins 2 and 4, to the
password clear position, covering pins 4 and 6.
Close the server chassis.
Power up the server, wait 10 seconds or POST completes.
Power down the server.
Open the chassis and move the jumper back to default position, covering pins 2 and 4.
Close the server chassis.
Power up the server. The password is now cleared and you can reset it by going into
the BIOS setup. The BIOS password is now cleared.
Force ME Update (J6E1)
When this 3-pin jumper is set, it manually puts the ME firmware in update mode, which enables the user
to update ME firmware code when necessary.
Table 58. Force ME Update Jumper
Jumper Position
10-12
8-10
Mode of
Operation
Normal
Normal operation
Update
ME in force update mode
Note
Note: Normal ME functionality is disabled with the Force ME Update jumper is set to the
enabled position. You should never run the server with the ME Force Update jumper set in this
position. You should only use this jumper setting when the standard firmware update process
fails. This jumper should remain in the default/disabled position when the server is
running normally.
Steps to perform the Force ME Update:
1.
Power down and remove the AC power cord.
2.
Open the server chassis. For instructions, see your server chassis documentation.
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Configuration Jumpers
Intel®Server System H2000LP Family TPS
3.
Move jumper from the default operating position (covering pins 10 and 12) to the
enabled position (covering pins 8 and 10).
4.
Close the server chassis.
5.
Reconnect the AC cord and power up the server.
6.
Perform the ME firmware update procedure as documented in the README.TXT file
that is included in the given ME firmware update package (same package as BIOS).
7.
Power down and remove the AC power cord.
8.
Open the server chassis.
9.
Move jumper from the enabled position (covering pins 8 and 10) to the disabled position
(covering pins 10 and 12).
10. Close the server chassis.
The password is now cleared and you can reset it by going into the BIOS setup.
8.7
Reset BIOS Settings (J6E1)
This jumper used to be the CMOS Clear jumper. The BIOS has moved CMOS data to the
NVRAM region of the BIOS flash since the previous generation. The BIOS checks during boot
to determine if the data in the NVRAM must be set to default.
Table 59. Reset BIOS Jumper
Jumper Position
1-3
Mode of Operation
Normal
3-5
Reset BIOS Configuration
Note
These pins should have a jumper in place for normal
system operation. (Default)
If these pins 3-5 are connected with AC power plugged,
the CMOS settings are cleared within five seconds.
These pins should not be connected for normal
operation.
Steps to reset the BIOS settings to default:
1. Power down server. Do not unplug the power cord.
2. Open the server chassis. For instructions, see your server chassis documentation.
3. Move jumper (J1D5) from the default operating position, covering pins 1 and 3, to the
reset/clear position, covering pins 3 and 5.
4. Wait five seconds.
5. Remove AC power.
6. Move the jumper back to default position, covering pins 1 and 3.
7. Close the server chassis.
8. Power up the server.
The BIOS settings are now cleared and you can reset it by going into the BIOS setup.
Revision 1.0
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Intel®Server System H2000LP FamilyTPS
Configuration Jumpers
Note: Removing AC Power before performing the BIOS settings Clear operation causes the
system to automatically power up and immediately power down, after the procedure is followed
and AC power is re-applied. If this happens, remove the AC power cord again, wait 30 seconds,
and re-install the AC power cord. Power-up the system and proceed to the <F2> BIOS Setup
Utility to reset the desired settings.
60
Revision 1.0
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PCI Express* Riser Card and Assembly
9.
Intel®Server System H2000LP Family TPS
PCI Express* Riser Card and Assembly
Each compute node in Intel® Server System H2000LP Family includes two PCI Express* riser
slots that accepts dedicated PCI Express* x16 Gen3 Risers to support low profile add-in card
and Intel® IO module. Riser Slot 1 and Riser Slot 2 are available for risers. The PCI Express*
slot on riser also accommodates PCI Express* x8, x4, and x1 adapters.
9.1
PCI Express* Riser for Slot 1
9.1.1
Overview of PCI-Express Riser
Riser slot 1 on baseboard provides standard PCI Express* x16 Gen3 signals(PCI Express* x8
Gen3 for IB sku), together with specific power pins to support high-power Graphic/GPGPU addin card.
Note: Riser Slot 1 on baseboard only supports Intel® 1U/2U Risers. It will cause damage to any
PCI-E based add-in card, which is directly plugged into the Riser Slot 1 on baseboard.
Figure 36. PCI Express* Riser for Riser Slot 1
9.1.2
Pinout definition on Slot 1 Riser
Below is a list of pin definition on Slot 1 Riser.
Table 60. Riser Card Edge Pinout
Pin
Pin Name
Description
Pin
Pin Name
Description
B1
12V
20W 3.3V generated on riser
A1
12V
20W 3.3V generated on riser
B2
12V
66W for GPU
A2
12V
66W for GPU
B3
12V
66W for GPU
A3
12V
66W for GPU
B4
12V
66W for GPU
A4
SMDATA
Revision 1.0
61
Intel order number: G59328-001
Intel®Server System H2000LP FamilyTPS
Pin
Pin Name
B5
SMCLK
B6
3.3VAUX
B7
PCI Express* Riser Card and Assembly
Description
Pin
Pin Name
Description
A5
3.3VAUX
For wake on LAN
A6
GPU_NODE_ON
can turn of 2U GPU power
GND
A7
GPU_PWRGD
B8
Tach9
A8
Tach11
B9
Tach8
A9
Tach10
B10
Tach7
A10
Tach6
B11
Spare
A11
Spare
B12
Spare
A12
PWM2
B13
Spare
A13
GND
B14
GND
A14
PERST#
B15
SMBUS_R4
CLK
A15
WAKE#
B16
SMBUS_R4
DAT
A16
GND
B17
GND
A17
REFCLK+
Clock pair 1
B18
PETxP0
Tx Lane 0+
A18
REFCLK-
Clock pair 1
B19
PETxN0
Tx Lane 0-
A19
GND
B20
GND
A20
PERxP0
Rx Lane 0+
B21
GND
A21
PERxN0
Rx Lane 0-
B22
PETxP1
Tx Lane 1+
A22
GND
B23
PETxN1
Tx Lane 1-
A23
GND
B24
GND
A24
PERxP1
Rx Lane 1+
B25
GND
A25
PERxN1
Rx Lane 1-
B26
PETxP2
Tx Lane 2+
A26
GND
B27
PETxN2
Tx Lane 2-
A27
GND
B28
GND
A28
PERxP2
Rx Lane 2+
B29
GND
A29
PERxN2
Rx Lane 2-
B30
PETxP3
Tx Lane 3+
A30
GND
B31
PETxN3
Tx Lane 3-
A31
GND
B32
GND
A32
PERxP3
Rx Lane 3+
B33
GND
A33
PERxN3
Rx Lane 3-
B34
PETxP4
Tx Lane 4+
A34
GND
B35
PETxN4
Tx Lane 4-
A35
GND
B36
GND
A36
PERxP4
Rx Lane 4+
B37
GND
A37
PERxN4
Rx Lane 4-
B38
PETxP5
Tx Lane 5+
A38
GND
B39
PETxN5
Tx Lane 5-
A39
GND
B40
GND
A40
PERxP5
Rx Lane 5+
B41
GND
A41
PERxN5
Rx Lane 5-
B42
PETxP6
Tx Lane 6+
A42
GND
B43
PETxN6
Tx Lane 6-
A43
GND
B44
GND
A44
PERxP6
For wake on LAN
KEY
62
GPU Fan speed control
Rx Lane 6+
Revision 1.0
Intel order number: G59328-001
PCI Express* Riser Card and Assembly
Pin
Pin Name
Intel®Server System H2000LP Family TPS
Description
Pin
Pin Name
Description
B45
GND
A45
PERxN6
B46
PETxP7
Tx Lane 7+
A46
GND
B47
PETxN7
Tx Lane 7-
A47
GND
B48
GND
A48
PERxP7
Rx Lane 7+
B49
GND
A49
PERxN7
Rx Lane 7-
B50
PETxP8
Tx Lane 8+
A50
GND
B51
PETxN8
Tx Lane 8-
A51
GND
B52
GND
A52
PERxP8
Rx Lane 8+
B53
GND
A53
PERxN8
Rx Lane 8-
B54
PETxP9
Tx Lane 9+
A54
GND
B55
PETxN9
Tx Lane 9-
A55
GND
B56
GND
A56
PERxP9
Rx Lane 9+
B57
GND
A57
PERxN9
Rx Lane 9-
B58
PETxP10
Tx Lane 10+
A58
GND
B59
PETxN10
Tx Lane 10-
A59
GND
B60
GND
A60
PERxP10
Rx Lane 10+
B61
GND
A61
PERxN10
Rx Lane 10-
B62
PETxP11
Tx Lane 11+
A62
GND
B63
PETxN11
Tx Lane 11-
A63
GND
B64
GND
A64
PERxP11
Rx Lane 11+
B65
GND
A65
PERxN11
Rx Lane 11-
B66
PETxP12
Tx Lane 12+
A66
GND
B67
PETxN12
Tx Lane 12-
A67
GND
B68
GND
A68
PERxP12
Rx Lane 12+
B69
GND
A69
PERxN12
Rx Lane 12-
B70
PETxP13
Tx Lane 13+
A70
GND
B71
PETxN13
Tx Lane 13-
A71
GND
B72
GND
A72
PERxP13
Rx Lane 13+
B73
GND
A73
PERxN13
Rx Lane 13-
B74
PETxP14
Tx Lane 14+
A74
GND
B75
PETxN14
Tx Lane 14-
A75
GND
B76
GND
A76
PERxP14
Rx Lane 14+
B77
REFCLK+
Clock pair 2
A77
PERxN14
Rx Lane 14-
B78
REFCLK-
Clock pair 2
A78
GND
B79
GND
A79
PERxP15
Rx Lane 15+
B80
PETxP15
Tx Lane 15+
A80
PERxN15
Rx Lane 15-
B81
PETxN15
Tx Lane 15-
A81
GND
B82
GND
A82
Riser ID
Revision 1.0
Rx Lane 6-
Fix to High: PCIe x16
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Intel order number: G59328-001
Intel®Server System H2000LP FamilyTPS
PCI Express* Riser Card and Assembly
There is a standard PCI Express* Gen3 x16 slot on riser card for PCIe based add-in card. The pin
definitions for the slot are as below:
Table 61. PCI Express* Slot Pinout on Riser Card
Pin-Side B
82
PCI Spec Signal
RSVD
Pin-Side A
82
PCI Spec Signal
GND
81
PRSNT2#
81
HSIN15
80
GND
80
HSIP15
79
HSON15
79
GND
78
HSOP15
78
GND
77
GND
77
HSIN14
76
GND
76
HSIP14
75
HSON14
75
GND
74
HSOP14
74
GND
73
GND
73
HSIN13
72
GND
72
HSIP13
71
HSON13
71
GND
70
HSOP13
70
GND
69
GND
69
HSIN12
68
GND
68
HSIP12
67
HSON12
67
GND
66
HSOP12
66
GND
65
GND
65
HSIN11
64
GND
64
HSIP11
63
HSON11
63
GND
62
HSOP11
62
GND
61
GND
61
HSIN10
60
GND
60
HSIP10
59
HSON10
59
GND
58
HSOP10
58
GND
57
GND
57
HSIN9
56
GND
56
HSIP9
55
HSON9
55
GND
54
HSOP9
54
GND
53
GND
53
HSIN8
52
GND
52
HSIP8
51
HSON8
51
GND
50
HSOP8
50
RSVD
49
GND
49
GND
48
PRSNT2#
48
HSIN7
47
GND
47
HSIP7
46
HSON7
46
GND
45
HSOP7
45
GND
44
GND
44
HSIN6
43
GND
43
HSIP6
64
Revision 1.0
Intel order number: G59328-001
PCI Express* Riser Card and Assembly
Pin-Side B
42
Intel®Server System H2000LP Family TPS
PCI Spec Signal
HSON6
Pin-Side A
42
GND
PCI Spec Signal
41
HSOP6
41
GND
40
GND
40
HSIN5
39
GND
39
HSIP5
38
HSON5
38
GND
37
HSOP5
37
GND
36
GND
36
HSIN4
35
GND
35
HSIP4
34
HSON4
34
GND
33
HSOP4
33
RSVD
32
GND
32
RSVD
31
PRSNT2#
31
GND
30
RSVD
30
HSIN3
29
GND
29
HSIP3
28
HSON3
28
GND
27
HSOP3
27
GND
26
GND
26
HSIN2
25
GND
25
HSIP2
24
HSON2
24
GND
23
HSOP2
23
GND
22
GND
22
HSIN1
21
GND
21
HSIP1
20
HSON1
20
GND
19
HSOP1
19
RSVD
18
GND
18
GND
17
PRSNT2#
17
HSIN0
16
GND
16
HSIP0
15
HSON0
15
GND
14
HSOP0
14
REFCLK-
13
GND
13
REFCLK+
12
RSVD
12
GND
KEY
KEY
KEY
KEY
11
WAKE#
11
PWRGD
10
3.3V AUX
10
3.3V
9
JTAG1
9
3.3V
8
3.3V
8
JTAG5
7
GND
7
JTAG4
6
SMDAT
6
JTAG3
5
SMCLK
5
JTAG2
4
GND
4
GND
3
RSVD
3
12V
2
12V
2
12V
1
12V
1
PRSNT1#
Revision 1.0
65
Intel order number: G59328-001
Intel®Server System H2000LP FamilyTPS
9.2
9.2.1
PCI Express* Riser Card and Assembly
PCI Express* Riser with IOM Carrier for Slot 2 (Optional)
Overview of PCI-E Riser with IOM Carrier
The Riser with IOM carrier is provided as accessory to the server system. It is combined with
below functions:

Provide PCI Express* x8 Gen 3 signals from riser

Integrated 1GbE management port for Intel® Remote Management Module 4

Support PCI Express* x4 based Intel® IO Module
Riser slot 2 on baseboard provides standard PCI Express* x8 Gen3 signals, together with
specific power pins to support high-power Graphic/GPGPU add-in card.
Note: Riser Slot 2 on baseboard only supports Intel® 1U/2U Risers. It will cause damage to any
PCI-E based add-in card, which is directly plugged into the Riser Slot 2.Riser Slot2 only support
PCIe Gen II IO module.
The PCI-E slot on Riser is x16 mechanically with x8 electrically. The IOM carrier is using PCI-E
x8 card edge with PCI-E x4 IO module slot.
Figure 37. PCI Express* Riser with bracket for Riser Slot 2
66
Revision 1.0
Intel order number: G59328-001
PCI Express* Riser Card and Assembly
Intel®Server System H2000LP Family TPS
Figure 38. IOM Carrier
The 1GbE port is dedicated NIC port for RMM4 Lite module. It only works once the RMM4 Lite
module is installed in the system. The LED of dedicated NIC port is following the
below definition:
Table 62. Dedicated NIC Port LED Functionality
LED
Color
Green
Condition
On
Functionality
1Gbps mode
Dedicated NIC Speed
Amber
On
100Mbps mode
Off
10Mbps mode
Green
On
LAN link and no access
Green
Blink
LAN access
Off
Idle
Dedicated NIC
Activity
9.2.2
Pinout definition on Slot 2 Riser and IOM Carrier
Below is a list of pin definition for Slot 2 Riser and IOM Carrier.
Table 63. Riser Card Edge Pinout
Pin
Pin Name
Description
Pin
Pin Name
Description
B1
12V
20W 3.3V generated on riser
A1
12V
20W 3.3V generated on riser
B2
12V
66W for GPU
A2
12V
66W for GPU
B3
12V
66W for GPU
A3
12V
66W for GPU
B4
12V
66W for GPU
A4
SMDATA
for rIOM temp sensor
5VAUX
For DNM and IOM wake on
LAN
PRESENT#
DNM function present
B5
B6
SMCLK
for rIOM temp sensor
3.3V Aux
For DNM and IOM wake on
LAN
B7
GND
B8
TXD_0
B9
B10
A5
A6
A7
RIOM_ACT#
RGMII txmit data
A8
RXD_3
RGMII receive data
TXD_1
RGMII txmit data
A9
RXD_2
RGMII receive data
TXD_2
RGMII txmit data
A10
RXD_1
RGMII receive data
B11
TXD_3
RGMII txmit data
A11
KEY
RXD_0
RGMII receive data
B12
GND
A12
RX_CTL
RGMII receive Cntrl
B13
TX_CLK
RGMII txmit Clock
A13
GND
B14
TX_CTL
RGMII txmit Cntrl
A14
RX_CLK
B15
MDIO
A15
MDC
B16
PERST#
A16
GND
B17
WAKE#
A17
REFCLK+
Clock pair 1
B18
PETxP0
Tx Lane 0+
A18
REFCLK-
Clock pair 1
B19
PETxN0
Tx Lane 0-
A19
GND
Revision 1.0
RGMII receive Clock
67
Intel order number: G59328-001
Intel®Server System H2000LP FamilyTPS
Pin
Pin Name
PCI Express* Riser Card and Assembly
Description
Pin
Pin Name
Description
B20
GND
A20
PERxP0
Rx Lane 0+
B21
GND
A21
PERxN0
Rx Lane 0-
B22
PETxP1
Tx Lane 1+
A22
GND
B23
PETxN1
Tx Lane 1-
A23
GND
B24
GND
A24
PERxP1
Rx Lane 1+
B25
GND
A25
PERxN1
Rx Lane 1-
B26
PETxP2
Tx Lane 2+
A26
GND
B27
PETxN2
Tx Lane 2-
A27
GND
B28
GND
A28
PERxP2
Rx Lane 2+
B29
GND
A29
PERxN2
Rx Lane 2-
B30
PETxP3
Tx Lane 3+
A30
GND
B31
PETxN3
Tx Lane 3-
A31
GND
B32
GND
A32
PERxP3
Rx Lane 3+
B33
GND
A33
PERxN3
Rx Lane 3-
B34
PETxP4
Tx Lane 4+
A34
GND
B35
PETxN4
Tx Lane 4-
A35
GND
B36
GND
A36
PERxP4
Rx Lane 4+
B37
GND
A37
PERxN4
Rx Lane 4-
B38
PETxP5
Tx Lane 5+
A38
GND
B39
PETxN5
Tx Lane 5-
A39
GND
B40
GND
A40
PERxP5
Rx Lane 5+
B41
GND
A41
PERxN5
Rx Lane 5-
B42
PETxP6
Tx Lane 6+
A42
GND
B43
PETxN6
Tx Lane 6-
A43
GND
B44
GND
A44
PERxP6
Rx Lane 6+
B45
GND
A45
PERxN6
Rx Lane 6-
B46
PETxP7
Tx Lane 7+
A46
GND
B47
PETxN7
Tx Lane 7-
A47
GND
B48
GND
A48
PERxP7
Rx Lane 7+
B49
GND
A49
PERxN7
Rx Lane 7-
B50
PETxP8
Tx Lane 8+
A50
GND
B51
PETxN8
Tx Lane 8-
A51
GND
B52
GND
A52
PERxP8
Rx Lane 8+
B53
GND
A53
PERxN8
Rx Lane 8-
B54
PETxP9
Tx Lane 9+
A54
GND
B55
PETxN9
Tx Lane 9-
A55
GND
B56
GND
A56
PERxP9
Rx Lane 9+
B57
GND
A57
PERxN9
Rx Lane 9-
B58
PETxP10
Tx Lane 10+
A58
GND
B59
PETxN10
Tx Lane 10-
A59
GND
B60
GND
A60
PERxP10
Rx Lane 10+
B61
GND
A61
PERxN10
Rx Lane 10-
68
Revision 1.0
Intel order number: G59328-001
PCI Express* Riser Card and Assembly
Pin
Pin Name
Intel®Server System H2000LP Family TPS
Description
Pin
Pin Name
Description
B62
PETxP11
Tx Lane 11+
A62
GND
B63
PETxN11
Tx Lane 11-
A63
GND
B64
GND
A64
PERxP11
Rx Lane 11+
B65
GND
A65
PERxN11
Rx Lane 11-
B66
PETxP12
Tx Lane 12+
A66
GND
B67
PETxN12
Tx Lane 12-
A67
GND
B68
GND
A68
PERxP12
Rx Lane 12+
B69
GND
A69
PERxN12
Rx Lane 12-
B70
PETxP13
Tx Lane 13+
A70
GND
B71
PETxN13
Tx Lane 13-
A71
GND
B72
GND
A72
PERxP13
Rx Lane 13+
B73
GND
A73
PERxN13
Rx Lane 13-
B74
PETxP14
Tx Lane 14+
A74
GND
B75
PETxN14
Tx Lane 14-
A75
GND
B76
GND
A76
PERxP14
Rx Lane 14+
B77
REFCLK+
Clock pair 2
A77
PERxN14
Rx Lane 14-
B78
REFCLK-
Clock pair 2
A78
GND
B79
GND
A79
PERxP15
Rx Lane 15+
B80
PETxP15
Tx Lane 15+
A80
PERxN15
Rx Lane 15-
B81
PETxN15
Tx Lane 15-
A81
GND
B82
GND
A82
Riser ID
Table 64. PCI Express* Slot Pinout on Riser Card
Pin-Side B
82
PCI Spec Signal
RSVD
Pin-Side A
82
PCI Spec Signal
GND
81
PRSNT2#
81
HSIN15
80
GND
80
HSIP15
79
HSON15
79
GND
78
HSOP15
78
GND
77
GND
77
HSIN14
76
GND
76
HSIP14
75
HSON14
75
GND
74
HSOP14
74
GND
73
GND
73
HSIN13
72
GND
72
HSIP13
71
HSON13
71
GND
70
HSOP13
70
GND
69
GND
69
HSIN12
68
GND
68
HSIP12
67
HSON12
67
GND
66
HSOP12
66
GND
65
GND
65
HSIN11
Revision 1.0
69
Intel order number: G59328-001
Intel®Server System H2000LP FamilyTPS
Pin-Side B
64
PCI Express* Riser Card and Assembly
PCI Spec Signal
GND
Pin-Side A
64
PCI Spec Signal
HSIP11
63
HSON11
63
GND
62
HSOP11
62
GND
61
GND
61
HSIN10
60
GND
60
HSIP10
59
HSON10
59
GND
58
HSOP10
58
GND
57
GND
57
HSIN9
56
GND
56
HSIP9
55
HSON9
55
GND
54
HSOP9
54
GND
53
GND
53
HSIN8
52
GND
52
HSIP8
51
HSON8
51
GND
50
HSOP8
50
RSVD
49
GND
49
GND
48
PRSNT2#
48
HSIN7
47
GND
47
HSIP7
46
HSON7
46
GND
45
HSOP7
45
GND
44
GND
44
HSIN6
43
GND
43
HSIP6
42
HSON6
42
GND
41
HSOP6
41
GND
40
GND
40
HSIN5
39
GND
39
HSIP5
38
HSON5
38
GND
37
HSOP5
37
GND
36
GND
36
HSIN4
35
GND
35
HSIP4
34
HSON4
34
GND
33
HSOP4
33
RSVD
32
GND
32
RSVD
31
PRSNT2#
31
GND
30
RSVD
30
HSIN3
29
GND
29
HSIP3
28
HSON3
28
GND
27
HSOP3
27
GND
26
GND
26
HSIN2
25
GND
25
HSIP2
24
HSON2
24
GND
23
HSOP2
23
GND
22
GND
22
HSIN1
21
GND
21
HSIP1
20
HSON1
20
GND
70
Revision 1.0
Intel order number: G59328-001
PCI Express* Riser Card and Assembly
Pin-Side B
19
Intel®Server System H2000LP Family TPS
PCI Spec Signal
HSOP1
Pin-Side A
19
RSVD
PCI Spec Signal
18
GND
18
GND
17
PRSNT2#
17
HSIN0
16
GND
16
HSIP0
15
HSON0
15
GND
14
HSOP0
14
REFCLK-
13
GND
13
REFCLK+
12
RSVD
12
GND
KEY
KEY
KEY
KEY
11
WAKE#
11
PWRGD
10
3.3V AUX
10
3.3V
9
JTAG1
9
3.3V
8
3.3V
8
JTAG5
7
GND
7
JTAG4
6
SMDAT
6
JTAG3
5
SMCLK
5
JTAG2
4
GND
4
GND
3
RSVD
3
12V
2
12V
2
12V
1
12V
1
PRSNT1#
Table 65. IO Module Slot on Carrier
Pin
Signal
Pin
Signal
1
3.3V
2
12V
3
3.3V
4
12V
5
3.3V
6
12V
7
3.3V
8
12V
9
RSVD
10
FRU/TEMP ADDR [I]
11
GND
12
5VSB
13
RSVD+
14
FM_IO_MODULE_EN
15
RSVD-
16
3.3VSTBY
17
GND
18
LED_GLOBAL ACT#
19
RSVD
20
FM_IOM_PRESENT_N
21
RSVD
22
WAKE#
23
GND
24
PERST#
25
SMB CLK
26
GND
27
SMB DAT
28
rIOM REFCLK+ [0]
29
GND
30
rIOM REFCLK- [0]
31
PCIe Gen3 Tn [7]]
32
GND
33
PCIe Gen3 Tp [7]
34
PCIe Gen3 Rn [7]
Revision 1.0
71
Intel order number: G59328-001
Intel®Server System H2000LP FamilyTPS
Pin
PCI Express* Riser Card and Assembly
Signal
Pin
Signal
35
GND
36
PCIe Gen3 Rp [7]
37
PCIe Gen3 Tn [6]
38
GND
39
PCIe Gen3 Tp [6]
40
PCIe Gen3 Rn [6]
41
GND
42
PCIe Gen3 Rp [6]
43
PCIe Gen3 Tn [5]
44
GND
45
PCIe Gen3 Tp [5]
46
PCIe Gen3 Rn [5]
47
GND
48
PCIe Gen3 Rp [5]
49
PCIe Gen3 Tn [4]
50
GND
51
PCIe Gen3 Tp [4]
52
PCIe Gen3 Rn [4]
53
GND
54
PCIe Gen3 Rp [4]
55
PCIe Gen3 Tn [3]
56
GND
57
PCIe Gen3 Tp [3]
58
PCIe Gen3 Rn [3]
59
GND
60
PCIe Gen3 Rp [3]
61
PCIe Gen3 Tn [2]
62
GND
63
PCIe Gen3 Tp [2]
64
PCIe Gen3 Rn [2]
65
GND
66
PCIe Gen3 Rp [2]
67
PCIe Gen3 Tn [1]
68
GND
69
PCIe Gen3 Tp [1]
70
PCIe Gen3 Rn [1]
71
GND
72
PCIe Gen3 Rp [1]
73
PCIe Gen3 Tn [0]
74
GND
75
PCIe Gen3 Tp [0]
76
PCIe Gen3 Rn [0]
77
GND
78
PCIe Gen3 Rp [0]
79
RSVD
80
GND
72
Revision 1.0
Intel order number: G59328-001
Appendix A: Integration and Usage Tips
Intel®Server System H2000LP Family TPS
Appendix A: Integration and Usage Tips
Before attempting to integrate and configure your system, you should reference this section,
which provides a list of useful information.

After the system is integrated with processors, memory, and peripheral devices, the
FRUSDR utility must be run to load the proper Sensor Data Record data to the
integrated Server Management subsystem. Failure to run this utility may prevent Server
Management from accurately monitoring system health and may affect system
performance. The FRUSDR utility for this server system can either be run from the Intel
Deployment CDROM that came with your system, or can be downloaded from the Intel
website referenced at the bottom of this page.

To ensure the highest system reliability, make sure the latest system software is loaded
on the server before deploying the system onto a live networking environment. This
includes system BIOS, FRUSDR, BMC firmware, and hot-swap controller firmware. The
system software can be updated using the Intel Deployment CDROM that came with
your system or can be downloaded from the Intel website referenced at the bottom of
this page.

System fans are not hot-swappable.

Only supported memory validated by Intel should be used in this server system. A list of
supported memory can be found in the Intel® Server Board S2400LP Tested Memory
List which can be downloaded from the Intel website referenced at the bottom of this
page.

This system supports the Intel® Xeon® processor E5-2400 sequence. You cannot use
Intel® Xeon® processors not referenced on the supported processor list in this server
system.

You must use the CPU/memory air duct to maintain system thermals.

To maintain system thermals, you must populate all hard drive bays with either a hard
drive or drive blank.

You must remove AC power from the system prior to opening the chassis for service
You can download the latest system documentation, drivers, and system software from the Intel
Support website at http://www.intel.com/p/en_US/support/highlights/server/H2000LP.
Revision 1.0
73
Intel order number: G59328-001
Intel®Server System H2000LP Family TPS
Appendix B: POST Code LED Decoder
Appendix B: POST Code LED Decoder
During the system boot process, the BIOS executes a number of platform configuration
processes, each of which is assigned a specific hex POST code number. As each configuration
routine is started, the BIOS displays the POST code to the POST Code Diagnostic LEDs on the
back edge of the server board. To assist in troubleshooting a system hang during the POST
process, you can use the diagnostic LEDs to identify the last POST process executed.
Figure 39. Diagnostic LED location
Table 66. POST Code Diagnostic LED Location
A
ID LED
B
Status LED
C
Diagnostic LED #7 MSB
G
Diagnostic LED #3
D
Diagnostic LED #6
H
Diagnostic LED #2
E
Diagnostic LED #5
I
Diagnostic LED #1
F
Diagnostic LED #4
J
Diagnostic LED #0 LSB
Each POST code is represented by the eight amber diagnostic LEDs. The POST codes are
divided into two nibbles, an upper nibble and a lower nibble. The upper nibble bits are
represented by diagnostic LEDs #4, #5, #6, and #7. The lower nibble bits are represented by
diagnostics LEDs #0, #1, #2, and #3. If the bit is set in the upper and lower nibbles, then the
corresponding LED is lit. If the bit is clear, then the corresponding LED is off.
The diagnostic LED #7 is labeled as “MSB” (Most Significant Bit), and the diagnostic LED #0 is
labeled as “LSB” (Least Significant Bit).
In the following example, the BIOS sends a value of ACh to the diagnostic LED decoder. The
LEDs are decoded as follows:
74
Revision 1.0
Intel order number: G59328-001
Appendix B: POST Code LED Decoder
Intel®Server System H2000LP Family TPS
Table 67. POST Progress Code LED Example
Upper Nibble LEDs
MSB
LED #7
8h
ON
1
LEDs
Status
Results
LED #6
4h
OFF
0
LED #5
2h
ON
1
Lower Nibble LEDs
LED #4
1h
OFF
0
LED #3
8h
ON
1
LED #2
4h
ON
1
Ah
LED #1
2h
OFF
0
LSB
LED #0
1h
OFF
0
Ch
Upper nibble bits = 1010b = Ah; Lower nibble bits = 1100b = Ch; the two are concatenated as ACh.
Table 68. Diagnostic LED POST Code Decoder
Checkpoint
MSB
8h
LED
#7
Host Processor
0x04h
X
0x10h
X
0x11h
X
0x12h
X
0x13h
X
Chipset
0x21h
X
Memory
0x22h
X
0x23h
X
0x24h
X
0x25h
X
0x26h
X
0x27h
X
0x28h
X
PCI Bus
0x50h
X
0x51h
X
0x52h
X
0x53h
X
0x54h
X
0x55h
X
0x56h
X
0x57h
X
USB
0x58h
X
0x59h
X
ATA/ATAPI/SATA
0x5Ah
X
0x5Bh
X
0x5Ch
X
0x5Dh
X
Diagnostic LED Decoder
O = On, X=Off
Upper Nibble
Lower Nibble
4h
#6
X
X
X
X
X
2h
#5
X
X
X
X
X
X
X
X
X
O
O
O
O
O
O
O
X
X
X
X
X
O
O
O
O
1h
#4
X
X
X
X
X
X
X
X
O
O
O
O
O
X
X
X
X
X
X
X
X
O
O
O
O
O
O
X
X
O
O
X
X
X
X
X
X
X
X
X
X
O
O
O
O
O
O
O
O
4h
#2
O
X
X
X
X
X
X
O
O
O
O
O
O
O
O
8h
#3
X
X
X
X
X
O
O
O
X
X
X
X
O
O
O
O
X
X
O
O
X
O
X
X
O
O
X
X
O
O
X
O
X
O
X
X
O
X
O
X
O
X
O
X
X
O
O
X
X
Power-on initialization of the host processor (Boot Strap Processor)
Host processor cache initialization (including AP)
Starting application processor initialization
SMM initialization
O Initializing a chipset component
X
X
O
O
X
X
X
Early processor initialization (flat32.asm) where system BSP is selected
X
X
O
X
O
X
O
O
O
O
X
O
O
O
O
O
O
X
X
X
O
O
X
X
X
X
X
X
X
X
X
X
2h
#1
Description
LSB
1h
#0
Reading configuration data from memory (SPD on FBDIMM)
Detecting presence of memory
Programming timing parameters in the memory controller
Configuring memory parameters in the memory controller
Optimizing memory controller settings
Initializing memory, such as ECC in it
Testing memory
Enumerating PCI buses
Allocating resources to PCI buses
Hot Plug PCI controller initialization
Reserved for PCI bus
Reserved for PCI bus
Reserved for PCI bus
Reserved for PCI bus
Reserved for PCI bus
X Resetting USB bus
O Reserved for USB devices
X
O
X
O
Resetting SATA bus and all devices
Detecting the presence of ATA device
Enable SMART if supported by ATA device
Reserved for ATA
Revision 1.0
75
Intel order number: G59328-001
Intel®Server System H2000LP Family TPS
Appendix B: POST Code LED Decoder
Diagnostic LED Decoder
O = On, X=Off
Upper Nibble
Lower Nibble
Checkpoint
MSB
8h
#7
4h
LED
#6
SMBUS
0x5Eh
X
O
0x5Fh
X
O
Local Console
0x70h
X
O
0x71h
X
O
0x72h
X
O
Remote Console
0x78h
X
O
0x79h
X
O
0x7Ah
X
O
Keyboard (only USB)
0x90h
O
X
0x91h
O
X
0x92h
O
X
0x93h
O
X
0x94h
O
X
0x95h
O
X
Mouse (only USB)
0x98h
O
X
0x99h
O
X
0x9Ah
O
X
0x9Bh
O
X
Fixed Media
0xB0h
O
X
0xB1h
O
X
2h
#5
1h
#4
8h
#3
4h
#2
2h
#1
X
X
O
O
O
O
O
O
O
O
Description
LSB
1h
#0
X Resetting SMBUS*
O Reserved for SMBUS*
O
O
O
O
O
O
X
X
X
X
X
X
X
X
O
X
O
X
Resetting the video controller (VGA)
Disabling the video controller (VGA)
Enabling the video controller (VGA)
O
O
O
O
O
O
O
O
O
X
X
X
X
X
O
X
O
X
Resetting the console controller
Disabling the console controller
Enabling the console controller
X
X
X
X
X
X
O
O
O
O
O
O
X
X
X
X
X
X
X
X
X
X
O
O
X
X
O
O
X
X
X
O
X
O
X
O
Resetting the keyboard
Disabling the keyboard
Detecting the presence of the keyboard
Enabling the keyboard
Clearing keyboard input buffer
Reserved for keyboard
X
O
X
O X
O X
O X
X
X
O
O
O
O
X
O
X
X
X
X
O
O
Resetting the mouse
Detecting the mouse
Detecting the presence of mouse
O Enabling the mouse
Resetting fixed media device
Disabling fixed media device
Detecting presence of a fixed media device (SATA hard drive detection,
and so on)
Enabling/configuring a fixed media device
O
O
O
O
X
X
X
X
X
X
X
O
O
O
X
X
O
X
0xB3h
O
X
O
O X
Removable Media
0xB8h
O
X
O
O
O
0xB9h
O
X
O
O
O
X
O
O
X
X
X
X
X
O
0xBAh
O
X
O
X
O O
O
X
X
Resetting removable media device
Disabling removable media device
Detecting presence of a removable media device (SATA CDROM
detection, and so on)
Enabling/configuring a removable media device
X
X
X
O X
O
X
X
X
X
X
O
X
X
O
O
X
X
O
X
O
X
Entered the Boot Device Selection phase (BDS)
Return to last good boot device
Setup boot device selection policy
Connect boot device controller
Attempt flash update boot mode
X
O
X
O
Transfer control to EFI boot
X
O
O
O
O
O
X
O
Trying to boot device selection
Reserved for boot device selection
0xB2h
O
O
X
X
O
0xBCh
O
X
O
Boot Device Selection (BDS)
0xD0
O
O
X
0xD1
O
O
X
0xD2
O
O
X
0xD3
O
O
X
0xD4
O
O
X
0xD5
O
O
O
O
O
O
X
O
0xD6
O
O
X
O
0xDF
O
O
X
O
Pre-EFI Initialization (PEI) Core
76
Revision 1.0
Intel order number: G59328-001
Appendix B: POST Code LED Decoder
Intel®Server System H2000LP Family TPS
Diagnostic LED Decoder
O = On, X=Off
Upper Nibble
Lower Nibble
Checkpoint
MSB
8h 4h 2h 1h 8h 4h
LED
#7 #6 #5 #4 #3 #2
0xE0h
O
O
O
X
X
X
0xE1h
O
O
O
X
X
X
0xE2h
O
O
O
X
X
X
0xE3h
O
O
O
X
X
X
Driver eXecution Environment (DXE) Core
0xE4h
O
O
O
X
X
O
0xE5h
O
O
O
X
X
O
0xE6h
O
O
O
X
X
O
DXE Drivers
0xE7h
O
O
O
X
O
O
0xE8h
O
O
O
X
O
X
0xE9h
O
O
O
X
O
X
0xEAh
O
O
O
X
O
O
0xEEh
O
O
O
X
O
O
0xEFh
O
O
O
X
O
O
Pre-EFI Initialization Module (PEIM)/Recovery
0x30h
X
X
O
O
X
X
0x31h
X
X
O
O
X
X
0x34h
X
X
O
O
X
O
0x35h
X
X
O
O
X
O
0x3Fh
X
X
O
O
O
O
Runtime Phase/EFI Operating System Boot
LSB
2h 1h
#1 #0
X
X
X
O
O
X
O
O
0XF2h
0XF4h
0XF5h
O
O
O
O
O
O
O
O
O
O
O
O
X
X
X
0XF8h
O
O
O
O
Progress Code
0XF9h
O
0xFAh
O
X
X
X
X
O
O
X
X
X
O
O
Description
Entered Pre-EFI Initialization phase (PEI)
Started dispatching early initialization modules (PEIM)
Initial memory found, configured, and installed correctly
Transfer control to the DXE Core
Entered EFI driver execution phase (DXE)
Started dispatching drivers
X Started connecting drivers
X
X
X
X
X
X
O
X
O
X
X
O
Waiting for user input
Checking password
Entering BIOS setup
Flash Update
Calling Int 19. One beep unless silent boot is enabled.
Unrecoverable boot failure
X
X
X
X
O
X
O
X
O
O
Crisis recovery has been initiated because of a user request
Crisis recovery has been initiated by software (corrupt flash)
Loading crisis recovery capsule
Handing off control to the crisis recovery capsule
Crisis recovery capsule failed integrity check of capsule descriptors
X
O
O
O
X
X
X
X
O
O
X
X
X
Signal that the OS has switched to virtual memory mode
Entering the sleep state
Exiting the sleep state
Operating system has requested EFI to close boot services has been
cancelled.
X
X
X
X
X
X
X
O
Resetting the keyboard
Disabling the keyboard
Revision 1.0
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Appendix C: Video POST Code Errors
Intel®Server System H2000LP Family TPS
Appendix C: Video POST Code Errors
Whenever possible, the BIOS outputs the current boot progress codes on the video screen.
Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class,
subclass, and operation information. The class and subclass fields point to the type of hardware
being initialized. The operation field represents the specific initialization activity. Based on the
data bit availability to display progress codes, a progress code can be customized to fit the data
width. The higher the data bit, the higher the granularity of information that can be sent on the
progress port. The progress codes may be reported by the system BIOS or option ROMs.
The Response section in the following table is divided into three types:



No Pause: The message is displayed on the local Video screen during POST or in the Error
Manager. The system continues booting with a degraded state. The user may want to replace the
erroneous unit. The setup POST error Pause setting does not have any effect with this error.
Pause: The message is displayed on the Error Manager screen, and an error is logged to the
SEL. The setup POST error Pause setting determines whether the system pauses to the Error
Manager for this type of error, where the user can take immediate corrective action or choose to
continue booting.
Halt: The message is displayed on the Error Manager screen, an error is logged to the SEL, and
the system cannot boot unless the error is resolved. The user needs to replace the faulty part and
restart the system. The setup POST error Pause setting does not have any effect with this error.
Table 69. POST Error Message and Handling
Error Code
0012
0048
0108
0109
0113
0140
0141
0146
0192
0194
0195
0196
0197
0198
019F
5220
5221
5224
8110
8111
8120
8121
8130
8131
8140
8141
8160
Error Message
CMOS date/time not set.
Password check failed.
Keyboard component encountered a locked error.
Keyboard component encountered a stuck key error.
Fixed Media The SAS RAID firmware cannot run properly. The user should attempt to reflash the firmware.
PCI component encountered a PERR error.
PCI resource conflict.
PCI out of resources error.
L3 cache size mismatch.
CPUID, processor families are different.
Front side bus mismatch.
Processor model mismatch.
Processor speed mismatch.
Processor family is unsupported.
Processor and chipset stepping configuration is unsupported.
CMOS/NVRAM configuration cleared.
Password cleared by jumper.
Password clear jumper is set.
Processor 01 internal error (IERR) on last boot.
Processor 02 internal error (IERR) on last boot.
Processor 01 thermal trip error on last boot.
Processor 02 thermal trip error on last boot.
Processor 01 disabled.
Processor 02 disabled.
Processor 01 Failed FRB-3 Timer.
Processor 02 Failed FRB-3 Timer..
Processor 01 unable to apply BIOS update.
78
Response
Pause
Halt
No Pause
No Pause
Pause
Pause
Pause
Pause
Halt
Halt
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
No Pause
No Pause
Pause
Revision 1.0
Intel order number: G59328-001
Intel®Server System H2000LP Family TPS
Error Code
8161
8170
8171
8180
8181
8190
8198
8300
84F2
84F3
84F4
84FF
8500
8520
8521
8522
8523
8524
8525
8526
8527
8528
8529
852A
852B
852C
852D
852E
852F
8540
8541
8542
8543
8544
8545
8546
8547
8548
8549
854A
854B
854C
854D
854E
854F
8560
8561
8562
8563
8564
8565
8566
8567
8568
8569
856A
856B
Appendix C: Video POST Code Errors
Error Message
Processor 02 unable to apply BIOS update.
Processor 01 failed Self Test (BIST).
Processor 02 failed Self Test (BIST).
Processor 01 BIOS does not support the current stepping for processor.
Processor 02 BIOS does not support the current stepping for processor.
Watchdog timer failed on last boot.
Operating system boot watchdog timer expired on last boot.
Integrated Baseboard Management Controller failed Self Test.
Integrated Baseboard Management Controller failed to respond.
Integrated Baseboard Management Controller in update mode.
Sensor data record empty.
System event log full.
Memory component could not be configured in the selected RAS mode.
DIMM_A1 failed Self Test (BIST).
DIMM_A2 failed Self Test (BIST).
DIMM_A3 failed Self Test (BIST).
DIMM_A4 failed Self Test (BIST).
DIMM_B1 failed Self Test (BIST).
DIMM_B2 failed Self Test (BIST).
DIMM_B3 failed Self Test (BIST).
DIMM_B4 failed Self Test (BIST).
DIMM_C1 failed Self Test (BIST).
DIMM_C2 failed Self Test (BIST).
DIMM_C3 failed Self Test (BIST).
DIMM_C4 failed Self Test (BIST).
DIMM_D1 failed Self Test (BIST).
DIMM_D2 failed Self Test (BIST).
DIMM_D3 failed Self Test (BIST).
DIMM_D4 failed Self Test (BIST).
DIMM_A1 Disabled.
DIMM_A2 Disabled.
DIMM_A3 Disabled.
DIMM_A4 Disabled.
DIMM_B1 Disabled.
DIMM_B2 Disabled.
DIMM_B3 Disabled.
DIMM_B4 Disabled.
DIMM_C1 Disabled.
DIMM_C2 Disabled.
DIMM_C3 Disabled.
DIMM_C4 Disabled.
DIMM_D1 Disabled.
DIMM_D2 Disabled.
DIMM_D3 Disabled.
DIMM_D4 Disabled.
DIMM_A1 Component encountered a Serial Presence Detection (SPD) fail error.
DIMM_A2 Component encountered a Serial Presence Detection (SPD) fail error.
DIMM_A3 Component encountered a Serial Presence Detection (SPD) fail error.
DIMM_A4 Component encountered a Serial Presence Detection (SPD) fail error.
DIMM_B1 Component encountered a Serial Presence Detection (SPD) fail error.
DIMM_B2 Component encountered a Serial Presence Detection (SPD) fail error.
DIMM_B3 Component encountered a Serial Presence Detection (SPD) fail error.
DIMM_B4 Component encountered a Serial Presence Detection (SPD) fail error.
DIMM_C1 Component encountered a Serial Presence Detection (SPD) fail error.
DIMM_C2 Component encountered a Serial Presence Detection (SPD) fail error.
DIMM_C3 Component encountered a Serial Presence Detection (SPD) fail error.
DIMM_C4 Component encountered a Serial Presence Detection (SPD) fail error.
Response
Pause
Pause
Pause
No Pause
No Pause
Pause
Pause
Pause
Pause
Pause
Pause
No Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
79
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Appendix C: Video POST Code Errors
Error Code
856C
856D
856E
856F
8580
Intel®Server System H2000LP Family TPS
Error Message
DIMM_D1 Component encountered a Serial Presence Detection (SPD) fail error.
DIMM_D2 Component encountered a Serial Presence Detection (SPD) fail error.
DIMM_D3 Component encountered a Serial Presence Detection (SPD) fail error.
DIMM_D4 Component encountered a Serial Presence Detection (SPD) fail error.
DIMM_A1 Correctable ECC error encountered.
DIMM_A2 Correctable ECC error encountered.
8581
DIMM_A3 Correctable ECC error encountered.
8582
DIMM_A4 Correctable ECC error encountered.
8583
DIMM_B1 Correctable ECC error encountered.
8584
DIMM_B2 Correctable ECC error encountered.
8585
DIMM_B3 Correctable ECC error encountered.
8586
DIMM_B4 Correctable ECC error encountered.
8587
DIMM_C1 Correctable ECC error encountered.
8588
DIMM_C2 Correctable ECC error encountered.
8589
DIMM_C3 Correctable ECC error encountered.
858A
DIMM_C4 Correctable ECC error encountered.
858B
DIMM_D1 Correctable ECC error encountered.
858C
DIMM_D2 Correctable ECC error encountered.
858D
DIMM_D3 Correctable ECC error encountered.
858E
DIMM_D4 Correctable ECC error encountered.
858F
85A0
85A1
85A2
85A3
85A4
85A5
85A6
85A7
85A8
85A9
85AA
85AB
85AC
85AD
85AE
85AF
8601
8602
8603
8604
9000
9223
DIMM_A1 Uncorrectable ECC error encountered.
DIMM_A2 Uncorrectable ECC error encountered.
DIMM_A3 Uncorrectable ECC error encountered.
DIMM_A4 Uncorrectable ECC error encountered.
DIMM_B1 Uncorrectable ECC error encountered.
DIMM_B2 Uncorrectable ECC error encountered.
DIMM_B3 Uncorrectable ECC error encountered.
DIMM_B4 Uncorrectable ECC error encountered.
DIMM_C1 Uncorrectable ECC error encountered.
DIMM_C2 Uncorrectable ECC error encountered.
DIMM_C3 Uncorrectable ECC error encountered.
DIMM_C4 Uncorrectable ECC error encountered.
DIMM_D1 Uncorrectable ECC error encountered.
DIMM_D2 Uncorrectable ECC error encountered.
DIMM_D3 Uncorrectable ECC error encountered.
DIMM_D4 Uncorrectable ECC error encountered.
Override jumper is set to force boot from lower alternate BIOS bank of flash ROM.
WatchDog timer expired (secondary BIOS may be bad!).
Secondary BIOS checksum fail.
Chipset Reclaim of non-critical variables complete.
Unspecified processor component has encountered a non-specific error.
Keyboard component was not detected.
80
Response
Pause
Pause
Pause
Pause
Pause after 10
Occurrence
Pause after 10
Occurrence
Pause after 10
Occurrence
Pause after 10
Occurrence
Pause after 10
Occurrence
Pause after 10
Occurrence
Pause after 10
Occurrence
Pause after 10
Occurrence
Pause after 10
Occurrence
Pause after 10
Occurrence
Pause after 10
Occurrence
Pause after 10
Occurrence
Pause after 10
Occurrence
Pause after 10
Occurrence
Pause after 10
Occurrence
Pause after 10
Occurrence
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
No Pause
No Pause
No Pause
No Pause
Pause
No Pause
Revision 1.0
Intel order number: G59328-001
Intel®Server System H2000LP Family TPS
Error Code
9226
9243
9246
9266
9268
9269
9286
9287
9288
92A3
92A9
92C6
92C7
92C8
94C6
94C9
9506
95A6
95A7
95A8
9609
9641
9667
9687
96A7
96AB
96E7
0xA022
0xA027
0xA028
0xA421
0xA500
0xA501
0xA5A0
0xA5A1
0xA5A4
0xA6A0
Appendix C: Video POST Code Errors
Error Message
Keyboard component encountered a controller error.
Mouse component was not detected.
Mouse component encountered a controller error.
Local Console component encountered a controller error.
Local Console component encountered an output error.
Local Console component encountered a resource conflict error.
Remote Console component encountered a controller error.
Remote Console component encountered an input error.
Remote Console component encountered an output error.
Serial port component was not detected
Serial port component encountered a resource conflict error.
Serial Port controller error
Serial Port component encountered an input error.
Serial Port component encountered an output error.
LPC component encountered a controller error.
LPC component encountered a resource conflict error.
ATA/ATPI component encountered a controller error.
PCI component encountered a controller error.
PCI component encountered a read error.
PCI component encountered a write error.
Unspecified software component encountered a start error.
PEI Core component encountered a load error.
PEI module component encountered an illegal software state error.
DXE core component encountered an illegal software state error.
DXE boot services driver component encountered an illegal software state error.
DXE boot services driver component encountered invalid configuration.
SMM driver component encountered an illegal software state error.
Processor component encountered a mismatch error.
Processor component encountered a low voltage error.
Processor component encountered a high voltage error.
PCI component encountered a SERR error.
ATA/ATPI ATA bus SMART not supported.
ATA/ATPI ATA SMART is disabled.
PCI Express* component encountered a PERR error.
PCI Express* component encountered a SERR error.
PCI Express* IBIST error.
DXE boot services driver Not enough memory available to shadow a legacy option ROM.
Response
No Pause
No Pause
No Pause
No Pause
No Pause
No Pause
No Pause
No Pause
No Pause
Pause
Pause
No Pause
No Pause
No Pause
No Pause
Pause
No Pause
No Pause
No Pause
No Pause
No Pause
No Pause
Halt
Halt
Halt
No Pause
Halt
Pause
No Pause
No Pause
Halt
No Pause
No Pause
No Pause
Halt
Pause
No Pause
POST Error Beep Codes
The following table lists POST error beep codes. Prior to system video initialization, the BIOS
uses these beep codes to inform users on error conditions. The beep code is followed by a
user-visible code on POST Progress LEDs.
Table 70. POST Error Beep Codes
Beeps
3
Error Message
Memory error
POST Progress Code
Multiple
Description
System halted because a fatal error related to the memory
was detected.
USB Device Beeps When POST
81
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Appendix C: Video POST Code Errors
Intel®Server System H2000LP Family TPS
Intel® Server Boards S2400LP family are designed to indicate USB readiness by a series of
beep codes early during POST, just before video becomes available. These four to five beeps
mean that the USB is powered and initialized, in order for USB devices such as keyboard and
mouse to become operational.
If a USB device such as a pen drive or USB CD/DVD ROM drive is attached to any external
USB port, a beep code means that the device is recognized, powered and initialized. Each USB
port will issue a beep once an external device is ready for use.
These beep codes do not signal any errors. They are designed to advise the user of USB
readiness during POST and while attaching external devices.
This USB Beep is OS Independent.
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Glossary
Intel®Server System H2000LP Family TPS
Glossary
Term
ACPI
Advanced Configuration and Power Interface
AP
Application Processor
APIC
Advanced Programmable Interrupt Control
ASIC
Application Specific Integrated Circuit
ASMI
Advanced Server Management Interface
BIOS
Basic Input/Output System
BIST
Built-In Self Test
BMC
Baseboard Management Controller
Bridge
Circuitry connecting one computer bus to another, allowing an agent on one to access the other
BSP
Bootstrap Processor
Byte
8-bit quantity.
CBC
Chassis Bridge Controller (A microcontroller connected to one or more other CBCs, together they
bridge the IPMB buses of multiple chassis.)
CEK
Common Enabling Kit
CHAP
Challenge Handshake Authentication Protocol
CMOS
In terms of this specification, this describes the PC-AT compatible region of battery-backed 128 bytes
of memory, which normally resides on the server board
DPC
Direct Platform Control
EEPROM
Electrically Erasable Programmable Read-Only Memory
EHCI
Enhanced Host Controller Interface
EMP
Emergency Management Port
EPS
External Product Specification
ESB2-E
Enterprise South Bridge 2
FBD
Fully Buffered DIMM
FMB
Flexible Mother Board
FRB
Fault Resilient Booting
FRU
Field Replaceable Unit
FSB
Front Side Bus
GB
1024MB
GPIO
General Purpose I/O
GTL
Gunning Transceiver Logic
HSC
Hot-Swap Controller
Hz
Hertz (1 cycle/second)
2
Definition
IC
Inter-Integrated Circuit Bus
IA
Intel Architecture
IBF
Input Buffer
ICH
I/O Controller Hub
ICMB
Intelligent Chassis Management Bus
IERR
Internal Error
IFB
I/O and Firmware Bridge
INTR
Interrupt
®
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Glossary
Term
Definition
IP
Internet Protocol
IPMB
Intelligent Platform Management Bus
IPMI
Intelligent Platform Management Interface
IR
Infrared
ITP
In-Target Probe
KB
1024 bytes
KCS
Keyboard Controller Style
LAN
Local Area Network
LCD
Liquid Crystal Display
LED
Light Emitting Diode
LPC
Low Pin Count
LUN
Logical Unit Number
MAC
Media Access Control
MB
1024KB
MCH
Memory Controller Hub
MD2
Message Digest 2 – Hashing Algorithm
MD5
Message Digest 5 – Hashing Algorithm – Higher Security
ms
milliseconds
MTTR
Memory Type Range Register
Mux
Multiplexor
NIC
Network Interface Controller
NMI
Nonmaskable Interrupt
OBF
Output Buffer
OEM
Original Equipment Manufacturer
Ohm
Unit of electrical resistance
PEF
Platform Event Filtering
PEP
Platform Event Paging
PIA
Platform Information Area (This feature configures the firmware for the platform hardware.)
PLD
Programmable Logic Device
PMI
Platform Management Interrupt
POST
Power-On Self Test
PSMI
Power Supply Management Interface
PWM
Pulse-Width Modulation
RAM
Random Access Memory
RASUM
Reliability, Availability, Serviceability, Usability, and Manageability
RISC
Reduced Instruction Set Computing
RMM3
Remote Management Module – Third generation
RMM3 NIC
Remote Management Module – Third generation dedicated management NIC
ROM
Read Only Memory
RTC
Real-Time Clock (Component of ICH peripheral chip on the server board.)
SDR
Sensor Data Record
SECC
Single Edge Connector Cartridge
SEEPROM
Serial Electrically Erasable Programmable Read-Only Memory
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Glossary
Intel®Server System H2000LP Family TPS
Term
Definition
SEL
System Event Log
SIO
Server Input/Output
SMI
Server Management Interrupt (SMI is the highest priority nonmaskable interrupt.)
SMM
Server Management Mode
SMS
Server Management Software
SNMP
Simple Network Management Protocol
SSI
Server System Infrastructure
TBD
To Be Determined
TIM
Thermal Interface Material
UART
Universal Asynchronous Receiver/Transmitter
UDP
User Datagram Protocol
UHCI
Universal Host Controller Interface
UTC
Universal time coordinate
VID
Voltage Identification
VRD
Voltage Regulator Down
Word
16-bit quantity
ZIF
Zero Insertion Force
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Reference Documents
Reference Documents
Refer to the following documents for additional information:

Intel® Server Board S2400LP Technical Product Specification (Intel Order Code:
G52803)

ACPI 3.0: http://www.acpi.info/spec.htm

IPMI 2.0

Data Center Management Interface Specification v1.0, May 1, 2008:
www.intel.com/go/dcmi

PCI Bus Power Management Interface Specification 1.1: http://www.pcisig.com/

PCI Express* Base Specification Rev 2.0 Dec 06: http://www.pcisig.com/

PCI Express* Card Electromechanical Specification Rev 2.0: http://www.pcisig.com/

PMBus*: http://pmbus.org

SATA 2.6: http://www.sata-io.org/

SMBIOS 2.4

SSI-EEB 3.0: http://www.ssiforum.org

USB 1.1: http://www.usb.org

USB 2.0: http://www.usb.org

Windows Logo/SDG 3.0

Intel® Dynamic Power Technology Node Manager 1.5 External Interface
Specification using IPMI, 2007. Intel Corporation.

Node Power and Thermal Management Architecture Specification v1.5, rev.0.79.
2007, Intel Corporation.

Intel® Server System Integrated Baseboard Management Controller Core External
Product Specification, 2007 Intel Corporation.

Intel® Thurley Server Platform Services IPMI Commands Specification, 2007. Intel
Corporation.

Intel® Server Safety and Regulatory, 2011. Intel Corporation. (Intel Order Code:
G23122)

Intelligent Platform Management Bus Communications Protocol Specification,
Version 1.0, 1998. Intel Corporation, Hewlett-Packard Company, NEC Corporation,
Dell Computer Corporation.

Platform Environmental Control Interface (PECI) Specification, Version 2.0. Intel
Corporation.

Platform Management FRU Information Storage Definition, Version 1.0, Revision 1.2,
2002. Intel Corporation, Hewlett-Packard Company, NEC Corporation, Dell
Computer Corporation: http://developer.intel.com/design/servers/ipmi/spec.htm.
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