ER-OLED0 .83-1 - Display Future

EASTRISING TECHNOLOGY CO.,LIMITED
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ER-OLED0 .83-1
OLED Module User Manual
EastRising Technology Co., Limited
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Document Name: ER-OLED0.83-1 Manual
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Contents
pecification
ns................................................................................................................ 1~6
1. Basic Sp
1.1
1.2
1.3
1.4
1.5
1.6
Display Specifications ................................................................................................................. 1
Mechanical Specifications............................................................................................................ 1
Active Area / Memory Mapping & Pixel Construction ...................................................................... 1
Mechanical Drawing.................................................................................................................... 2
Pin Definition ............................................................................................................................. 3
Block Diagram............................................................................................................................ 5
1.6.1 VCC Supplied Externally...................................................................................................... 5
1.6.2 VCC Generated by Internal DC/DC Circuit............................................................................. 6
2. Ab
bsollute Maximu
um Ra
atings
s ........................................................................................................7
3. Optics & Ellecttrica
al Cha
aracteristtics ....................................................................................... 8~12
3.1 Optics Characteristics.................................................................................................................. 8
3.2 DC Characteristics ...................................................................................................................... 8
3.3 AC Characteristics............................................................. ......................................................... 9
3.3.1 68XX-Series MPU Parallel Interface Timing Characteristics.................................................... 9
3.3.2 80XX-Series MPU Parallel Interface Timing Characteristic ......... ...... ...... ......... ........ ..... 10
3.3.3 Serial Interface Timing Characteristics .......... .. .. ............................................................. 11
3.3.4 I2C Interface Timing Characteristics .... . ..... .... .......... ...... ................ .. ....... ............ 12
4. Functional Specification ........... .............. ..... .. ......... ... .. .... ........................... ........... ..13~17
4.1 Commands .......................................... ... .. ........................................................................... 13
4.2 Power down and Power up Sequence..... ... ............................................................................... 13
4.2.1 Power up Sequence ........................................................................................................ 13
4.2.2 Power down Sequence .. . ............................................................................................... 13
4.3 Reset Circuit ..................... ... . ................................................................................................ 13
4.4 Actual Application Example.. ..................................................................................................... 14
4.4.1 VCC Supplied Externally.................................................................................................... 14
4.4.2 VCC Generated by Internal DC/DC Circuit........................................................................... 16
5. Reliabiility ..................................................................................................................................18
5.1 Contents of Reliability Tests ...................................................................................................... 18
5.2 Failure Check Standard ............................................................................................................. 18
utgo
oing Qua
ality Conttrol Sp
pec
cification
ns ............................................................................19~22
6. Ou
6.1 Environment Required .............................................................................................................. 19
6.2 Sampling Plan .......................................................................................................................... 19
6.3 Criteria & Acceptable Quality Level............................................................................................. 19
6.3.1 Cosmetic Check (Display Off) in Non-Active Area............................................................... 19
6.3.2 Cosmetic Check (Display Off) in Active Area...................................................................... 21
6.3.3 Pattern Check (Display On) in Active Area......................................................................... 22
7. Package Specifications..............................................................................................................23
8. Prrecauttions Wh
hen Us
sing These OE
EL Displlay Modu
ules .......................................................24~26
8.1
8.2
8.3
8.4
8.5
Handling Precautions ................................................................................................................ 24
Storage Precautions.................................................................................................................. 24
Designing Precautions............................................................................................................... 25
Precautions when disposing of the OEL display modules .............................................................. 25
Other Precautions..................................................................................................................... 25
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Warranty ........................................................................................................................................26
Notiice .............................................................................................................................................26
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1. Basic Specifications
1.1 Display Specifications
1)
2)
3)
Display Mode:
Display Color:
Drive Duty:
Passive Matrix
Monochrome (Light Blue)
1/39 Duty
1.2 Mechanical Specifications
1)
2)
3)
4)
5)
6)
7)
Outline Drawing:
Number of Pixels:
Panel Size:
Active Area:
Pixel Pitch:
Pixel Size:
Weight:
According to the annexed outline drawing
96 × 39
23.80 × 16.20 × 1.30 (mm)
19.372 × 7.858 (mm)
0.202 × 0.202 (mm)
0.182 × 0.182 (mm)
0.99 (g)
1.3 Active Area / Memory Mapping & Pixel Construction
Driver IC Memory Mapping
(96 x 39 in 128 x 64)
P0.202x96-0.02=19.372
"A"
Segment 95
( Column 1 )
Common 32
( Row 38 )
Common 50
( Row 2 )
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0.202
0.182
Segment 0
(127, 38)
0.202
0.182
P0.202x39-0.02=7.858
(0, 0) (32, 0)
( Column 96 )
Common 0
( Row 39 )
Common 19
Detail "A"
Scale (10:1)
( Row 1 )
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7 86 (A/A)
9 86 (V/A)
11 3 (Polarizer)
12 3±0 2 (Cap Size)
16 2±0 2 (Panel Size)
(26)
Protective Tape
15x8x0 05mm
Contact Side
Customer Approval
Signature
4 1±0 2
5±0 2
9 8±0 3
1 5±0 3
Document Name: ER-OLED0.83-1 Manual
mm
To ran e
Dim sion ±0 3
Angle
±1
General Roughness
Uni
(1 45)
0 202
0 182
Detail "A"
Scale (10:1)
By
Date
Title
Drawn
Gary Lin
20101229
EE
Ting-Kuo Hu
20101229
Panel / E
Ivy Lo
20101229
ER-OLED0.83-1
B
PM
Tiffany Hsu
20101229
( Row 1 )
Common 50
( Row 2 )
( Row 39 )
Common 19
( Row 38 )
Common 0
( Column 1 )
Common 32
Segment 0
( Column 96 )
Segment 95
"A"
P0 202x96-0 02=19 372
Date
20101108
20101229
EASTRISING TECHNOLOGY CO.,LTD
Unless Otherwi e Spe i ied
0 1±0 03
Contact Side
0 182
0 202
Color: Light Blue/White
Blue
Driver IC: SSD1306
FPC Number: ER-OLED0 83-1
Interface:
8-bit 68XX/80XX Parallel, 4-wire SPI, I2C
5 General Tolerance: ±0 30
6 The total thickness (1 40 Max) is without polarizer protective film & remove tape
The actual assembled total thickness with above materials should be 1 65 Max
0.8
1 3±0 1
(1 6)
W=0 32±0 03
16 75±0 1 (Alignment Hole)
P0 65x(28-1)=17 55±0 05
18 55±0 2
28
2 -φ
.1
±0
5
(17 8)
Notes:
(2 63)
1
10
Active Area 0.83"
0.8 "
96 x 39 Pixels
23 8±0 2 (Panel Size)
23 8±0 2 (Cap Size)
22 8 (Polarizer)
21 37 (V/A)
19 37 (A/A)
P0 202x39-0 02=7 858
1
2
3
4
0 5±0 5
(1 21)
(2 21)
(2 1)
(1 1)
0 5±0 5
Polarizer
t=0 2mm
R
Remove Tape
t=0 15mm Max
Glue
B
(9 87)
RW
Item
A
B
Material
Drawing Number
Symbol
N.C. (GND)
C2P
C2N
C1P
C1N
VDDB
VSS
VDD
BS1
BS2
CS#
RES#
D/C#
R/W#
E/RD#
D0
D1
D2
D3
D4
D5
D6
D7
IREF
VCOMH
VCC
VLSS
N.C. (GND)
Rev
B
Scale
1:1
Sheet
1 of 1
Size
A3
Soda Lime / Polyimide
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Modify Pin Define
Remark
Original Drawing
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1.4 Mechanical Drawing
8
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The drawing contained herein is the exclusive property of EastRising It is not allowed to copy, reproduce and or disclose in any formats without permission of EastRising
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1.5 Pin Definition
Symbol
I/O
Function
8
VDD
P
7
VSS
P
26
VCC
P
27
VLSS
P
Pow
werr Su
upply for Lo
ogic
This is a voltage supply pin. It must be connected to external source.
ogic Ciirc
cuit
Ground of Lo
This is a ground pin. It acts as a reference for the logic pins. It must be
connected to external ground.
Power Supply for OEL Panel
This is the most positive voltage supply pin of the chip. A stabilization capacitor
should be connected between this pin and VSS when the converter is used. It
must be connected to external source when the converter is not used.
Ground of Analog Circuit
This is an analog ground pin. It should be connected to VSS externally.
24
IREF
I
25
VCOMH
O
Pin Number
Power Supply
Driver
Currren
nt Reference for Brrig
ghtness Adjustm
ment
This pin is segment current reference pin. A resistor should be connected
between this pin and VSS. Set the current at 12.5μA maximum.
Voltage Output High Level for COM Signal
This pin is the input pin for the voltage output high level for COM signals. A
capacitor should be connected between this pin and VSS.
DC Co
onverte
er
DC/D
6
VDDB
P
4/5
2/3
C1P / C1N
C2P / C2N
I
Pow
werr Su
upply for DC/DC Conve
erter Cirrcuitt
T s is the p w supply pin fo the interna buff r o the C/DC voltage converter.
It must be connect d to external source when the converter is u ed. It should be
connected to VDD when the converter is not used.
e minall off the Flyiing Inve
ertti g Cap
pac tor
Posittive Te
Negativ e Terminal of the Flying Boost Capacito
or
The charge-pump capac to s a e required between the term nals. They must be
floated when the converter is not used.
Interface
e
9
10
BS1
BS2
I
12
RES#
I
11
CS#
I
13
D/C#
I
15
E/RD#
I
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Communicating Protocol Select
These pins are MCU interface selection input. See the following table:
BS1
BS2
I2C
1
0
0
0
4-wire SPI
8-bit 68XX Parallel
0
1
1
1
8-bit 80XX Parallel
Power Reset for Controller and Driver
This pin is reset signal input. When the pin is low, initialization of the chip is
executed.
Chip Sellect
This pin is the chip select input. The chip is enabled for MCU communication only
when CS# is pulled low.
Data/Command Control
This pin is Data/Command control pin. When the pin is pulled high, the input at
D7~D0 is treated as display data. When the pin is pulled low, the input at D7~D0
will be transferred to the command register. For detail relationship to MCU
interface signals, please refer to the Timing Characteristics Diagrams.
When the pin is pulled high and serial interface mode is selected, the data at SDIN
is treated as data. When it is pulled low, the data at SDIN will be transferred to
the command register. In I2C mode, this pin acts as SA0 for slave address
selection.
Read/W
Writte Enable
e or Read
d
This pin is MCU interface input.
When interfacing to a 68XX-series
microprocessor, this pin will be used as the Enable (E) signal. Read/write operation
is initiated when this pin is pulled high and the CS# is pulled low.
When connecting to an 80XX-microprocessor, this pin receives the Read (RD#)
signal. Data read operation is initiated when this pin is pulled low and CS# is
pulled low.
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1.5 Pin Definition (Continued)
Pin Number
Symbol
I/O
Function
Interface (Continued)
14
R/W#
I
16~23
D0~D7
I/O
N.C. (GND)
-
Read/Write Select or Write
This pin is MCU interface input.
When interfacing to a 68XX-series
microprocessor, this pin will be used as Read/Write (R/W#) selection input. Pul
this pin to “High” for read mode and pull it to “Low” for write mode.
When 80XX interface mode is selected, this pin will be the Write (WR#) input.
Data write operation is initiated when this pin is pulled low and the CS# is pulled
low.
Host Data Input/Output Bus
These pins are 8-bit bi-directional data bus to be connected to the
microprocessor’s data bus. When serial mode is selected, D1 will be the seria
data input SDIN and D0 will be the serial clock input SCLK. When I2C mode is
selected, D2 & D1 should be tired together and serve as SDAout & SDAin in
application and D0 is the serial clock input SCL.
Reserve
1, 28
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Reserv
ved Piin (Supporttin
ng Pin
n)
The supporting pins can reduce the influences from stresses on the function pins.
These pins must be connected to external ground as the ESD protection circuit.
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1.6 Block Diagram
1.6.1 VCC Supplied Externally
Common 19
~ ~ ~
Common 0
Segment 0
Segment 95
~
Common 32
Common 50
Active Area 0.83"
0.8 "
96 x 39 Pixels
~
VLSS
D7
~
IREF
VCOMH
VCC
D0
VDD
BS1
BS2
CS#
RES#
D/C
R/W#
E/RD#
C2P
C2N
C1P
C1N
VDDB
VSS
SSD1306
C5
C1
C2
R1
C3
C4
MCU Interface Selection:
BS1 and BS2
Pins connected to MCU interface: CS#, RES#, D/C#, R/W#, E/RD#, and D0~D7
C1, C3: 0.1μF
C2:
2.2μF
C4, C5: 4.7μF / 16V, X7R
R1:
390kΩ, R1 = (Voltage at IREF - VSS) / IREF
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1.6.2 VCC Generated by Internal DC/DC Circuit
Common 0
IREF
VCOMH
VCC
~
Common 19
Segment 0
~ ~ ~
D7
Segment 95
~
Common 32
Common 50
Active Area 0.83"
0.8 "
96 x 39 Pixels
C6
C5
C2
~
C1
VLSS
D0
VDD
BS1
BS2
CS#
RES#
D/C#
R/W#
E/RD#
VSS
C2P
C2N
C1P
C1N
VDDB
SSD1306
C3
C4
R1
MCU Interface Selection:
BS1 and BS2
Pins connected to MCU interface: CS#, RES#, D/C#, R/W#, E/RD#, and D0~D7
C1, C2: 1μF
C3:
2.2μF
C4:
4.7μF / 16V X7R
C5, C6: 1μF / 16V X5R
R1:
390kΩ, R1 = (Voltage at IREF - VSS) / IREF
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solutte Maxiimu
um Ra
atin
ngs
s
2.. Abs
Parameter
Symbol
Min
Max
Unit
Notes
Supply Voltage for Logic
VDD
-0.3
4
V
1, 2
Supply Voltage for Display
VCC
0
11
V
1, 2
Supply Voltage for DC/DC
VDDB
-0.3
5
V
1, 2
Operating Temperature
TOP
-40
70
°C
Storage Temperature
TSTG
-40
80
°C
10,000
-
hour
Life Time (100 cd/m2)
3
Note 1: All the above voltages are on the basis of “VSS = 0V”.
Note 2: When this module is used beyond the above absolute maximum ratings, permanent breakage of the
module may occur. Also, for normal operations, it is desirable to use this module under the
conditions according to Section 3. “Optics & Electrical Characteristics”. If this module is used
beyond these conditions, malfunctioning of the module can occur and the reliability of the module
may deteriorate.
Note 3: VCC = 7.25V, Ta = 25°C, 50% Checkerboard.
Software configuration follows Section 4.4 Initialization.
End of lifetime is specified as 50% of initial brightness reached. The average operating lifetime at
r om temp rature is estimated by the accelerated operation at high temperature conditions.
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3. Optics & Electrical Characteristics
3.1 Optics Characteristics
Characteristics
Symbol
Conditions
Min
Typ
Max
Unit
Brightness
Lbr
Note 4
80
100
-
cd/m2
C.I.E. (Blue)
(x)
(y)
C.I.E. 1931
0.12
0.22
0.16
0.26
0.20
0.30
Dark Room Contrast
CR
-
>10,000:1
-
-
Free
-
Viewing Angle
degree
* Optical measurement taken at VDD = 2.8V, VCC = 7.25V.
Software configuration follows Section 4.4 Initialization.
3.2 DC Characteristics
Characteristics
Symbol
Supply Voltage for Logic
VDD
Supply Voltage for Display
(Supplied Externally)
VCC
Supply Voltage for DC/DC
Supply Voltage for Display
(Generated by Internal DC/DC)
VDDB
High Level Input
Conditions
Note 4
(Internal DC/DC Disable)
Min
Typ
Max
Unit
1.65
2.8
3.3
V
7.0
7.25
7.5
V
-
4.2
V
-
7.5
V
VIH
Internal DC/DC Enable
3.3
Note 4
7.0
(Internal DC/DC Enable)
IOUT = 100μA, 3.3MHz 0.8×VDD
-
VDD
V
Low Level Input
VIL
IOUT = 100μA, 3.3MHz
-
0.2×VDD
V
High Level Output
VOH
IOUT = 100μA, 3.3MHz 0.9×VDD
-
VDD
V
Low Level Output
VOL
IOUT = 100μA, 3.3MHz
0
-
0.1×VDD
V
Operating Current for VDD
IDD
-
180
300
μA
Note 5
-
2.3
2.9
mA
Note 6
-
3.6
4.5
mA
Note 7
-
7.2
9.0
mA
Note 5
-
6.9
8.6
mA
Note 6
-
10.9
13.6
mA
Note 7
-
20.8
26.0
mA
Operating Current for VCC
(VCC Supplied Externally)
VCC
ICC
0
Operating Current for VDDB
(VCC Generated by Internal DC/DC)
IDDB
Sleep Mode Current for VDD
IDD, SLEEP
-
1
5
μA
Sleep Mode Current for VCC
ICC, SLEEP
-
2
10
μA
Note 4: Brightness (Lbr) and Supply Voltage for Display (VCC) are subject to the change of the panel
characteristics and the customer’s request.
Note 5: VDD = 2.8V, VCC = 7.25V, 30% Display Area Turn on.
Note 6: VDD = 2.8V, VCC = 7.25V, 50% Display Area Turn on.
Note 7: VDD = 2.8V, VCC = 7.25V, 100% Display Area Turn on.
* Software configuration follows Section 4.4 Initialization.
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3.3 AC Characteristics
3.3.1 68XX-Series MPU Parallel Interface Timing Characteristics:
Symbol
tcycle
Description
Min
Max
Unit
Clock Cycle Time
300
-
ns
tAS
Address Setup Time
0
-
ns
tAH
Address Hold Time
0
-
ns
tDSW
Write Data Setup Time
40
-
ns
tDHW
Write Data Hold Time
7
-
ns
tDHR
Read Data Hold Time
20
-
ns
tOH
Output Disable Time
-
70
ns
tACC
Access Time
-
140
ns
-
ns
-
ns
PWCSL
PWCSH
Chip Select Low Pulse Width (Read)
120
Chip Select Low Pulse width (Write)
60
Chip Select High Pulse Width (Read)
60
Chip Select High Pulse Width (Write)
60
tR
Rise Time
-
40
ns
tF
Fal Time
-
40
ns
* (VDD - VSS = 1.65V to
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3V, Ta = 25°C)
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3.3.2 80XX-Series MPU Parallel Interface Timing Characteristics:
Symbol
Description
Min
Max
Unit
Clock Cycle Time
300
-
ns
tAS
Address Setup Time
10
-
ns
tAH
Address Hold Time
0
-
ns
tDSW
Write Data Setup Time
40
-
ns
tDHW
Write Data Hold Time
7
-
ns
tDHR
Read Data Hold Time
20
-
ns
tOH
Output Disable Time
-
70
ns
tACC
Access Time
-
140
ns
tPWLR
Read Low Time
120
-
ns
tPWLW
Write Low Time
60
-
ns
tPWHR
Read High Time
60
-
ns
tPWHW
Write High Time
60
-
ns
tCS
Chip Select Setup Time
0
-
ns
tCSH
Chip Select Hold Time to Read Signal
0
-
ns
tCSF
Chip Select Hold Time
20
-
ns
tcycle
tR
Rise Time
-
40
ns
tF
Fall Time
-
40
ns
* (VDD - VSS = 1.65V to 3.3V, Ta = 25°C)
( Read Timing )
( Write Timing )
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3.3.3 Serial Interface Timing Characteristics:
Symbol
Description
Min
Max
Unit
Clock Cycle Time
100
-
ns
tAS
Address Setup Time
15
-
ns
tAH
Address Hold Time
15
-
ns
tCSS
Chip Select Setup Time
20
-
ns
tCSH
Chip Select Hold Time
10
-
ns
tDSW
Write Data Setup Time
15
-
ns
tDHW
Write Data Hold Time
15
-
ns
tCLKL
Clock Low Time
20
-
ns
tCLKH
Clock High Time
20
-
ns
tcycle
tR
Rise Time
-
40
ns
tF
Fall Time
-
40
ns
* (VDD - VSS = 1.65V to 3.3V, Ta = 25°C)
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3.3.4 I2C Interface Timing Characteristics:
Symbol
tcycle
tHSTART
Description
Min
Max
Unit
Clock Cycle Time
2.5
-
μs
Start Condition Hold Time
0.6
-
μs
-
ns
Data Hold Time (for “SDAOUT” Pin)
0
Data Hold Time (for “SDAIN” Pin)
300
Data Setup Time
100
-
ns
tSSTART
Start Condition Setup Time
(Only relevant for a repeated Start condition)
0.6
-
μs
tSSTOP
Stop Condition Setup Time
0.6
-
μs
tHD
tSD
tR
Rise Time for Data and Clock Pin
300
ns
tF
Fall Time for Data and Clock Pin
300
ns
-
μs
tIDLE
Idle Time before a New Transmission can Start
1.3
* (VDD - VSS = 1.65V to 3.3V, Ta = 25°C)
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4. Functional Specification
4.1 Commands
Refer to the Technical Manual for the SSD1306
4.2 Power down and Power up Sequence
To protect OEL panel and extend the panel life time, the driver IC power up/down routine should include
a delay period between high voltage and low voltage power sources during turn on/off. It gives the
OEL panel enough time to complete the action of charge and discharge before/after the operation.
4.2.1 Power up Sequence:
VDDD / VDDB on
Power up VDD / VDDB
Send Display off command
Initialization
Clear Screen
Power up VCC
Delay 100ms
(When VCC is stable)
7. Send Display on command
1.
2.
3.
4.
5.
6.
VCC on
Display on
VCC
VDD/VDDB
VSS/Ground
Display
y offf
.2.2 Power down Sequence:
VCCC / VDDD offf
1. Send Display off command
2. Power down VCC / VDD
3. Delay 100ms
(When VCC / VDDB is reach 0 and panel is
completely discharges)
4. Power down VDD
VDD offf
VCC/VDDB
VDD
VSS/Ground
Note 8:
1) Since an ESD protection circuit is connected between VDD and VCC inside the driver IC, VCC
becomes lower than VDD whenever VDD is ON and VCC is OFF.
2) VCC / VDDB should be kept float (disable) when it is OFF.
3) Power Pins (VDD, VCC, VDDB ) can never be pulled to ground under any circumstance.
4) VDD should not be power down before VCC / VDDB power down.
4.3 Reset Circuit
When RES# input is low, the chip is initialized with the following status:
1. Display is OFF
2. 128×64 Display Mode
3. Normal segment and display data column and row address mapping (SEG0 mapped to column
address 00h and COM0 mapped to row address 00h)
4. Shift register data clear in serial interface
5. Display start line is set at display RAM address 0
6. Column address counter is set at 0
7. Normal scan direction of the COM outputs
8. Contrast control register is set at 7Fh
9. Normal display mode (Equivalent to A4h command)
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4.4 Actual Application Example
Command usage and explanation of an actual example
4.4.1 VCC Supplied Externally
<Power up Sequence>
VDD/VCC off State
Set Multiplex Ratio
0xA8, 0x27
Set Pre-Charge Period
0xD9, 0x25
Power up VDD
(RES# as Low State)
Set Display Offset
0xD3, 0x00
Set VCOMH Deselect Level
0xDB, 0x20
Power Stabilized
(Delay Recommended)
Set Display Start Line
0x40
Set Entire Display On/Off
0xA4
Set RES# as High
(3μs Delay Minimum)
Set Charge Pump
0x8D, 0x10
Set Normal/Inverse Display
0xA6
Initialized State
(Parameters as Default)
Set Segme t Re-Map
0xA1
Clear Screen
Set Display Off
0xAE
Set COM Output Scan Direction
0xC8
Power up VCC
(100ms Delay Recommended)
Initial Settings
Configuration
Set COM Pins Hardware Configuration
0xDA, 0x12
Set Display On
0xAF
Set Display Clock Divide Ratio/Oscillator Frequency
0xD5, 0x80
Set Contrast Control
0x81, 0xAF
Display Data Sent
If the noise is accidentally occurred at the displaying window during the operation, please reset
the display in order to recover the display function.
<Power down Sequence>
Normal Operation
Power down VCC
(100ms Delay Recommended)
Set Display Off
0xAE
Power down VDD
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VDD/VCC off State
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<Entering Sleep Mode>
Normal Operation
Power down VCC
Set Display Off
0xAE
Sleep Mode
<Exiting Sleep Mode>
Sleep Mode
Set Display On
0xAF
Power up VCC
(100ms Delay Recommended)
Normal Operation
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4.4.2 VCC Generated by Internal DC/DC Circuit
<Power up Sequence>
VDD/VDDB off State
Set Display Clock Divide Ratio/Oscillator Frequency
0xD5, 0x80
Set Contrast Control
0x81, 0xAF
Power up VDD
(RES# as Low State)
Set Multiplex Ratio
0xA8, 0x27
Set Pre-Charge Period
0xD9, 0x25
Power Stabilized
(Delay Recommended)
Set Display Offset
0xD3, 0x00
Set VCOMH Deselect Level
0xDB, 0x20
Power up VDDB
(100ms Delay Recommended)
Set Display Start Line
0x40
Set Entire Display On/Off
0xA4
Set RES# as High
(3μs Delay Minimum)
Set Charge Pump
0x8D 0x14
Set Normal/Inverse Display
0xA6
Initialized State
(Parameters as Default)
Set Segment Re-Map
0xA1
Clear Screen
Set Display Off
0xAE
Set COM Output Scan Direction
0xC8
Set Display On
0xAF
Initial Settings
Configuration
Set COM Pins Hardware Configuration
0xDA, 0x12
Display Data Sent
If the noise is accidentally occurred at the displaying window during the operation, please reset
the display in order to recover the display function.
<Power down Sequence>
Normal Operation
Power Stabilized
(100ms Delay Recommended)
Set Display Off
0xAE
Power down VDDB
(50ms Delay Recommended)
Set Charge Pump
0x8D, 0x10
Power down VDD
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<Entering Sleep Mode>
Normal Operation
Set Charge Pump
0x8D, 0x10
Set Display Off
0xAE
Power down VDDB
Sleep Mode
<Exiting Sleep Mode>
Sleep Mode
Set Charge Pump
0x8D, 0x14
Power up VDDB
(100ms Delay Recommended)
Set Display On
0xAF
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Normal Operation
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eliabiilitty
5.. Re
5.1 Contents of Reliability Tests
Item
Conditions
High Temperature Operation
70°C, 120 hrs
Low Temperature Operation
-40°C, 120 hrs
High Temperature Storage
80°C, 120 hrs
Low Temperature Storage
-40°C, 120 hrs
High Temperature/Humidity Operation
60°C, 90% RH 120 hrs
Thermal Shock
-40°C ⇔ 80°C, 24 cycles
60 mins dwell
Criteria
The operational
functions work.
* The samples used for the above tests do not include polarizer.
* No moisture condensation is observed during tests.
5.2 Failure Check Standard
After the completion of the described reliability test, the samples were left at room temperature for 2
hrs prior to conducting the failure test at 23±5°C; 55±15% RH.
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g Qua
ality Control Spe
eciffic
catio
ons
6. Outgoing
6.1 Environment Required
Customer’s test & measurement are required to be conducted under the following conditions:
Temperature:
23 ± 5°C
Humidity:
55 ± 15% RH
Fluorescent Lamp:
30W
≥ 50cm
Distance between the Panel & Lamp:
Distance between the Panel & Eyes of the Inspector: ≥ 30cm
Finger glove (or finger cover) must be worn by the inspector.
Inspection table or jig must be anti-electrostatic.
6.2 Sampling Plan
Level II, Normal Inspection, Single Sampling, MIL-STD-105E
6.3 Criteria & Acceptable Quality Level
Partition
AQL
Definition
Major
0.65
Defects in Pattern Check (Display On)
Minor
1.0
Defects in Cosmetic Check (Display Off)
6 3.1 Cosmetic Check (Displa Off) in Non-Active Area
Classification
Check Item
Criteria
X > 6 mm (Along with Edge)
Y > 1 mm (Perpendicular to edge)
X
Panel General Chipping
Y
Minor
X
Y
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6.3.1 Cosmetic Check (Display Off) in Non-Active Area (Continued)
Check Item
Classification
Criteria
Any crack is not allowable.
Panel Crack
Minor
Copper Exposed
(Even Pin or Film)
Minor
Film or Trace Damage
Minor
Terminal Lead Prober Mark
Acceptable
Glue or Contamination on Pin
(Couldn’t Be Removed by Alcohol)
Minor
Ink Marking on Back Side of panel
(Exclude on Film)
Acceptable
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Not Allowable by Naked Eye Inspection
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6.3.2 Cosmetic Check (Display Off) in Active Area
It is recommended to execute in clear room environment (class 10k) if actual in necessary.
Check Item
Classification
Criteria
Any Dirt & Scratch on Polarizer’s
Protective Film
Acceptable
Ignore for not Affect the Polarizer
Scratches, Fiber, Line-Shape Defect
(On Polarizer)
Minor
Dirt, Black Spot, Foreign Material,
(On Polarizer)
Minor
Dent, Bubbles, White spot
(Any Transparent Spot on Polarizer)
Minor
Fingerprint, Flow Mark
(On Polarizer)
Minor
Ignore
W ≤ 0.1
W > 0.1, L ≤ 2
n≤1
L>2
n=0
Φ ≤ 0.1
Ignore
0.1 < Φ ≤ 0.25
n≤1
0.25 < Φ
n=0
Φ ≤ 0.5
Î Ignore if no Influence on Display
0.5 < Φ
n=0
N t Allowable
* Protective film should not be tear off when cosmetic check.
** Definition of W & L & Φ (Unit: mm): Φ = (a + b) / 2
L
W
b: Minor Axis
a: Major Axis
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6.3.3 Pattern Check (Display On) in Active Area
Check Item
Classification
No Display
Major
Missing Line
Major
Pixel Short
Major
Darker Pixel
Major
Wrong Display
Major
Un-uniform
Major
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7. Package Specifications
EPE COVER FOAM 351x212x1,
ANTISTATIC x 1 Pcs
x 1 pcs (Empty)
B Pcs Tray Vacuum packing
Module
EPE PROTECTTIVE
x A pcs
Staggered Stacking
Tray 420x285 T=0.8mm
Primary Box C SET
Wrapped with adhesive tape
x B pcs
Vacuum packing bag
EPE PROTECTTIVE
370mm x 2 mm x 20mm
CARTON BOX
Prima L450mm x W296 x H110, B wave
x C Pcs
Label
Carton Box L464mm x W313mm x H472mm, AB wave
(Major / Maximum)
Item
Quantity
Module
900
per Primary Box
Holding Trays
(A)
15
per Primary Box
Total Trays
(B)
16
per Primary Box (Including 1 Empty Tray)
Primary Box
(C)
1~4
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per Carton (4 as Major / Maximum)
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8.. Prreca
aution
ns Whe
en Usin
ng These OEL Displa
ay Modu
ules
8.1 Handling Precautions
1)
2)
3)
4)
5)
6)
Since the display panel is being made of glass, do not apply mechanical impacts such us dropping
from a high position.
If the display panel is broken by some accident and the internal organic substance leaks out, be
careful not to inhale nor lick the organic substance.
If pressure is applied to the display surface or its neighborhood of the OEL display module, the cell
structure may be damaged and be careful not to apply pressure to these sections.
The polarizer covering the surface of the OEL display module is soft and easily scratched. Please
be careful when handling the OEL display module.
When the surface of the polarizer of the OEL display module has soil, clean the surface. It takes
advantage of by using following adhesion tape.
* Scotch Mending Tape No. 810 or an equivalent
Never try to breathe upon the soiled surface nor wipe the surface using cloth containing solvent
such as ethyl alcohol, since the surface of the polarizer will become cloudy.
Also, pay attention that the following liquid and solvent may spoil the polarizer:
* Water
* Ketone
* Aromatic Solvents
Hold OEL display module very carefully when placing OEL display module into the system housing.
Do not apply excessive stress or pressure to OEL display module. And, do not over bend the film
with electrode pattern layouts. These stresses will influence the display performance Also,
secure sufficient rigidity for the outer cases.
7)
8)
9)
10)
Do not apply stress to the driver IC and the surrounding molded sections.
Do not disassemble nor modify the OEL display module.
Do not apply input signals while the logic power is off.
Pay sufficient attention to the working environments when handing OEL display modules to prevent
occurrence of element breakage accidents by static electricity.
* Be sure to make human body grounding when handling OEL display modules.
* Be sure to ground tools to use or assembly such as soldering irons.
* To suppress generation of static electricity, avoid carrying out assembly work under dry
environments.
* Protective film is being applied to the surface of the display panel of the OEL display module.
Be careful since static electricity may be generated when exfoliating the protective film.
11) Protection film is being applied to the surface of the display panel and removes the protection film
before assembling it. At this time, if the OEL display module has been stored for a long period of
time, residue adhesive material of the protection film may remain on the surface of the display
panel after removed of the film. In such case, remove the residue material by the method
introduced in the above Section 5).
12) If electric current is applied when the OEL display module is being dewed or when it is placed under
high humidity environments, the electrodes may be corroded and be careful to avoid the above.
8.2 Storage Precautions
1)
When storing OEL display modules, put them in static electricity preventive bags avoiding exposure
to direct sun light nor to lights of fluorescent lamps. and, also, avoiding high temperature and high
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2)
humidity environment or low temperature (less than 0°C) environments. (We recommend you to
store these modules in the packaged state when they were shipped from EastRising Technology Co
Ltd.)
At that time, be careful not to let water drops adhere to the packages or bags nor let dewing occur
with them.
If electric current is applied when water drops are adhering to the surface of the OEL display
module, when the OEL display module is being dewed or when it is placed under high humidity
environments, the electrodes may be corroded and be careful about the above.
8.3 Designing Precautions
1)
2)
3)
4)
5)
6)
7)
8)
The absolute maximum ratings are the ratings which cannot be exceeded for OEL display module,
and if these values are exceeded, panel damage may be happen.
To prevent occurrence of malfunctioning by noise, pay attention to satisfy the VIL and VIH
specifications and, at the same time, to make the signal line cable as short as possible.
We recommend you to install excess current preventive unit (fuses, etc.) to the power circuit (VDD).
(Recommend value: 0.5A)
Pay sufficient attention to avoid occurrence of mutual noise interference with the neighboring
devices.
As for EMI, take necessary measures on the equipment side basically.
When fastening the OEL display module, fasten the external plastic housing section.
If power supply to the OEL display module is forcibly shut down by such errors as taking out the
main battery while the OEL display panel is in ope ation, we cannot guarantee the quality of this
OEL display module.
The electric potential to be conne ted to the rear fa e f the IC chip should be as follows: SSD1306
* Connection (contact) to any other potential than the above may lead to rupture of the IC.
8.4 Precautions when disposing of the OEL display modules
1)
Request the qualified companies to handle industrial wastes when disposing of the OEL display
modules. Or, when burn ng them, be sure to observe the environmental and hygienic laws and
regulations.
8.5 Other Precautions
1)
2)
3)
4)
5)
When an OEL display module is operated for a long of time with fixed pattern may remain as an
after image or slight contrast deviation may occur.
Nonetheless, if the operation is interrupted and left unused for a while, normal state can be
restored. Also, there will be no problem in the reliability of the module.
To protect OEL display modules from performance drops by static electricity rapture, etc., do not
touch the following sections whenever possible while handling the OEL display modules.
* Pins and electrodes
* Pattern layouts such as the FPC
With this OEL display module, the OEL driver is being exposed.
Generally speaking,
semiconductor elements change their characteristics when light is radiated according to the
principle of the solar battery. Consequently, if this OEL driver is exposed to light, malfunctioning
may occur.
* Design the product and installation method so that the OEL driver may be shielded from light in
actual usage.
* Design the product and installation method so that the OEL driver may be shielded from light
during the inspection processes.
Although this OEL display module stores the operation state data by the commands and the
indication data, when excessive external noise, etc. enters into the module, the internal status may
be changed. It therefore is necessary to take appropriate measures to suppress noise generation
or to protect from influences of noise on the system design.
We recommend you to construct its software to make periodical refreshment of the operation
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statuses (re-setting of the commands and re-transference of the display data) to cope with
catastrophic noise.
Warran
nty::
The warranty period shall last twelve (12) months from the date of delivery. Buyer shall be completed to
assemble all the processes within the effective twelve (12) months. EastRising Technology Co.,Ltd shall be
liable for replacing any products which contain defective material or process which do not conform to the
product specification, applicable drawings and specifications during the warranty period. All products must be
preserved, handled and appearance to permit efficient handling during warranty period. The warranty
coverage would be exclusive while the returned goods are out of the terms above.
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