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RTL8201CP
SINGLE-CHIP/SINGLE-PORT
10/100M FAST ETHERNET PHYCEIVER
(With Auto Crossover)
DATASHEET
Rev. 1.21
12 October 2004
Track ID: JATR-1076-21
RTL8201CP
Datasheet
COPYRIGHT
©2004 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
1.0
1.1
Release Date
2003/06/09
2003/09/26
1.2
2004/01/20
1.21
2004/10/12
Summary
First release.
Minor cosmetic changes.
Modify LED Pin behavior.
Add LED multi-mode definition (7.5 LED and PHY Address
Configuration, page 19).
Add Power dissipation info (Table 31).
Bit <0:8> default setting changed to 0 (Table 9).
Bit <0:13> default setting changed to 0 (Table 9).
Bit <5:7> default setting changed to 0 (Table 14).
Bit <17:5> default setting changed to 1 (Table 17).
Bit <25:0> default setting changed to 0 (Table 20).
Bit <25:1> default setting changed to 0 (Table 20).
Bit <25:11~7> default setting changed to 00001 (Table 20).
Package additions. See section 10, Ordering Information, page 33.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
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Track ID: JATR-1076-21 Rev. 1.21
RTL8201CP
Datasheet
Table of Contents
1.
GENERAL DESCRIPTION................................................................................................................................................1
2.
FEATURES...........................................................................................................................................................................1
3.
BLOCK DIAGRAM.............................................................................................................................................................2
4.
PIN ASSIGNMENTS ...........................................................................................................................................................3
5.
PIN DESCRIPTION ............................................................................................................................................................4
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
5.8.
6.
REGISTER DESCRIPTIONS ............................................................................................................................................8
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
6.10.
6.11.
6.12.
7.
MII INTERFACE ............................................................................................................................................................4
SNI (SERIAL NETWORK INTERFACE) 10MBPS ONLY....................................................................................................5
CLOCK INTERFACE .......................................................................................................................................................5
10MBPS/100MBPS NETWORK INTERFACE ....................................................................................................................5
DEVICE CONFIGURATION INTERFACE ...........................................................................................................................6
LED INTERFACE/PHY ADDRESS CONFIGURATION.......................................................................................................6
POWER AND GROUND PINS ..........................................................................................................................................7
RESET AND OTHER PINS ...............................................................................................................................................7
REGISTER 0 BASIC MODE CONTROL REGISTER ............................................................................................................8
REGISTER 1 BASIC MODE STATUS REGISTER ...............................................................................................................9
REGISTER 2 PHY IDENTIFIER REGISTER 1 ...................................................................................................................9
REGISTER 3 PHY IDENTIFIER REGISTER 2 ...................................................................................................................9
REGISTER 4 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR) ....................................................................10
REGISTER 5 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR)......................................................10
REGISTER 6 AUTO-NEGOTIATION EXPANSION REGISTER (ANER) .............................................................................11
REGISTER 16 NWAY SETUP REGISTER (NSR) ............................................................................................................12
REGISTER 17 LOOPBACK, BYPASS, RECEIVER ERROR MASK REGISTER (LBREMR) ................................................12
REGISTER 18 RX_ER COUNTER (REC).....................................................................................................................13
REGISTER 19 SNR DISPLAY REGISTER ......................................................................................................................13
REGISTER 25 TEST REGISTER .....................................................................................................................................13
FUNCTIONAL DESCRIPTION.......................................................................................................................................14
7.1.
7.1.1.
7.1.2.
7.2.
7.2.1.
7.2.2.
7.2.3.
7.2.4.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.8.1.
7.8.2.
7.8.3.
7.9.
7.10.
7.11.
MII AND MANAGEMENT INTERFACE ..........................................................................................................................14
Data Transition.....................................................................................................................................................14
Serial Management...............................................................................................................................................15
AUTO-NEGOTIATION AND PARALLEL DETECTION ......................................................................................................16
Setting the Medium Type and Interface Mode to MAC.........................................................................................16
UTP Mode and MII Interface ...............................................................................................................................16
UTP Mode and SNI Interface ...............................................................................................................................17
Fiber Mode and MII Interface..............................................................................................................................17
FLOW CONTROL SUPPORT ..........................................................................................................................................17
HARDWARE CONFIGURATION AND AUTO-NEGOTIATION ............................................................................................18
LED AND PHY ADDRESS CONFIGURATION ................................................................................................................19
SERIAL NETWORK INTERFACE ....................................................................................................................................20
POWER DOWN, LINK DOWN, POWER SAVING, AND ISOLATION MODES ......................................................................20
MEDIA INTERFACE .....................................................................................................................................................20
100Base-TX ..........................................................................................................................................................20
100Base-FX Fiber Mode Operation.....................................................................................................................21
10Base-T TX/RX ...................................................................................................................................................21
REPEATER MODE OPERATION.....................................................................................................................................22
RESET, AND TRANSMIT BIAS ......................................................................................................................................22
3.3V POWER SUPPLY AND VOLTAGE CONVERSION CIRCUIT .......................................................................................22
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RTL8201CP
Datasheet
7.12.
8.
FAR END FAULT INDICATION ......................................................................................................................................22
CHARACTERISTICS .......................................................................................................................................................23
8.1.
8.1.1.
8.1.2.
8.1.3.
8.1.4.
8.2.
8.2.1.
8.2.2.
8.2.3.
8.2.4.
8.2.5.
8.3.
8.4.
9.
DC CHARACTERISTICS ...............................................................................................................................................23
Absolute Maximum Ratings ..................................................................................................................................23
Operating Conditions ...........................................................................................................................................23
Power Dissipation ................................................................................................................................................23
Input Voltage: Vcc ................................................................................................................................................23
AC CHARACTERISTICS ...............................................................................................................................................24
MII Transmission Cycle Timing............................................................................................................................24
MII Reception Cycle Timing .................................................................................................................................25
SNI Transmission Cycle Timing............................................................................................................................27
SNI Reception Cycle Timing .................................................................................................................................28
MDC/MDIO Timing..............................................................................................................................................29
CRYSTAL CHARACTERISTICS ......................................................................................................................................30
TRANSFORMER CHARACTERISTICS ............................................................................................................................30
MECHANICAL DIMENSIONS .......................................................................................................................................31
9.1.
10.
MECHANICAL DIMENSIONS NOTES ............................................................................................................................32
ORDERING INFORMATION......................................................................................................................................33
List of Tables
Table 1. MII Interface..................................................................................................................................4
Table 2. SNI (Serial Network Interface) 10Mbps Only ..............................................................................5
Table 3. Clock Interface ..............................................................................................................................5
Table 4. 10Mbps/100Mbps Network Interface............................................................................................5
Table 5. Device Configuration Interface .....................................................................................................6
Table 6. LED Interface/PHY Address Configuration..................................................................................6
Table 7. Power and Ground Pins .................................................................................................................7
Table 8. Reset and Other Pins......................................................................................................................7
Table 9. Register 0 Basic Mode Control Register .......................................................................................8
Table 10. Register 1 Basic Mode Status Register..........................................................................................9
Table 11. Register 2 PHY Identifier Register 1.............................................................................................9
Table 12. Register 3 PHY Identifier Register 2.............................................................................................9
Table 13. Register 4 Auto-Negotiation Advertisement Register (ANAR)..................................................10
Table 14. Register 5 Auto-Negotiation Link Partner Ability Register (ANLPAR) ....................................10
Table 15. Register 6 Auto-Negotiation Expansion Register (ANER) .........................................................11
Table 16. Register 16 NWay Setup Register (NSR)....................................................................................12
Table 17. Register 17 Loopback, Bypass, Receiver Error Mask Register (LBREMR) ..............................12
Table 18. Register 18 RX_ER Counter (REC)............................................................................................13
Table 19. Register 19 SNR Display Register ..............................................................................................13
Table 20. Register 25 Test Register.............................................................................................................13
Table 21. Serial Management ......................................................................................................................15
Table 22. Setting the Medium Type and Interface Mode to MAC..............................................................16
Table 23. UTP Mode and MII Interface ......................................................................................................16
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RTL8201CP
Datasheet
Table 24. UTP Mode and SNI Interface......................................................................................................17
Table 25. Fiber Mode and MII Interface .....................................................................................................17
Table 26. Auto-Negotiation Mode Pin Settings ..........................................................................................18
Table 27. LED Definitions ..........................................................................................................................19
Table 28. Power Saving Mode Pin Settings ................................................................................................20
Table 29. Absolute Maximum Ratings........................................................................................................23
Table 30. Operating Conditions...................................................................................................................23
Table 31. Power Dissipation........................................................................................................................23
Table 32. Input Voltage: Vcc.......................................................................................................................23
Table 33. MII Transmission Cycle Timing .................................................................................................24
Table 34. MII Reception Cycle Timing.......................................................................................................25
Table 35. SNI Transmission Cycle Timing .................................................................................................27
Table 36. SNI Reception Cycle Timing ......................................................................................................28
Table 37. MDC/MDIO Timing....................................................................................................................29
Table 38. Crystal Characteristics.................................................................................................................30
Table 39. Transformer Characteristics ........................................................................................................30
Table 40. Ordering Information...................................................................................................................33
List of Figures
Figure 1. Block Diagram .............................................................................................................................2
Figure 2. Pin Assignments...........................................................................................................................3
Figure 3. Read Cycle .................................................................................................................................15
Figure 4. Write Cycle ................................................................................................................................15
Figure 5. LED and PHY Address Configuration.......................................................................................19
Figure 7. MII Transmission Cycle Timing-1.............................................................................................24
Figure 8. MII Transmission Cycle Timing-2.............................................................................................25
Figure 9. MII Reception Cycle Timing-1 ..................................................................................................26
Figure 10. MII Reception Cycle Timing-2 ..................................................................................................26
Figure 11. SNI Transmission Cycle Timing-1 ............................................................................................27
Figure 12. SNI Transmission Cycle Timing-2 ............................................................................................27
Figure 13. SNI Reception Cycle Timing-1..................................................................................................28
Figure 14. SNI Reception Cycle Timing-2..................................................................................................28
Figure 15. MDC/MDIO Timing ..................................................................................................................29
Figure 16. MDC/MDIO MAC to PHY Transmission Without Collision ...................................................29
Figure 17. MDC/MDIO PHY to MAC Reception Without Error ...............................................................30
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Track ID: JATR-1076-21 Rev. 1.21
RTL8201CP
Datasheet
1.
General Description
The RTL8201CP is a single-chip/single-port PHYceiver with an MII (Media Independent Interface)/SNI
(Serial Network Interface). It implements all 10/100M Ethernet Physical-layer functions including the
Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), Twisted Pair Physical Medium
Dependent Sublayer (TP-PMD), with an auto crossover detection function, 10Base-Tx Encoder/Decoder,
and Twisted-Pair Media Access Unit (TPMAU).
A PECL (Pseudo Emitter Coupled Logic) interface is supported to connect with an external 100Base-FX
fiber optical transceiver. The chip utilizes an advanced CMOS process to meet low voltage and low
power requirements. With on-chip DSP (Digital Signal Processing) technology, the chip provides
excellent performance under all operating conditions.
The RTL8201CP can be used for applications such as those for a Network Interface Adapter, MAU
(Media Access Unit), CNR (Communication and Network Riser), ACR (Advanced Communication
Riser), an Ethernet hub, and an Ethernet switch. In addition, it can be used in any embedded system with
an Ethernet MAC that needs a UTP physical connection or Fiber PECL interface to an external
100Base-FX optical transceiver module.
2.
Features
The Realtek RTL8201CP is a Fast Ethernet PHYceiver with selectable MII or SNI interface to the MAC
chip. It provides the following features:
Supports repeater mode
Pin-to-pin compatible with the RTL8201BL
Supports MII and 7-wire SNI (Serial Network
Interface)
Adaptive Equalization
10/100Mbps operation
Flow control support
Full/half duplex operation
25MHz crystal/oscillator as clock source
Twisted pair or fiber mode output
IEEE 802.3/802.3u compliant
Auto-Negotiation
Supports power down mode
Supports IEEE 802.3u clause 28; 1.8V
operation with 3.3V IO signal tolerance
Supports operation under Link Down Power
Saving mode
Low dual power supply, 1.8V and 3.3V; 1.8V
is generated by an internal regulator
Supports Base Line Wander (BLW)
compensation
0.18µm CMOS process
Network status LEDs
48-pin LQFP package
Supports auto crossover detection (new
RTL8201CP function)
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
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Track ID: JATR-1076-21 Rev. 1.21
RTL8201CP
Datasheet
3.
Block Diagram
100M
MII
Interface
SNI
Interface
5B 4B
Decoder
10/100
half/full
Switch
Logic
Data
Alignment
4B 5B
Encoder
Descrambler
TXD
TXC 25M
Scrambler
10/100M Auto-negotiation
Control Logic
RXD
RXC 25M
Link pulse
10M
TXC10
TXD10
RXC10
RXD10
TXC 25M
TXD
Manchester coded
waveform
10M Output waveform
shaping
Data Recovery
Receive low pass filter
TD+
Parrallel
to Serial
3 Level
Driver
TXO+
TXO -
Variable Current
Baseline
wander
Correction
3 Level
Comparator
MLT-3
to NRZI
RXC 25M
RXD
Serial to
Parrallel
Peak
Detect
ck
data
Adaptive
Equalizer
RXIN+
RXIN-
Master
PPL
Slave
PLL
Control
Voltage
25M
Figure 1. Block Diagram
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
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Track ID: JATR-1076-21 Rev. 1.21
RTL8201CP
Datasheet
25. MDC
26. MDIO
27. NC
28. RTSET
29. AGND
30. TPRX-
31. TPRX+
32. PWFBOUT
33. TPTX-
34. TPTX+
35. AGND
Pin Assignments
36. AVDD33
37. ANE
24. RXER
/FXEN
38. DUPLEX
23. CRS
39. SPEED
22. RXDV
40. RPTR
21. RXD0
41. LDPS
20. RXD1
42. RESETB
19. RXD2
RTL8201CP
43. ISOLATE
18. RXD3
12. LED2/
PHYAD2
11. DGND
13. LED3/
PHYAD3
10. LED1/
PHYAD1
48. DVDD33
9. LED0/
PHYAD0
14. DVDD33
8. PWFBIN
47. X2
7. TXC
15. LED4/
PHYAD4
6. TXD0
46. X1
5. TXD1
16. RXC
3. TXD3
45. DGND
2. TXEN
17. DGND
1. COL
44. MII/SNIB
4. TXD2
4.
Figure 2. Pin Assignments
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
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Track ID: JATR-1076-21 Rev. 1.21
RTL8201CP
Datasheet
5.
Pin Description
LI: Latched Input during Power up or Reset
O: Output
IO: Bi-directional input and output
P: Power
I: Input
5.1. MII Interface
Name
TXC
Type
O
Pin No.
7
TXEN
I
2
TXD[3:0]
I
3, 4, 5, 6
RXC
O
16
COL
LI/O
1
CRS
LI/O
23
RXDV
O
22
RXD[3:0]
O
18, 19, 20, 21
RXER/
FXEN
LI/O
24
Table 1. MII Interface
Description
Transmit Clock.
This pin provides a continuous clock as a timing reference for TXD[3:0] and
TXEN.
Transmit Enable.
The input signal indicates the presence of valid nibble data on TXD[3:0].
Transmit Data.
The MAC will source TXD[0..3] synchronous with TXC when TXEN is
asserted.
Receive Clock.
This pin provides a continuous clock reference for RXDV and RXD[0..3]
signals. RXC is 25MHz in 100Mbps mode and 2.5Mhz in 10Mbps mode.
Collision Detect.
COL is asserted high when a collision is detected on the media.
During power on reset, this pin status is latched to determine at which LED
mode to operate:
0: CP LED mode
1: BL LED mode
An internal weak pull low resistor sets this to the default CP LED mode. It is possible
to use an external 5.1KΩ pull high resistor to enable BL LED mode.
Carrier Sense.
This pin’s signal is asserted high if the media is not in Idle state.
An internal weak pull low resistor sets this to normal operation mode. An external
5.1KΩ pull low resistor could be reserved to ensure operating at normal mode.
Receive Data Valid.
This pin’s signal is asserted high when received data is present on the RXD[3:0]
lines. The signal is de-asserted at the end of the packet. The signal is valid on
the rising edge of the RXC.
Receive Data.
These are the four parallel receive data lines aligned on the nibble boundaries
driven synchronously to the RXC for reception by the external physical unit
(PHY).
Receive Error.
If a 5B decode error occurs, such as invalid /J/K/, invalid /T/R/, or invalid
symbol, this pin will go high.
Fiber/UTP Enable.
During power on reset, this pin status is latched to determine the media mode to
operate in.
1: Fiber mode
0: UTP mode
An internal weak pull low resistor sets this to the default of UTP mode. It is possible to
use an external 5.1KΩ pull high resistor to enable fiber mode.
After power on, the pin operates as the Receive Error pin.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
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Track ID: JATR-1076-21 Rev. 1.21
RTL8201CP
Datasheet
Name
MDC
Type
I
Pin No.
25
MDIO
IO
26
Description
Management Data Clock.
This pin provides a clock synchronous to MDIO, which may be asynchronous to
the transmit TXC and receive RXC clocks. The clock rate can be up to 2.5MHz.
Management Data Input/Output.
This pin provides the bi-directional signal used to transfer management
information.
5.2. SNI (Serial Network Interface) 10Mbps Only
Name
COL
RXD0
CRS
RXC
Type
O
O
O
O
TXD0
TXC
I
O
TXEN
I
Table 2. SNI (Serial Network Interface) 10Mbps Only
Pin No.
Description
1
Collision Detect.
21
Received Serial Data.
23
Carrier Sense.
16
Receive Clock.
Resolved from received data.
6
Transmit Serial Data.
7
Transmit Clock.
Generated by PHY.
2
Transmit Enable.
For MAC to indicate transmit operation.
5.3. Clock Interface
Name
X2
Type
O
Pin No.
47
X1
I
46
Table 3. Clock Interface
Description
25MHz Crystal Output.
This pin provides the 25MHz crystal output. It must be left open when an external
25MHz oscillator drives X1.
25MHz Crystal Input.
This pin provides the 25MHz crystal input. If a 25MHz oscillator is used, connect
X1 to the oscillator’s output (see 8.3 Crystal Characteristics, page 30, for clock
source specifications.
5.4. 10Mbps/100Mbps Network Interface
Name
TPTX+
TPTX-
Type
O
O
RTSET
I
TPRX+
TPRX-
I
I
Table 4. 10Mbps/100Mbps Network Interface
Pin No.
Description
34
Transmit Output.
33
Differential transmit output pair shared by 100Base-TX, 100Base-FX and
10Base-T modes. When configured as 100Base-TX, output is an MLT-3 encoded
waveform. When configured as 100Base-FX, the output is pseudo-ECL level.
28
Transmit Bias Resistor Connection.
This pin should be pulled to GND by a 2KΩ (1%) resistor to define driving
current for the transmit DAC. The resistance value may be changed, depending on
experimental results of the RTL8201CP.
31
Receive Input.
30
Differential receive input pair shared by 100Base-TX, 100Base-FX, and 10Base-T
modes.
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Track ID: JATR-1076-21 Rev. 1.21
RTL8201CP
Datasheet
5.5. Device Configuration Interface
Name
ISOLATE
Type
I
Pin No.
43
RPTR
I
40
SPEED
LI
39
DUPLEX
LI
38
ANE
LI
37
LDPS
I
41
MII/SNIB
LI/O
44
Table 5. Device Configuration Interface
Description
Set high to isolate the RTL8201CP from the MAC. This will also isolate the MDC/MDIO
management interface. In this mode, the power consumption is minimum. This pin can be
directly connected to GND or VCC.
Set high to put the RTL8201CP into repeater mode. This pin can be directly connected
to GND or VCC.
This pin is latched to input during a power on or reset condition. Set high to put
the RTL8201CP into 100Mbps operation. This pin can be directly connected to GND or
VCC.
This pin is latched to input during a power on or reset condition. Set high to
enable full duplex. This pin can be directly connected to GND or VCC.
This pin is latched to input during a power on or reset condition. Set high to
enable Auto-negotiation mode, set low to force mode. This pin can be directly
connected to GND or VCC.
Set high to put the RTL8201CP into LDPS mode. This pin can be directly connected
to GND or VCC. See 7.7 Power Down, Link Down, Power Saving, and Isolation
Modes, page 20, for more information.
This pin is latched to input during a power on or reset condition. Pull high to set
the RTL8201CP into MII mode operation. Set low for SNI mode. This pin can be
directly connected to GND or VCC.
5.6. LED Interface/PHY Address Configuration
These five pins are latched into the RTL8201CP during power up reset to configure the PHY address
[0:4] used for the MII management register interface. In normal operation, after initial reset, they are used
as driving pins for status indicator LEDs. The driving polarity, active low or active high, is determined by
each latched status of the PHY address [4:0] during power-up reset. If the latched status is High, then it
will be active low. If the latched status is Low, then it will be active high. See section 7.5 LED and PHY
Address Configuration, page 19, for more information.
Name
PHYAD0/
LED0
Type
LI/O
PHYAD1/
LED1
LI/O
PHYAD2/
LED2
LI/O
Table 6. LED Interface/PHY Address Configuration
Pin No.
Description
9
PHY Address [0].
Link LED.
Lit when linked.
10
PHY Address [1].
Full Duplex LED.
Lit when in Full Duplex operation.
12
PHY Address [2].
CP LED Mode: 10 ACT LED
Blinking when transmitting or receiving data.
BL LED Mode: Link 10 / ACT LED
Active when linked in 10Base-T mode, and blinking when transmitting or
receiving data.
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RTL8201CP
Datasheet
Name
PHYAD3/
LED3
Type
LI/O
Pin No.
13
PHYAD4/
LED4
LI/O
15
Description
PHY Address [3].
CP LED Mode: 100 ACT LED
Blinking when transmitting or receiving data.
BL LED Mode: Link 100 / ACT LED
Active when linked in 100Base-T mode, and blinking when transmitting or
receiving data.
PHY Address [4].
Collision LED.
Blinks when collisions occur.
5.7. Power and Ground Pins
Name
AVDD33
Type
P
Pin No.
36
AGND
P
29, 35
DVDD33
P
14, 48
DGND
P
11, 17, 45
Table 7. Power and Ground Pins
Description
3.3V Analog Power Input.
3.3V power supply for analog circuit; should be well decoupled.
Analog Ground.
Should be connected to a larger GND plane.
3.3V Digital Power Input.
3.3V power supply for digital circuit.
Digital Ground.
Should be connected to a larger GND plane.
5.8. Reset and Other Pins
Name
RESETB
Type
I
Pin No.
42
PWFBOUT
O
32
PWFBIN
NC
I
8
27
Table 8. Reset and Other Pins
Description
RESETB.
Set low to reset the chip. For a complete reset, this pin must be asserted low
for at least 10ms.
Power Feedback Output.
Be sure to connect a 22uF tantalum capacitor for frequency compensation and
a 0.1uF capacitor for noise de-coupling. Then connect this pin through a
ferrite bead to PWFBIN (pin8). The connection method is outlined in
7.11 3.3V Power Supply and Voltage Conversion Circuit, page 22.
Power Feedback Input. See the PWFBOUT description above.
Not Connected.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
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Track ID: JATR-1076-21 Rev. 1.21
RTL8201CP
Datasheet
6.
Register Descriptions
This section describes the functions and usage of the registers available in the RTL8201CP.
In this section the following abbreviations are used:
RO: Read Only
RW: Read/Write
6.1. Register 0 Basic Mode Control Register
Address
0:15
0:14
0:13
0:12
0:11
0:10
0:9
0:8
0:7:0
Table 9. Register 0 Basic Mode Control Register
Description
This bit sets the status and control registers of the PHY in a default
state. This bit is self-clearing.
1: Software reset
0: Normal operation
Loopback This bit enables loopback of transmit data nibbles TXD3:0 to the
receive data path.
1: Enable loopback
0: Normal operation
Spd_Set
This bit sets the network speed.
1: 100Mbps
0: 10Mbps
After completing auto negotiation, this bit will reflect the Speed status.
1: 100Base-T
0: 10Base-T)
When 100Base-FX mode is enabled, this bit=1 and is read only.
Auto
This bit enables/disables the NWay auto-negotiation function.
Negotiation 1: Enable auto-negotiation; bits 0:13 and 0:8 will be ignored.
Enable
0: Disable auto-negotiation; bits 0:13 and 0:8 will determine the link
speed and the data transfer mode, respectively.
When 100Base-FX mode is enabled, this bit=0 and is read only.
Power Down This bit turns down the power of the PHY chip, including the internal
crystal oscillator circuit. The MDC, MDIO is still alive for accessing
the MAC.
1: Power down
0: Normal operation
Reserved
Restart Auto This bits allows the NWay auto-negotiation function to be reset.
Negotiation 1: Re-start auto-negotiation
0: Normal operation
Duplex
This bit sets the duplex mode if auto-negotiation is disabled
Mode
(bit 0:12=0).
1: Full duplex
0: Half duplex
After completing auto-negotiation, this bit will reflect the duplex status.
1: Full duplex
0: Half duplex
Reserved
Name
Reset
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
8
Mode
RW
Default
0
RW
0
RW
0
RW
1
RW
0
RW
0
RW
0
Track ID: JATR-1076-21 Rev. 1.21
RTL8201CP
Datasheet
6.2. Register 1 Basic Mode Status Register
Address
1:15
1:14
1:13
1:12
1:11
1:10~7
1:6
1:5
1:4
1:3
1:2
1:1
1:0
Table 10. Register 1 Basic Mode Status Register
Name
Description
100Base-T4
1: Enable 100Base-T4 support
0: Suppress 100Base-T4 support
100Base_TX_ FD 1: Enable 100Base-TX full duplex support
0: Suppress 100Base-TX full duplex support
100BASE_TX_HD 1: Enable 100Base-TX half duplex support
0: Suppress 100Base-TX half duplex support
10Base_T_FD
1: Enable 10Base-T full duplex support
0: Suppress 10Base-T full duplex support
10_Base_T_HD
1: Enable 10Base-T half duplex support
0: Suppress 10Base-T half duplex support
Reserved
MF Preamble
The RTL8201CP will accept management frames with preamble
Suppression
suppressed.
A minimum of 32 preamble bits are required for the first SMI
read/write transaction after reset. One idle bit is required
between any two management transactions as per IEEE 802.3u
specifications.
Auto Negotiation 1: Auto-negotiation process completed
Complete
0: Auto-negotiation process not completed
Remote Fault
1: Remote fault condition detected (cleared on read)
0: No remote fault condition detected
When in 100Base-FX mode, this bit means an in-band signal
Far-End-Fault has been detected. See 7.12 Far End Fault
Indication, page 22.
Auto Negotiation 1: Link has not experienced fail state
0: Link experienced fail state
Link Status
1: Valid link established
0: No valid link established
Jabber Detect
1: Jabber condition detected
0: No jabber condition detected
Extended Capability 1: Extended register capability
0: Basic register capability only
Mode
RO
Default
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
0
RO
0
RO
1
RO
0
RO
0
RO
1
Mode
RO
Default
0000
Mode
RO
Default
8201
6.3. Register 2 PHY Identifier Register 1
Address
2:15~0
Name
PHYID1
Table 11. Register 2 PHY Identifier Register 1
Description
PHY identifier ID for software recognition of the RTL8201CP.
6.4. Register 3 PHY Identifier Register 2
Address
3:15~0
Name
PHYID2
Table 12. Register 3 PHY Identifier Register 2
Description
PHY identifier ID for software recognition of the RTL8201CP.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
9
Track ID: JATR-1076-21 Rev. 1.21
RTL8201CP
Datasheet
6.5. Register 4 Auto-Negotiation Advertisement Register (ANAR)
This register contains the advertised abilities of this device as they will be transmitted to its link partner
during auto-negotiation.
Address
4:15
4:14
4:13
4:12
4:11
4:10
4:9
4:8
4:7
4:6
4:5
4:4~0
Table 13. Register 4 Auto-Negotiation Advertisement Register (ANAR)
Name
Description
Mode
NP
Next Page bit.
RO
0: Transmitting the primary capability data page
1: Transmitting the protocol specific data page
ACK
1: Acknowledge reception of link partner capability data word
RO
0: Do not acknowledge reception
RF
1: Advertise remote fault detection capability
RW
0: Do not advertise remote fault detection capability
Reserved
TXFC
1: TX flow control is supported by local node
RW
0: TX flow control not supported by local node
RXFC
1: RX flow control is supported by local node
RW
0: RX flow control not supported by local node
T4
1: 100Base-T4 is supported by local node
RO
0: 100Base-T4 not supported by local node
TXFD
1: 100Base-TX full duplex is supported by local node
RW
0: 100Base-TX full duplex not supported by local node
TX
1: 100Base-TX is supported by local node
RW
0: 100Base-TX not supported by local node
10FD
1: 10Base-T full duplex supported by local node
RW
0: 10Base-T full duplex not supported by local node
10
1: 10Base-T is supported by local node
RW
0: 10Base-T not supported by local node
Selector
Binary encoded selector supported by this node. Currently only
RW
CSMA/CD 00001 is specified. No other protocols are supported.
Default
0
0
0
0
0
0
1
1
1
1
00001
6.6. Register 5 Auto-Negotiation Link Partner Ability Register
(ANLPAR)
This register contains the advertised abilities of the Link Partner as received during auto-negotiation. The
content changes after a successful auto-negotiation if Next-pages are supported.
Address
5:15
5:14
5:13
5:12
5:11
Table 14. Register 5 Auto-Negotiation Link Partner Ability Register (ANLPAR)
Name
Description
Mode
NP
Next Page bit.
RO
0: Transmitting the primary capability data page
1: Transmitting the protocol specific data page
ACK
1: Link partner acknowledges reception of local node’s capability
RO
data word
0: No acknowledgement
RF
1: Link partner is indicating a remote fault
RO
0: Link partner does not indicate a remote fault
Reserved
TXFC
1: TX flow control is supported by Link partner
RO
0: TX flow control not supported by Link partner
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
10
Default
0
0
0
0
Track ID: JATR-1076-21 Rev. 1.21
RTL8201CP
Datasheet
Address
5:10
Name
RXFC
5:9
T4
5:8
TXFD
5:7
100BASE-TX
5:6
10FD
5:5
10Base-T
5:4~0
Selector
Description
1: RX flow control is supported by Link partner
0: RX flow control not supported by Link partner
1: 100Base-T4 is supported by link partner
0: 100Base-T4 not supported by link partner
1: 100Base-TX full duplex is supported by link partner
0: 100Base-TX full duplex not supported by link partner
1: 100Base-TX is supported by link partner
0: 100Base-TX not supported by link partner
This bit will also be set if the link in 100Base is established by
parallel detection.
1: 10Base-T full duplex is supported by link partner
0: 10Base-T full duplex not supported by link partner
1: 10Base-T is supported by link partner
0: 10Base-T not supported by link partner
This bit will also be set if the link in 10Base-T is established by
parallel detection.
Link Partner’s binary encoded node selector Currently only
CSMA/CD 00001 is specified
Mode
RO
Default
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
00000
6.7. Register 6 Auto-Negotiation Expansion Register (ANER)
This register contains additional status for NWay auto-negotiation.
Address
6:15~5
6:4
6:3
6:2
6:1
6:0
Table 15. Register 6 Auto-Negotiation Expansion Register (ANER)
Name
Description
Mode
Reserved
This bit is permanently set to 0.
MLF
Indicates whether a multiple link fault has occurred.
RO
1: Fault occurred
0: No fault occurred
LP_NP_ABLE Indicates whether the link partner supports Next Page negotiation.
RO
1: Supported
0: Not supported
NP_ABLE
This bit indicates whether the local node is able to send additional
RO
Next Pages. Internal use only.
PAGE_RX
This bit is set when a new Link Code Word Page has been
RO
received. It is automatically cleared when the auto-negotiation link
partner’s ability register (register 5) is read by management.
LP_NW_ABLE 1: Link partner supports NWay auto-negotiation.
RO
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
11
Default
0
0
0
0
0
Track ID: JATR-1076-21 Rev. 1.21
RTL8201CP
Datasheet
6.8. Register 16 NWay Setup Register (NSR)
Address
16:15~12
16:11
16:10
16:9
16:8~3
16:2
16:1
16:0
Name
Reserved
ENNWLE
Testfun
NWLPBK
Reserved
FLAGABD
FLAGPDF
FLAGLSC
Table 16. Register 16 NWay Setup Register (NSR)
Description
Mode
Default
1: LED4 Pin indicates linkpulse
1: Auto-negotiation speeds up internal timer
1: Set NWay to loopback mode
RW
RW
RW
0
0
0
1: Auto-negotiation experienced ability detect state
1: Auto-negotiation experienced parallel detection fault state
1: Auto-negotiation experienced link status check state
RO
RO
RO
0
0
0
6.9. Register 17 Loopback, Bypass, Receiver Error Mask
Register (LBREMR)
Address
17:15
17:14
17:13
17:12
17:11
17:10
17:9
17:8
17:7
17:6
17:5
17:4
17:3
17:2
17:1
17:0
Table 17. Register 17 Loopback, Bypass, Receiver Error Mask Register (LBREMR)
Name
Description
Mode
RPTR
Set to 1 to put the RTL8201CP into repeater mode.
RW
BP_4B5B
Assertion of this bit allows bypassing of the 4B/5B & 5B/4B
RW
encoder.
BP_SCR
Assertion of this bit allows bypassing of the
RW
scrambler/descrambler.
LDPS
Set to 1 to enable Link Down Power Saving mode.
RW
AnalogOFF
Set to 1 to power down analog function of transmitter and receiver.
RW
Reserve
Reserved.
LB
Set to 1 to enable DSP Loopback.
RW
F_Link_10
Used to logic force good link in 10Mbps for diagnostic purposes.
RW
F_Link_100
Used to logic force good link in 100Mbps for diagnostic purposes.
RW
JBEN
Set to 1 to enable Jabber Function in 10Base-T.
RW
CODE_err
Assertion of this bit causes a code error detection to be reported.
RW
PME_err
Assertion of this bit causes a pre-mature end error detection to be
RW
reported.
LINK_err
Assertion of this bit causes a link error detection to be reported.
RW
PKT_err
Assertion of this bit causes a ‘detection of packet errors due to
RW
722 ms time-out’ to be reported.
FXMODE
This bit indicates whether Fiber Mode is Enabled.
RO
RMIIMODE This bit indicates whether RMII mode is Enabled.
RO
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
12
Default
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
Track ID: JATR-1076-21 Rev. 1.21
RTL8201CP
Datasheet
6.10. Register 18 RX_ER Counter (REC)
Address
18:15~0
Name
RXERCNT
Table 18. Register 18 RX_ER Counter (REC)
Description
This 16-bit counter increments by 1 for each valid packet received.
Mode
RW
Default
H’[0000]
Mode
Default
RW
0000
Mode
RW
RO
Default
6.11. Register 19 SNR Display Register
Address
19:15~4
Name
Reserved
19:3~0
SNR
Table 19. Register 19 SNR Display Register
Description
Realtek Test Mode Internal use. Do not change this field without
Realtek’s approval.
These 4-bits show the Signal to Noise Ratio value.
6.12. Register 25 Test Register
Address
25:15~12
25:11~7
Name
Test
PHYAD[4:0]
25:6~2
25:1
Test
LINK10
25:0
LINK100
Table 20. Register 25 Test Register
Description
Reserved for internal testing.
Reflects the PHY address defined by external PHY address
configuration pins.
Reserved for internal testing.
1: 10Base-T link established
0: No 10Base-T link established
1: 100Base-FX or 100Base-TX link established
0: No 100Base link established
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
13
00001
RO
RO
0
RO
0
Track ID: JATR-1076-21 Rev. 1.21
RTL8201CP
Datasheet
7.
Functional Description
The RTL8201CP PHYceiver is a physical layer device that integrates 10Base-T and
100Base-TX/100Base-FX functions, and some extra power management features into a 48-pin single chip
that is used in 10/100 Fast Ethernet applications. This device supports the following functions:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MII interface with MDC/MDIO SMI management interface to communicate with MAC
IEEE 802.3u clause 28 Auto-Negotiation ability
Flow control ability support to cooperate with MAC
Speed, duplex, auto-negotiation ability configurable by hard wire or MDC/MDIO
Flexible LED configuration
7-wire SNI (Serial Network Interface) support (only in 10Mbps mode)
Power Down mode support
4B/5B transform
Scrambling/De-scrambling
NRZ to NRZI, NRZI to MLT-3
Manchester Encode and Decode for 10Base-T operation
Clock and Data recovery
Adaptive Equalization
Far End Fault Indication (FEFI) in fiber mode
7.1. MII and Management Interface
7.1.1.
Data Transition
To set the RTL8201CP for MII mode operation, pull the MII/SNIB pin high and set the ANE, SPEED,
and DUPLEX pins.
The MII (Media Independent Interface) is an 18-signal interface (as described in IEEE 802.3u) supplying
a standard interface between the PHY and MAC layer. This interface operates at two frequencies –
25MHz and 2.5MHz to support 100Mbps/10Mbps bandwidth for both transmit and receive functions.
Transmission
The MAC asserts the TXEN signal. It then changes byte data into 4-bit nibbles and passes them to the
PHY via TXD[0..3]. The PHY will sample TXD[0..3] synchronously with TXC — the transmit clock
signal supplied by PHY – during the interval TXEN is asserted.
Reception
The PHY asserts the RXEN signal. It passes the received nibble data RXD[0..3] clocked by RXC. CRS
and COL signals are used for collision detection and handling.
In 100Base-TX mode, when the decoded signal in 5B is not IDLE, the CRS signal will assert. When 5B is
recognized as IDLE it will be de-asserted. In 10Base-T mode, CRS will assert when the 10M preamble
has been confirmed and will be de-asserted when the IDLE pattern has been confirmed.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
14
Track ID: JATR-1076-21 Rev. 1.21
RTL8201CP
Datasheet
The RXDV signal will be asserted when decoded 5B are /J/K/ and will be de-asserted if the 5B are /T/R/
or IDLE in 100Mbps mode. In 10Mbps mode, the RXDV signal is the same as the CRS signal.
The RXER (Receive Error) signal will be asserted if any 5B decode errors occur such as invalid J/K,
invalid T/R, or invalid symbol. This pin will go high for one or more clock periods to indicate to the
reconciliation sublayer that an error was detected somewhere in the frame.
Note: The RTL8201CP does not use a TXER signal. This does not affect the transmit function.
7.1.2.
Serial Management
The MAC layer device can use the MDC/MDIO management interface to control a maximum of 31
RTL8201CP devices, configured with different PHY addresses (00001b to 11111b). During a hardware
reset, the logic levels of pins 9, 10, 12, 13, 15 are latched into the RTL8201CP to be set as the PHY
address for management communication via the serial interface. Setting the PHY address to 00000b will
put the RTL8201CP into power down mode. The read and write frame structure for the management
interface is illustrated in Figure 3 and Figure 4.
MDC
MDIO
32 1s
0
Preamble
1
1
ST
0
A4
A3
OP
A2
A1 A0
R4
R3
PHYAD[4:0]
R2
R1
R0
Z
REGAD[4:0]
0
D15 D14 D13 D12 D11 D10
D9
TA
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA
Idle
MDIO is sourced by PHY. Clock data from PHY on rising edge of MDC
MDIO is sourced by MAC. Clock data into PHY on rising edge of MDC
Figure 3. Read Cycle
MDC
MDIO
32 1s
Preamble
0
1
ST
0
1
OP
A4
A3
A2
A1
PHYAD[4:0]
A0
R4
R3
R2
R1
R0
1
0
D15 D14 D13 D12 D11 D10
D9
TA
REGAD[4:0]
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA
Idle
MDIO is sourced by MAC. Clock data into PHY on rising edge of MDC
Figure 4. Write Cycle
Name
Preamble
ST
OP
PHYAD
REGAD
TA
DATA
IDLE
Table 21. Serial Management
Description
32 contiguous logical ‘1’s sent by the MAC on MDIO along with 32 corresponding cycles on MDC. This
provides synchronization for the PHY.
Start of Frame. Indicated by a 01 pattern.
Operation Code.
Read: 10
Write: 01
PHY Address. Up to 31 PHYs can be connected to one MAC. This 5-bit field selects which PHY the
frame is directed to.
Register Address. This is a 5-bit field that sets which of the 32 registers of the PHY this operation refers to.
Turnaround. This is a 2-bit time-spacing between the register address and the data field of a frame to avoid
contention during a read transaction. For a read transaction, both the STA and the PHY shall remain in a
high-impedance state for the first bit time of the turnaround. The PHY shall drive a zero bit during the
second bit time of the turnaround of a read transaction.
Data. These are the 16 bits of data.
Idle Condition. Not truly part of the management frame. This is a high impedance state. Electrically, the
PHY’s pull-up resistor will pull the MDIO line to a logical ‘1’.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
15
Track ID: JATR-1076-21 Rev. 1.21
RTL8201CP
Datasheet
7.2. Auto-Negotiation and Parallel Detection
The RTL8201CP supports IEEE 802.3u clause 28 Auto-negotiation for operation with other transceivers
supporting auto-negotiation. The RTL8201CP can auto detect the link partner’s abilities and determine
the highest speed/duplex configuration possible between the two devices. If the link partner does not
support auto-negotiation, then the RTL8201CP will enable half duplex mode and enter parallel detection
mode. The RTL8201CP will default to transmit FLP (Fast Link Pulse) and wait for the link partner to
respond. If the RTL8201CP receives FLP, then the auto-negotiation process will go on. If it receives NLP
(Normal Link Pulse), then the RTL8201CP will change to 10Mbps and half duplex mode. If it receives a
100Mbps IDLE pattern, it will change to 100Mbps and half duplex mode.
To enable auto-negotiation mode operation on the RTL8201CP, just pull the ANE (Auto-Negotiation
Enable) pin high. The SPEED and DUPLEX pins will set the ability content of the auto-negotiation
register. Auto-negotiation mode can be externally disabled by pulling the ANE pin low. In this case, the
SPEED pin and DUPLEX pin will change the media configuration of the RTL8201CP.
Below is a list of all configurations of the ANE/SPEED/DUPLEX pins and their operation in Fiber or
UTP mode.
7.2.1.
Setting the Medium Type and Interface Mode to MAC
FX (Pin 24)
L
L
H
7.2.2.
Table 22. Setting the Medium Type and Interface Mode to MAC
MII/SNIB (Pin 44) Operation Mode
H
UTP mode and MII interface.
L
UTP mode and SNI interface.
X
Fiber mode and MII interface.
UTP Mode and MII Interface
ANE
(Pin 37)
SPEED
(Pin 39)
H
L
H
L
H
H
H
H
L
L
L
L
L
H
L
H
Table 23. UTP Mode and MII Interface
DUPLEX
Operation
(Pin 38)
Auto-negotiation enabled. The ability field does not support 100Mbps or full
L
duplex mode operation.
Auto-negotiation enabled. The ability field does not support 100Mbps
H
operation.
Auto-negotiation enabled. The ability field does not support full duplex
L
mode operation.
Default setup, auto-negotiation enabled. The RTL8201CP supports 10Base-T
H
/100Base-TX, half/full duplex mode operation.
Auto-negotiation disabled. Forces the RTL8201CP into 10Base-T and half
L
duplex mode.
Auto-negotiation disabled. Forces the RTL8201CP into 10Base-T and full
H
duplex mode.
Auto-negotiation disabled. Forces the RTL8201CP into 100Base-TX and half
L
duplex mode.
Auto-negotiation disabled. Forces the RTL8201CP into 100Base-TX and full
H
duplex mode.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
16
Track ID: JATR-1076-21 Rev. 1.21
RTL8201CP
Datasheet
7.2.3.
UTP Mode and SNI Interface
SNI interface to MAC (only operates in 10Base-T when the SNI interface is enabled)
ANE
(Pin 37)
X
SPEED
(Pin 39)
X
X
X
7.2.4.
Table 24. UTP Mode and SNI Interface
DUPLEX
Operation
(Pin 38)
L
The duplex pin is pulled low to support the 10Base-T half duplex function.
10Base-T half duplex is the specified default mode in the SNI interface.
H
The RTL8201CP also supports full duplex in SNI mode. The duplex pin is
pulled high to support 10Base-T full duplex function.
Fiber Mode and MII Interface
The RTL8201CP only supports 100Base-FX when Fiber mode is enabled. ANE (Auto-Negotiation
Enable) and SPEED configuration is ignored when Fiber mode is enabled.
ANE
(Pin 37)
X
X
SPEED
(Pin 39)
X
X
Table 25. Fiber Mode and MII Interface
DUPLEX
Operation
(Pin 38)
H
The duplex pin is pulled high to support 100Base-FX full duplex function.
L
The duplex pin is pulled low to support 100Base-FX half duplex function.
7.3. Flow Control Support
The RTL8201CP supports flow control indications. The MAC can program the MII register to indicate to
the PHY that flow control is supported. When the MAC supports the Flow Control mechanism, setting
bit 10 of the ANAR register using the MDC/MDIO SMI interface, then the RTL8201CP will add the
ability to its NWay ability. If the Link partner also supports Flow Control, then the RTL8201CP can
recognize the Link partner’s NWay ability by examining bit 10 of ANLPAR (register 5).
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
17
Track ID: JATR-1076-21 Rev. 1.21
RTL8201CP
Datasheet
7.4. Hardware Configuration and Auto-Negotiation
This section describes methods to configure the RTL8201CP and set the auto-negotiation mode. Table 26
shows the various pins and their settings.
Pin Name
Isolate
RPTR
LDPS
MII/SNIB
ANE
SPEED
DUPLEX
Table 26. Auto-Negotiation Mode Pin Settings
Description
Set high to isolate the RTL8201CP from the MAC. This will also isolate the MDC/MDIO
management interface. In this mode, power consumption is minimum (see 7.7 Power Down, Link
Down, Power Saving, and Isolation Modes, page 20).
Pull high to set the RTL8201CP into repeater mode. This pin is pulled low by default (see
7.9 Repeater Mode Operation, page 22.
Pull high to set the RTL8201CP into LDPS mode. This pin is pulled low by default (see 7.7 Power
Down, Link Down, Power Saving, and Isolation Modes, page 20).
Pull high to set RTL8201CP into MII mode operation, which is the default mode for the RTL8201.
This pin pulled low will set the RTL8201CP into SNI mode operation. When set to SNI mode, the
RTL8201CP will operate at 10Mbps (see 7.6 Serial Network Interface, page 20).
Auto-Negotiation Enable. Pull high to enable auto-negotiation (default). Pull low to disable autonegotiation and activate the parallel detection mechanism (see 7.2 Auto-Negotiation and Parallel
Detection, page 16).
When ANE is pulled high, the ability to adjust speed is setup. When ANE is pulled low, pull this pin
low to force 10Mbps operation and high to force 100Mbps operation (see 7.2 Auto-Negotiation and
Parallel Detection, page 16).
When ANE is pulled high, the ability to adjust the DUPLEX pin will be setup. When ANE is pulled
low, pull this pin low to force half duplex and high to force full duplex operation (see 7.2 AutoNegotiation and Parallel Detection, page 16).
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
18
Track ID: JATR-1076-21 Rev. 1.21
RTL8201CP
Datasheet
7.5. LED and PHY Address Configuration
In order to reduce the pin count on the RTL8201CP, the LED pins are duplexed with the PHY address
pins. Because the PHYAD strap options share the LED output pins, the external combinations required
for strapping and LED usage must be considered in order to avoid contention. Specifically, when the LED
outputs are used to drive LEDs directly, the active state of each output driver is dependent on the logic
level sampled by the corresponding PHYAD input upon power-up/reset. For example, as Figure 5 (leftside) shows, if a given PHYAD input is resistively pulled high then the corresponding output will be
configured as an active low driver. On the right side, we can see that if a given PHYAD input is
resistively pulled low then the corresponding output will be configured as an active high driver. The PHY
address configuration pins should not be connected to GND or VCC directly, but must be pulled high or
low through a resistor (ex 5.1KΩ). If no LED indications are needed, the components of the LED path
(LED+510Ω) can be removed.
VCC
PAD[0:4]/
LED[0:4]
LED
LED
5.1K ohm
510 ohm
510 ohm
5.1K ohm
PAD[0:4]/
LED[0:4]
PHY Address[:] = Logical 1
LED Indication = Active low
PHY Address[:] = Logical 0
LED Indication = Active High
Figure 5. LED and PHY Address Configuration
LED
LED0
LED1
LED2
LED3
LED4
Table 27. LED Definitions
LED Definitions
Link
Full Duplex
[CP LED Mode]10-Activity
[CP LED Mode]Fiber/100-Activity
Collision
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
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RTL8201CP
Datasheet
7.6. Serial Network Interface
The RTL8201CP also supports the traditional 7-wire serial interface to operate with legacy MACs or
embedded systems. To setup for this mode of operation, pull the MII/SNIB pin low. By doing so, the
RTL8201CP will ignore the setup of the ANE and SPEED pins. In this mode, the RTL8201CP will set
the default operation to 10Mbps and half-duplex mode.
Note: The RTL8201CP also supports full-duplex mode operation if the DUPLEX pin has been pulled high.
This interface consists of a 10Mbps transmit and receive clock generated by PHY, 10Mbps transmit and
receive serial data, transmit enable, collision detect, and carry sense signals.
7.7. Power Down, Link Down, Power Saving, and Isolation
Modes
Four types of Power Saving mode operation are supported. This section describes how to implement each
mode. The first three modes are configured through software, and the fourth through hardware.
Mode
Analog Off
LDPS
PWD
Isolation
Table 28. Power Saving Mode Pin Settings
Description
Setting bit 11 of register 17 to 1 will put the RTL8201CP into analog off state. In analog off state, the
RTL8201CP will power down all analog functions such as transmit, receive, PLL, etc. However, the
internal 25MHz crystal oscillator will not be powered down. Digital functions in this mode are still
available which allows reacquisition of analog functions
Setting bit 12 of register 17 to 1, or pulling the LDPS pin high will put the RTL8201CP into LDPS
(Link Down Power Saving) mode. In LDPS mode, the RTL8201CP will detect the link status to
decide whether or not to turn off the transmit function. If the link is off, FLP or 100Mbps
IDLE/10Mbps NLP will not be transmitted. However, some signals similar to NLP will be
transmitted. Once the receiver detects leveled signals, it will stop the signal and transmit FLP or
100Mbps IDLE/10Mbps NLP again. This can cut power used by 60%~80% when the link is down.
Setting bit 11 of register 0 to 1 puts the RTL8201CP into power down mode. This is the maximum
power saving mode while the RTL8201CP is still alive. In PWD mode, the RTL8201CP will turn off
all analog/digital functions except the MDC/MDIO management interface. Therefore, if the
RTL8201CP is put into PWD mode and the MAC wants to recall the PHY, it must create the
MDC/MDIO timing by itself (this is done by software).
This mode is different from the three previous software configured power saving modes. This mode
is configured by hardware pin 43. Setting pin 43 high will isolate the RTL8201CP from the Media
Access Controller (MAC) and the MDC/MDIO management interface. In this mode, power
consumption is minimal.
7.8. Media Interface
7.8.1.
100Base-TX
100Base-TX Transmit Function
Transmit data in 4-bit nibbles (TXD[3:0]) clocked at 25MHz (TXC) is transformed into 5B symbol code
(4B/5B encoding). Scrambling, serializing, and conversion to 125MHz, and NRZ to NRZI then takes
place. After this process, the NRZI signal is passed to the MLT-3 encoder, then to the transmit line driver.
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RTL8201CP
Datasheet
The transmitter will first assert TXEN. Before transmitting the data pattern, it will send a /J/K/ symbol
(Start-of-frame delimiter), the data symbol, and finally a /T/R/ symbol known as the End-Of-Frame
delimiter. The 4B/5B and the scramble process can be bypassed via a PHY register setting (see Table 1,
page 4, Pin number 24). For better EMI performance, the seed of the scrambler is based on the PHY
address. In a hub/switch environment, each RTL8201CP will have different scrambler seeds and so
spread the output of the MLT-3 signals.
100Base-TX Receive Function
The received signal is compensated by the adaptive equalizer to make up for signal loss due to cable
attenuation and Inter Symbol Interference (ISI). Baseline Wander Correction monitors the process and
dynamically applies corrections to the process of signal equalization. The PLL then recovers the timing
information from the signals and from the receive clock. With this, the received signal is sampled to form
NRZI data. The next steps are the NRZI to NRZ process, unscrambling of the data, serial to parallel and
5B to 4B conversion, and passing of the 4B nibble to the MII interface.
7.8.2.
100Base-FX Fiber Mode Operation
The RTL8201CP can be configured as 100Base-FX via hardware configuration. The hardware
100Base-FX setting takes priority over NWay settings. A scrambler is not required in 100Base-FX.
100Base-FX Transmit Function
Di-bits of TXD are processed as 100Base-TX except without a scrambler before the NRZI stage. Instead
of converting to MLT-3 signals, as in 100Base-TX, the serial data stream is driven out as NRZI PECL
signals, which enter the fiber transceiver in differential-pairs form.
100Base-FX Receive Function
The signal is received through PECL receiver inputs from the fiber transceiver and directly passed to the
clock recovery circuit for data/clock recovery. The scrambler/de-scrambler is bypassed in 100Base-FX.
7.8.3.
10Base-T TX/RX
10Base-T Transmit Function
Transmit data in 4-bit nibbles (TXD[3:0]) clocked at 25MHz (TXC) is first fed to a parallel-to-serial
converter, then the 10Mbps NRZ signal is sent to a Manchester encoder. The Manchester encoder
converts the 10Mbps NRZ data into a Manchester Encoded data stream for the TP transmitter and adds a
Start of Idle pulse (SOI) at the end of the packet as specified in IEEE 802.3. Finally, the encoded data
stream is shaped by a bandlimited filter embedded in the RTL8201CP and then transmitted.
10Base-T Receive Function
In 10Base-T receive mode, the Manchester decoder in the RTL8201CP converts the Manchester encoded
data stream into NRZ data by decoding the data and stripping off the SOI pulse. Then the serial NRZ data
stream is converted to a parallel 4-bit nibble signal (RXD[0:3]).
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RTL8201CP
Datasheet
7.9. Repeater Mode Operation
Setting bit 15 of register 17 to 1, or pulling the RPTR pin high, sets the RTL8201CP into repeater mode.
In repeater mode, the RTL8201CP will assert CRS high only when receiving a packet. In NIC mode, the
RTL8201CP will assert CRS high both when transmitting and receiving packets. If using the RTL8201CP
in a NIC or switch application, set to the default mode. NIC/Switch mode is the default setting and has
the RPTR pin pulled low, or bit 15 of register 17 is set to 0.
7.10. Reset, and Transmit Bias
The RTL8201CP can be reset by pulling the RESETB pin low for about 10ms, then pulling the pin high.
It can also be reset by setting bit 15 of register 0 to 1, and then setting it back to 0. Reset will clear the
registers and re-initialize them. The media interface will disconnect and restart the autonegotiation/parallel detection process.
The RTSET pin must be pulled low by a 2KΩ resister with 1% accuracy to establish an accurate transmit
bias. This will affect the signal quality of the transmit waveform. Keep its circuitry away from other clock
traces and transmit/receive paths to avoid signal interference.
7.11. 3.3V Power Supply and Voltage Conversion Circuit
The RTL8201CP is fabricated in a 0.18µm process. The core circuit needs to be powered by 1.8V,
however, the digital IO and DAC circuits need a 3.3V power supply. A regulator is embedded in the
RTL8201CP to convert 3.3V to 1.8V. As with many commercial voltage conversion devices, the 1.8V
output pin (PWFBOUT) of this circuit requires the use of an output capacitor (22uF tantalum capacitor)
as part of the device frequency compensation, and another small capacitor (0.1uF) for high frequency
noise de-coupling.
PWFBIN is fed with the 1.8V power from PWFBOUT through a ferrite bead as shown in the reference
design schematic document (available for download from www.realtek.com.tw).
Note: Do not supply 1.8V produced by any power device other than PWFBOUT and PWFBIN.
The analog and digital ground planes should be as large and intact as possible. If the ground plane is large
enough, the analog and digital grounds can be separated, which is the ideal configuration. However, if the
total ground plane is not sufficiently large, partition of the ground plane is not a good idea. In this case,
all the ground pins can be connected together to a larger single and intact ground plane.
7.12. Far End Fault Indication
The MII Reg.1.4 (Remote Fault) is the Far End Fault Indication (FEFI) bit when 100FX mode is enabled
and indicates when a FEFI has been detected. FEFI is an alternative in-band signaling method which is
composed of 84 consecutive ‘1’s followed by one ‘0’. When the RTL8201CP detects this pattern three
times, Reg.1.4 is set, which means the transmit path (the Remote side’s receive path) has a problem. On
the other hand, if an incoming signal fails to cause a ‘Link OK’, the RTL8201CP will start sending this
pattern, which in turn causes the remote side to detect a Far End Fault. This means that the receive path
has a problem from the point of view of the RTL8201CP. The FEFI mechanism is used only in 100BaseFX mode.
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RTL8201CP
Datasheet
8.
Characteristics
8.1. DC Characteristics
8.1.1.
Absolute Maximum Ratings
Item
Supply Voltage
Storage Temperature
8.1.2.
Maximum
3.6V
125°C
Operating Conditions
Table 30. Operating Conditions
Condition
Minimum
3.3V Supply voltage
3.0V
Operating Temperature
0°C
Item
Vcc 3.3V
TA
8.1.3.
Table 29. Absolute Maximum Ratings
Minimum
Typical
3.0V
3.3V
-55°C
Typical
3.3V
Maximum
3.6V
70°C
Power Dissipation
Test Condition: VCC=3.3V
Table 31. Power Dissipation
Symbol
PLDPS
PAnaOff
PPWD
PIsolate
P100F
P10F
P10TX
P10RX
P10IDLE
8.1.4.
Condition
Link down power saving mode
Analog off mode
Power down mode
Isolate mode
100Base full duplex
10Base-T full duplex
10Base-T transmit
10Base-T receive
10Base-T idle
Total Current Consumption
19mA
19mA
14mA
14mA
116mA
120mA
120mA
19mA
18mA
Input Voltage: Vcc
Table 32. Input Voltage: Vcc
Symbol
TTL VIH
TTL VIL
TTL VOH
TTL VOL
TTL IOZ
IIN
PECL VIH
PECL VIL
PECL VOH
PECL VOL
Condition
Input High Vol.
Input Low Vol.
Output High Vol.
Output Low Vol.
Tri-state Leakage
Input Current
PECL Input High Vol.
PECL Input Low Vol.
PECL Output High Vol.
PECL Output Low Vol.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
IOH=-8mA
IOL=8mA
Vout=Vcc or GND
Vin=Vcc or GND
Minimum
0.5*Vcc
-0.5V
0.9*Vcc
-10uA
-1.0uA
Vdd -1.16V
Vdd -1.81V
Vdd -1.02V
Maximum
Vcc +0.5V
0.3*Vcc
Vcc
0.1*Vcc
10uA
1.0uA
Vdd -0.88V
Vdd -1.47V
Vdd -1.62V
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Datasheet
8.2. AC Characteristics
8.2.1.
MII Transmission Cycle Timing
Symbol
t1
Table 33. MII Transmission Cycle Timing
Description
Minimum
Typical
TXCLK high pulse width
100Mbps
14
20
t2
TXCLK low pulse width
t3
TXCLK period
t4
TXEN, TXD[0:3] setup to
TXCLK rising edge
t5
TXEN, TXD[0:3] hold after
TXCLK rising edge
t6
TXEN sampled to CRS high
t7
TXEN sampled to CRS low
Maximum
26
Unit
ns
10Mbps
140
200
260
ns
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
14
140
20
200
40
400
24
26
260
ns
ns
ns
ns
ns
10Mbps
100Mbps
5
10
25
ns
ns
10Mbps
100Mbps
10Mbps
100Mbps
5
40
400
160
ns
ns
ns
ns
2000
ns
70
140
ns
100
400
170
ns
ns
ns
10
10Mbps
t8
Transmit latency
100Mbps
t9
Sampled TXEN inactive to end
of frame
10Mbps
100Mbps
10Mbps
60
Figure 6 shows an example of a packet transfer from MAC to PHY on the MII interface.
t3
VI H(min)
VI L(max)
TXCLK
t4
t5
t1
t2
VIH(min)
VI L(max)
TXD[0:3]
TXEN
Figure 6. MII Transmission Cycle Timing-1
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RTL8201CP
Datasheet
TXCLK
TXEN
TXD[0:3]
t6
t7
CRS
t8
TPTX+-
t9
Figure 7. MII Transmission Cycle Timing-2
8.2.2.
Symbol
t1
t2
MII Reception Cycle Timing
Table 34. MII Reception Cycle Timing
Minimum
Typical
100Mbps
14
20
10Mbps
140
200
RXCLK low pulse width
100Mbps
14
20
Description
RXCLK high pulse width
t3
RXCLK period
t4
RXER, RXDV, RXD[0:3] setup to
RXCLK rising edge
t5
RXER, RXDV, RXD[0:3] hold
after RXCLK rising edge
t6
Receive frame to CRS high
t7
End of receive frame to CRS low
t8
Receive frame to sampled edge of
RXDV
t9
End of receive frame to sampled
edge of RXDV
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
10Mbps
100Mbps
140
10Mbps
100Mbps
10Mbps
100Mbps
200
40
Maximum
26
260
26
Unit
ns
ns
ns
260
ns
ns
400
ns
ns
ns
ns
10
6
10
10Mbps
100Mbps
6
130
ns
ns
10Mbps
100Mbps
10Mbps
100Mbps
600
240
600
150
ns
ns
ns
ns
10Mbps
100Mbps
3200
120
ns
ns
10Mbps
800
ns
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Track ID: JATR-1076-21 Rev. 1.21
RTL8201CP
Datasheet
Figure 8 shows an example of a packet transfer from PHY to MAC on the MII interface.
t3
V
RXCLK
V
t4
t5
t1
IH(min)
I L(max)
t2
RXD[0:3]
RXDV
RXER
V
V
I H(min)
I L(max)
Figure 8. MII Reception Cycle Timing-1
RXCLK
t9
t8
RXDV
RXD[0:3]
t6
t7
CRS
TPRX+Figure 9. MII Reception Cycle Timing-2
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RTL8201CP
Datasheet
8.2.3.
SNI Transmission Cycle Timing
Symbol
t1
t2
t3
t4
t5
t8
Table 35. SNI Transmission Cycle Timing
Description
Minimum
Maximum
TXCLK high pulse width
36
TXCLK low pulse width
36
TXCLK period
80
120
TXEN, TXD0 setup to TXCLK rising edge
20
TXEN, TXD0 hold after TXCLK rising edge
10
Transmit latency
50
Unit
ns
ns
ns
ns
ns
ns
Figure 10 shows an example of a packet transfer from MAC to PHY on the SNI interface.
Note: SNI mode only runs at 10Mbps.
t3
V
TXCLK
V
t5
t4
t1
IL(max)
t2
V
TXD0
TXEN
IH(min)
V
IH(min)
IL(max)
Figure 10. SNI Transmission Cycle Timing-1
TXCLK
TXEN
TXD0
TPTX+-
t8
t9
Figure 11. SNI Transmission Cycle Timing-2
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RTL8201CP
Datasheet
8.2.4.
SNI Reception Cycle Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
Table 36. SNI Reception Cycle Timing
Description
Minimum
Typical
RXCLK high pulse width
36
RXCLK low pulse width
36
RXCLK period
80
RXD0 setup to RXCLK rising edge
40
RXD0 hold after RXCLK rising edge
40
Receive frame to CRS high
End of receive frame to CRS low
Decoder acquisition time
600
Maximum
Unit
ns
ns
ns
ns
ns
ns
ns
ns
120
50
160
1800
Figure 12 shows an example of a packet transfer from PHY to MAC on the SNI interface.
Note: SNI mode only runs at 10Mbps.
t3
V
RXCLK
V
t4
t5
IH(min)
IL(max)
t2
t1
V
RXD0
V
I H(min)
IL(max)
Figure 12. SNI Reception Cycle Timing-1
RXCLK
t8
RXD0
t6
t7
CRS
TPRX+Figure 13. SNI Reception Cycle Timing-2
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RTL8201CP
Datasheet
8.2.5.
Symbol
t1
t2
t3
t4
t5
t6
MDC/MDIO Timing
Table 37. MDC/MDIO Timing
Description
Minimum
MDC high pulse width
160
MDC low pulse width
160
MDC period
400
MDIO setup to MDC rising edge
10
MDIO hold time from MDC rising edge
10
MDIO valid from MDC rising edge
0
Maximum
Unit
ns
ns
ns
ns
ns
ns
300
t3
VIH(min)
VIL(max)
MDC
t5
t4
MDIO
sourced by
STA
t1
t2
VIH(min)
VIL(max)
t6
MDIO
sourced by
RTL8201CP
VIH(min)
VIL(max)
Figure 14. MDC/MDIO Timing
Transmission Without Collision
Figure 15 shows an example of a packet transfer from MAC to PHY.
Figure 15. MDC/MDIO MAC to PHY Transmission Without Collision
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Track ID: JATR-1076-21 Rev. 1.21
RTL8201CP
Datasheet
Reception Without Error
Figure 16 shows an example of a packet transfer from PHY to MAC.
Figure 16. MDC/MDIO PHY to MAC Reception Without Error
8.3. Crystal Characteristics
Parameter
Nominal Frequency
Oscillation Mode
Frequency Tolerance at 25°C
Operating Temperature Range
Equivalent Series Resistance
Drive Level
Load Capacitance
Shunt Capacitance
Insulation Resistance
Test Impedance Meter
Aging Rate Per Year
Table 38. Crystal Characteristics
Range
25.000MHz
Base wave
±50 ppm
-10°C ~ +70°C
30 ohm Max.
0.1 mV
20 pF
7 pF Max.
Mega ohm Min./DC 100V
Saunders 250A
±0.0003%
8.4. Transformer Characteristics
Parameter
Turn Ratio
Inductance (min.)
Leakage Inductance
Capacitance (max)
DC Resistance (max)
Table 39. Transformer Characteristics
Transmit End
Receive End
1:1 CT
1:1
350 uH @ 8mA
350 uH @ 8mA
0.05-0.15 uH
0.05-0.15 uH
15 pF
15 pF
0.4 ohm
0.4 ohm
Note: To enable the Auto-Crossover Detection Function, a transformer with symmetrical TX/RX
schematics plus TX Center Tap shorted to RX Center Tap is necessary, i.e. Pulse Engineer H1245 (refer to
the suggested RTL8201CP Schematic available for download at www.realtek.com.tw).
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Datasheet
9.
Mechanical Dimensions
See the following page for drawing related notes.
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Datasheet
9.1. Mechanical Dimensions Notes
Notes:
Symb Dimension in
ol
inchs
Min
Nom
A
A1
0.000
0.004
A2
0.051
0.055
b
0.006
0.009
b1
0.006
0.008
c1
D
D1
E
E1
0.004
e
L
L1
θ
θ1
θ2
θ3
0.016
0°
0°
Max
0.067
0.008
0.059
0.011
0.010
Dimension in
millimeters
Min
Nom
0.00
0.1
1.30
1.40
15
0.22
0.15
0.20
0.006
0.354 BSC
0.276 BSC
0.354 BSC
0.276 BSC
0.020 BSC
0.09
0.024
0.031
0.039 REF
3.5°
9°
12° TYP
12° TYP
0.40
0°
0°
1.To be determined at seating plane -c2.Dimensions D1 and E1 do not include mold protrusion.
D1 and E1 are maximum plastic body size dimensions
including mold mismatch.
3.Dimension b does not include dambar protrusion.
Dambar can not be located on the lower radius of the foot.
4.Exact shape of each corner is optional.
5.These dimensions apply to the flat section of the lead
between 0.10 mm and 0.25 mm from the lead tip.
6. A1 is defined as the distance from the seating plane to
the lowest point of the package body.
7.Controlling dimension: millimeter.
8. Reference document: JEDEC MS-026, BBC
Max
1.70
0.20
1.50
0.29
0.25
0.16
9.00 BSC
7.00 BSC
9.00 BSC
7.00 BSC
0.50 BSC
TITLE: 48LD LQFP ( 7x7x1.4mm)
PACKAGE OUTLINE DRAWING, FOOTPRINT 2.0mm
LEADFRAME MATERIAL:
0.60
0.80
1.00 REF
3.5°
9°
12° TYP
12° TYP
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
DOC. NO.
VERSION
1
PAGE
OF
DWG NO.
SS048 - P1
CHECK
DATE
REALTEK SEMICONDUCTOR CORP.
APPROVE
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RTL8201CP
Datasheet
10.
Ordering Information
Part Number
RTL8201CP
RTL8201CP-LF
RTL8201CP-VD
RTL8201CP-VD-LF
Table 40. Ordering Information
Package
Rev. C. 48-pin LQFP
Rev. C. 48-pin LQFP Lead (Pb)-Free package
Rev. D. 48-pin LQFP
Rev. D. 48-pin LQFP Lead (Pb)-Free package
Status
Realtek Semiconductor Corp.
Headquarters
No. 2, Industry East Road IX, Science-based
Industrial Park, Hsinchu, 300, Taiwan, R.O.C.
Tel: 886-3-5780211 Fax: 886-3-5776047
www.realtek.com.tw
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
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Track ID: JATR-1076-21 Rev. 1.21