CS7401xx
Energy Measurement SoC
Description
The CS7401xx energy measurement system-on-chip (SoC) device reduces the cost to implement advanced digital power meters
for electrical utilities as well as enabling many other energy conservation applications. The 24-bit Delta-Sigma (∆Σ) ADCs coupled
with the on-chip metrology code enable the highest quality power
measurement available. The 32-bit processor and targeted peripherals have the power to implement metrology, advanced data management standards, and communication protocols all in the same
device. The extensive software library enables quick and easy program development.
•
Features
•
• Analog-to-Digital Converter
- Three Independent 24-bit Delta-Sigma ADCs
- Selectable Sampling Rate (1 kHz-8 kHz)
- FIFO for Buffered Data Collection
- Voltage and Current Sampled Simultaneously
- Third ADC can be used for Tamper Detection
- On-chip Temperature Sensor
• Analog Front End
- Single-ended or Differential Inputs
- Programmable Gain (1x, 3x, 6x, 12x)
- Supports 50 µΩ Shunts
- 1.8V Reference Compensated to 10 ppm/°C
• Measurement
- ANSI C12-20 / IEC 62053-22 Class 0.2% Accuracy
- Active Power Accuracy ±0.1% Over 3000:1 Range
- Fast Phase Calibration up to ±18° Range
- Wide Frequency Range: 45 Hz to 70 Hz
- Supports Total and Fundamental Measurements for
Active, Reactive, and Apparent Power
• Microcontroller Subsystem
- ARM7TDMI™ 16/32-bit RISC CPU
- Dynamic Core Frequency from 4 MHz to 32 MHz
•
•
- 32kB, 64kB, or 128kB On-chip Flash Memory
- Flash Locking Mechanism to Protect User's Program
- 8 kB On-chip RAM, 32kB On-chip ROM
- Single 32 kHz Crystal with FLL to Internal Oscillator
- Internal Oscillator: Robust Operation with EFT Events
- On-chip Crystal Capacitors for Frequency Stability
- JTAG Interface
On-chip Peripherals
- LCD Driver with up to 120 Segments (30 x 4)
- RTC with Auto Calibration and 1Hz Output
- Two UART Communications Ports
- Configurable Sync Serial Port with SPI™ Mode
- Programmable GPIOs, Timers, and Watchdog Timer
- Dedicated Energy Pulse Output
ROM Profile
- Factory-ready Communications using UART0
- Automated/Fast Calibration of Gain, Offset, and Phase
- Power Measurement Access for Evaluation
- Power Management for Low-power Operation
- General-purpose Device Drivers
- Program Loader for Flash Code Download
Advanced Power Management
- On-chip Switching Buck Converter for Internal 1.8V
- 5 mA @ 4 MHz, 17 mA @ 32MHz
- Low-power Mode: 25 µA @ 16kHz
- Power Supervisor with Power On Reset (POR)
- Programmable Battery Monitoring
- Programmable Brown-out
Other
- Single Power Supply; VH = +2.6 to +3.6 V
- 64-lead LQFP Package
- Temperature Range: -40 °C to +85 °C
- Supports ARM7™ Industry-standard Tools
- Supports Shunts & Current Transformers (CTs)
- Customer Development Board (CDB) Available
ORDERING INFORMATION:
See page 40 for details.
DISPLAY
CS7401xx
Current Sense
Tamper Detect
or Other Input
3.6V Power
Supply
LCD Driver
ADC1
ADC2
SSP
FIFO
Power Line
Voltage Sense
ARM7TDMI®
CPU/ROM/
RAM/Flash
ADC3
Power Mgmt
RTC
High-speed
Interface
Epulse
GPIO
Buttons, LEDs,
Switches
RS232
IRDA or RFComm
Application
Components Layer
Device Driver Layer
Hardware Abstraction
Layer (HAL)
Battery
Xtal
Hardware Solution
http://www.cirrus.com
ROM
Profile
Copyright © Cirrus Logic, Inc. 2008
(All Rights Reserved)
Software Solution
AUG ‘08
DS728F1
CS7401xx
TABLE OF CONTENTS
1. Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Firmware/API Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 GPIO Pin Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4. Characteristics & Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1.1 Analog Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.2 ADC Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.3 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.4 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
20
20
20
5.2 Power Supervisor and Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2.1 On-chip Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2.2 Power On Reset and Brown-out Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2.3 Low-battery Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3 Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3.1 ARM7TDMI™ CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3.1.1 Thumb® Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3.1.2 Long Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3.1.3 EmbeddedICE™ Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3.1.4 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3.1.5 ARM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3.2 Memory System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3.2.1 Memory Remap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3.2.2 I/O peripherals overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3.2.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3.2.4 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3.2.5 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.2.6 FLASH and FLASH Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.3 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.3.1 Interrupt Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.4 Boot Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3.5 JTAG Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.4 Embedded Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.4.1 Clock Generation & Real Time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.4.2 UART/IRDAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.4.3 Synchronous Serial Communication Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.4.4 LCD Controller/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.4.4.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.4.4.2 LCD Operating Frequencies Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.4.5 Timers and Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.4.6 GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6. Using a CS7401xx-based power meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.1 AC/DC-Offset and Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.1.1 Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.1.2 Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.1.3 Calibration Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.2 Temperature Sensor Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.2.1 Temperature Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.2.2 Temperature Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.3 RTC Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.4 Power Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1.5 Phase Compensation Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2 Energy Pulse and 1 Hz RTC Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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6.3 Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7. Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9. Environmental, Manufacturing, & Handling Information . . . . . . . . . . . . . . . . . . . 40
9. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
LIST OF FIGURES
Figure 1. CS7401xx Feature Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Firmware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. DC Supply and Reference Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. EPOUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5. CLK1HZ Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. POR and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. Brownout Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. Typical Fully Differential Connection for Current Channel . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. On-chip Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. POR and Brownout Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11. Low Battery Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. CS7401xx Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. CS7401xx Boot Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 14. Clock Generation Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 15. Typical UART Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 16. Typical IrDA Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 17. CS7401xx SSP Port Connections in Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 18. CS7401xx LCD Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 19. DC/AC-Offset and Gain Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 20. Typical Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
LIST OF TABLES
Table 1. CS7401xx Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. GPIO Pin Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Typical Brownout and POR Threshold Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4. Channel PGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6. Memory Types and Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 7. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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CS7401xx
1. HARDWARE DESCRIPTION
The CS7401xx is part of a family of energy measurement system-on-a-chip (SoC) products that provides the ability to implement Metrology, Register, and Communication (MRC) functions all in the same device. Building on our high-quality line of Delta-Sigma (∆Σ) analog-to-digital converters (ADCs), Cirrus Logic has added a very powerful but economical 32-bit processing sub-system, along with a
targeted set of peripherals to provide a very powerful yet cost-effective energy measurement solution. The
CS740111/CS740121/CS740131 are identical except for the amount of flash memory, which is 32 kB/64 kB/128 kB respectively.
Basic to all energy measurement applications is the ability to acquire the voltage and current data with a high degree of precision. The
CS7401xx family of products is built around three independent, high-precision ADCs that concurrently acquire both voltage and current
information at a data rate high enough to measure up to the 30th harmonic. A third channel is available for 3-wire measurement, neutral
current measurement, and for anti-tampering applications. The sampled data is processed through a pipeline of computations which results in a 24-bit quantity available at 1, 2, 4, or 8 kHz.
The power behind this advanced system is a high-performance, 32-bit embedded ARM7™-based subsystem capable of executing the
most demanding standards. The large logical address space allows ease of code development. The ARM7TDMI™ core features a hardware multiplier, 31 registers, a JTAG debug port, EmbeddedICE™ module, flexible interrupt mechanism, and an optional 16-bit Thumb®
instruction set. The CPU can run from Flash, ROM, or RAM. The device includes on-chip debug circuitry that provides non-intrusive,
full-speed, in-circuit debugging of the device installed in the end application.
The 32-bit processing subsystem includes the ROM, RAM, on-chip flash memory, and FIFO interface to the ADC. The 32 kB of ROM
contains a profile for initial code download along with many APIs (see the Firmware/API Description for more details). Application code
can be downloaded to the on-chip flash memory which provides a "Flash-lock" feature that ensures code will remain secure. The ROM
and flash programs are supported by 8 kB of on-chip SRAM that is intended for temporary data storage, but can also be used to execute
code. A special feature of the SoC is having a FIFO interface from the ADC to the processing subsystem, reducing the interrupt overhead
in acquiring data.
The CS7401xx's integrated peripherals reduce the overall system cost. The 120-segment LCD interface eliminates the need for an external LCD controller. The synchronous serial port (SSP) allows the device to interface to many different high-speed peripherals including
non-volatile memory, SRAM, etc. Two UART ports allow communication to RS485, Infrared (IR), or other subsystems. The internal real
time clock (RTC) eliminates the need for an external RTC chip. Other features include several timer/counters, a dedicated HW Energy
Pulse output, and GPIOs to interface with buttons, switches, and control signals. Flexible control allows multiple functionality for each GPIO
pin, enabling custom configuration for different applications.
Power management is key in any system’s design. The device integrates a switching buck converter that efficiently provides a 1.8V internal
supply from the external power supply that is very well regulated. This provides a high level of immunity to power supply noise. The device
has an option for a battery mode with a battery monitor and brown-out detection which allows the software the flexibility to control the power
mode.
Figure 1. CS7401xx Feature Diagram
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2. FIRMWARE/API DESCRIPTION
Development of user Metrology, Register, and Communications (MRC) code is accelerated with the availability of many high-level
APIs in both ROM-based firmware and library function calls. The product is supported with application examples, many development notes, and library of functions which are available in the CS7401xx Software Development Kit (SDK). C-code-based development platforms for the ARM7™ can be provided by several vendors such as Keil.
One of the key firmware APIs is Cirrus Logic's wavelet-based algorithm for power calculation. This algorithm, coupled with the
high-performance Delta-Sigma (∆Σ) ADCs, produces data linearity accuracy of ±0.1% over 3000:1 dynamic range for active power measurement. In addition to active power, it also provides for measurement of reactive and apparent power for both total and
fundamental power. A key feature of this algorithm is the accuracy of the fundamental reactive power measurement which measures the fundamental line frequency (45 Hz to 70 Hz), applies an extremely narrow-band filter to the voltage and current then
calculates the phase angle — all with accuracy similar to that of the active power calculations. Being available in firmware, this
algorithm allows for quick and accurate application development with proven metrology code.
While the Cirrus Logic power measurement algorithm is always available in ROM, it can be partially or totally customized with
flash-based code. This "open" approach to metrology is one of the unique features that is enabled by having a single 32-bit RISC
processing element.
In addition to the metrology, the processor has enough power to implement standards-based data management and secure communications protocols. Metrology typically requires much less than 4 MHz of processor bandwidth. The capabilities of the processing systems to dynamically change processor frequency allows the application to boost the processing power upon demand.
For example, when a communication event occurs, the processor can change the system to 32 MHz operation, service the communication request, and go back to 4MHz operation, minimizing the average power consumption.
The APIs are layered into a component layer, device driver layer, and Hardware Abstraction Layer (HAL). The component layer
provides support for saving/restoring system settings, rapid calibration, handling the ADCs, FIFO interface, filters, power calculations algorithms, and power management to detect brownout condition and manage low-power operation. The device driver
layer contains a set of modules that implements the higher-level functionality needed for managing a hardware block including
reading and writing the flash memory, the interrupt controller, UARTs, calibration/settings partition, energy partition, analog front
end (AFE), core, RTC, timers, SSP, and LCD.
In addition to the APIs, the ROM code contains a full application profile allowing Evaluation, Development, and Manufacturing
(EDM) capabilities over a UART port. This ROM EDM profile allows access to the firmware metrology algorithms and device calibration during initial evaluation and also supports code download to the flash during development and manufacturing. Early evaluation is available using the CDB7401xx-LV (customer demonstration board). This, coupled with a Windows®-based software
tool (CapturePlus II), allows the user to calibrate and test the CS7401xx. Please refer to the CDB7401xx-LV data sheet for details
on the CDB7410xx-LV and the CapturePlus II software.
Figure 2. Firmware Architecture
DS728PP3
5
CS7401xx
GPIO35/SEG27/DSR0/DSR1
GPIO36/SEG28/DCD0/DCD1/BOOT
GPIO37/SEG29/CTS0/CTS1/RCLK
GPIO38/TXD1/TE0/DCLK/SIROUT1
GPIO39/RXD1/SIRIN1
GPIO40/RXD0/SIRIN0
GPIO41/TXD0/SIROUT0/FLASH_LOCK
TDO
TDI
TMS
TCK
RESET
GND
VSC
VH
VD
3. PIN DESCRIPTION
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VA
1
48
AIN1P
2
47
GPIO33/SPCLK/SEG25
AIN1N
3
46
GPIO32/SPCS/SEG24/RI
GPIO34/SPITXD/SEG26
AIN2P
4
45
GPIO31/SPIRXD/SEG23
AIN2N
5
44
EPOUT/GPIO30/TE1/SEG22/CLK1HZ
VBAT
6
43
LCDV3/GPIO29
AIN3P
7
42
LCDV2/GPIO28
AIN3N
8
41
LCDV1/GPIO27
GNDA
9
40
LCDV0/GPIO26
CS7401xx
XIN
10
39
LCDBP3/GPIO25
VREF
11
38
LCDBP2GPIO24
XOUT
12
37
LCDBP1/GPIO23
VBG
13
36
LCDBP0/GPIO22
14
35
SEG21/GPIO21/EM
SEG1/GPIO1
15
34
SEG20/GPIO20
SEG2/GPIO2
16
33
SEG19/GPIO19
SEG0/GPIO0
SEG18/GPIO18
SEG17/GPIO17
SEG16/GPIO16
SEG15/GPIO15
SEG14/GPIO14
SEG13/GPIO13
SEG12/GPIO12
SEG11/GPIO11
SEG10/GPIO10
SEG9/GPIO9
SEG8/GPIO8
SEG7/GPIO7
SEG6/GPIO6
SEG5/GPIO5
SEG4/GPIO4
SEG3/GPIO3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Table 1. CS7401xx Pin Functions
Name
Pin
#
I/O
Function
VA
1
AIN1P
2
I
Differential analog input pin for analog channel 1
AIN1N
3
I
Differential analog input pin for analog channel 1
AIN2P
4
I
Differential analog input pin for analog channel 2
AIN2N
5
I
Differential analog input pin for analog channel 2
VBAT
6
I
Battery voltage monitor
AIN3P
7
I
Differential analog input pin (+) for analog channel 3
AIN3N
8
I
Differential analog input pin (-) for analog channel 3
GNDA
9
XIN
10
External Analog supply (1.8 V)
Analog ground
I
Input of inverting amplifier for crystal oscillator. Connect to one side of 32.768k Hz crystal or to
crystal oscillator source. When using an external 32.768 kHz clock, the input level require-
ments for the XIN pin are 0 to 1.8V.
6
DS728PP3
CS7401xx
Table 1. CS7401xx Pin Functions (Continued)
VREF
11
O
Internal reference voltage output (1.8V)
XOUT
12
O
Output of inverting amplifier for crystal oscillator. Connect to one side of 32 768k Hz crystal
VBG
13
O
Output of band-gap (1.2V)
SEG0/GPIO0
14
I/O
LCD segment output 0 / General-purpose digital I/O 0
SEG1/GPIO1
15
I/O
LCD segment output 1 / General-purpose digital I/O 1
SEG2/GPIO2
16
I/O
LCD segment output 2 / General-purpose digital I/O 2
SEG3/GPIO3
17
I/O
LCD segment output 3 / General-purpose digital I/O 3
SEG4/GPIO4
18
I/O
LCD segment output 4 / General-purpose digital I/O 4
SEG5/GPIO5
19
I/O
LCD segment output 5 / General-purpose digital I/O 5
SEG6/GPIO6
20
I/O
LCD segment output 6 / General-purpose digital I/O 6
SEG7/GPIO7
21
I/O
LCD segment output 7 / General-purpose digital I/O 7
SEG8/GPIO8
22
I/O
LCD segment output 8 / General-purpose digital I/O 8
SEG9/GPIO9
23
I/O
LCD segment output 9 / General-purpose digital I/O 9
SEG10/GPIO10
24
I/O
LCD segment output 10 / General-purpose digital I/O 10
SEG11/GPIO11
25
I/O
LCD segment output 11 / General-purpose digital I/O 11
SEG12/GPIO12
26
I/O
LCD segment output 12 / General-purpose digital I/O 12
SEG13/GPIO13
27
I/O
LCD segment output 13 / General-purpose digital I/O 13
SEG14/GPIO14
28
I/O
LCD segment output 14 / General-purpose digital I/O 14
SEG15/GPIO15
29
I/O
LCD segment output 15 / General-purpose digital I/O 15
SEG16/GPIO16
30
I/O
LCD segment output 16 / General-purpose digital I/O 16
SEG17/GPIO17
31
I/O
LCD segment output 17 / General-purpose digital I/O 17
SEG18/GPIO18
32
I/O
LCD segment output 18 / General-purpose digital I/O 18
SEG19/GPIO19
33
I/O
LCD segment output 19 / General-purpose digital I/O 19
SEG20/GPIO20
34
I/O
LCD segment output 20 / General-purpose digital I/O 20
SEG21/GPIO21
35
I/O
LCD segment output 21 / General-purpose digital I/O 21 / Energy Meter (EM) mode select
LCDBP0/GPIO22
36
I/O
LCD backplane output 0 / General-purpose digital I/O 22
LCDBP1/GPIO23
37
I/O
LCD backplane output 1 / General-purpose digital I/O 23
LCDBP2/GPIO24
38
I/O
LCD backplane output 2 / General-purpose digital I/O 24
LCDBP3/GPIO25
39
I/O
LCD backplane output 3 / General-purpose digital I/O 25
LCDLV0/GPIO26
40
I/O
Analog LCD voltage Level 0 (lowest) / General-purpose digital I/O 26
LCDLV1/GPIO27
41
I/O
Analog LCD voltage level 1/ General-purpose digital I/O 27
LCDLV2/GPIO28
42
I/O
Analog LCD voltage level 2/ General-purpose digital I/O 28
LCDLV3/GPIO29
43
I/O
Analog LCD voltage level 3 (highest)/ General-purpose digital I/O 29
EPOUT/GPIO30/TE1/
SEG22
44
I/O
Energy Pulse output/General-purpose digital I/O 30 / Timer Enable 1 / LCD segment output
22/RTC generated reference clock (CLK1HZ) / Sleep Recovery
GPIO31/SPIRXD/SEG23
45
I/O
General-purpose digital I/O 31/ SPI Receive Data / LCD segment output 23
GPIO32/SPICS/SEG24
46
I/O
General-purpose digital I/O 32/ SPI Chip Select / LCD segment output 24/RI
GPIO33/SPICLK/SEG25
47
I/O
General-purpose digital I/O 33 / SPI Clock / LCD segment output 25
GPIO34/SPITXD/SEG26
48
I/O
General-purpose digital I/O 34 / SPI Transmit Data LCD segment output 26
DS728PP3
7
CS7401xx
Table 1. CS7401xx Pin Functions (Continued)
GPIO35/SEG27/DSR0/
DSR1
49
I/O
General-purpose digital I/O 35 / LCD segment output 27 / DSR 0 / DSR 1
GPIO36/SEG28/DCD0/
DCD1/BOOT
50
I/O
General-purpose digital I/O 36 / LCD segment output 28 / DCD 0 / DCD 1 / Boot mode select (from
FLASH or ROM). Should be pulled high for energy meter applications.
GPIO37/SEG29/CTS0/
CTS1/RCLK
51
I/O
General-purpose digital I/O 37 / LCD segment output 29 / CTS 0 / CTS 1/RCLK (XTAL Calibration
clock)
GPIO38/TXD1/TE0/
DCLK/SIROUT1
52
I/O
General-purpose digital I/O 38 / TXD 1 /Timer Enable 0 / DCLK Output / SIROUT1
GPIO39/RXD1/SIRIN1
53
I/O
General-purpose digital I/O 39 / RXD 1 / SIRIN1
GPIO40/RXD0/SIRIN0
54
I/O
General-purpose digital I/O 40 / RXD 0 / SIRIN0
GPIO41/TXD0/SIROUT0
55
I/O
General-purpose digital I/O 41 / TXD 0 / SIROUT0/ FLASH_LOCK
TD0
56
O
Test data output of Test/Debug (JTAG) Port
TDI
57
I
Test data input of Test/Debug (JTAG) Port
TMS
58
I
Test mode signal input of Test/Debug (JTAG) Port
TCK
59
I
Test clock input of Test/Debug (JTAG) Port
RESET
60
I
Active-low reset
GND
61
Ground
VSC
62
Internal Voltage regulator output.
VH
63
External 3.3 V supply
VD
64
External Digital supply (1.8 V)
See Section 5.4.6 GPIOs on page 34 for details on special functionality of some GPIO pins.
3.1 GPIO Pin Multiplexing
The GPIO pins can be multiplexed with various other functions such as SSP port, serial ports, timer input, energy pulse output,
clock I/Os, and various pull-ups and pull-downs that control initialization. The following provide a reference for the pin multiplexing
options.
Table 2. GPIO Pin Multiplexing
Pin #
14-34
35
36-39
40-43
44
45
46
47
48
49
50
51
52
53
54
55
8
LCD Function
LCD Seg 0-20
LCD Seg 21
LCD BP 0-3
LCD voltage 0-3
LCD Seg 22
LCD Seg 23
LCD Seg 24
LCD Seg 25
LCD Seg 26
LCD Seg 27
LCD Seg 28
LCD Seg 29
GPIO Pins
GP I/O 0-20
GP I/O 21
GP I/O 22-25
GP I/O 26-29
GP I/O 30
GP I/O 31
GP I/O 32
GP I/O 33
GP I/O 34
GP I/O 35
GP I/O 36
GP I/O 37
GP I/O 38
GP I/O 39
GP I/O 40
GP I/O 41
SSP Port
Serial Port Timers
EPulse
Clock
Init. PU/PD
Pull Up (Energy Meter)
SPI Receive
SPI CS
SPI Clock
SPI Transmit RTS 0
DSR 0
DCD 0
CTS 0
TXD1
RXD1
RXD0
TXD0
T4 Enable Epulse
1Hz Out
T3 Enable
Pull Up (Boot Mode)
RCLK In
DCLK Out Pull Down (Test)
Pull Down (Flash Lock)
DS728PP3
CS7401xx
4. CHARACTERISTICS & SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter
Positive Supply Voltage
Symbol
Min
Typ
Max
Unit
VH
2.6
2.4
3.3
2.7
3.6
3.6
V
V
VSC
-
1.8
-
V
(Note 1)
Active Mode
Power Saving Modes
Internal Supply Voltage
Digital Supply Voltage
(Note 2)
VD
1.7
1.8
1.9
V
Analog Supply Voltage
(Note 2)
VA
1.7
1.8
1.9
V
Internal Voltage Reference
VREF
-
1.8
-
V
Internal or External Bandgap Reference
VBG
-
1.27
-
V
System Clock
DCLK
1.953
4096
32768
kHz
RTCLK
-
32.768
-
kHz
TA
-40
-
+85
°C
Real Time Clock Crystal Frequency
Operating Temperature Range
Notes: 1. See diagram below for typical power supply connection. See section 5.1.5 for the definition of power modes.
2.
Supplied by VSC.
3.3 V Operation
3.3 V
VH
10uF
VREF
Ext. VREF
(1.8V)
.1uF
1uF
10uH
VBG
VSC
External VREF
VD
2.2uF
10uF
1uH
VREF
Ext. VBG
1.2V
VA
1uF
1uF
VBG
10uF
External VBG
VREF
1uF
VBG
(Internal VREF
and VBG)
Figure 3. DC Supply and Reference Connections
DS728PP3
9
CS7401xx
ANALOG CHARACTERISTICS
•
•
•
•
•
Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
VH = 3.3 V ±5%; GNDA = GND = 0 V; VREF = +1.8 V. All voltages with respect to 0 V.
MCLK (modulator clock) = 256 kHz; DCLK (CPU Clock) = 4.096MHz.
Accuracy measurements are based upon using ROM-based metrology code provided by Cirrus Logic.
Parameter
Symbol
Min
Typ
Max
Unit
-
±0.1
-
%
Accuracy
Active Power Accuracy
(Note 3)
Input Range 0.03% - 100%
P
(Note 3)
Input Range 0.2% - 100%
Input Range 0.1% - 0.2%
Q
-
±0.1
±0.5
-
%
(Note 3)
Input Range 0.2% - 100%
Input Range 0.1% - 0.2%
RMS
-
±0.1
±0.5
-
%
(Note 3)
Input Range 0.2% - 100%
Input Range 0.1% - 0.2%
S
-
±0.1
±0.5
-
%
(Note 3)
Input Range 0.2% - 100%
Input Range 0.1% - 0.2%
PF
-
±0.1
±0.5
-
%
IIN
-
-
±400
±200
±100
±50
-
±200
±100
±50
±25
mV
IIN
-
Input Capacitance
IC
-
35
-
pF
Effective Input Impedance
EII
400
-
-
kΩ
-
-120
-
dB
CMRR
-
-60
-
dB
Gain Error
GE
-
0.3
-
%
Gain Drift
GD
-
20
-
ppm/°C
Reactive Power Accuracy
Voltage & Current RMS Accuracy
Apparent Power Accuracy
Power Factor Accuracy
Analog Inputs
Differential Input Range
Single Ended Input Range
Channel to Channel Crosstalk (50, 60 Hz)
Common Mode Rejection
1.34x
3x
6x
12x
1.34X
3X
6X
12X
(Note 4)
(50, 60 Hz)
mV
Notes: 3. Applies when the HPF option is enabled, input frequency 50 Hz ±5% and fundamental+harmonics measurement.
4.
10
Full-scale input to the “driven” channel and “measured” channel input grounded.
DS728PP3
CS7401xx
ANALOG CHARACTERISTICS (Continued)
Parameter
Symbol
Min
Typ
Max
Unit
T
-
±5
-
°C
-
5
-
-
6
-
-
16
-
-
17
-
-
24
-
-
27
-
-
23
-
µA
PC
-
16
-
µA
PSRR
-
-85
-
dB
Temperature Channel
Temperature Accuracy
(Note 5)
Power Supplies
Supply Current, Active Mode VH = 3.3 V(Note 6, Note 7, Note 8)
MCLK = 256 kHz, DCLK = 4.096 MHz
MCLK = 512 kHz, DCLK = 4.096 MHz
MCLK = 256 kHz, DCLK = 32.768 MHz
PC
MCLK = 512 kHz, DCLK = 32.768 MHz
mA
Supply Current, Standby Mode VH = 2.7 V(Note 6, Note 7, Note 8)
Internal OSC =OFF, DCLK = 2.048 kHz
Internal OSC = OFF, DCLK = 32 kHz
PC
µA
Supply Current, Sleep Mode VH = 2.7 V(Note 6, Note 7, Note 8)
Internal OSC = OFF, DCLK = Off, Crystal OSC = ON
PC
Supply Current, OFF Mode VH = 2.7 V(Note 7, Note 7, Note 8)
Internal OSC = OFF, Crystal OSC = OFF
Power Supply Rejection Ratio (50 Hz, 60 Hz) (Note 9)
Notes: 5. After temperature sensor calibration.
6.
7.
8.
9.
DS728PP3
MCLK is sourced by the on-chip oscillator, DCLK is the CPU clock
See section 5.1.5 for a description of “Active”, “Standby”, “Sleep”, and “OFF” modes.
All outputs unloaded. All inputs CMOS level. All gains = 1.34x.
Definition for PSRR: VH = 3.3 V, a 150 mV (peak-to-peak) (60 Hz) sinewave is imposed onto the +3.3 V DC supply
voltage at VH pins. The “+” and “-” input pins of both input channels are shorted to AGND. Then the CS7401xx is
commanded to continuous conversion acquisition mode, and digital sampled data is collected for the channel under
test. The zero-to-peak value of the digital sinusoidal output signal is determined, and this value is converted into
the zero-to-peak value of the sinusoidal voltage (measured in mV) that would need to be applied at the channel’s
inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as Veq. PSRR is then (in
dB):
⎧ 150 ⎫
PSRR = 20 ⋅ log ⎨ ---------- ⎬
⎩ V eq ⎭
11
CS7401xx
VOLTAGE REFERENCE
Parameter
Symbol
Min
Typ
Max
Unit
VREF
+1.7
+1.8
+1.9
V
TCVREF
-
±60
±20
-
ppm/°C
ppm/°C
VREF
-
+1.8
-
V
Input Capacitance
-
4
-
pF
Input CVF Current
-
33
-
µA
-
+1.27
-
V
Input Capacitance
-
4
-
pF
Input Current
-
-
2
µA
Internal Reference
Voltage
VREF Temperature Coefficient
(Note 10)
Uncalibrated
Factory Calibrated
External Reference Input
Input Voltage Range
External Bandgap Reference Input
Input Voltage Range
VBG
Notes: 10. The voltage at VREF is measured across the temperature range. Device Flash has not been written. From these
measurements the following formula is used to calculate the VREF Temperature Coefficient:
( VREF MAX – VREF MIN )
1
6
TC VREF = ⎛ --------------------------------------------------------------------⎞ ⎛ ------------------------------------⎞ ( 1.0 × 10 )
⎝
⎠ ⎝ T MAX – T MIN⎠
VREF AVG
11.
12
Specified at maximum recommended output of 1 µA, source or sink.
DS728PP3
CS7401xx
DIGITAL CHARACTERISTICS
•
•
•
•
Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
VH = 3.3 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
MCLK = 256 kHz; DCLK = 4.096MHz.
Parameter
Symbol
Min
Typ
Max
Unit
XIN Frequency (watch crystal or external source), (Note 12)
XIN
-
32.768
-
kHz
-
±20
-
ppm
Clock Characteristics
XIN Frequency Tolerance @ TA = 25°C
Digital Clock Frequency
(Note 13) DCLK
1.953
4096
32768
kHz
Modulator Clock Frequency
(Note 13) MCLK
256
256
512
kHz
XIN Crystal Characteristics
(Note 14)
Frequency Temperature Coefficient
fTC
-
-0.034
Motional Series Resistance @ TA = 25°C
RM
-
-
70
kΩ
Drive Level@ TA = 25°C
DL
-
-
1
µW
Shunt Capacitance
C0
-
1
-
pF
Load Capacitance
CL
-
12.5
-
pF
Quality Factor
Q
-
53000
-
-9
-
+9
°
1
-
8
kHz
-
0.5
-
Hz
ppm/°C
EM Characteristics (Using ROM-based energy monitor metrology code)
Phase Compensation Range
Output Word Rate
High-pass Filter Corner Frequency
OWR
-3 dB
Input/Output Characteristics
High-level Input Voltage (VH=3.3V)
VIH
VH - 0.5
-
-
V
Low-level Input Voltage (VH = 3.3 V)
VIL
-
-
0.5
V
High-level Output Voltage (VH=3.3V)
Iout = +2 mA
VOH
VH - 1.0
-
-
V
Low-level Output Voltage (VH=3.3V)
Iout = -2 mA
VOL
-
-
0.4
V
Input Leakage Current
Iin
-
±1
±10
µA
3-state Leakage Current
IOZ
-
-
±10
µA
Digital Output Pin Capacitance
Cout
-
5
-
pF
Notes: 12. When using an external 32.768 kHz clock, the input level requirements for the XIN pin are 0 to 1.8V.
13.
14.
DS728PP3
MCLK is sourced by the on-chip oscillator, DCLK is the CPU clock.
Citizen CM415 or equivalent crystal.
13
CS7401xx
SWITCHING CHARACTERISTICS
•
•
•
•
Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
VA = 1.8 V ±.1 V, VD = 1.8 V ± 0.1 V; GNDA = GND = 0 V. All voltages with respect to 0 V.
Logic Levels: Logic 0 = 0 V, Logic 1 = VD.
Parameter
Symbol
Min
Typ
Max
Unit
trise
-
50
1.0
-
µs
ns
tfall
-
50
1.0
-
µs
ns
16)
trtcos
-
0.3
-
s
See Figure 6
tsysos
-
1
-
s
SPICLK0
-
-
2
MHz
t1
t2
200
200
-
-
ns
ns
SPICS0 Falling to SPICLK0 Rising
t3
50
-
-
ns
Data Set-up Time Prior to SPICLK0 Rising
t4
50
-
-
ns
Data Hold Time After SPICLK0 Rising
t5
100
-
-
ns
SPICS0 Falling to SPITXD Driving
t6
-
20
50
ns
SPICLK0 Falling to New Data Bit (hold time)
t7
-
20
50
ns
SPICS0 Rising to SPITXD Hi-Z
t8
-
20
50
ns
t9
t10
-
8
8
-
ns
MODE setup time to RESET Rising
t11
50
-
-
ns
RESET rising to CS falling
t12
48
-
-
ns
SPICS0 falling to SPICLK0 rising
t13
100
8
-
ns
SPICLK0 falling to SPICS0 rising
t14
-
16
-
ns
SPICS0 rising to driving MODE low
t15
50
-
-
ns
SPITXD setup time to SPICLK0 rising
t16
100
-
-
ns
Rise Times
(Note 15)
Any Digital Output
Fall Times
(Note 15)
Any Digital Output
Start-up
RTCLK Start-up Time
XTAL = 32.768 kHz (Note
MCLK and DCLK Start-up Time
Serial Port (SSP) Timing
Serial Clock Frequency
Serial Clock Pulse Widths
Pulse Width High
Pulse Width Low
SPIRXD Timing
SPITXD Timing
External E2PROM Mode Timing
Serial Clock (SPICLK0)
Pulse Width Low
Pulse Width High
Notes: 15. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
16.
14
Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external
clock source.
DS728PP3
CS7401xx
SWITCHING CHARACTERISTICS (Continued)
Parameter
Symbol
Min
Typ
Max
Unit
tperiod
0.5
-
230 - 1
µs
Pulse Width
tpw
0.25
-
230 - 2
µs
Rising Time
ton
-
20
-
ns
Falling Time
toff
-
20
-
ns
tperiod
-
1
-
s
Pulse Width
tpw
-
0.5
-
ms
Rising Time
ton
-
20
-
ns
Falling Time
toff
-
20
-
ns
EPOUT Timing
(Note 17, 17and 19)
Period
CLK1HZ Timing
Period
Notes: 17. Pulse output timing is specified at DCLK = 4.096 MHz. Both period and pulse width are user programmable.
18.
19.
Output pin has the driving load of 30 pF.
Timing is proportional to the frequency of DCLK
toff
tpw
ton
EPOUT
tperiod
Figure 4. EPOUT Timing
toff
tpw
ton
CLK1HZ
tperiod
Figure 5. CLK1HZ Timing
DS728PP3
15
CS7401xx
ABSOLUTE MAXIMUM RATINGS
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Parameter
Symbol
Min
Typ
Max
Unit
DC Power Supplies
(Notes 20 and 21)
Digital
Analog
VH
VD
VA
-0.3
-0.3
-0.3
-
3.63
1.98
1.98
V
V
V
Input Current, Any Pin Except Supplies
(Notes 22, 23, 24)
IIN
-
-
±10
mA
IOUT
-
-
100
mA
5
mA
Output Current
Output Current Sourced or Sunk by Any I/O Pin
-
Analog Input Voltage
All Analog Pins
VINA
-0.3
-
(VA) + 0.3
V
Digital Input Voltage
All Digital Pins
VIND
-0.3
-
(VD) + 0.3
V
Ambient Operating Temperature
TA
-40
-
85
°C
Storage Temperature
Tstg
-65
-
150
°C
Notes: 20. VA and GNDA must satisfy [(VA) - (AGND)] ≤ + 1.98 V.
21.
22.
23.
24.
16
VD and GNDA must satisfy [(VD) - (AGND)] ≤ + 1.98 V.
Applies to all pins including continuous over-voltage conditions at the analog input pins.
Transient current of up to 100 mA will not cause SCR latch-up.
Maximum DC input current for a power supply pin is ±50 mA.
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CS7401xx
MEMORY
Parameter
Symbol
Min
Typ
Max
Unit
30
-
-
ns
Program Time per Word
20
-
40
µs
Read Time (No Wait State)
30
-
-
ns
Page Erase (2 kB)
20
-
40
ms
Mass Erase
20
-
40
ms
-
20
-
k
RAM
Read/Write Time (No Wait State)
FLASH
Maximum number of Write Cycles
Notes: 25. Minimum supply voltage when the data in the RAM remain unchanged. No program execution should take place.
POWER ON RESET (POR) AND BROWNOUT DETECTION TIMING
Parameter
Symbol
Min
Typ
Max
Unit
VH=Vt1 to RESET pin high
t0
2
-
-
ms
VH=Vt1 to POR_3.3V rising
t1
-
50
-
µs
POR_3.3V rising to Bandgap_on rising
t2
-
2
-
ns
Bandgap_on rising to Bandgap_rdy rising
t3
-
50
-
µs
Bandgap_rdy rising to 65.536 MHz OSC_on rising
t4
-
20
-
ns
65.536 MHz OSC_on rising to Regulator_on rising
t5
-
1
-
µs
Buck Regulator_on to ARM_Reset rising
t6
-
4
-
µs
VH=vt2 to PSUP_INT[1] high
t7
-
60
-
µs
26.
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POR timing parameters and timing are shown in Figure 6 on page 18
17
CS7401xx
Vt1
Vt4
VH=3.3V
t0
RESET Pin
t1
POR_3.3V
t2
Bandgap_on
t3
Bandgap_rdy
t4
65.536MHz OSC_on
t5
Buck Regulator_on
t6
ARM_Reset
Figure 6. POR and Reset Timing
Vt2
Vt3
VH=3.3V
t7
PSUP_INT[1]
Figure 7. Brownout Timing
Table 3. Typical Brownout and POR Threshold Voltages
Voltage Threshold
18
VH
Voltage Threshold Vt1
1.95 V
Voltage Threshold Vt2
2.66 V
Voltage Threshold Vt3
2.6 V
Voltage Threshold Vt4
1.7 V
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5. FUNCTIONAL DESCRIPTION
5.1 Analog Front End
The CS7401xx Analog Front End (AFE) incorporates three fully differential analog input channels. Inputs AINx± are designed for
voltage and/or current channel inputs.
Each channel has a highly integrated, 24-bit ADC, designed using multi-bit delta-sigma techniques. The ADCs operate at an oversample rate of programmable 32, 64, 128, or 256 times the system output word rate (OWR). The different clock rates maximize
power savings while maintaining high performance. The multiple-ADC structure samples the voltage and current inputs simultaneously. The ADC operates in one of two clock rates: 256 kHz and 512 kHz. The output word rates supported can be from 1 kHz
to 8 kHz. For power meter applications, the typical output word rate is 4 kHz. The AFE is tightly integrated within the SoC with
configuration registers, status registers, and ADC data interface mapped into the CPU I/O memory.
5.1.1 Analog Channels
To accommodate different sensing elements each channel incorporates a Programmable Gain Amplifier (PGA) with four programmable input gains. Table3 illustrates the ADC channels’ four gain selections and corresponding maximum input-signal level.
The maximum level of single-ended signal is half of that of fully differential signal.
Table 4. Channel PGA Configuration
Input Connection Type
Fully Differential
Maximum Input Range
RMS
Gain
±400 mVp
282.8 mVRMS
1.34x
±200 mVp
141.4 mVRMS
3x
±100 mVp
70.7 mVRMS
6x
±50 mVp
35.4 mVRMS
12x
±200 mV
141.4 mVRMS
1.34x
±100 mV
70.7 mVRMS
3x
±50 mV
35.4 mVRMS
6x
±25mV
17.7 mVRMS
12x
Single Ended
For example, the channel’s PGA gain is set to 1.34x. If the input signal is fully differential and pure sinusoid, the maximum signal
level will be 400 mVp or 282.8 mVrms which generates full-scale ADC data output. If the input signal is single-ended, the maximum signal level will be 200 mVp or 141.4 mVrms which generates half the full-scale ADC data output. To achieve the maximum
input impedance, the ADCs should be configured as single-ended or differential mode according to the actual signal input connection.
Figure 9 shows a typical fully differential connection for the current channel with a current transformer (CT). In this diagram,
Ri± (470 ohms) and Ci± (33nF) act as the simple RC anti-alias filter that has about 30 dB attenuation at the sampling rate
MCLK = 256KHz.
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CS7401xx
Line
Current
CS7401xx
Ri+ = 470
½
Rburden
AIN2P
Ci+ = 33nF
Current
Transformer
(CT)
Ci- = 33nF
½
Rburden
Ri- = 470
AIN2N
Figure 8. Typical Fully Differential Connection for Current Channel
5.1.2 ADC Measurements
The CS7401xx AFE incorporates three oversampling, delta-sigma (∆Σ) analog-to-digital converters (ADCs). The high-fidelity
24-bit ADCs are identical. The ADCs operate with analog supply voltage VA of 1.8V and provide an output word rate of up to
8k samples per second. The AFE ADCs can be powered down individually to save power consumption.
A 3rd-order, feed-forward, multi-bit delta-sigma modulator is the core of the AFE A/D converters. The multi-bit modulator architecture facilitates ultra-low-power operation. The decimation ratio (DR) of the ADCs is 32/64/128/256 programmable. The ADCs
perform instantaneous measurements at an output word rate (OWR) of
MCLK
OWR = ----------------
DR
Therefore, with MCLK = 256KHz and DR = 64, the maximum OWR is 4k samples per second and the ADC frequency bandwidth
is 2 kHz.
At each instantaneous measurement, the 24-bit sample is stored in the AFE FIFO. When the data in the FIFO reaches a user
determined level, an interrupt is generated to the CPU. Handling this AFE interrupt is the main responsibility of the meter pre-process component in Energy Monitor firmware. The meter pre-process component offers a variety of filters and other services to
manipulate the samples acquired by the AFE.
After the meter pre-process, the power utilities component in the Energy Monitor firmware provides functions to calculate both
basic and advanced power parameters such as RMS voltage/current, active power, apparent power, reactive power, power factor, etc.
5.1.3 Voltage Reference
A high-precision, low-drift 1.8 V bandgap reference is provided on-chip. The internal reference also appears on the VREF pin.
When using the internal reference, a 10 µF capacitor must be connected from the VREF pin to AGND to filter the output-stage
noise and ensure stability during conversions. Also a 1µF capacitor must be connected from VBG pin to AGND to filter the bandgap noise. The reference can be used as a reference for other circuits in the system. However, an external buffer would be required because of the low drive capability of the VREF output. The VREF pin also provides a means of connecting an external
reference.
5.1.4 Temperature Sensor
The CS7401xx contains an on-chip temperature sensor which is designed to assist in characterizing the measurement elements
over a desired temperature range. Once a temperature characterization is performed, the temperature sensor can then be utilized
to assist in compensating for temperature drift.
By setting the appropriate bits in temperature sensor configuration register (CONFIG_TS), the temperature sensor can be powered up and routed to an ADC channel (ADC channel 2 or 3). The ADC output can then be calculated to the real temperature
value by the firmware. The calibration component in ROM also provides temperature calibrations. After the calibrations, the
on-chip temperature sensor can reach to an accuracy of ±5 °C.
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5.2 Power Supervisor and Power Modes
The CS7401xx power supervisor circuitry provides battery-mode detection, power on reset, and programmable brown-out detection and low-battery detection. The supervisory circuit guarantee the RESET assertion to protect the SoC during power up and
power down. The battery-mode detection, brown-out detection and low-battery detection generate interrupts which can be used
by software to initiate specific power down sequence to put the SoC into different power modes for power saving and proper operation.
Typically, power modes for the CS7401xx include “Active”, “Standby”, “Sleep”, and “Off”. Each mode is defined in Table 5.
.
Table 5. Power Modes
Power Mode
Active
Description
All circuitry is operational. The Buck regulator is enabled.
Standby
The linear regulator is enabled. The internal oscillator, bandgap, ADCs
and temperature sensor are powered down. The digital sections including
the ARM7 are running using a slow clock from RTC oscillator. The speed
of the digital clock is dependent upon the settings of the Clock Divider
Control and Enable register.
Sleep
The linear regulator is enabled. All circuits are shut down or disabled
except the RTC. This mode can only be exited by applying a low-to-high
transition on GPIO30 (pin 44) or by a chip reset.
Off
RAM retention only. The linear regulator is enabled. All circuits are shut
down or disabled including internal oscillator and RTC oscillator. This
mode can only be exited by a chip reset.
5.2.1 On-chip Voltage Regulators
The CS7401xx has two voltage regulators internally to step down the single power supply (VH) to1.8V for the analog and the
digital circuitry. Refer to figure 2 on page 8 for recommended power supply connections.
CS7401xx
VH
VSC
Buck Regulator
Buck_enable
Linear Regulator
L
VD
L
VA
Figure 9. On-chip Voltage Regulators
The buck regulator can supply the maximum load current of 80mA and is used in active power mode. The operation of the buck
regulator needs the internal 65.536 MHz oscillator and bandgap to be ready. The linear regulator can supply a load current up to
2 mA and be used in power saving modes. If the linear regulator is enabled, the Flash operation (read or write) must be avoided
and software code should be running from either ROM or RAM. The internal Buck_enable signal controls which regulator is enabled.
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CS7401xx
5.2.2 Power On Reset and Brown-out Detection
Proper operation of the POR system requires that the external reset pin be connected to a RC with a time constant greater than
2 ms. This reset input pin is AND-ed with an internal signal indicating that the voltage is above 1.95 V to start the power-on sequence within the device. This signal will then enable the band gap, internal 65.536MHz oscillator, buck regulator, and finally
release the reset to the ARM processor. This comparator has hysteresis such that when the voltage drops back below 1.7 V, the
part will be held in reset. Refer to Power On Reset (POR) and Brownout Detection Timing on page 17 and Figure 6 on page 18
for detail on timing.
There are two conditions that can generate an interrupt to the ARM processor as an indication of a potential brown-out condition.
The first is a comparator between VH and the battery. If VH falls below the battery voltage, the internal PSUP_INT[0] interrupt
will trigger, if enabled. The second is a comparator between VH and an internal, programmable comparator. This comparator can
be programmed from 2.75 V to 3.05 V in 0.1 V steps. If VH falls below the programmed threshold, the internal PSUP_INT[1] interrupt will trigger, if enabled.
At the point the interrupts occur, it is the responsibility of the software to manage the power state. See the power manager software development note for more details on the software operation during this condition.
VH
RESET
Startup
1.95/1.7V
PSUP_INT[1]
3.6V
VH
VBat
Brownout3p3_cntrl
(2.75 to 3.05V)
PSUP_INT[0]
Figure 10. POR and Brownout Functional Diagram
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5.2.3 Low-battery Detection
The CS7401xx contains a voltage comparator for low-battery detection. When the comparator is enabled and the battery voltage
is lower than the pre-programmed threshold, the Vbat_low bit in the power supervisory register will be set. Because battery voltage may differ considerably with or without a load, an internal 8 Kohms resistive load can be enabled on VBAT pin to implement
more practical low-battery detection.
CS7401xx
BrownoutVbat_load_enable
8 KOhms
-
VBAT
Vbat_low
Voltage Threshold
+
BrownoutVbat_cntrl[4:0]
Figure 11. Low Battery Detection
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5.3 Central Processor Unit (CPU)
The CPU offers a high-performance processor utilizing the high-speed 16/32-bit ARM7TDMI™ core, resulting in a high instruction
throughput while maintaining high code efficiency. The processor core views ROM, SRAM, Flash, and memory-mapped registers
(MMRs) as a single, linear array. ICE debugging is supported via the JTAG interface.
5.3.1 ARM7TDMI™ CORE
The ARM7TDM™ core is a 32-bit reduced instruction set computer (RISC). It uses a single 32-bit bus for instruction and data.
The length of the data can be 8, 16, or 32 bits and the length of the instruction word is 32 bits. The ARM7TDMI™ is an ARM7™
core with 4 additional features:
-
Thumb® 16-bit compressed instruction set
JTAG Debug support on-chip, enabling the processor to halt in response to a debug request
Multiplier enhanced with higher performance, yielding a full 64-bit result
EmbeddedICE™ included within the core hardware to support embedded system debugging.
5.3.1.1 Thumb® Mode
An ARM® instruction is 32-bits long. The ARM7TDMI™ processor supports a second instruction set that has been compressed
into 16-bits, the Thumb® instruction set. Greater code density can usually be achieved by using the Thumb instruction set instead
of the ARM instruction set, which makes the ARM7TDMI core particularly suitable for embedded applications. However, the
Thumb mode has two limitations:
- Thumb code usually uses more instructions for the same job, so ARM code is usually best for maximizing the performance
of any time-critical code.
- The Thumb instruction set does not include some instructions that are needed for exception handling, so the core will
automatically switch to ARM code for exception handling.
Since the CS7401xx program memory (Flash) is on-chip, up to 30% code density can be achieved by utilizing Thumb instructions.
Thumb and ARM instructions both reside in 32-bit Flash memory. Therefore, one fetch will retrieve two Thumb instructions from
the 32-bit memory.
5.3.1.2 Long Multiply
The Energy Monitor (EM) requires efficient digital signal processing (DSP) routines to calculate power/energy measurements.
The ARM7TDMI instruction set includes four extra instructions which perform 32-bit by 32-bit multiplication with 64-bit product,
and 32-bit by 32-bit multiplication-accumulation (MAC) with 64-bit result. These calculations are achieved in a reduced number
of cycles compared to a standard ARM7 core.
5.3.1.3 EmbeddedICE™ Module
The EmbeddedICE™ module provides integrated on-chip support for the core. The EmbeddedICE module contains the breakpoint and watchpoint registers which allow code to be halted for debugging purposes. These registers are controlled through the
JTAG test port. When a breakpoint or watchpoint is encountered, the processor halts and enters the debug state. Once in the
debug state, the processor registers may be inspected as well as the embedded Flash, SRAM, and MMRs.
5.3.1.4 Exceptions
ARM supports five types of exceptions, and a privileged processing mode for each type. The five type of exceptions are:
-
normal interrupt or IRQ provided to service general-purpose interrupt handling of internal and external events
fast interrupt or FIQ provided to service data transfer or communication with low latency. FIQ has priority over IRQ.
memory abort
attempted execution of an undefined instruction
software interrupt (SWI) instruction which can be used to make a call to an operating system
Typically the programmer will define interrupts as IRQ, but for a higher-priority interrupt, the programmer can define the interrupt
as FIQ for faster response time.
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5.3.1.5 ARM Registers
The ARM7TDMI™ processor has a total of 37 registers, of which 31 are general-purpose registers and six are status registers.
Each operating mode has dedicated, banked registers.
When writing user-level programs, 15 general-purpose 32-bit registers (r0 to r14), the program counter (r15), and the current program status register (CPSR) are usable. The remaining registers are used only for system-level programming and for exception
handling.
When an exception occurs, some of the standard registers are replaced with registers specific to the exception mode. All exception modes have replacement banked registers for the stack pointer (r13) and the link register (r14), as represented in Figure 12.
The fast interrupt mode has more registers (8 to 12) for fast interrupt processing, so that the interrupt processing can begin without the need to save or restore these registers and thus save critical time in the interrupt handling process.
5.3.2 Memory System
The CS7401xx SoC is constructed so that the complete memory system is on-chip. On-chip memory can support zero-wait-state
access speeds and provides better power efficiency and reduced electromagnetic interference. The CS7401xx on-chip SRAM is
preferred to cache memory for a number of reasons: it is simpler, cheaper, uses less power, and has a more deterministic behavior. The memory controller and Flash interface enable the ARM7 to access RAM, Flash, and ROM via the AHB (Advanced
High-speed Bus).
The CPU is configured with the types of memory shown in Table 6: Memory Types and Sizes.
Memory Type
Size
Address
ROM
32 kB
0x0800_0000
SRAM
8 kB
0x0400_0000
FLASH
32 kB, 64 kB, or 128 kB
0x0000_0000
Table 6. Memory Types and Sizes
Bank size and cycle times are fixed for the ROM and SRAM, but can be configured for Flash. The memory types are described
later.
5.3.2.1 Memory Remap
The CS7401xx is a small embedded implementation with memory constraints. However, a hardware solution is provided which
allows a portion of ROM that overlays Flash to be remapped. As on all ARM-based processors, the boot strap loader (BSL) image
starts execution at address 0x0000_0000. The first instruction executed loads the program counter with the reset vector address
stored at an initial offset (of usually 0x0000_0020). Execution then continues at the reset vector address. The memory map has
two states:
- Normal, selected when BOOT pin (pin 50) is low at reset.
- Remapped, selected when the BOOT pin (pin 50) is high at reset.
For energy meter applications, pin 50 (BOOT) should be pulled high.
5.3.2.2 I/O peripherals overview
The CPU utilizes a standard memory-mapped I/O approach to perform I/O functions. The base address of all I/O memory mapped
registers (MMRs) is factory defined, starting at address 0x1800_0000. The SoC architecture supports embedded peripherals in
two areas:
- Advanced Peripheral Bus (APB)
- Advanced High-speed Bus (AHB)
The AHB peripherals implement a Clock Generator and System Controller which are connected to the AMBA AHB. Other embedded peripherals such as interrupt controller, timers/counters, LCD driver, RTC, UART, SSP and GPIOs are connected to the
APB.
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CS7401xx
5.3.2.3 Memory Map
The CS7401xx has its memory arranged as a linear set of logical addresses. The ARM7 core sees memory as a linear array of
232 byte locations. The different blocks of memory are mapped as outlined in Figure 12. The memory organization is configured
in little endian format – the least-significant byte is located in the lowest byte address and the most-significant byte in the highest-byte address. Register addresses are all word-aligned. The exception vectors are all mapped at the bottom of the memory
array from address 0x0000_0000 to 0x0000_0020.
0xFFFFFFFF
0x1FFFFFFF
System Registers
0x10000000
0x08007FFF
Clock Sys
0x1D000000
AFE
0x1C000000
Oscillator
0x18A00000
LCD
0x18800000
GPIO
0x18700000
RTC
0x18600000
UART1
0x18500000
UART0
0x18400000
Timer
0x18300000
SSP
0x18100000
APB
0x18000000
Memory Configuration
0x11000000
30K ROM
0x08000800
0x080007FF
0x08000000
2K FLASH
0x04001FFF
8K RAM
Reserved EM and BM
0x040000D0
0x040000CF
0x04000000
Reserved for EM/
Calibrations
0x0001FFFF
0x0001F800
0x0001F7FF
0x00000018
126K FLASH
0x00000800
0x00000020
0x0000001F
0x00000000
0x1100001F
0x1100000C
Boot Monitor (BM)
Exception, Interrupt and Reset Vectors
FIQ
IRQ
Reserved
Data Abort
Prefetch Abort
Software Interrupt
Undefined Instructions
Reset
0x00000016
0x00000014
0x0000000C
0x00000008
0x00000004
0x00000000
Figure 12. CS7401xx Memory Map
C language programs expect to have access to a fixed area of program memory (where the application image resides) and to
support two data areas that grow dynamically and where the compiler often cannot work out an optimum size. These dynamic
areas are:
- The stack. Whenever a (non-trivial) function is called, a new activation frame is created. When a function returns, its stack
space is automatically recovered and will be reused for the next function call.
- The heap. The heap is an area of memory used to satisfy program request for more memory for new data structures. A
program which continues to request memory over a long period of time should be careful to free up all sections that are no
longer needed, otherwise the heap will grow until memory is full.
Due to the limitations of the SRAM in a small embedded system such as the CS7401xx, minimal stand-alone run-time libraries
should be ported to the target environment, which allows basic C programs to run. This library therefore reflects the minimal requirements of a C program.
5.3.2.4 ROM
ROM provides single-cycle, read-only memory and is factory programmed with a Boot Monitor and the Energy Monitor firmware image.
At power up and with the BOOT pin high, the SoC is in remapped state (See Figure 12), ROM aliases Flash at 0x0000_0000 and Boot
Monitor initiates the SoC boot sequence. See 5.3.4 Boot Monitor on page 28 for detailed boot sequence.
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5.3.2.5 SRAM
Synchronous SRAM is used to provide single-cycle, read-write memory. The SRAM region is organized as 2k x 32-bits and is chosen
to represent temporary data memory. SRAM is used for temporary power calculation storage and for the dynamic stack/heap areas.
The memory controller provides the interface between SRAM and the AHB (Advanced High-speed Bus). The SRAM is located at address 0x0400_0000. SRAM locations from 0x0400_0000 to 0x0400_00CF are reserved for Boot Monitor and Energy Monitor firmware.
Free SRAM for custom applications starts from 0x0400_00D0.
5.3.2.6 FLASH and FLASH Interface
The Flash memory is organized into pages of 2 kB. The total Flash size is up to 128 kB and is connected to the ARM7 core via the
Memory Controller and Flash Interface and the AHB. Address, data along with clock and control signals are passed to the Flash from
the AHB. Programming and erase function are configured and controlled via the internal Memory Controller and Flash Interface registers. The Flash locations from 0x0001F800 to 0x0001FFF are reserved for calibration functions of Energy Monitor. All other locations
can be used to store user’s application code and data.
To protect the customer’s application code, the Flash memory can be locked either by hardware (pin55 - Flash Lock) or by software.
Once the flash is locked, the Flash memory can not be read through JTAG. Only a mass erase can clear the Flash lock state.
Refer to the MEMORY table on page 17 for the timing specifications for the Flash memory.
5.3.3 Interrupt Controller
The interrupt controller provides a simple software interface to the interrupt system. The interrupt controller is compliant with the ARM
Reference Peripheral Specification (RPS). The mapping of the interrupt controller registers conforms to the RPS with a base address
of 0x1890_0000. In the CS7401xx system, two levels of interrupts are available:
- FIQ (Fast Interrupt Request) for fast, low-latency interrupt handling
- IRQ (Interrupt Request) for more-general interrupts
Separate interrupt controllers are used for FIQ and IRQ. The difference is that only a single bit position is defined for FIQ, which is intended for use by a single interrupt source, while 32 bits are available in the IRQ controller. A number of methods may be used to extend
the IRQ interrupt controller if more than 32 interrupt sources are required.
The CPU utilizes a single-source FIQ, which is driven by the AFE circuit. This provides a true low-latency interrupt, because a single
source ensures that the interrupt service routine may be executed directly without the need to determine the source of the interrupt. It
also reduces the interrupt latency because the extra banked registers that are available for FIQ interrupts may be used to maximum
efficiency by preventing the need for a context save.
The IRQ interrupt controller uses a bit position for each interrupt source. Bit positions are defined for software-programmed interrupts,
communication channels, timers/counters, real time clock, and analog front end. Bit 0 is unassigned in the IRQ controller so that it may
share the same interrupt source as the FIQ controller. All IRQ interrupt source inputs are active high and level sensitive. A programmed
interrupt register is provided to generate an interrupt under software control.
5.3.3.1 Interrupt Latency
The worst-case latency for an FIQ consists of the longest time the request can take to pass through the synchronizer, plus the time for
the longest instruction to complete (the longest instruction is an LDM) which loads all the registers including the program counter (PC),
plus the time for the data abort entry, plus the time for FIQ entry. At the end of this time, the ARM7TDMI will be executing the instruction
at 0x1C (FIQ interrupt vector address). The maximum total time is 50 processor cycles, which is just over 1.5 µSec in a system using
a continuous 32 MHz processor clock. The maximum IRQ latency calculation is similar, but must allow for the fact that FIQ has higher
priority and could delay entry into the IRQ handling routine for an arbitrary length of time. This time can be reduced to 42 cycles if the
LDM command is not used, some compilers have an option to compile without using this command. Another option is to run that part
of the code in Thumb mode where the time is reduced to 22 cycles.
The minimum latency for FIQ or IRQ interrupts is five cycles, which consists of the shortest time the request can take through the synchronizer plus the time to enter the exception mode.
Note: The ARM7TDMI will always be run in ARM (32-bit) mode when in privileged modes, i.e. when
executing interrupt service routines.
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5.3.4 Boot Monitor
The Boot Monitor is part of the factory-embedded firmware in ROM. After the SoC comes out of reset with BOOT pin high, the
Boot Monitor starts to run and guide the boot sequence as follows.
Reset
Initialize
ARM Vectors
Check
EM Pin (Pin35)
EM Pin High
MRC
Application
EM Pin Low
Initialize
Internal Oscilator
Check for
Signature
Y
N
Initailze
UART
Spin
Jum p to Flash
0x00000804
Send out
Boot prompt
ROM EDM Profile
Figure 13. CS7401xx Boot Sequence
1) Initialize ARM Vectors - All exception vectors except for reset jump to RAM. This step initializes the exception
vector table by initializing the code in RAM to the “b.” instruction.
2) Check EM Pin - Check Pin 35 which is EM pin (pin 35). The latched state of the EM pin is in bit 2 of the
MEM_PROT register. If the pin is high, the process branches to the Flash-based MRC user application. If the
pin is low, then branches to the embedded ROM EDM profile.
3) Check for Signature - This step checks if the custom application code loaded at Flash address 0x00000800 contains a valid data signature of “CRUS”. If the signature exists, then the process steps to the next address location
(0x00000804) and executes the loaded application code. If the signature does not exist, then the process remains a loop.
4) Initialize Internal Oscillator - This step initializes the internal 65.536 MHz oscillator. This step must occur before
using the UART. Failure to perform this step causes the CS7401xx UART baud rate to deviate more than 5%
from acceptable levels. As a result, the CS7401xx will be unable to communicate with other devices through the
UART.
5) Initial UART - Initialize the UART0 to 9600 baud, 8 bits, no parity, and no stop bit.
6) Send Out Prompt - Sends out a ‘>’ prompt so that a host computer can initiate ROM EDM profile commands
through RS232 port.
7) ROM EDM Profile - This step branches to the main routine in ROM EDM Profile.
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5.3.5 JTAG Debug Interface
The ARM7TDMI™ processor debug interface is based on IEEE std. 1149.1 - 1990, Standard Test Access Port and Boundary-scan Architecture. Refer to this standard for an explanation of the terms and for a description of the Test Access Port (TAP)
controller states. The CPU contains hardware extensions for advanced debugging features. These make it easier to develop application software, monitors/BSL, and the hardware itself.
The EmbeddedICE™ module provides integrated, on-chip support for the core. A JTAG debug probe (e.g. Multi-ICE) and EmbeddedICE are a JTAG-based debugging system for the CS7401xx SoC providing the interface between a debugger and the
ARM7 core embedded within the ASSP.
This system provides:
-
real-time, address-dependent, and data-dependent breakpoints
watchpoint registers
single stepping
full access to, and control of the ARM core
full access to the SOC
full memory access (read and write). Once the Flash is locked, access to Flash is prohibited.
full I/O system access (read and write)
enable the embedded microprocessor to access services of the host system
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5.4 Embedded Peripherals
The CS7401xx SoC incorporates a collection of intelligent peripherals that are required in applications specific to energy metering. All embedded peripherals are fully compliant with the widely used SoC bus protocol, the Advanced Microcontroller Bus Architecture (AMBA®) protocol from ARM. The embedded peripherals utilize the AMBA Advanced Peripheral Bus (APB), which is
optimized for minimal power consumption and reduced interface complexity to support peripheral functions. APB is used in conjunction with the standard AMBA AHB version of the on-chip system bus for high system performance.
5.4.1 Clock Generation & Real Time Clock (RTC)
All clocks on the CS7401xx are generated from a single, low-cost 32.768 kHz crystal. To further reduce cost, the 22 pF capacitors
typically needed for crystal operation, are integrated into the device. This oscillator circuit drives the fast clock generation, RTC
subsystem and can drive the ARM process for ultra-low-power operation.
The real time clock (RTC) subsystem is driven from the 32 kHz oscillator. This clock is then divided down to a 1 Hz clock to operate a digital counter that can be used to generate time and date information. In many cases, the low-cost, 32.768 kHz crystal
oscillator may not meet the accuracy requirements of the application. In this case, an external 16.77721 MHz clock can be used
to calibrate the RTC to produce a highly accurate 1 Hz clock. Once calibrated, the RTC block will always generate an accurate
clock with the crystal. Other than counting on the 1 Hz clock, the RTC can also generate an interrupt. The real time clock portion
of the circuit operates whenever power is applied and the 32 kHz input clock is running.
On on-chip relaxation oscillator is used to generate a 65.536 MHz internal high-speed clock. This clock feeds both the analog
front end (AFE) subsystem and the digital core. The AFE subsystem has its own clock divider needed to set the sampling rate of
the ADC. The digital core is clocked by the output of a clock divider which can provide 4 MHz, 8 MHz, 16 MHz or 32 MHz operational speed. The default DCLK is 4.096 MHz.
During brownout conditions, the system clock can be switched to 32 kHz operation. This is a low-power standby mode where the
RTC, RAM, and CPU are still operational. The AFE is not powered during standby mode. In standby mode, Flash is operational
only in read mode. Interrupts can be used to bring the system out of standby mode or the power management can detect that
power has been restored and software will bring the device out of standby mode.
Fast Clock
Generation
22pF
OSC
32.768
kHz
XOUT
AGND
16.777216 MHz
RCLK
CLK1HZ
22pF
32.768 kHz
XIN
65.536 MHz
DCLK is also used to drive the timing for the SPP and UART peripherals. Care must be taken to ensure these clock dividers are
changed when the DCLK speed is changed.
÷1024
XCLK
RTC
Calibration
RTC
Counter
Div by MCLK
32,64,
128,256
Div by
2,4,
8,16
XCLK Switch
Slow Clk En
Analog
Front
End
UART
Clock Divider
SSP
Clock Divider
Timers
Watchdog
DCLK
To ARM, Memory &
Other Peripherals
Figure 14. Clock Generation Diagram
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5.4.2 UART/IRDAs
Each of the two UARTs is a serial communication controller with full infrared support which is also compatible to industry-standard
16C550 UART devices. These intelligent peripherals support the RS-232 and Infrared Data Association (IrDA®) SIR physical layer standards. Modem control signals CTS, DCD, DSR and RI are supported. DTR and RTS signals are not supported and could
be implemented using GPIOs.
The controllers have a 16-byte FIFO which frees the CPU of excessive software overhead. Interrupt support for all operations
has been included in this architecture. The controllers offer programmable registers for routing interrupts and handshake signals.
The UARTs incorporate an IrDA SIR ENDEC (encoder/decoder). The IrDA physical layer specification is intended to define a
half-duplex, infrared communication link for exchanging data over a distance of up to 1 meter. The full standard includes data
rates up to 115 kbps.
UART0 is the dedicated communication interface to a host PC when the CS7401xx is running in ROM EDM Profile.
Optional
Signals
CS7401xx
DTR0
RTS0
DSR0
Isolation
PC/
and
MODEM
RS232
Driver/ RS232
Receiver
DCD0
CTS0
RI0
TXD0
RXD0
Figure 15. Typical UART Connections
CS7401xx
TXD1
RXD1
GPIO
IrDa
Transceiver
Shutdown
Figure 16. Typical IrDA Connections
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5.4.3 Synchronous Serial Communication Port
The synchronous serial communication port (SSP) provides a convenient method of serial interaction for high-speed communication between similar shift-register-type devices. The SSP is a programmable serial port that is an AMBA® APB intelligent peripheral. The SSP port supports Motorola® SPI™ format, TI® synchronous serial format, and National Semiconductor®
Microwire™ format.
The SSP is a high-speed, synchronous serial, input/output port that allows a serial bit stream of programmed length (4 to 16 bits)
to be shifted into and out of the device at a programmed bit-transfer rate. The SSP is normally used for communication between
the CPU and external peripherals or another microcontroller. Typical applications include interface to external I/O or peripheral
expansion via devices such as nonvolatile memory, display drivers, and digital-to-analog converters.
The SSP is equipped with four communication interface signals. The pins SPICLK0, SPIRXD, and SPITXD are used in all SSP
pin modes. The pin SPCS0 is optional and may be used if the pin is configured.
CS7401xx
SPICS
SPICLK
SPITXD
SSP Compliant
Device
SPIRXD
Figure 17. CS7401xx SSP Port Connections in Master Mode
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5.4.4 LCD Controller/Driver
The LCD controller generates the timing signals that drive a static or multiplexed LCD panel, with support for up to 30 segments
multiplexed with up to four common signals. The LCD controller consists of a control register, 3 display memory registers and 3
buffer registers. The control register defines the mux mode, number of segments, LCD frequency and blinking control, etc. Display memory registers defines the pixels display on or off. Display memory registers are written through buffer registers. To drive
a LCD panel, the corresponding segment and common pins have to be configured as LCD driver enabled.
LCD controller features include:
-
display buffer
blink capability
configurable frame frequency and blink frequency
number of segments programmable
support for four types of LCDs: static, 2-mux, 3-mux, and 4-mux
5.4.4.1 Operation
The number of pixels that an LCD can drive is given by the mux mode times the number of segment pins. The voltage applied
across a particular pixel is the voltage on the COM pin minus the voltage on the SEG pin. If the resulting voltage is above the Von
threshold voltage, the pixel is visible. If the voltage is below the Voff threshold voltage, the pixel will not be visible. In multiplexed
LCD applications, the segment data for the second, third, and fourth column of the display memory are time-multiplexed with
COM1, COM2, and COM3 respectively.
5.4.4.2 LCD Operating Frequencies Example
- When DCLK = 4.096MHz, fLCD is programmable among 1 kHz, 512 Hz, 256 Hz, 128 Hz, 64Hz, 32Hz and 16Hz
- fLCD = 2 * Muxmode * fframe
- When DCLK= 4.096MHz, the blink frequency is programmable among 0.03Hz, 0.06Hz, 0.12Hz, 0.25 Hz, 0.5 Hz, 1 Hz, and
2 Hz.
Table 7. Modes of Operation
Mode
Voltage Across
On Pixel
Voltage Across
Off Pixel
Static
Vdd, -Vdd
0
2-mux
Vdd, -Vdd
Vdd/2, -Vdd/2
3-mux
2Vdd/3, -2Vdd/3
Vdd/3, -Vdd/3
4-mux
2Vdd/3, -2Vdd/3
Vdd/3, -Vdd/3
CS7401xx
SEG<0:29>
LCD Panel
LCDBP <0:3>
LCDLVL <0:3>
LCD
Level
Figure 18. CS7401xx LCD Connections
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5.4.5 Timers and Counters
In CS7401xx, two 32-bit and two 16-bit timers/counters are available and can be used for a wide range of functions:
-
frequency measurement
event counting
interval measurement
pulse generation
delay timing
Watchdog timer
etc.
The timers are driven by a system clock and can be initialized by writing a count value through the APB. Each timer is a down
counter with selectable pre-scale. The pre-scaler allows either the system clock to be used directly, or the clock (frequency) divided by 16 or 256 may be used. This functionality is provided by 0, 4, or 8 stages of pre-scale. Each timer may be configured as
either a free running or a periodic timer. The timer is loaded by writing to the load register and then, if enabled, the timer will begin
counting down. After reaching a zero count, an interrupt will be generated. The interrupt is cleared by writing to the clear register.
If the timer is operating in free-running mode, it continues to count down from its maximum value after reaching a zero count. If
the timer is operating in periodic mode, then the timer will reload from the load register after reaching a zero count and continue
to count down. In this mode the timer will effectively generate a periodic interrupt. The timer mode is selected by a bit in the control
register. In addition to the enable bit in the control register, the two 32-bit timers can also be enabled/disabled by pin inputs TE0
and TE1. One of the 32-bit timers can be used as a watchdog timer.
5.4.6 GPIOs
Pin14 to pin 55 of CS7401xx are functionality-multiplexed input/output pins. They can be configured individually as the input/output interfaces for the embedded peripherals such as LCD driver, SSP port, and UARTs, etc., or as general purpose digital input/outputs (GPIOs). When configured as input GPIOs, these pins also have interrupt generation capability. The interrupt
properties of each GPIO pin are individually configurable.
Because some of the I/O pins have special functionality after reset and by default, the following concerns must be taken
carefully when using CS7401xx.
1) After reset and by default, pin 14 through pin 34, and pin 36 through pin 43 are configured as LCD functionality.
2) After reset and by default, pin 35, and pin 44 through pin 55 are input GPIOs that need to be pulled to a high/low
CMOS level externally.
3) Pin 52 (TXD1) has special factory-test functionality and has to be pulled down at reset.
4) Pin 55 (TXD0) acts as a Flash lock request at reset if it is high, so normally this pin should be pulled down at
reset. Flash lock can be done by software.
5) Pin 50 is the BOOT pin and normally pulled high at reset in order to boot from ROM.
6) Pin 35 is the EM pin and normally pulled up at reset in order to run the application code after the booting from
ROM. A pull-down option (through a button/switch) should also be provided to be able to run the ROM EDM
Profile after reset.
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6. USING A CS7401xx-BASED POWER METER
6.1 Calibration
6.1.1 AC/DC-Offset and Gain Calibration
To ensure power measurement accuracy, a CS7401xx based power meter requires calibration prior to field use. When calibration
completes, the calibration results are saved to Flash memory for subsequent use. Factory-embedded Energy Monitor firmware
provides all the power measurement calibration functions through calibration components. This section discusses the technical
details and steps for calibrating a CS7401xx power meter.
The CS7401xx provides DC-offset and gain calibration that are applied to the voltage and current measurement, and AC-offset
calibration, which is applied to the voltage and current RMS calculations. Since all ADC channels have independent offset and
gain calibration values, users can perform offset and gain calibration on any path independently. In power meter applications with
high-pass filters enabled, DC offset is optional. For most applications, AC offset calibration is not required.
Figure 19 demonstrates the algorithms within the calibration data flow. The value in the APR (Accumulation Period Register),
which is passed during component initialization, determines the number (N) of samples averaged during calibration. DC-offset
and gain calibrations take N + TSETTLE samples. As N is increased, the accuracy of calibration results also increases. Cirrus Logic
recommends setting N and TSETTLE to at least 4000 samples.
Reference
Input
Modulator
And
SINC Filter
AFE
and
Software
Filter(s)
N
+
X
X
÷N
+
N
DC Offset
Gain
Negate
1
X
AC Offset
÷N
Negate
0.6
X
Figure 19. DC/AC-Offset and Gain Data Flow
6.1.1.1 Offset Calibration
During offset calibrations, no line voltage or current should be applied to the power meter.
DC-Offset Calibration
The DC-offset calibration function measures and averages DC values on the specified ADC channel with zero input and returns
the inverse result. This result is passed to the AFE device driver during initialization and added to instantaneous measurements
in subsequent conversions, removing the DC offset. Prior to performing DC offset calibration, the gain of the channel should be
set to 1.0.
AC-Offset Calibration
The AC offset calibration function measures the residual RMS value on the specified ADC channel with zero input and returns
the inverse result. This result is passed to the power utilities component during initialization and added to RMS measurements
in subsequent conversions, removing the AC offset.
6.1.1.2 Gain Calibration
During gain calibration, reference voltage and current must be applied to the power meter, or optionally, apply scaled low-level
signals to the AIN1± and AIN2± pins of the CS7401xx. Either AC or DC low-level reference signals can be used on the AIN1±
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CS7401xx
and AIN2± pins for AC gain calibration. If a DC signal is used, the associated high-pass filter (HPF) must be disabled. Using a
reference that is too large or too small can cause an out-of-range condition and should be avoided. Refer to the 5.1.1 Analog
Channels on page 19 for the maximum input voltages on AIN1± and AIN2± pins.
AC Gain Calibration
Normally the maximum current (Imax) and reference voltage (Un) are used for AC gain calibration and Irms/Vrms will be calibrated to 60% of the full-scale register value.
During AC gain calibration, the RMS level of the applied reference is measured with the preset gain, then divided into 0.6 and the
quotient is returned as the gain calibration value.
DC Gain Calibration
With a DC reference applied, the DC gain calibration function measures and averages DC values on the specified voltage or
current paths and returns the reciprocal result as the gain calibration value. For power/energy measurement applications, DC
gain calibration is not applicable.
6.1.1.3 Calibration Order
1.
DC Offset (if needed)
2.
AC Gain
3.
AC Offset (if needed)
If both AC gain and offset calibrations were performed, it is possible to repeat both to obtain additional
accuracy as AC gain and offset may interact.
6.1.2 Temperature Sensor Calibration
By setting the appropriate bits in the CONFIG_TS register, the internal temperature sensor can be routed to ADC channel 2 or
channel 3. Temperature calculation and calibration functions are provided through the components in Energy Monitor firmware.
Temperature sensor calibration involves the adjustment of two internal parameters: Temperature Gain and Temperature Offset.
These parameters are applied to measured temperature in the following way:
TemperatureReported = [TemperatureRead * TemperatureGain] + TemperatureOffset
By default, Temperature Gain is 1 and Temperature Offset is 0. The temperature calibration process involves the software reporting a temperature and then the user manually calculating the Gain and Offset using the external temperature reference.
6.1.2.1 Temperature Gain Calibration
To calibrate temperature gain, use two temperature points far enough apart to give reasonable accuracy, for example 25°C and
85°C. Divide the actual temperature difference by the software measured difference for the two temperatures, resulting in a gain
correction factor. Save this value as the Temperature Gain and it will be multiplied as shown above.
6.1.2.2 Temperature Offset Calibration
Even though users can perform offset calibration at any temperature, Cirrus Logic recommends a temperature of mid-scale if any
gain error exists. Subtract the software measured temperature from the actual temperature to determine the offset error. Save
this value as the Temperature Offset and it will be added as shown above.
6.1.3 RTC Calibration
RTC calibration requires a very stable and accurate 16.777216 MHz clock source connected to the CS7401xx RCLK pin (51).
The RTC device driver in Energy Monitor firmware provides RTC calibration software functions. Both hardware and software controls the RTC calibration process. The calibration duration is 1, 2, or 4 seconds configurable. After calibration completes, software
stores the calibrated value in the RTCINCR register.
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6.1.4 Power Offset Calibration
Power offset calibration compensates for erroneous power sources resident in the metering system not originating from the power
line. Residual power offsets occur due to crosstalk between current and voltage channels (ADC channels 1, 2, and 3), or due to
ripple within the power meter or the CS7401xx SoC power supply. Positive or negative offsets indicate crosstalk coupling either
in phase or out of phase with the applied voltage input. Power offset calibration is performed without a load connected (current
channel). Power offset calibration is one of the calibration components provided by the Energy Monitor firmware.
6.1.5 Phase Compensation Calibration
Phase compensation calibration is implemented by setting the different time delays on both voltage and current ADC paths.
CS7401xx ADC hardware provides up to 63 samples delay (1 hardware sample delay = 1/MCLK) on voltage channel. Energy
Monitor can provides a software delay of up to 3 samples (1 software sample delay = 1/OWR) on both voltage and current channel.
The phase calibration component calculates the phase shift between the voltage channel and the current channel using wavelet
technology and translates the phase shift into the number of samples of delay needed on the voltage and current ADC paths.
The actual compensated phase shift in degrees is also depended on the line frequency. Table 7 lists the phase ranges and step
sizes that the phase calibration component can calibrate precisely based on different MCLK/OWR and line frequencies.
For the phase shift beyond the ranges in Table 7, the application code needs to calculate phase shift and set the delay by itself
to make the phase compensation. The maximum phase shift ranges that could be compensated are listed in table 8.
Energy Monitor requires the OWR to be 4KHz with BR-filter disabled or 8KHz with BR-filter enabled.
Table 8. Phase Compensation Calibration Range
50 Hz
60 Hz
MCLK/OWR
Range
Step Size
Range
Step Size
256 kHz / 4KHz
-6.75° ~ 8.96°
0.0703°
-8.10° ~ 10.76°
0.0844°
512 kHz / 8KHz
-6.703° ~ 8.854°
0.0352°
-8.019° ~ 10.567°
0.0422°
Table 9. Maximum Phase Compensation Range
50 Hz
60 Hz
MCLK/OWR
Range
Range
256 kHz / 4KHz
-13.5° ~ 17.93°
-16.2° ~ 21.516°
512 kHz / 8KHz
-6.703° ~ 8.854°
-8.019° ~ 10.567°
6.2 Energy Pulse and 1 Hz RTC Output
To support accuracy verification of energy measurement and RTC, the CS7401xx I/O pin 44 can be configured to provide the
EPOUT or CLK1Hz signal.
When configured as EPOUT, pin 44 generates pulses of variable frequency that directly corresponds to the power values measured by the power utilities component in Energy Monitor firmware. EPOUT can output active, reactive, or apparent energy pulses. The energy type, polarity, the maximum pulse rate and pulse width are configurable through the power utilities component in
the Energy Monitor.
When configured as CLK1Hz, pin 44 generates a fixed RTC 1 Hz reference clock. This 1Hz clock can used to measure or verify
the accuracy of the CS7401xx RTC.
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6.3 Typical Application Circuit
Figure 20 below show a typical CS7401xx based single phase power meter application circuit with the AIN3 channel used for
tampering detection.
N
L
MBR0520L
3.6 V
0.1uF
Power
Supply
MBR0520L
10uF
3.0 V
VH
VBAT
VSC
AIN1P
10uH
CS7401xx
R 1 R2
VD
CV-
R V-
Ferrite
CV+
2 uF
VA
AIN1N
1uF
32.768 kHz
XOUT
VREF
10uF
XIN
VBG
I-
½ RBurden
C I-
½ RBurden
CI+
AIN2P
RXD0
TXD0
AIN2N
RXD1
TXD1
AIN3N
SPICS
SPIRXD
SPITXD
RI+
RS-232
PC/
Modem
Infrared/
Optical
Interface
CT
Transceiver
R
ISOLATION
(Optional)
1uF
C IR Shunt
RI+
CI+
ISOLATION
(Optional)
R ISerial
Device
SPICLK
AIN3P
VH
LCDBP0…3
Push Button
LOAD
EM
SEG0…SEG20
LCD Display
VH
LCDLVL0…
...LCDLVL3
BOOT
LCD
Level
EPOUT
RESET
GNDA
GNDD
Figure 20. Typical Connection Diagram (Single-phase, 2-wire, direct connection power meter)
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7. PACKAGE INFORMATION
64L LQFP PACKAGE DRAWING
E
E1
D D1
1
e
B
A
∝
A1
L
DIM
A
A1
B
D
D1
E
E1
e*
L
MIN
--0.002
0.007
0.461
0.390
0.461
0.390
0.016
0.018
0.000°
∝
* Nominal pin pitch is 0.50 mm
INCHES
NOM
0.55
0.004
0.008
0.472 BSC
0.393 BSC
0.472 BSC
0.393 BSC
0.020 BSC
0.024
4°
MAX
0.063
0.006
0.011
0.484
0.398
0.484
0.398
0.024
0.030
7.000°
MIN
--0.05
0.17
11.70
9.90
11.70
9.90
0.40
0.45
0.00°
MILLIMETERS
NOM
1.40
0.10
0.20
12.0 BSC
10.0 BSC
12.0 BSC
10.0 BSC
0.50 BSC
0.60
4°
MAX
1.60
0.15
0.27
12.30
10.10
12.30
10.10
0.60
0.75
7.00°
Controlling dimension is mm.
JEDEC Designation: MS026
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8. ORDERING INFORMATION
Model
Package
Temperature
64-pin LQFP
-40 to +85 °C
CS740111-IQZ (32 kB Flash)
CS740121-IQZ (64 kB Flash)
CS740131-IQZ (128 kB Flash)
9. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number
Peak Reflow Temp
MSL Rating*
Max Floor Life
250 °C
3
7 Days
CS740111-IQZ
CS740121-IQZ
CS740131-IQZ
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
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REVISION HISTORY
Revision
Date
A1
October 2007
PP1
April 2008
Initial Preliminary Release
PP2
April 2008
Preliminary Release
PP3
August 2008
Initial Public Release
F1
August 2008
Final Release
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CS7401xx
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives
consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY, SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR
CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO
FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
IrDA is a registered trademark of Infrared Data Association Corporation.
SPI is a trademark of Motorola, Inc. Motorola is a registered trademark of Motorola, Inc.
ARM, AMBA, Primecell, and Thumb are registered trademarks of ARM Limited. ARM7, ARM7TDMI, TDMI, and EmbeddedICE are trademarks of ARM Limited.
Microwire is a trademark of National Semiconductor Corporation.
TI is a registered trademark of Texas Instruments Incorporated.
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