PCI,DMA,Interrupt
ForUMassLowell16.480/552
Prof.YanLuo
Some slides are adopted from Brey’s book. All rights are with the author and publisher.
PeripheralComponent
Interconnect
15–2 PERIPHERALCOMPONENT
INTERCONNECT(PCI)BUS
• PCI(peripheralcomponentinterconnect)
isvirtuallytheonlybusfoundinnewsystems.
– ISAstillexistsbyspecialorderforoldercards
• PCIhasreplacedtheVESAlocalbus.
• PCIhasplug-and-playcharacteristicsand
abilitytofunctionwitha64-bitdatabus.
• APCIinterfacecontainsregisters,locatedina
smallmemorydevicecontaininginformation
abouttheboard.
– thisallowsPCtoautomaticallyconfigurethecard
– thisprovidesplug-and-playcharacteristicstotheISA
bus,oranyotherbus
• Calledplug-and-play(PnP),itisthereasonPCIhas
becomesopopular.
• Figure15–6showsthesystemstructure
forthePCIbusinaPCsystem.
Figure15–6 SystemblockdiagramforthePCthatcontainsaPCIbus.
– the microprocessor connects
to the PCI bus through an IC
called a PCI bridge
– virtually any
processor can
interface to PCI
with a bridge
– The resident
local bus is
often called a
front side bus
AnotherViewofaTypicalPCI
system
Figure source: The Linux Device Driver, 3rd Ed.
6
ThePCIBusPin-Out
• PCIfunctionswitha32- or64-bitdatabus
andafull32-bitaddressbus.
– addressanddatabuses,labeledAD0–AD63 are
multiplexedtoreducesizeoftheedgeconnector
• A32-bitcardhasconnections1through62,the
64-bitcardhasall94connections.
• The64-bitcardcanaccommodatea64-bitaddress
ifrequiredatsomefuturepoint.
• Figure15–7showsthePCIbuspin-out.
Figure15–7 Thepin-outofthePCIbus.
– PCI is most often used for I./O
interface to the microprocessor
– memory could be interfaced, but
with a Pentium, would operate
at 33 MHz, half the speed of the
Pentium resident local
– PCI 2.1 operates at 66 MHz, and
33 MHz for older interface cards
– P4 systems use 200 MHz bus
speed (often listed as 800 MHz)
ThePCIAddress/DataConnections
• ThePCIaddressappearsonAD0–AD31 and
ismultiplexedwithdata.
– somesystemshavea64-bitdatabususing
AD32–AD63 fordatatransferonly
– thesepinscanbeusedforextendingthe
addressto64bits
• Fig15–8showsthePCIbustimingdiagram
– whichshowstheaddressmultiplexedwithdataand
controlsignalsusedformultiplexing
Figure15–8 ThebasicburstmodetimingforthePCIbussystem.Notethatthis
transferseitherfour32-bitnumbers(32-bitPCI)orfour64-bitnumbers(64-bitPCI).
ConfigurationSpace
• PCIcontainsa256-bytememorytoallow
thePCtointerrogatethePCIinterface.
– thisfeatureallowsthesystemtoautomatically
configureitselfforthePCIplug-board
– Microsoftcallsthisplug-and-play(PnP)
• Thefirst64bytescontaininformationaboutthe
PCIinterface.
• Thefirst32-bitdoubleword containstheunit
IDcodeandthevendorIDcode.
• Fig15–9showstheconfigurationmemory.
Figure15–9 ThecontentsoftheconfigurationmemoryonaPCIexpansionboard.
AmoredetailedviewofthePCI
configurationspace(first64B)
Figure source: The Linux Device Driver, 3rd Ed. (fig. 12-2)
13
• UnitIDcodeisa16-bitnumber(D31–D16).
– anumberbetween0000H&FFFEHto
identifytheunitifitisinstalled
– FFFFHiftheunitisnotinstalled
• TheclasscodeisfoundinbitsD31–D16 of
configurationmemoryatlocation08H.
– classcodesidentifythePCIinterfaceclass
– bitsD15–D0 aredefinedbythemanufacturer
• CurrentclasscodesarelistedinTable15–5and
areassignedbythePCISIG.
WhatPCIdevicesDoWeHave?A
LinuxView
• Demos(/sbin/lspci -s02:00-x–vv)
– lspci command
– devicenumber
– detailedinfoaboutaPCIdevice
– configurationspaceofthePCIdevice
• vendor,class
• baseaddress
15
• Thebaseaddressspaceconsistsofabaseaddress
forthememory,asecondfortheI/Ospace,anda
thirdfortheexpansionROM.
• ThoughIntelmicroprocessorsusea16-bitI/O
address,thereisroomforexpandingto32bits
addressing.
• ThestatuswordisloadedinbitsD31–D16 of
location04Hoftheconfigurationmemory.
– thecommandisatbitsD15–D0 of04H
• Fig15–10showsthestatus&commandregisters.
Figure15–10 Thecontentsofthestatusandcontrolwordsintheconfiguration
memory.
BIOSforPCI
• MostmodernPCshaveanextensiontothenormal
systemBIOSthatsupportsPCIbus.
– thesesystemsaccessPCIatinterruptvector1AH
• Table15–6listsfunctionsavailablethroughtheDOSINT
1AHinstructionwithAH=0B1HforthePCI.
– Example15–5(nextslide)showshowtheBIOSisused
todeterminewhetherthePCIbusextensionavailable.
• TheBIOSand/orOS(e.g.Linux)performconfiguration
transactionswitheveryPCIdevice
– allocatesafespaceforeachaddressregionitoffers
– mapmemoryorI/Oregionstotheprocessor’saddressspace
Example15-5:BIOSPCIFunctions
.MODEL SMALL
.DATA
MES1 DB “PCI BUS IS PRESENT$”
MES2 DB “PCI BUS IS NOT FOUND$”
.CODE
.STARTUP
MOV AH, 0B1H
; access PCI BIOS
MOV AL, 1
INT 1AH
MOV DX, OFFSET MSE2
.IF CARRY?
; if PCI is present
MOV DX, OFFSET MSE1
.ENDIF
MOV AH, 9
; display MES1 or MES2
INT 21H
.EXIT
END
19
PClInterface
• IfaPCIinterfaceisconstructed,aPCIcontrolleris
oftenusedbecauseofthecomplexityofthis
interface.
• ThebasicstructureofthePCIinterfaceis
illustratedinFigure15–11.
– thediagramillustratesrequiredcomponents
forafunctioningPCIinterface
• Registers,ParityBlock,Initiator,Target,and
VendorIDEPROMarerequiredcomponentsofany
PCIinterface.
Figure15–11 TheblockdiagramofthePCIinterface.
PCIExpressBus
• ThePCIExpresstransfersdatainserialat
2.5GHztolegacyPCIapplications,
– 250MBps to8GBps forPCIExpressinterfaces
– standardPCIdeliversdataatabout133MBps
• EachserialconnectiononthePCIExpressbusis
calledalane.
– e.g.slotsonthemainboardaresinglelaneslots
withatotaltransferspeedof1GBps (4lanes)
• E.g.aPCIExpressvideocardconnectorhas16
laneswithatransferspeedof4GBps.
• Thestandardallowsupto32lanes.
– atpresentthewidestisthe16lanesvideocard
• Mostmainboardscontainfoursinglelaneslots
forperipheralsandone16laneslotforthevideo
card.
– afewnewerboardscontaintwo16laneslots
• PCIExpress2buswasreleasedinlate2007.
– transferspeedfrom250MBpsto500MBps,
twicethatofthePCIExpress
• PCIisreplacingmostcurrentvideocardsonthe
AGPportwiththePCIExpressbus.
• Thistechnologyallowsmanufacturerstouseless
spaceonthemainboardandreducethecostof
manufacturingamainboard.
– connectorsaresmaller,whichalsoreducescost
• SoftwareusedwithPCIExpressremainsthesame
asusedwiththePCIbus.
– newprogramsarenotneededtodevelopdrivers
• Theconnectorisa36-pinconnectorasillustrated
inFigure15–12.
– the pin-out for the single lane connector,
appears in Table 15–7
– signaling on the PCI Express bus uses 3.3 V
with differential signals degrees out of phase
– the lane is constructed from a pair of data pipes,
one for input data and one for output data
Figure15–12 ThesinglelanePCIExpressconnector.
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