a
PRODUCT DESCRIPTION
The AD8002 is a dual, low-power, high-speed amplifier designed
to operate on ±5 V supplies. The AD8002 features unique transimpedance linearization circuitry. This allows it to drive video
loads with excellent differential gain and phase performance on
only 50 mW of power per amplifier. The AD8002 is a current
feedback amplifier and features gain flatness of 0.1 dB to 60 MHz
while offering differential gain and phase error of 0.01% and
0.02°. This makes the AD8002 ideal for professional video
electronics such as cameras and video switchers. Additionally,
the AD8002’s low distortion and fast settling make it ideal for
buffer high-speed A-to-D converters.
The AD8002 offers low power of 5.5 mA/amplifier max (VS =
± 5 V) and can run on a single 12 V power supply, while capable
of delivering over 70 mA of load current. It is offered in an
8-lead plastic DIP, SOIC, and µSOIC package. These features
make this amplifier ideal for portable and battery-powered
applications where size and power are critical.
OUT1 1
8 V+
–IN1 2
7 OUT2
+IN1 3
6 –IN2
V– 4
5 +IN2
AD8002
The outstanding bandwidth of 600 MHz along with 1200 V/µs
of slew rate make the AD8002 useful in many general purpose
high speed applications where dual power supplies of up to ± 6 V
and single supplies from 6 V to 12 V are needed. The AD8002 is
available in the industrial temperature range of –40°C to +85°C.
1
SIDE 1
G = +2
RL = 100⍀
VIN = 50mV
SIDE 2
0
–1
–2
–3
0.1
0
SIDE 1
–4
–5
–0.1
SIDE 2
–0.2
–6
–0.3
–7
–0.4
–8
–0.5
1M
NORMALIZED FREQUENCY RESPONSE – dB
APPLICATIONS
A-to-D Driver
Video Line Driver
Differential Line Driver
Professional Cameras
Video Switchers
Special Effects
RF Receivers
FUNCTIONAL BLOCK DIAGRAM
8-Lead Plastic DIP, SOIC, and ␮SOIC
NORMALIZED FLATNESS – dB
FEATURES
Excellent Video Specifications (RL = 150 ⍀, G = +2)
Gain Flatness 0.1 dB to 60 MHz
0.01% Differential Gain Error
0.02ⴗ Differential Phase Error
Low Power
5.5 mA/Amp Max Power Supply Current (55 mW)
High Speed and Fast Settling
600 MHz, –3 dB Bandwidth (G = +1)
500 MHz, –3 dB Bandwidth (G = +2)
1200 V/␮s Slew Rate
16 ns Settling Time to 0.1%
Low Distortion
–65 dBc THD, f C = 5 MHz
33 dBm Third Order Intercept, F1 = 10 MHz
–66 dB SFDR, f = 5 MHz
–60 dB Crosstalk, f = 5 MHz
High Output Drive
Over 70 mA Output Current
Drives Up to Eight Back-Terminated 75 ⍀ Loads
(Four Loads/Side) While Maintaining Good
Differential Gain/Phase Performance (0.01%/0.17ⴗ)
Available in 8-Lead Plastic DIP, SOIC and ␮SOIC Packages
Dual 600 MHz, 50 mW
Current Feedback Amplifier
AD8002
–9
1G
10M
100M
FREQUENCY – Hz
Figure 1. Frequency Response and Flatness, G = +2
SIDE 1
G = +2
1V STEP
SIDE 2
200mV
5ns
Figure 2. 1 V Step Response, G = +1
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
Powered by TCPDF (www.tcpdf.org)
IMPORTANT LINKS for the AD8002*
Last content update 08/18/2013 12:36 am
DOCUMENTATION
DESIGN COLLABORATION COMMUNITY
AN-692: Universal Precision Op Amp Evaluation Board
AN-649: Using the Analog Devices Active Filter Design Tool
AN-356: User's Guide to Applying and Measuring Operational
Amplifier Specifications
MT-057: High Speed Current Feedback Op Amps
MT-051: Current Feedback Op Amp Noise Considerations
MT-034: Current Feedback (CFB) Op Amps
MT-059: Compensating for the Effects of Input Capacitance on VFB
and CFB Op Amps Used in Current-to-Voltage Converters
A Stress-Free Method for Choosing High-Speed Op Amps
UG-129: Evaluation Board User Guide
UG-128: Universal Evaluation Board for Dual High Speed Op Amps in
SOIC Packages
Current Feedback Amplifiers Part 1: Ask The Applications Engineer-22
Current Feedback Amplifiers Part 2: Ask The Applications Engineer-23
Two-Stage Current-Feedback Amplifier
PARAMETRIC SELECTION TABLES
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Quality and Reliability
Lead(Pb)-Free Data
SAMPLE & BUY
DESIGN TOOLS, MODELS, DRIVERS & SOFTWARE
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AD8002
View Price & Packaging
Request Evaluation Board
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EVALUATION KITS & SYMBOLS & FOOTPRINTS
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purchasing
Symbols and Footprints
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet.
Note: Dynamic changes to the content on this page (labeled 'Important Links') does not
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This content may be frequently modified.
AD8002–SPECIFICATIONS (@ T = 25ⴗC, V = ⴞ5 V, R = 100 ⍀, R
A
S
L
1
C
= 75 ⍀, unless otherwise noted.)
Model
Conditions
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth,
N Package
R Package
RM Package
Min
AD8002A
Typ
Max
Unit
G = +2, RF = 750 Ω
G = +1, RF = 1.21 kΩ
G = +2, RF = 681 Ω
G = +1, RF = 953 Ω
G = +2, RF = 681 Ω
G = +1, RF = 1 kΩ
500
600
500
600
500
600
MHz
MHz
MHz
MHz
MHz
MHz
G = +2, R F = 750 Ω
G = +2, R F = 681 Ω
G = +2, R F = 681 Ω
G = +2, VO = 2 V Step
G = –1, VO = 2 V Step
G = +2, VO = 2 V Step
G = +2, VO = 2 V Step, RF = 750 Ω
60
90
60
700
1200
16
2.4
MHz
MHz
MHz
V/µs
V/µs
ns
ns
fC = 5 MHz, VO = 2 V p-p
G = +2, RL = 100 Ω
f = 5 MHz, G = +2
f = 10 kHz, RC = 0 Ω
f = 10 kHz, +In
–In
NTSC, G = +2, R L = 150 Ω
NTSC, G = +2, R L = 150 Ω
f = 10 MHz
f = 10 MHz
f = 5 MHz
–65
dBc
–60
2.0
2.0
18
0.01
0.02
33
14
–66
dB
nV/√Hz
pA/√Hz
pA/√Hz
%
Degree
dBm
dBm
dB
Bandwidth for 0.1 dB Flatness
N Package
R Package
RM Package
Slew Rate
Settling Time to 0.1%
Rise and Fall Time
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion
Crosstalk, Output to Output
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
Third Order Intercept
1 dB Gain Compression
SFDR
DC PERFORMANCE
Input Offset Voltage
2.0
2.0
10
5.0
TMIN –TMAX
Offset Drift
–Input Bias Current
TMIN –TMAX
+Input Bias Current
Open Loop Transresistance
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
Offset Voltage
–Input Current
+Input Current
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current2
Short Circuit Current2
POWER SUPPLY
Operating Range
Quiescent Current/Both Amplifiers
Power Supply Rejection Ratio
–Input Current
+Input Current
3.0
TMIN –TMAX
VO = ± 2.5 V
TMIN –TMAX
250
175
+Input
–Input
+Input
6
9
25
35
6.0
10
900
10
50
1.5
3.2
VCM = ± 2.5 V
VCM = ± 2.5 V, TMIN –TMAX
VCM = ± 2.5 V, TMIN –TMAX
49
R L = 150 Ω
2.7
85
54
0.3
0.2
60
49
MΩ
Ω
pF
±V
1.0
0.9
10.0
75
56
0.5
0.1
dB
µA/V
µA/V
±V
mA
mA
3.1
70
110
± 3.0
TMIN –TMAX
+VS = +4 V to +6 V, –VS = –5 V
–VS = – 4 V to – 6 V, +VS = +5 V
TMIN –TMAX
TMIN –TMAX
mV
mV
µV/°C
±µA
±µA
±µA
±µA
kΩ
kΩ
± 6.0
11.5
2.5
0.5
V
mA
dB
dB
µA/V
µA/V
NOTES
1
RC is recommended to reduce peaking and minimize input reflections at frequencies above 300 MHz. However, R C is not required.
2
Output current is limited by the maximum power dissipation in the package. See the power derating curves.
Specifications subject to change without notice.
–2–
REV. D
AD8002
ABSOLUTE MAXIMUM RATINGS 1
MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 V
Internal Power Dissipation2
Plastic DIP Package (N) . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . . . 0.9 W
µSOIC Package (RM) . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 W
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ± VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 1.2 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range N, R, RM . . . . . –65°C to +125°C
Operating Temperature Range (A Grade) . . . – 40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
The maximum power that can be safely dissipated by the
AD8002 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150°C. Exceeding this
limit temporarily may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of 175°C for an extended
period can result in device failure.
2.0
8-LEAD PLASTIC-DIP PACKAGE
MAXIMUM POWER DISSIPATION – W
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air:
8-Lead Plastic DIP Package: θJA = 90°C/W
8-Lead SOIC Package: θJA = 155°C/W
8-Lead µSOIC Package: θJA = 200°C/W
While the AD8002 is internally short circuit protected, this
may not be sufficient to guarantee that the maximum junction
temperature (150°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the maximum
power derating curves.
8-LEAD SOIC PACKAGE
1.5
TJ = 150ⴗC
1.0
0.5
8-LEAD ␮SOIC
PACKAGE
0
–50 –40 –30 –20 –10
0
10
20
30 40
50
60
70
80 90
AMBIENT TEMPERATURE – ⴗC
Figure 3. Plot of Maximum Power Dissipation vs.
Temperature
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
Brand Code
AD8002AN
AD8002AR
AD8002AR-REEL
AD8002AR-REEL7
AD8002ARM
AD8002ARM-REEL
AD8002ARM-REEL7
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead PDIP
8-Lead SOIC
8-Lead SOIC 13" REEL
8-Lead SOIC 7" REEL
8-Lead µSOIC
8-Lead µSOIC 13" REEL
8-Lead µSOIC 7" REEL
N-8
SO-8
SO-8
SO-8
RM-8
RM-8
RM-8
Standard
Standard
Standard
Standard
HFA
HFA
HFA
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8002 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. D
–3–
WARNING!
ESD SENSITIVE DEVICE
AD8002–Typical Performance Characteristics
750⍀
953⍀
10␮F
+5V
10␮F
+5V
0.1␮F
0.1␮F
750⍀
AD8002
AD8002
75⍀
PULSE
GENERATOR
50⍀
TR/TF = 250ps
75⍀
0.1␮F
VIN
PULSE
GENERATOR
10␮F
50⍀
TR/TF = 250ps
–5V
TPC 1. Test Circuit , Gain = +1
SIDE 1
0.1␮F
VIN
RL = 100⍀
RL = 100⍀
10␮F
–5V
TPC 4. Test Circuit, Gain = +2
SIDE 1
G = +1
100mV STEP
G = +2
100mV STEP
SIDE 2
SIDE 2
TPC 2. 100 mV Step Response, G = +1
SIDE 1
5ns
20mV
5ns
20mV
TPC 5. 100 mV Step Response, G = +2
G = +1
1V STEP
SIDE 1
G = +2
1V STEP
SIDE 2
SIDE 2
200mV
5ns
20mV
TPC 3. 1 V Step Response, G = +1
5ns
TPC 6. 1 V Step Response, G = +2
–4–
REV. D
AD8002
–20
SIDE 2
–2
–3
0.1
SIDE 1
0
–0.1
–4
–5
75⍀
50⍀
–0.2
–1
50⍀
SIDE 2
–6
–7
–0.3
RF
681⍀
681⍀
–0.4
–0.5
1M
–8
–30
–40
–50
CROSSTALK – dB
NORMALIZED FLATNESS – dB
G = +2
RL = 100⍀
VIN = 50mV
0
NORMALIZED FREQUENCY RESPONSE – dB
1
SIDE 1
OUTPUT SIDE 1
–60
OUTPUT SIDE 2
–70
–80
–90
–100
–110
–120
100k
–9
1G
10M
100M
FREQUENCY – Hz
VIN = –4dBV
RL = 100⍀
VS = ⴞ5.0V
G = +2
RF = 750⍀
TPC 7. Frequency Response and Flatness, G = +2
1M
10M
FREQUENCY – Hz
100M
TPC 10. Crosstalk (Output-to-Output) vs. Frequency
–50
G = +2
RL = 100⍀
DISTORTION – dBc
–60
G=+2
RF = 750⍀
RC = 75⍀
RL = 100⍀
SIDE 1
–70
2ND HARMONIC
–80
3RD HARMONIC
SIDE 2
–90
–100
5ns
–110
10k
100k
1M
FREQUENCY – Hz
10M
100M
NOTES: SIDE 1: VIN = 0V; 8mV/div RTO
SIDE 2: 1V STEP RTO; 400mV/div
TPC 8. Distortion vs. Frequency, G = +2, RL = 100 Ω
TPC 11. Pulse Crosstalk, Worst Case, 1 V Step
–60
DIFF GAIN – %
–80
2 BACK-TERMINATED
LOADS (75⍀)
0.01
0.00
–0.01
–0.02
2ND HARMONIC
3RD HARMONIC
–100
–110
–120
10k
100k
1M
FREQUENCY – Hz
10M
100M
TPC 9. Distortion vs. Frequency, G = +2, RL = 1 kΩ
REV. D
1 BACK-TERMINATED
LOAD (150⍀)
G = +2
RF = 750⍀
NTSC
–90
DIFF PHASE – Degrees
DISTORTION – dBc
–70
0.02
G = +2
RL = 1k⍀
VOUT = 2V p-p
2 BACK-TERMINATED
LOADS (75⍀)
0.08
0.06
1 BACK-TERMINATED
LOAD (150⍀)
0.04
0.02
0.00
1
2
3
4
5
6
IRE
7
8
9
10
11
TPC 12. Differential Gain and Differential Phase
(per Amplifier)
–5–
2
1
VIN = 50mV
G = +1
RF = 953⍀
RL = 100⍀
SIDE 1
0
INPUT LEVEL – dBV
GAIN – dB
SIDE 2
–1
–2
75⍀
–3
50⍀
50⍀
–4
6
–3
3
–6
0
–9
–3
–12
–6
–15
–9
–18
–21
953⍀
–5
G = +2
RF = 681⍀
VS = ⴞ5V
RL = 100⍀
–12
–15
–18
–24
–6
1M
10M
100M
FREQUENCY – Hz
–27
1M
1G
TPC 13. Frequency Response, G = +1
9
RL = 100⍀
G = +1
RF = 1.21k⍀
6
G = +1
RL = 100⍀
VOUT = 2V p-p
INPUT/OUTPUT LEVEL – dBV
–50
–21
500M
10M
100M
FREQUENCY – Hz
TPC 16. Large Signal Frequency Response, G = +2
–40
DISTORTION – dBc
0
OUTPUT LEVEL – dBV
AD8002
–60
–70
2ND HARMONIC
–80
3RD HARMONIC
–90
3
0
–3
–6
75⍀
50⍀
–9
50⍀
–12
–15
1.21k⍀
–18
–100
10k
100k
1M
FREQUENCY – Hz
10M
–27
1M
100M
TPC 14. Distortion vs. Frequency, G = +1, RL = 100 Ω
45
G = +1
RL = 1k⍀
40
VS = ⴞ5V
RL = 100⍀
35
–60
30
GAIN – dB
DISTORTION – dBc
500M
TPC 17. Large Signal Frequency Response, G = +1
–40
–50
10M
100M
FREQUENCY – Hz
–70
2ND HARMONIC
3RD HARMONIC
–80
25
G = +100
RF = 1000⍀
20
15
G = +10
RF = 499⍀
10
–90
5
–100
–110
10k
0
100k
1M
FREQUENCY – Hz
10M
–5
1M
100M
TPC 15. Distortion vs. Frequency, G = +1, RL = 1 kΩ
10M
100M
FREQUENCY – Hz
1G
TPC 18. Frequency Response, G = +10, G = +100
–6–
REV. D
AD8002
OUTPUT
G = +2
2V STEP
RF = 750⍀
RC = 75⍀
RL = 100⍀
G = +2
2V STEP
RF = 750⍀
RC = 75⍀
ERROR,
(0.05%/DIV)
ERROR,
(0.05%/DIV)
OUTPUT
INPUT
INPUT
400mV
10ns
400mV
TPC 19. Short-Term Settling Time
TPC 22. Long-Term Settling Time
4
3.4
DEVICE #1
3.3
3
OUTPUT SWING – Volts
3.2
INPUT OFFSET VOLTAGE – mV
RL = 150⍀
VS = ⴞ5V
3.1
+VOUT
|–VOUT|
3.0
2.9
RL = 50⍀
2.8
VS = ⴞ5V
2.7
+VOUT
2.5
–55
–35
–15
5
1
DEVICE #2
0
DEVICE #3
–1
–2
|–VOUT|
2.6
2
25
45
65
85
105
–3
–55
125
–35
JUNCTION TEMPERATURE – ⴗC
–15
5
25
45
65
85
105
125
JUNCTION TEMPERATURE – ⴗC
TPC 20. Output Swing vs. Temperature
TPC 23. Input Offset Voltage vs. Temperature
11.5
5
4
TOTAL SUPPLY CURRENT – mA
INPUT BIAS CURRENT – ␮A
–IN
3
2
1
0
–1
+IN
–2
–3
–55
–35
–15
5
25
45
65
85
105
10.5
VS = ⴞ5V
10.0
9.5
9.0
–55
125
–35
–15
5
25
45
65
85
105
125
JUNCTION TEMPERATURE – ⴗC
JUNCTION TEMPERATURE – ⴗC
TPC 21. Input Bias Current vs. Temperature
REV. D
11.0
TPC 24. Total Supply Current vs. Temperature
–7–
AD8002
120
100
110
105
10
100
|SINK ISC|
RESISTANCE – ⍀
SOURCE ISC
95
90
85
1
RbT = 50⍀
RF = 750⍀
RC = 75⍀
VS = ⴞ5.0V
POWER = 0dBm
(223.6mVrms)
G = +2
RbT = 0⍀
0.1
80
75
0.01
70
–55
–35
–15
5
25
45
65
85
105
125
10k
100k
1M
10M
FREQUENCY – Hz
JUNCTION TEMPERATURE – ⴗC
100M
1G
TPC 28. Output Resistance vs. Frequency
TPC 25. Short Circuit Current vs. Temperature
100
100
1
–3dB BANDWIDTH
0
SIDE 1
SIDE 2
INVERTING CURRENT VS = ⴞ5V
10
10
NONINVERTING CURRENT VS = ⴞ5V
NOISE CURRENT – pA/ Hz
NOISE VOLTAGE – nV/ Hz
0.2
–1
–2
0.1
SIDE 1
0.1dB FLATNESS
0
–3
–4
–0.1
–0.2
–0.3
VOLTAGE NOISE VS = ⴞ5V
VS = ⴞ5V
VIN = 50mV
G = –1
RL = 100⍀
RF = 549⍀
–5
SIDE 2
–6
OUTPUT VOLTAGE – dB
SHORT CIRCUIT CURRENT – mA
115
–7
–8
1
100k
1
100
10
1k
FREQUENCY – Hz
10k
1M
TPC 26. Noise vs. Frequency
–9
1G
10M
100M
FREQUENCY – Hz
TPC 29. –3 dB Bandwidth vs. Frequency, G = –1
–48
–50.0
–52.5
–49
–PSRR
–55.0
–50
–57.5
PSRR – dB
CMRR – dB
–CMRR
–51
+CMRR
–52
–53
2V SPAN
–60.0
CURVES ARE FOR WORSTCASE CONDITION WHERE
ONE SUPPLY IS VARIED
WHILE THE OTHER IS
HELD CONSTANT.
–62.5
–65.0
–67.5
–54
–70.0
+PSRR
–55
–56
–55
–72.5
–35
–15
5
25
45
65
85
JUNCTION TEMPERATURE – ⴗC
105
–75.0
–55
125
–35
–15
5
25
45
65
85
105
125
JUNCTION TEMPERATURE – ⴗC
TPC 30. PSRR vs. Temperature
TPC 27. CMRR vs. Temperature
–8–
REV. D
AD8002
0
0
VIN
–10
604⍀
57.6⍀
VIN = 200mV
G = +2
–20
50⍀
–30
154⍀
154⍀
–30
PSRR – dB
CMRR – dB
–20
–10
604⍀
0.1␮F
–5V
–40
SIDE 2
VS = ⴞ5.0V
RL = 100⍀
VIN = 200mV
10M
100M
FREQUENCY – Hz
–80
–90
30k 100k
1G
1M
100M
10M
FREQUENCY – Hz
TPC 34. PSRR vs. Frequency
TPC 31. CMRR vs. Frequency
SIDE 1
+PSRR
–70
–60
1M
–50
–60
SIDE 1
–50
–PSRR
–40
G = –1
RF = 576⍀
RG = 576⍀
RC = 50⍀
SIDE 1
G = –2
2V STEP
RF = 549⍀
SIDE 2
SIDE 2
400mV
5ns
400mV
TPC 32. 2 V Step Response, G = –1
5ns
TPC 35. 2 V Step Response, G = –2
576⍀
549⍀
576⍀
274⍀
50⍀
50⍀
54.9⍀
61.9⍀
50⍀
50⍀
SIDE 1
SIDE 1
SIDE 2
SIDE 2
G = –1
100mV STEP
RF = 549⍀
G = –1
RF = 576⍀
RG = 576⍀
RC = 50⍀
RL = 100⍀
20mV
20mV
5ns
TPC 36. 100 mV Step Response, G = –2
TPC 33. 100 mV Step Response, G = –1
REV. D
5ns
–9–
500M
AD8002
THEORY OF OPERATION
Printed Circuit Board Layout Considerations
A very simple analysis can put the operation of the AD8002, a
current feedback amplifier, in familiar terms. Being a current
feedback amplifier, the AD8002’s open-loop behavior is expressed
as transimpedance, ∆VO/∆I–IN, or TZ. The open-loop transimpedance behaves just as the open-loop voltage gain of a voltage
feedback amplifier, that is, it has a large dc value and decreases
at roughly 6 dB/octave in frequency.
As expected for a wideband amplifier, PC board parasitics can
affect the overall closed-loop performance. Of concern are
stray capacitances at the output and the inverting input nodes. If
a ground plane is to be used on the same side of the board as
the signal traces, a space (5 mm min) should be left around the
signal lines to minimize coupling. Additionally, signal lines
connecting the feedback and gain resistors should be short
enough so that their associated inductance does not cause high
frequency gain errors. Line lengths on the order of less than
5 mm are recommended. If long runs of coaxial cable are being
driven, dispersion and loss must be considered.
Since the RIN is proportional to 1/gm, the equivalent voltage
gain is just TZ × gm, where the gm in question is the transconductance of the input stage. This results in a low open-loop
input impedance at the inverting input, a now familiar result.
Using this amplifier as a follower with gain, Figure 4, basic
analysis yields the following result.
Power Supply Bypassing
Adequate power supply bypassing can be critical when optimizing the performance of a high-frequency circuit. Inductance in
the power supply leads can form resonant circuits that produce
peaking in the amplifier’s response. In addition, if large current
transients must be delivered to the load, bypass capacitors
(typically greater than 1 µF) will be required to provide the
best settling time and lowest distortion. A parallel combination of 4.7 µF and 0.1 µF is recommended. Some brands of
electrolytic capacitors will require a small series damping resistor ≈4.7 Ω for optimum results.
TZ (S )
VO
=G×
VIN
TZ (S ) + G × RIN + R1
G = 1+
R1
RIN = 1 / g m ≈ 50 Ω
R2
R1
R2
DC Errors and Noise
Recognizing that G × RIN << R1 for low gains, it can be seen to
the first order that bandwidth for this amplifier is independent
of gain (G).
Considering that additional poles contribute excess phase at
high frequencies, there is a minimum feedback resistance below
which peaking or oscillation may result. This fact is used to
determine the optimum feedback resistance, R F. In practice
parasitic capacitance at the inverting input terminal will also add
phase in the feedback loop, so picking an optimum value for R F
can be difficult.
There are three major noise and offset terms to consider in a
current feedback amplifier. For offset errors, refer to the equation below. For noise error, the terms are root-sum-squared to
give a net output error. In the circuit shown in Figure 5 they
are input offset (VIO), which appears at the output multiplied by
the noise gain of the circuit (1 + R F/R I), noninverting input
current (IBN × RN), also multiplied by the noise gain, and the
inverting input current, which, when divided between RF and RI
and subsequently multiplied by the noise gain, always appears
at the output as IBN × RF. The input voltage noise of the AD8002
is a low 2 nV/√Hz. At low gains, though, the inverting input
current noise times RF is the dominant noise source. Careful
layout and device matching contribute to better offset and
drift specifications for the AD8002 compared to many other
current feedback amplifiers. The typical performance curves in
conjunction with the equations below can be used to predict the
performance of the AD8002 in any application.
Achieving and maintaining gain flatness of better than 0.1 dB at
frequencies above 10 MHz requires careful consideration of
several issues.


R 
R 
VOUT = VIO × 1 + F  ± I BN × RN × 1 + F  ± I BI × RF


RI 
RI 
RIN
VOUT
VIN
Figure 4.
Choice of Feedback and Gain Resistors
RF
The fine scale gain flatness will, to some extent, vary with
feedback resistance. It, therefore, is recommended that once
optimum resistor values have been determined, 1% tolerance
values should be used if it is desired to maintain flatness over a
wide range of production lots. In addition, resistors of different
construction have different associated parasitic capacitance
and inductance. Surface mount resistors were used for the bulk
of the characterization for this data sheet. It is not recommended
that leaded components be used with the AD8002.
RI
RN
IBI
IBN
VOUT
Figure 5. Output Offset Voltage
–10–
REV. D
AD8002
Driving Capacitive Loads
–45
The AD8002 was designed primarily to drive nonreactive loads.
If driving loads with a capacitive component is desired, best
frequency response is obtained by the addition of a small series
resistance as shown in Figure 6.
THIRD ORDER IMD – dBc
909⍀
RSERIES
IN
RL
500⍀
G = +2
F1 = 10MHz
F2 = 12MHz
–50
CL
–55
2F2 – F1
–60
2F1 – F2
–65
–70
–75
–80
–8 –7
Figure 6. Driving Capacitive Loads
Figure 7 shows the optimum value for RSERIES versus capacitive
load. It is worth noting that the frequency response of the circuit
when driving large capacitive loads will be dominated by the
passive roll-off of RSERIES and CL.
40
RSERIES – V
30
20
–6
–5
–4
–3 –2 –1 0
1
INPUT POWER – dBm
2
3
4
5
6
Figure 8. Third Order IMD; F1 = 10 MHz, F2 = 12 MHz
Operation as a Video Line Driver
The AD8002 has been designed to offer outstanding performance as a video line driver. The important specifications of
differential gain (0.01%) and differential phase (0.02°) meet the
most exacting HDTV demands for driving one video load with
each amplifier. The AD8002 also drives four back-terminated
loads (two each), as shown in Figure 9, with equally impressive
performance (0.01%, 0.07°). Another important consideration
is isolation between loads in a multiple load application. The
AD8002 has more than 40 dB of isolation at 5 MHz when driving two 75 Ω back-terminated loads.
750⍀
75⍀
75⍀ CABLE
750⍀
VOUT #1
10
+VS
75⍀
4.7␮F
+
0
0
0.1␮F
5
10
15
20
25
CL – pF
75⍀
1/2
AD8002
Figure 7. Recommended RSERIES vs. Capacitive Load
75⍀
CABLE
VOUT #2
75⍀
0.1␮F
Communications
Distortion is a key specification in communications applications.
Intermodulation distortion (IMD) is a measure of the ability of
an amplifier to pass complex signals without the generation of
spurious harmonics. The third order products are usually the
most problematic since several of them fall near the fundamentals and do not lend themselves to filtering. Theory predicts that
the third order harmonic distortion components increase in
power at three times the rate of the fundamental tones. The
specification of third order intercept as the virtual point where
fundamental and harmonic power are equal is one standard measure of distortion performance. Op amps used in closed-loop
applications do not always obey this simple theory. At a gain of
two, the AD8002 has performance summarized in Figure 8. Here
the worst third order products are plotted versus. input power.
The third order intercept of the AD8002 is 33 dBm at 10 MHz.
REV. D
–11–
75⍀
CABLE
4.7␮F
VIN
75⍀
–VS
1/2
AD8002
75⍀
75⍀ CABLE
VOUT #3
75⍀
750⍀
750⍀
75⍀
75⍀ CABLE
VOUT #4
75⍀
Figure 9. Video Line Driver
AD8002
Driving A-to-D Converters
The AD8002 is well suited for driving high-speed analog-todigital converters such as the AD9058. The AD9058 is a dual
8-bit 50 MSPS ADC. In Figure 10, the AD8002 is shown driving the inputs of the AD9058 which are configured for 0 V to 2 V
ranges. Bipolar input signals are buffered, amplified (–2×), and
offset (by 1.0 V) into the proper input range of the ADC. Using
the AD9058’s internal 2 V reference connected to both ADCs
as shown in Figure 10 reduces the number of external components required to create a complete data acquisition system. The
20 Ω resistors in series with ADC inputs are used to help the
AD8002s drive the 10 pF ADC input capacitance. The AD8002
adds only 100 mW to the power consumption, while not limiting the performance of the circuit.
10
ENCODE A
8
549⍀
38
ANALOG
IN A
ⴞ0.5V
274⍀
1.1k⍀
50⍀
1/2
AD8002
20⍀
1k⍀
74ACT04
ENCODE
6
10pF
50⍀
36
ENCODE B
–VREF A
+VS
–VREF B
5, 9, 22,
24, 37, 41
+5V
0.1␮F
RZ1
AIN A
D0A (LSB)
18
17
AD707
0.1␮F
20k⍀
20k⍀
0.1␮F
3
43
14
+VREF A
13
11
RZ2
AD9058
(J-LEAD)
D0B (LSB)
274⍀
28
29
20⍀
40
74ACT 273
30
1/2
50⍀ AD8002
31
AIN B
32
33
1
D7B (MSB)
–VS
RZ1, RZ2 = 2,000⍀ SIP (8-PKG)
35
7, 20,
26, 39
0.1␮F
4,19, 21
8
34
COMP
0.1␮F
8
12
+VREF B
1.1k⍀
ANALOG
IN B
ⴞ0.5V
15
+VINT
D7A (MSB)
549⍀
74ACT 273
16
2
–2V
–5V
CLOCK
1N4001
25, 27, 42
Figure 10. AD8002 Driving a Dual A-to-D Converter
–12–
REV. D
AD8002
Single-Ended-to-Differential Driver Using an AD8002
The two halves of an AD8002 can be configured to create a
single-ended-to-differential high-speed driver with a –3 dB
bandwidth in excess of 200 MHz, as shown in Figure 11. Although
the individual op amps are each current feedback, the overall
architecture yields a circuit with attributes normally associated
with voltage feedback amplifiers, while offering the speed advantages inherent in current feedback amplifiers. In addition, the gain
of the circuit can be changed by varying a single resistor, RF,
which is often not possible in a dual op amp differential driver.
RF 511⍀
OP AMP #1
1/2
AD8002
50⍀
OUTPUT #1
RA
511⍀
RB
511⍀
Reactive elements can be used in the feedback network. This is
in contrast to current feedback amplifiers that restrict the use of
reactive elements in the feedback. The circuit described requires
about 0.9 pF of capacitance in shunt across RF in order to optimize
peaking and realize a –3 dB bandwidth of more than 200 MHz.
50⍀
1/2
AD8002
RF 
R 
× 1 + A 
RG 
RB 
The resulting architecture offers several advantages. First, the gain
can be changed by changing a single resistor. Changing either
RF or RG will change the gain as in an inverting op amp circuit.
For most types of differential circuits, more than one resistor
must be changed to change gain and still maintain good CMR.
RA
511⍀
RB
511⍀
G =
OUTPUT #2
OP AMP #2
Figure 11. Differential Line Driver
The peaking exhibited by the circuit is very sensitive to the value
of this capacitor. Parasitics in the board layout on the order of
tenths of picofarads will influence the frequency response and
the value required for the feedback capacitor, so a good layout is essential.
The current feedback nature of the op amps, in addition to
enabling the wide bandwidth, provides an output drive of more
than 3 V p-p into a 20 Ω load for each output at 20 MHz. On the
other hand, the voltage feedback nature provides symmetrical
high impedance inputs and allows the use of reactive components in the feedback network.
The circuit consists of the two op amps, each configured as a
unity gain follower by the 511 Ω RA feedback resistors between
each op amp’s output and inverting input. The output of each op
amp has a 511 Ω RB resistor to the inverting input of the other
op amp. Thus, each output drives the other op amp through a
unity gain inverter configuration. By connecting the two amplifiers as cross-coupled inverters, their outputs are freed to be equal
and opposite, assuring zero-output common-mode voltage.
The shunt capacitor type selection is also critical. A good microwave type chip capacitor with high Q was found to yield best
performance. The part selected for this circuit was a muRata
Erie part number MA280R9B.
The distortion was measured at 20 MHz with a 3 V p-p input
and a 100 Ω load on each output. For Output #1 the distortion
is –37 dBc and –41 dBc for the second and third harmonics
respectively. For Output #2 the second harmonic is –35 dBc
and the third harmonic is –43 dBc.
With this circuit configuration, the common-mode signal of the
outputs is reduced. If one output moves slightly higher, the negative input to the other op amp drives its output to go slightly
lower and thus preserves the symmetry of the complementary
outputs, which reduces the common-mode signal. The commonmode output signal was measured to be –50 dB at 1 MHz.
Looking at this configuration overall, there are two high impedance inputs (the + inputs of each op amp), two low impedance
outputs, and high open-loop gain. If we consider the two noninverting inputs and just the output of Op Amp #2, the structure
looks like a voltage feedback op amp having two symmetrical,
high-impedance inputs, and one output. The +input to Op Amp
#2 is the noninverting input (it has the same polarity as Output
#2) and the +input to Amplifier #1 is the inverting input (opposite polarity of Output #2).
6
CC = 0.9pF
4
2
0
OUTPUT – dB
VIN
The differential gain of this circuit is:
The RF /RG term is the gain of the overall op amp configuration
and is the same as for an inverting op amp except for the polarity.
If Output #1 is used as the output reference, the gain is positive. The 1 + RA/RB term is the noise gain of each individual op
amp in its noninverting configuration.
CC 0.5–1.5pF
RG
511⍀
With a feedback resistor RF, an input resistor RG, and grounding
of the +input of Op Amp #2, a feedback amplifier is formed.
This configuration is just like a voltage feedback amplifier in an
inverting configuration if only Output #2 is considered. The
addition of Output #1 makes the amplifier differential output.
–2
–4
–6
OUT+
–8
–10
OUT–
–12
–14
1M
10M
100M
FREQUENCY – Hz
1G
Figure 12. Differential Driver Frequency Response
REV. D
–13–
AD8002
RF
Layout Considerations
The specified high-speed performance of the AD8002 requires
careful attention to board layout and component selection.
Proper RF design techniques and low parasitic component selection are mandatory.
+VS
RG
IN
RBT
OUT
RT
RS
The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low
impedance ground path. The ground plane should be removed
from the area near the input pins to reduce stray capacitance.
–VS
Inverting Configuration
Chip capacitors should be used for supply bypassing (see Figure
13). One end should be connected to the ground plane and the
other within 1/8 in. of each power pin. An additional large tantalum electrolytic capacitor (4.7 µF–10 µF) should be connected in
parallel, but not necessarily so close, to supply current for fast,
large-signal changes at the output.
+VS
C1
0.1␮F
C3
10␮F
C2
0.1␮F
C4
10␮F
–VS
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the inverting input will significantly affect high-speed performance.
Supply Bypassing
RF
Stripline design techniques should be used for long signal traces
(greater than about 1 in.). These should be designed with a
characteristic impedance of 50 Ω or 75 Ω and be properly terminated at each end.
+VS
RG
RBT
OUT
*RC
IN
RT
–VS
*SEE TABLE I
Noninverting Configuration
Figure 13. Inverting and Noninverting Configurations
Table I. Recommended Component Values
AD8002AN (DIP)
Gain
AD8002AR (SOIC)
Gain
Component
–10
–2
–1
+1
+2
+10
+100
–10
–2
–1
+1
+2
+10
+100
RF (Ω)
RG (Ω)
RBT (Nominal) (Ω)
RC (Ω)*
RS (Ω)
RT (Nominal) (Ω)
Small Signal BW (MHz)
0.1 dB Flatness (MHz)
499
49.9
49.9
549
274
49.9
576
576
49.9
1210
–
49.9
75
750
750
49.9
75
499
54.9
49.9
0
1000
10
49.9
0
499
49.9
49.9
499
249
49.9
549
549
49.9
953
–
49.9
75
681
681
49.9
75
499
54.9
49.9
0
1000
10
49.9
0
49.9
–
270
45
49.9
61.9
380
80
49.9
54.9
410
130
49.9
600
35
49.9
500
60
49.9
170
24
49.9
17
3
49.9
–
250
50
49.9
61.9
410
100
49.9
54.9
410
100
49.9
600
35
49.9
500
90
49.9
170
24
49.9
17
3
AD8002ARM (␮SOIC)
Gain
Component
–10
–2
–1
+1
+2
+10
+100
RF (Ω)
RG (Ω)
RBT (Nominal) (Ω)
RC (Ω)*
RS (Ω)
RT (Nominal) (Ω)
Small Signal BW (MHz)
0.1 dB Flatness (MHz)
499
49.9
49.9
499
249
49.9
590
590
49.9
1000
–
49.9
75
681
681
49.9
75
499
54.9
49.9
0
1000
10
49.9
0
49.9
–
270
60
49.9
61.9
400
100
49.9
49.9
410
100
49.9
600
35
49.9
450
70
49.9
170
35
49.9
19
3
*RC is recommended to reduce peaking, and minimizes input reflections at frequencies above 300 MHz. However, R C is not required.
–14–
REV. D
AD8002
Figure 14. Board Layout (Silkscreen)
REV. D
–15–
AD8002
Figure 15. Board Layout (Component Layer)
–16–
REV. D
AD8002
Figure 16. Board Layout (Solder Side) (Looking through the Board)
REV. D
–17–
AD8002
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP (N-8)
0.430 (10.92)
0.348 (8.84)
8
5
1
PIN 1
0.280 (7.11)
0.240 (6.10)
4
0.325 (8.25)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.022 (0.558) 0.070 (1.77) SEATING
0.014 (0.356) 0.045 (1.15) PLANE
8-Lead SOIC (SO-8)
0.1968 (5.00)
0.1890 (4.80)
8
5
1
4
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.0196 (0.50)
ⴛ 45ⴗ
0.0099 (0.25)
0.0500 (1.27)
BSC
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
8ⴗ
0.0500 (1.27)
0.0098 (0.25) 0ⴗ
0.0160 (0.41)
0.0075 (0.19)
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
8-Lead ␮SOIC (RM-8)
0.122 (3.10)
0.114 (2.90)
8
5
0.199 (5.05)
0.187 (4.75)
0.122 (3.10)
0.114 (2.90)
1
4
PIN 1
0.0256 (0.65) BSC
0.120 (3.05)
0.112 (2.84)
0.006 (0.15)
0.002 (0.05)
0.018 (0.46)
SEATING 0.008 (0.20)
PLANE
0.120 (3.05)
0.112 (2.84)
0.043 (1.09)
0.037 (0.94)
0.011 (0.28)
0.003 (0.08)
–18–
33ⴗ
27ⴗ
0.028 (0.71)
0.016 (0.41)
REV. D
Revision History– AD8002
Location
Page
Data Sheet changed from REV. C to REV. D.
MAX RATINGS changed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
REV. D
–19–
–20–
PRINTED IN U.S.A.
C01044b–0–4/01(D)
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
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AD8002AR-EBZ AD8002ARM-EBZ AD8002ARZ AD8002ANZ AD8002ARMZ AD8002AR AD8002ARMZ-REEL
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