VisionLink CLS
Camera Link simulator for PCI Express
Description
The VisionLink CLS is a Camera
Link 2.0 simulator that simulates base
through 80-bit mode cameras, 1–10
taps, at pixel clock rates of 20 to 85
MHz on a PCI Express Gen3 board.
Actual or generated images are output as Camera Link data, facilitating
development and testing of imaging
systems, cameras, and software.
Images are sent via DMA from host
memory, with data rates of up to 850
MB/s (85 MHz, 10-tap, 8-bit) as supported by the host computer. Internal
counters can be used as an alternative
source of image data.
Simulator setup is facilitated by
text-based configuration scripts, easily
modifiable to match the timing parameters of multiple camera models.
Line and frame triggering are supported over camera control lines.
C language libraries provide access
to all simulator functions and allow the
user to define appropriate responses to
UART commands from the interface.
Features
Simulates Camera Link cameras, base through extended full mode, 1—10 taps
Supports pixel clock rates of 20 to 85 MHz
Outputs actual or generated images as Camera Link data
Allows internal counters to be used as alternative source of image data
Supports DMA from host memory at data rates up to 850 MB/s (85 MHz, 10tap, 8-bit), as supported by host
Includes text-based configuration scripts modifiable for various camera models
Supports line and frame triggering over camera control lines
Allows emulation of camera UART commands
Applications
Development and testing of...
- Cameras
- Image-processing software
- Image-processing hardware
- Imaging systems and applications
Record-playback systems
Engineering Design Team, Inc. | 3423 NW John Olsen Pl., Hillsboro, Oregon 97124 USA | Tel: +1-503-690-1234 (800-435-4350) | Fax: +1-503-690-1243 | info@edt.com | edt.com
VisionLink CLS
Specifications
Data Format
Camera Link
Memory
FIFO
Up to several lines of data Camera Link Compliance Version
2.0
Base, dual base, medium, full, extended full — common configurations
(Dual base outputs can use the same or different pixel clock sources.)
20—85 MHz
9600 to 115,200 baud (via API, serial DLL, or loopback)
Supported
SDR26
Modes
Pixel clock rate
Serial
CC1 - CC4 Connectors
EU Compliance
Contact EDT
PCI Express Compliance
Form factor
PCIe version
Direct memory access (DMA)
Number of lanes
Noise
0 dB
MTBF
Estimated at 200,000 hours
Triggering
Freerun or via CC lines
Connectors
Two SDR26 Camera Link
For data and control
Cabling
Camera Link (purchased separately)
SDR-to-SDR or SDR-to-MDR
Physical
Weight
Dimensions
3.5 oz.
With connectors and backpanel, 4.75 x 5.0 x 0.75”; without, 4.0 x 4.625 x 0.5”
Environmental
Temperature (operating / non-operating)
Humidity (operating / non-operating)
10° to 40° C / -20° to 60° C
1% to 90%, non-condensing at 40° C / 95%, non-condensing at 45° C
Software
Half-length, full-height
Gen3
Yes
8
Software is included for Windows and Linux; for versions, see edt.com.
Ordering Options
• VisionLink CLS: Standard options
• Camera Link cabling: Purchased separately
Bold is default. Ask about custom options.
Contact EDT to discuss engineer-to-engineer support, from phone consults to custom design of hardware, firmware, or software.
20171110
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