Improving UPS’ Static Switch Performance by the Means of
Control Logic and Component Technology
Kalle Pirinen
Left to be examined as a M.Sc. thesis in Lappeenranta on 13.04.2017
Examiner:
Supervisor:
Prof. Pertti Silventoinen
M.Sc. Jari Uusitalo
Master’s Thesis
LUT School of Energy Systems
Electrical Engineering
2
3
ABSTRACT
Lappeenranta University of Technology
School of Energy Systems
Degree Program in Electrical Engineering
Kalle Pirinen
Improving UPS’ Static Switch Performance by the Means of Control Logic and
Component Technology
Master’s Thesis
66 pages, 19 figures, 5 tables, 2 appendices
Thesis supervisor M.Sc. Jari Uusitalo, Eaton Power Quality Oy
1st examiner Prof. Pertti Silventoinen
2nd examiner M.Sc. Jari Uusitalo
Keywords: UPS, static switch, control methods, switching component technology, commutation, transformer inrush current elimination
A static switch is an electronic switch used to provide an alternate power path to the load
to either provide fast and controllable backup power routing in case of inverter failure,
overload condition, or to clear a fuse in case of load equipment failure. Traditionally static
switch consists of two antiparallel thyristors per phase.
The goal of this thesis is to inspect alternative for thyristors as the switching components
of the static switch to improve its performance without affecting the production costs too
much On-state losses, power rating, and turn-off time, are used as the meters of performance. Additionally, control methods are developed to improve static switch performance
in some common situations. These include power supply under- and overvoltage, and using 3-phase isolation transformer on the UPS output.
As conclusions, it was discovered that SiC-MOSFETs could be used for similar on-state
losses and faster turn-off time, compared to thyristors, but due to high cost of compo-
4
nents, it’s not a financially viable option to change the component type used in the static
switch assembly.
Based on simulations, two control methods using UPSs inverter, were proposed to mitigate thyristor commutation time. In case of grid undervoltage, the turn-off time of the static
switch was reduced from worst case scenario of 10 ms to 1 ms. In case of grid overvoltage, the turn-off time of the static switch was reduced from worst case scenario of 10 ms
to 5.1 ms.
Additionally, based on simulations, a control method was proposed, which eliminates inrush currents on a delta-primary winding 3-phase transformer. The effectiveness of the
control method was verified on a test setup.
5
TIIVISTELMÄ
Lappeenrannan teknillinen yliopisto
School of Energy Systems
Sähkötekniikan koulutusohjelma
Kalle Pirinen
UPS:n staattisen ohituskytkimen suorituskyvyn parantaminen ohjauslogiikalla ja
komponettivalinnoilla
Diplomityö
66 sivua, 19 kuvaa, 5 taulukkoa, 2 liitettä
Työn ohjaaja: DI Jari Uusitalo, Eaton Power Quality Oy
1. Tarkastaja: Prof. Pertti Silventoinen
2. Tarkastaja: DI Jari Uusitalo
Hakusanat: UPS, staattinen ohituskytkin, ohjausmenetelmät, kytkinkomponenttiteknologia,
kommutointi, muuntajan käynnistysvirran eliminointi
Staattinen ohituskytkin on sähköinen kytkin, jolla voidaan ohittaa UPS:n tehoelektroniikka,
ja jonka kautta kuormalle voidaan syöttää suoraan verkkovirtaa esimerkiksi huoltotöiden
ajan. Staattinen kytkin koostuu perinteisesti kahdesta vastarinnan kytketystä tyristorista
jokaista vaihetta kohden.
Työn tarkoituksena on selvittää, onko staattisen kytkimen kytkinkomponentit mahdollista
korvata eri komponenttityypillä suorityskyvyn parantamiseksi tuotantokustannuksia paljoa
lisäämättä.
Suorituskyvyn
mittareina
käytetään
johtotilan
häviöitä,
komponentin
tehonkestoa sekä poiskytkentäaikaa. Lisäksi työssä tarkastellaan simulaatioiden pohjalta
ohjausmenetelmiä, joilla nykyisen staattisen kytkimen suorituskykyä voidaan parantaa
havaittaessa verkon ali- tai ylijännite, sekä käytettäessä kolmivaiheista erotusmuuntajaa
laitteen lähdössä.
6
Työn tuloksena saatiin selville, että piikarbidi-MOSFET:llä staattisen ohituskytkimen
poiskytkentäaikaa saataisiin nopeutettua ja johtotilan häviöitä saataisiin samalle tasolle
verrattuna tyristoriin,
mutta komponenttityypin vaihtaminen ei
ole taloudellisesti
kannattavaa.
Simulaatioiden
pohjalta
kommutoinniksi
UPS:n
esitettiin
ohjausalgoritmit
vaihtosuuntaajan
avustuksella.
staattisen
ohituskytkimen
Alijännitteen
tapauksessa
poiskytkentäaika saatiin vähennettyä pahimman tapauksen 10 ms:sta 1 ms:iin,
ylijännitteen tapauksessa 10 ms:sta 5,1 ms:iin.
Lisäksi
simulaatioden
kolmivaihemuuntajan
pohjalta
esitettiin
käynnistysvirtapiikki
ohajusmenetelmä,
saadaan
toiminta varmistettiin testaamalla sitä testilaitteistolla.
jolla
eliminoitua.
kolmioensiöisen
Ohjausmenetelmän
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ACKNOWLEDGEMENTS
This Thesis was carried out at Eaton Power Quality Oy Espoo. I’d like to thank Eaton
Power Quality Oy for this wonderful chance for the interesting master’s thesis topic. I’d like
to especially thank Jari, Tuomo and Anders for helping me with the thesis by providing
their expertise with the UPS.
After publishing this thesis, my years of studying in Lappeenranta will be over. The last six
years have been the most fulfilling time of my life. I’d like to thank all my friends and family
for all the support during all these years.
Espoo, March 2017
Kalle Pirinen
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Table of Contents
1.
2.
3.
4.
INTRODUCTION ................................................................................................. 11
1.1
Background ................................................................................................. 11
1.2
Research problems, goals and scope............................................................ 11
1.3
Research methodology ................................................................................. 13
1.4
Structure of the thesis................................................................................... 13
GENERAL........................................................................................................... 14
2.1
UPS............................................................................................................. 14
2.2
Static Switch ................................................................................................ 17
POSSIBLE SWITCHING COMPONENTS USED IN STATIC SWITCH .................. 18
3.1
Thyristor ...................................................................................................... 18
3.2
GTO ............................................................................................................ 22
3.3
IGCT ........................................................................................................... 24
3.4
Power MOSFET ........................................................................................... 25
3.5
IGBT............................................................................................................ 28
3.6
Choosing switching components for a static switch ........................................ 31
CONTROL CHALLENGES................................................................................... 36
4.1
Simulation model.......................................................................................... 36
4.2
Turn-off Time ............................................................................................... 38
4.2.1 Thyristor turn-off time minimization on AC-source undervoltage ................. 39
4.2.2 Thyristor turn-off time minimization on AC-source overvoltage.................... 40
4.3
Transformer Inrush Current Elimination ......................................................... 43
5.
TESTING ............................................................................................................ 57
6.
CONCLUSIONS AND SUMMARY........................................................................ 62
REFERENCES ........................................................................................................... 63
APPENDICES ............................................................................................................ 65
9
USED ABBREVIATIONS AND SYMBOLS
Abbreviations
AC
Alternating current
DC
Direct Current
GTO
Gate Turn-off Thyristor
IGBT
Insulated Gate Bipolar Transistor
IGCT
Integrated Gate-Commutated Thyristor
LL
Line-to-Line
LN
Line-to-Neutral
MOSFET
Metal-Oxide-Semiconductor Field-Effect Transistor
PLL
Phase Lock Loop
PT
Punch Through
RMS
Root Mean Square
SiC
Silicon Carbide
UPS
Uninterruptible Power Supply
VFD
Voltage and Frequency Dependent
VFI
Voltage and Frequency Independent
VI
Voltage Independent
Symbols
cos⁡()
Power factor
C
Capacitance
f
Frequency
g
Transconductance
I
Current
L
Inductance
N
Number of Turns
S
Apparent Power
P
Real Power
Q
Reactive Power
R
Resistance
t
Time
T
Period
10
v
Instantaneous voltage
V
Voltage
X
Reactance
Z
Impedance

NPN-transistor gain

PNP-transistor gain

Magnetic Flux
Units
A
Ampere
F
Farad
H
Henry
Hz
Hertz
pu
Proportional Unit
s
Second
S
Siemens
T
Tesla
V
Volt
VA
Volt-Ampere
VAr
Volt-Ampere Reactive
W
Watt
Wb
Weber
Ω
Ohm
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1. INTRODUCTION
1.1
Company background
Eaton Power Quality Oy is affiliated company of the Eaton Corporation. In Finland,
Eaton Power Quality focuses on production and development of UPS-devices. The
company employs over 200 people in Espoo, Finland.
The company was founded in 1962 as Fiskars Elektroniikka. In 1982, parts of
Fiskars Elektroniikka and Televa merged in to Fiskars Tehoelektroniikka, which
later on was renamed Fiskars Power Systems. In 1985 the company bought Behlman, then in 1986 Warren, in 1987 Ulveco and in 1988 Deltec, and merged them
into its own business. In 1996, Exide Electronics bought the company. In 1997
BTR bought Exide Electronics, and in 1999 it merged with Siebe and the merged
company was named Invensys. At the same time Finnish branch was renamed
Powerware Oy. In 2000 the branch was renamed Invensys Secure Power, and in
2002 Invensys Powerware. In 2004 Invensys Powerware was bought by Eaton
Corporation and was merged to Eaton Power Quality, and has remained that since
then. (Uusitalo, 2016-2017)
1.2
Research problems, goals and scope
In this thesis, methods to improve performance of the static switch of a UPS by the
means of component technology and control methods are researched.
A static switch is an electronic switch used to provide alternate power path to the
load to either provide fast and controllable backup power routing in case of overload condition, or to clear a fuse in case of load equipment failure. It can also be
used to improve system total energy efficiency when AC –source quality is within
predefined limits. Furthermore it can be used in case of a converter or an inverter
failure to ensure continuous power to the load. Conventionally static switch is realized with thyristors.
12
The UPSs in the scope of the thesis include the 20 kVA family of the Eaton 93PS
devices. They all share a common static switch design, and the hardware limitations for the inverter current are the same. All the possible modifications are done
only on the static switch hardware and firmware, No other modifications are being
made to the other hardware and firmware of the UPS.
The first problem of the thesis is to determine, if there is a more suitable component technology to replace thyristors with. The aspects to consider regarding suitability are component losses, turn-off time, power withstand capability and costs. If
suitable component technology is found, a prototype is made and tested.
The second problem is turn-off time minimization on a static switch realized with
thyristors. The natural commutation of the thyristors can take up 10 ms on a 50 Hz
system and 8.3 ms on a 60 Hz system, and voltage anomalies that long can prove
fatal to the sensitive electronic loads. The goal is to determine, if there’s a control
method to use the inverter of the UPS in unison with the static switch to minimize
turn-off time of thyristors during abnormal voltage conditions. The possible control
method is tested on an existing platform, if it can be realized with minor changes in
the inverter and static switch control. A 50 Hz system is used in simulations due to
its longer possible commutation times.
The third problem involves minimizing the inrush currents on 3-phase transformers
with delta-primary windings, that are commonly used with UPS devices. Inrush
current is the current transient that occurs when an electrical device is first turned
on. When discussing transformers, the inrush can be characterized by its initial
peak value. It can cause excess stress for the transformer and the connected circuitry. It can also cause erroneous tripping of overload protection. The possible
control method is initially developed for the static switch on a simulated environment, and is then tested on an existing platform. The possibility of using the same
control method using different switching components is considered on a theoretical
level.
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1.3
Research methodology
The first research problem is approached as a study on current component technologies. The pros and cons of each plausible component type are assessed when
used in a static switch, and if a more suitable component type is found, it will be
used to make a prototype of a new static switch.
The second and third research problems are approached by simulating the current
system, and developing control methods that can solve the problem. If a suitable
method is found, it will be tested on a real system assuming it can be realized with
reasonable amount of changes in the firmware.
1.4
Structure of the thesis
In chapter 1, the research problems, goals, and the scope of the thesis are determined. Eaton Power Quality Oy is also introduced. In chapter 2, the static switch
and UPS devices are introduced.
In chapter 3, the possible component technologies that could be used in a static
switch are introduced. The suitability of usage on a static switch of each component type is assessed.
In chapter 4, the simulation model of the current system is introduced. The simulation model is then used to assess possible control methods to solve the research
problems. In chapter 5, the control methods proposed in chapter 4 are realized on
a real system, and their functionality is assessed by measurements. Chapter 6 is
reserved for summary and conclusions.
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2. GENERAL
2.1
UPS
“A Uninterruptible Power Supply (UPS) is a device that provides power conditioning and backup power when the utility power fails. Backup power is usually provided either long enough for critical equipment to shut down gracefully so that no data
is lost, or long enough to keep required loads operational until secondary alternating current (AC) source comes online. A UPS can also be used to condition incoming power so that sags and surges don’t damage sensitive electronic gear.”
(Eaton, 2015) The UPSs are available with power ratings as low as tens of VA and
as high as several MVA. The UPSs can be either one-phase or three-phase, and
three-phase systems can have four- or three-wire connection (i.e. with or without
neutral conductor).
The IEC standard 62040-3 states a three-step code to classify UPSs, e.g. “VFI SS
111”. The first step is to classify by the dependency of UPS output on the input
power grid. The second step is classification by the voltage waveform of the UPS
output. The third one is classification by the dynamic tolerance curves of the UPS
output. (IEC, 2011)
The first step can be divided in three classes: voltage and frequency independent
(VFI), voltage independent (VI), and voltage and frequency dependent (VFD). A
VFI UPS “is independent of supply (mains) voltage and frequency variations …
and shall protect the load against adverse effects from such variations without depleting the stored energy source“ (IEC, 2011). For VI UPS, the “output is dependent on a.c. input frequency and the voltage shall remain within prescribed limits
provided by additional corrective voltage functions, such as those arising from the
use of active and/or passive circuits” (IEC, 2011). For VFD UPS, “the output of the
UPS is dependent on changes in a.c., input voltage and frequency and is not intended to provide additional corrective functions, such as those arising from the
use of tapped transformers” (IEC, 2011).
15
The second step categorizes the output voltage waveform in normal mode and
stored energy mode with a two-character structure. First character corresponds
the waveform on normal or bypass mode and second the waveform on stored energy mode. The characters that define the waveform are as follows. S for sinusoidal waveform “presenting total harmonic distortion ≤ 8 % and individual harmonic
distortion within limits … under all linear and reference non-linear load conditions”
(IEC, 2011). X for sinusoidal/non-sinusoidal waveform that is “meeting ‘S’ specification under all linear load condition” and “not meeting ‘S’ under rated non-linear
load condition” (IEC, 2011). Y for non-sinusoidal waveform that is “not meeting ‘S’
specification under reference linear load conditions”. (IEC, 2011)
The third step defines the maximum allowed dynamic deviations from clean sine
wave with a three-character structure. The first character shows performance during operating mode changes, e.g. from stored energy mode to normal mode. The
second character shows worst case performance with linear load step. The third
character shows the worst case performance with non-linear load step. Each character can get a value from 1 to 3. The character “1” means that the “UPS output
voltage remains within the limits of Figure 2.1, and this level of performance is required for sensitive critical loads” (IEC, 2011).
Figure 2.1, Dynamic output performance classification 1 (IEC, 2011)
16
The character “2” means that the “UPS output voltage remains within the limits of
Figure 2.2, and this level of performance is accepted by most types of critical load”
(IEC, 2011).
Figure 2.2, Dynamic output performance classification 2 (IEC, 2011)
The character “3” means that the “UPS output voltage remains within the limits of
Figure 2.3, and this level of performance is accepted by general purpose IT loads”
(IEC, 2011).
Figure 2.3, Dynamic output performance classification 3 (IEC, 2011)
17
2.2
Static Switch
A static switch is an electronic switch used to provide an alternate power path to
the load to either provide fast and controllable backup power routing in case of
overload condition, or to clear a fuse in case of load equipment failure. Usually a
static switch consists of two thyristors, connected antiparallel per phase, as shown
in Figure 2.4. While static switch is in use, the thyristors are triggered so that both
half-periods of a sinusoidal wave are passed to the load.
Figure 2.4, Static switch topology
In VFI UPSs, the static switch is mainly used to bypass double-conversion in case
of overload condition, or to clear a fuse in case of load equipment failure. Furthermore it can be used in case of inverter or AC/DC –converter failure to ensure continuous power to the load.
In some UPSs, the static switch can be used to bypass the double conversion,
when the AC source is within predefined limits, to improve the overall efficiency of
the UPS. If the quality of the AC supply falls out of the limits, the UPS automatically switches to double-conversion mode and turns off the static switch to maintain
the quality of the electricity fed to the load. In the case of AC supply blackout, the
UPS automatically turns off the static switch, and starts to supply the load using
the UPS’s energy storage, like batteries, capacitors, or flywheel through the converter/inverter portion of the UPS.
18
3. POSSIBLE SWITCHING COMPONENTS USED IN STATIC SWITCH
3.1
Thyristor
“A thyristor is semiconductor device with three terminals and four alternating layers
of P- and N-type materials. It comprises of three electrodes: anode, cathode, and
control electrode, gate. The load is connected in the anode-cathode circuit and
control is realized via the gate. The structure of a thyristor on the physical and
electronic level, and the thyristor symbol can be seen in Figure 3.1.” (Dokić, 2015)
Figure 3.1, Structure of a thyristor on the physical and electronic level, and the thyristor
symbol
The nominal values of the present day thyristors range from several mA up to several thousands of A and the nominal values of voltages extend up to 15 kV.
“Thyristors have three states: reverse blocking mode, forward blocking mode and
forward conducting mode. In reverse blocking mode, voltage is applied in the direction that would be blocked by a diode. In forward blocking mode, voltage is applied in the direction that would cause a diode to conduct, but there has been no
gate trigger to induce the conduction in the device.” (Dokić, 2015)
19
“In forward conducting mode, the gate trigger has been introduced to the device,
and the device will remain conducting until the forward current drops below
threshold value known as the holding current h ” (Dokić, 2015). Typical values of h
are within range from several hundreds of µA up to hundreds of mA. “After the thyristor is turned on, no gate drive is required. Moreover, it is then of no use because
it only heats up the thyristor. In addition, the negative gate bias has no use, because it increases the reverse anode current. Because of all this, the gate should
be “picket fence” pulse train driven. Each driving pulse should have the required
gate current g, gate voltage g , and sufficient gate pulse length g .” (Dokić, 2015)
“The time g is several µs, but practically it is between 10 and 20 µs. The gate
voltage has to be higher than the threshold voltage of the P-N –junction, which is
about 0.5 V. The maximum voltage GM is several V and the maximum current GM
ranges from 100 mA up to several A.” (Dokić, 2015)
“The turn-on process mentioned before is only valid under the assumption that the
anode voltage changes are slow. At high rates of anode voltage variations the
turning on will be faster. Since, the collector P-N –junctions of transistors Tn and
Tp are reverse biased, they can be considered as capacitor, as shown in Figure
3.2.” (Dokić, 2015)
Figure 3.2, High frequency thyristor model (Dokić, 2015, p. 174, modified)
“If the voltage drop across the forward biased emitter junctions is neglected, the
current through this capacitor is
20
 = CB
A

+ A
CB

1
A
2

≈ ⁡ CB
(3.1)
since CB ⁡~⁡1/√A . Thus the anode current is proportional to the rate of the anode
current, and at higher rates of dVA/dt this current may become significant. As the
current rises, current gains α n and αp increase and the turn-on conditions are fulfilled at lower input voltages. In other words, the turn-on occurs at lower voltages
compared to the static breakpoint voltage PMO . Thus, the capacitive current causes the thyristor to turn on via the same mechanism as that of the gate current. This
phenomenon is often called the dv/dt effect or dv/dt capability, and it is defined in
device specifications as the maximum value of dv/dt. It ranges from 10 V/µs to
about 1000 V/µs.” (Dokić, 2015)
“Conventionally designed thyristors have a side positioned control electrode, as
shown in Figure 3.3. Immediately after positive pulse at the gate, the full voltage g
will appear only at the part of the junction J2 nearest to the gate terminal. Due to
the voltage drop across the transversal resistance Rs of the region P2, the remote
parts will be at lower potential, therefore at a lower forward bias. This means that
at the beginning only a narrow part of the thyristor is conducting while the major
part of it is in the off state.” (Dokić, 2015)
“Due to high current density at this narrow part the dissipation in this part is the
highest, which may lead to overheating of the junction and destruction of the el ement. If the rate of increase in current di/dt is smaller than the maximum permitted
(di/dt)M, the current due to regenerative process will be distributed evenly across
the cross section and thus causes no damage to the thyristor.” (Dokić, 2015) The
values of di/dt capability of thyristors can be up to tens of thousands of A/µs.
21
Figure 3.3, Thyristor with amplifying gate (Dokić, 2015, p. 177)
“While a thyristor is on, all P-N –junctions are forward biased and both transistors
are in saturation. Due to this there are considerable piled up charges in all four
parts of the thyristor. Figure 3.4 shows the corresponding minority carrier distributions. The most part of the charge is stored in region N1 because the region is the
widest and the least conductive. On the anode and cathode electrodes the concentrations of minority carriers are negligible due to conductivities of the regions P1
and N2 are very high.” (Dokić, 2015)
Figure 3.4, Distribution of minority carriers on conducting thyristor (Dokić, 2015, p. 179)
“If a thyristor is to be turned off, the piled-up charge needs to be cleared away,
which is accomplished by cutting off anode circuit or reversing the bias. The turnoff time ti of a thyristor is the elapsed time from the reverse bias of the anode circuit until the thyristor is again capable of blocking a positive anode voltage at the
maximum permitted value at the maximum permitted rate of change. This time is
typically several tens of µs, and for fast thyristor it is of the order of 1 µs.
22
It’s also worth noticing that the gate voltage will influence turn-off time; it will increase it if positive and decrease it if negative. This is understandable due to positive voltage supporting regeneration within a thyristor, and negative extracting positive charge from region P1, suppressing regeneration.” (Dokić, 2015)
3.2
GTO
“Gate turn-off thyristors (GTO) are thyristors that are turned on and off by the gate.
A cross section, two-transistor model, and symbol of a GTO are shown in Figure
3.5. Turning off is achieved by negative gate current. In order to initiate the regenerative process, both transistors during turn-off need to be in the active region.
Thus, the base current of T n needs to be lower than the saturation base current,
i.e.
Bn = ⁡ p A −⁡ G ⁡ ≤ ⁡
(1−⁡0 )A
n
.
(3.2)
From Equation 3.2 it follows that the minimum gate current required for turning off
the thyristor is determined by
G ⁡ ≥ ⁡
p +⁡n −1
n
A.
(3.3)
Consequently, it is possible in principle to turn-off any thyristor by the gate. However, a very high gate current, even higher than the anode current, would be
needed to achieve this level of control.” (Dokić, 2015)
23
Figure 3.5, cross-section, two-transistor model, and symbol of GTO thyristor (Dokić, 2015, p.
190)
“The ratio of the anode and gate current required for turn-off is often called the
turn-off current gain and is determined by
I = ⁡
A
G
=⁡
n
p +⁡n −1
.
(3.4)
For conventional thyristors I ⁡ ≈ 1. In order to make the gate turn-off process practically possible, the condition I ⁡ ≫ 1 has to be met. This, according to Equation
3.4, means that the sum of current gains  should be approximately 1, but
p + ⁡ n ⁡ > 1 and p should be as small as possible. This can be technologically
accomplished in several ways. A cross section of GTO thyristor can be seen in
Figure 3.5. The p-emitter surface is small, so p is small. On the other hand, the nemitter surrounds the gate, so its effective surface is large and thus making n
large.” (Dokić, 2015)
Generally, GTOs with similar nominal voltage and current values compared to thyristors, have a higher on-state voltage drop than thyristors.
24
3.3
IGCT
“Integrated Gate-Commutated Thyristor (IGCT) is a semiconductor device, whose
characteristics are similar to those of a GTO thyristor. Unlike the GTO thyristor,
IGCT has much greater gate turn-off current, which results in complete elimination
of minority carriers from the lower P-N –junction and consequently a shorter turnoff time. The idea was to get a switching component with a low voltage drop and
low losses in the on-state, and the ability to turn off rapidly with minimal switching
losses.” (Dokić, 2015)
“It is known that the turning off of the GTO thyristor can be realized by the gate
current. The goal is to have a turn-off time as short as possible. While a GTO is
turning off, the gate current sharply increases before the anode voltage begins to
rise. In this case, known as “hard-driven turn-off”, the NPN transistor turns off first,
as shown in Figure 3.6a, and then the PNP transistor with an open base assumes
the basic function of turning off the GTO thyristor, as shown in Figure 3.6b.”
(Dokić, 2015)
“In general, the maximum turn-off current for GTOs can be determined by
GMogg = ⁡
Goff s
Gt
,
(3.5)
where Goff turn-off gate voltage, Gt is the total inductance of gate and s is the
GTO storage time (time from moment when negative voltage between the gate
and cathode appears to the moment when anode voltage starts to rise).” (Dokić,
2015)
“It can be concluded, based on Equation 3.5, that the maximum turn-off current
can be increased by increasing the voltage Goff and the time s , and reducing inductance Gt . Even with state-of-the-art technology it is difficult to increase Goff
and s , so the only solution is to decrease the Gt . The reduction of the inductance
in the IGCT is realized by placing the gate unit as close as possible to the GCT
thyristor on the same printed circuit board. This allows the maximum gate currents
of 1000 A and more to be achieved.” (Dokić, 2015)
25
Figure 3.6, Two transistor model (a) and hard driven turn off of GTO thyristor (b) (Dokić,
2015, p. 193)
“The gate has a special power supply unit, which is a low voltage source connected via an isolation transformer to the gate unit that is usually at a different voltage
relative to the source. This can be a problem if the IGCT is used in high voltage
applications, because the necessary isolation transformers are larger, and it’s
more difficult to apply a reliable method of isolation. Also, the external power supply increases the costs and decreases the overall efficiency and reliability of the
system.” (Dokić, 2015)
3.4
Power MOSFET
Metal-oxide-semiconductor field-effect transistor (MOSFET) is a three-terminal
power semiconductor device with vertical structure as shown in Figure 3.7a.
“When sufficiently high positive control voltage is applied between gate and
source, an n-conducting channel is formed within the p-region below the gate terminal. This channel conducts electrons from emitter through the n —drift area to the
bottom terminal, where they deplete the charge carrier region. These electrons
alone conduct the main current, making MOSFETs unipolar components.”
(Semikron, 2015)
26
Figure 3.7, Power MOSFET cell including the key parasitic elements a) in the cellular structure; b) in equivalent circuit diagram (Semikron, 2015, p. 62)
“As can be seen from Figure 3.7b, the equivalent circuit diagram shows, apart from
internal capacitances and resistances, an “ideal MOSFET” and an NPN transistor.
Lateral resistance of the p-well RW and the base-to-collector connection of the parasitic bipolar transistor form inverse diode, which makes MOSFET reverse conducting.” (Semikron, 2015)
“If a positive drain source voltage VDS and gate-source voltage VGS below the gatesource threshold voltage level VGS(TH) is applied, only a very small cut-off current
IDSS will flow between the drain and source terminal. When VDS rises, IDSS increases
slightly at first. Above specified, maximum rated drain-source voltage VDSS there
will be an avalanche breakdown of the PIN-junction p+ -well/ n- drift area/ n+ epitaxy
layer drain region (drain-source breakdown voltage V(BR)DSS).” (Semikron, 2015)
“Physically speaking, V(BR)DSS corresponds roughly to the breakdown voltage VCER
of the parasitic bipolar NPN-transistor in the MOSFET structure. The multiplication
current generated during avalanche breakdown in the collector-base diode can
lead to destruction of the component, caused by bipolar transistor turn-on.”
(Semikron, 2015)
27
“The forward on-state at a positive drain-source voltage VDS and positive drain current ID comprises of characteristic curve areas, active region and ohmic characteristic area.” (Semikron, 2015)
“In the active region, where the gate-emitter voltage VGE hardly exceeds the gateemitter threshold voltage VGE(TH), a relatively high voltage share will be depleted
through the channel owing to the current saturation. The drain current ID is controlled by VGS. As a measure of transfer behavior, the forward transconductance gfs
is defined as
fs = ⁡
∆D
∆GS
=
D
GS −GS(ℎ)
.
(3.6)
Forward transconductance rises in proportion to the increase in drain current ID
and the drain-source voltage VDS and falls as chip temperature increases. Stationary module operation is not permissible, because VGS(TH) drops when the temperature rises, meaning that even a small differences between chips may cause thermal instability.” (Semikron, 2015)
“The ohmic characteristic area, which corresponds to ON –state during switching
operations, is reached when ID is determined by the outer circuit only. On-state
behavior is characterized by the drain-source on-resistance RDS(on) as a quotient of
changing gate-source voltage VGS and the chip temperature. In the operating temperature range of a MOSFET, RDS(on) is almost doubled in the range between 25°C
and 125°C.” (Semikron, 2015)
“In inverse mode, the MOSFET has a diode characteristic at VGS < VGS(TH). This
behavior caused by the parasitic diode in MOSFET structure, the on-state voltage
of the collector (source)-base (drain) –pn –junction. The bipolar current flow
through this diode determines the on-state behavior of the MOSFET in reverse direction when the channel is closed. If the channel is additionally controlled while
the bipolar inverse diode is conducting, it will result in a lower on-state voltage than
for a simple parallel connection diode and MOSFET, since the injected charge car-
28
riers laterally diffuse as well, thus improving MOSFET conductivity.” (Semikron,
2015)
“If the drain-source voltage is externally limited, e.g. by connecting a schottky diode in parallel, to values below the threshold voltage of the inverse diode, the inverse current will remain a unipolar electron flow from drain to source. Consequently the switching behavior corresponds to that of a MOSFET. The inverse current depends on -VDS and VGS.” (Semikron, 2015)
“The switching behavior of MOSFET power modules are determined by their structural, internal capacitances and the internal and terminal resistances. Contrary to
the ideal of powerless voltage control via MOSFET gate, frequency-dependent
control power is required. This is owing to the recharge of the internal capacitances which is needed for switching. Furthermore, the commutation processes are effected by the parasitic connection inductances present in the components and
connections and generated by connecting transistor chips in power modules. They
induce transient overvoltages and may cause oscillations due to the circuit and
transistor capacitances.” (Semikron, 2015)
In the present, SiC power MOSFET modules with nominal breakdown voltages up
to 1200 V and nominal continuous currents up to 300 A can be found.
3.5
IGBT
Insulated-gate bipolar transistor (IGBT) is a three-terminal power semiconductor
device with vertical structure as shown in Figure 3.8a.
“When sufficiently high positive control voltage is applied between gate and emitter, an n-conducting channel is formed within the p-region below the gate terminal.
This channel conducts electrons from emitter through the n —drift area to the bottom terminal, where they deplete the charge carrier region. As soon as electrons
enter the p + area of the collector, holes will be injected from the p + area to the n area. The injected holes will flow directly from the drift area to the emitter-p –
contact. Thus, the n—drift area is flooded with holes; this charge carrier enhancement conducts the biggest part of the main current. The main current depletes the
29
charge carrier region, which results in a decline in collector-emitter voltage. This
means that IGBT are bipolar components.” (Semikron, 2015)
Figure 3.8, NPT-IGBT cell structure with parasitic elements a) in cellular structure, b) on
equivalent circuit (Semikron, 2015, p. 46)
As can be seen on the Figure 3.8b, “the equivalent circuit diagram of the IGBT
shows, apart from internal capacitances and resistances, an “ideal MOSFET”, an
NPN-transistor at the gate side and a PNP-transistor at collector side. The NPNand PNP-transistors form a thyristor circuit, which causes latch-up, when the condition
(p +⁡ n ) = 1, where p , n = TE
(3.7)
where M is multiplication factor, T is base transport factor, and E is emitter efficiency, is met. The latch-up would lead to a loss of IGBT controllability and to its
destruction. Appropriate design measures will reliably prevent latch-up in modern
IGBT types under permissible static and dynamic conditions.” (Semikron, 2015)
“If a positive collector-emitter voltage VCE and a gate-emitter voltage VGE is applied
below the gate-emitter threshold voltage VGE(TH), only a small collector-emitter cutoff current ICES flows between collector and emitter terminal. When VCE rises, ICES
increases slightly at first. Above a specified, maximum rated collector-emitter volt-
30
age VCES, there will be an avalanche breakdown of the PIN –junction p+ -well / ndrift area / n+ epitaxy layer (collector-emitter breakdown voltage V(BR)CES).”
(Semikron, 2015)
“The forward on-state at a positive collector-emitter voltage VCE and positive collector current IC comprises of characteristic curve areas, active region and saturation
region.” (Semikron, 2015)
“In active region, with a gate-emitter voltage VGE that hardly exceeds the gateemitter threshold voltage VGE(TH), a relatively high voltage share will be depleted
through the channel owing to current saturation. The collector current is controlled
by VGE. As a measure for the transfer behavior the forward transconductance gfs is
defined as
 = ⁡
∆
∆
=⁡

 −(ℎ)
.
(3.8)
Forward transconductance rises in proportion to the collector current IC and the
collector-emitter voltage VCE, and falls as the chip temperature increases. In the
switching mode the active region is only run through during turn-on and turn-off.
Stationary module operation in the active region is not permissible, because VGE(TH)
falls when temperature rises, meaning that even small differences between the individual chips may cause thermal instability.” (Semikron, 2015)
“The saturation region, which corresponds to on-state during switching operations,
has been reached when IC is solely determined by the outer circuit. The on-state
behavior is characterized by the residual voltage VCE(sat) (collector-emitter saturation voltage) of the IGBT. In the majority of modern IGBT structures VCE(sat) rises in
proportion to the temperature. Only for IGBT designed to the punch through (PT)
concept will VCE(sat) decline in the rated current range as the temperature increases.” (Semikron, 2015)
“In the reverse operation, the PN –junction of the IGBT at the collector side is
poled in reverse direction. The permissible voltage of this PIN –diode is no more
31
than a couple of tens of volts. Today, reverse blocking IGBTs are therefore
equipped with fast series connected diodes, whereas reverse conducting IGBTs
used in standard applications are equipped with fast, antiparallel diodes. Thus, the
on-state features of IGBTs in inverse operation exclusively result from the properties of these diodes.” (Semikron, 2015)
“The switching behavior of an IGBT is determined by their structural, internal capacitances and the internal and external resistances. Contrary to the ideal of powerless voltage control via the MOS-gate, frequency-dependent control power is required owing to the recharge currents of internal capacitances which is needed for
switching. Furthermore, the commutation processes are affected by the parasitic
connection inductances present in the components and connections and generated by connecting transistor chips in power modules. They induce transient overvoltages and may cause oscillations due to the circuit and transistor capacitances.”
(Semikron, 2015)
The nominal values of the present day IGBTs range to continuous collector current
values up to several hundreds of amperes and collector-emitter voltages up to
6.5kV, though with higher voltage ratings the collector currents are lower. By paralleling single chips in a module, higher current ratings can be achieved. Typically,
the IGBTs can be switched at the rates of several kHz.
3.6
Choosing switching components for a static switch
The static switch in discussion in this thesis is used on a three-phase VFI UPS
rated for 380V/400V/415V and 20 kVA (Eaton, 2015b), where it can be used also
in energy saving mode to minimize UPS losses by bypassing the rectifier and inverter portions of the circuit, i.e. the double conversion. Due to this, the components used on it should have minimal conduction losses to reach maximum efficiency.
Other matters to discuss are component costs, turn-off time, and behavior in
emergency situations, such as overcurrent and undervoltage. Switching losses are
negligible while considering a static switch due to relative rarity for the need of
32
switching. When discussing component choices, the properties are compared to
currently used thyristor to determine if they would be an improvement to the system. Also system-scale control methods are taken in to consideration. The considered possible component types have been introduced above.
To be able to compare components, some specifications need to be set. Nominal
per phase current for the aforementioned UPS can be calculated using equation
3.9
rms,phase = ⁡
nom
nom √3
,
(3.9)
where nom is rated power and nom is rated phase to phase voltage. Using lowest
rated nominal voltage, we get per phase current rms,phase ≈ 30.4⁡, which is used
as baseline to select components. The datasheet of the device also specifies, that
it is able to handle 125% overload indefinitely and 1000% overload for 20 ms, so
the components need to be able withstand a continuous overload current OL =
1.25rms,phase ≈ 38.0⁡indefinitely, and a short circuit current sc = 10rms,phase =
304A⁡ for 20 ms, and these values are also considered while choosing components.
Another thing to consider while choosing the components is the voltage withstand
capability. IEC 62040-2 standard (IEC, 2016) specifies, that a UPS shall be able to
withstand voltage surge of 1 kV, so I’ll be using that as a baseline while considering component voltage withstand capability. Selected components should be able
to withstand this voltage both forward and reverse biased.
While considering conduction losses on switching components, there are two main
features to focus on: the forward on-state voltage drop and on-state resistance.
Semiconductor devices have a characteristic on-state voltage drop, which remains
unchanged regardless of the current flowing through. On the other hand, all electrical components have some internal resistance, which in the case of switching
devices, is given as on-state resistance. Losses due to this resistance grow larger
as the current gets higher. Total on-state voltage drop due to both of these fea-
33
tures is usually presented as graph on the component datasheet. Total on-state
power loss on 3-phase system can be calculated using equation 3.10.
f,loss = ⁡3f rms,phase ,
(3.10)
where Vf is on-state voltage drop. With these specifications I looked for feasible
components to be used in a static switch. First I’ll be considering their technical
feasibility on this application, and after that I’ll reflect that on the financial viability.
Other than the thyristor currently in use (Semikron, 2008), the GTO and IGCT
where left out due to the fact that all the available components were designed for
much higher power ratings. There were two component types available that fulfilled the aforementioned specifications, IGBT and silicon carbide MOSFET. Regarding the continuous current withstand capability, both component types needed
to be heavily overrated to be able to withstand the overload current sc .
For these components, the continuous Drain-Source -/Collector-Emitter –current of
300 A was chosen due to the fact that these component types can’t handle large
overcurrent without damaging the component. Most of the components that fulfill
this feature are also capable of withstanding forward biased voltages up to 1200 V,
which in turn fulfills the voltage withstand capability requirement.
The chosen components for comparison for the IGBT is Infineon FS300R12KE3
module (Infineon, 2013) and for the MOSFET Cree CAS300M12BM2 module
(Cree, 2014). Both modules are packed in half-bridge configuration with antiparallel freewheeling diodes. Neither of the modules has any notable reverse blocking
voltage capability, so they need a reverse blocking diode in series with them to be
able to withstand AC-voltages while the static switch is turned off. The configuration needed in static switch usage can be seen in Figure 3.9.
34
Figure 3.9, Needed configuration for components in static switch with a) MOSFET, b) IGBT
The needed configuration increases the total forward voltage drop due to current
flowing through two components while in forward conducting state. The on-state
voltage drop Vf for a diode rated at 1200 V and 30-40 A varies between 1.1 V and
1.3 V. At the nominal current, the total forward voltage drop and total power loss
calculated using equation 3.10 for each component type is shown in Table 3-1.
Table 3-1, On-state voltage drops and total power losses on a static switch using different
components
Component
Total
on-state
voltage Total power loss on nom-
drop on nominal current inal current [W]
[V]
Thyristor
1.2
109
IGBT
1.9-2.1
173-191
SiC MOSFET
1.3-1.5
119-137
As we can see from the table above, the currently used thyristor has the lowest onstate voltage drop and due to that the lowest power loss.
The semiconductor device costs to realize a static switch using aforementioned
modules are shown in Table 3-2.
35
Table 3-2, Total costs of semiconductor devices to implement a 3-phase static switch with
different switching components
Component
Cost / 3-phase static switch [€]
Thyristor
~30
IGBT
~300
SiC MOSFET
~1800
As we can see from the tables above, it is easy to understand why all the current
static switches used in UPS equipment are implemented with thyristors. Due to the
lower losses and costs, the only downfall of the thyristor is slower turn-off time.
Turn-off time is only an issue when a UPS switches from bypass or energy saving
mode to double conversion and might occur only when doing maintenance on the
UPS or having problems with the source of supply.
Considering the facts mentioned above, I’d say the best choice of component on
this power scale static switch is the thyristor. The IGBT is not a viable choice due
to higher total losses and increased semiconductor costs. SiC MOSFETs might be
a viable alternative for the switching component if their prices come down in the future, but due to it being a rather new technology, it might take years or even decades to it become reasonably priced for this usage.
36
4. CONTROL CHALLENGES
4.1
Simulation model
To determine if there are ways to improve static switch functionality by control
methods, a simulation model of a UPS was made using Mathworks’ Simulink with
Simscape Power Systems toolbox. Eaton 93PS 20 kVA UPS (Eaton, 2015b) was
used as the basis of the simulation. The model was simplified by leaving out the
AC/DC –converter and energy storage found in the system. The model has the following parts after simplifications: the AC –grid, static switch, inverter and load.
The AC –grid is modeled as a three-phase voltage source connected in series with
RL-circuit which simulates grid impedance. The grid impedance is calculated so,
that its prospective short circuit current corresponds that defined in the standard
IEC 61000-3-12 (IEC, 2011b). The model has a possibility to simulate AC –grid
abnormalities, e.g. over- and undervoltage, short circuit, and open circuit, during
simulation. The frequency of the grid could be controlled, but was chosen to be
static 50 Hz to simulate the commercial power grid used in Finland.
The static switch is simulated as two antiparallel thyristors per phase, as seen in
Figure 2.4Error! Reference source not found.. Each thyristor pair has its own
gate control.
The inverter is modeled as controllable current source in parallel with the output of
the static switch. The model uses a certain transfer function to convert the voltage
reference to a current reference. The maximum output voltage of the inverter is the
nominal peak line-to-neutral (LN) voltage, and maximum instantaneous output current is limited according to real hardware to 72 A. The inverter can be turned on
and off using an external signal. Unlike in the real system, in the simulation each
phase can be controlled separately. The inverter model was given for my use by
Eaton Power Quality Oy.
37
The load is modeled as series RLC-circuit with adjustable power factor and apparent power rating. The model has the possibility to swap between different load
types during the simulation, or to leave the load open circuited.
The datasheet of the 93PS defines that the load power factor cos⁡() should be between 0.8 inductive to 0.8 capacitive on full load. All the control methods proposed
in this thesis should be able to work with power factors of that and higher. Typical
industrial loads, e.g. electric motors, fall between the limits and they have standards to limit their power factor, but with smaller devices there are no such standards. Their power factors may get a lot lower, even as low as 0.3, but this mainly
due to their large harmonic content (Uusitalo, 2016-2017).
To make sure that the possible control methods work on standard limits and other
common loads, I’ll be testing them with power factors from 1.0 down to as low as
0.3. The loads used in simulations are shown in Table 4-1.
Table 4-1, Loads used in simulations
cos⁡() 1
0.8
0.5
0.3
Load [pu]
1.00
UV/OV
UV/OV
UV/OV
UV/OV
0.50
UV/OV
UV/OV
UV/OV
UV/OV
where UV stands for “Undervoltage simulation” and OV stands for “Overvoltage
simulation”
I will also be using a 3-phase core-type transformer magnetic model provided in
Power Systems Toolbox, which takes into account the physical and magnetic
properties of the transformer, to simulate transformer behavior. The windings can
be connected in delta- or wye –configuration on both primary and secondary side
of the transformer. The model is configured using a 20 kVA transformer as a reference, and the parameters used to configure the model can be found in Appendices
A and B. The transformer model is saturable, but does not have its hysteresis
modeled. The load model mentioned above can be used to load the transformer.
38
There are also four current and voltage measurement points, one to measure static switch input, one to measure total output of the UPS, one to measure inverter
output, and last to measure transformer secondary output. Each Voltage measurement can be set as line-to-line (LL) or line-to-neutral (LN) measurement.
All the initializations for the simulation are made in a MATLAB script, excluding
changing some minor control signal generators, e.g. switching between step and
stair signal generators to control static switch gates. This makes it easier to
change values between several different simulation cases.
Some adjustments were needed, compared to the real system, to make the simulation model work in desired manner. All the switching components and inductances in the model are modeled as current sources, so they need a high-valued resistance in parallel with them to work when connected in series with other current
source models. The large resistances on the other hand make the system have
both fast and slow time constants, which might make the simulation run slower. To
compromise between speed and accuracy, parallel resistances were chosen to be
about 2 orders of magnitude larger than the nominal load impedance.
The Simulink solver also had a major impact on the performance of the simulations. The ode23tb –solver was chosen to be used as it had the best performance
in solving the simulated system in general.
4.2
Turn-off Time
When the UPS is feeding the load via the static switch, i.e. is on bypass or energy
saving mode, the output power quality can’t be controlled. Due to this, the load is
exposed to all the abnormalities in the AC source, e.g. frequency fluctuation, overand undervoltage. Some electronic loads are really sensitive to the fluctuations
from nominal values, and thus the UPS should swap from the static switch to double conversion to maintain power quality. On a traditional static switch with thyristors, the turn-off can take up to 10 ms on a 50 Hz system and 8.33 ms on a 60 Hz
system. This might prove fatal on the most sensitive equipment, and minimizing
the length of abnormal power conditions diminishes the possibility of damage to
the load. 50 Hz is used in simulations due to longer possible commutation times.
39
4.2.1 Thyristor turn-off time minimization on AC-source undervoltage
The standards IEC 60364-5-52 (IEC, 2009) and EN 60038 (EN, 2011) define, that
the AC grid can have a maximum undervoltage of 15 % under the nominal voltage.
If the load is protected with a class 1 UPS, this is the lowest voltage where the
static switch should be turned off and the UPS should switch for to doubleconversion or back-up power to maintain power quality. Thus in simulations I’ll be
using a 20% undervoltage to make sure that the possible control works properly on
conditions defined in the standards.
During grid undervoltage, due to the fact that the inverter can generate a higher
voltage than the grid peak voltage, the inverter can be used to force thyristors to
commutate at any moment after the undervoltage is detected. This can be
achieved by giving the inverter a voltage reference of the peak nominal voltage for
a short time. The polarity of the reference voltage peak should be the same as the
polarity of the current at the moment, i.e. if grid current is negative, negative voltage reference should be used. This is to eliminate possible inverter backfeed to
the grid.
The simulations were run with pulse start time steps of 1 ms for one phase period
per load type, i.e. 20 simulations per load type. Pulse time was chosen to be 1 ms.
The longest simulated commutation time of thyristors was 520 µs. The longest
turn-off time was achieved with nominal, resistive load. If implemented on real
hardware, turn-off times might get longer, so a longer pulse might be needed.
I’ll propose a following control logic to minimize undervoltage turn-off time, based
on the simulation results:
1. Detect undervoltage
2. Stop thyristor gate pulses
3. Measure polarities of the input currents
4. Turn on inverter and give it at least 550 µs long nominal peak LN voltage
reference with same polarity as the current.
5. Continue inverter operation in normal online-state
40
Due to the simplicity of the proposed control logic, the simulations ran smoothly
without any problems. The same methods works on both three-wire and four-wire
systems due to the fact that the control itself doesn’t need any voltage measurement.
4.2.2 Thyristor turn-off time minimization on AC-source overvoltage
The standard EN 60038 (EN, 2011) defines, that at commercial AC grid can have
a maximum overvoltage of 10 % over the nominal voltage. If the load is protected
with a UPS, this is the highest voltage where the static switch should be turned off
and the UPS should switch for the double-conversion to maintain power quality. In
simulations I’ll be using a 15 % overvoltage to make sure that the possible control
works properly on conditions defined in standards.
A similar approach was chosen to minimize thyristor turn-off time on overvoltage
as with the undervoltage. The only difference in this case is that inverter can’t always generate higher voltages than there is on the grid. If Overvoltage detection
happens during these times, the start of the pulse needs to be delayed until the
grid instantaneous voltage drops below nominal LN peak voltage. A three-wire
and a four-wire system need a somewhat different approach due to the difference
in voltage measurements. It’s also noteworthy that the whole pulse needs to be of
a higher voltage than the grid voltage, or otherwise the polarity of the current might
change, possibly increasing the turn-off time due to inverter backfeeding the grid.
This might happen on the first and third voltage quadrant, if the voltage pulse is
started too late, and on the second and fourth quadrant, if the pulse is started too
early. To ensure that this doesn’t happen, the highest LN voltage when the pulse
can be safely triggered on the first and third voltage quadrant can be calculated
using equation 4.1, assuming that the overvoltage is sinusoidal.
1
limit = ⁡ peak ∗  ∗ sin⁡(sin−1 ( ) − 2πpulse ),

(4.1)
where peak is nominal LN peak voltage,  is overvoltage multiplier, pulse is the
length of the voltage pulse, and f is AC-frequency. If using an overvoltage of 15 %
41
and pulse length of 1 ms, we get limit ≈ 0.78peak , which happens at phase angle
low = 0.74 + π⁡. To minimize the risk of false voltage triggering, the multiplier should be a little lower, so in simulations I’ll be using voltage limit limit =
0.77peak , which means phase angle low = 0.74⁡ + π⁡⁡ . On the second and
fourth quadrant the earliest point when the pulse can be triggered is when the instantaneous voltage is below peak , which means phase angle high = 2.09⁡ +
π⁡⁡.
The simulations were run with pulse start time steps of 1 ms for one phase period
per load type, i.e. 20 simulations per load type. Pulse time was chosen to be 1 ms.
The longest simulated thyristor commutation time of thyristors on all simulation
runs was 5.1 ms, which is about half of the worst-case self-commutation time. The
longest turn-off time was achieved with nominal load with power factor cos() =
0.8.
It’s also noteworthy, that when delaying the start of the pulse, on some loads thyristors might self-commutate due to natural current zero-crossing, which in turn
forces the voltage to zero. So if current zero-crossing happens while waiting for the
pulse, it’s safe to turn on that phase of the inverter, and would be advisable to minimize the power downtime on one of the phases.
I’ll propose a following control logic to minimize overvoltage turn-off time on a fourwire system, based on the simulation results:
1. Detect overvoltage
2. Stop all thyristor gate pulses
3. Log input currents at the overvoltage detection
4. Measure input LN voltage phase angles and amplitudes
a. If on 1st or 3rd quadrant and voltage lower than limit , set a
flag for safe inverter starting
b. If on 2nd or 4th quadrant and voltage lower than peak , set a
flag for safe inverter starting
c. Else keep safe inverter starting flag cleared
5. Measure input currents
42
a. If safe inverter flag set, go to 6
b. If safe inverter start flag not set and current hasn’t changed
polarity (i.e. no current zero-crossing happens), go to 4
c. If safe inverter start flag not set and current changes polarity
(i.e. current zero-crossing happens), go to 7
6. Turn on inverter and give it at least 1 ms long nominal peak LN
voltage reference with same polarity as the current.
7. Continue inverter operation in normal online-state
When discussing a three-wire system, LN voltages can’t be measured directly, only the LL voltages. It’s known that LL voltages lead the LN voltages by π/6 rad.
Thus the phase angle interval where turning on the phases isn’t allowed can be
calculated by adding π/6 rad to the low and high values. The phase angles can
be detected if the system has a PLL on input voltage.
This leads to following control method for three-wire system:
1. Detect overvoltage
2. Stop all thyristor gate pulses
3. Log input currents at the overvoltage detection
4. Measure input LN voltage phase angles and amplitudes
a. If voltage phase is low < ⁡⁡ < ⁡ high , keep safe inverter
starting flag cleared
b. Else set safe inverter starting flag
5. Measure input currents
a. If safe inverter flag set, go to 6
b. If safe inverter start flag not set and current hasn’t changed
polarity (i.e. no current zero-crossing happens), go to 4
c. If safe inverter start flag not set and current changes polarity
(i.e. current zero-crossing happens), go to 7
6. Turn on inverter and give it at least 1 ms long nominal peak LN
voltage reference with same polarity as the current.
7. Continue inverter operation in normal online-state
43
The same control method also works for the four-wire systems, so this is the preferable method to be implemented.
The control logic simulations had some problems on the connectivity with the inverter model, and the overvoltage simulations had to be run in two parts. First I
had to run a simulation without turning on the inverter model, to get calculated values for the inverter switch-on times. Then I had to hardcode those calculated
switch-on times to the model. This increased the total overall time to conduct the
simulations, but shouldn’t make any difference on the functionality of the proposed
control logic.
4.3
Transformer Inrush Current Elimination
A transformer is an electrical device that transfers electrical energy between circuits through electromagnetic induction. Transformers are used to increase or decrease AC voltage levels, or to produce galvanic isolation between circuits, or
both.
Generally a power transformer consists of “two or more windings of wire wrapped
around a ferromagnetic core. These windings are not electrically connected, but
they are magnetically coupled, i.e. connected by the magnetic flux present within
the core. One of the windings, the primary winding, is connected to a AC source.
The second winding, the secondary winding, supplies electric power loads. If the
transformer more than two windings, the additional windings (tertiary windings) are
also used to supply loads or work as a tank circuit in ferro-resonant designs. The
electrical load received by the primary winding is converted into magnetic energy
that is reconverted back into electrical energy in the secondary and possible tertiary windings.” (Georgilagis, 2009)
“If the primary voltage of the transformer is lower than the secondary voltage, the
transformer is called step-up transformer. If the primary voltage is higher than the
secondary voltage, the transformer is called step-down transformer. The trans-
44
formers are classified into various categories, according to their use, cooling
method, insulating medium, and core construction.” (Georgilagis, 2009)
“In the context of transformers, the importance of magnetic materials is twofold.
First, through their use it’s possible to obtain large magnetic flux densities with relatively low levels of magnetizing force. Second, since magnetic materials can be
used to constrain and direct magnetic fields, they are used to maximize the coupling between the windings as well as to lower the excitation current required for
transformer operation.” (Georgilagis, 2009)
The relationship between magnetic field density H and magnetic flux density B for
magnetic materials is nonlinear. In general, the characteristics of the material cannot be described analytically, and are more commonly presented in graphical form.
The graphs are based on empirical measurements of test samples of the material,
and the most commonly used curves are the B-H –curve and hysteresis loop.
“(Georgilagis, 2009)
For the ferromagnetic material, the following relationship holds:
 = ⁡,
(4.2)
where  is the permeability of the ferromagnetic material. The permeability can be
expressed as follows:
 = ⁡ 0 r ,
(4.3)
where r is the relative permeability of the material and 0 is the permeability of
the free space with constant value of 0 = 4π ∗ 10−7 ⁡H/m. The relative permeability of the material varies with magnetic flux density. (Georgilagis, 2009)
The magnetic field in the core is produced by the primary winding of the transformer. The source of this magnetic field is magnetomotive force, which can be
expressed as follows:
45
ℱ = ,
(4.4)
where N is number of winding turns and i current of the winding. Ampere’s law
states that the line integral of the magnetic field intensity H around a closed path is
equal to net current enclosed by that path:
ℱ = ⁡ ∮ .
(4.5)
Assuming that the magnetic flux density B is uniform across the core section area,
the line integral of H is
∮  = c c ,
(4.6)
where c is the magnitude of H along mean flux path, and c is the average length
of said path.
The magnetic flux  crossing an area is the surface integral of the magnetic flux
density:
 = ⁡ ∮ .
(4.7)
“According to field theory, all the flux that enters the surface enclosing a volume
must leave that volume over some other portion of that surface, because magnetic
flux lines form closed loops. If magnetic flux outside the core is neglected, then
equation 4.7 reduces to following form:
c = ⁡ c c ,
(4.8)
where c is the magnetic flux in the core, c is the magnetic flux density in the
core, and c is the cross section area of the core.” (Georgilagis, 2009)
46
Supposing that permeability  of the core material is constant, and since the magnetic flux density is uniform, the following expression is obtained from equation 4.2
for calculation of c :
c = ⁡c .
(4.9)
Solving equation 4.9 for c gives:

c = ⁡ c .
(4.10)

Solving equation 4.8 for c gives:
c = ⁡
c
c
.
(4.11)
If we substitute equations 4.11 and 4.10 into 4.6, we obtain:
ℱ = ⁡ c c =
c

c = ⁡
c c
c
.
(4.12)
The reluctance c of the magnetic core is defined from the following:
c = ⁡
c
c
.
(4.13)
Substituting 4.13 into 4.12 we obtain:
ℱ = ⁡ c c .
(4.14)
The rated power of a transformer is the output that can be delivered at rated secondary voltage and frequency without exceeding the specified temperature rise
limitations. The rated power n of the three-phase transformer is calculated using
following equation:
n=⁡√3n n ,
(4.15)
47
where n is rated voltage and n is rated current of the transformer. Similarly, the
rated power of the single-phase transformer is calculated by following equation:
n = ⁡ n n .
(4.16)
The efficiency of any electrical machine is defined as the ratio of the useful power
output to the total input power, i.e.
 =⁡
out
in
=
out
out +losses
.
(4.17)
In transformers, the losses consist of constant “no-load losses and load dependent
load losses. No-load losses, or excitation losses, are incident to the excitation of
the transformer. They include core loss, dielectric loss, conductor loss in the winding due to excitation current, and conductor loss due to circulating current in parallel windings. Load losses are incident of a specified load. They include loss in the
current carrying parts (e.g. windings, leads), eddy losses in conductors due to eddy currents, and stray loss induced by leakage flux.” (Georgilagis, 2009)
“Generally transformers have efficiency from 95% to 99%. This means that the
transformer changes one AC voltage level to another while keeping the input power practically equal to the output power.” (Georgilagis, 2009)
“The vector group of the transformer determines the phase displacement between
the primary and secondary winding. The primary and secondary windings can be
connected in different ways in order to have a three phase transformer. These
connections are delta (D or d), star (Y or y), and zigzag (Z or z). The uppercase
letter annotates primary winding type, lowercase letter secondary winding type.
There might be additional marking for existing neutral connection outside the
transformer (N or n) and phase displacement.” (Georgilagis, 2009) E.g. ZNd0 has
zigzag primary winding with neutral connection, delta secondary winding, and
phase displacement of 0.
48
“In magnetic circuits with windings, when the magnetic field in the core varies in
time, an induced voltage v is produced at the terminals, which is calculated by
Faraday’s law
=


,
(4.18)
where N is the number of turns and  is time varying magnetic flux.” (Georgilagis,
2009) The terminal voltage usually easier to measure than the magnetic flux, so
solving  from equation 4.18 gives:

 = ∫ .

(4.19)
Inrush current is the current transient that occurs when an electrical device is first
turned on. When discussing transformers, the inrush usually manifests as an instantaneous current peak value, and it is caused by the residual magnetic flux that
has remained in the transformer core during previous de-energization of the transformer.
Transformers may draw a transient current up to 10-15 times larger than the rated
current when first energized. The normalization of the current waveform after initial
peak takes several cycles. A simulated waveform of inrush peak on a three-phase
transformer can be seen in . Toroidal transformers, which use less copper to
achieve same power rating, can have inrush currents up to 60 times larger than
rated current. For one-phase transformers, the worst inrush currents happen if the
device is energized on primary voltage zero-crossing and if the polarity of the voltage half cycle is the same as the polarity of the remanence in the iron core
(Dobrogowski, 2009).
The three-phase transformers act a bit differently due to their physical construction. There are two basic core constructions for a three-phase transformer, threelegged (core-type) and five-legged (shell type). With three legged build the magnetic flux must flow through the other two legs and the flux also flows through the
windings of the other phases. With five legged build the fluxes have a free return
path through the external legs.
49
Figure 4.1, Simulated transformer inrush current of a three-phase 20 kVA transformer on
nominal load
The problem that arises from short inrush currents is choosing proper overcurrent
protection devices, such as circuit breakers and fuses. The protection should be
able to react quickly to overload or short circuit faults, but shouldn’t break the circuit when the usually harmless inrush current flows.
The remanent flux in the core-type transformer typically form a pattern with near
zero flux in one phase and plus and minus finite value in other two. The remanent
flux can assume values up to 85% of the peak normal flux, but are typically in
range of 20% to 70%. It can also be shown that the remanent flux in cores of three
phase transformer must inherently sum to zero (Brunke, 1998).
There has been some previous research regarding elimination of the inrush current on power transformers using controlled switching methods. Brunke (Brunke,
50
2001, 2001b) proposed three different methods to eliminate inrush on an unloaded
power transformer. All methods include calculating remanent flux during the
transformer de-energization, and then closing transformer phases using circuit
breakers so that remanent fluxes match the dynamic flux in the transformer
phases.
The first method, rapid closing startegy, closes one phase first and remaining two
within a quarter cycle, and requires knowledge of the remanent flux in all three
phases. The second method, simultaneous closing strategy, closes all three
phases at the same time. This method requires knowledge of the remanent flux on
all three phases, a flux pattern that follows the traditional pattern, and the two of
the remanent fluxes are high. The third method, delayed closing strategy, closes
one phase first ant the remaining two phases 2-3 cycles later. This effectively
eliminates the remanent flux on the latter two phases, and knowledge of remanent
flux on only one phase is needed. The transformer in discussion is of type Ygd,
and the model uses three one-phase transformer cores, not a single core. (Brunke,
2001)
When discussing transfomers used with UPS devices, the most common type is
Dyn11 isolation transformers that can be used either on the input or the output of
the UPS (Uusitalo, 2016-2017). The primary delta-winding creates a situation
whereby all the transformer phases can’t be energized independently. The first
transformer phase can be energized by closing two related electrical phases. This
also causes the other two transformer phases to energize with half the voltage.
Closing of the remaining electrical phase causes the last two transformer phases
to fully energize. The commonly used delta primary transformers have a shared
three-legged core, not three separate cores, enabling the magnetic interaction
between phases.
The UPSs also don’t usually connect the power for an output transformer during
energization with circuit breakers, but with the static switch. The UPSs power
electronics are not used for this, because they usually have limits for the output
current. The static switch can usually handle the inrush currents caused by the
51
transformer without breaking, but the excess currents can still affect the lifetime of
the components, e.g. fuses.
The static switch commutation might affect how the remanent fluxes behave during
the transformer de-energization. On the other hand, the static switch can be closed
much more precisely at the desired moment compared to circuit breakers.
Regarding the transformer secondary loads, the transformer might not always be
unloaded when energizing or de-energizing the transformer. As the UPS is meant
to be backup power source, the transformer might experience short blackouts
while partially or fully loaded, and the re-energization might therefore also happen
when load is connected. The varying load conditions might have some effect on
the remanent flux on the transformer core by affecting the voltage behaviour.
Due to the transformer model not having a hysteresis model, the effect of the load
on the remanent flux can not be simulated accurately. The remananent flux during
re-energization can still be simulated due to the model having the possibility to
initialize the magnetic fluxes on the system. Initial simulations regarding reenergization of the transformer can be conducted assuming the remanent fluxes
follow the typical pattern described above.
The transformer parameters used in simulations are from a real 20 kVA core-type
isolation transformer from Trafox, and the parameters can be seen in Appendix A.
The transformer represents a generic isolation transformer of its power rating. The
material of the transformer core is SURA NO50, and its BH –characteristics can be
seen in Appendix B. The inverter model is disabled during these simulations to only consider usage of static switch on transformer inrush elimination.
To determine the effectiveness of the simulated control method, reference simulations need to be conducted. For these simulations, a nominal transformer load is
used, and first the transformer core is demagnetized, and second it’s magnetized
in traditional pattern with flux magnitudes of ϕrem = {0 -ϕpeak ϕpeak}. All three transformer phases are energized at the same time, so the only variable that can affect
52
transformer magnetization is timing of the energization. Inrush current peaks are
logged in pu, and can be seen in Table 4-2.
Table 4-2, Inrush current peaks in relation to triggering angle
Trigger angle
Current peak
Current peak with
related to
with demagnetfully magnetized
voltage AB [rad] ized core [pu]
core [pu]
0
2.67
4.21
π/12
3.23
3.75
π/6
3.50
3.06
π/4
3.43
2.35
π/3
3.21
1.73
5π/12
3.14
1.00
π/2
2.99
0.97
7π/12
2.74
1.20
2π/3
2.21
1.85
3π/4
2.40
2.87
5π/6
2.77
4.07
11π/12
3.09
5.09
π
3.21
5.88
-11π/12
3.18
6.34
-5π/6
3.45
6.49
-3π/4
3.38
6.44
-2π/3
3.21
6.93
-7π/12
3.11
7.20
-π/2
2.96
7.25
-5π/12
2.72
7.08
-π/3
2.20
6.66
-π/4
2.45
6.03
-π/6
2.82
5.22
-π/12
3.11
4.41
As we can see, with demagnetized core, the inrush peak varies between 2.2 pu
and 3.5 pu when the transformer core is demagnetized, and between 1 pu and
7.25 pu when the transformer core is fully magnetized. The phase difference between lowest and highest peak is π /2 with demagnetized core and π with magnetized core.
53
The rapid closing strategy seems to be the most lucrative method to be implemented on the system due to the fast reacting nature of the UPS systems. The
simultaneous closing strategy seems like it might be connected to the rapid closing
strategy, so a possibility of combining both into a single method is considered.
To test the validity of these methods, two simulation cases are conducted, one
with remnant flux pattern ϕrem = {0 0 0} with a delay of 1/4th of a period between the
energization of first phase and the other two, and second case with remnant flux
pattern ϕrem = {0 -ϕpeak ϕpeak}, where ϕpeak is peak value of dynamic flux, with simultaneous energization. The latter flux pattern shouldn’t be plausible in a real system, but it’s still conducted to ensure functionality on unlikely situations. The flux
patterns of these cases can be seen in Figure 4.2 andFigure 4.3.
Figure 4.2, Magnetic flux waveform using rapid closing strategy with remanent flux pattern
ϕrem = {0 0 0}
As we can see, the rapid closing strategy normalizes the waveform to the steady
state waveform with close to no deviation. The simultaneous closing strategy creates some deviation from the steady state waveform, but not large enough to
cause inrush peaks higher than nominal current, only a minor distortion in the current waveform, as seen in Figure 4.4.
54
Figure 4.3, Magnetic flux waveforms using simultaneous closing strategy with remnant flux
pattern ϕrem = {0 – ϕpeak ϕpeak}
Figure 4.4, Current waveforms using simultaneous closing strategy with remnant flux pattern ϕrem = {0 -ϕpeak ϕpeak}
In normal conditions, where one of the remanent fluxes is zero, the maximum value of other two fluxes is
rem,peak = peak ∗ |cos (rem,0 ±
2π
3
)|,
(4.20)
55
where zero is the electrical angle of the phase with zero remanent flux and peak
is maximum value of dynamic magnetic flux. When using sinusoidal waves, rem,0
= ±π/2, and maximum of the remanent flux gets value rem,peak ⁡ ≈ 0.866peak .
This value corresponds the maximum value mentioned in the literature (Brunke,
2001).
If none of the phases has zero remnant flux, it might be wisest to use the phase
with the lowest absolute remnant flux as a reference point. The voltage angle
where we get remnant flux on steady state can be calculated with
rem,0 =  (−
rem,0
peak
) + phase,0 ,
(4.21)
where phase,0 is phase shift of the phase with lowest absolute remnant flux. This is
the voltage angle where the first phase should be energized. The timing for other
two phases cannot be analytically solved. But if we know the magnitude of remnant flux in each phase, the timing to energize last two phases can be determined
by comparing total flux on both phases to the prospective fluxes. The prospective
fluxes can be calculated by integrating switch input voltage over time, and total flux
with
tot = rem,phase + ∫ phase ⁡,
(4.22)
where phase is the voltage over transformer phase coil. The optimal triggering angle is when the sum of the absolute differences between total fluxes and prospective fluxes is at its minimum, i.e.
 = ⁡ |tot,1 − prospective,1 | + |tot,2 − prospective,2 |
(4.23)
gets its minimum value. At this moment, the remnant fluxes on all three phases are
closest to the prospective fluxes, effectively eliminating the inrush currents.
56
To confirm the functionality of the control method, the logic was implemented in
the simulation model. The timing for the energization of the first phase is calculated during the initialization of the simulation, and the energization of other two
phases is timed by the simulated control logic. The remnant fluxes in the model
are initialized in a traditional pattern, but with the possibility of phase shifting all
three fluxes at the same time. This fulfills the inherent property of the sum of fluxes
being zero, while taking into account the cases when none of the fluxes is zero or
close to zero. The phase shift can have values between 0 and 2π rad, while the
magnitude of the fluxes can have values between 0 pu and 1 pu.
The simulations indicate, that the method described above effectively eliminates
inrush current peaks, when the remnant fluxes follow the inherent relation of summing to zero and the magnitudes have a phase shift of 2π/3 between each other.
This method also effectively combines the rapid closing strategy and simultaneous
closing strategy.
The final control method for inrush elimination goes as follows:
1. Detect turn-off signal, turn off thyristor gate pulses and calculate remnant
fluxes
2. Determine which phase has remnant flux closest to zero
3. Calculate turn-on electric angle for the detected and lagging phase
a. If ϕrem,leading > ϕrem,lagging, 0 = acos⁡(−
b.
Else, 0 = − acos (−
rem,0
peak
rem,0
peak
)⁡+ phase,0
) +⁡ phase,0
4. Save phase determined in step 2 along with calculated angle
5. When turn-on signal is received, turn on detected phase and lagging phase
at the calculated electric angle
6. When the minimum of Equation 4.5 is detected, turn on last phase
57
5. TESTING
The control method proposed in chapter 4.3 was implemented on an existing
Eaton 93PS –series UPS hardware using modified firmware, and the functionality
of the method was confirmed using test equipment. The software used to implement the modifications to the firmware was Code Composer Studio 7.0.0.00042
with TI Optimizing C-compiler C2000 V6.1.0, DSP/BIOS 5.41.13.42 and xdctools
3.22.04.46. The coding language used is C.
The modifications to the firmware were made using good coding practices. The
modifications made to the firmware won’t be published here due to it being intellectual property of Eaton Power Quality Oy. The implemented control method follows
the proposed method without interfering with the normal operations of the UPS.
Only the transformer inrush current elimination was implemented in the firmware.
This is because the modifications needed to implement the over- and undervoltage
commutation control would have taken too much time. Implementation of new control algorithms for the inverter would have been necessary, and also the internal
communication between power modules and external communication between devices would need vast modifications to the firmware. These modifications are also
outside the scope of the thesis, so it was decided to not implement them during
this thesis.
The test equipment consists of a 20 kVA Eaton 93PS –UPS, 10 kVA Dzn0 transformer and a 30kVA Dyn11 transformer, which were available at the time for testing purposes. The Dzn0 transformer is basically a Dyn transformer, but coils of
each phase are in two parts, and the other half is around different phase leg to
eliminate phase shift between primary and secondary voltages. The UPS used
400V/50Hz grid as its power source.
The output LN-voltage waveforms were captured using LeCroy Wavesurfer
44MXs-B –oscilloscope with voltage probes. The output current waveforms were
captured using LeCroy Wavesurfer 454 –oscilloscope with current clamps. The re-
58
quired LL-voltages, and therefore transformer phase fluxes, can be calculated from
the measured voltages.
For a load I was using the test laboratory’s water cooled resistive loads. The load
of each phase could be adjusted with the resolution of 1 kW, from 0 kW up to
63kW. Due to this, the measurements were made using total loads with 3 kW
steps.
The oscilloscopes were set up so, that both trigger at the same time and waveforms are time synced. The sample length was 10000 samples for both oscilloscopes. The sampling windows used were 200ms and 500ms, so the sampling
rates were 50 kHz and 20 kHz. Both are greater than the UPSs ADC interrupt rate
for voltage and current measurements, which is 4.5 kHz. This gives us some room
to filter the oscilloscope measurements if needed.
To have a reference point where to compare the results of the control method, a
set of four measurements per load level were conducted using currently implemented turn-off and turn-on commands of the UPS. This also shows whether or
not the simulation model functions similarly to the real equipment. The measured
peak currents can be seen in Table 5-1. The transformer used for these was the
10kVA Dzn0 transformer.
Table 5-1, Inrush peaks of the reference measurements
Load
9 kW
6 kW
3 kW
0 kW
#1
Current
[pu]
3.67
3.52
2.33
3.22
#2
Current
[pu]
2.97
2.10
5.35
3.60
#3
Current
[pu]
2.94
3.57
5.05
3.44
#4
Current
[pu]
1.95
2.44
2.33
3.30
The reference measurements show similar results to the simulations, the measured inrush current peaks vary between two to five times the nominal current peak,
whereas the simulated results varied between one to seven times. The slight dif-
59
ference might be explained by the physical and magnetic properties of the transformer, e.g. core material and size, and coiling, which causes difference in the
magnetic flux behavior.
A set of measurements was made to determine the behavior of the remnant fluxes
with different load levels, and to determine how long the primary voltages need to
be calculated to get accurate results on the remnant flux. To get a wider set for
reference, the 30 kVA Dyn11 transformer was used. The loads could be adjusted
with the same 1 kW resolution per phase, so the loads chosen for testing were
chosen to be between 0 kW and 21 kW in 3 kW steps. Loads over 21 kW were not
used so as not to overload the UPS too much. The UPSs static switch is able to
withstand the worst case inrush currents generated by the transformer used.
Each load level had 6 measurements, three with 200 ms total sample time, and
three with 500 ms total sample time. The flux waveforms for each load were compared to determine how long the voltage waveform needs to be integrated to get
the remnant flux values appropriately. It’s most likely that the noise of the voltage
measurement starts to affect the flux waveforms when the voltage levels get low
enough. At the same time, the relation of the load level to the remanent flux magnitude can be inspected.
When analyzing the magnetic flux waveforms, it was noted that the waveforms of
the same load level followed similar waveforms until the LL-voltages reached the
same level. After that the waveforms started to diverge with no apparent logic. This
is most likely, as suspected, due to the noise in the voltage measurements. The
moment when the voltages reach the same level is also most likely the point where
the voltage waveform needs to be integrated to get the amount of remnant flux left
in the transformer core.
This being said, the relation of load level to the remnant flux can be examined
when point of measurement is established. There seems to be a positive relation
to the magnitude of load level to the magnitude of remnant flux. With no load connected, the remnant fluxes are almost at zero, and with the 21 kW load the remnant fluxes get a magnitude of about 0.25 pu. The flux waveforms don’t follow the
60
traditional pattern in most cases, but seem to be somewhat phase shifted. Sum of
these is zero, as mentioned in the literature (Brunke, 2001). This means the control method proposed in Chapter 4.3 can be used as is.
The control method was then tested on the 10 kVA Dzn0 transformer. The load
level was changed to vary the remnant flux on the transformer core. The load level
was also changed between the de- and re-energization to simulate real-life situations where the load level might be changed e.g. while servicing equipment. The
remnant fluxes were monitored during the testing using the UPSs debugging functionality, and current and voltage waveforms were captured using the oscilloscopes.
The control method worked as expected. The current peaks never rose above the
nominal current peak level of the transformer. The highest remnant fluxes detected
were about 0.33 pu. Only one measurement, the load change from 9 kW to 3 kW,
out of the 16 showed some overshoot in relation to the rated current of the reenergization load, as seen in Figure 5.1. It should be noted that even though the
current waveform is slightly distorted, the voltage waveform remained sinusoidal,
as seen in Figure 5.2. It should also be noted that the highest current peak here is
below the nominal current rating of the transformer.
The control method should also be realizable with the other semiconductor switching components. The calculation of the remnant fluxes stays the same regardless
of the circuit opening method, and all semiconductor switching components are
capable of closing the circuit with similar accuracy similar to the thyristors. This
could be tested using the UPSs inverter to close and open the circuit. This won’t
be tested on the scope of this thesis due to need of excessive modifications needed on the UPS firmware.
61
Figure 5.1, Most distorted current waveform during re-energization
Figure 5.2, Voltage waveform, when the current waveform was most distorted
62
6. CONCLUSIONS AND SUMMARY
The goal of this thesis was to improve performance of the UPSs static switch by
the means of switching component technologies and control methods.
The plausible component technologies were compared to the thyristors currently in
use on the static switch. The goal was to determine, if there’s a more suitable
component type that could replace the thyristor. The aspects to be compared were
component losses, turn-off time, and power withstand capability. The costs of
components are also used to determine suitability. The turn-off time has the least
weight on the comparison. This is due to the fact, that need for quick turn-off is relatively rare on the lifespan of the device.
Only component type that can have an improvement over thyristors in performance are SiC MOSFETs. They have similar on-state losses and faster turn-off
times than thyristors, and largest components can withstand as high loads as the
thyristors within the 20 kVA scale. However, the current price of the switching
components makes them unsuitable to be used on the static switch. The price of
the switching components would be 60 times larger if the power withstand capabilities stayed the same, imposing a significant increase in overall cost of the device.
The plausible control methods to minimize thyristor commutation time were researched. The research was conducted using simulation model of a UPS on a 50
Hz power grid. A method to minimize thyristor commutation time from maximum of
10 ms to maximum of 1 ms when power grid undervoltage is detected was proposed. A method to minimize thyristor commutation time from maximum of 10 ms
to maximum of 5.1 ms when power grid overvoltage is detected was proposed.
The plausible control methods to eliminate a delta-primary 3-phase transformer
were researched. The research was conducted using simulation model of the
transformer and the static switch. A control method was proposed, that effectively
eliminates the inrush current of the transformer. The method was tested on a real
system and was proven to be as effective as in the simulated system.
63
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64
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65
APPENDICES
Appendix A
Transformer parameters for the simulation
Parameter
Value
Unit
Apparent power S
20
kVA
Frequency f
50
Hz
Primary/Secondary
400 / 400
V/V
Coil Resistance R
0.03507
pu
Coil Reactance X
0.02645
pu
193 / 106
r/r
60 x 110
mm x mm
330 x 370
mm x mm
Losses P0 / PCu
230 / 630
W /W
Connection Type
Dyn11
Voltage Uprim/Usec
Primary/Secondary
coil
turns
Core Cross Section
hxd
Core External
Dimensions h x w
66
Appendix B
Transformer core material (SURA NO50) BH –characteristics on the simulated transformer
B [T]
H@50Hz [A/m]
0.1
31.5
0.2
42.0
0.3
49.4
0.4
56.1
0.5
63.1
0.6
70.7
0.7
79.5
0.8
90.1
0.9
103
1.0
121
1.1
145
1.2
185
1.3
273
1.4
557
1.5
1520
1.6
3560
1.7
6730
1.8
11400
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