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TPS7A10
SBVS314 – MARCH 2018
TPS7A10 300-mA, Low VIN, Low VOUT, Ultra-Low Dropout Regulator
•
•
1
•
•
•
•
•
•
Ultra-Low Input Voltage Range: 0.7 V to 3.3 V
Ultra-Low Dropout for Minimum Power Loss:
– 150 mV (Maximum) at 300 mA (1.5 V VOUT)
Low Quiescent Current: 5 µA (Typical)
High PSRR: 40 dB at 1.5 MHz
Output Accuracy: 0.5% (Typical), 1.5%
Overtemperature
Available in Fixed-Output Voltages:
– 0.5 V to 3.0 V (In 50-mV Steps)
Packages:
– 1.50-mm × 1.50-mm WSON
– 0.78-mm × 1.13-mm WCSP-5
Active Output Discharge Available
2 Applications
•
•
•
•
•
•
Portable and Battery-Powered Equipment
Desktop, Notebooks, and Ultrabooks
eReaders, Tablets, and Remote Controls
Portable Consumer Products
Camera Modules
Set-Top Boxes and Gaming Consoles
The VBIAS rail that powers the internal circuitry of the
LDO draws very low current IQ (5-μA), and can be
connected to a power supply that is equal to or
greater than 1.4 V above the output voltage. The
main power path is through VIN, which can be a lower
voltage than VBIAS; this path can be as low as VOUT +
VDO, increasing the efficiency of the solution in many
power-sensitive applications. For example, VIN can be
an output of a high-efficiency, dc/dc step-down
regulator, and the VBIAS pin can be connected to an
Li-ion battery.
The TPS7A10 is stable with ceramic capacitors and
yields a dropout voltage of 90 mV (max) at a 300-mA
output load. In addition, the TPS7A10 is equipped
with the active pulldown feature that actively pulls
down the output to quickly discharge the outputs and
ensures a known start-up state.
The TPS7A10 is fully specified over the ambient
temperature range of TJ = –40°C to +125°C, and
uses a precision voltage reference and feedback loop
to achieve an overall accuracy of 1.5%
overtemperature. The device is available in a 5-pin
DSGBA, which is an ultra-small wafer chip-scale
package (WCSP), that makes the device suitable for
handheld applications. The TPS7A10 is also available
in a 6-pin WSON package.
Device Information(1)
3 Description
PART NUMBER
The TPS7A10 device is an ultra-small, low quiescent
current, low-dropout regulator (LDO) that can source
300 mA with outstanding ac performance (PSRR,
load, and line transient responses). This device has
an output range of 0.5 V to 3.0 V with a maximum
1.5% accuracy.
TPS7A10
PACKAGE
BODY SIZE (NOM)
WSON (6)(2)
1.50 mm × 1.50 mm
DSBGA (5)
1.13 mm × 0.78 mm
(0.35-mm pitch)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Preview package.
Startup Waveform
Typical Application Circuit
2.75
VBATT
2.5
2.25
2
CBIAS
Voltage (V)
1.75
1.5
1.25
1
IN
0.75
0.25
VIN
VOUT
0
OUT
Standalone
DC/DC
Converter
or PMU
0.5
VBIAS
VEN
BIAS
1.5 V
IN
OUT
TPS7A10
CIN
EN
1.2 V
VCORE
COUT
GND
-0.25
0
100
200
300
400 500 600
Time (µs)
700
800
900 1000
GND
VEN
D014
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
ADVANCE INFORMATION
1 Features
TPS7A10
SBVS314 – MARCH 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
10.1 Layout Guidelines .................................................
10.2 Layout Examples...................................................
10.3 Recommended Layout for the YKA (DSBGA)
Package ...................................................................
10.4 YKA (DSBGA) Package Light Sensitivity..............
10.5 Thermal Considerations ........................................
19
19
20
20
20
11 Device and Documentation Support ................. 21
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Detailed Description .............................................. 9
7.1
7.2
7.3
7.4
ADVANCE INFORMATION
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
8.2 Typical Application .................................................. 17
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 19
Overview ................................................................... 9
Functional Block Diagram ......................................... 9
Feature Description................................................. 10
Device Functional Modes........................................ 11
Device Support ....................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
21
21
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
March 2018
*
Initial release.
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SBVS314 – MARCH 2018
5 Pin Configuration and Functions
DSE Package (Preview)
6-Pin WSON
Top View
YKA Package
5-Pin DSBGA
Top View
C3
OUT
1
6
C1
BIAS
EN
IN
B2
GND
NC
2
5
GND
EN
3
4
BIAS
A3
OUT
A1
IN
Not to scale
Pin Functions: DSE Package
NO.
I/O
DESCRIPTION
BIAS
4
I
BIAS supply voltage. This pin enables the use of low-input voltage, low-output voltage conditions, (LILO), (that
is, VIN = 0.7 V, VOUT = 0.5 V) to reduce power dissipation across the die. A 0.1-µF or larger ceramic capacitor
from BIAS to ground is required to reduce the impedance of the bias supply. Place the bias capacitor as close
as possible to the bias; see the Input and Output Capacitor Requirements section for more details.
EN
3
I
Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the device.
If enable functionality is not required, this pin must be connected to IN or BIAS.
GND
5
—
IN
6
I
NC
2
—
No internal connection. TI recommends connecting this pin to GND for thermal dissipation.
OUT
1
O
Regulated output voltage. A 2.2-µF or larger ceramic capacitor from OUT to ground is required for stability.
Place the output capacitor as close as possible to the output; see the Input and Output Capacitor Requirements
section for more details.
Ground pin
Input supply voltage. A 1.0-µF or larger ceramic capacitor from IN to ground is required to reduce the
impedance of the input supply. Place the input capacitor as close as possible to the input; see the Input and
Output Capacitor Requirements section for more details.
Pin Functions: YKA Package
PIN
I/O
DESCRIPTION
NO.
NAME
A1
IN
I
Input supply voltage. A 1.0-µF or larger ceramic capacitor from IN to ground is required to reduce the
impedance of the input supply. Place the input capacitor as close as possible to the input; see the Input and
Output Capacitor Requirements section for more details.
A3
OUT
O
Regulated output voltage. A 2.2-µF or larger ceramic capacitor from OUT to ground is required for stability.
Place the output capacitor as close as possible to the output; see the Input and Output Capacitor Requirements
section for more details.
B2
GND
—
Ground pin
C1
BIAS
I
BIAS supply voltage. This pin enables the use of low-input voltage, low-output voltage conditions, (LILO), (that
is, VIN = 0.7 V, VOUT = 0.5 V) to reduce power dissipation across the die. A 0.1-µF or larger ceramic capacitor
from BIAS to ground is required to reduce the impedance of the bias supply. Place the bias capacitor as close
as possible to the bias; see the Input and Output Capacitor Requirements section for more details.
C3
EN
O
Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the device.
If enable functionality is not required, this pin must be connected to IN or BIAS.
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3
ADVANCE INFORMATION
PIN
NAME
TPS7A10
SBVS314 – MARCH 2018
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Voltage
Temperature
(1)
(2)
(3)
(4)
MIN
MAX
Supply, VIN
–0.3
VBIAS + 0.3 (2) (3)
UNIT
Enable, VEN
–0.3
6.0
Bias, VBIAS
–0.3
6.0
Output, VOUT
–0.3
3.6 or (VIN + 0.3) (3) (4)
Operating junction, TJ
–40
150
Storage, Tstg
–65
150
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The absolute maximum rating is 3.6 V or (VBIAS + 0.3 V), whichever is less.
VIN – VOUT cannot exceed 3.6 V.
The absolute maximum rating is 3.6 V or (VIN + 0.3 V), whichever is less.
ADVANCE INFORMATION
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction-air temperature range (unless otherwise noted)
MIN
VIN
Input voltage (steady-state)
MAX
UNIT
VBIAS or 3.3 (1)
V
(2)
5.5
V
0.5
3.0
V
300
mA
VBIAS
Bias voltage
VOUT
Output voltage
IOUT
Peak output current
0
CIN
Input capacitor
1
CBIAS
Bias capacitor
COUT
Output capacitor (3)
TJ
Operating junction temperature
(1)
(2)
(3)
NOM
0.7
1.7 or VOUT + 1.4
µF
0.1
µF
1
47 (3)
µF
–40
125
°C
Whichever is less.
Whichever is greater.
Maximum ESR must be less than 250 mΩ.
6.4 Thermal Information
TPS7A10
THERMAL METRIC (1)
DSE (SON)
YKA (DSBGA)
UNIT
6 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
TBD
169.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
TBD
1.1
°C/W
RθJB
Junction-to-board thermal resistance
TBD
55.4
°C/W
ψJT
Junction-to-top characterization parameter
TBD
1.7
°C/W
ψJB
Junction-to-board characterization parameter
TBD
55.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
TBD
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBVS314 – MARCH 2018
6.5 Electrical Characteristics
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(NOM) + 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN =
1.0 V, CIN = 1 µF, COUT = 2.2 µF, and CBIAS = 0.1 µF )unless otherwise noted); all typical values are at TJ = 25°C
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input voltage
0.7
3.3
V
VBIAS
BIAS voltage
1.7
5.5
V
VOUT
Output voltage
0.5
3.0
V
–0.5%
0.5%
–5
5
–2%
2%
–15
15
–2.3%
2.3%
TJ = 25°C, VOUT ≥ 0.8 V
TJ = 25°C, 0.5 V ≤ VOUT < 0.8 V
DSBGA
package
–40°C ≤ TJ ≤ 85°C, VOUT ≥ 0.8 V
–40°C ≤ TJ ≤ 85°C,
0.5 V ≤ VOUT < 0.8 V
VOUT ≥ 0.8 V
0.5 V ≤ VOUT < 0.8 V
VOUT accuracy
TJ = 25°C, VOUT ≥ 0.8 V
TJ = 25°C, 0.5 V ≤ VOUT < 0.8 V
WSON
package
–40°C ≤ TJ ≤ 85°C, VOUT ≥ 0.8 V
–40°C ≤ TJ ≤ 85°C,
0.5 V ≤ VOUT < 0.8 V
VOUT ≥ 0.8 V
0.5 V ≤ VOUT < 0.8 V
–20
20
–0.5%
0.5%
–5
5
–1%
1%
–10
10
–1.5%
1.5%
–15
15
ΔVOUT(ΔVIN)/
VOUT(NOM)
Line regulation
VOUT(NOM) + 0.5 V ≤ VIN ≤ 3.3 V
0.02%
0.03%
ΔVOUT(ΔVBIAS)/
VOUT(NOM)
VBIAS line regulation
1.7 V ≤ VBIAS ≤ 5.5 V
0.15%
0.25%
ΔVOUT/ΔIOUT
Load regulation
0.1 mA ≤ IOUT ≤ 300 mA
TJ = 25°C, IOUT = 0 mA
20
3
5
–40°C ≤ TJ ≤ 85°C, IOUT = 0 mA
IBIAS
BIAS current
14
IOUT = 50 mA
150
IOUT = 0 mA
2.5
IOUT = 50 mA
20
IOUT = 300 mA
50
VEN ≤ 0.4 V, –40°C ≤ TJ ≤ 85°C
µA
µA
400
nA
1
µA
VEN ≤ 0.4 V, –40°C < TJ < 85°C
1
VEN ≤ 0.4 V, –40°C < TJ < 125°C
2
Shutdown current
ICL
Output current limit
VOUT = 0.9 × VOUT(NOM)
ISC
Short-circuit current limit
VOUT = 0 V
Dropout input voltage (2)
VIN = VOUT(NOM) – 0.1 V (2),
(VBIAS – VOUT(NOM)) = 1.4 V,
IOUT = 300 mA
60
90
VIN = VOUT(NOM) + 0.5 V,
VOUT = VOUT(NOM) – 0.1 V,
IOUT = 300 mA
1.0
1.4
(1)
(2)
µV/mA
VEN ≤ 0.4 V, –40°C ≤ TJ ≤ 125°C
ISHDN
Dropout BIAS voltage
mV
1.65
BIAS shutdown current
VDO_BIAS
mV
1.45
IBIAS
VDO_IN
mV
450
0.9
–40°C ≤ TJ ≤ 85°C, IOUT = 0 mA
Ground current
mV
7
IOUT = 0 mA
TJ = 25°C, IOUT = 0 mA
IGND
mV
10.5
IOUT = 300 mA
(1)
mV
VIN = VOUT(NOM) + 0.5 V,
VOUT = VOUT(NOM) – 0.1 V,
IOUT = 150 mA
ADVANCE INFORMATION
PARAMETER
VIN
360
435
605
150
µA
mA
mA
mV
V
1.2
IGND is the current that flows from VIN to GND.
VDO_IN cannot be measured for outputs below 0.8 V.
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Electrical Characteristics (continued)
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(NOM) + 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN =
1.0 V, CIN = 1 µF, COUT = 2.2 µF, and CBIAS = 0.1 µF )unless otherwise noted); all typical values are at TJ = 25°C
PARAMETER
VIN PSRR
VBIASPSRR
Power-supply rejection ratio,
VIN
Power-supply rejection ratio,
VBIAS
TEST CONDITIONS
f = 100 kHz, IOUT = 50 mA
40
f = 1 MHz, IOUT = 50 mA
35
f = 1.5 MHz, IOUT = 50 mA
35
f = 1 kHz, IOUT = 50 mA
60
f = 100 kHz, IOUT = 50 mA
40
f = 1 MHz, IOUT = 50 mA
35
ADVANCE INFORMATION
Output noise voltage
Bandwidth = 10 Hz to 100 kHz,
VOUT = 1 V, IOUT = 50 mA
VUVLO(BIAS)
Undervoltage lockout
VBIAS rising
VUVLO,
VBIAS falling
HYST(BIAS)
Undervoltage lockout
hysteresis
VUVLO(IN)
Undervoltage lockout
VIN rising
VUVLO,HYST(IN)
Undervoltage lockout
hysteresis
VIN falling
tSTR
Startup time
COUT = 2.2 µF (3)
VHI(EN)
EN pin high voltage
(enabled)
VLO(EN)
EN pin low voltage (enabled)
IEN
Enable pin current
EN = 5.5 V
RPULLDOWN
Pulldown resistance
(3)
6
Thermal shutdown
TYP
65
Vn
TSD
MIN
f = 1 kHz, IOUT = 50 mA
MAX
dB
dB
110
1.55
1.6
µVRMS
1.65
80
650
675
V
mV
750
75
500
UNIT
mV
mV
1200
0.9
µs
V
0.4
V
10
nA
VBIAS = 3.3 V
120
Ω
Temperature rising
160
Temperature falling
145
°C
Startup time = time from EN assertion to 0.95 × VOUT(NOM).
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6.6 Typical Characteristics
at TJ = 25°C, VIN = VOUT(NOM)+ 0.5 V, VBIAS = VOUT(NOM)+ 1.4 V, IOUT = 1 mA, VEN= VIN, CIN = 1.0 µF, COUT = 2.2 µF, and CBIAS =
0.1 µF (unless otherwise noted)
80
70
Power-Supply Rejection Ratio (dB)
65
60
55
50
45
40
35
I OUT
1 mA
10 mA
50 mA
30
25
20
10
100
100 mA
200 mA
300 mA
1k
10k
100k
Frequency (Hz)
1M
70
60
50
40
30
VDO
200 mV
400 mV
600 mV
20
10
10
10M
70
70
65
60
55
50
45
30
25
10
100
4.5 V
5.0 V
5.5 V
1k
10k
100k
Frequency (Hz)
1M
60
50
100
4.0 V
4.5 V
5.0 V
5.5 V
1k
10k
100k
Frequency (Hz)
50
45
40
VBIAS
2.5 V
3.0 V
3.5 V
4.0 V
35
30
100
1M
10M
1k
10k
100k
Frequency (Hz)
1M
10M
D007
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
0.0005
10
D008
VIN = 1.0 V, CIN = 1.0 µF, VOUT = 0.5 V, COUT = 2.2 µF,
IOUT = 300 mA
4.5 V
5.0 V
5.5 V
Figure 4. VBIAS PSRR vs Frequency and VBIAS
Output Spectral Noise Density (PV —Hz)
Power-Supply Rejection Ration (dB)
70
20
10
55
VIN = 1.6 V, CIN = 1.0 µF, VOUT = 1.1 V, COUT = 2.2 µF,
IOUT = 300 mA
Figure 3. PSRR vs Frequency and VBIAS
30
D004
60
D005
80
VBIAS
1.9 V
2.5 V
3.0 V
3.5 V
10M
65
25
10
10M
VIN = 2.1 V, CBIAS = 0.1 µF, VOUT = 1.1 V, COUT = 2.2 µF,
IOUT = 300 mA
40
1M
Figure 2. PSRR vs Frequency and VDO
75
Power-Supply Rejection Ratio (dB)
Power-Supply Rjection Rario (dB)
Figure 1. PSRR vs Frequency and IOUT
35
10k
100k
Frequency (Hz)
VBIAS = 2.5 V, CBIAS = 0.1 µF, VOUT = 1.1 V, COUT = 2.2 µF,
IOUT = 300 mA
75
VBIAS
2.5 V
3.0 V
3.5 V
4.0 V
1k
D003
VIN = 1.6 V, VBIAS = 2.5 V, CBIAS = 0.1 µF, VOUT = 1.1 V,
COUT = 2.2 µF
40
100
800 mV
1.0 V
ADVANCE INFORMATION
Power-Supply Rejection Ratio (dB)
75
COUT, µVRMS
2.2 µF, 107.8
10 µF, 104.0
4.7 µF, 101.1
22 µF, 117.4
100
1k
10k
100k
Frequency (Hz)
1M
10M
D010
VIN = 1.6 V, CIN = 1.0 µF, VBIAS = 2.5 V, CBIAS = 0.1 µF,
VOUT = 0.5 V, IOUT = 300 mA
Figure 5. VBIAS PSRR vs Frequency and VBIAS
Figure 6. Noise Density vs Frequency
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Typical Characteristics (continued)
at TJ = 25°C, VIN = VOUT(NOM)+ 0.5 V, VBIAS = VOUT(NOM)+ 1.4 V, IOUT = 1 mA, VEN= VIN, CIN = 1.0 µF, COUT = 2.2 µF, and CBIAS =
0.1 µF (unless otherwise noted)
2.75
2.5
2.5
2.25
2.25
2
2
1.75
1.75
Voltage (V)
Voltage (V)
2.75
1.5
1.25
1
0.75
1.5
1.25
1
0.75
0.5
0.5
0.25
0.25
VIN
VOUT
0
VBIAS
VEN
VIN
VOUT
0
-0.25
VBIAS
VEN
-0.25
0
100
200
300
400 500 600
Time (µs)
700
800
900 1000
0
D014
VIN = 1.6 V, CIN = 1.0 µF, VBIAS = 2.5 V, CBIAS = 0.1 µF,
VOUT = 1.1 V, COUT = 2.2 µF
Figure 7. Startup Time (VIN = VEN)
100
200
300
400 500 600
Time (µs)
700
800
900 1000
D015
VIN = 1.6 V, CIN = 1.0 µF, VBIAS = 2.5 V, CBIAS = 0.1 µF,
VOUT = 1.1 V, COUT = 2.2 µF
Figure 8. Startup Time With Separated VEN
ADVANCE INFORMATION
8
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7 Detailed Description
7.1 Overview
The TPS7A10 is an ultra-low input, ultra-low dropout, and low quiescent current linear regulator that is optimized
for excellent transient performance. These characteristics make the device ideal for most battery-powered
applications. The implementation of the BIAS pin on the TPS7A10 vastly improves efficiency of low-voltage
output applications by allowing the use of a preregulated, low-voltage input supply that offers sub-band-gap
output voltages. The high PSRR (40 dB at 1.5 MHz), low noise, low ground pin current, and ultra-small
packaging make this device suitable for ultra-portable applications. This device also offers high output voltage
accuracy of 1.5% over the recommended junction temperature range.
7.2 Functional Block Diagram
OUT
Current
Limit
ADVANCE INFORMATION
IN
Thermal
Shutdown
120
BIAS
+
±
EN
Global
UVLO
Bandgap
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7.3 Feature Description
7.3.1 Excellent Transient Response
The TPS7A10 responds quickly to a transient on the input supply (line transient) or the output current (load
transient) resulting from the device high input impedance and low output impedance across frequency. This
same capability also means that the device has a high power-supply rejection ratio (PSRR) and low internal
noise floor (en). The low-dropout regulator (LDO) approximates an ideal power supply in ac (small-signal) and dc
(large-signal) conditions.
The choice of external component values optimizes the small- and large-signal response; see the Input and
Output Capacitor Requirements section for proper selection.
7.3.2
Global Undervoltage Lockout (UVLO)
The TPS7A10 uses two undervoltage lockout (UVLO) circuits: one on the BIAS pin and one on the IN pin to
prevent the device from turning on before both VBIAS and VIN rise above their lockout voltages. The two UVLO
signals are connected internally through an AND gate, as shown in Figure 9, which allows the device to be
turned off when either rail is below its lockout voltage.
VIN_UVLO
ADVANCE INFORMATION
Global UVLO
VBIAS_UVLO
Figure 9. Global UVLO circuit
7.3.3 Active Discharge
The device has an internal pulldown MOSFET that connects a 120-Ω resistor to ground when the device is
disabled to actively discharge the output voltage. The active discharge circuit is activated by an enable or
undervoltage lockout (UVLO).
The discharge time after disabling the device depends on the output capacitance (COUT) and the load resistance
(RL) in parallel with the 120-Ω pulldown resistor. Equation 1 calculates the time constant:
120 · RL
t=
· COUT
120 + RL
(1)
Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input
supply collapses because reverse current can possibly flow from the output to the input. This reverse current flow
can cause damage to the device. Limit reverse current to no more than 5% of the device-rated current for a short
period of time.
7.3.4 Enable
The enable pin for the device is active high. The output of the device is turned on when the enable pin voltage is
greater than its rising voltage threshold (0.9 V, min), and the output of the device is turned off when the enable
pin voltage is less than its falling voltage threshold (0.4 V, max).
7.3.5 Internal Foldback Current Limit
The internal foldback current limit circuit is used to protect the LDO against high-load current faults or shorting
events. The foldback mechanism lowers the current limit as the output voltage decreases, and limits power
dissipation during short-circuit events while still allowing for the device to operate at its rated output current. A
foldback example for this device is that when VOUT is 90% of VOUT(nom) the current limit is 435 mA (typical);
however, if VOUT is forced to 0 V the current limit is 150 mA (typical).
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Feature Description (continued)
Thermal shutdown can activate during a current-limit event because of the high power dissipation typically found
in these conditions. To ensure proper operation of the current limit, minimize the inductances to the input and
load. Continuous operation in current limit is not recommended.
7.3.6 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when thermal junction
temperature (TJ) of the main pass-FET rises to 160°C (typical). Thermal shutdown hysteresis assures that the
LDO resets again (turns on) when the temperature falls to 145°C (typical).
The thermal time constant of the semiconductor die is fairly short, and thus the device may cycle on and off
when thermal shutdown is reached until the power dissipation is reduced.
A fast start-up when TJ > 145°C (typical, outside of the specified operating range) causes the device thermal
shutdown to assert at TSD(rising) and prevents the device from turning on until the junction temperature is reduced
below TSD(falling).
7.4 Device Functional Modes
The device has several modes of operation that are listed below:
• Normal operation: The device regulates to the nominal output voltage
• Dropout operation: The pass element operates as a resistor and the output voltage is set as VIN – VDO
• Disabled: The output of the device is disabled and the discharge circuit is activated
Table 1 shows the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VBIAS
VEN
IOUT
TJ
TJ < 160°C
Normal mode
VIN > VOUT(nom) + VDO and VIN > VIN(min)
VBIAS > VOUT + 1.4 V
VEN > VHI(EN)
IOUT < peak output
current
Dropout mode
VIN(min) < VIN < VOUT(nom) + VDO
VBIAS < VOUT + 1.4 V
VEN > VHI(EN)
IOUT < peak output
current
TJ < 160°C
VIN < VUVLO
VBIAS < VBIAS(UVLO)
VEN < VLO(EN)
—
TJ > 160°C
Disabled mode
(any true condition
disables the device)
7.4.1 Normal Mode
The device regulates the output to the nominal output voltage when all normal mode conditions in Table 1 are
met.
7.4.2 Dropout Mode
The device is not in regulation, and the output voltage tracks the input voltage minus the voltage drop across the
pass element of the device. In this mode, PSRR and the noise performance of the device are significantly
degraded.
7.4.3 Disable Mode
In this mode, the pass element is turned off, the internal circuits are shut down, and the output voltage is actively
discharged to ground by an internal resistor.
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For reliable operation, limit the junction temperature to a maximum of 125°C. Operation above 125°C causes the
device to exceed its operational specifications. Although the internal protection circuitry of the device is designed
to protect against thermal overload conditions, this circuitry is not intended to replace proper heat sinking.
Continuously running the device into thermal shutdown or above a junction temperature of 125°C reduces longterm reliability.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Successfully implementing an LDO in an application depends on the application requirements. This section
discusses key device features and the best implementation to achieve a reliable design.
8.1.1 Recommended Capacitor Types
ADVANCE INFORMATION
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input,
output, and BIAS pins. Multilayer ceramic capacitors are the industry standard for these types of applications and
are recommended, but must be used with good judgment. Ceramic capacitors that use X7R-, X5R-, and COGrated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5Vrated capacitors is not recommended because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and
temperature; derate ceramic capacitors by at least 50%. The input, output, and bias capacitors recommended
herein account for a capacitance derating of approximately 50%.
8.1.2 Input and Output Capacitor Requirements
The TPS7A10 is designed and characterized for operation with ceramic capacitors of 2.2 µF or greater at the
output pin, 1.0 µF or greater at the input pin, and 0.1 µF or greater at the BIAS pin. TI requires using a capacitor
with a value of at least 1.0 µF at the input to minimize input impedance and a capacitor with a value of at least
2.2 µF with maximum ESR of less than 250 mΩ at the output.
The BIAS pin also requires a small capacitor, however, the BIAS pin does not source high current. If source
impedance is not sufficiently low, then a small 0.1-µF bypass capacitor is required. This small capacitor is used
to counteract reactive input sources, improve transient response, and improve noise rejection and ripple
rejection.
Place the input, output, and bias capacitors as close as possible to the respective pins to minimize trace
parasitics.
8.1.3 Undervoltage Lockout Circuit Operation
The VIN pin UVLO circuit ensures that the device stays disabled before the input supply reaches the minimum
operational voltage range, and ensures that the device shuts down when the input supply collapses. Similarly,
the VBIAS pin UVLO circuit ensures that the device stays disabled before the bias supply reaches the minimum
operational voltage range, and ensures that the device shuts down when the bias supply collapses.
Figure 10 depicts the UVLO circuit response to various input or bias voltage events. This figure can be separated
into the following parts:
• Region A: The device does not start until the input or bias voltage reaches the UVLO rising threshold
• Region B: Normal operation, regulating device
• Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The
output may fall out of regulation but the device is still enabled.
• Region D: Normal operation, regulating device
• Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the
output falls as a result of the load and active discharge circuit. The device is re-enabled when the UVLO
rising threshold is reached and a normal start-up follows.
• Region F: Normal operation followed by the input or bias falling to the UVLO falling threshold
• Region G: The device is disabled as the input or bias voltages fall below the UVLO falling threshold to 0 V.
The output falls as a result of the load and active discharge circuit.
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Application Information (continued)
UVLO Rising Threshold
UVLO Hysteresis
VIN / VBIAS
C
VOUT
tAt
tBt
tDt
tEt
tFt
tGt
Figure 10. Typical VIN or VBIAS UVLO Circuit Operation
Power-Supply Rejection Ratio (PSRR)
PSRR is a measure of how well the LDO control-loop rejects signals from VIN to VOUT across the frequency
spectrum (usually 10 Hz to 10 MHz). Equation 2 gives the PSRR calculation as a function of frequency for the
input signal [VIN(f)] and output signal [VOUT(f)].
PSRR dB
§ V f
20 log10 ¨ IN
¨V
© OUT f
·
¸¸
¹
(2)
Even though PSRR is a loss in signal amplitude, PSRR is shown as positive values in decibels (dB) for
convenience.
Power-Supply Rejection-Ratio (dB)
Figure 11 shows a simplified diagram of PSRR versus frequency.
Bandgap
Bandgap RC
Filter
Error Amplifier, Flat-Gain
Region
Error Amplifier,
Gain Roll-off
Output Capacitor
|ZCOUT| Decreasing
Output Capacitor
|ZCOUT| Increasing
10 Hz ± 1 MHz
Sub 10 Hz
100 kHz +
Frequency (Hz)
Figure 11. Power-Supply Rejection Ratio Diagram
An LDO is often employed not only as a dc-dc regulator, but also to provide exceptionally clean power-supply
voltages that exhibit ultra-low noise and ripple to sensitive system components.
8.1.5 Output Voltage Noise
The TPS7A10 is designed for system applications where minimizing noise on the power-supply rail is essential to
system performance. LDO noise is defined as the internally generated intrinsic noise created by the
semiconductor circuits alone. This noise is the sum of various types of noise (such as shot noise associated with
current-through-pin junctions, thermal noise caused by thermal agitation of charge carriers, flicker noise, or 1/f
noise and dominates at lower frequencies as a function of 1/f). Figure 12 depicts a simplified output voltage noise
density plot versus frequency.
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8.1.4
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fN
1/
oi
se
Wide-band Noise
N
oi
se
ai
G
Integrated Noise
From Bandgap and Error Amplifier
n
R
ol
ff
l -O
Output Voltage Noise Density (nV/¥+])
Application Information (continued)
Measurement Noise Floor
Frequency (Hz)
Figure 12. Output Voltage Noise Diagram
ADVANCE INFORMATION
For further details, see the How to Measure LDO Noise white paper.
8.1.6 Load Transient Response
The load-step transient response is the output voltage response by the LDO to a step in load current, whereby
output voltage regulation is maintained. There are two key transitions during a load transient response: the
transition from a light to a heavy load and the transition from a heavy to a light load. The regions in Figure 13 are
broken down as described in this section. Regions A, E, and H are where the output voltage is in steady-state.
During transitions from a light load to a heavy load, the:
• Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the
output capacitor (region B)
• Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage
regulation (region C)
During transitions from a heavy load to a light load, the:
• Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to
increase (region F)
• Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load
discharging the output capacitor (region G)
A larger output capacitance reduces the peaks during a load transient but slows down the response time of the
device. A larger dc load also reduces the peaks because the amplitude of the transition is lowered and a higher
current discharge path is provided for the output capacitor.
tAt
tCt
B
tDt
tEt
tGt
tHt
F
Figure 13. Load Transient Waveform
8.1.7 Dropout Voltage
Generally speaking, the dropout voltage often refers to the minimum voltage difference between the input and
output voltage (VDO = VIN – VOUT) that is required for regulation. When VIN drops below the required VDO for the
given load current, the device functions as a resistive switch and does not regulate output voltage. Dropout
voltage is linearly proportional to the output current because the device is operating as a resistive switch.
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Application Information (continued)
8.1.8 Behavior When Transitioning From Dropout Into Regulation
Some applications can have transients that place the device into dropout, such as slower ramps on VIN for startup or load transients. As with many other LDOs, the output can overshoot on recovery from these conditions.
As shown in Figure 14, a ramping input supply can cause an LDO to overshoot on start-up when the slew rate
and voltage levels are in the right range. This condition is easily avoided through the use of the enable signal.
Input Voltage
Response time for
LDO to get back into
regulation.
Load current discharges
output voltage.
VIN = VOUT(nom) + VDO
Dropout
VOUT = VIN - VDO
Output Voltage in
normal regulation.
Time
Figure 14. Start-Up Into Dropout
8.1.9 Power Dissipation (PD)
Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
must be as free as possible of other heat-generating devices that cause added thermal stresses.
Equation 3 calculates the maximum allowable power dissipation for the device in a given package:
PD-MAX = [(TJ – TA) / RθJA]
(3)
Equation 4 represents the actual power being dissipated in the device:
PD = (VIN – VOUT) × IOUT
(4)
Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system
voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low
dropout of the TPS7A10 allows for maximum efficiency across a wide range of output voltages.
The main heat conduction path for the device depends on the ambient temperature and the thermal resistance
across the various interfaces between the die junction and ambient air.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
According to Equation 5, maximum power dissipation and junction temperature are most often related by the
junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of
the ambient air (TA). The equation is rearranged in Equation 6 for output current.
TJ = TA + (RθJA × PD)
IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)]
(5)
(6)
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Voltage
Output Voltage
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Application Information (continued)
Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the
planes. The RθJA recorded in the table is determined by the JEDEC standard, PCB, and copper-spreading area,
and is only used as a relative measure of package thermal performance.
8.1.10 Estimating Junction Temperature
The JEDEC standard recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of
the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are used in accordance with Equation 7 and are given in the table.
ΨJT : TJ = TT + ΨJT × PD and ΨJB : TJ = TB + ΨJB × PD
where:
•
•
•
8.1.11 Recommended Area for Continuous Operation
The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input
voltage. The recommended area for continuous operation for a linear regulator is shown in Figure 15 and can be
separated into the following regions:
•
•
•
•
Dropout voltage limits the minimum differential voltage between the input and the output (VIN – VOUT) at a
given output current level.
The rated output currents limits the maximum recommended output current level. Exceeding this rating
causes the device to fall out of specification.
The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating
causes the device to fall out of specification and reduces long-term reliability.
– Equation 6 provides the shape of the slope. The slope is nonlinear because the maximum rated junction
temperature of the LDO is controlled by the power dissipation across the LDO, thus when VIN – VOUT
increases the output current must decrease.
The rated input voltage range governs both the minimum and maximum of VIN – VOUT.
Output Current (A)
ADVANCE INFORMATION
PD is the power dissipated as explained in Equation 4
TT is the temperature at the center-top of the device package, and
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
(7)
Output Current Limited
by Dropout
Rated Output
Current
Output Current Limited
by Thermals
Limited by
Maximum VIN
Limited by
Minimum VIN
VIN ± VOUT (V)
Figure 15. Region Description of Continuous Operation Regime
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8.2 Typical Application
VBATTERY
CBIAS
BIAS
1.0 V
0.5 V
IN
Standalone DC/DC
Converter or PMU
VCORE
OUT
CIN
COUT
TPS7A10
EN
GND
VEN
8.2.1 Design Requirements
Table 2 summarizes the design requirements for Figure 16.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VIN
1.0 V
VBIAS
2.7 V
VOUT
0.5 V
IOUT
10-mA typical, 300-mA peak
Maximum ambient temperature
60°C
8.2.2 Detailed Design Procedures
8.2.2.1 Input Current
During normal operation, the input current to the LDO is approximately equal to the output current of the LDO.
During startup, the input current is higher as a result of the inrush current charging the output capacitor. Use
Equation 8 to calculate the current through the input.
VOUT(t)
COUT ´ dVOUT(t)
IOUT(t) =
+
RLOAD
dt
where:
•
•
•
VOUT(t) is the instantaneous output voltage of the turnon ramp
dVOUT(t) / dt is the slope of the VOUT ramp
RLOAD is the resistive load impedance
(8)
8.2.2.2 Thermal Dissipation
The junction temperature can be determined using the junction-to-ambient thermal resistance (RθJA) and the total
power dissipation (PD). Use Equation 9 to calculate the power dissipation. As Equation 10 shows, multiply PD by
RθJA and add the ambient temperature (TA) to calculate the junction temperature (TJ).
PD = (IGND+ IOUT) × (VIN – VOUT)
TJ = RθJA × PD + TA
(9)
(10)
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Figure 16. Typical Application Schematic
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If the (TJ(MAX)) value does not exceed 125°C, use Equation 11 to calculate the maximum ambient temperature.
Equation 12 calculates the maximum ambient temperature with a value of 99.59°C.
TA(MAX) = TJ(MAX) – RθJA × PD
TA(MAX) = 125°C – 169.4 × (1.0 V – 0.5 V) × (0.3 A) = 99.59°C
(11)
(12)
8.2.3 Application Curves
Power-Supply Rejection Ratio (dB)
75
70
65
60
55
50
45
40
35
30
25
ADVANCE INFORMATION
20
10
VDO
400 mV
500 mV
1.0 V
100
1k
10k
100k
Frequency (Hz)
1M
10M
D006
VBIAS = 2.7 V, CBIAS = 0.1 µF, VOUT = 0.5 V, COUT = 2.2 µF, IOUT = 300 mA
Figure 17. PSRR vs Frequency and VDO
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9 Power Supply Recommendations
This device is designed to operate from an input supply voltage range of 0.7 V to 3.3 V, and a bias supply
voltage range of VOUT + 1.4 V to 5.5 V. The input supply must be well regulated and free of spurious noise. To
ensure that the output voltage is well regulated and dynamic performance is optimum, the input supply must be
at least VOUT + 0.1 V. A minimum of a 2.2-µF or greater output capacitor is required to be used with a maximum
ESR value of less than 250 mΩ.
10 Layout
10.1 Layout Guidelines
•
•
•
Place input, output, and bias capacitors as close to the device as possible.
Use copper planes for device connections to optimize thermal performance.
Place thermal vias around the device to distribute heat.
10.2 Layout Examples
CIN
ADVANCE INFORMATION
OUT
IN
COUT
A1
GND
A3
B2
C1
C3
CBIAS
EN
BIAS
Figure 18. Recommended Layout for the YKA Package
OUT
1
IN
6
COUT
CIN
2
NC
GND
5
CBIAS
3
EN
BIAS
4
Figure 19. Recommended Layout for the DSE Package
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10.3 Recommended Layout for the YKA (DSBGA) Package
The DSBGA package requires specific mounting techniques that are detailed in the AN-1112 DSBGA Wafer
Level Chip Scale Package application report. Referring to the AN-1112 section Surface Mount Assembly
Considerations, the pad style that must be used with the 5-pin package is the non-solder mask defined (NSMD)
type.
For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the
DSBGA device.
10.4 YKA (DSBGA) Package Light Sensitivity
The wavelengths that have the most detrimental effect are reds and infra-reds, which means that the fluorescent
lighting used inside most buildings has little effect on performance. Tests carried out on a DSBGA test board
showed a negligible effect on the regulated output voltage when brought within 1 cm of a fluorescent lamp. A
deviation of less than 0.1% from nominal output voltage was observed.
10.5 Thermal Considerations
ADVANCE INFORMATION
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the
device to cool. When the junction temperature cools to approximately +145°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This cycling limits regulator dissipation and protects the regulator from damage as a
result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature must be limited to +125°C maximum. To estimate the
margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection must
trigger at least 35°C above the maximum expected ambient condition of the particular application. This
configuration produces a worst-case junction temperature of +125°C at the highest expected ambient
temperature and worst-case load.
The internal protection circuitry of the TPS7A10 is designed to protect against overload conditions. This circuitry
is not intended to replace proper heatsinking. Continuously running the TPS7A10 into thermal shutdown
degrades device reliability.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Table 3. Device Nomenclature (1) (2)
PRODUCT
TPS7A10xx(x)yyyz
(1)
(2)
VOUT
xx(x) is the nominal output voltage. For output voltages with a resolution of 50 mV, two digits are used
in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V).
yyy is the package designator.
z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
Output voltages from 0.9 V to 3.6 V in 50-mV increments are available. Contact the factory for details and availability.
11.2 Documentation Support
For related documentation see the following:
• Using New Thermal Metrics
• AN-1112 DSBGA Wafer Level Chip Scale Package
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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11.2.1 Related Documentation
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
ADVANCE INFORMATION
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PACKAGE OUTLINE
YKA0005
DSBGA - 0.4 mm max height
SCALE 13.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
INDEX AREA
D
0.4 MAX
C
SEATING PLANE
0.18
0.13
BALL
TYP
0.05 C
0.35
C
0.7
SYMM
B
0.35
A
5X
0.015
0.24
0.19
C A B
1
3
2
SYMM
4223737/B 05/2017
NanoFree Is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
TM
3. NanoFree package configuration.
www.ti.com
EXAMPLE BOARD LAYOUT
YKA0005
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.35)
5X ( 0.2)
2
1
3
A
(0.35)
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:50X
( 0.2)
METAL
SOLDER MASK
OPENING
0.0325 MAX
EXSPOSED
METAL
METAL
UNDER
SOLDER MASK
0.0325 MIN
EXPOSED
METAL
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
( 0.2)
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NOT TO SCALE
4223737/B 05/2017
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YKA0005
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.35)
5X ( 0.21)
1
2
(R0.05) TYP
3
A
(0.35)
SYMM
B
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm - 0.1 mm THICK STENCIL
SCALE:50X
4223737/B 05/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
23-Mar-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
PTPS7A1006PYKAR
ACTIVE
DSBGA
YKA
5
12000
TBD
Call TI
Call TI
-40 to 125
PTPS7A10105PYKAR
ACTIVE
DSBGA
YKA
5
12000
TBD
Call TI
Call TI
-40 to 125
PTPS7A1010PYKAR
ACTIVE
DSBGA
YKA
5
12000
TBD
Call TI
Call TI
-40 to 125
PTPS7A1011PYKAR
ACTIVE
DSBGA
YKA
5
12000
TBD
Call TI
Call TI
-40 to 125
PTPS7A1012PYKAR
ACTIVE
DSBGA
YKA
5
12000
TBD
Call TI
Call TI
-40 to 125
PTPS7A1030PYKAR
ACTIVE
DSBGA
YKA
5
12000
TBD
Call TI
Call TI
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Mar-2018
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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