A Low Noise High Linearity GPS Low Noise Amplifier
With Integrated Shutdown Function and Adjustable Operating Current
Using Avago Technologies’ MGA-635T6
Application Note 5275
Introduction
Avago Technologies’ MGA-635T6 is a low noise amplifier
designed for GPS application. This amplifier is housed in
a ultra thin small leadless package which have small footprint (2 x 1.3 mm2 ) and very low profile (0.4mm max.). By
using Avago Technologies proprietary GaAs E-pHEMT (Enhancement-mode pHEMT) process, this LNA can achieve
high gain operation with very low noise figures and high
linearity. The uniqueness of using E-pHEMT technologies
is the part still useable with low voltage supply. This is important where the critical functions of the mobile receiver
still working at battery weak condition.
This application note describes the design of a GPS LNA
using MGA-635T6. The circuit is demonstrated on a low
cost FR4 material with standard 0402 chip inductors. Following figures show some information on the view and
stacking structure of the demoboard.
Figure 2a. Bottom View of Demoboard (Bottom Layer)
Figure 1. Top View of Demoboard (Top Layer)
Figure 2b. Ground Layer at the Middle Layer of Demoboard (Middle Layer)
16 mil FR4 material
Top
1.4 mil
Copper Layers
Total Thickness 62 mils
Middle
(For mechanical strength)
FR4 material
Bottom
(Support material)
Figure 3. PCB Stacking Structure
Pin Configuration, Biasing, Shutdown and Current Adjustment
Pin 6
25
Pin 2
Pin 5
20
Pin 3
Pin 4
Pin 1 & 3 : not connected
Pin 2 : RF input
Pin 4 : VSD
Pin 5 : RF Output
Pin 6 : VDD
Figure 4. Pin Configuration
Id (mA)
Pin 1
15
10
5
0
1000
10000
100000
R1 (ohm)
Figure 5. Current, Id versus Resistance of Bias Resistor, R1
Figure above showing the pin configuration of the amplifier. In this design, the LNA required just one single
positive dc supply. Both the VDD and VSD are connected
to a +2.85 volts supply and a bias resistor is placed at VSD
pin to adjust to desired operating current. Bias resistor
with lower resistance will give higher current which bring
higher gain and linearity. In fact, the current is determine
by the voltage apply to the VSD pin. The resistor placed at
the VSD pin drop the 2.85 volts voltage supply to desired
voltage level. For design with low voltage supply, the bias
resistor can be omitted and the VSD pin is directly connect to the supply pin. Figure 5 shows the device current
versus the value of resistor place at the VSD pin (VDD =
VSD = +2.85 volts).
The integrated shutdown function in the LNA becomes
an advanced feature for application in portable devices
where the battery power must be conserved. This LNA
can be easily turned off by applying 0 volts to the shutdown pin. Instead of placing a resistor at the shutdown
pin, the device current can be controlled by applying a
fixed voltage to the shutdown pin. By connecting the VSD
pin to a microcontroller which gives the desired voltage
to the LNA, software control can turn off the amplifier
when it is not needed to extend the battery life.
Table below shows the gain and noise figure of the part
when different voltage applied to the VSD pin and VDD
pin. (VDD = VSD; R1= 0 ohm). The measured performance
is based on the 5 mA application circuit (refer to figure 6
and table 3). At lower current (<5mA), the output matching may need to retune to achieve unconditional stability.
The overall performance (gain, noise figure and stability)
is improved with higher device current.
Table 1. Gain and Noise Figure for Different Voltage Supply to VDD
and VSD (Measured based on 5 mA application circuit, R1 = 22kW)
VDD and
VSD(volts)
ID(mA)
S21(dB)
NF(dB)
3
22.5
17
0.75
2.5
18.8
16.8
0.75
2
14.7
16.5
0.77
1.5
10.1
15.8
0.80
1
5.2
14.2
0.94
0.6
1.2
7.9
2.06
Application Circuit for MGA-635T6 in GPS Low Noise Amplifier
Vdd
C2
R2
C1
L3
RF ln
L1
RF Out
40 mils
L2
Bias
R1
Vsd
Figure 6. Application Circuit Schematic
The figure above shows the application circuit for MGA635T6. External blocking capacitors are not needed at
the input and output as the capacitors are integrated
internally to reduce the number of external components.
A 22kW resistor (R1) is placed at the shutdown pin to set
the current at about 5mA.
In this design, the input is matched to get a very low
noise figure with acceptable input return loss and good
gain. The input matching is formed by a series inductor
followed by a shunt inductor to bring the input impedance close to the optimum noise match (Γopt). The measured noise figure is about 0.9 dB with associated gain
of 14.8 dB including the losses from SMA connector and
transmission line. By replacing the whole input matching network with a series 5.6 nH inductor, noise figure
improved while compromising on the input return loss.
At the output of the LNA, a 10 ohm damping resistor
(R2) is put to improve the stability of the design. The DC
supply line needs to be properly bypassed to improve
the third order intercept performance (IP3) and to avoid
unwanted feedback from the supply which may cause a
low frequency oscillation to happen. With 5 mA of current, this low noise amplifier can achieve >+1 dBm of IIP3.
The excellent third order intercept performance of this
low noise amplifier offers good selectivity in a receiver
system especially in a multi-carrier system.
For applications which need better RF performance, the
LNA can be set to operate at a slightly higher current. By
placing a 12kW resistor at the shutdown pin will set the
operating current to about 8 mA. This will increase the
gain by 1dB and improve the noise figure to about 0.8 dB
on the demoboard. The matching topology is the same
for both of the designs. Table below summarize the RF
performance of both the 5mA and 8mA design.
Table 2. On Board Performance for MGA-635T6 at 5mA and 8mA
Parameter and Test Condition
Units
R1 = 22kW
R1 = 12kW
VDD, Supply Voltage
V
2.85
2.85
Id, Supply Current
mA
5.2
8.4
S21, Power Gain
dB
14.8
15.8
NF, Noise Figure
dB
0.9
0.8
IP1dB, Input 1dB Compressed Power
dBm
2.6
0.8
IIP3, Input 3rd Order Intercept Point
(F1=1570MHz, F2=1575MHz, Pin= -20 dBm)
dBm
1.5
3.3
IRL, Input Return Loss
dB
-7.5
-9.8
ORL, Output Return Loss
dB
-10.6
-10.5
Associated Gain, S21 at 5mA (dB)
Associated Gain, S21 at 8mA (dB)
This low noise amplifier is still useable at battery weak
condition. Following figures show the gain and noise
figure when the voltage applied to the VDD and VSD pin
drop. The measured result is based on the 5 mA (R1 =
22kW) and 8 mA (R1 = 12kW) application circuits.
20
15
10
5
0
-5 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
-10
-15
-20
VDD(V)
Noise Figure, NF at 8mA (dB)
Noise Figure, NF at 5mA (dB)
Figure 7. Associated Gain versus VDD for 5 mA (R1=22kW) and 8 mA (R1=12kW) Application (VDD = VSD)
16
14
12
10
8
6
4
2
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
VDD( V)
Figure 8. Noise Figure versus VDD for 5 mA (R1=22kW) and 8 mA (R1=12kW) Application (VDD = VSD)
dB(Input_Return_Loss_8mA..S(1,1))
dB(Input_Return_Loss_5mA..S(1,1))
Narrowband Performance (VDD = VSD = 2.85 volts)
0
-3
-6
-9
-12
-15
1. 40
1. 45
1. 50
1. 55
freq, GHz
1. 60
1. 65
1. 70
1. 60
1. 65
1. 70
1.60
1.65
1.70
dB(Output_Return_Loss_8mA..S(2,2))
dB(Output_Return_Loss_5mA..S(2,2))
Figure 9. Measured Input Return Loss for 5mA and 8mA Application
0
-4
-8
-12
-16
1. 40
1. 45
1. 50
1. 55
freq, GHz
Figure 10. Measured Output Return Loss for 5mA and 8mA Application
20
dB(Gain_5mA..S(2,1))
dB(Gain_8mA..S(2,1))
16
12
8
4
0
1.40
1.45
1.50
1.55
freq, GHz
Figure 11. Measured Associated Gain for 5mA and 8mA Application
dB(Reverse_Isolation_8mA..S(1,2))
dB(Reverse_Isolation_5mA..S(1,2))
0
-6
-12
-18
-24
-30
1.40
1.45
1.50
1.55
freq, GHz
1.60
1.65
1.70
Figure 12. Measured Reverse Isolation for 5mA and 8mA Application
Noise Figure, NF at 5 mA (dB)
Noise Figure, NF at 8 mA (dB)
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.50 1.51 1.52 1.53 1.54 1.55
1.56 1.57 1.58 1.59 1.60
freq, GHz
Figure 13. Measured Noise Figure for 5 mA and 8 mA Application
k_factor_8mA..StabFact1
k_factor_5mA..StabFact1
8
7
6
5
4
3
2
1
0
20.05
18.05
16.05
14.05
Figure 14. Measured k factor for 5 mA and 8 mA Application
12.05
10.05
8.05
6.05
4.05
2.05
0.05
freq, GHz
16
12
8
4
0
0
2
4
6
8
10
12
14
16
18
20
22
dB(Input_Return_Loss_8mA..S(1,1))
dB(Input_Return_Loss_5mA..S(1,1))
freq, GHz
0
-4
-8
-1 2
-1 6
0
2
4
6
8
10 12
freq, GHz
14
16
Figure 15. Measured S parameter for 5 mA and 8 mA Application
18
20
dB(Reverse_Isolation_8mA..S(1,2))
dB(Reverse_Isolation_5mA..S(1,2))
dB(Gain_8mA..S(2,1))
dB(Gain_5mA..S(2,1))
20
dB(Output_Return_Loss_8mA..S(2,2))
dB(Output_Return_Loss_5mA..S(2,2))
Broadband S parameter Performance (VDD = VSD = 2.85 volts)
0
-4
-8
-1 2
-1 6
02
2
4
6
8
10
12
14
16
18
20
22
freq, GHz
0
-1 0
-2 0
-3 0
-4 0
0
2
4
6
8
10
12
freq, GHz
14
16
18
20
C2
R2
C1
L1
40 milsL3
xxx
L2
R1
Figure 16. Component Placement on Demoboard
Table 3. Bill of Material for GPS LNA using MGA-635T6
Component Value
Size
@Id = 5 mA
@Id = 8 mA
Manufacturer and Part Number
L1
0402
6.8 nH
6.8 nH
TOKO LLP1005-FH6N8C
L2
0402
18 nH
18 nH
TOKO LL1005-FHL18NJ
L3
0402
5.6 nH (1)
6.8 nH (2)
TOKO LL1005-FH5N6S (1)
TOKO LLP1005-FH6N8C (2)
C1
0402
6.8 pF
6.8 pF
Murata GRM1555C1H6R8CZ01D
C2
0402
0.1 uF
0.1 uF
Murata GRM155R61A104KA01D
R1
0402
22kW (1)
12kW (2)
ROHM MCR01J223 (1)
ROHM MCR01J123 (2)
R2
0402
10 ohm
10 ohm
KOA RK73B1ELTP100J
Improve Third Order Intercept Performance
For application which need better third order intercept
performance at low current (5mA), the IIP3 can be improved by putting the input matching circuit slightly
away from the MGA-635T6 as shown as the schematic
below. This will improve the IIP3 to >2dBm (refer to figure
17). More than 3dBm IIP3 can be achieved by replacing
the L3 with a 6.8nH inductor and the R2 with a parallel RL
network (R=12ohm, L=33nH), to achieve unconditional
stability (refer to figure 18).
Vdd
C2 = 0.1 uF
R2 = 10Ω
C1 = 6.8 uF
L3 = 5.6 nH
RF ln
L1 = 5.6 nH
140 mils
RF Out
MGA-635T6
L2 = 12 nH
R1 = 22kΩ
Vsd
Figure 17. Application Circuit Schematic for >2dBm IIP3 at 5mA
Vdd
C2 = 0.1 uF
L4 = 33 nH
R2 = 12Ω
C1 = 6.8 uF
L3 = 6.8 nH
RF ln
L1 = 5.6 nH
140 mils
RF Out
MGA-635T6
L2 = 12 nH
R1 = 12kΩ
Figure 18. Application Circuit Schematic for >3dBm IIP3 at 5mA
Vsd
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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2006 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0171EN
AV02-0451EN - May 23, 2007
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