1747-6.15, SLC 500_ and MicroLogix_ 1000 Instruction Set

1747-6.15, SLC 500_ and MicroLogix_ 1000 Instruction Set

Allen-Bradley

SLC 500

t

and

MicroLogix

t

1000

Instruction Set

(Cat. Nos. 1747-L511, 1747-L514,

1747-L524,

1747-L531, 1747-L532,

1747-L541, 1747-L542, 1747-L543,

1747-L551, 1747-L552, 1747-L553, and Bulletin 1761 Controllers)

Reference

Manual

File Name: AB_SLC500_MicroLogix1000_1747_L5xx_ref_D198

Important User Information

Because of the variety of uses for the products described in this publication, those responsible for the application and use of this control equipment must satisfy themselves that all necessary steps have been taken to assure that each application and use meets all performance and safety requirements, including any applicable laws, regulations, codes, and standards.

The illustrations, charts, sample programs and layout examples shown in this guide are intended solely for purposes of example. Since there are many variables and requirements associated with any particular installation, Allen-Bradley does not assume responsibility or liability (to include intellectual property liability) for actual use based on the examples shown in this publication.

Allen-Bradley publication SGI-1.1, Safety Guidelines for the Application,

Installation, and Maintenance of Solid-State Control (available from your local

Allen-Bradley office), describes some important differences between solid-state equipment and electromechanical devices that should be taken into consideration when applying products such as those described in this publication.

Reproduction of the contents of this copyrighted publication, in whole or in part, without written permission of Allen-Bradley Company, Inc., is prohibited.

Throughout this manual, we use notes to make you aware of safety considerations:

Identifies information about practices or circumstances that can lead to personal injury or death, property damage, or economic loss.

Attention statements help you to:

• identify a hazard

• avoid the hazard

• recognize the consequences

Note

Identifies information that is critical for successful application and understanding of the product.

PLC–2, PLC–3, and PLC–5 are registered trademarks of Rockwell Automation.

SLC 500, SLC 5/01, SLC 5/02, SLC 5/03, SLC 5/04, SLC 5/05, MicroLogix, and Data Highway Plus are trademarks of Rockwell Automation.

WINtelligent EMULATE 500, WINtelligent LINX, RSLogix 500, RSLinx, RSTune, and A.I. Series are trademarks of Rockwell Software, Inc.

Ethernet is a registered trademark of Digital Equipment Corporation, Intel, and Xerox Corporation.

MS–DOS and Windows 95 are registered trademarks of Microsoft Corporation.

Windows NT is a trademark of Microsoft Corporation.

NEC Versa is a trademark of Nippon Electric Company Information Systems, Inc.

Gateway 2000 is a trademark of Gateway 2000, Inc.

Summary of Changes

Summary of Changes

New Information Added to this Manual

The list below summarizes the changes that have been made to the Instruction Set

Reference manual since the last printing:

For this New Information:

Addition of new SLC 5/05 Processor.

Two new MicroLogix 1000 chapters:

MicroLogix Communication Instruction

MicroLogix Communication Protocols

Revised information on how to use the status bits for the MSG instruction and new ladder logic examples.

Revised Interrupt Latency specifications for STI, DII, and IOI.

New application example: Interfacing with Enhanced Bar

Code Decoders Over DH-485 Network.

See:

throughout

Ch. 9

Ch. 14

Ch. 8

App. D

App. H

To help you find new information and updated information in this release of the manual, we have included change bars as shown to the right of this paragraph.

i

Table of Contents

Table of Contents

1

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Who Should Use this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Purpose of this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents of this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Common Techniques Used in this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Basic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

About the Basic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bit Instructions Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output and Input Data Files (Files O0: and I1:) . . . . . . . . . . . . . . . . . . . . . . .

Status File (File S2:)

Bit Data File (B3:)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timer and Counter Data Files (T4: and C5:)

Control Data File (R6:)

. . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Integer Data File (N7:) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Examine if Closed (XIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Examine if Open (XIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Energize (OTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Latch (OTL) and Output Unlatch (OTU) . . . . . . . . . . . . . . . . . . . . . . . . . .

Using OTL

Using OTU

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

One–Shot Rising (OSR)

Entering Parameters

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timer Instructions Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters

Addressing Structure

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timer On–Delay (TON)

Using Status Bits

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timer Off–Delay (TOF)

Using Status Bits

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Retentive Timer (RTO)

Using Status Bits

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Counter Data File Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–9

1–9

1–10

1–10

1–11

1–11

1–11

1–12

1–14

1–1

1–2

1–3

1–3

1–4

1–5

1–5

1–6

1–7

1–14

1–15

1–17

1–17

1–18

1–18

1–19

1–20

1–21

1–21

1–21

P-1

P-1

P-1

P-2

P-3

P-4

toc–iii

2

3

Addressing Structure

How Counters Work

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Count Up (CTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Count Down (CTD)

Using Status Bits

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

High-Speed Counter (HSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

High-Speed Counter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

High-Speed Counter Data Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reset (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Basic Instructions in the Paper Drilling Machine Application Example . . . . . . . .

Adding File 2

Adding File 6

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

About the Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Comparison Instructions Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using Indexed Word Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using Indirect Word Addresses

Equal (EQU)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Not Equal (NEQ)

Less Than (LES)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Less Than or Equal (LEQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Greater Than (GRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Greater Than or Equal (GEQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Masked Comparison for Equal (MEQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Limit Test (LIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Comparison Instructions in the Paper Drilling Machine Application Example

Beginning a Subroutine in File 7

. . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

About the Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Math Instructions Overview

Entering Parameters

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using Indexed Word Addresses

Using Indirect Word Addresses

Updates to Arithmetic Status Bits

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Overflow Trap Bit, S:5/0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Changes to the Math Register, S:13 and S:14 . . . . . . . . . . . . . . . . . . . . . . . . .

2–4

2–4

2–5

2–5

2–5

2–5

2–7

2–7

2–1

2–2

2–2

2–2

2–2

2–3

2–3

2–3

2–4

1–22

1–23

1–24

1–24

1–25

1–25

1–26

1–26

1–28

1–31

1–32

1–32

1–33

3–1

3–3

3–3

3–3

3–3

3–4

3–4

3–4

3–5

toc–iv

Table of Contents

Using Floating Point Data File (F8:)

Add (ADD)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits

Subtract (SUB)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits

32-Bit Addition and Subtraction

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Math Overflow Selection Bit S:2/14

Multiply (MUL)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Changes to the Math Register, S:13 and S:14

Divide (DIV)

. . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Changes to the Math Register, S:13 and S:14 . . . . . . . . . . . . . . . . . . . . . . . . .

Double Divide (DDV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Changes to the Math Register, S:13 and S:14

Clear (CLR)

. . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Square Root (SQR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Scale with Parameters (SCP)

Entering Parameters

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits

Application Examples

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Scale Data (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Application Example 1 –

Converting 4mA–20mA Analog Input Signal to PID Process Variable . .

Application Example 2 –

Scaling an Analog Input to Control an Analog Output

Application Example 3 –

Convert Voltage Input to Percent (MicroLogix)

. . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . .

Absolute (ABS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits

Compute (CPT)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Swap (SWP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–12

3–12

3–12

3–13

3–13

3–13

3–13

3–14

3–14

3–15

3–15

3–17

3–17

3–18

3–5

3–6

3–6

3–6

3–6

3–7

3–7

3–10

3–10

3–10

3–11

3–11

3–11

3–18

3–19

3–23

3–24

3–24

3–24

3–25

3–25

3–25

3–26

3–27

toc–v

4

Entering Parameters

Arc Sine (ASN)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits

Arc Cosine (ACS)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits

Arc Tangent (ATN)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits

Cosine (COS)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Natural Log (LN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Log to the Base 10 (LOG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Sine (SIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tangent (TAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

X to the Power of Y (XPY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Math Instructions in the Paper Drilling Machine Application Example . . . . . . . .

Adding File 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Data Handling Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

About the Data Handling Instructions

Convert to BCD (TOD)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Changes to the Math Register, S:13 and S:14 . . . . . . . . . . . . . . . . . . . . . . . . .

Convert from BCD (FRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Changes to the Math Register, S:13 and S:14

Radian to Degrees (DEG)

. . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Degrees to Radians (RAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Decode 4 to 1 of 16 (DCD)

Entering Parameters

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits

Encode 1 of 16 to 4 (ENC)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–7

4–9

4–9

4–10

4–10

4–1

4–2

4–3

4–3

4–3

4–6

4–6

4–10

4–10

4–11

4–11

4–11

4–12

4–12

3–31

3–31

3–31

3–31

3–32

3–32

3–33

3–33

3–27

3–28

3–28

3–28

3–28

3–29

3–29

3–29

3–29

3–30

3–30

3–30

3–30

toc–vi

5

Table of Contents

Updates to Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Copy File (COP) and Fill File (FLL) Instructions . . . . . . . . . . . . . . . . . . . . . . . . .

Using COP

Using FLL

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Move and Logical Instructions Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using Indexed Word Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using Indirect Word Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Changes to the Math Register, S:13 and S:14

Move (MOV)

. . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Masked Move (MVM)

Entering Parameters

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits

And (AND)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Or (OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Exclusive Or (XOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Not (NOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Negate (NEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Updates to Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

FIFO and LIFO Instructions Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Effects on Index Register S:24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

FIFO Load (FFL) and FIFO Unload (FFU)

LIFO Load (LFL) and LIFO Unload (LFU)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Data Handling Instructions in the Paper Drilling Machine Application Example

Adding File 7

.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Program Flow Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Jump (JMP) and Label (LBL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters

Using JMP

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using LBL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Jump to Subroutine (JSR), Subroutine (SBR), and Return (RET) . . . . . . . . . . . . .

Nesting Subroutine Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–19

4–19

4–19

4–21

4–21

4–22

4–22

4–23

4–23

4–24

4–24

4–25

4–25

4–26

4–26

4–27

4–28

4–29

4–30

4–30

4–12

4–13

4–13

4–15

4–17

4–17

4–17

4–17

4–17

4–17

4–18

4–18

4–18

5–1

5–2

5–2

5–2

5–3

5–3

5–4

toc–vii

6

7

Using JSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using SBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using RET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Master Control Reset (MCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SLC Processor Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Temporary End (TND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Suspend (SUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Immediate Input with Mask (IIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Immediate Output with Mask (IOM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters

I/O Refresh (REF)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using an SLC 5/02 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using SLC 5/03 and Higher Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Program Flow Control Instructions in the

Paper Drilling Machine Application Example . . . . . . . . . . . . . . . . . . . . . . . . .

Adding File 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Application Specific Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bit Shift Instructions Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Effects on Index Register S:24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bit Shift Left (BSL) Bit Shift Right (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Sequencer Instructions Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Effects on Index Register S:24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Applications Requiring More than 16-Bits . . . . . . . . . . . . . . . . . . . . . . . . . . .

Sequencer Output (SQO) Sequencer Compare (SQC) . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters

Sequencer Load (SQL)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Application Specific Instructions in the Paper Drilling Machine Application Example . . . . . . . . . . . . . . . . . . . .

Using High-Speed Counter Instructions

About the High-Speed Counter Instructions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

High-Speed Counter Instructions Overview

Counter Data File Elements

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

High-Speed Counter (HSC)

Entering Parameters

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using the Up Counter and the Up Counter with Reset and Hold . . . . . . . . . .

5–4

5–5

5–5

5–6

5–7

5–7

5–8

5–8

5–8

5–8

5–9

5–9

5–10

5–10

5–11

5–12

5–12

6–1

6–2

6–2

6–3

6–4

6–7

6–7

6–7

6–7

6–8

6–13

6–13

6–16

7–1

7–2

7–3

7–3

7–6

7–6

7–8

toc–viii

8

Table of Contents

Using the Bidirectional Counter and the

Bidirectional Counter with Reset and Hold . . . . . . . . . . . . . . . . . . . . . . .

Using the Bidirectional Counter with

Reset and Hold with a Quadrature Encoder

High-Speed Counter Load (HSL)

. . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

High-Speed Counter Reset (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

High-Speed Counter Reset Accumulator (RAC) . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters

Operation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

High-Speed Counter Interrupt Enable (HSE) and Disable (HSD)

Using HSE

. . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using HSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Update High-Speed Counter Image Accumulator (OTE) . . . . . . . . . . . . . . . . . . . .

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

What Happens to the HSC When Going to REM Run Mode . . . . . . . . . . . . . . . . .

High-Speed Counter Instructions in the Paper Drilling Machine Application Example . . . . . . . . . . . . . . . . . . . .

SLC Communication Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

About the Communication Instructions

SLC 5/02 Message Instruction Overview

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Related Status File Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Available Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters

Using Status Bits

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timing Diagram for SLC 5/02 MSG Instruction

Control Block Layout

. . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Application Examples for SLC 5/02 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . .

Example 1

Example 2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Example 3

Example 4

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SLC 5/03 and SLC 5/04 Message Instruction Overview . . . . . . . . . . . . . . . . . . . .

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Related Status File Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Available Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters

Using Status Bits

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–10

7–23

7–23

7–24

7–24

7–25

7–25

7–25

7–26

7–15

7–19

7–19

7–19

7–22

7–22

7–23

7–30

8–6

8–8

8–9

8–9

8–10

8–13

8–14

8–15

8–15

8–16

8–17

8–17

8–18

8–1

8–2

8–2

8–2

8–3

8–3

8–4

8–5

toc–ix

9

10

MSG Instruction Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SLC 5/05 Message Instruction Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ethernet Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ethernet MSG Instruction Parameters

MSG Instruction Control Block

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interpreting Ethernet Status Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MSG Instruction Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timing Diagram for SLC 5/03, SLC 5/04, and SLC 5/05 MSG Instruction . . . . .

Examples: Ladder Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Enabling the MSG Instruction Via Ladder Logic . . . . . . . . . . . . . . . . . . . . . .

Enabling the MSG Instruction Via User Supplied Input

Using Local Messaging

. . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using Remote Messaging

Service Communications (SVC)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using an SLC 5/02 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using SLC 5/03 and Higher Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Channel Servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MicroLogix Communication Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Types of Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Initiator (Master) Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Responder (Slave) Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Message Instruction (MSG)

Entering Parameters

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timing Diagram for a Successful MSG Instruction . . . . . . . . . . . . . . . . . . . . . . . .

MSG Instruction Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Application Examples that Use the MSG Instruction . . . . . . . . . . . . . . . . . . . . . . .

Example 1

Example 2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Example 3

Example 4

Example 5

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Proportional Integral Derivative Instruction . . . . . . . . . . . . . . . . . . . . . . . . . .

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

The PID Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

The PID Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters

PID Instruction Flags

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–1

10–1

10–2

10–3

10–3

10–8

9–1

9–2

9–2

9–2

9–2

9–3

9–6

9–8

9–10

9–12

9–12

9–13

9–14

9–17

9–18

8–21

8–23

8–23

8–23

8–24

8–25

8–29

8–31

8–34

8–37

8–37

8–38

8–39

8–42

8–58

8–58

8–59

8–60

toc–x

11

Table of Contents

Control Block Layout

Runtime Errors

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PID and Analog I/O Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using the SCL Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using the SCP Instruction

Application Notes

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input/Output Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Scaling to Engineering Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Zero–crossing Deadband DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Limiting with Anti-Reset Windup . . . . . . . . . . . . . . . . . . . . . . . . . . . .

The Manual Mode

PID Rungstate

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Feed Forward or Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Time Proportioning Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PID Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–10

10–11

10–13

10–13

10–14

10–17

10–17

10–17

10–19

10–19

10–20

10–20

10–21

10–22

10–22

10–24

ASCII Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ASCII Instruction Overview

Protocol Parameter Overview

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Test Buffer for Line (ABL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Number of Characters In Buffer (ACB)

Entering Parameters

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

String to Integer (ACI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ASCII Clear Receive and/or Send Buffer (ACL) . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters

String Concatenate (ACN)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters

String Extract (AEX)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ASCII Handshake Lines (AHL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Integer to String (AIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ASCII Read Characters (ARD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timing Diagram for a Successful ARD, ARL, AWA, and AWT Instruction .

ASCII Read Line (ARL)

Entering Parameters

String Search (ASC)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–7

11–7

11–9

11–10

11–10

11–11

11–11

11–12

11–12

11–13

11–13

11–1

11–2

11–3

11–5

11–6

11–6

11–14

11–15

11–15

11–17

11–18

11–18

11–20

toc–xi

12

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ASCII String Compare (ASR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ASCII Write with Append (AWA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using In-line Indirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ASCII Write (AWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ASCII Instruction Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ASCII Conversion Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–20

11–21

11–21

11–22

11–22

11–24

11–25

11–25

11–27

11–28

Understanding Interrupt Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

User Fault Routine Overview

Status File Data Saved

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Creating a User Fault Subroutine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

User Interrupt Routine Application Example . . . . . . . . . . . . . . . . . . . . . . . . .

Selectable Timed Interrupt Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Basic Programming Procedure for the STI Function . . . . . . . . . . . . . . . . . . . .

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STI Subroutine Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupt Latency and Interrupt Occurrences . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Status File Data Saved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STI Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STD and STE Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Selectable Timed Disable – STD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Selectable Timed Enable – STE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STD/STE Zone Example

Selectable Timed Start (STS)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Discrete Input Interrupt Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Basic Programming Procedure for the DII Function . . . . . . . . . . . . . . . . . . . .

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Counter Mode

Event Mode

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DII Subroutine Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupt Latency and Interrupt Occurrences . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Status File Data Saved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reconfigurability

DII Parameters

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Discrete Input Interrupt Application Example . . . . . . . . . . . . . . . . . . . . . . . . .

12–20

12–20

12–21

12–21

12–22

12–23

12–25

12–11

12–15

12–15

12–15

12–15

12–17

12–17

12–18

12–19

12–19

12–19

12–1

12–2

12–2

12–2

12–4

12–7

12–7

12–8

12–8

12–9

12–10

12–11

toc–xii

13

Table of Contents

I/O Interrupt Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Basic Programming Procedure for the I/O Interrupt Function . . . . . . . . . . . .

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupt Subroutine (ISR) Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupt Latency and Interrupt Occurrences . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Status File Data Saved

I/O Interrupt Parameters

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O Interrupt Disable (IID) and I/O Interrupt Enable (IIE) . . . . . . . . . . . . . . . . . . .

IID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IIE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IID/IIE Zone Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reset Pending Interrupt (RPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupt Subroutine (INT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–27

12–27

12–28

12–28

12–29

12–30

12–31

12–31

12–33

12–33

12–33

12–34

12–35

12–35

12–35

SLC Communication Protocols

Overview

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DH-485 Communication Protocol

DH-485 Network Protocol

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Data Highway Plus Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Global Status Word Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PLC–5 to SLC 500 Communication Using PLC–2 Type MSG Commands

How the PLC-5 Processors Address Data

. .

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using the SLC 500 CIF File (PLC-2 Emulation) . . . . . . . . . . . . . . . . . . . . . .

Programming to Handle the Word/Byte Addressing Differences . . . . . . . . . .

SLC 5/03, SLC 5/04, and SLC 5/05 Processors to

PLC-5 Communication Using SLC 500 or PLC-5 MSG Commands

DF1 Via RS-232 Communication Protocol

DF1 Full-Duplex Protocol

DF1 Half-Duplex Master

. . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DF1 Half-Duplex Master/Slave Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RTS Send Delay and RTS Off Delay Parameters

ASCII Communication Protocol

Using the Passthru Features

. . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–18

13–20

13–20

13–23

Considerations When Communicating as a DF1 Slave on a Multi–drop Link

Using Modems that Support DF1 Communication Protocols . . . . . . . . . . . . . . . .

13–28

13–29

Modem Control Line Operation in SLC 5/03, SLC 5/04 and SLC 5/05 Processors

13–30

DF1 Full–Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–30

DF1 Half-Duplex Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–31

13–32

13–33

13–34

13–35

13–1

13–1

13–4

13–4

13–5

13–9

13–11

13–15

13–16

13–16

13–17

toc–xiii

14

15

DH+ to DH-485 Passthru – (All SLC 5/04 processors) . . . . . . . . . . . . . . . . . .

DF1 to DH+ Passthru – (SLC 5/04 OS401 and above processors) . . . . . . . . .

Remote I/O Passthru

(SLC 5/03 OS302, SLC 5/04 OS401, and SLC 5/05 processors)

Considerations when DF1 to DH+ Passthru is Enabled

. . . . . .

. . . . . . . . . . . . . . . . .

Ethernet Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SLC 5/05 Performance Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SLC 5/05 and PC Connections to the Ethernet Network . . . . . . . . . . . . . . . . .

Configuring the Ethernet Channel on the SLC 5/05 . . . . . . . . . . . . . . . . . . . .

Configuration Using RSLogix500 Programming Software . . . . . . . . . . . . . . .

Configuration Via BOOTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using Subnet Masks and Gateways . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–35

13–35

13–35

13–36

13–37

13–38

13–39

13–40

13–41

13–41

13–47

MicroLogix Communication Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Automatic Protocol Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RS-232 Communication Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DF1 Full-Duplex Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DF1 Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DF1 Full-Duplex Channel 0 Configuration Parameters . . . . . . . . . . . . . . . . .

DF1 Half-Duplex Slave Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DF1 Half-Duplex Slave Configuration Parameters . . . . . . . . . . . . . . . . . . . . .

Considerations When Communicating as a DF1 Slave on a Multi-drop Link

Ownership Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using Modems that Support DF1 Communication Protocols

DH-485 Communication Protocol

. . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DH-485 Network Description

DH-485 Token Rotation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DH-485 Configuration Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DH-485 Network Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Devices that use the DH-485 Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Important DH-485 Network Planning Considerations

Example DH-485 Connections

. . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14–1

14–2

14–2

14–3

14–3

14–3

14–6

14–7

14–8

14–9

14–10

14–11

14–12

14–12

14–13

14–13

14–14

14–15

14–18

Troubleshooting Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Automatically Clearing Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SLC Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MicroLogix 1000 Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Manually Clearing Faults (SLC Processors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using the Fault Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fault Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MicroLogix 1000 Controller Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15–1

15–1

15–1

15–2

15–2

15–3

15–3

15–3

toc–xiv

A

B

C

Table of Contents

SLC Processor Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Troubleshooting SLC 5/03 and Higher Processors . . . . . . . . . . . . . . . . . . . . . . . . .

Powerup LED Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Identifying Processor Errors while Downloading an Operating System . . . . .

15–8

15–20

15–20

15–20

MicroLogix 1000 Controller Status File

Status File Overview

SLC Status File

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Status File Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Status File Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Status File Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Conventions Used in the Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Memory Usage and Instruction Execution Times

MicroLogix 1000 Controllers

. . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MicroLogix 1000 Execution Time Example . . . . . . . . . . . . . . . . . . . . . . . . . .

Estimating Memory Usage for Your MicroLogix 1000 Control System . . . . .

MicroLogix 1000 Memory Usage Example . . . . . . . . . . . . . . . . . . . . . . . . . .

Memory Usage Overview for the SLC Processors

Fixed and SLC 5/01 Processors

. . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fixed or SLC 5/01 Execution Time Example . . . . . . . . . . . . . . . . . . . . . . . . .

Estimating Total Memory Usage of Your System

Using a Fixed or SLC 5/01 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fixed Controller Memory Usage Example . . . . . . . . . . . . . . . . . . . . . . . . . . .

SLC 5/01 Processor Memory Usage Example

SLC 5/02 Processor

. . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SLC 5/02 Execution Time Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Estimating Total Memory Usage of Your System

Using a SLC 5/02 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SLC 5/02 Memory Usage Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SLC 5/02 – Instructions Having Indexed Addresses . . . . . . . . . . . . . . . . . . . .

SLC 5/02 – Instructions Having M0 and M1 Data File Addresses . . . . . . . . .

User Word Comparison Between SLC 5/03 (and higher) Processors and the SLC 5/02 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Instruction Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Data Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SLC 5/03 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SLC 5/03 Execution Time Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SLC 5/03 Processor Floating Point Operations . . . . . . . . . . . . . . . . . . . . . . . .

Estimating Total Memory Usage of Your System

Using an SLC 5/03 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A–1

A–2

A–3

B–1

B–2

B–5

B–5

C–21

C–21

C–22

C–23

C–29

C–30

C–31

C–11

C–12

C–13

C–14

C–17

C–18

C–19

C–20

C–20

C–1

C–1

C–5

C–6

C–7

C–7

C–8

C–10

toc–xv

D

toc–xvi

SLC 5/03 Memory Usage Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SLC 5/03 – Instructions Having Indexed Addresses . . . . . . . . . . . . . . . . . . . .

SLC 5/03 – Instructions Having M0 and M1 Data File Addresses

SLC 5/04 and SLC 5/05 Processors

. . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SLC 5/04 or SLC 5/05 Execution Time Example . . . . . . . . . . . . . . . . . . . . . .

SLC 5/04 and SLC 5/05 Processor Floating Point Operations . . . . . . . . . . . .

Estimating Total Memory Usage of Your System

Using an SLC 5/04 or SLC 5/05 Processor . . . . . . . . . . . . . . . . . . . . . . .

SLC 5/04 and SLC 5/05 – Instructions Having Indexed Addresses . . . . . . . .

SLC 5/04 and SLC 5/05 – Instructions Having

M0 and M1 Data File Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Execution Times for Word-Level Indirect Addresses

Execution Times for Bit-Level Indirect Addresses

. . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . .

Instruction Execution Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Estimating Scan Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Processor Operating Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Access Times for M0/M1 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupt Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MicroLogix 1000 User Interrupt Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SLC User Interrupt Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Calculating Interrupt Latency for SLC 5/03

Selectable Timed Interrupt (STI)

. . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Discrete Input Interrupt (DII)

I/O Event Interrupt (IOI)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Calculating Interrupt Latency for SLC 5/04 or SLC 5/05

Selectable Timed Interrupt (STI)

. . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Discrete Input Interrupt (DII)

I/O Event Interrupt (IOI)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Example – SLC 5/03 (OS302, FRN10 and higher) Processor

Selectable Timed Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Example – SLC 5/05 Processor Selectable Timed Interrupt

Scan Time Worksheets

. . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Defining Worksheet Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Worksheet A – Estimating the Scan Time of Your

MicroLogix 1000 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Worksheet B – Estimating the Scan Time of Your Fixed Controller . . . . . . . .

Worksheet C – Estimating the Scan Time of Your SLC 5/01 Processor . . . . .

Worksheet D – Estimating the Scan Time of Your SLC 5/02 Processor

Worksheet E – Estimating the Scan Time of Your SLC 5/03 Processor

. . . . .

. . . . .

Worksheet F – Estimating Scan Time of Your SLC 5/04 or 5/05 Processor . .

C–42

C–43

C–43

C–44

C–45

C–46

C–47

C–32

C–33

C–33

C–34

C–40

C–41

D–6

D–6

D–7

D–7

D–8

D–9

D–11

D–13

D–16

D–19

D–1

D–2

D–2

D–3

D–3

D–3

D–4

D–4

D–4

D–4

D–5

D–5

D–5

D–5

E

F

G

Table of Contents

Scan Time for I/O Modules

Example Scan Time Calculation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Example: Worksheet C – Estimating the Scan Time of an

SLC 5/01 Processor Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Programming Instruction References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Valid Addressing Modes and File Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Understanding the Different Addressing Modes . . . . . . . . . . . . . . . . . . . . . . .

Data File Organization and Addressing

Understanding File Organization

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Processor File Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Understanding How Processor Files are Stored and Accessed . . . . . . . . . . . . . . . .

Download . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Addressing Data Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Specifying Logical Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Specifying Indexed Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Monitoring Indexed Addresses

Specifying an Indirect Address

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Addressing File Instructions – Using the File Indicator (#)

Numeric Constants

. . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

M0 and M1 Data Files – Specialty I/O Modules

Addressing M0–M1 Files

. . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Restrictions on Using M0-M1 Data File Addresses

Monitoring Bit Addresses

. . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transferring Data Between Processor Files and M0 or M1 Files

Access Time

. . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Minimizing the Scan Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Capturing M0-M1 File Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Specialty I/O Modules with Retentive Memory . . . . . . . . . . . . . . . . . . . . . . .

G Data Files – Specialty I/O Modules

Editing G File Data

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Number Systems

Binary Numbers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Positive Decimal Values

Negative Decimal Values

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Hexadecimal Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D–22

D–24

D–25

E–1

E–1

E–2

F–15

F–17

F–18

F–21

F–22

F–22

F–22

F–23

F–24

F–24

F–25

F–1

F–1

F–1

F–4

F–5

F–5

F–6

F–6

F–7

F–8

F–13

F–26

F–26

F–27

F–28

G–1

G–1

G–1

G–2

G–3

toc–xvii

H

Hex Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Binary Floating-Point Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Application Example Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Paper Drilling Machine Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Paper Drilling Machine Operation Overview

Drill Mechanism Operation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Conveyor Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Drill Calculation and Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Paper Drilling Machine Ladder Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Time Driven Sequencer Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Time Driven Sequencer Ladder Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Event Driven Sequencer Application Example

Event Driven Sequencer Ladder Program

. . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

On/Off Circuit Application Example

On/Off Circuit Ladder Program

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interfacing with Enhanced Bar Code Decoders

Over DH-485 Network Using the MSG Instruction

Processor and Decoder Operation

. . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Set Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Sequence of Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Optimizing MSG Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Example MSG Instruction Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Example Scanner and Decoder Configuration . . . . . . . . . . . . . . . . . . . . . . . . .

Example Ladder Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

G–5

G–6

H–1

H–2

H–3

H–3

H–3

H–4

H–4

H–16

H–16

H–18

H–18

H–20

H–21

H–22

H–22

H–23

H–24

H–25

H–26

H–27

H–28

H–29

I–1

toc–xviii

Preface

Preface

Read this preface to familiarize yourself with the rest of the manual. It provides information concerning:

• who should use this manual

• purpose of this manual

• conventions used in this manual

Who Should Use this Manual

Use this manual if you are responsible for designing, installing, programming, or troubleshooting control systems that use Allen–Bradley small logic controllers.

You should have a basic understanding of SLC 500

products. If you do not, contact your local Allen–Bradley representative for the proper training before using this product.

Purpose of this Manual

This manual is a reference guide for the SLC 500 processors and the

MicroLogix 1000 controllers. This manual:

• provides status file functions

• provides the instructions used in your ladder logic programs

• complements the online help available at the terminal

P-1

Contents of this Manual

Chapter

1

2

3

Preface

Title

Basic Instructions

Comparison Instructions

4

5

6

7

8

9

10

11

12

13

14

Data Handling Instructions

Program Flow Instructions

Application Specific

Instructions

Using High-Speed Counter

Instructions

SLC Communication

Instructions

MicroLogix Communication

Instruction

Proportional Integral

Derivative Instruction

ASCII Instructions

Understanding Interrupt

Routines

Understanding the SLC

Communication Protocols

Understanding the

MicroLogix Communication

Protocols

Troubleshooting Faults

15

Appendix A

MicroLogix 1000 Controller

Status File

Appendix B

Math Instructions

SLC Status File

Contents

Describes the purpose, background, and scope of this manual. Also specifies the audience for whom this manual is intended.

Describes how to use ladder logic instructions for relay replacement functions, counting, and timing.

Describes the comparison instructions which allow you to compare values of data.

Describes the math instructions which allow you to perform computation and math operations on individual words.

Describes how to perform data handling instructions, including move and logical instructions and FIFO and LIFO instructions.

Describes the ladder logic instructions that affect program flow and execution.

Describes the bit shift, sequencer and STI related instructions.

Describes the four modes of the high-speed counter instruction and its related instructions.

Describes the message and service communication instruction and their associated parameters.

Describes the message and service communication instruction and their associated parameters.

Describes the PID concept, equation, associated parameters, and control block layout..

Describes the ASCII instructions and their usages.

Describes the selectable timed interrupts, the discrete input interrupt, and I/O interrupts and their associated parameters.

Explains the different types of communication protocols used with SLC 500 processors.

Explains the different types of communication protocols used with SLC 500 processors.

Explains how to interpret and correct problems with the software and processor.

Describes major and minor faults, diagnostic information, processor modes, scan times, baud rates, and system node addresses for the MicroLogix 1000 controllers.

Describes major and minor faults, diagnostic information, processor modes, scan times, baud rates, and system node addresses for the SLC 500 processors.

P-2

Preface

Chapter

Appendix C

Title

Memory Usage and

Instruction Execution Times

Appendix D

Estimating Scan Time

Appendix E

Appendix F

Programming Instruction

References

Data File Organization and

Addressing

Appendix G

Number Systems

Appendix H

Application Example

Programs

Contents

Provides the user memory capacity and instruction execution times. Also describes how to estimate the total memory usage of a system.

Provides interrupt latency, M0/M1 access time information, and worksheets for estimating scan times.

Provides a listing of instructions with their parameters and valid file types.

Provides details on data files, covering file formats and how to create and delete data.

Describes the hexadecimal, binary, and decimal numbering systems along with the floating point format.

Provides advanced application examples for the high-speed counter, sequencer, and bit shift instructions.

Related Documentation

The following documents contain additional information concerning Allen–Bradley

SLC products. To obtain a copy, contact your local Allen–Bradley office or distributor.

Read this Document

SLC 500 System Overview

For

An overview of the SLC 500 family of products

An introduction to APS for first–time users, containing basic concepts but focusing on simple tasks and exercises, and allowing the reader to begin programming in the shortest time possible

A procedural and reference manual for technical personnel who use the APS import/export utility to convert APS files to

ASCII and conversely ASCII to APS files

APS Quick Start for New Users

APS Import/Export User Manual

A training and quick reference guide to APS

A guide of common procedures used in APS

A procedural manual for technical personnel who use APS to develop control applications

A description on how to install and use your Fixed SLC 500 programmable controller

SLC 500 Software Programmer’s Quick Reference Guide,

Publication Number ABT-1747-TSJ50

 available on

PASSPORT at a list price of $50.00

SLC 500 Software Common Procedures Guide, Publication

Number ABT-1747-TSJ50

 available on PASSPORT at a list price of $50.00

Rockwell Software Advanced Programming Software (APS)

User Manual

Installation and Operation Manual for Fixed Hardware Style

Programmable Controllers, Catalog Number 1747-6.1

P-3

For

A description on how to install and use your Modular SLC 500 programmable controller

A description on how to install and use your MicroLogix 1000 controllers. This manual also contains status file data and instruction set information for the micro controllers.

A complete listing of current Allen–Bradley documentation, including ordering instructions. Also indicates whether the documents are available on CD–ROM or in multi–languages.

Read this Document

Installation and Operation Manual for Modular Hardware Style

Programmable Controllers, Publication Number 1747-6.2

MicroLogix 1000 Controllers User Manual, Publication Number

1761-6.3.

Allen–Bradley Publication Index, Publication Number SD499

A glossary of industrial automation terms and abbreviations

Allen–Bradley Industrial Automation Glossary, Publication

Number AG-7.1

Common Techniques Used in this Manual

The following conventions are used throughout this manual:

Bulleted lists provide information, not procedural steps.

Numbered lists provide sequential steps or hierarchical information.

Text in this font

indicates words or phrases you should type.

Italic type is used for emphasis.

The following table summarizes the conventions used to distinguish the differences between the SLC 5/03, SLC 5/04, and SLC 5/05 keyswitch positions, the processor modes, and the actual display on the programmer status line.

When Referring to the

Keyswitch Position

RUN position

REMote position

PROGram position

When Referring to the

Processor Mode

Run mode

Run mode

Program mode

Test – Single Step mode

Test – Single Scan mode

Test – Continuous Scan mode

Program mode

When Referring to the

Status Line

RUN

REM RUN

REM PROG

REM SRG

REM SSN

REM CSN

PROG

P-4

Basic Instructions

1

Basic Instructions

This chapter contains general information about the basic instructions and explains how they function in your application program. Each of the basic instructions includes information on:

• what the instruction symbol looks like

• how to use the instruction

In addition, the last section contains an application example for a paper drilling machine that shows the basic instructions in use.

Bit Instructions

Mnemonic

Instruction

Name

XIC

XIO

Examine if Closed Examines a bit for an On condition.

Examine if Open Examines a bit for an Off condition.

OTE

OTL and

OTU

OSR

Output Energize

Output Latch and

Output Unlatch

One-Shot Rising

Turns a bit On or Off.

OTL turns a bit on when the rung is executed, and this bit retains its state when the rung is not executed or a power cycle occurs. OTU turns a bit off when the rung is executed, and this bit retains its state when the rung is not executed or when power cycle occurs.

Triggers a one-time event.

1–9

1–9

1–10

1–10

1–11

continued on next page

1–1

Timer/Counter Instructions

Mnemonic

Instruction

Name

TON

Timer On-Delay

TOF

RTO

Timer Off-Delay

Retentive Timer

CTU

CTD

HSC

RES

Count Up

Count Down

High-Speed

Counter

Reset

Counts timebase intervals when the instruction is true.

Counts timebase intervals when the instruction is false.

Counts timebase intervals when the instruction is true and retains the accumulated value when the instruction goes false or when power cycle occurs.

Increments the accumulated value at each false–to– true transition and retains the accumulated value when the instruction goes false or when power cycle occurs.

Decrements the accumulated value at each false– to–true transition and retains the accumulated value when the instruction goes false or when power cycle occurs.

Counts high-speed pulses from a fixed controller high-speed input.

Resets the accumulated value and status bits of a timer or counter. Do not use with TOF timers.

1–17

1–18

1–19

1–24

1–25

1–26

1–31

About the Basic Instructions

These instructions, when used in ladder programs, represent hardwired logic circuits used for the control of a machine or equipment.

The basic instructions are separated into three groups: bit, timer, and counter.

Before you learn about the instructions in each of these groups, we suggest that you read the overview that precedes the group:

Bit Instructions Overview

Timer Instructions Overview

Counter Instructions Overview

1–2

Basic Instructions

Bit Instructions Overview

Note

These instructions operate on a single bit of data. During operation, the processor may set or reset the bit, based on logical continuity of ladder rungs. You can address a bit as many times as your program requires.

Using the same address with multiple output instructions is not recommended.

Bit instructions are used with the following data files:

Output and Input Data Files (Files O0: and I1:)

These represent external outputs and inputs. Bits in file 1 are used to represent external inputs. In most cases, a single 16-bit word in these files will correspond to a slot location in your controller, with bit numbers corresponding to input or output terminal numbers. Unused bits of the word are not available for use.

The table below explains the addressing format for outputs and inputs. Note that the format specifies e

as the slot number and s

as the word number. When you are dealing with file instructions, refer to the element as e.s

(slot and word), taken together.

Format

O:e.s/b

I:e.s/b

Explanation

O

Output

I

Input

:

Element delimiter

e

Slot number

(decimal)

Slot 0, adjacent to the power supply in the first chassis, applies to the processor module (CPU). Succeeding slots are I/O slots, numbered from 1 to a maximum of 30.

s

.

Word delimiter. Required only if a word number is necessary as noted below.

Word number

Required if the number of inputs or outputs exceeds 16 for the slot. Range: 0–255 (range accommodates multi-word

“specialty cards”)

/

Bit delimiter

b

Terminal number

Inputs: 0–15

Outputs: 0–15

1–3

Examples (applicable to the controller shown on page F–12):

O:3/15

O:5/0

O:10/11

I:7/8

I:2.1/3

Word addresses:

Output 15, slot 3

Output 0, slot 5

Output 11, slot 10

Input 8, slot 7

Input 3, slot 2, word 1

O:5

O:5.1

I:8

Output word 0, slot 5

Output word 1, slot 5

Input word 0, slot 8

Default Values: Your programming device will display an address more formally. For example, when you assign the address O:5/0, the programming device will show it as O:5.0/0 (Output file, slot 5, word 0, terminal 0).

Status File (File S2:)

You cannot add to or delete from the status file. The MicroLogix 1000 controller

status file is explained in appendix A and the SLC 500 processor status file is

explained in appendix B. You can address various bits and words as follows:

Format Explanation

S:e/b

S

Status file

:

Element delimiter

e

Element number

Ranges from 0–15 in a fixed or SLC 5/01 controller,

0–32 in an SLC 5/02,

0–83 in an SLC 5/03 OS300,

0–96 in an SLC 5/03 OS301 and later and 5/04 OS400, and

0–64 in an SLC 5/04 OS401 and SLC 5/05 processors.

These are 1-word elements. 16 bits per element.

/

Bit delimiter

b

Bit number Bit location within the element. Ranges from 0–15.

Examples:

S:1/15 Element 1, bit 15. This is the “first pass” bit, which you can use to initialize instructions in your program.

S:3 Element 3. The lower byte of this element is the current scan time. The upper byte is the watchdog scan time.

1–4

Basic Instructions

Bit Data File (B3:)

File 3 is the bit file, used primarily for bit (relay logic) instructions, shift registers, and sequencers. The maximum size of the file is 256 1-word elements, a total of

4096 bits. You can address bits by specifying the element number (0 to 255) and the bit number (0 to 15) within the element. You can also address bits by numbering them in sequence, 0 to 4095.

You can also address elements of this file.

Format

Bf:e/b

Format

Bf/b

Explanation

B

Bit type file

f

File number. Number 3 is the default file. A file number between 9–255 can be used if additional storage is required.

:

Element delimiter

e

Element number

Ranges from 0–255. These are

1-word elements. 16 bits per element.

/

Bit delimiter

b

Bit number

Bit location within the element.

Ranges from 0–15.

Explanation

B

/ f b

Same as above.

Same as above.

Same as above.

Bit number

Numerical position of the bit within the file. Ranges from 0–4095.

Examples

B3:3/14

Bit 14, element 3

B3:252/00

Bit 0, element 252

B3:9

Bits 0–15, element 9

Examples

B3/62

Bit 62

B3/4032

Bit 4032

Timer and Counter Data Files (T4: and C5:)

See pages 1–15 and 1–22 respectively for the addressing formats.

1–5

Control Data File (R6:)

These instructions use various control bits. These are 3-word elements, used with

Bit Shift, FIFO, LIFO, Sequencer instructions, and ASCII instructions ABL, ACB,

AHL, ARD, ARL, AWA, and AWT. Word 0 is the status word, word 1 indicates the length of stored data, and word 2 indicates position. This is shown in the following figure.

In the control element there are eight status bits and an error code byte. A fixed controller and an SLC 5/01 control element has six bits. Bits EU and EM are not used by the processor.

15 14 13 12 11 10

Control Element

9 8 7 6 5 4 3

EN EU DN EM ER UL IN FD Error Code

Length of Bit array or File (LEN)

Bit Pointer or Position (POS)

2 1 0

Word

0

1

2

Addressable Bits Addressable Words

EN = Enable

EU = Unload Enable

LEN = Length

POS = Position

DN = Done

EM = Stack Empty

ER = Error

UL = Unload (Bit shift only)

IN = Inhibit

(This is the Running Bit [RN bit 9] for ASCII instructions)

FD = Found (SQC only)

Error Code value is displayed in HEX and is not addressable.

Assign control addresses as follows:

Format

Rf:e

Explanation

R

Control file

f

File number. Number 6 is the default file. A file number between 9–255 can be used if additional storage is required.

:

Element delimiter

e

Element number

Ranges from 0–255. These are 3-word elements. See figure above.

1–6

Basic Instructions

Example: R6:2 Element 2, control file 6.

Address bits and words by using the format Rf:e.s/b where Rf:e is explained above, and:

. is the word delimiter

s indicates subelement

/ is the bit delimiter

b indicates bit

R6:2/15 or

R6:2/EN

Enable bit

R6:2/14 or

R6:2/EU

Unload Enable bit

R6:2/13 or

R6:2/DN

Done bit

R6:2/12 or

R6:2/EM

Stack Empty bit

R6:2/11 or

R6:2/ER

Error bit

R6:2/10 or

R6:2/UL

Unload bit

R6:2/9

or

R6:2/IN

Inhibit bit

R6:2/8

or

R6:2/FD

Found bit

R6:2.1

or R6:2.LEN Length value

R6:2.2

or R6:2.POS Position value

R6:2.1/0

R6:2.2/0

Bit 0 of length value

Bit 0 of position value

Integer Data File (N7:)

Use these addresses (at the bit level) as your program requires. These are 1-word elements, addressable at the element and bit level.

1–7

1–8

Assign integer addresses as follows:

Format

Nf:e/b

Explanation

N

Integer file

f

File number. Number 7 is the default file. A file number between 9–255 can be used if additional storage is required.

:

Element delimiter

e

Element number

/

Bit delimiter

b

Bit number

Ranges from 0–255. These are 1-word elements.

16 bits per element.

Bit location within the element. Ranges from 0–15.

Examples:

N7:2

N7:2/8

N10:36

Element 2, integer file 7

Bit 8 in element 2, integer file 7

Element 36, integer file 10 (file 10 designated as an integer file by the user)

Basic Instructions

Examine if Closed (XIC)

] [

Input Instruction

✓ ✓ ✓ ✓ ✓ ✓ ✓

Use the XIC instruction in your ladder program to determine if a bit is On. When the instruction is executed, if the bit addressed is on (1), then the instruction is evaluated as true. When the instruction is executed, if the bit addressed is off (0), then the instruction is evaluated as false.

Bit Address State

0

1

False

True

XIC Instruction

Examples of devices that turn on or off include:

• a push button wired to an input (addressed as I:0/4)

• an output wired to a pilot light (addressed as O:0/2)

• a timer controlling a light (addressed as T4:3/DN)

Examine if Open (XIO)

]/[

Input Instruction

✓ ✓ ✓ ✓ ✓ ✓ ✓

Use the XIO instruction in your ladder program to determine if a bit is Off. When the instruction is executed, if the bit addressed is off (0), then the instruction is evaluated as true. When the instruction is executed, if the bit addressed is on (1), then the instruction is evaluated as false.

Bit Address State

0

1

True

False

XIO Instruction

Examples of devices that turn on or off include:

• motor overload normally closed (N.C.) wired to an input (I:0/10)

• an output wired to a pilot light (addressed as O:0/4)

• a timer controlling a light (addressed as T4:3/DN)

1–9

Output Energize (OTE)

( )

Output Instruction

Note

✓ ✓ ✓ ✓ ✓ ✓ ✓

Use the OTE instruction in your ladder program to turn on a bit when rung conditions are evaluated as true.

An example of a device that turns on or off is an output wired to a pilot light

(addressed as O:0/4).

OTE instructions are reset when:

You enter or return to the REM Run or REM Test mode or power is restored.

The OTE is programmed within an inactive or false Master Control Reset

(MCR) zone.

A bit that is set within a subroutine using an OTE instruction remains set until the subroutine is scanned again.

Output Latch (OTL) and

Output Unlatch (OTU)

✓ ✓ ✓ ✓ ✓ ✓ ✓

(L)

(U)

Output Instructions

OTL and OTU are retentive output instructions. OTL can only turn on a bit, while

OTU can only turn off a bit. These instructions are usually used in pairs, with both instructions addressing the same bit.

Your program can examine a bit controlled by OTL and OTU instructions as often as necessary.

Under fatal error conditions, physical outputs are turned off. Once the error conditions are cleared, the controller resumes operation using the data table value of the operand.

1–10

Basic Instructions

Using OTL

When you assign an address to the OTL instruction that corresponds to the address of a physical output, the output device wired to this screw terminal is energized when the bit is set (turned on or enabled).

When rung conditions become false (after being true), the bit remains set and the corresponding output device remains energized.

When enabled, the latch instruction tells the controller to turn on the addressed bit.

Thereafter, the bit remains on, regardless of the rung condition, until the bit is turned off (typically by a OTU instruction in another rung).

Using OTU

When you assign an address to the OTU instruction that corresponds to the address of a physical output, the output device wired to this screw terminal is de–energized when the bit is cleared (turned off or disabled).

The unlatch instruction tells the controller to turn off the addressed bit. Thereafter, the bit remains off, regardless of the rung condition, until it is turned on (typically by a OTL instruction in another rung).

One–Shot Rising (OSR)

✓ ✓ ✓ ✓ ✓ ✓ ✓

[OSR]

Input Instruction

The OSR instruction is a retentive input instruction that triggers an event to occur one time. Use the OSR instruction when an event must start based on the change of state of the rung from false-to-true.

When the rung conditions preceding the OSR instruction go from false-to-true, the

OSR instruction will be true for one scan. After one scan is complete, the OSR instruction becomes false, even if the rung conditions preceding it remain true. The

OSR instruction will only become true again if the rung conditions preceding it transition from false-to-true.

The SLC 500 and SLC 5/01 processors allow you to use one OSR instruction per output in a rung; the OSR cannot be within a branch. The SLC 5/02 and higher processors and MicroLogix 1000 controllers allow you to use one OSR instruction per output in a rung; putting the OSR within a branch is permitted.

1–11

Entering Parameters

Note

The address assigned to the OSR instruction is not the one-shot address referenced by your program, nor does it indicate the state of the OSR instruction. This address allows the OSR instruction to remember its previous rung state.

Use a bit address from either the bit or integer data file. The addressed bit is set (1) for one scan when rung conditions preceding the OSR instruction are true (even if the OSR instruction becomes false); the bit is reset (0) when rung conditions preceding the OSR instruction are false.

The bit address you use for this instruction must be unique. Do not use it elsewhere

in the program.

Do not use an input or output address to program the address parameter of the OSR

instruction.

Examples

The following rungs illustrate the use of the OSR instruction. The first four rungs apply to SLC 500 and SLC 5/01 processors. The fifth rung involves output branching and applies to the SLC 5/02 and higher processors and MicroLogix 1000 controllers.

SLC 500 and SLC 5/01 Processors

I:1.0

] [

0

B3

[OSR]

0

O:3.0

( )

0

When the input instruction goes from false-to-true, the OSR instruction conditions the rung so that the output goes true for one program scan. The output goes false and remains false for successive scans until the input makes another false-to-true transition.

I:1.0

] [

0

B3

[OSR]

0

TOD

TO BCD

Source Tf:0.ACC

Dest O:3

In this case, the accumulated value of a timer is converted to

BCD and moved to an output word where an LED display is connected. When the timer is running, the accumulated value is changing rapidly. This value can be frozen and displayed for each false-to-true transition of the input condition of the rung.

1–12

Basic Instructions

Using an OSR Instruction in a Branch (SLC 500 and SLC 5/01 Processors)

I:1.0

] [

0

B3

[OSR]

0

O:3.0

( )

0

O:3.0

( )

1

In the above rung, the OSR instruction is not permitted inside a branch.

I:1.0

] [

0

B3

[OSR]

0

O:3.0

( )

0

O:3.0

( )

1

In this case, the OSR instruction is not in the branch so the rung is legal.

The SLC 500 and SLC 5/01 processors allow you to use one OSR instruction per rung.

When using a SLC 500 or SLC 5/01 processor, do not place input conditions after the OSR instruction in a rung. Unexpected operation may occur.

SLC 5/02 (and higher) Processors and MicroLogix 1000 Controllers

I:1.0

] [

0

B3

]/[

1

B3

] [

2

B3

[OSR]

0

B3

[OSR]

3

O:3.0

( )

0

O:3.0

( )

1

The SLC 5/02 and higher processors and MicroLogix 1000 controllers allow you to use one OSR instruction per output in a rung.

1–13

Timer Instructions Overview

Each timer address is made of a 3-word element. Word 0 is the control word, word 1 stores the preset value, and word 2 stores the accumulated value.

Word 0

Word 1

Word 2

15 14 13

EN TT DN Internal Use

Preset Value

Accumulator Value

Addressable Bits

EN = Bit 15 Enable

TT = Bit 14 Timer Timing

DN = Bit 13 Done

Addressable Words

PRE = Preset Value

ACC = Accumulated Value

Bits labeled “Internal Use” are not addressable.

Entering Parameters

Accumulator Value (.ACC)

This is the time elapsed since the timer was last reset. When enabled, the timer updates this continually.

Preset Value (.PRE)

This specifies the value which the timer must reach before the controller sets the done bit. When the accumulated value becomes equal to or greater than the preset value, the done bit is set. You can use this bit to control an output device.

Preset and accumulated values for timers range from 0 to +32,767. If a timer preset or accumulated value is a negative number, a runtime error occurs.

Timebase

The timebase determines the duration of each timebase interval. For Fixed and

SLC 5/01 processors, the timebase is set at 0.01 second. For SLC 5/02 and higher processors and MicroLogix 1000 controllers, the timebase is selectable as 0.01

(10 ms) second or 1.0 second.

1–14

Basic Instructions

Timer Accuracy

Note

Timer accuracy refers to the length of time between the moment a timer instruction is enabled and the moment the timed interval is complete. Inaccuracy caused by the program scan can be greater than the timer timebase. You must also consider the time required to energize the output device.

Timing accuracy is

0.01 to

+

0 seconds, with a program scan of up to 2.5 seconds.

The 1-second timer maintains accuracy with a program scan of up to 1.5 seconds. If your programs can exceed 1.5 or 2.5 seconds, repeat the timer instruction rung so that the rung is scanned within these limits.

Timing could be inaccurate if Jump (JMP), Label (LBL), Jump to Subroutine (JSR), or Subroutine (SBR) instructions skip over the rung containing a timer instruction while the timer is timing. If the skip duration is less than 2.5 seconds, no time will be lost; if the skip duration exceeds 2.5 seconds, an undetectable timing error occurs. When using subroutines, a timer must be executed at least every 2.5 seconds

to prevent a timing error.

Addressing Structure

Address bits and words using the format Tf:e.s/b

Explanation

T

Timer file

f

File number. For SLC 500 processors the default is 4. A file number between

9–255 can be used for additional storage. The only valid file number is 4 for

MicroLogix 1000 controllers.

:

Element delimiter

e

Element number

These are 3-word elements. For SLC 500 processors the range is 0–255. For MicroLogix 1000 controllers the range is from 0–39.

.

Word element s Subelement

/ Bit delimiter b Bit

1–15

Addressing Examples

T4:0/15 or T4:0/EN Enable bit

T4:0/14 or T4:0/TT Timer timing bit

T4:0/13 or T4:0/DN Done bit

T4:0.1 or T4:0.PRE Preset value of the timer

T4:0.2 or T4:0.ACC Accumulated value of the timer

T4:0.1/0 or T4:0.PRE/0 Bit 0 of the preset value

T4:0.2/0 or T4:0.ACC/0 Bit 0 of the accumulated value

1–16

Basic Instructions

Timer On–Delay (TON)

✓ ✓ ✓ ✓ ✓ ✓ ✓

TON

TIMER ON DELAY

Timer T4:0

Time Base

Preset

Accum

0.01

120

0

(EN)

(DN)

Output Instruction

Use the TON instruction to turn an output on or off after the timer has been on for a preset time interval. The TON instruction begins to count timebase intervals when rung conditions become true. As long as rung conditions remain true, the timer adjusts its accumulated value (ACC) each evaluation until it reaches the preset value

(PRE). The accumulated value is reset when rung conditions go false, regardless of whether the timer has timed out.

Using Status Bits

This Bit

Timer Done Bit DN (bit 13)

Timer Timing Bit TT (bit 14)

Timer Enable Bit EN (bit 15)

Is Set When

And Remains Set Until One of the Following

accumulated value is equal to or greater than the preset value rung conditions are true and the accumulated value is less than the preset value rung conditions are true rung conditions go false rung conditions go false or when the done bit is set rung conditions go false

When the processor changes from the REM Run or REM Test mode to the REM

Program mode or user power is lost while the instruction is timing but has not reached its preset value, the following occurs:

Timer Enable (EN) bit remains set.

Timer Timing (TT) bit remains set.

Accumulated value (ACC) remains the same.

On returning to the REM Run or REM Test mode, the following can happen:

Condition

If the rung is true:

If the rung is false:

Result

EN bit remains set.

TT bit remains set.

ACC value is reset.

EN bit is reset.

TT bit is reset.

ACC value is reset.

1–17

Timer Off–Delay (TOF)

✓ ✓ ✓ ✓ ✓ ✓ ✓

TOF

TIMER OFF DELAY

Timer

Time Base

Preset

Accum

T4:1

0.01

120

0

(EN)

(DN)

Output Instruction

Use the TOF instruction to turn an output on or off after its rung has been off for a preset time interval. The TOF instruction begins to count timebase intervals when the rung makes a true-to-false transition. As long as rung conditions remain false, the timer increments its accumulated value (ACC) each scan until it reaches the preset value (PRE). The accumulated value is reset when rung conditions go true regardless of whether the timer has timed out.

Using Status Bits

This Bit

Timer Done Bit DN (bit 13)

Timer Timing Bit TT (bit 14)

Is Set When

rung conditions are true rung conditions are false and the accumulated value is less than the preset value rung conditions are true

And Remains Set Until One of the Following

rung conditions go false and the accumulated value is greater than or equal to the preset value rung conditions go true or when the done bit is reset rung conditions go false Timer Enable Bit EN (bit 15)

When processor operation changes from the REM Run or REM Test mode to the

REM Program mode or user power is lost while a timer off-delay instruction is timing but has not reached its preset value, the following occurs:

Timer Enable (EN) bit remains set.

Timer Timing (TT) bit remains set.

Timer Done (DN) bit remains set.

Accumulated value (ACC) remains the same.

1–18

Basic Instructions

On returning to the REM Run or REM Test mode, the following can happen:

Condition

If the rung is true:

If the rung is false:

Result

TT bit is reset.

DN bit remains set.

EN bit is set.

ACC value is reset.

TT bit is reset.

DN bit is reset.

EN bit is reset.

ACC value is set equal to the preset value.

Note

The Reset (RES) instruction cannot be used with the TOF instruction because

RES always clears the status bits as well as the accumulated value. (See page

1–31.)

The TOF times inside an inactive MCR Pair.

Retentive Timer (RTO)

✓ ✓ ✓ ✓ ✓ ✓ ✓

RTO

RETENTIVE TIMER ON

Timer

Time Base

Preset

Accum

T4:2

0.01

120

0

(EN)

(DN)

Output Instruction

Use the RTO instruction to turn an output on or off after its timer has been on for a preset time interval. The RTO instruction is a retentive instruction that begins to count timebase intervals when rung conditions become true.

The RTO instruction retains its accumulated value when any of the following occurs:

Rung conditions become false.

You change processor operation from the REM Run or REM Test mode to the

REM Program mode.

The processor loses power (provided that battery backup is maintained).

A fault occurs.

When you return the processor to the REM Run or REM Test mode and/or rung conditions go true, timing continues from the retained accumulated value. By retaining its accumulated value, retentive timers measure the cumulative period during which rung conditions are true.

1–19

Using Status Bits

Note

This Bit

Timer Done Bit DN (bit 13)

Timer Timing Bit TT (bit 14)

Timer Enable Bit EN (bit 15)

Is Set When

And Remains Set Until One of the Following

accumulated value is equal to or greater than the preset value rung conditions are true and the accumulated value is less than the preset value rung conditions are true the appropriate RES instruction is enabled rung conditions go false or when the done bit is set rung conditions go false

To reset the retentive timer’s accumulated value and status bits after the RTO rung goes false, you must program a reset (RES) instruction with the same address in another rung.

When the processor changes from the REM Run or REM Test mode to the REM

Program or REM Fault mode, or user power is lost while the timer is timing but not yet at the preset value, the following occurs:

Timer Enable (EN) bit remains set.

Timer Timing (TT) bit remains set.

Accumulated value (ACC) remains the same.

On returning to the REM Run or REM Test mode or when power is restored, the following can happen:

Condition

If the rung is true:

If the rung is false:

Result

TT bit remains set.

EN bit remains set.

ACC value remains the same and resumes incrementing.

TT bit is reset.

DN bit remains in its last state.

EN bit is reset.

ACC value remains in its last state.

1–20

Basic Instructions

Using Counters

Counter Data File Elements

Each Counter address is made of a 3-word data file element. Word 0 is the control word, containing the status bits of the instruction. Word 1 is the preset value. Word

2 is the accumulated value.

The control word for counter instructions includes six status bits, as indicated below.

Word 0

Word 1

Word 2

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

CU CD DN OV UN UA Internal Use

Preset Value

Accumulated Value

Addressable Bits

CU = Count up enable

CD = Count down enable

DN = Done bit

OV = Overflow bit

UN = Underflow bit

UA = Update accum. value

(HSC in fixed controller only)

Addressable Words

PRE = Preset

ACC = Accum

Bits labeled “Internal Use” are not addressable.

For information on the MicroLogix 1000 controller high-speed counter instruction,

see chapter 7.

Entering Parameters

Accumulator Value (.ACC)

This is the number of false-to-true transitions that have occurred since the counter was last reset.

1–21

Preset Value (PRE)

Specifies the value which the counter must reach before the controller sets the done bit. When the accumulator value becomes equal to or greater than the preset value, the done status bit is set. You can use this bit to control an output device.

Preset and accumulated values for counters range from –32,768 to +32,767, and are stored as signed integers. Negative values are stored in two’s complement form.

Addressing Structure

Assign counter addresses using the format Cf:e.s/b

C

: f e

/ b

.

s

Explanation

Counter

File number. For SLC 500 processors the default is 5. A file number between 9–255 can be used for additional storage.

The only valid file number is 5 for MicroLogix 1000 controllers.

Element delimiter

Element number

These are 3-word elements. For SLC

500 processors the range is 0–255. For

MicroLogix 1000 controllers the range is from 0–31.

Word element

Subelement

Bit delimiter

Bit

1–22

Basic Instructions

Examples

C5:0/15 or C5:0/CU Count up enable bit

C5:0/14 or C5:0/CD Count down enable bit

C5:0/13 or C5:0/DN Done bit

C5:0/12 or C5:0/OV Overflow bit

C5:0/11 or C5:0/UN Underflow bit

C5:0/10 or C5:0/UA Update accum. bit (HSC in fixed controller only)

C5:0.1 or C5:0PRE Preset value of the counter

C5:0.2 or C5:0.ACC Accumulated value of the counter

C5:0.1/0 or C5:0.PRE/0 Bit of the preset value

C5:0.2/0 or C5:0.ACC/0 Bit 0 of the accumulated value

How Counters Work

The figure below demonstrates how a counter works. The count value must remain in the range of

32768 to

+

32767. If the count value goes above

+

32767 or below

32768, a counter status overflow (OV) or underflow (UN) bit is set.

A counter can be reset to zero using the reset (RES) instruction.

–32,768 0

(CTU)

Count Up

+32,767

Counter Accumulated Value

Count Down

(CTD)

Underflow Overflow

1–23

Count Up (CTU)

✓ ✓ ✓ ✓ ✓ ✓ ✓

CTU

COUNT UP

Counter

Preset

Accum

C5:0

120

0

(CU)

(DN)

Output Instruction

Note

The CTU is an instruction that counts false-to-true rung transitions. Rung transitions can be caused by events occurring in the program (from internal logic or by external field devices) such as parts traveling past a detector or actuating a limit switch.

When rung conditions for a CTU instruction have made a false-to-true transition, the accumulated value is incremented by one count, provided that the rung containing the CTU instruction is evaluated between these transitions. The ability of the counter to detect false–to–true transitions depends on the speed (frequency) of the incoming signal.

The on and off duration of an incoming signal must not be faster than the scan time

2x (assuming a 50% duty cycle).

The accumulated value is retained when the rung conditions again become false.

The accumulated count is retained until cleared by a reset (RES) instruction that has the same address as the counter reset.

Using Status Bits

This Bit

Count Up Overflow Bit OV

(bit 12)

Done Bit DN (bit 13)

Count Up Enable Bit CU

(bit 15)

Is Set When

accumulated value wraps around to –32,768 (from

+32,767) and continues counting up from there

And Remains Set Until One of the

Following

a RES instruction having the same address as the CTU instruction is executed OR the count is decremented less than or equal to

+32,767 with a CTD instruction the accumulated value becomes less than the preset value accumulated value is equal to or greater than the preset value rung conditions are true rung conditions go false OR a RES instruction having the same address as the CTU instruction is enabled

The accumulated value is retained after the CTU instruction goes false, or when power is removed from and then restored to the controller. Also, the on or off status of counter done, overflow, and underflow bits is retentive. The accumulated value and control bits are reset when the appropriate RES instruction is enabled. The CU bits are always set prior to entering the REM Run or REM Test modes.

1–24

Basic Instructions

Count Down (CTD)

✓ ✓ ✓ ✓ ✓ ✓ ✓

CTD

COUNT DOWN

Counter

Preset

Accum

C5:1

120

0

(CD)

(DN)

Output Instruction

The CTD is an instruction that counts false-to-true rung transitions. Rung transitions can be caused by events occurring in the program such as parts traveling past a detector or actuating a limit switch.

When rung conditions for a CTD instruction have made a false-to-true transition, the accumulated value is decremented by one count, provided that the rung containing the CTD instruction is evaluated between these transitions.

The accumulated counts are retained when the rung conditions again become false.

The accumulated count is retained until cleared by a reset (RES) instruction that has the same address as the counter reset.

Using Status Bits

This Bit

Count Down Underflow Bit UN

(bit 11)

Done Bit DN (bit 13)

Count Down Enable Bit CD

(bit 14)

Is Set When

accumulated value wraps around to +32,767 (from

–32,768) and continues counting down from there

And Remains Set Until One of the Following

a RES instruction having the same address as the CTD instruction is enabled. OR the count is incremented greater than or equal to

+32,767 with a CTU instruction the accumulated value becomes less than the preset accumulated value is equal to or greater than the preset value rung conditions are true rung conditions go false OR a RES instruction having the same address as the CTD instruction is enabled

The accumulated value is retained after the CTD instruction goes false, or when power is removed from and then restored to the controller. Also, the on or off status of counter done, overflow, and underflow bits is retentive. The accumulated value and control bits are reset when the appropriate RES instruction is executed. The CD bits are always set prior to entering the REM Run or REM Test modes.

1–25

High-Speed Counter (HSC)

✓ ✓

HSC

HIGH SPEED COUNTER

Counter

Preset

Accum

C5:0

120

0

(CU)

(DN)

The High-Speed Counter is a variation of the CTU counter. The HSC instruction is enabled when the rung logic is true and disabled when the rung logic is false.

Output Instruction

For information on using the high-speed counter instruction, see chapter 7.

Note

Note

The HSC instruction counts transitions that occur at input terminal I:0/0. The HSC

instruction does not count rung transitions. You enable or disable the HSC rung to

enable or disable the counting of transitions occurring at input terminal I:0/0. We recommend placing the HSC instruction in an unconditional rung. Do not place the

XIC instruction with address I:0/0 in series with the HSC instruction because counts will be lost.

The HSC is a special CTU counter for use with 24 VDC SLC fixed and 24 VDC

MicroLogix 1000 controllers. The HSC’s status bits and accumulated values are non-retentive.

This instruction provides high-speed counting for fixed I/O controllers with 24 VDC

inputs. One HSC instruction is allowed per controller. To use the instruction, you

must cut the jumper as shown below. A shielded cable is recommended to reduce noise to the input.

High-Speed Counter Operation

For high-speed counter operation you must do the following:

1.

Turn off power to the fixed controller.

2.

Remove the SLC 500 cover.

3.

Locate and cut jumper wire J2. Do not remove completely but make certain that the ends of the cut jumper wire are not touching each other.

1–26

The High–Speed Counter jumper is located either beneath the battery connector OR to the right of the battery connector.

J2

J2

Basic Instructions

Note

4.

Replace the cover.

Input I:0/0 then operates in the high-speed mode. The address of the high–speed counter enable bit is C5:0/CU. When rung conditions are true, C5:0/CU is set and transitions occurring at input I:0/0 are counted.

To begin high-speed counting, load a preset value into C5:0.PRE and enable the counter rung. To load a preset value, do one of the following:

Change to the REM Run or REM Test mode from another mode.

Power up the processor in the REM Run mode.

Reset the HSC using the RES instruction.

Automatic reloading occurs when the HSC itself sets the DN bit on interrupt.

Each input transition that occurs at input I:0/0 causes the HSC accumulated value to increment. When the accumulated value equals the preset value, the Done bit

(C5:0/DN) is set, the accumulated value is cleared, and the preset value (C5:0.PRE) is loaded into the HSC in preparation for the next high-speed transition at input

I:0/0.

Your ladder program should poll the Done bit (C5:0/DN) to determine the state of the HSC. Once the Done bit has been detected as set, the ladder program should clear bit C5:0/DN (using the unlatch OTU instruction) before the HSC accumulated again reaches the preset value, or the overflow bit (C5:0/OV) will be set.

1–27

The HSC differs from the CTU and CTD counters. The CTU and CTD are software counters. The HSC is a hardware counter and operates asynchronously to the ladder program scan. The HSC accumulated value (C5:0.ACC) is normally updated each time the HSC rung is evaluated in the ladder program. This means that the HSC hardware accumulator value is transferred to the HSC software accumulator. Only use the OTE instruction to transfer this value. The HSC instruction immediately clears bit C5:0/UA following the accumulated update.

Many HSC counts may occur between HSC evaluations, which would make

C5:0.ACC inaccurate when used throughout a ladder program. To allow for an accurate HSC accumulated value, the update accumulator bit (C5:0/UA) causes

C5:0.ACC to be immediately updated to the state of the hardware accumulator when set.

Use the RES instruction to reset the high–speed counter at address C5:0. The HSC instruction clears the status bits, the accumulator, and loads the preset value during:

• power up

• entry into the REM Run mode

• a reset

High-Speed Counter Data Elements

Address C5:0 is the HSC counter 3-word element.

Word 0

Word 1

Word 2

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

CU CD DN OV UN UA Not Used

Preset Value

Accumulator Value

CU = Counter up enable bit

CD = Counter down enable bit

DN = Done bit

OV = Overflow bit

UN = Underflow bit

UA = Update accumulator (HSC only)

1–28

Basic Instructions

Word 0 contains the following status bits of the HSC instruction:

Bit 10 (UA) updates the accumulator word of the HSC to reflect the immediate state of the HSC when true.

Bit 12 (OV) indicates if a HSC overflow has occurred.

Bit 13 (DN) indicates if the HSC preset value has been reached.

Bit 15 (CU) shows the Enable/Disable state of the HSC instruction.

Word 1 contains the preset value that is loaded into the HSC when either the

RES instruction is executed, when the Done bit is set, or when powerup takes place. The valid range is

+

1 to

+

32767.

Word 2 contains the HSC accumulator value. This word is updated each time the HSC instruction is evaluated and when the update accumulator bit is set using an OTE instruction. This accumulator is read only. Any value written to the accumulator is overwritten by the actual high–speed counter on instruction evaluation, reset, or REM Run mode entry.

Application Example

In the following figures, rungs 1, 18, and 31 of the main program file each consist of an XIC instruction addressed to the HSC done bit and a JSR instruction. These rungs poll the status of the HSC done bit. When the Done bit is set at any of these poll points, program execution moves to subroutine file 3, executing the HSC logic.

After the HSC logic is executed, the Done bit is reset by an unlatch instruction, and program execution returns to the main program file.

1–29

Application Example – File 2 (Poll for DN Bit in Main Program)

JSR

JUMP TO SUBROUTINE 3

Rung 1

Rung 2

C5:0

] [

DN

] [ ] [

] [

( )

Rung 17

Rung 18

Rung 19

] [

C5:0

] [

DN

] [

] [

] [

] [

( )

JSR

JUMP TO SUBROUTINE 3

] [ ( )

Rung 30

Rung 31

Rung 32

] [

C5:0

] [

DN

] [

] [

] [

] [

( )

JSR

JUMP TO SUBROUTINE 3

] [

( )

Application Example – File 3 (Execute HSC Logic)

Rung 0

Rung 1

] [

] [ ] [ ] [

( )

( )

Application Logic

Rung 20

Rung 21

RET

RETURN

C5:0

(U)

DN

Unlatch DN Bit

1–30

Basic Instructions

Reset (RES)

(RES)

Output Instruction

Note

✓ ✓ ✓ ✓ ✓ ✓ ✓

Use a RES instruction to reset a timer or counter. When the RES instruction is enabled, it resets the Timer On Delay (TON), Retentive Timer (RTO), Count Up

(CTU), or Count Down (CTD) instruction having the same address as the RES instruction.

Using a RES instruction for a:

Timer

(Do not use a RES instruction with a TOF.)

Counter

Control

The processor resets the:

ACC value to 0

DN bit

TT bit

EN bit

ACC value to 0

OV bit

UN bit

DN bit

CU bit

CD bit

POS value to 0

EN bit

EU bit

DN bit

EM bit

ER bit

UL bit

IN and FD go to last state

If using this instruction to reset the MicroLogix 1000 controller HSC accumulator,

see page 7–22.

When resetting a counter, if the RES instruction is enabled and the counter rung is enabled, the CU or CD bit is reset.

If the counter preset value is negative, the RES instruction sets the accumulated value to zero. This in turn causes the done bit to be set by a count down or count up instruction.

Because the RES instruction resets the accumulated value, and the done, timing, and enabled bits, do not use the RES instruction to reset a timer address used in a TOF instruction. Otherwise, unpredictable machine operation or injury to personnel may occur.

1–31

Basic Instructions in the Paper Drilling Machine

Application Example

This section provides ladder rungs to demonstrate the use of basic instructions. The rungs are part of the paper drilling machine application example described in

appendix H. You will be adding the main program in file 2 and adding a subroutine

to file 6.

Adding File 2

The rungs shown on the following page are referred to as the program’s “start–up” logic. They determine the conditions necessary to start the machine in motion by monitoring the start and stop push buttons. When the start push button is pressed, it enables the conveyor to move and starts spinning the drill bit. When the stop push button is pressed, it disables the conveyor motion and turns off the drill motor.

The start–up logic also checks to make sure that the drill is fully retracted (in the home position) and that the drill bit is not past its useful life (determined elsewhere in the program) before allowing the conveyor to move.

Drill Home

I:1/5

Drill On/Off O:3/1

1–32

Basic Instructions

Rung 2:0

These rungs will start the conveyer in motion when the start button is pressed. However, there are other conditions that must also be met before we start the conveyor. They are: the drill must be in its fully retracted position (home) and the drill bit must not be past its maximum useful life.

These rungs will also stop the conveyor when the stop button is pressed or when the drill life is exceeded.

| START |Drill STOP Machine |

| Button |Home LS Button RUN |

| Latch |

| I:1.0 I:1.0 I:1.0 B3:0 |

|–+––––] [––––––––] [–––––+––––]/[–––––––––––––––––––––––––––––––––––––( )–––––|

| | 6 5 | 7 0 |

| | Machine | |

| | RUN | |

| | Latch | |

| | B3:0 | |

| +––––] [––––––––––––––––+ |

| 0 |

Rung 2:1

| Machine Drill |

| RUN Motor ON |

| Latch |

| B3:0 O:3.0 |

|––––] [––––––––––––––––––––––––––––––––––––––––––––––––+––––––––––––( )–––––+–|

| 0 | 1 | |

| | Conveyor | |

| | Start/Stop | |

| | | |

| | B3:0 O:3.0 | |

| +––[OSR]–––––(L)–––––+ |

| 1 0 |

Rung 2:2

Stop the conveyor if any conditions exist that unlatch the ”Machine RUN Latch” bit.

| Machine | Conveyor |

| RUN | Start/Stop |

| Latch | |

| B3:0 O:3.0 |

|––––]/[–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––(U)–––––|

| 0 0 |

Adding File 6

This subroutine controls the up and down motion of the drill for the paper drilling machine.

Drill Home

I:1/5

Drill On/Off O:3/1

Drill Retract O:3/2

Drill Forward O:3/3

Drill Depth

I:1/4

1–33

1–34

Rung 6:0

This section of ladder logic controls the up/down motion of the drill for the book drilling machine.

When the conveyor positions the book under the drill, the DRILL SEQUENCE START bit is set. This rung uses that bit to begin the drilling operation. Because the bit is set for the entire drilling operation, the OSR is required to be able to turn off the forward signal so the drill must retract.

| Drill |Drill Subr| Drill |

| Sequence | OSR | Forward |

| Start | |

| B3:2 B3:3 O:3.0 |

|––––] [–––––––[OSR]–––––––––––––––––––––––––––––––––––––––––––––––––––(L)–––––|

| 0 0 3 |

Rung 6:1

When the drill has drilled through the book, the body of the drill will actuate the DRILL DEPTH limit switch. When this happens, the DRILL FORWARD signal is turned off and the DRILL RETRACT signal is turned on.

| Drill Drill |

| Depth LS Forward |

| I:1.0 O:3.0 |

|–+––––] [––––––––––––––––+–––––––––––––––––––––––––––––––––––––+––––(U)–––––+–|

| | 4 | | 3 | |

| | 1’st |Drill | | Drill | |

| | Pass |Home LS | | Retract | |

| | S:1 I:1.0 | | O:3.0 | |

| +––––] [––––––––]/[–––––+ +––––(L)–––––+ |

| 15 5 2 |

Rung 6:2

When the drill is retracting (after drilling a hole), the body of the drill will actuate the DRILL HOME limit switch. When this happens the DRILL

RETRACT signal is turned off, the DRILL SEQUENCE START bit is turned off to indicate the drilling process is complete, and the conveyor is restarted.

| Drill |Drill Drill |

| Home LS |Retract Retract |

| I:1.0 O:3.0 O:3.0 |

|––––] [––––––––] [––––––––––––––––––––––––––––––––––+–––––––––––––––(U)–––––+–|

| 5 2 | 2 | |

| | Drill | |

| | Sequence | |

| | Start | |

| | B3:2 | |

| +–––––––––––––––(U)–––––+ |

| | 0 | |

| | Machine |Conveyor | |

| | RUN |Start/Stop | |

| | Latch | | |

| | B3:0 O:3.0 | |

| +––––] [––––––––(L)–––––+ |

| 0 0 |

Comparison Instructions

2

Comparison Instructions

This chapter contains general information about comparison instructions and explains how they function in your application program. Each of the comparison instructions includes information on:

• what the instruction symbol looks like

• how to use the instruction

In addition, the last section contains an application example for a paper drilling machine that shows the comparison instructions in use.

Comparison Instructions

Mnemonic

Instruction

Name

EQU

NEQ

Equal

Not Equal

LES

LEQ

GRT

GEQ

MEQ

LIM

Less Than

Less Than or

Equal

Greater Than

Greater Than or

Equal

Masked

Comparison for

Equal

Limit Test

Test whether two values are equal.

Test whether one value is not equal to a second value.

Test whether one value is less than a second value.

Test whether one value is less than or equal to a second value.

Test whether one value is greater than another.

Test whether one value is greater than or equal to a second value.

Test portions of two values to see whether they are equal. Compares 16-bit data of a source address to

16-bit data at a reference address through a mask.

Test whether one value is within the limit range of two other values.

2–3

2–3

2–3

2–4

2–4

2–4

2–5

2–5

2–1

About the Comparison Instructions

Comparison instructions are used to test pairs of values to condition the logical continuity of a rung. As an example, suppose a LES instruction is presented with two values. If the first value is less than the second, then the comparison instruction is true.

To learn more about the compare instructions, we suggest that you read the

Compare Instructions Overview that follows.

Comparison Instructions Overview

The following general information applies to comparison instructions.

Using Indexed Word Addresses

When using comparison instructions, you have the option of using indexed word addresses for instruction parameters specifying word addresses. Indexed addressing

is discussed in appendix F of this manual.

Using Indirect Word Addresses

You have the option of using indirect word-level and bit-level addresses for instructions specifying word addresses when using an SLC 5/03 OS302,

SLC 5/04 OS401, or SLC 5/05 processors. See appendix F for more information.

2–2

Comparison Instructions

Equal (EQU)

EQU

EQUAL

Source A

Source B

Input Instruction

✓ ✓ ✓ ✓ ✓ ✓ ✓

Use the EQU instruction to test whether two values are equal. If source A and source B are equal, the instruction is logically true. If these values are not equal, the instruction is logically false.

Source A must be an address. Source B can either be a program constant or a address. Negative integers are stored in two’s complementary form.

Not Equal (NEQ)

✓ ✓ ✓ ✓ ✓ ✓ ✓

NEQ

NOT EQUAL

Source A

Source B

Input Instruction

Use the NEQ instruction to test whether two values are not equal. If source A and source B are not equal, the instruction is logically true. If the two values are equal, the instruction is logically false.

Source A must be an address. Source B can be either a program constant or an address. Negative integers are stored in two’s complementary form.

Less Than (LES)

✓ ✓ ✓ ✓ ✓ ✓ ✓

LES

LESS THAN

Source A

Source B

Input Instruction

Use the LES instruction to test whether one value (source A) is less than another

(source B). If source A is less than the value at source B, the instruction is logically true. If the value at source A is greater than or equal to the value at source B, the instruction is logically false.

Source A must be an address. Source B can either be a program constant or an address. Negative integers are stored in two’s complementary form.

2–3

Less Than or Equal (LEQ)

✓ ✓ ✓ ✓ ✓ ✓ ✓

LEQ

LESS THAN OR EQUAL

Source A

Source B

Input Instruction

Use the LEQ instruction to test whether one value (source A) is less than or equal to another (source B). If the value at source A is less than or equal to the value at source B, the instruction is logically true. If the value at source A is greater than the value at source B, the instruction is logically false.

Source A must be an address. Source B can either be a program constant or an address. Negative integers are stored in two’s complementary form.

Greater Than (GRT)

✓ ✓ ✓ ✓ ✓ ✓ ✓

GRT

GREATER THAN

Source A

Source B

Input Instruction

Use the GRT instruction to test whether one value (source A) is greater than another

(source B). If the value at source A is greater than the value at source B, the instruction is logically true. If the value at source A is less than or equal to the value at source B, the instruction is logically false.

Source A must be an address. Source B can either be a program constant or an address. Negative integers are stored in two’s complementary form.

Greater Than or Equal (GEQ)

GEQ

GRTR THAN OR EQUAL

Source A

Source B

Input Instruction

✓ ✓ ✓ ✓ ✓ ✓ ✓

Use the GEQ instruction to test whether one value (source A) is greater than or equal to another (source B). If the value at source A is greater than or equal to the value at source B, the instruction is logically true. If the value at source A is less than the value at source B, the instruction is logically false.

Source A must be an address. Source B can either be a program constant or an address. Negative integers are stored in two’s complementary form.

2–4

Comparison Instructions

Masked Comparison for

Equal (MEQ)

✓ ✓ ✓ ✓ ✓ ✓ ✓

MEQ

MASKED EQUAL

Source

Mask

Compare

Input Instruction

Use the MEQ instruction to compare data at a source address with data at a compare address. Use of this instruction allows portions of the data to be masked by a separate word.

Entering Parameters

Source is the address of the value you want to compare.

Mask is the address of the mask through which the instruction moves data. The mask can be a hexadecimal value.

Compare is an integer value or the address of the reference.

If the 16 bits of data at the source address are equal to the 16 bits of data at the compare address (less masked bits), the instruction is true. The instruction becomes false as soon as it detects a mismatch. Bits in the mask word mask data when reset; they pass data when set.

Limit Test (LIM)

✓ ✓ ✓ ✓ ✓

LIM

LIMIT TEST

Low Lim

Test

High Lim

Use the LIM instruction to test for values within or outside a specified range, depending on how you set the limits.

Input Instruction

Entering Parameters

The Low Limit, Test, and High Limit values can be word addresses or constants, restricted to the following combinations:

If the Test parameter is a program constant, both the Low Limit and High Limit parameters must be word addresses.

2–5

If the Test parameter is a word address, the Low Limit and High Limit parameters can be either a program constant or a word address.

True/False Status of the Instruction

If the Low Limit has a value equal to or less than the High Limit, the instruction is true when the Test value is between the limits or is equal to either limit. If the Test value is outside the limits, the instruction is false, as shown below.

–32,768

False

Low Limit

True False

+ 32,767

High Limit

Example, low limit less than high limit:

Low

Limit

High

Limit

Instruction is True when Test value is

5 8 5 through 8

Instruction is False when Test value is

–32,768 through 4 and 9 through 32,767

If the Low Limit has a value greater than the High Limit, the instruction is false when the Test value is between the limits. If the Test value is equal to either limit or outside the limits, the instruction is true, as shown below.

–32,768

True

High Limit

False True

+ 32,767

Low Limit

Example, low limit greater than high limit:

Low

Limit

8

High

Limit

5

Instruction is True when Test value is

–32,768 through 5 and 8 through 32,767

Instruction is False when Test value is

6 and 7

2–6

Comparison Instructions

Comparison Instructions in the Paper Drilling Machine

Application Example

This section provides ladder rungs to demonstrate the use of comparison instructions. The rungs are part of the paper drilling machine application example

described in appendix H.

Beginning a Subroutine in File 7

This section of ladder keeps track of the total inches of paper the current drill bit has drilled through. As the current bit wears out, a light illuminates on the operator panel, as shown below, to warn the operator to change the drill bit.

OPERATOR PANEL

Start I:1/6 Stop I:1/7

Thumbwheel for

Thickness in 1/4”

Change Tool Soon

O:3/4

Tool Change Reset

Change Tool Now

O:3/6

5 Hole

3 Hole 7 Hole

I:1/11–I:1/14

(Keyswitch)

I:1/8

I:1/9–I:1/10

2–7

2–8

Rung 7:0

This rung examines the number of 1/4” thousands that have accumulated over the life of the current drill bit. If the bit has drilled between 100,000–101,999

1/4” increments of paper, then the ”change drill” light will illuminate steady.

When the value is between 102,000–103,999, then the ”change drill” light will flash at a 1.28 second rate. When the value reaches 105,000, then the ”change drill” light will flash, and the ”change drill now” light will illuminate.

| 1/4” 100,000 |

| Thousands 1/4” |

| increments |

| have |

| occurred |

| +GEQ–––––––––––––––+ B3:1 |

|–––––––+–+GRTR THAN OR EQUAL+–––––––––––––––––––––––––––––––––––––––( )–––––+–|

| | |Source A N7:11| 0 | |

| | | 0| | |

| | |Source B 100| | |

| | | | | |

| | +––––––––––––––––––+ | |

| | 1/4” 102,000 | |

| | Thousands 1/4” | |

| | increments | |

| | have | |

| | occurred | |

| | +GEQ–––––––––––––––+ B3:1 | |

| +–+GRTR THAN OR EQUAL+–––––––––––––––––––––––––––––––––––––––( )–––––+ |

| | |Source A N7:11| 1 | |

| | | 0| | |

| | |Source B 102| | |

| | | | | |

| | +––––––––––––––––––+ | |

| | 1/4” change | |

| | Thousands drill bit | |

| | NOW | |

| | +GEQ–––––––––––––––+ O:3.0 | |

| +–+GRTR THAN OR EQUAL+–––––––––––––––––––––––––––––––––––––––( )–––––+ |

| | |Source A N7:11| 6 | |

| | | 0| | |

| | |Source B 105| | |

| | | | | |

| | +––––––––––––––––––+ | |

| | 100,000 |102,000 change | |

| | 1/4” |1/4” drill | |

| | increments|increments bit | |

| | have |have soon | |

| | occurred |occurred | |

| | B3:1 B3:1 O:3.0 | |

| +–+–––––––––––––––––––––––] [––––––––]/[––––––––––––––––+––––( )–––––+ |

| | 0 1 | 4 |

| | 100,000 |102,000 |1.28 | |

| | 1/4” |1/4” |second | |

| | increments|increments|free | |

| | have |have |running | |

| | occurred |occurred |clock bit | |

| | B3:1 B3:1 S:4 | |

| +–––––––––––––––––––––––] [––––––––] [––––––––] [–––––+ |

| 0 1 7 |

Math Instructions

3

Math Instructions

This chapter contains general information about math instructions and explains how they function in your logic program. Each of the math instructions includes information on:

• what the instruction symbol looks like

• how to use the instruction

In addition, the last section contains an application example for a paper drilling machine that shows the math instructions in use.

Math Instructions

Mnemonic

Instruction

Name

ADD

Add

SUB

MUL

Subtract

Multiply

DIV

DDV

Divide

Double Divide

CLR

SQR

SCP

Clear

Square Root

Scale with

Parameters

Adds source A to source B and stores the result in the destination.

Subtracts source B from source A and stores the result in the destination.

Multiplies source A by source B and stores the result in the destination.

Divides source A by source B and stores the result in the destination and the math register.

Divides the contents of the math register by the source and stores the result in the destination and the math register.

Sets all bits of a word to zero.

3–6

3–6

3–10

3–11

3–12

3–13

Calculates the square root of the source and places the integer result in the destination.

Produces a scaled output value that has a linear relationship between the input and scaled values.

3–13

3–14

continued on next page

3–1

3–2

Mnemonic

Instruction

Name

SCL

ABS

CPT

SWP

ASN

ACS

ATN

COS

LN

LOG

SIN

TAN

XPY

Scale Data

Absolute

Compute

Swap

Arc Sine

Arc Cosine

Multiplies the source by a specified rate, adds to an offset value, and stores the result in the destination.

Calculates the absolute value of the source and places the result in the destination.

Evaluates an expression and stores the result in the destination.

Swaps the low and high bytes of a specified number of words in a bit, integer, ASCII, or string file.

Takes the arc sine of a number and stores the result

(in radians) in the destination.

Takes the arc cosine of a number and stores the result (in radians) in the destination.

Arc Tangent

Cosine

Takes the arc tangent of a number and stores the result (in radians) in the destination.

Takes the cosine of a number and stores the result in the destination.

Natural Log Takes the natural log of the value in the source and stores it in the destination.

Log to the Base 10 Takes the log base 10 of the value in the source and stores the result in the destination.

Sine Takes the sine of a number and stores the result in the destination.

Tangent Takes the tangent of a number and stores the result in the destination.

X to the Power of Y Raise a value to a power and stores the result in the destination.

3–17

3–24

3–25

3–27

3–28

3–28

3–29

3–29

3–30

3–30

3–31

3–31

3–32

Math Instructions

About the Math Instructions

The majority of the instructions take two input values, perform the specified arithmetic function, and output the result to an assigned memory location.

For example, both the ADD and SUB instructions take a pair of input values, add or subtract them, and place the result in the specified destination. If the result of the operation exceeds the allowable value, an overflow or underflow bit is set.

To learn more about the math instructions, we suggest that you read the Math

Instructions Overview that follows.

Math Instructions Overview

The following general information applies to math instructions.

Entering Parameters

Source is the address(es) of the value(s) on which the mathematical, logical, or move operation is to be performed. This can be word addresses or program constants. An instruction that has two source operands does not accept program constants in both operands.

Destination is the address of the result of the operation. Signed integers are stored in two’s complementary form and apply to both source and destination parameters.

When using either an SLC 5/03 (OS301 and higher), SLC 5/04, or SLC 5/05 processor; floating point and string values (specified at the word level) are

supported. Refer to appendix E for additional valid addressing types.

Using Indexed Word Addresses

You have the option of using indexed word addresses for instruction parameters specifying word addresses (except for fixed and SLC 5/01 processors). Indexed

addressing is discussed in appendix F.

3–3

Using Indirect Word Addresses

You have the option of using indirect word-level and bit-level addresses for instructions specifying word addresses when using an SLC 5/03 (OS302), SLC 5/04

(OS401), or SLC 5/05 processors. See appendix C for more information.

Updates to Arithmetic Status Bits

The arithmetic status bits are found in Word 0, bits 0–3 in the controller status file.

After an instruction is executed, the arithmetic status bits in the status file are updated:

S:0/0

S:0/1

S:0/2

S:0/3

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Controller:

sets if carry is generated; otherwise cleared.

indicates that the actual result of a math instruction does not fit in the designated destination.

indicates a 0 value after a math, move, or logic instruction.

indicates a negative (less than 0) value after a math, move, or logic instruction.

Overflow Trap Bit, S:5/0

Minor error bit (S:5/0) is set upon detection of a mathematical overflow or division by zero. If this bit is set upon execution of an END statement or a Temporary End

(TND) instruction, or an I/O Refresh (REF), the recoverable major error code 0020 is declared.

In applications where a math overflow or divide by zero occurs, you can avoid a

CPU fault by using an unlatch (OTU) instruction with address S:5/0 in your program. The rung must be between the overflow point and the END, TND, or REF statement.

3–4

Math Instructions

Changes to the Math Register, S:13 and S:14

Status word S:13 contains the least significant word of the 32-bit values of the MUL and DDV instructions. It contains the remainder for DIV and DDV instructions. It also contains the first four BCD digits for the Convert from BCD (FRD) and

Convert to BCD (TOD) instructions.

Status word S:14 contains the most significant word of the 32-bit values of the MUL and DDV instructions. It contains the unrounded quotient for DIV and DDV instructions. It also contains the most significant digit (digit 5) for TOD and FRD instructions.

Using Floating Point Data File (F8:)

This file type is valid for SLC 5/03 (OS301 and higher), SLC 5/04, and SLC 5/05 processors. These are 2-word elements and addressable only at the element level.

Assign floating point addresses as follows:

Format

Ff:e

Explanation

F

Floating Point file

f

File number. Number 8 is the default file. A file number between 9- 255 can be used if additional storage is required.

:

Element delimiter

e

Element number

Ranges from 0- 255. These are 2-word elements.

Non-extended 32-bit numbers

Examples:

F8:2

F10:36

Element 2, floating point file 8

Element 36, floating point file 10 (file 10 designated as a floating point file by the user)

3–5

Add (ADD)

✓ ✓ ✓ ✓ ✓ ✓ ✓

ADD

ADD

Source A

Source B

Dest

Output Instruction

Use the ADD instruction to add one value (source A) to another value (source B) and place the result in the destination.

Updates to Arithmetic Status Bits

With this Bit: The Processor:

Carry (C)

Overflow (V)

Zero (Z) sets if carry is generated; otherwise resets (integer). For floating point, it is cleared.

sets if overflow is detected at destination; otherwise resets. On overflow, the minor error flag is also set. For floating point, the overflow value is placed in the destination. For an integer, the value –32,768 or 32,767 is placed in the destination. Exception: If you are using an SLC 5/02 or higher processor or a MicroLogix 1000 controller and have S:2/14 (math overflow selection bit) set, then the unsigned, truncated overflow remains in the destination.

sets if result is zero; otherwise resets.

Sign (S) sets if result is negative; otherwise resets.

Subtract (SUB)

SUB

SUBTRACT

Source A

Source B

Dest

✓ ✓

Use the SUB instruction to subtract one value (source B) from another (source A) and place the result in the destination.

✓ ✓ ✓ ✓ ✓

Output Instruction

Updates to Arithmetic Status Bits

With this Bit: The Processor:

Carry (C) sets if borrow is generated; otherwise resets (integer). For floating point it is cleared.

Overflow (V)

Zero (Z)

Sign (S) sets if underflow; otherwise reset. On underflow, the minor error flag is also set. For floating point, the overflow value is placed in the destination. For an integer, the value –32,768 or 32,767 is placed in the destination.

Exception: If you are using an SLC 5/02 or higher processor or a MicroLogix 1000 controller and have S:2/14

(math overflow selection bit) set, then the unsigned, truncated overflow remains in the destination.

sets if result is zero; otherwise resets.

sets if result is negative; otherwise resets.

3–6

Math Instructions

32-Bit Addition and Subtraction

✓ ✓ ✓ ✓ ✓

You have the option of performing 16-bit or 32-bit signed integer addition and subtraction. This is facilitated by status file bit S:2/14 (math overflow selection bit).

Math Overflow Selection Bit S:2/14

Note

Note

Note

Set this bit when you intend to use 32-bit addition and subtraction. When S:2/14 is set, and the result of an ADD, SUB, MUL, DIV, or NEG instruction cannot be represented in the destination address (due to math underflow or overflow):

The overflow bit S:0/1 is set.

The overflow trap bit S:5/0 is set.

The destination address contains the unsigned, truncated, least significant 16 bits of the result.

For MUL, DIV, integer, and all floating point instructions with an integer destination, when S:2/14 is set, the state change takes effect immediately.

When S:2/14 is reset (default condition), and the result of an ADD, SUB, MUL,

DIV, or NEG instruction cannot be represented in the destination address (due to math underflow or overflow):

The overflow bit S:0/1 is set.

The overflow trap bit S:5/0 is set.

The destination address contains 32767 if the result is positive or –32768 if the result is negative.

Additionally, the SLC 5/03 and higher processors only assert the state of bit S:2/14 at the end of scan for the ADD, SUB, and NEG instructions.

Note that the status of bit S:2/14 has no effect on the DDV instruction. Also, it has no effect on the math register content when using MUL and DIV instructions.

The SLC 5/03 and higher processors only interrogate this bit upon going to the Run mode and end-of-scan. Use the Data Monitor function to make this selection prior to entering the Run mode.

3–7

Example of 32-bit Addition

The following example shows how a 16-bit signed integer is added to a 32-bit signed integer. Remember that S:2/14 must be set for 32-bit addition.

Note that the value of the most significant 16 bits (B3:3) of the 32-bit number is increased by 1 if the carry bit S:0/0 is set and it is decreased by 1 if the number being added (B3:1) is negative.

To avoid a major error from occurring at the end of the scan, you must unlatch overflow trap bit S:5/0 as shown.

3–8

Math Instructions

Add Operation

Add 16–bit value B3:1 to 32–bit value B3:3 B3:2

Binary Hex Decimal

Addend

Addend

B3:3 B3:2

B3:1

Sum

B3:3 B3:2

0000 0000 0000 0011 0001 1001 0100 0000

0101 0101 1010 1000

0003 1940

55A8

0000 0000 0000 0011 0110 1110 1110 1000 0003 6EE8

The programming device displays 16-bit decimal values only. The decimal value of a 32-bit integer is derived from the displayed binary or hex value. For example, 0003 1940 Hex is 16

4 x3 + 16

3 x1 + 16

2 x9 + 16

1 x4 + 16

0 x0 = 203,072.

203,072

21,928

225,000

B3

] [

0

B3

[OSR]

1

S:0

] [

0

B3

] [

31

ADD

ADD

Source A B3:1

0101010110101000

Source B B3:2

0001100101000000

Dest B3:2

0001100101000000

ADD

ADD

Source A 1

Source B B3:3

0000000000000011

Dest B3:3

0000000000000011

SUB

SUBTRACT

Source A B3:3

0000000000000011

Source B 1

Dest B3:3

0000000000000011

S:5

(U)

0

END

When rung goes true for a single scan, B3:1 is added to B3:2. The result is placed in B3:2.

If a carry is generated (S:0/0 set), 1 is added to B3:3.

If B3:1 is negative (B3/31 set), 1 is subtracted from

B3:3.

Overflow trap bit S:5/0 is unlatched to prevent a major error from occurring at the end of the scan.

Application Note: You can use the rung above with a DDV instruction and a counter to find the average value of B3:1.

3–9

Multiply (MUL)

✓ ✓ ✓ ✓ ✓ ✓ ✓

MUL

MULTIPLY

Source A

Source B

Dest

Output Instruction

Use the MUL instruction to multiply one value (source A) by another (source B) and place the result in the destination.

Updates to Arithmetic Status Bits

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Processor:

always resets.

sets if overflow is detected at destination; otherwise resets. On overflow, the minor error flag is also set. The value –32,768 or 32,767 is placed in the destination. Exception: If you are using an SLC 5/02 or higher processor or a MicroLogix 1000 controller and have S:2/14 (math overflow selection bit) set, then the unsigned, truncated overflow remains in the destination. For floating point destinations, the overflow result remains in the destination.

sets if result is zero; otherwise resets.

sets if result is negative; otherwise resets.

Changes to the Math Register, S:13 and S:14

Integer – Contains the 32-bit signed integer result of the multiply operation. This result is valid at overflow.

Floating Point – The math register does not change.

3–10

Math Instructions

Divide (DIV)

✓ ✓ ✓ ✓ ✓ ✓ ✓

DIV

DIVIDE

Source A

Source B

Dest

Use the DIV instruction to divide one value (source A) by another (source B). The rounded quotient is then placed in the destination. If the remainder is 0.5 or greater, round up occurs in the destination. The unrounded quotient is stored in the most significant word of the math register. The remainder is placed in the least significant word of the math register.

Output Instruction

Updates to Arithmetic Status Bits

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Processor:

always resets.

sets if division by zero or overflow is detected; otherwise resets. On overflow, the minor error flag is also set. The value 32,767 is placed in the destination. Exception: If you are using an SLC1 5/02 or higher processor or a MicroLogix 1000 controller and have S:2/14 (math overflow selection bit) set, then the unsigned, truncated overflow remains in the destination. For floating point destinations, the overflow result remains in the destination.

sets if result is zero; otherwise resets; undefined if overflow is set.

sets if result is negative; otherwise resets; undefined if overflow is set.

Changes to the Math Register, S:13 and S:14

Integer – The unrounded quotient is placed in the most significant word, the remainder is placed in the least significant word.

Floating Point – The math register does not change.

Example

The remainder of 11/2 is 0.5, so the quotient is rounded up to 6 and is stored in the destination. The unrounded quotient, which is 5, is stored in S:14 and the remainder, which is 1, is stored at S:13.

DIV

DIVIDE

Source A

Source B

Dest

N7:0

11

N7:1

2

N7:2

6

where: N7:0 = 11

N7:1 = 2

N7:2 = 6 result: S:14 = 5

S:13 = 1

3–11

Double Divide (DDV)

DDV

DOUBLE DIVIDE

Source

Dest

✓ ✓ ✓ ✓ ✓ ✓ ✓

The 32-bit content of the math register is divided by the 16-bit source value and the rounded quotient is placed in the destination. If the remainder is 0.5 or greater, the destination is rounded up.

Output Instruction

This instruction typically follows a MUL instruction that creates a 32-bit result.

Updates to Arithmetic Status Bits

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Processor:

always resets.

sets if division by zero or if result is greater than 32,767 or less than

–32,768; otherwise resets. On overflow, the minor error flag is also set.

The value 32,767 is placed in the destination.

sets if result is zero; otherwise resets.

sets if result is negative; otherwise resets; undefined if overflow is set.

Changes to the Math Register, S:13 and S:14

Initially contains the dividend of the DDV operation. Upon instruction execution, the unrounded quotient is placed in the most significant word of the math register.

The remainder is placed in the least significant word of the math register.

3–12

Math Instructions

Clear (CLR)

✓ ✓ ✓ ✓ ✓ ✓ ✓

CLR

CLEAR

Dest

Output Instruction

Use the CLR instruction to set the destination value of a word to zero.

Updates to Arithmetic Status Bits

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Processor:

always resets.

always resets.

always sets.

always resets.

Square Root (SQR)

SQR

SQUARE ROOT

Source

Dest

✓ ✓ ✓ ✓ ✓

When this instruction is evaluated as true, the square root of the absolute value of the source is calculated and the rounded result is placed in the destination.

Output Instruction

The instruction calculates the square root of a negative number without overflow or faults. In applications where the source value may be negative, use a comparison instruction to evaluate the source value to determine if the destination may be invalid.

Updates to Arithmetic Status Bits

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Processor:

is reserved (integer). For floating point, it is always cleared.

always resets.

sets when destination value is zero.

always resets.

3–13

Scale with Parameters (SCP)

SCP

SCALE W/PARAMETERS

Input

Input Min.

Input Max.

Scaled Min.

Scaled Max.

Scaled Output

Output Instruction

Note

✓ ✓ ✓

Use the SCP instruction to produce a scaled output value that has a linear relationship between the input and scaled values. This instruction supports integer and floating point values. Use this instruction with SLC 5/03 (OS302), SLC 5/04

(OS401), and SLC 5/05 processors.

Use the following formula to convert analog input data to engineering units: y = mx + b

Where:

y = scaled output

m = slope (scaled max. – scaled min.) / (input max. – input min.)

x = input value

b = offset (y intercept) = scaled min – (input min. slope)

The Input Minimum, Input Maximum, Scaled Minimum, and Scaled Maximum are used to determine the slope and offset values. The input value can go outside of the specified input limits and no ordering is required. For example, the scaled output value is not necessarily clamped between the scaled minimum and scaled maximum values.

Entering Parameters

Enter the following parameters when programming this instruction:

Input value can be a word address or an address of floating point data elements.

Input Minimum and Input Maximum values determine the range of data that appears in the Input Value parameter. The value can be a word address, an integer constant, floating point data element, or a floating point constant.

Scaled Minimum and Scaled Maximum values determine the range of data that appears in the Scaled Output parameter. The value can be a word address, an integer constant, floating point data element, or a floating point constant.

Scaled Output value can be a word address or an address of floating point data elements.

3–14

Math Instructions

Updates to Arithmetic Status Bits

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Processor:

always resets.

sets if overflow generated or an unsupported input is detected; otherwise resets.

sets when destination value is zero; otherwise resets.

sets if the destination value is negative; otherwise resets.

Application Examples

Example 1

In the first example, an analog I/O combination module (1746–NIO4I) is in slot 1 of the chassis. A pressure transducer is connected to input 0 and we want to read the value in engineering units. The pressure transducer measures pressures from

0–1000 psi and provides a 0–10V signal to the analog module. For a 0–10V signal, the analog module provides a range between 0–32,767. The following program rung places a number between 0–1000 into N7:20 based on the input signal coming from the pressure transducer into the analog module.

Rung 2:0

| +SCP––––––––––––––––––––+ |

|––––––––––––––––––––––––––––––––––––––––––––––––––––+SCALE W/PARAMETERS +–|

| |Input I:1.0| |

| | 0| |

| |Input Min. 0| |

| | | |

| |Input Max. 32767| |

| | | |

| |Scaled Min. 0| |

| | | |

| |Scaled Max. 1000| |

| | | |

| |Scaled Output N7:20| |

| | 0| |

| +–––––––––––––––––––––––+ |

3–15

Example 2

In the second example, an analog I/O combination module (1746-NIO4I) is in slot 1 of the chassis. We want to control the proportional valve connected to output 0.

The valve takes a 4–20mA signal to control how far it opens (0–100%). (Assume that additional logic is present in the program that calculates how far to open the valve in percent and places a number between 0–100 into N7:21.) The analog module provides a 4–20mA output signal for a number between 6242–31,208. The following program rung directs an analog output to provide a 4–20 mA signal to the proportional valve (N7:21), based on a number between 0–100.

Rung 2:1

| +SCP––––––––––––––––––––+ |

|––––––––––––––––––––––––––––––––––––––––––––––––––––+SCALE W/PARAMETERS +–|

| |Input N7:21| |

| | 0| |

| |Input Min. 0| |

| | | |

| |Input Max. 100| |

| | | |

| |Scaled Min. 6242| |

| | | |

| |Scaled Max. 31208| |

| | | |

| |Scaled Output O:1.0| |

| | 0| |

| +–––––––––––––––––––––––+ |

3–16

Math Instructions

Scale Data (SCL)

✓ ✓ ✓ ✓ ✓

When this instruction is true, the value at the source address is multiplied by the rate value. The rounded result is added to the offset value and placed in the destination.

SCL

SCALE

Source

Rate [/10000]

Offset

Dest

Output Instruction

Example

SCL

SCALE

Source N7:0

100

Rate [/10000] 25000

Offset

Dest

127

N7:1

377

The source 100 is multiplied by

25000 and divided by 10000 and added to 127. The result 377 is placed in the destination.

Note

Anytime an underflow or overflow occurs in the destination file, minor error bit

S:5/0 must be reset by the program. This must occur before the end of the current scan to prevent major error code 0020 from being declared. This instruction can overflow before the offset is added.

Note that the term rate is sometimes referred to as slope. The rate function is limited to the range –3.2768 to 3.2767. For example, –32768/10000 to

+

32767/10000.

Entering Parameters

The value for the following parameters is between –32,768 to 32,767.

Source can be either a constant or a word address.

Rate (or slope) is the positive or negative value you enter divided by 10,000. It can be either a constant or a word address.

Offset can be either a constant or a word address.

3–17

Updates to Arithmetic Status Bits

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Processor:

is reserved.

sets if an overflow is detected; otherwise resets. On overflow, minor error bit S:5/0 is also set and the value –32,768 or 32,767 is placed in the destination. The presence of an overflow is checked before and after the offset value is applied.

➀ sets when destination value is zero.

sets if the destination value is negative; otherwise resets.

If the result of the Source times the Rate, divided by 10000, is greater than 32767, the SCL instruction overflows, causing error 0020 (Minor Error Bit), and places 32767 in the Destination. This occurs regardless of the current offset.

Application Example 1 – Converting 4mA–20mA Analog Input Signal to PID

Process Variable

16,383

(Scaled Max.)

Scaled Value

0

(Scaled Min.)

3,277

(Input Min.)

Input Value

16,384

(Input Max.)

3–18

Math Instructions

Calculating the Linear Relationship

Use the following equations to express the linear relationship between the input value and the resulting scaled value:

Scaled value = (input value x rate)

+

offset

Rate = (scaled max. – scaled min.) / (input max. – input min.)

(16,383

0) / (16,384 – 3277)

=

1.249 (or 12,490/10000)

Offset = scaled min. – (input min. x rate)

0 – (3277

×

1.249)

=

–4093

Application Example 2 – Scaling an Analog Input to Control an Analog

Output

32,764 10V

(Scaled Max.)

Scaled Value

0 0V

(Scaled Min.)

3,277 4mA

(Input Min.)

Input Value

16,384 20mA

(Input Max.)

3–19

Calculating the Linear Relationship

Use the following equations to calculate the scaled units:

Scaled value = (input value x rate)

+

offset

Rate = (scaled max. – scaled min.) / (input max. – input min.)

(32,764 – 0) / (16,384 – 3277)

=

2.4997 (or 24,997/10000)

Offset = scaled min. – (input min. x rate)

0

(3277

×

2.4997)

=

– 8192

The above offset and rate values are correct for the SCL instruction. However, if the input exceeds 13,107, the instruction overflows. For example:

17mA = 13,926

×

2.4997 = 34,810 (actual overflow)

34,810 – 8192 = 26,618

Notice that an overflow occurred even though the final value was correct. This happens because the overflow condition occurred during the rate calculation.

To avoid an overflow, we recommend shifting the linear relationship along the input value axis and reduce the values.

The following graph shows the shifted linear relationship. The input minimum value of 3,277 is subtracted from the input maximum value of 16,384, resulting in the value of 13,107.

3–20

32,764 10V

(Scaled Max.)

Scaled Value

0 0V

(Scaled Min.)

0 4mA

(Shifted Input Min.)

13,107 20mA

(Shifted Input Max.)

Input Value

Calculating the Shifted Linear Relationship

Use the following equations to calculate the scaled units:

Scaled value = (input value x rate)

+

offset

Rate = (scaled max. – scaled min.) / (input max. – input min.)

(32,764

0) / (13,107

0)

=

2.4997 (or 24,997/10000)

Offset = scaled min. – (input min. x rate)

0 – (0

×

2.4997)

=

0

Math Instructions

3–21

3–22

In this example, the SCL instruction is entered in the ladder logic program as follows:

Apply the Shift

SUB

SUBTRACT

Source A

Source B

Dest

I:1.0

3277

N7:0

Analog Input

Scale Shifted Analog Value

SCL

SCALE

Source N7:0

Rate [/10000] 24997

Offset

Dest

0

O:2.0

Analog Output

Math Instructions

Application Example 3 – Convert Voltage Input to Percent (MicroLogix)

The following example takes a 0V to 10V analog input from a MicroLogix 1000 analog controller and scales the raw input data to a value between 0 and 100%. The input value range is 0V to 10V which corresponds to 0 to 31,207 counts. The scaled value range is 0 to 100%.

100

(Scaled Max.)

Scaled Value

(percent)

0

(Scaled Min.)

0 0V

(Input Min.)

31,207 10V

(Input Max.)

Input Value

Calculating the Linear Relationship

Use the following equations to calculate the scaled units:

Scaled value = (input value x rate)

+

offset

Rate = (scaled max. – scaled min.) / (input max. – input min.)

= (100 – 0) / (31,207 –

0

)

= .00320 (or 320/10000)

Offset = scaled min. – (input min. x rate)

= 0

(0

×

.00320)

=

0

3–23

Absolute (ABS)

✓ ✓ ✓

ABS

ABSOLUTE VALUE

Source

Dest

Output Instruction

Use the ABS instruction to calculate the absolute value of the Source and place the result in the Destination. This instruction supports integer and floating point values.

Use this instruction with SLC 5/03 (OS302), SLC 5/04 (OS401), and SLC 5/05 processors.

Entering Parameters

Enter the following parameters when programming this instruction:

Source can be a word address, an integer constant, floating point data element, or a floating point constant.

Destination can only be a word address or a floating point data element.

Updates to Arithmetic Status Bits

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Processor:

always resets.

always resets with a floating point value; sets if the input is –32,768

(integer value).

sets when destination value is zero; otherwise resets.

always resets.

3–24

Math Instructions

Compute (CPT)

CPT

COMPUTE

Dest

Expression

Output Instruction

Note

✓ ✓ ✓

The CPT instruction performs copy, arithmetic, logical, and conversion operations.

You define the operation in the Expression and the result is written in the

Destination. The CPT uses functions to operate on one or more values in the

Expression to perform operations such as:

• converting from one number format to another

• manipulating numbers

• performing trigonometric functions

Use this instruction with SLC 5/03 (OS302), SLC 5/04 (OS401), and SLC 5/05 processors.

Instructions that can be used in the Expression include:

+, –, *, | (DIV), SQR, – (NEG), NOT, XOR, OR, AND, TOD, FRD, LN,

TAN, ABS, DEG, RAD, SIN, COS, ATN, ASN, ACS, LOG, and ** (XPY).

The execution time of a CPT instruction is longer than a single arithmetic operation and uses more instruction words.

Entering Parameters

Enter the following parameters when programming this instruction:

Destination can be a word address or the address of a floating-point data element.

Expression is zero or more lines, with up to 28 characters per line, up to 255 characters.

Updates to Arithmetic Status Bits

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Processor:

sets based on the result of the last instruction in the Expression.

sets any time an overflow occurs during the evaluation of the Expression.

sets based on the result of the last instruction in the Expression.

sets based on the result of the last instruction in the Expression.

The above bits are cleared at the start of the CPT instruction. See S:34/2 for special handling of the math status bits when using floating point.

3–25

Application Example

This application example uses Pythagorean’s theorem to find the length of the long leg of a triangle, knowing the two other leg lengths. Use the following equation: c

2

= a

2

+ b

2 where c = (a

2

+ b

2

)

N10:0 =

Ǹ

(N7:1)

2

+ (N7:2)

2

Rung 2:0 uses standard math instructions to implement Pythagorean’s theorem.

Rung 2:1 uses the CPT instruction to obtain the same calculation.

| Rung 2:0 +XPY–––––––––––––––+ |

|–––––––––––––––––––––––––––––––––––––––––––––––––––––+–+X TO POWER OF Y +–+–|

| | |Source A N7:1| | |

| | | 3| | |

| | |Source B 2| | |

| | | | | |

| | |Dest N7:3| | |

| | | 0| | |

| | +––––––––––––––––––+ | |

| | +XPY–––––––––––––––+ | |

| +–+X TO POWER OF Y +–+ |

| | |Source A N7:2| | |

| | | 4| | |

| | |Source B 2| | |

| | | | | |

| | |Dest N7:4| | |

| | | 0| | |

| | +––––––––––––––––––+ | |

| | +ADD–––––––––––––––+ | |

| +–+ADD +–+ |

| | |Source A N7:3| | |

| | | 0| | |

| | |Source B N7:4| | |

| | | 0| | |

| | |Dest N7:5| | |

| | | 0| | |

| | +––––––––––––––––––+ | |

| | +SQR–––––––––––––––+ | |

| +–+SQUARE ROOT +–+ |

| |Source N7:5| |

| | 0| |

| |Dest N7:0| |

| | 0| |

| +––––––––––––––––––+ |

| Rung 2:1 +CPT––––––––––––––––––––––––+ |

|––––––––––––––––––––––––––––––––––––––––––––––––+COMPUTE +–|

| |Dest N10:0| |

| | 0| |

| |Expression | |

| |SQR ((N7:1 ** 2) + (N7:2 **| |

| |2)) | |

| +–––––––––––––––––––––––––––+ |

| Rung 2:2 |

|–––––––––––––––––––––––––––––––––––––+END+––––––––––––––––––––––––––––––––––––|

| |

3–26

Math Instructions

Swap (SWP)

SWP

SWAP

Source

Length

Output Instruction

✓ ✓ ✓

Use this instruction to swap the low and high bytes of a specified number of words in a bit, integer, ASCII, or string file. Use this instruction with SLC 5/03

(OS302), SLC 5/04 (OS401), and SLC 5/05 processors.

Entering Parameters

Enter the following parameters when programming this instruction:

Source can only be an indexed word address.

Length refers to the number of words to be swapped, regardless of the file type.

The address is limited to integer constants. For bit, integer, and ASCII file types, the length range is 1 to 128. For the string file type, the length range is 1 to 41. Note that this instruction is restricted to a single string element and cannot cross a string element boundary.

The following example shows how the SWP instruction works.

SWP

SWAP

Source

Length

#ST10:1.1

13

Before:

ST10:1 = abcdefghijklmnopqrstuvwxyz

After

ST10:1 = badcfehgjilknmporqtsvuxwzy

3–27

Arc Sine (ASN)

ASN

ARC SINE

Source

Dest

Output Instruction

✓ ✓ ✓

Use the ASN instruction to take the arc sine of a number (source in radians) and store the result (in radians) in the destination. The source must be greater than or equal to –1 and less than or equal to 1. The resulting value in the destination is always greater than or equal to –Pi/2 and less than or equal to Pi/2, where Pi =

3.141592. Use this instruction with SLC 5/03 (OS302), SLC 5/04 (OS401), and

SLC 5/05 processors.

Updates to Arithmetic Status Bits

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Processor:

always resets.

sets if an overflow is generated or an unsupported input is detected; otherwise resets.

sets if the result is zero; otherwise resets.

sets if the result is negative; otherwise resets.

Arc Cosine (ACS)

ACS

ARC COSINE

Source

Dest

Output Instruction

✓ ✓ ✓

Use the ACS instruction to take the arc cosine of a number (source in radians) and store the result (in radians) in the destination. The source must be greater than or equal to –1 and less than or equal to 1. The resulting value in the destination is always greater than or equal to 0 and less than or equal to Pi, where Pi = 3.141592.

Use this instruction with SLC 5/03 (OS302), SLC 5/04 (OS401), and SLC 5/05 processors.

Updates to Arithmetic Status Bits

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Processor:

always resets.

sets if an overflow is generated or an unsupported input is detected; otherwise resets.

sets if the result is zero; otherwise resets.

always resets.

3–28

Math Instructions

Arc Tangent (ATN)

ATN

ARC TANGENT

Source

Dest

Output Instruction

✓ ✓ ✓

Use the ATN instruction to take the arc tangent of a number (source) and store the result (in radians) in the destination. The resulting value in the destination is always greater than or equal to –Pi/2 and less than or equal to Pi/2, where Pi = 3.141592.

Use this instruction with SLC 5/03 (OS302), SLC 5/04 (OS401), and SLC 5/05 processors.

Updates to Arithmetic Status Bits

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Processor:

always resets.

sets if an overflow is generated or an unsupported input is detected; otherwise resets.

sets if the result is zero; otherwise resets.

sets if the result is negative; otherwise resets.

Cosine (COS)

COS

COSINE

Source

Dest

Output Instruction

✓ ✓ ✓

Use the COS instruction to take the cosine of a number (source in radians) and store the result in the destination. The source must be greater than or equal to –205887.4

and less than or equal to 205887.4. The greatest accuracy is achieved when the source is greater than –2 Pi and less than 2 Pi, where Pi = 3.141592. The resulting value in the destination is always greater than or equal to –1 and less than or equal to 1. Use this instruction with SLC 5/03 (OS302), SLC 5/04 (OS401), and

SLC 5/05 processors.

Updates to Arithmetic Status Bits

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Processor:

always resets.

sets if an overflow is generated or an unsupported input is detected; otherwise resets.

sets if the result is zero; otherwise resets.

sets if the result is negative; otherwise resets.

3–29

Natural Log (LN)

LN

NATURAL LOG

Source

Dest

Output Instruction

✓ ✓ ✓

Use the LN instruction to take the natural log of the value in the source and store the result in the destination. The source must be greater than zero. The resulting value in the destination is always greater than or equal to –87.33654 and less than or equal to 88.72284. Use this instruction with SLC 5/03 (OS302), SLC 5/04 (OS401), and

SLC 5/05 processors.

Updates to Arithmetic Status Bits

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Processor:

always resets.

sets if an overflow is generated or an unsupported input is detected; otherwise resets.

sets if the result is zero; otherwise resets.

sets if the result is negative; otherwise resets.

Log to the Base 10 (LOG)

LOG

LOG BASE 10

Source

Dest

Output Instruction

✓ ✓ ✓

Use the LOG instruction to take the log base 10 of the value in the source and store the result in the destination. The source must be greater than zero. The resulting value in the destination is always greater than or equal to –37.92978 and less than or equal to 38.53184. Use this instruction with SLC 5/03 (OS302), SLC 5/04 (OS401), and SLC 5/05 processors.

Updates to Arithmetic Status Bits

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Processor:

always resets.

sets if an overflow is generated or an unsupported input is detected; otherwise resets.

sets if the result is zero; otherwise resets.

sets if the result is negative; otherwise resets.

3–30

Math Instructions

Sine (SIN)

SIN

SINE

Source

Dest

Output Instruction

✓ ✓ ✓

Use the SIN instruction to take the sine of a number (source in radians) and store the result in the destination. The source must be greater than or equal to –205887.4 and less than or equal to 205887.4. The greatest accuracy is achieved when the source is greater than –2 Pi and less than 2 Pi, where Pi = 3.141592. The resulting value in the destination is always greater than or equal to –1 and less than or equal to 1. Use this instruction with SLC 5/03 (OS302), SLC 5/04 (OS401), and SLC 5/05 processors.

Updates to Arithmetic Status Bits

With this Bit: The Processor:

Carry (C)

Overflow (V) always resets.

sets if an overflow is generated or an unsupported input is detected; otherwise resets.

Zero (Z)

Sign (S) sets if the result is zero; otherwise resets.

sets if the result is negative; otherwise resets.

Tangent (TAN)

TAN

TANGENT

Source

Dest

Output Instruction

✓ ✓ ✓

Use the TAN instruction to take the tangent of a number (source in radians) and store the result in the destination. The value in the source must be greater than or equal to –102943.7 and less than or equal to 102943.7. The greatest accuracy is achieved when the source is greater than –2 Pi and less than 2 Pi, where

Pi = 3.141592. The resulting value in the destination is either a real number or infinity. Use this instruction with SLC 5/03 (OS302), SLC 5/04 (OS401), and

SLC 5/05 processors.

Updates to Arithmetic Status Bits

With this Bit: The Processor:

Carry (C) always resets.

Overflow (V)

Zero (Z)

Sign (S) sets if an overflow is generated or an unsupported input is detected; otherwise resets.

sets if the result is zero; otherwise resets.

sets if the result is negative; otherwise resets.

3–31

X to the Power of Y (XPY)

XPY

X TO POWER OF Y

Source A

Source B

Dest

Output Instruction

✓ ✓ ✓

Use the XPY instruction to raise a value (source A) to a power (source B) and store the result in the destination. If the value in source A is negative, the exponent

(source B) should be a whole number. If it is not a whole number, the overflow bit is set and the absolute value of the base is used in the calculation. Use this instruction with SLC 5/03 (OS302), SLC 5/04 (OS401), and SLC 5/05 processors.

The XPY instruction uses the following algorithm:

XPY = 2 ** (Y * log

2

(X))

If any of the intermediate operations in this algorithm produce an overflow, the

Arithmetic Overflow Status bit (S:0/1) is set.

Updates to Arithmetic Status Bits

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Processor:

always resets.

sets if an overflow is generated or an unsupported input is detected; otherwise resets.

sets if the result is zero; otherwise resets.

sets if the result is negative; otherwise resets.

3–32

Math Instructions

Math Instructions in the Paper Drilling Machine

Application Example

This section provides ladder rungs to demonstrate the use of math instructions. The rungs are part of the paper drilling machine application example described in

appendix H. You will be adding to the subroutine in file 7 that was started in

chapter 1.

Adding File 7

Rung 7:1

This rung resets the number of 1/4” increments and the 1/4” thousands when the

”drill change reset” keyswitch is energized. This should occur following each drill bit change.

| drill 1/4” |

| change Thousands |

| reset |

| keyswitch |

| I:1.0 +CLR–––––––––––––––+ |

|––––] [––––––––––––––––––––––––––––––––––––––––––––––+–+CLEAR +–+–|

| 8 | |Dest N7:11| | |

| | | 0| | |

| | +––––––––––––––––––+ | |

| | 1/4” | |

| | increments | |

| | | |

| | +CLR–––––––––––––––+ | |

| +–+CLEAR +–+ |

| |Dest N7:10| |

| | 0| |

| +––––––––––––––––––+ |

Rung 7:6

Keep a running total of how many inches of paper have been drilled with the current drill bit. Every time a hole is drilled, add the thickness (in 1/4”s) to the running total (kept in 1/4”s). The OSR is necessary because the ADD executes every time the rung is true, and the drill body would actuate the

DRILL DEPTH limit switch for more than 1 program scan. Integer N7:12 is the integer–converted value of the BCD thumbwheel on inputs I:3/11 – I:3/14.

| Drill |Tool Wear 1/4” |

| Depth LS | OSR 1 increments |

| |

| I:1.0 B3:1 +ADD–––––––––––––––+ |

|––––] [–––––––[OSR]––––––––––––––––––––––––––––––––––––––+ADD +–|

| 4 8 |Source A N7:12| |

| | 1| |

| |Source B N7:10| |

| | 0| |

| |Dest N7:10| |

| | 0| |

| +––––––––––––––––––+ |

3–33

3–34

Rung 7:7

When the number of 1/4” increments surpasses 1000, find out now many increments we are past 1000 and store in N7:20, add 1 to the total of ’1000

1/4”’ increments, and re–initialize the 1/4” increments accumulator to how many increments were beyond 1000.

| 1/4” |

| increments |

| |

| +GEQ–––––––––––––––+ +SUB–––––––––––––––+ |

|–+GRTR THAN OR EQUAL+––––––––––––––––––––––––––––––––+–+SUBTRACT +–+–|

| |Source A N7:10| | |Source A N7:10| | |

| | 0| | | 0| | |

| |Source B 1000| | |Source B 1000| | |

| | | | | | | |

| +––––––––––––––––––+ | |Dest N7:20| | |

| | | 0| | |

| | +––––––––––––––––––+ | |

| | 1/4” | |

| | Thousands | |

| | +ADD–––––––––––––––+ | |

| +–+ADD +–+ |

| | |Source A 1| | |

| | | | | |

| | |Source B N7:11| | |

| | | 0| | |

| | |Dest N7:11| | |

| | | 0| | |

| | +––––––––––––––––––+ | |

| | | |

| | | |

| | | |

| | 1/4” | |

| | increments | |

| | +MOV–––––––––––––––– | |

| +–+MOVE +–+ |

| |Source N7:20| |

| | 0| |

| |Dest N7:10| |

| | 0| |

| +––––––––––––––––––+ |

|–––––––––––––––––––––––––––––––––––––+END+––––––––––––––––––––––––––––––––––––|

Data Handling Instructions

4

Data Handling Instructions

This chapter contains general information about the data handling instructions and explains how they function in your application program. Each of the instructions includes information on:

• what the instruction symbol looks like

• how to use the instruction

In addition, the last section contains an application example for a paper drilling machine that shows the data handling instructions in use.

Data Handling Instructions

Mnemonic

Instruction

Name

TOD

FRD

DEG

RAD

DCD

ENC

COP and

FLL

Convert to BCD Converts the integer source value to BCD format and stores it in the destination.

Convert from BCD Converts the BCD source value to an integer and stores it in the destination.

Convert from

Radians to

Degrees

Converts radians (source) to degrees and stores the result in the destination.

Convert from

Degrees to

Radians

Converts degrees (source) to radians and stores the result in the destination.

Decode 4 to 1 of

16

Decodes a 4-bit value (0 to 15), turning on the corresponding bit in the 16-bit destination.

Encode 1 of 16 to 4 Encodes a 16-bit source to a 4-bit value. Searches the source from the lowest to the highest bit, and looks for the first set bit. The corresponding bit position is written to the destination as an integer.

Copy File and

Fill File

The COP instruction copies data from the source file to the destination file The FLL instruction loads a source value into each position in the destination file.

4–3

4–6

4–10

4–11

4–12

4–13

4–14

continued on next page

4–1

AND

OR

XOR

NOT

NEG

Mnemonic

Instruction

Name

MOV

Move

MVM

Masked Move

FFL and

FFU

And

Or

Exclusive Or

Not

Negate

FIFO Load and

FIFO Unload

LFL and

LFU

LIFO Load and

LIFO Unload

Moves the source value to the destination.

Moves data from a source location to a selected portion of the destination.

Performs a bitwise AND operation.

Performs a bitwise inclusive OR operation.

Performs a bitwise exclusive OR operation.

Performs a NOT operation.

Changes the sign of the source and stores it in the destination.

The FFL instruction loads a word into a FIFO stack on successive false-to-true transitions. The FFU unloads a word from the stack on successive falseto-true transitions. The first word loaded is the first to be unloaded.

The LFL instruction loads a word into a LIFO stack on successive false-to-true transitions. The LFU unloads a word from the stack on successive falseto-true transitions. The last word loaded is the first to be unloaded.

4–30

4–19

4–20

4–22

4–23

4–24

4–25

4–26

4–29

About the Data Handling Instructions

Use these instructions to convert information, manipulate data in the controller, and perform logic operations.

In this chapter you will find a general overview preceding groups of instructions.

Before you learn about the instructions in each of these groups, we suggest that you read the overview. This chapter contains the following overviews:

Move and Logical Instructions Overview

FIFO and LIFO Instructions Overview

4–2

Data Handling Instructions

Convert to BCD (TOD)

✓ ✓ ✓ ✓ ✓ ✓ ✓

TOD

TO BCD

Source

Dest S:13

00000000

Output Instruction

Fixed and SLC 5/01

Processors

TOD

TO BCD

Source

Dest

Output Instruction

SLC 5/02 and higher processors and MicroLogix 1000 controllers

Use this instruction to convert 16-bit integers into BCD values.

With Fixed and SLC 5/01 processors, the destination can only be the math register.

With SLC 5/02 and higher processors and MicroLogix 1000 controllers, the destination parameter can be a word address in any data file, or it can be the math register, S:13 and S:14.

If the integer value you enter is negative, the absolute value of the number is used for conversion.

Updates to Arithmetic Status Bits

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Processor:

always resets.

sets if the BCD result is larger than 9999. Overflow results in a minor error.

sets if destination value is zero.

sets if the source word is negative; otherwise resets.

Changes to the Math Register, S:13 and S:14

Contains the 5–digit BCD result of the conversion. This result is valid at overflow.

4–3

Example 1

Example 2

✓ ✓ ✓ ✓

The integer value 9760 stored at N7:3 is converted to BCD and the BCD equivalent is stored in N10:0. The maximum BCD value possible is 9999.

TOD

TO BCD

Source

Dest

N7:3

9760

N10:0

9760

The destination value is displayed in

BCD format.

9 7 6 0

N7:3 Decimal

0010 0110 0010 0000

9 7 6 0

N10:0 4–digit BCD

1001 0111 0110 0000

✓ ✓ ✓ ✓

The integer value 32760 stored at N7:3 is converted to BCD. The 5-digit BCD value is stored in the math register. The lower 4 digits of the BCD value is moved to output word O:2 and the remaining digit is moved through a mask to output word

O:3.

When using the math register as the destination parameter in the TOD instruction, the maximum BCD value possible is 32767. However, for BCD values above 9999, the overflow bit is set, resulting in minor error bit S:5/0 also being set. Your ladder program can unlatch S:5/0 before the end of the scan to avoid major error 0020, as done in this example.

4–4

Overflow Bit

Data Handling Instructions

3 2 7 6 0

N7:3 Decimal

0

15

0 0 3

0

2

15

7 6 0

0

S:13 & S:14 5–digit BCD

S:14 S:13

This example will output the absolute value (0–32767) contained in N7:3 as 5 BCD digits in output slots 2 and 3.

] [

TOD

TO BCD

Source

Dest

N7:3

32760

S:13

00032760

S:13 and S:14 are displayed in BCD format.

Minor Error Bit

S:0

] [

1

S:5

(U)

0

MOV

MOVE

Source

Dest

S:13

10080

O:2.0

10080

0010 0111 0110 0000

MVM

MASKED MOVE

Source

Mask

Dest

S:14

3

000F

O:3.0

3

0000 0000 0000 0011

4–5

Convert from BCD (FRD)

FRD

FROM BCD

Source S:13

00000000

Dest

Output Instruction

Fixed and SLC 5/01

Processors

✓ ✓ ✓ ✓ ✓ ✓ ✓

Use this instruction to convert BCD values to integer values. With Fixed and

SLC 5/01 processors, the source can only be the math register. With SLC 5/02 and higher processors and MicroLogix 1000 controllers, the source parameter can be a word address in any data file, or it can be the math register, S:13.

FRD

FROM BCD

Source

Dest

Output Instruction

SLC 5/02 and higher Processors and MicroLogix 1000 controllers

Updates to Arithmetic Status Bits

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Processor:

always resets.

sets if non–BCD value is contained at the source or the value to be converted is greater than 32,767; otherwise reset. Overflow results in a minor error.

sets if destination value is zero.

always resets.

Note

We recommend that you always provide ladder logic filtering of all BCD input devices prior to performing the FRD instruction. The slightest difference in point-to-point input filter delay can cause the FRD instruction to overflow due to the conversion of a non–BCD digit.

4–6

S:1

]/[

15

EQU

EQUAL

Source A

Source B

N7:1

0

I:0.0

0

Data Handling Instructions

FRD

FROM BCD

Source

Dest

I:0.0

0

N7:2

0

MOV

MOVE

Source

Dest

I:0.0

0

N7:1

0

Note

In the above example, the two rungs cause the processor to verify that the value at

I:0.0 remains the same for two consecutive scans before it executes the FRD. This prevents the FRD from converting a non-BCD value during an input value change.

To convert numbers larger than 9999 BCD, the source must be the Math Register

(S:13). You must reset the Minor Error bit (S:5.0) to prevent an error.

Changes to the Math Register, S:13 and S:14

Used as the source for converting the entire number range of a register.

Example 1

✓ ✓ ✓ ✓ ✓

The BCD value 9760 at source N7:3 is converted and stored in N10:0. The maximum source value is 9999, BCD.

FRD

FROM BCD

Source

Dest

N7:3

9760

N10:0

9760

The source value is displayed in BCD format.

9 7 6 0

N7:3 4–digit BCD

1001 0111 0110 0000

9 7 6 0

N10:0 Decimal

0010 0110 0010 0000

4–7

Example 2

Note

✓ ✓ ✓ ✓ ✓ ✓ ✓

The BCD value 32760 in the math register is converted and stored in N7:0. The maximum source value is 32767, BCD.

FRD

FROM BCD

Source S:13

00032760

Dest N7:0

32760

S:13 and S:14 are displayed in BCD format.

0000 0000 0000 0011 0010 0111 0110 0000

15

S:14

0 15

S:13

0

0 0 0 3 2 7 6 0

5–digit BCD

3 2 7 6 0

N7:0 Decimal

0111 1111 1111 1000

You should convert BCD values to integer before you manipulate them in your ladder program. If you do not convert the values, the processor manipulates them as integers and their value is lost.

If the math register (S:13 and S:14) is used as the source for the FRD instruction and the BCD value does not exceed 4 digits, be sure to clear word S:14 before executing the FRD instruction. If S:14 is not cleared and a value is contained in this word from another math instruction located elsewhere in the program, an incorrect decimal value will be placed in the destination word.

4–8

Data Handling Instructions

Clearing S:14 before executing the FRD instruction is shown below:

I:1

] [

0

MOV

MOVE

Source

Dest

N7:2

4660

S:13

4660

CLR

CLEAR

Dest S:14

0

FRD

FROM BCD

Source S:13

00001234

Dest N7:0

1234

0001 0010 0011 0100

S:13 and S:14 are displayed in BCD format.

0000 0100 1101 0010

When the input condition is set (1), a BCD value (transferred from a 4-digit thumbwheel switch for example) is moved from word N7:2 into the math register.

Status word S:14 is then cleared to make certain that unwanted data is not present when the FRD instruction is executed.

4–9

Radian to Degrees (DEG)

DEG

Radians to Degrees

Source

Dest

Output Instruction

✓ ✓ ✓

Use this instruction to convert radians (source) to degrees and store the result in the destination. The following formula applies:

Source 180/

Π where

Π

= 3.141592

Use this instruction with SLC 5/03 (OS302), SLC 5/04 (OS401), and SLC 5/05 processors.

Entering Parameters

Source is the integer and/or floating point values.

Destination is the address of the word where the data is to be stored.

Updates to Arithmetic Status Bits

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Processor:

always resets.

sets if overflow generated or an unsupported input is detected; otherwise resets sets if the result is zero; otherwise resets sets if the result is negative; otherwise resets

4–10

Data Handling Instructions

Degrees to Radians (RAD)

RAD

Degress to Radians

Source

Dest

Output Instruction

✓ ✓ ✓

Use this instruction to convert degrees (source) to radians and store the result in the destination. The following formula applies:

Source

Π/

180 where

Π

= 3.141592

Use this instruction with SLC 5/03 (OS302), SLC 5/04 (OS401), and SLC 5/05 processors processors.

Entering Parameters

Source is the integer and/or floating point values.

Destination is the address of the word where the data is to be stored.

Updates to Arithmetic Status Bits

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Processor:

always resets.

sets if overflow generated or an unsupported input is detected; otherwise resets sets if the result is zero; otherwise resets sets if the result is negative; otherwise resets

4–11

Decode 4 to 1 of 16 (DCD)

DCD

DECODE 4 to 1 of 16

Source

Dest

✓ ✓ ✓ ✓ ✓ ✓ ✓

When executed, this instruction sets one bit of the destination word. The particular bit that is turned on depends on the value of the first four bits of the source word.

See the table below.

Output Instruction

Use this instruction to multiplex data in applications such as rotary switches, keypads, and bank switching.

Source Destination

Bit 15–04 03 02 01 00 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

x 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

x 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

x 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

x 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

x 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

x 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

x 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

x 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

x 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0

x 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

x 1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0

x 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0

x 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0

x 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

x 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Entering Parameters

Source is the address that contains the bit decode information. Only the first four bits (0–3) are used by the DCD instruction. The remaining bits may be used for other application specific needs. Change the value of the first four bits of this word to select one bit of the destination word.

Destination is the address of the word where the data is to be stored.

Updates to Arithmetic Status Bits

Unaffected.

4–12

Data Handling Instructions

Encode 1 of 16 to 4 (ENC)

ENC

ENCODE 1 of 16 to 4

Source

Dest

When the rung is true, this output instruction searches the source from the lowest to the highest bit, and looks for the first set bit. The corresponding bit position is written to the destination as an integer as shown in the table below.

Output Instruction

Source Destination

Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15–04 03 02 01 00

x x x x x x x x x x x x x x x 1 x 0 0 0 0

x x x x x x x x x x x x x x 1 0 x 0 0 0 1

x x x x x x x x x x x x x 1 0 0 x 0 0 1 0

x x x x x x x x x x x x 1 0 0 0 x 0 0 1 1

x x x x x x x x x x x 1 0 0 0 0 x 0 1 0 0

x x x x x x x x x x 1 0 0 0 0 0 x 0 1 0 1

x x x x x x x x x 1 0 0 0 0 0 0 x 0 1 1 0

x x x x x x x x 1 0 0 0 0 0 0 0 x 0 1 1 1

x x x x x x x 1 0 0 0 0 0 0 0 0 x 1 0 0 0

x x x x x x 1 0 0 0 0 0 0 0 0 0 x 1 0 0 1

x x x x x 1 0 0 0 0 0 0 0 0 0 0 x 1 0 1 0

x x x x 1 0 0 0 0 0 0 0 0 0 0 0 x 1 0 1 1

x x x 1 0 0 0 0 0 0 0 0 0 0 0 0 x 1 1 0 0

x x 1 0 0 0 0 0 0 0 0 0 0 0 0 0 x 1 1 0 1

x 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 1 1 1 0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 1 1 1 1

Entering Parameters

Source is the address of the word to be encoded. Only one bit of this word should be on at any time. If more than one bit in the source is set, the destination bits are set based on the least significant bit that is set. If a source of zero is used, all of the destination bits are reset and the zero bit is set.

Destination is the address that contains the bit encode information. Bits 4–15 of the destination are reset by the ENC instruction.

Updates to Arithmetic Status Bits

The arithmetic status bits are found in Word 0, bits 0–3 in the status file. After an instruction is executed, the arithmetic status bits in the status file are updated:

S:0/0

With this Bit:

Carry (C)

S:0/1

S:0/2

S:0/3

Overflow (V)

Zero (Z)

Sign (S) always resets.

always resets.

The Controller:

sets if more than one bit in the source is set; otherwise reset. The math overflow bit (S:5/0) is not set.

sets if destination value is zero.

4–13

Copy File (COP) and

Fill File (FLL) Instructions

✓ ✓ ✓ ✓ ✓ ✓ ✓

COP

COPY FILE

Source

Dest

Length

FLL

FILL FILE

Source

Dest

Length

Output Instructions

Using COP

The destination file type determines the number of words that an instruction transfers. For example, if the destination file type is a counter and the source file type is an integer, three integer words are transferred for each element in the counter-type file.

After a COP or FLL instruction is executed, index register S:24 is cleared to zero.

This instruction copies blocks of data from one location into another. It uses no status bits. If you need an enable bit, program an output instruction (OTE) in parallel using an internal bit as the output address. The following figure shows how file instruction data is manipulated.

Source Destination

File to File

Entering Parameters

Enter the following parameters when programming this instruction:

Source is the address of the file you want to copy. You must use the file indicator (#) in the address. When using either an SLC 5/03 (OS301 or higher),

SLC 5/04 (OS401), or SLC 5/05 processor, floating point and string values are supported.

Destination is the starting address where the instruction stores the copy. You must use the file indicator (#) in the address. When using either an SLC 5/03

(OS301 or higher), SLC 5/04 (OS401), or SLC 5/05 processor, floating point and string values are supported.

4–14

Note

Data Handling Instructions

Length is the number of elements in the file you want to copy.

For SLC processors, if the destination file type is 3 words per element

(Timer or Counter), you can specify a maximum length of 42. If the destination file type is 1 word per element, you can specify a maximum length of 128 words.

MicroLogix 1000 controllers, see the table below:

Output

Input

Status

Bit

Timer

Counter

Control

Integer

type is a:

33

32

40

32

then you can specify a maximum length of:

Discrete Controllers Analog Controllers

1

2

5

8

16

105

The maximum lengths apply when the source is of the same file type.

All elements are copied from the source file into the destination file each time the instruction is executed. Elements are copied in ascending order.

If your destination file type is a timer, counter, or control file, be sure that the source words corresponding to the status words of your destination file contains zeros.

Be sure that you accurately specify the starting address and length of the data block you are copying. The instruction will not write over a file boundary (such as between files N16 and N17) at the destination. An error occurs if a write is attempted over a file boundary.

You can perform file shifts by specifying a source element address one or more elements greater than the destination element address within the same file. This shifts data to lower element addresses.

4–15

Using FLL

This instruction loads elements of a file with either a program constant or value from an element address.

The instruction fills the words of a file with a source value. It uses no status bits. If you need an enable bit, program a parallel output that uses a storage address. The following figure shows how file instruction data is manipulated.

Destination

Source

Word to File

Entering Parameters

Enter the following parameters when programming this instruction:

Source is the program constant or element address. The file indicator (#) is not required for an element address. When using either an SLC 5/03 (OS301 or higher), SLC 5/04 (OS401), or SLC 5/05 processor, floating point and string values are supported.

Destination is the destination starting address of the file you want to fill. You must use the file indicator (#) in the address. When using either an SLC 5/03

(OS301 or higher), SLC 5/04 (OS401), or SLC 5/05 processor, floating point and string values are supported.

4–16

Data Handling Instructions

Length is the number of elements in the file you want filled.

For SLC processors, if the destination file type is 3 words per element

(Timer or Counter), you can specify a maximum length of 42. If the destination file type is 1 word per element, you can specify a maximum length of 128 words.

For MicroLogix 1000 controllers, see the table below:

Output

Input

Status

Bit

Timer

Counter

Control

Integer

type is a:

33

32

40

32

then you can specify a maximum length of:

Discrete Controllers Analog Controllers

1

2

5

8

16

105

All elements are filled from the source value (typically a constant) into the specified destination file each scan the rung is true. Elements are filled in ascending order.

The instruction will not write over a file boundary (such as between files N16 and

N17) at the destination. An error is declared if a write is attempted over a file boundary.

4–17

Move and Logical Instructions Overview

The following general information applies to move and logical instructions.

Entering Parameters

Source is the address of the value on which the logical or move operation is to be performed. The source can be a word address or a program constant, unless otherwise described. If the instruction has two source operands, it does not accept program constants in both operands.

When using either an SLC 5/03 (OS301 or higher), SLC 5/04, or SLC 5/05 processor, floating point and string values are supported.

Destination is the result address of a move or logical operation. It must be a word address.

Using Indexed Word Addresses

You have the option of using indexed word addresses for instruction parameters

specifying word addresses. Indexed addressing is discussed in appendix C.

Updates to Arithmetic Status Bits

The arithmetic status bits are found in Word 0, bits 0–3 in the controller status file.

After an instruction is executed, the arithmetic status bits in the status file are updated.

Using Indirect Word Addresses

You have the option of using indirect word-level and bit-level addresses for instructions specifying word addresses when using an SLC 5/03 (OS302), SLC 5/04

(OS401), or SLC 5/05 processors processors. See appendix C for more information.

Changes to the Math Register, S:13 and S:14

Move and logical instructions do not affect the math register.

4–18

Data Handling Instructions

Move (MOV)

MOV

MOVE

Source

Dest

Output Instruction

✓ ✓ ✓ ✓ ✓ ✓ ✓

This output instruction moves the source value to the destination location. As long as the rung remains true, the instruction moves the data each scan.

Entering Parameters

Enter the following parameters when programming this instruction:

Source is the address or constant of the data you want to move.

Destination is the address where the instruction moves the data.

Application Note: If you wish to move one word of data without affecting the math flags, use a copy (COP) instruction with a length of 1 word instead of the

MOV instruction.

Updates to Arithmetic Status Bits

S:0/0

S:0/1

S:0/2

S:0/3

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Controller:

always resets.

always resets.

sets if result is zero; otherwise resets.

sets if result is negative (most significant bit is set); otherwise resets.

4–19

Masked Move (MVM)

MVM

MASKED MOVE

Source

Mask

Dest

Output Instruction

✓ ✓ ✓ ✓ ✓ ✓ ✓

The MVM instruction is a word instruction that moves data from a source location to a destination, and allows portions of the destination data to be masked by a separate word. As long as the rung remains true, the instruction moves the data each scan.

Entering Parameters

Enter the following parameters when programming this instruction:

Source is the address of the data you want to move.

Mask is the address of the mask through which the instruction moves data; the mask can be a hexadecimal value (constant).

Destination is the address where the instruction moves the data.

Updates to Arithmetic Status Bits

S:0/0

S:0/1

S:0/2

S:0/3

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Controller:

always resets.

always resets.

sets if result is zero; otherwise resets.

sets if result is negative; otherwise resets.

4–20

Operation

Note

Data Handling Instructions

When the rung containing this instruction is true, data at the source address passes through the mask to the destination address. See the figure below.

MVM

MASKED MOVE

Source

Mask

Dest

B3:0

F0F0

B3:2

B3:2 before move

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 source B3:0

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Mask F0F0

1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0

B3:2 after move

0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 1

Mask data by resetting bits in the mask; pass data by setting bits in the mask to one.

The bits of the mask can be fixed by a constant value, or you can vary them by assigning the mask a direct address.

Bits in the destination that correspond to zeros in the mask are not altered.

4–21

And (AND)

AND

BITWISE AND

Source A

Source B

Dest

Output Instruction

✓ ✓ ✓ ✓ ✓ ✓ ✓

This instruction performs a bit-by-bit logical AND. The operation is performed using the value at source A and the value at source B. The result is stored in the destination.

Truth Table

A

0

1

0

1

Dest = A AND B

B

1

1

0

0

Dest

0

1

0

0

Source A and B can either be a word address or a constant; however, both sources cannot be a constant. The destination must be a word address.

Application Note: When entering constants, you can use the ampersand (&) operator to change the radix of your entry. For example, instead of entering –1 as a constant, you could enter &B1111111111111111 or &HFFFF.

Updates to Arithmetic Status Bits

S:0/0

S:0/1

S:0/2

S:0/3

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Controller:

always resets.

always resets.

sets if result is zero; otherwise resets.

sets if most significant bit is set; otherwise resets.

4–22

Data Handling Instructions

Or (OR)

OR

BITWISE INCLUS OR

Source A

Source B

Dest

Output Instruction

✓ ✓ ✓ ✓ ✓ ✓ ✓

This instruction performs a bit-by-bit logical OR. The operation is performed using the value at source A and the value at source B. The result is stored in the destination.

Truth Table

A

0

1

0

1

Dest = A OR B

B

1

1

0

0

Dest

1

1

0

1

Source A and B can either be a word address or a constant; however, both sources cannot be a constant. The destination must be a word address.

Application Note: When entering constants, you can use the ampersand (&) operator to change the radix of your entry. For example, instead of entering –1 as a constant, you could enter &B1111111111111111 or &HFFFF.

Updates to Arithmetic Status Bits

S:0/0

S:0/1

S:0/2

S:0/3

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Controller:

always resets.

always resets.

sets if result is zero; otherwise resets.

sets if result is negative (most significant bit is set) otherwise resets.

4–23

Exclusive Or (XOR)

XOR

BITWISE EXCLUS OR

Source A

Source B

Dest

Output Instruction

✓ ✓ ✓ ✓ ✓ ✓ ✓

This instruction performs a bit-by-bit logical XOR. The operation is performed using the value at source A and the value at source B. The result is stored in the destination.

Truth Table

A

0

1

0

1

Dest = A XOR B

B

1

1

0

0

Dest

1

0

0

1

Source A and B can either be a word address or a constant; however, both sources cannot be a constant. The destination must be a word address.

Application Note: When entering constants, you can use the ampersand (&) operator to change the radix of your entry. For example, instead of entering –1 as a constant, you could enter &B1111111111111111 or &HFFFF.

Updates to Arithmetic Status Bits

S:0/0

S:0/1

S:0/2

S:0/3

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Controller:

always resets.

always resets.

sets if result is zero; otherwise resets sets if result is negative (most significant bit is set); otherwise resets.

4–24

Data Handling Instructions

Not (NOT)

NOT

NOT

Source

Dest

Output Instruction

✓ ✓ ✓ ✓ ✓ ✓ ✓

This instruction performs a bit-by-bit logical NOT. The operation is performed using the value at source A. The result (one’s complement of A) is stored in the destination.

Truth Table

Dest = NOT A

A

0

1

Dest

1

0

The source and destination must be word addresses.

Application Note: When entering constants, you can use the ampersand (&) operator to change the radix of your entry. For example, instead of entering –1 as a constant, you could enter &B1111111111111111 or &HFFFF.

Updates to Arithmetic Status Bits

S:0/0

S:0/1

S:0/2

S:0/3

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Controller:

always resets.

always resets.

sets if result is zero; otherwise resets.

sets if result is negative (most significant bit is set); otherwise resets.

4–25

Negate (NEG)

NEG

NEGATE

Source

Dest

Output Instruction

✓ ✓ ✓ ✓ ✓ ✓ ✓

Use the NEG instruction to change the sign of the source and then place it in the destination. The destination contains the two’s complement of the source. For example, if the source is 5, the destination would be –5.

The source and destination must be word addresses.

Updates to Arithmetic Status Bits

S:0/0

With this Bit:

Carry (C)

S:0/1 Overflow (V)

S:0/2

S:0/3

Zero (Z)

Sign (S)

The Controller:

clears if 0 or overflow, otherwise sets.

sets if overflow, otherwise reset. Overflow occurs only if

–32,768 is the source. On overflow, the minor error flag is also set. The value 32,767 is placed in the destination. If S:2/14 is set, then the unsigned, truncated overflow remains in the destination.

For floating point destinations, the overflow result remains in the destination.

sets if result is zero; otherwise resets.

sets if result is negative; otherwise resets.

4–26

Data Handling Instructions

FIFO and LIFO Instructions Overview

FIFO instructions load words into a file and unload them in the same order as they were loaded. The first word in is the first word out.

LIFO instructions load words into a file and unload them in the opposite order as they were loaded. The last word in is the first word out.

Entering Parameters

Enter the following parameters when programming these instructions:

Source is a word address or constant (–32,768 to 32,767) that becomes the next value in the stack.

Destination is a word address that stores the value that exits from the stack.

This Instruction:

FIFO’s FFU

LIFO’s LFU

Unloads the Value from:

First word

The last word entered

FIFO/LIFO is the address of the stack. It must be an indexed word address in the bit, input, output, or integer file. Use the same FIFO address for the associated FFL and FFU instructions; use the same LIFO address for the associated LFL and LFU instructions.

Length specifies the maximum number of words in the stack. For SLC processors this is 128 words and 105 words for MicroLogix 1000 controllers.

Address the length value by mnemonic (LEN).

Position is the next available location where the instruction loads data into the stack. This value changes after each load or unload operation. Address the position value by mnemonic (POS).

Control is a control file address. The status bits, the stack length, and the position value are stored in this element. Do not use the control file address for any other instruction.

4–27

Status bits of the control structure are addressed by mnemonic. These include:

Empty Bit EM (bit 12) is set by the processor to indicate the stack is empty.

Done Bit DN (bit 13) is set by the processor to indicate the stack is full.

This inhibits loading the stack.

FFU/LFU Enable Bit EU (bit 14) is set on a false-to-true transition of the

FFU/LFU rung and is reset on a true-to-false transition.

FFL/LFL Enable Bit EN (bit 15) is set on a false-to-true transition of the

FFL/LFL rung and is reset on a true-to-false transition.

Effects on Index Register S:24

The value present in S:24 is overwritten with the position value when a false-to–true transition of the FFL/FFU or LFL/LFU rung occurs. For the FFL/LFL, the position value determined at instruction entry is placed in S:24. For the FFU/LFU, the position value determined at instruction exit is placed in S:24.

When the DN bit is set, a false-to–true transition of the FFL/LFL rung does not change the position value or the index register value. When the EM bit is set, a false-to–true transition of the FFU/LFU rung does not change the position value or the index register value.

4–28

Data Handling Instructions

FIFO Load (FFL) and FIFO Unload (FFU)

FFL

FIFO LOAD

Source

FIFO

Control

Length

Position

FFU

FIFO UNLOAD

FIFO

Dest

Control

Length

Position

Output Instructions

✓ ✓ ✓ ✓ ✓

(EN)

(DN)

(EM)

FFL and FFU instructions are used in pairs. The FFL instruction loads words into a user-created file called a FIFO stack. The FFU instruction unloads words from the

FIFO stack, in the same order as they were entered.

(EU)

(DN)

(EM)

Instruction parameters have been programmed in the FFL–FFU instruction pair shown below.

FFL

FIFO LOAD

Source

FIFO

Control

Length

Position

N7:10

#N7:12

R6:0

34

9

(EN)

(DN)

(EM)

FFU

FIFO UNLOAD

FIFO

Dest

Control

Length

Position

#N7:12

N7:11

R6:0

34

9

(EU)

(DN)

(EM)

FFL–FFU Instruction Pair

N7:11

FFU instruction unloads data from stack #N7:12 at position 0,

N7:12.

Destination

N7:12

N7:13

N7:14

Position

0

1

4

5

2

3

8

9

6

7

34 words are allocated for FIFO stack starting at

N7:12, ending at N7:45.

Source

N7:10

FFL instruction loads data into stack #N7:12 at the next available position, 9 in this case.

N7:45

33

Loading and Unloading of Stack #N7:12

FFL Instruction Operation: When rung conditions change from false-to-true, the

FFL enable bit (EN) is set. This loads the contents of the source, N7:10, into the stack element indicated by the position number, 9. The position value then increments.

The FFL instruction loads an element at each false-to-true transition of the rung, until the stack is filled (34 elements). The processor then sets the done bit (DN), inhibiting further loading.

FFU Instruction Operation: When rung conditions change from false-to-true, the

FFU enable bit (EU) is set. This unloads the contents of the element at stack position 0 into the destination, N7:11. All data in the stack is shifted one element toward position zero, and the highest numbered element is zeroed. The position value then decrements.

The FFU instruction unloads an element at each false–to-true transition of the rung, until the stack is empty. The processor then sets the empty bit (EM).

4–29

LIFO Load (LFL) and LIFO Unload (LFU)

✓ ✓ ✓ ✓ ✓

LFL

LIFO LOAD

Source

LIFO

Control

Length

Position

LFU

LIFO UNLOAD

LIFO

Dest

Control

Length

Position

Output Instructions

(EN)

(DN)

(EM)

(EU)

(DN)

(EM)

LFL and LFU instructions are used in pairs. The LFL instruction loads words into a user–created file called a LIFO stack. The LFU instruction unloads words from the

LIFO stack in the opposite order as they were entered.

Instruction parameters have been programmed in the LFL – LFU instruction pair shown below.

LFL

LIFO LOAD

Source

LIFO

Control

Length

Position

N7:10

#N7:12

R6:0

34

9

(EN)

(DN)

(EM)

LFU

LIFO UNLOAD

LIFO

Dest

Control

Length

Position

#N7:12

N7:11

R6:0

34

9

(EU)

(DN)

(EM)

LFL–LFU Instruction Pair

LFU instruction unloads data from stack #N7:12 at position 8.

N7:11

Destination

N7:12

N7:13

N7:14

LFL instruction loads data into stack #N7:12 at the next available position, 9 in this case.

N7:10

Source

N7:45

Loading and Unloading of Stack #N7:12

Position

0

1

2

7

8

9

5

6

3

4

34 words are allocated for LIFO stack starting at

N7:12, ending at N7:45.

33

LFL Instruction Operation: When rung conditions change from false-to-true, the

LFL enable bit (EN) is set. This loads the contents of the source, N7:10, into the stack element indicated by the position number, 9. The position value then increments.

The LFL instruction loads an element at each false-to-true transition of the rung, until the stack is filled (34 elements). The processor then sets the done bit (DN), inhibiting further loading.

LFU Instruction Operation: When rung conditions change from false-to-true, the

LFU enable bit (EU) is set. This unloads data from the last element loaded into the stack (at the position value minus 1), placing it in the destination, N7:11. The position value then decrements.

The LFU instruction unloads one element at each false-to-true transition of the rung, until the stack is empty. The processor then sets the empty bit (EM).

4–30

Data Handling Instructions

Data Handling Instructions in the Paper Drilling Machine

Application Example

This section provides ladder rungs to demonstrate the use of data handling instructions. The rungs are part of the paper drilling machine application example

described in appendix H. You will be adding to the subroutine in file 7 that was

started in chapter 1.

Adding File 7

Rung 7:3

This rung moves the single digit BCD thumbwheel value into an internal Integer register. This is done to properly align the four BCD input signals prior to executing the BCD to Integer instruction (FRD). The thumbwheel is used to allow the operator to enter the thickness of the paper that is to be drilled. The thickness is entered in 1/4” increments. This provides a range of 1/4” to 2.25”

| BCD bit 0 |FRD bit 0 |

| I:1.0 N7:14 |

|––––––––––––––––––––––––––––––––––––––––––––––––––––+––––] [––––––––( )–––––+–|

| | 11 0 | |

| | BCD bit 1 |FRD bit 1 | |

| | I:1.0 N7:14 | |

| +––––] [––––––––( )–––––+ |

| | 12 1 | |

| | BCD bit 2 |FRD bit 2 | |

| | I:1.0 N7:14 | |

| +––––] [––––––––( )–––––+ |

| | 13 2 | |

| | BCD bit 3 |FRD bit 3 | |

| | I:1.0 N7:14 | |

| +––––] [––––––––( )–––––+ |

| 14 3 |

4–31

4–32

Rung 7:4

This rung converts the BCD thumbwheel value from BCD to Integer. This is done because the processor operates upon Integer values. This rung also ”debounces” the thumbwheel to ensure that the conversion only occurs on valid BCD values.

Note that invalid BCD values can occur while the operator is changing the BCD thumbwheel. This is due to input filter propagation delay differences between the 4 input circuits that provide the BCD input value.

| 1’st previous

| pass scan’s debounced

| bit BCD input BCD value

| value

| S:1 +EQU–––––––––––––––+ +FRD–––––––––––––––+ |

|–+––––]/[–––––+EQUAL +–+–––––––––––+FROM BCD +–+––––+––––|

| | 15 |Source A N7:13| | |Source N7:14| | | |

| | | 0| | | 0000| | | |

| | |Source B N7:14| | | 0000| | | |

| | | 0| | |Dest N7:12| | | |

| | +––––––––––––––––––+ | | 1| | | |

| | | Math +––––––––––––––––––+ | | |

| | | Math Math | | |

| | | Overflow Error | | |

| | | Bit Bit | | |

| | | S:0 S:5 | | |

| | +––––] [––––––––––––––(U)––––––––+ | |

| | 1 0 | |

| | this | |

| | scan’s | |

| | BCD input | |

| | value | |

| | +MOV–––––––––––––––+ | |

| +––––––––––––––––––––––––––––––––––––––––––––––––––+MOVE +–+ |

| |Source N7:14| |

| | 0| |

| |Dest N7:13| |

| | 0| |

| +––––––––––––––––––+ |

Rung 7:5

This rung ensures that the operator cannot select a paper thickness of 0. If this were allowed, the drill bit life calculation could be defeated, resulting in poor quality holes due to a dull drill bit. Therefore, the minimum paper thickness that is used to calculate drill bit wear is 1/4”.

| debounced debounced |

| BCD BCD |

| value value |

| +EQU–––––––––––––––+ +MOV–––––––––––––––+ |

|–+EQUAL +––––––––––––––––––––––––––––––––––––+MOVE +–|

| |Source A N7:12| |Source 1| |

| | 1| | | |

| |Source B 0| |Dest N7:12| |

| | | | 1| |

| +––––––––––––––––––+ +––––––––––––––––––+ |

Program Flow Instructions

5

Program Flow Instructions

This chapter contains general information about the program flow instructions and explains how they function in your application program. Each of the instructions includes information on:

• what the instruction symbol looks like

• how to use the instruction

In addition, the last section contains an application example for a paper drilling machine that shows the program flow control instructions in use.

Program Flow Control Instructions

Mnemonic

JMP and

LBL

JSR, SBR, and RET

MCR

TND

SUS

Instruction

Name

Jump to Label and

Label

Jump to Subroutine, Subroutine, and Return from Subroutine

Master Control Reset

Temporary End

Suspend

IIM

IOM

REF

Immediate Input with Mask

Immediate Output with Mask

Refresh

Jump forward or backward to the specified label instruction.

Jump to a designated subroutine and return.

Turn off all non–retentive outputs in a section of ladder program.

Mark a temporary end that halts program execution.

Identifies specific conditions for program debugging and system troubleshooting.

Program an Immediate Input with Mask.

Program an Immediate Output with Mask.

Interrupt the program scan to execute the I/O scan and service communications.

About the Program Flow Control Instructions

Use these instructions to control the sequence in which your program is executed.

Control instructions allow you to change the order in which the processor scans a ladder program. Typically, these instructions are used to minimize scan time, create a more efficient program, and troubleshoot a ladder program.

5–2

5–3

5–6

5–7

5–8

5–8

5–9

5–10

5–1

Jump (JMP) and Label (LBL)

(JMP)

]LBL[

✓ ✓ ✓ ✓ ✓ ✓ ✓

Use these instructions in pairs to skip portions of the ladder program.

If the Rung Containing the

Jump Instruction is:

True

False

Then the Program:

Skips from the rung containing the JMP instruction to the rung containing the designated LBL instruction and continues executing. You can jump forward or backward.

Does not execute the JMP instruction.

Note

Jumping forward to a label saves program scan time by omitting a program segment until needed. Jumping backward lets the controller execute program segments repeatedly.

Be careful not to jump backwards an excessive number of times. The watchdog timer could time out and fault the controller. Use a counter, timer, or the “program scan” register (system status register, word S:3, bits 0–7) to limit the amount of time you spend looping inside of JMP/LBL instructions.

Entering Parameters

Enter a decimal label number from 0 to 999. You can place up to:

256 labels for SLC processors in each subroutine file

1,000 labels for MicroLogix 1000 controllers in each subroutine file

Using JMP

The JMP instruction causes the controller to skip rungs. You can jump to the same label from one or more JMP instruction.

5–2

Program Flow Instructions

Using LBL

Note

This input instruction is the target of JMP instructions having the same label number. You must program this instruction as the first instruction of a rung. This instruction has no control bits.

You can program multiple jumps to the same label by assigning the same label number to multiple JMP instructions. However, label numbers must be unique.

Do not jump (JMP) into an MCR zone. Instructions that are programmed within the

MCR zone starting at the LBL instruction and ending at the ‘END MCR’ instruction are always evaluated as though the MCR zone is true, regardless of the true state of the “Start MCR” instruction.

Jump to Subroutine (JSR),

Subroutine (SBR), and Return (RET)

...

JSR

JUMP TO SUBROUTINE

SBR file number

SBR

SUBROUTINE

RET

RETURN

✓ ✓ ✓ ✓ ✓ ✓ ✓

The JSR, SBR, and RET instructions are used to direct the controller to execute a separate subroutine file within the ladder program and return to the instruction following the JSR instruction.

Note

If you use the SBR instruction, the SBR instruction must be the first instruction on the first rung in the program file that contains the subroutine.

Use a subroutine to store recurring sections of program logic that must be executed from several points within your application program. A subroutine saves memory because you program it only once.

Update critical I/O within subroutines using immediate input and/or output instructions (IIM, IOM), especially if your application calls for nested or relatively long subroutines. Otherwise, the controller does not update I/O until it reaches the end of the main program (after executing all subroutines).

Outputs controlled within a subroutine remain in their last state until the subroutine is executed again.

5–3

Nesting Subroutine Files

Nesting subroutines allows you to direct program flow from the main program to a subroutine and then on to another subroutine. The following rules apply when nesting subroutines:

You can nest up to eight levels of subroutines. If you are using an STI subroutine,

HSC interrupt subroutine, or user fault routine, you can nest subroutines up to three levels from each subroutine.

With Fixed and SLC 5/01 processors, you can nest subroutines up to four levels.

With SLC 5/02 and higher processors and MicroLogix 1000 controllers, you can nest subroutines up to eight levels. If you are using an STI subroutine, I/O event–driven interrupt subroutine, user fault routine, or HSC interrupt subroutine, you can nest subroutines up to three levels from each subroutine.

Main

Program

6

JSR

The following figure illustrates how subroutines may be nested.

Level 1

Subroutine File 6

Level 2

Subroutine File 7

SBR SBR

7

JSR

8

JSR

Level 3

Subroutine File 8

SBR

RET RET RET

Example of Nesting Subroutines to Level 3

An error occurs if more than the allowable levels of subroutines are called

(subroutine stack overflow) or if more returns are executed than there are call levels

(subroutine stack underflow).

Using JSR

When the JSR instruction is executed, the controller jumps to the subroutine instruction (SBR) at the beginning of the target subroutine file and resumes execution at that point. You cannot jump into any part of a subroutine except the first instruction in that file.

5–4

Program Flow Instructions

You must program each subroutine in its own program file by assigning a unique file number:

3–255 for SLC processors

4–15 for MicroLogix 1000 controllers

Fixed and SLC 5/01 specific – The JSR instruction should not be programmed in nested output branches. A compiler error will occur if a rung containing multiple outputs with conditional logic and a JSR instruction is encountered.

Using SBR

The target subroutine is identified by the file number that you entered in the JSR instruction. This instruction serves as a label or identifier for a program file as a regular subroutine file.

This instruction has no control bits. It is always evaluated as true. The instruction must be programmed as the first instruction of the first rung of a subroutine. Use of this instruction is optional; however, we recommend using it for clarity.

Using RET

Note

This output instruction marks the end of subroutine execution or the end of the subroutine file. It causes the controller to resume execution at the instruction following the JSR instruction. If a sequence of nested subroutines is involved, the instruction causes the processor to return program execution to the previous subroutine.

The rung containing the RET instruction may be conditional if this rung precedes the end of the subroutine. In this way, the controller omits the balance of a subroutine only if its rung condition is true.

Without an RET instruction, the END instruction (always present in the subroutine) automatically returns program execution to the instruction following the JSR instruction in your calling ladder file.

The RET instruction terminates execution of the DII subroutine (SLC 5/03 and higher processors), STI subroutine, I/O event-driven interrupt subroutine, and the user error handler when a SLC 5/02 or higher processor is used.

5–5

Master Control Reset (MCR)

(MCR)

✓ ✓ ✓ ✓ ✓ ✓ ✓

Use MCR instructions in pairs to create program zones that turn off all the non-retentive outputs in the zone. Rungs within the MCR zone are still scanned, but scan time is reduced due to the false state of non-retentive outputs.

If the MCR Rung that Starts the

Zone is:

True

False

Then the Controller:

Executes the rungs in the MCR zone based on each rung’s individual input condition (as if the zone did not exist).

Resets all non–retentive output instructions in the MCR zone regardless of each rung’s individual input conditions.

Note

MCR zones let you enable or inhibit segments of your program, such as for recipe applications.

When you program MCR instructions, note that:

You must end the zone with an unconditional MCR instruction.

You cannot nest one MCR zone within another.

Do not jump into an MCR zone. If the zone is false, jumping into it activates the zone.

Always place the MCR instruction as the last instruction in a rung.

The MCR instruction is not a substitute for a hard–wired master control relay that provides emergency stop capability. You still must install a hard–wired master control relay to provide emergency I/O power shutdown.

If you start instructions such as timers or counters in an MCR zone, instruction operation ceases when the zone is disabled. Re–program critical operations outside the zone if necessary.

5–6

Program Flow Instructions

SLC Processor Operation

Do not jump (JMP) into an MCR zone. Instructions that are programmed within the

MCR zone starting at the LBL instruction and ending at the ‘END MCR’ instruction are always evaluated as though the MCR zone is true, regardless of the true state of the “Start MCR” instruction. If the zone is false, jumping into it activates the zone from the LBL to the end of the zone.

If you start instructions such as timers or counters in an MCR zone, instruction operation ceases when the zone is disabled. Re-program critical operations outside the zone if necessary.

The TOF timer activates when placed inside of a false MCR zone.

The MCR instruction is not a substitute for a hard-wired master control relay.

We recommend that your programmable controller system include a hard-wired master control relay and emergency stop switches to provide I/O power shut down. Emergency stop switches can be monitored but should not be controlled by the ladder program. Wire these devices as described in the installation manual.

SLC 5/03 and and higher processors – When online and an unmatched MCR instruction exists in your program, the END instruction acts as the second unconditional MCR instruction and all of the rungs following the first MCR instruction execute via the current MCR instruction state.

You can save the program while online if unattended MCR instructions exist.

However, if you are offline and unattended MCR instructions exist, an error will occur.

Temporary End (TND)

(TND)

Output Instruction

Note

✓ ✓ ✓ ✓ ✓ ✓ ✓

This instruction, when its rung is true, stops the processor from scanning the rest of the program file, updates the I/O, and resumes scanning at rung 0 of the main program (file 2). If this instruction’s rung is false, the processor continues the scan until the next TND instruction or the END statement. Use this instruction to progressively debug a program, or conditionally omit the balance of your current program file or subroutines.

If you use this instruction inside a nested subroutine, execution of all nested subroutines is terminated.

MicroLogix 1000 controllers – Do not execute this instruction from the user error fault routine (file 3), high–speed counter interrupt routine (file 4), or selectable timed interrupt routine (file 5) because a fault will occur.

5–7

Suspend (SUS)

SUS

SUSPEND

Suspend ID

Output Instruction

✓ ✓ ✓ ✓ ✓ ✓ ✓

When this instruction is executed, it causes the processor to enter the Suspend Idle mode and stores the Suspend ID in word 7 (S:7) of the status file. All outputs are de-energized.

Use this instruction to trap and identify specific conditions for program debugging and system troubleshooting.

Entering Parameters

Enter a suspend ID number from –32,768 to

+

32,767 when you program the instruction.

When the SUS instruction is executed, the programmed ID as well as the program file ID from which the SUS instruction executed is placed in the system status file.

Immediate Input with Mask (IIM)

✓ ✓ ✓ ✓ ✓ ✓ ✓

IIM

IMMEDIATE INPUT w MASK

Slot

Mask

Input Instruction

Fixed andSLC 5/01 processors and MicroLogix 1000 controllers

This instruction allows you to update data prior to the normal input scan. When the

IIM instruction is enabled, the program scan is interrupted. Data from a specified

I/O slot is transferred through a mask to the input data file, making the data available to instructions following the IIM instruction in the ladder program.

IIM

IMMEDIATE INPUT w MASK

Slot

Mask

Length

For the mask, a 1 in an input’s bit position passes data from the source to the destination. A 0 inhibits data from passing from the source to the destination.

Input Instruction

SLC 5/03 and higher Processors

Entering Parameters

Slot – Specify the input slot number and the word number pertaining to the slot.

Word 0 of a slot need not be specified. Fixed and SLC 5/01 processors can have up to 8 words associated with the slot. The SLC 5/02 and higher processors can have up to 32 words associated with the slot (0–31).

5–8

Program Flow Instructions

For all MicroLogix 1000 controllers specify I1:0.0. For 16 I/O controllers, I1:0/0–9 are valid and I1:0/10–15 are considered unused inputs. (They do not physically exist.) For 32 I/O controllers, I1:0/0–15 and I1:1/0–3 are valid. Specify I1:1 if you want to immediately update the last four input bits.

Example

I:2

I:2.1

I:1

Inputs of slot 2, word 0

Inputs of slot 2, word 1

Inputs of slot 1, word 0

Mask – Specify a hexadecimal constant or register address.

Length – For SLC 5/03 and higher processors, this parameter is used to transfer more than one word per slot.

Immediate Output with Mask (IOM)

✓ ✓ ✓ ✓ ✓ ✓ ✓

IOM

IMMEDIATE OUTPUT w MASK

Slot

Mask

Output Instruction

Fixed and SLC 5/01 processors and MicroLogix 1000 controllers

IOM

IMMEDIATE OUTPUT w MASK

Slot

Mask

Length

This instruction allows you to update the outputs prior to the normal output scan.

When the IOM instruction is enabled, the program scan is interrupted to transfer data to a specified I/O slot through a mask. The program scan then resumes.

For the mask, a 1 in the output bit position passes data from the source to the destination. A 0 inhibits the data from passing from the source to the destination.

Output Instruction

SLC 5/03 and higher Processors

Entering Parameters

Slot – Specify the slot number and the word number pertaining to the slot. Word 0 of a slot need not be specified. Fixed and SLC 5/01 processors can have up to 8 words associated with the slot. The SLC 5/02 and higher processors can have up to

32 words associated with the slot (0–31).

For all MicroLogix 1000 controllers specify O0:0.0. For 16 I/O controllers,

O0:0/0–5 are valid and O0:0/6–15 are considered unused outputs. (They do not physically exist.) For 32 I/O controllers, O0:0/0–11 are valid and O0:0/12–15 are considered unused outputs.

5–9

Example

O:2

O:1

O:2.1

Outputs of slot 2, word 0

Outputs of slot 1, word 0

Outputs of slot 2, word 1

Mask – Specify a hexadecimal constant or register address.

Length – For SLC 5/03 and higher processors, this parameter is used to transfer more than one word per slot.

I/O Refresh (REF)

✓ ✓ ✓ ✓

Using an SLC 5/02 Processor

(REF)

Output Instruction

The REF instruction has no programming parameters. When it is evaluated as true, the program scan is interrupted to execute the I/O scan and service communication portions of the operating cycle (write outputs, service comms, read inputs). The scan then resumes at the instruction following the REF instruction.

You are not allowed to place a REF instruction in a DII subroutine, STI subroutine,

I/O subroutine, or user fault subroutine.

The watchdog and scan timers are reset when executing the REF instruction.

You must insure that an REF instruction is not placed inside a non-terminating program loop. Do not place an REF instruction inside a program loop unless the program is thoroughly analyzed.

5–10

Program Flow Instructions

Using SLC 5/03 and Higher Processors

REF

I/O REFRESH

Channel 0

Channel 1

Output Instruction

Operation of the REF instruction in the SLC 5/03 and higher processors is the same as the SLC 5/02 processor. However, when using the SLC 5/03 and higher processors, you can also select a specific communication channel to be serviced.

SLC 5/03 processor

– channel 0 is RS-232/DF1 Full-Duplex or Half-Duplex (master or slave),

DH-485, or ASCII

– channel 1 is DH-485

SLC 5/04 processor

– channel 0 is RS-232/DF1 Full-Duplex or Half-Duplex (master or slave),

DH-485, or ASCII

– channel 1 is DH

+

SLC 5/05 processor

– channel 0 is RS-232/DF1 Full-Duplex or Half-Duplex (master or slave),

DH-485, or ASCII

– channel 1 is Ethernet

5–11

Program Flow Control Instructions in the Paper Drilling

Machine Application Example

This section provides ladder rungs to demonstrate the use of program flow control instructions. The rungs are part of the paper drilling machine application example

described in appendix H. You will be adding to the main program in file 2. The

new rungs are needed to call the other subroutines containing the logic necessary to run the machine.

Adding File 2

Rung 2:3

This rung calls the drill sequence subroutine. This subroutine manages the operation of a drilling sequence and restarts the conveyer upon completion of the drilling sequence

| +JSR–––––––––––––––+ |

|–––––––––––––––––––––––––––––––––––––––––––––––––––––––––+JUMP TO SUBROUTINE+–|

| |SBR file number 6| |

| +––––––––––––––––––+ |

Rung 2:4

This rung calls the subroutine that tracks the amount of wear on the current drill bit.

| +JSR–––––––––––––––+ |

|–––––––––––––––––––––––––––––––––––––––––––––––––––––––––+JUMP TO SUBROUTINE+–|

| |SBR file number 7| |

| +––––––––––––––––––+ |

Rung 2:5

There is some initialization logic in the DII subroutine (file 4) that must be executed prior to the first DII interrupt. So this rung allows the DII to be initialized by jumping to the DII subroutine when the processor enters the RUN mode.

| 1st |

| Pass |

| S:1 +JSR–––––––––––––––+ |

|––––] [––––––––––––––––––––––––––––––––––––––––––––––––––+JUMP TO SUBROUTINE+–|

| 15 |SBR file number 4| |

| +––––––––––––––––––+ |

5–12

Application Specific Instructions

6

Application Specific Instructions

This chapter contains general information about the application specific instructions and explains how they function in your application program. Each of the instructions includes information on:

• what the instruction symbol looks like

• how to use the instruction

In addition, the last section contains an application example for a paper drilling machine that shows the application specific instructions in use.

Application Specific Instructions

Mnemonic

Instruction

Name

BSL and

BSR

SQO and

SQC

SQL

Bit Shift Left and

Bit Shift Right

Sequencer Output and Sequencer

Compare

Sequencer Load

Loads a bit of data into a bit array, shifts the pattern of data through the array, and unloads the last bit of data in the array. The BSL shifts data to the left and the BSR shifts data to the right.

Controls sequential machine operations by transferring 16-bit data through a mask to image addresses.

Captures referenced conditions by manually stepping the machine through its operating sequences.

6–4

6–7

6–13

About the Application Specific Instructions

These instructions simplify your ladder program by allowing you to use a single instruction or pair of instructions to perform common complex operations.

In this chapter you will find a general overview preceding groups of instructions.

Before you learn about the instructions in each of these groups, we suggest that you read the overview. This chapter contains the following overviews:

Bit Shift Instructions Overview

Sequencer Instructions Overview

6–1

Bit Shift Instructions Overview

The following general information applies to bit shift instructions.

Entering Parameters

Enter the following parameters when programming these instructions:

File is the address of the bit array you want to manipulate. You must use the file indicator (#) in the bit array address.

Control is the control element that stores the status byte of the instruction and the size of the array (in number of bits). Note that the control address should not be used for any other instruction.

The control element is shown below.

Word 0

Word 1

Word 2

15 13 11 10 00

EN DN ER UL Not used

Size of bit array (number of bits)

Reserved

Status bits of the control element may be addressed by mnemonic. They include:

Unload Bit UL (bit 10) stores the status of the bit exited from the array each time the instruction is enabled.

Error Bit ER (bit 11), when set, indicates the instruction detected an error such as entering a negative number for the length or position. Avoid using the output bit when this bit is set.

Done Bit DN (bit 13), when set, indicates the bit array has shifted one position.

Enable Bit EN (bit 15) is set on a false-to-true transition of the rung and indicates the instruction is enabled.

6–2

Note

Note

Application Specific Instructions

When the register shifts and input conditions go false, the enable, done, and error bits are reset.

Bit Address is the address of the source bit that the instruction inserts in the first (lowest) bit position (BSL) or the last (highest) bit position (BSR).

Length (size of bit array) is the number of bits in the bit array, up to 2048 bits.

A length value of 0 causes the input bit to be transferred to the UL bit.

For SLC processors, the length is 2048.

For MicroLogix 1000 controllers, this length is 1680.

A length value that points past the end of the programmed file causes a runtime major error to occur.

If you alter a length value with your ladder program, make certain that the altered value is valid.

The instruction invalidates all bits beyond the last bit in the array (as defined by the length) up to the next word boundary.

If a STring element address is used for the file parameter, the maximum length for

SLC 5/03 and higher processors is 672 bits. Additionally, STring element boundaries cannot be crossed.

Effects on Index Register S:24

The shift operation clears the index register S:24 to zero.

6–3

Bit Shift Left (BSL)

Bit Shift Right (BSR)

✓ ✓ ✓ ✓ ✓ ✓ ✓

BSL

BIT SHIFT LEFT

File

Control

#B3:1

R6:14

Bit Address I:22/12

Length 58

(EN)

(DN)

BSL and BSR are output instructions that load data into a bit array one bit at a time.

The data is shifted through the array, then unloaded one bit at a time.

BSR

BIT SHIFT RIGHT

File #B3:2

Control R6:15

Bit AddressI:23/06

Length 38

(EN)

(DN)

Output Instructions

Using BSL

When the rung goes from false-to-true, the processor sets the enable bit (EN bit 15) and the data block is shifted to the left (to a higher bit number) one bit position. The specified bit at the bit address is shifted into the first bit position. The last bit is shifted out of the array and stored in the unload bit (UL bit 10). The shift is completed immediately.

For wraparound operation, set the position of the bit address to the last bit of the array or to the UL bit, whichever applies.

6–4

Using BSR

Application Specific Instructions

The figure below illustrates how the Bit Shift Left instruction works.

BSL

BIT SHIFT LEFT

File #B3:1

Control R6:14

Bit Address I:22/12

Length 58

(EN)

(DN)

Source Bit

I:22/12

Data block is shifted one bit at a time from bit 16 to bit 73.

31 30 29 28

47 46 45 44

27 26 25 24

43 42 41 40

23 22 21 20

39 38 37 36

63 62 61 60

INVALID

59 58 57 56

73 72

55 54 53 52

71 70 69 68

19 18 17 16

35 34 33 32

51 50 49 48

67 66 65 64

58 Bit Array #B3:1

Unload Bit

(R6:14/10)

If you wish to shift more than one bit per scan, you must create a loop in your application using the JMP, LBL, and CTU instructions.

When the rung goes from false-to-true, the enable bit (EN bit 15) is set and the data block is shifted to the right (to a lower bit number) one bit position. The specified bit at the bit address is shifted into the last bit position. The first bit is shifted out of the array and stored in the unload bit (UL bit 10) in the status byte of the control element. The shift is completed immediately.

For wraparound operation, set the position of the bit address to the first bit of the array or to the UL bit, whichever applies.

6–5

6–6

The figure below illustrates how the Bit Shift Right instruction works.

BSR

BIT SHIFT RIGHT

File #B3:2

Control R6:15

Bit Address I:23/06

Length 38

(EN)

(DN)

Unload Bit

(R6:15/10)

47 46 45 44

63 62 61 60

43 42 41 40

59 58 57 56

INVALID

39 38 37 36

55 54 53 52

69 68

35 34 33 32

51 50 49 48

67 66 65 64

Data block is shifted one bit at a time from bit 69 to bit 32.

Source Bit

I:23/06

38 Bit Array

#B3:2

If you wish to shift more than one bit per scan, you must create a loop in your application using the JMP, LBL, and CTU instructions.

Application Specific Instructions

Sequencer Instructions Overview

The following general information applies to sequencer instructions.

Effects on Index Register S:24

The value present in the index register S:24 is overwritten when the sequencer instruction is true. The index register value will equal the position value of the instruction.

Applications Requiring More than 16-Bits

Note

Note

When your application requires more than 16-bits, use parallel multiple sequencer instructions.

Refer to appendix H for application examples using the sequencer instructions.

If a STring element address is used for the file parameter, the maximum length for

SLC 5/03 and higher processors is 41 words. Additionally, STring element boundaries cannot be crossed.

Sequencer Output (SQO)

Sequencer Compare (SQC)

✓ ✓ ✓ ✓ ✓ ✓ ✓

SQO

SEQUENCER OUTPUT

File #B10:1

Mask 0F0F

Dest

Control

Length

Position

O:14

R6:20

4

2

(EN)

(DN)

These instructions transfer 16-bit data to word addresses for the control of sequential machine operations.

SQC

SEQUENCER COMPARE

File #B10:11

Mask FFF0

Source

Control

Length

Position

I:03

R6:21

4

2

(EN)

(DN)

(FD)

Output Instructions

6–7

Entering Parameters

Enter the following parameters when programming these instructions:

File is the address of the sequencer file. You must use the file indicator (#) for this address.

Sequencer file data is used as follows:

SQO

SQC

Instruction Sequencer File Stores

Data for controlling outputs

Reference data for monitoring inputs

Note

Mask (SQO, SQC) is a hexadecimal code or the address of the mask word or file through which the instruction moves data. Set mask bits to pass data and reset mask bits to mask data. Use a mask word or file if you want to change the mask according to application requirements.

If the mask is a file, its length will be equal to the length of the sequencer file.

The two files track automatically.

Source is the address of the input word or file for a SQC from which the instruction obtains data for comparison to its sequencer file.

Destination is the address of the output word or file for a SQO to which the instruction moves data from its sequencer file.

You can address the mask, source, or destination of a sequencer instruction as a word or file. If you address it as a file (using file indicator #), the instruction automatically steps through the source, mask, or destination file.

Control (SQO, SQC) is the control structure that stores the status byte of the instruction, the length of the sequencer file, and the instantaneous position in the file. You should not use the control address for any other instruction.

Word 0

Word 1

Word 2

15 13 11 08 00

EN DN ER FD

Length of sequencer file

Position

6–8

Note

Application Specific Instructions

Status bits of the control structure include:

Found Bit FD (bit 08) – SQC only. When the status of all non-masked bits in the source address match those of the corresponding reference word, the FD bit is set. This bit is assessed each time the SQC instruction is evaluated while the rung is true.

Error Bit ER (bit 11) is set when the processor detects a negative position value, or a negative or zero length value. This results in a major error if not cleared before the END or TND instruction is executed.

Done Bit DN (bit 13) is set by the SQO or SQC instruction after it has operated on the last word in the sequencer file. It is reset on the next false-to-true rung transition after the rung goes false.

Enable EN (bit 15) is set by a false-to-true rung transition and indicates the SQO or SQC instruction is enabled.

Length is the number of steps of the sequencer file starting at position 1. The maximum number you can enter is 255 words (104 words when using

MicroLogix 1000 controllers). Position 0 is the startup position. The instruction resets (wraps) to position 1 at each cycle completion.

The address assigned for a sequencer file is step zero. Sequencer instructions use length

+

1 word of data table files for each file referenced in the instruction.

This applies to the source, mask, and/or destination if addressed as files.

A length value that points past the end of the programmed file causes a runtime major error to occur.

If you alter a length value with your ladder program, make certain that the altered value is valid.

Position is the word location or step in the sequencer file from/to which the instruction moves data.

A position value that points past the end of the programmed file causes a runtime major error to occur. If you alter a position value with your ladder

program, make certain that the altered value is valid.

Application Note: You may use the reset (RES) instruction to reset a sequencer.

All control bits (except FD) will be reset to zero. The Position will also be set to zero. Program the address of your control register in the RES (e.g.,R6:0).

6–9

Using SQO

This output instruction steps through the sequencer file whose bits have been set to control various output devices.

When the rung goes from false-to-true, the instruction increments to the next step

(word) in the sequencer file. Data stored there is transferred through a mask to the destination address specified in the instruction. Current data is written to the corresponding destination word every scan that the rung remains true.

The done bit is set when the last word of the sequencer file is transferred. On the next false-to-true rung transition, the instruction resets the position to step one.

If the position is equal to zero at startup, when you switch the processor from the program mode to the run mode instruction operation depends on whether the rung is true or false on the first scan.

If true, the instruction transfers the value in step zero.

If false, the instruction waits for the first rung transition from false-to-true and transfers the value in step one.

The bits mask data when reset and pass data when set. The instruction will not change the value in the destination word unless you set mask bits. The mask can be fixed or variable. It will be variable if you enter an element address or a file address for changing the mask with each step.

6–10

Application Specific Instructions

The following figure indicates how the SQO instruction works.

SQO

SEQUENCER OUTPUT

File #B10:1

Mask

Dest

Control

Length

Position

0F0F

O:14.0

R6:20

4

2

(EN)

(DN)

Destination O:14.0

15 8 7 0

0000 0101 0000 1010

Mask Value 0F0F

15 8 7 0

0000 1111 0000 1111

Sequencer Output File #B10:1

Word

B10:1

2

3

4

0000 0000 0000 0000

1010 0010 1111 0101

1111 0101 0100 1010

0101 0101 0101 0101

5

0000 1111 0000 1111

Step

0

1

2

3

4

Current Step

External Outputs

Associated with O:14

05

06

07

08

09

10

00

01

02

03

04

11

12

13

14

15

ON

ON

ON

ON

Using SQC

When the status of all non-masked bits in the source word match those of the corresponding reference word, the instruction sets the found bit (FD) in the control word. Otherwise, the found bit (FD) is cleared.

The bits mask data when reset and pass data when set.

The mask can be fixed or variable. If you enter a hexadecimal code, it is fixed. If you enter an element address or a file address for changing the mask with each step, it is variable.

When the rung goes from false-to-true, the instruction increments to the next step

(word) in the sequencer file. Data stored there is transferred through a mask and compared against the source data for equality. If the source data equals the reference data, the FD bit is set in the SQC’s control counter. Current data is compared against the source every scan that the rung evaluates as true.

6–11

6–12

Applications of the SQC instruction include machine diagnostics. The following figure explains how the SQC instruction works.

SQC

SEQUENCER COMPARE

File

Mask

Source

Control

Length

Position

#B10:11

FFF0

I:3.0

R6:21

4

2

(EN)

(DN)

(FD)

Input Word I:3.0

0010 0100 1001 1101

Mask Value FFF0

1111 1111 1111 0000

Sequencer Ref File #B10:11

Word

B10:11

12

13

14

15

0010 0100 1001 0000

Step

0

3

4

1

2

SQC FD bit is set when the instruction detects that an input word matches (through mask) its corresponding reference word.

The FD bit R6:21/FD is set in this example, since the input word matches the sequencer reference value using the mask value.

Application Specific Instructions

Sequencer Load (SQL)

✓ ✓ ✓ ✓ ✓

SQL

SEQUENCER LOAD

File

Source

Control

Length

Position

Output Instruction

(EN)

(DN)

The SQL instruction stores 16-bit data into a sequencer load file at each step of sequencer operation. The source of this data can be an I/O or storage word address, a file address, or a constant.

Entering Parameters

Note

Note

Enter the following parameters when programming this instruction:

File is the address of the sequencer file. You must use the file indicator (#) for this address.

Source can be a word address, file address, or a constant (–32768 to 32767).

If the source is a file address, the file length equals the length of the sequencer load file. The two files will step automatically, per the position value.

Length is the number of steps of the sequencer load file (and also of the source if the source is a file address), starting at position 1. The maximum number you can enter is 255 words (104 words when using MicroLogix 1000 controllers).

Position 0 is the startup position. The instruction resets (wraps) to position 1 at each cycle completion.

The position address assigned for a sequencer file is step zero. Sequencer instructions use length plus one word of data for each file referenced in the instruction. This applies to the source if addressed as a file.

A length value that points past the end of the programmed file causes a runtime major error to occur.

If you alter a length value with your ladder program, make certain that the altered value is valid.

Position is the word location or step in the sequencer file to which data is moved.

A position value that points past the end of the programmed file causes a runtime major error to occur.

If you alter a position value with your ladder program, make certain that the altered value is valid.

6–13

6–14

Control is a control file address. The status bits, length value, and position value are stored in this element. Do not use the control file address for any other instruction.

The control element is shown below:

Word 0

Word 1

Word 2

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

EN DN ER

Length

Position

Status bits of the control structure include:

Error Bit ER (bit 11) is set when the processor detects a negative position value, or a negative or zero length value.

For SLC processors, this results in a major error if not cleared before the

END or TND instruction is executed.

For MicroLogix 1000 controllers, when the ER bit is set the minor error bit

(S5:2) is also set. Both bits must be cleared.

Done Bit DN (bit 13) is set after the instruction has operated on the last word in the sequencer load file. It is reset on the next false-to-true rung transition after the rung goes false.

Enable Bit EN (bit 15) is set on a false-to-true transition of the SQL rung and reset on a true-to-false transition.

Operation

Application Specific Instructions

Instruction parameters have been programmed in the SQL instruction shown below.

Input word I:1.0 is the source. Data in this word is loaded into integer file #N7:30 by the sequencer load instruction.

SQL

SEQUENCER LOAD

File

Source

Control

Length

Position

#N7:30

I:1.0

R6:4

4

2

(EN)

(DN)

Source I:1.0

15 8 7 0

0000 0101 0000 1010

Sequencer Load File #N7:30

Word

N7:30

31

32

33

0000 0000 0000 0000

1010 0010 1111 0101

0000 0101 0000 1010

0000 0000 0000 0000

34

0000 0000 0000 0000

Step

0

1

2

3

4

Current Step

External Inputs

Associated with I:1.0

05

06

07

08

09

10

00

01

02

03

04

11

12

13

14

15

ON

ON

ON

ON

When rung conditions change from false-to-true, the SQL enable bit (EN) is set.

The control element R6:4 increments to the next position in the sequencer file, and loads the contents of source I:1.0 into this location. The SQL instruction continues to load the current data into this location each scan that the rung remains true.

When the rung goes false, the enable bit (EN) is reset.

The instruction loads data into a new file element at each false–to–true transition of the rung. When step 4 is completed, the done bit (DN) is set. Operation cycles to position 1 at the next false–to–true transition of the rung after position 4.

If the source were a file address such as #N7:40, files #N7:40 and #N7:30 would both have a length of 5 (0–4) and would track through the steps together per the position value.

6–15

Application Specific Instructions in the Paper Drilling

Machine Application Example

This section provides ladder rungs to demonstrate the use of application specific instructions. The rungs are part of the paper drilling machine application example

described in appendix H. You will begin a subroutine in file 4.

This portion of the subroutine tells the conveyor where to stop to allow a hole to be drilled. Sequencer instructions are used to store conveyor stopping positions and to load the “next”stopping position into the DII Preset Word. (The Discrete Input

Interrupt, DII, is used to count pulses coming from the encoder that is attached to the conveyor.) The stop positions are different for each hole pattern (3 hole, 5 hole,

7 hole), so separate sequencers are used to store and access each of the three hole patterns.

OPERATOR PANEL

Start I:1/6 Stop I:1/7

Thumbwheel for

Thickness in 1/4”

Change Drill Soon

O:3/4

Drill Change Reset

Change Drill Now

O:3/6

5 Hole

3 Hole 7 Hole

I:1/11–I:1/14

(Keyswitch)

I:1/8

I:1/9–I:1/10

Hole Selector

Switch

Drill

Drilled Holes

6–16

Application Specific Instructions

Rung 4:0

This rung resets the hole count sequencers each time the processor enters the

RUN mode. This ensures that the first preset value is loaded into the DII preset at each entry into the run mode.

| 1st 3 hole |

| Pass preset |

| sequencer |

| +INT––––––––––––––––––––+ S:1 R6:4 |

|–+INTERRUPT SUBROUTINE +––––] [––––––––––––––––––––––––––––––+–––(RES)––––+–|

| +–––––––––––––––––––––––+ 15 | | |

| | 5 hole | |

| | preset | |

| | sequencer | |

| | R6:5 | |

| +–––(RES)––––+ |

| | | |

| | 7 hole | |

| | preset | |

| | sequencer | |

| | R6:6 | |

| +–––(RES)––––+ |

| |

Rung 4:2

This rung keeps track of the hole number that is being drilled and loads the next correct DII preset based on the hole count. This rung is only active when the ”hole selector switch” is in the ”3–hole” position. The sequencer uses step

0 as a null step upon reset. It uses the last step as a ”go forever” in anticipation of the ”end of manual”. Moving a 0 into S:49 tells the DII to trigger an interrupt when the trailing edge of the current book is detected.

| hole |hole 3 hole |

| selector |selector preset |

| switch |switch sequencer |

| bit 0 |bit 1 |

| I:1.0 I:1.0 +SQO–––––––––––––––+ |

|––––]/[––––––––] [–––––––––+––––––––––––––––––––––+SEQUENCER OUTPUT +–(EN)–+–|

| 9 10 | |File #N10:0+–(DN) | |

| | |Mask FFFF| | |

| | |Dest S:50| | |

| | |Control R6:4| | |

| | |Length 4| | |

| | |Position 0| | |

| | +––––––––––––––––––+ | |

| | | |

| | | |

| | force the | |

| | sequencer | |

| | to increment | |

| | on next scan | |

| | R6:4 | |

| +–––––––––––––––––––––––––(U)––––––––––––––––––––+ |

| | EN | |

6–17

6–18

Rung 4:3

This rung is identical to the previous rung except that it is only active when the ”hole selector switch” is in the ”5–hole” position.

| hole |hole 5 hole |

| selector |selector preset |

| switch |switch sequencer |

| bit 0 |bit 1 |

| I:1.0 I:1.0 +SQO–––––––––––––––+ |

|––––] [––––––––]/[–––––––––+––––––––––––––––––––––+SEQUENCER OUTPUT +–(EN)–+–|

| 9 10 | |File #N10:5+–(DN) | |

| | |Mask FFFF| | |

| | |Dest S:50| | |

| | |Control R6:5| | |

| | |Length 6| | |

| | |Position 0| | |

| | +––––––––––––––––––+ | |

| | | |

| | force the | |

| | sequencer | |

| | to increment | |

| | on the next scan | |

| | R6:5 | |

| +–––––––––––––––––––––––––(U)––––––––––––––––––––+ |

| | EN | |

Rung 4:4

This rung is identical to the 2 previous rungs except that it is only active when the ”hole selector switch” is in the ”7–hole” position.

| hole |hole 7 hole |

| selector |selector preset |

| switch |switch sequencer |

| bit 0 |bit 1 |

| I:1.0 I:1.0 +SQO–––––––––––––––+ |

|––––] [––––––––] [–––––––––+––––––––––––––––––––––+SEQUENCER OUTPUT +–(EN)–+–|

| 9 10 | |File #N10:12+–(DN) | |

| | |Mask FFFF| | |

| | |Dest S:50| | |

| | |Control R6:6| | |

| | |Length 8| | |

| | |Position 0| | |

| | +––––––––––––––––––+ | |

| | force the | |

| | sequencer | |

| | to increment | |

| | on the next scan | |

| | R6:6 | |

| +–––––––––––––––––––––––––(U)––––––––––––––––––––+ |

| | EN | |

Using High-Speed Counter Instructions

7

Using High-Speed Counter

Instructions

Note

This chapter contains general information about the high-speed counter instructions and explains how they function in your application program. Each of the instructions includes information on:

• what the instruction symbol looks like

• how to use the instruction

In addition, the last section contains an application example for a paper drilling machine that shows the high-speed counter instructions in use.

The high-speed counter instruction is only supported by the SLC 500 Fixed and

MicroLogix 1000 Controllers. The SLC modular controllers (SLC 5/01 thru

SLC 5/05) do not have an on-board high-speed counter.

High-Speed Counter Instructions

Mnemonic

HSC

HSL

RES

RAC

HSE

HSD

OTE

Name

High-Speed Counter

High-Speed Counter

Load

High-Speed Counter

Reset

High-Speed Counter

Reset Accumulator

High-Speed Counter

Interrupt Enable

High-Speed Counter

Interrupt Disable

Update High-Speed

Counter Image

Accumulator

Purpose

Applies configuration to the high-speed counter hardware, updates the image accumulator, enables counting when the HSC is true, and disables counting when the HSC rung is false.

Configures the low and high presets, the output patterns, and mask bit patterns.

Writes a zero to the hardware accumulator and image accumulator.

Writes the value specified to the hardware accumulator and image accumulator.

Enables or disables execution of the high-speed counter interrupt subroutine when a high preset, low preset, overflow, or underflow is reached.

Provides you with real-time access to the hardware accumulator value by updating the image accumulator.

Page

7–6

7–19

7–22

7–23

7–24

7–25

7–1

About the High-Speed Counter Instructions

The high-speed counter instructions used in your ladder program configure, control, and monitor the controllers’ hardware counter. The hardware counter’s accumulator increments or decrements in response to external input signals. When the high-speed counter is enabled, data table counter C5:0 is used by the ladder program for monitoring the high-speed counter accumulator and status. The high-speed counter operates independent of the controller scan.

When using the high-speed counter, make sure you adjust your input filters accordingly.

Before you learn about these instructions, read the overview that follows on the next page.

7–2

Using High-Speed Counter Instructions

High-Speed Counter Instructions Overview

Use the high-speed counter instructions to detect and store narrow (fast) pulses, and to initiate other control operations based on preset values. These control operations include the automatic and immediate execution of the high-speed counter interrupt routine (file 4) and the immediate update of outputs based on a source and mask pattern you set.

Counter Data File Elements

The high-speed counter instructions reference counter C5:0. The HSC instruction is fixed at C5:0. It is comprised of three words. Word 0 is the status word, containing

15 status bits. Word 1 is the preset value. Word 2 is the accumulated value. Once assigned to the HSC instruction, C5:0 is not available as an address for any other counter instructions.

Word 0

Word 1

Word 2

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

CU CD DN OV UN UA HP LP IV IN IH IL PE LS IE

Preset Value

Accumulator Value

Status

Word

CU = Counter Up Enable Bit

CD = Counter Down Enable Bit

DN = High Preset Reached Bit

OV = Overflow Occurred Bit

UN = Underflow Occurred Bit

UA = Update High-Speed Counter Accumulator Bit

HP = Accumulator

High Preset Bit

LP = Accumulator

Low Preset Bit

IV = Overflow Caused High-Speed Counter Interrupt Bit

IN = Underflow Caused High-Speed Counter Interrupt Bit

IH = High Preset Reached Caused Interrupt Bit

IL = Low Preset Reached Caused Interrupt Bit

PE = High-Speed Counter Interrupt Pending Bit

LS = High-Speed Counter Interrupt Lost Bit

IE = High-Speed Counter Interrupt Enable Bit

To access these bits, place your cursor on the instruction and press [F8], Data Monitor.

Counter preset and accumulated values are stored as signed integers.

7–3

Using Status Bits

Note

The high-speed counter status bits are retentive. When the high-speed counter is first configured, bits 3–7, 14, and 15 are reset and bit 1 (IE) is set.

Counter Up Enable Bit CU (bit 15) is used with all of the high-speed counter types. If the HSC instruction is true, the CU bit is set to one. If the HSC instruction is false, the CU bit is set to zero. Do not write to this bit.

Counter Down Enable Bit CD (bit 14) is used with the Bidirectional

Counters (modes 3–8). If the HSC instruction is true, the CD bit is set to one.

If the HSC instruction is false, the CD bit is set to zero. Do not write to this bit.

High Preset Reached Bit DN (bit 13) For the Up Counters (modes 1 and 2), this bit is an edge triggered latch bit. This bit is set when the high preset is reached. You can reset this bit with an OTU instruction or by executing an

RAC or RES instruction.

The DN bit is a reserved bit for all other Counter options (modes 3–8).

Overflow Occurred Bit OV (bit 12) For the Up Counters (modes 1 and 2), this bit is set by the controller when the high preset is reached if the DN bit is set.

For the Bidirectional Counters (modes 3–8), the OV bit is set by the controller after the hardware accumulator transitions from 32,767 to –32,768. You can reset this bit with an OTU instruction or by executing an RAC or RES instruction for both the up and bidirectional counters.

Underflow Occurred Bit UN (bit 11) is a reserved bit for the Up Counters

(modes 1 and 2). Do not write to this bit.

For the Bidirectional Counters (modes 3–8), the UN bit is set by the controller when the hardware accumulator transitions from –32,768 to

+

32,767. You can reset this bit with an OTU instruction or by executing an RAC or RES instruction.

Update High-Speed Counter Accumulator Bit UA (bit 10) is used with an

OTE instruction to update the instruction image accumulator value with the hardware accumulator value. (The HSC instruction also performs this operation each time the rung with the HSC instruction is evaluated as true.)

Accumulator

High Preset Bit HP (bit 9) is a reserved bit for all Up

Counters (modes 1 and 2).

For the Bidirectional Counters (modes 3–8), if the hardware accumulator becomes greater than or equal to the high preset, the HP bit is set. If the hardware accumulator becomes less than the high preset, the HP bit is reset by the controller. Do not write to this bit. (Exception – you can set or reset this bit

during the initial configuration of the HSC instruction. See page 7–6 for more

information.)

7–4

Using High-Speed Counter Instructions

Accumulator

Low Preset Bit LP (bit 8) is a reserved bit for all Up

Counters.

For the Bidirectional Counters, if the hardware accumulator becomes less than or equal to the low preset, the LP bit is set by the controller. If the hardware accumulator becomes greater than the low preset, the LP bit is reset by the controller. Do not write to this bit. (Exception – you can set or reset this bit

during the initial configuration of the HSC instruction. See page 7–6 for more

information.)

Overflow Caused High-Speed Counter Interrupt Bit IV (bit 7) is set to identify an overflow as the cause for the execution of the high-speed counter interrupt routine. The IN, IH, and IL bits are reset by the controller when the IV bit is set. Examine this bit at the start of the high-speed counter interrupt routine (file 4) to determine why the interrupt occurred.

Underflow caused High-Speed Counter Interrupt Bit IN (bit 6) is set to identify an underflow as the cause for the execution of the high-speed counter interrupt routine. The IV, IH, and IL bits are reset by the controller when the IN bit is set. Examine this bit at the start of the high-speed counter interrupt routine (file 4) to determine why the interrupt occurred.

High Preset Reached Caused High-Speed Counter Interrupt Bit IH (bit 5) is set to identify a high preset reached as the cause for the execution of the high-speed counter interrupt routine. The IV, IN, and IL bits are reset by the controller when the IH bit is set. Examine this bit at the start of the high-speed counter interrupt routine (file 4) to determine why the interrupt occurred.

Low Preset Reached Caused High-Speed Counter Interrupt Bit IL (bit 4) is set to identify a low preset reached as the cause for the execution of the high-speed counter interrupt routine. The IV, IN, and IH bits are reset by the controller when the IL bit is set. Examine this bit at the start of the high-speed counter interrupt routine (file 4) to determine why the interrupt occurred.

High-Speed Counter Interrupt Pending Bit PE (bit 3) is set to indicate that a high-speed counter interrupt is waiting for execution. This bit is cleared by the controller when the high-speed counter interrupt routine begins executing.

This bit is reset if an RAC or RES instruction is executed. Do not write to this bit.

High-Speed Counter Interrupt Lost Bit LS (bit 2) is set if an high-speed counter interrupt occurs while the PE bit is set. You can reset this bit with an

OTU instruction or by executing an RAC or RES instruction.

High-Speed Counter Interrupt Enable Bit IE (bit 1) is set when the high-speed counter interrupt is enabled to run when an high-speed counter interrupt condition occurs. It is reset when the interrupt is disabled. This bit is also set when the high-speed counter is first configured. Do not write to this bit.

7–5

High-Speed Counter (HSC)

HSC

HIGH SPEED COUNTER

Type

Counter

High Preset

Accum

C5:0

0

0

✓ ✓

(CU)

(CD)

(DN)

Use this instruction to configure the high-speed counter. Only one HSC instruction can be used in a program. The high-speed counter is not operational until the first true execution of the HSC instruction. When the HSC rung is false, the high-speed counter is disabled from counting, but all other HSC features are operational.

The Counter address of the HSC instruction is fixed at C5:0. After the HSC is configured, the image accumulator (C5:0.ACC) is updated with the current hardware accumulator value every time the HSC instruction is evaluated as true or false.

Entering Parameters

Enter the following parameters when programming this instruction:

Type indicates the counter selected. Refer to page 7–7 for making your

high-speed counter selection. Each type is available with reset and hold functionality.

High Preset is the accumulated value that triggers a user-specified action such as updating outputs or generating an high-speed counter interrupt.

Accumulator is the number of accumulated counts.

The following terminology is used in the following table to indicate the status of counting:

Up

– increments by 1 when the input energizes (edge).

Down

– decrements by 1 when the input energizes (edge).

Reset

– resets the accumulator to zero when the input energizes (edge).

Hold – disables the high-speed counter from counting while the input is energized (level).

Count – increments or decrements by 1 when the input energizes (edge).

Direction – allows up counts when the input is de-energized and down counts while the input is energized (level).

A – input pulse in an incremental (quadrature) encoder (edge/level).

B – input pulse in an incremental (quadrature) encoder (edge/level).

Z – reset pulse in an incremental (quadrature) encoder (edge/level).

– the signal is active on the rising edge only (off to on).

7–6

Using High-Speed Counter Instructions

Up

and Function Key

Up

(with reset and hold)

Pulse and direction

Pulse and direction

(with external reset and hold)

Up and down

The table below lists the function key you press to choose the type of high-speed counter you want.

Input Terminal Used

I/1 I/2 I/3

Up and down

(with external reset and hold)

Encoder

Encoder

(with external reset and hold)

H -Speed Coun er Func onal

Up Counter operation uses a single-ended input.

Up Counter operation uses a single input with external reset and hold inputs.

Bidirectional operation uses both pulse and direction inputs.

Bidirectional operation uses both pulse and direction inputs with external reset and hold inputs.

Bidirectional operation uses both up and down direction inputs.

Bidirectional operation uses both up and down pulse inputs with external reset and hold inputs.

Bidirectional operation uses quadrature encoder inputs.

Bidirectional operation uses both quadrature encoder inputs with external reset and hold inputs.

Up

I/0

Up

Count

Count

Up

Up

A

A

Not Used Not Used Not Used

Not Used Reset

Direction Not Used Not Used

Direction

Reset

Down

Down

B

B

Not Used Not Used

Reset

Not Used Not Used

Z

Hold

Hold

Hold

Hold

One difference between Up Counters and Bidirectional Counters is that for

Bidirectional Counters the accumulator and preset values are not changed by the high-speed counter when the presets are reached. The RAC and HSL instructions must be used for this function. The Up Counters clear the accumulator and re-load the high preset values whenever the preset is reached.

7–7

Using the Up Counter and the Up Counter with Reset and Hold

Up counters are used when the parameter being measured is uni-directional, such as material being fed into a machine or as a tachometer recording the number of pulses over a given time period.

Both types of Up Counters operate identically, except that the Up Counter with reset and hold uses external inputs 2 and 3.

For the Up Counter, each Off-to-On state change of input I:0/0 adds 1 to the accumulator until the high preset is reached. The accumulator is then automatically reset to zero. The Up Counter operates in the 0 to

+

32,767 range inclusive and can be reset to zero using the Reset (RES) instruction.

When the HSC instruction is first executed true, the:

Accumulator C5:0.ACC is loaded to the hardware accumulator.

High preset C5:0.PRE is loaded to the hardware high preset.

Operation

If you move data to the high preset without using the HSL instruction (with a MOV) after the high-speed counter has been configured, the data is loaded to the instruction image but is not loaded to the hardware. The modified high preset value is not loaded to the hardware until the existing hardware high preset is reached, or an RAC or RES instruction is executed.

The high preset value loaded to the hardware must be between 1 and 32,767 inclusive or an error

INVALID PRESETs LOADED TO HIGH SPEED COUNTER

(37H) occurs. Any value between –32,768 and

+

32,767 inclusive can be loaded to the hardware accumulator.

The Following Condition

A high preset is reached

Occurs when

either the hardware accumulator transitions from the hardware high preset –1 to the hardware high preset, or the hardware accumulator is loaded with a value greater than or equal to the hardware high preset, or the hardware high preset is loaded with a value that is less than or equal to the hardware accumulator.

7–8

Using High-Speed Counter Instructions

When a high preset is reached, no counts are lost.

Hardware and instruction accumulators are reset.

Instruction high preset is loaded to the hardware high preset.

If the DN bit is not set, the DN bit is set. The IH bit is also set and the IL, IV, and IN bits are reset.

If the DN bit is already set, the OV bit is set. The IV bit is also set and the IL,

IV and IN bits are reset.

High-speed counter interrupt file (program file 4) is executed if the interrupt is enabled. The IH bit is set and the IL, IV, and IN bits are set.

If the DN bit is already set when a high preset is reached, the OV bit is set.

The following tables summarize what the input state must be for the corresponding high-speed counter action to occur:

Up Counter

Input Count

(I/O)

Turning

Off-to-On

NA

Input

Direction

(I/1)

NA

NA

NA (Not Applicable)

NA

NA

Input State

Input Reset

(I/2)

Input Hold

(I/3)

NA

NA

HSC Rung

True

False

H -Speed

Counter Action

Count Up

Hold Count

7–9

Up Counter with Reset and Hold

Input Count

(I/O)

Turning

Off-to-On

Input

Direction

(I/1)

NA

NA NA

NA

Off, On, or

Turning Off

NA

NA (Not Applicable)

NA

NA

NA

Input state

Input Reset

(I/2)

Off, On, or

Turning Off

Off, On, or

Turning Off

Off, On, or

Turning Off

Off, On, or

Turning Off

Turning On

Input Hold

Off

On

NA

NA

NA

(I/3)

HSC Rung

True

NA

False

NA

NA

H -Speed

Counter Action

Count Up

Hold Count

Hold Count

Hold Count

Reset to 0

Using the Bidirectional Counter and the Bidirectional Counter with Reset and Hold

Bidirectional counters are used when the parameter being measured can either increment or decrement. For example, a package entering and leaving a storage bin is counted to regulate flow through the area.

The Bidirectional Counters operate identically except for the operation of inputs 1 and 0. For the Pulse and Direction type, input 0 provides the pulse and input 1 provides the direction. For the Up and Down type, input 0 provides the Up count and input 1 provides the Down count. Both types are available with and without

reset and hold. Refer to page 7–7 for more information regarding Bidirectional

Counter types.

For the Bidirectional Counters, both high and low presets are used. The low preset value must be less than the high preset value or an error

INVALID PRESETs

LOADED TO HIGH SPEED COUNTER

(37H) occurs. Hardware low preset is set to

–32,768.

Bidirectional Counters operate in the –32,768 to

+

32,767 range inclusive and can be reset to zero using the Reset (RES) instruction.

7–10

Operation

Using High-Speed Counter Instructions

When the HSC instruction is first executed true, the:

Instruction accumulator is loaded to the hardware accumulator.

Instruction high preset is loaded to the hardware high preset.

After the first true HSC instruction execution, data can only be transferred to the hardware accumulator via an RES or RAC instruction, or to the hardware high and low presets via the HSL instruction.

Any instruction accumulator value between –32,768 and

+

32,767 inclusive can be loaded to the hardware.

The Following Condition

A high preset is reached

Occurs when

either the hardware accumulator transitions from the hardware high preset –1 to the hardware high preset, or the hardware accumulator is loaded with a value greater than or equal to the hardware high preset, or the hardware high preset is loaded with a value that is less than or equal to the hardware accumulator.

When a high preset is reached, the:

HP bit is set.

High-speed counter interrupt file (program file 4) is executed if the interrupt is enabled. The IH bit is set and the IL, IV, and IN bits are reset.

Unlike the Up Counters, the accumulator value does not get reset and the high preset value does not get loaded from the image to the hardware high preset register.

The Following Condition

A low preset is reached

Occurs when

either the hardware accumulator transitions from the hardware low preset +1 to the hardware low preset, or the hardware accumulator is loaded with a value less than or equal to the hardware low preset, or the hardware low preset is loaded with a value that is greater than or equal to the hardware accumulator.

7–11

When the low preset is reached, the:

LP bit is set.

High-speed counter interrupt file (program file 4) is executed if the interrupt is enabled. The IL bit is set and the IH, IV, and IN bits are reset.

An overflow occurs when the hardware accumulator transitions from

+

32,767 to

–32,768. When an overflow occurs, the:

OV bit is set.

High-speed counter interrupt file (program file 4) is executed if the interrupt is enabled. The IV bit is set and the IH, IL, and IN bits are reset.

An underflow occurs when the hardware accumulator transitions from –32,768 to

+

32,767. When an underflow occurs, the:

UN bit is set.

High-speed counter interrupt file (program file 4) is executed if the interrupt is enabled. The IN bit is set and the IH, IL, and IV bits are reset.

The following tables summarize what the input state must be for the corresponding high-speed counter action to occur:

Bidirectional Counter (Pulse/direction)

Input Count

(I/0)

Turning

Off-to-On

Turning

Off-to-On

NA

Input

Direction

(I/1)

Off

On

NA

NA (Not Applicable)

NA

NA

NA

Input State

Input Reset

(I/2)

Input Hold

(I/3)

NA

NA

NA

HSC Rung

H -Speed

Counter Action

True

True

False

Count Up

Count Down

Hold Count

7–12

Using High-Speed Counter Instructions

Bidirectional Counter with Reset and Hold (Pulse/direction)

Input Count

(I/0)

Input

Direction

(I/1)

Input State

Input Reset

(I/2)

Input Hold

(I/3)

Turning

Off-to-On

Turning

Off-to-On

NA

NA

Off, On, or

Turning Off

NA

Off

On

NA

NA

NA

NA

Off, On, or

Turning Off

Off, On, or

Turning Off

Off, On, or

Turning Off

Off, On, or

Turning Off

Off, On, or

Turning Off

Turning On

Off

Off

NA

On

NA

NA

HSC Rung

True

True

False

NA

NA

NA

H -Speed

Counter Action

Count Up

Count Down

Hold Count

Hold Count

Hold Count

Reset to 0

NA (Not Applicable)

Bidirectional Counter (Up/down count)

Input Up

Count

(I/0)

Turning

Off-to-On

Off, On, or

Turning Off

NA

Input State

Input Down

Count

(I/1)

Off, On, or

Turning Off

Turning

Off-to-On

NA

HSC Rung

True

True

False

H -Speed

Counter Action

Count Up

Count Down

Hold Count

NA (Not Applicable)

7–13

Bidirectional Counter with Reset and Hold (Up/down count)

Input Up

Count

(I/0)

Turning

Off-to-On

Off, On, or

Turning Off

NA

NA

Off, On, or

Turning Off

NA

Input Down

Count

(I/1)

Off, On, or

Turning Off

Turning

Off-to-On

NA

NA

Off, On, or

Turning Off

NA

Input State

Input Reset

(I/2)

Off, On, or

Turning Off

Off, On, or

Turning Off

Off, On, or

Turning Off

Off, On, or

Turning Off

Off, On, or

Turning Off

Turning On

Input Hold

(I/3)

Off

Off

NA

On

NA

NA

HSC Rung

True

True

False

NA

NA

NA

H -Speed

Counter Action

Count Up

Count Down

Hold Count

Hold Count

Hold Count

Reset to 0

NA (Not Applicable)

When up and down input pulses occur simultaneously, the high-speed counter counts up, then down.

7–14

Using High-Speed Counter Instructions

Using the Bidirectional Counter with Reset and Hold with a Quadrature

Encoder

The Quadrature Encoder is used for determining direction of rotation and position for rotating, such as a lathe. The Bidirectional Counter counts the rotation of the

Quadrature Encoder.

Bidirectional Counters operate in the –32,768 to

+

32,767 range inclusive and can be reset to zero using the reset (RES) instruction. The following figure shows a quadrature encoder connected to inputs 0, 1, and 2. The count direction is determined by the phase angle between A and B. If A leads B, the counter increments. If B leads A, the counter decrements.

The counter can be reset using the Z input. The Z outputs from the encoders typically provide one pulse per revolution.

A

B

Quadrature Encoder

Forward Rotation

Z

(Reset input)

Input 0

Input 1

Input 2

Reverse Rotation

A

B

Count

1 2 3 2 1

7–15

Operation

For the Bidirectional Counters, both high and low presets are used. The low preset value must be less than the high preset value or an error

INVALID PRESETs

LOADED TO HIGH SPEED COUNTER

(37H) occurs.

When the HSC instruction is first executed true, the:

Instruction accumulator is loaded to the hardware accumulator.

Instruction high preset is loaded to the hardware high preset.

Any instruction accumulator value between –32,768 and

+

32,767 inclusive can be loaded to the hardware.

After the first true HSC instruction execution, data can only be transferred to the hardware accumulator via an RES or RAC instruction, or to the hardware high and low presets via the HSL instruction.

The Following Condition

A high preset is reached

Occurs when

either the hardware accumulator transitions from the hardware high preset –1 to the hardware high preset, or the hardware accumulator is loaded with a value greater than or equal to the hardware high preset, or the hardware high preset is loaded with a value that is less than or equal to the hardware accumulator.

When a high preset is reached, the:

HP bit is set.

High-speed counter interrupt file (program file 4) is executed if the interrupt is enabled. The IH bit is set and the IL, IN, and IV bits are reset.

Unlike the Up Counters, the accumulator value does not reset and the high preset value does not get loaded from the image to the hardware high preset register.

The Following Condition

A low preset is reached

Occurs when

either the hardware accumulator transitions from the hardware low preset +1 to the hardware low preset, or the hardware accumulator is loaded with a value less than or equal to the hardware low preset, or the hardware low preset is loaded with a value that is greater than or equal to the hardware accumulator.

7–16

Using High-Speed Counter Instructions

When a low preset is reached, the:

LP bit is set.

High-speed counter interrupt file (program file 4) is executed if the interrupt is enabled. The IL bit is set and the IH, IN, and IV bits are reset.

An overflow occurs when the hardware accumulator transitions from

+

32,767 to

–32,768. When an overflow occurs, the:

OV bit is set.

High-speed counter interrupt file (program file 4) is executed if the interrupt is enabled. The IV bit is set and the IH, IL, and IN bits are reset.

An underflow occurs when the hardware accumulator transitions from –32,768 to

+

32,767. When an underflow occurs, the:

UN bit is set.

High-speed counter interrupt file (program file 4) is executed if the interrupt is enabled. The IN bit is set and the IH, IL, and IV bits are reset.

The following tables summarize what the input state must be for the corresponding high-speed counter action to occur:

7–17

Bidirectional Counter (Encoder)

Input A

(I/0)

Turning On

Turning Off

NA

NA

Input State

Input B

(I/1)

Off

Off

On

NA

HSC Rung

True

True

NA

False

H -Speed

Counter Action

Count Up

Count Down

Hold Count

Hold Count

NA (Not Applicable)

Bidirectional Counter with Reset and Hold (Encoder)

NA

NA

NA

Off

Input A

(I/0)

Turning On

Turning Off

Off or On

On

NA

NA

Off

Off

Input B

(I/1)

Off

NA

Off

Off

Off

On

Input State

Input Z

(I/2)

Off

Off

Off

NA

NA

On

NA

Input Hold

(I/3)

Off

Off

NA

HSC Rung

True

True

NA

NA

False

NA

NA

NA (Not Applicable)

The optional hardware high-speed counter reset is the logical coincidence of A x B x Z.

H -Speed

Counter Action

Count Up

Count Down

Hold Count

Hold Count

Hold Count

Hold Count

Reset to 0

7–18

Using High-Speed Counter Instructions

High-Speed Counter Load (HSL)

HSL

HSC LOAD

Counter

Source

Length

C5:0

5

✓ ✓

(CU)

(DN)

This instruction allows you to set the low and high presets, low and high output source, and the output mask. When either a high or low preset is reached, you can instantly update selected outputs.

If you are using the HSL instruction with the Up Counter, the high preset must be

1 and

≤ +

32,767 or an error

INVALID PRESETs LOADED TO HIGH SPEED

COUNTER

(37H) occurs. For the bidirectional counters, the high preset must be greater than the low preset or an error

INVALID PRESETs LOADED TO HIGH

SPEED COUNTER

(37H) occurs.

The Counter referenced by this instruction has the same address as the HSC instruction counter and is fixed at C5:0.

Entering Parameters

Enter the following parameters when programming this instruction:

Source is an address that identifies the first of five data words used by the HSL.

The source can be either an integer or binary file element.

Length is the number of elements starting from the source. This number is always 5.

Operation

The HSL instruction allows you to configure the high-speed counter to instantaneously and automatically update external outputs whenever a high or low preset is reached. The physical outputs are automatically updated in less than 30

µ s.

(The physical turn-on time of the outputs is not included in this amount.) The output image is then automatically updated at the next poll for user interrupts, IOM instruction, or output scan, whichever occurs first.

With this instruction, you can change the high preset for the up counters or both the high and low presets for Bidirectional Counters during run. You can also modify the output mask configuration during run.

The source address is either an integer or binary file element. For example, if N7:5 is selected as the source address, the additional parameters for the execution of this instruction would appear as shown in the following table.

7–19

7–20

Parameter

Image

Location

Up Counter

Only

Bidirectional

Counters

N7:5

N7:6

N7:7

N7:8

N7:9

Output Mask

Output

Source

Hi Preset

Reserved

Reserved

Output Mask

Output High

Source

High Preset

Output Low

Source

Low Preset

Description

Identifies which group of bits in the output file

(word 0) are controlled.

000F=bits 3–0

00F0=bits 7–4

0003=bits 0 and 1

00FF= bits 7–0

(Up count.) The status of bits in this word are written “through” the mask to the actual outputs.

(Up count.) When the accumulator reaches this value, the output source is written through the output mask to the actual outputs, and the HSC subroutine (file 4) is scanned.

(Down count.) The status of bits in this word are written “through” the mask to the actual outputs.

(Down count.) When the accumulator reaches this value, the output source is written through the output mask to the actual outputs, and the

HSC subroutine (file 4) is scanned.

The bits in the output mask directly correspond to the physical outputs. If a bit is set to 1, the corresponding output can be changed by the high-speed counter. If a bit is set to 0, the corresponding output cannot be changed by the high-speed counter.

The bits in the high and low sources also directly correspond to the physical outputs.

The high source is applied when the high preset is reached. The low source is applied when the low preset is reached. The final output states are determined by applying the output source over the mask and updating only the unmasked outputs

(those with a 1 in the mask bit pattern).

You can always change the state of the outputs via the user program or programming device regardless of the output mask. The high-speed counter only modifies selected outputs and output image bits based on source and mask bit patterns when the presets are reached. The last device that changes the output image

(i.e., user program or high-speed counter) determines the actual output pattern.

Forces override any output control from either the high-speed counter or from the output image. Forces may also be applied to the high-speed counter inputs. Forced inputs are recognized by the high-speed counter (e.g., a forced count input off and on increments the high-speed accumulator).

Using High-Speed Counter Instructions

The high-speed counter hardware is updated immediately when the HSL instruction is executed regardless of high-speed counter type (Up Counter or Bidirectional

Counter). For the Up Counters, the last two registers are ignored since the low preset does not apply.

If a fault occurs due to the HSL instruction, the HSL parameters are not loaded to the high-speed counter hardware. You can use more than one HSL instruction in your program. The HSL instructions can have different image locations for the additional parameters.

Do not change a preset value and an output mask/source with the same HSL instruction as the accumulator is approaching the old preset value.

If the high-speed counter is enabled and the HSL instruction is evaluated true, the high-speed counter parameters in the HSL instruction are applied immediately without stopping the operation of the high-speed counter. If the same HSL instruction is being used to change the high-speed counter controlled mask/source and the preset, the mask/source is changed first and the preset second. (The preset is changed within 40

µ

s after the mask/source.)

If the original preset is reached after the new mask/source is applied but before the new preset is applied, the new outputs are applied immediately.

7–21

High-Speed Counter Reset (RES)

)

C5:0

RES

)

✓ ✓

The RES instruction allows you to write a zero to the hardware accumulator and image accumulator.

The counter referenced by this instruction has the same address as the HSC instruction counter and is entered as C0.

Operation

Execution of this instruction immediately:

• removes pending high-speed counter interrupts

• resets the hardware and instruction accumulators

• reset the PE, LS, OV, UN, and DN status bits

• loads the instruction high preset to the hardware high preset (if the high-speed counter is configured as an up counter)

• resets the IL, IH, IN, or IV status bits

You can have more than one RES instruction in your program.

7–22

Using High-Speed Counter Instructions

High-Speed Counter

Reset Accumulator (RAC)

RAC

RESET TO ACCUM VALUE

Counter C5:0

Source

✓ ✓

This instruction allows you to write a specific value to the hardware accumulator and image accumulator.

The counter referenced by this instruction has the same address as the HSC instruction counter and is fixed at C5:0.

Entering Parameters

Enter the following parameter when programming this instruction:

Source represents the value that is loaded to the accumulator. The source can be a constant or an address.

Operation

Execution of the RAC:

• removes pending high-speed counter interrupts

• resets the PE, LS, OV, UN, and DN status bits

• loads a new accumulator value to the hardware and instruction image

• loads the instruction high preset to the hardware high preset (if the high-speed counter is configured as an Up Counter)

• resets the IL, IH, IN, or IV status bits

The source can be a constant or any integer element in files 0–7. The hardware and instruction accumulators are updated with the new accumulator value immediately upon instruction execution.

You can have more than one RAC instruction per program referencing the same source or different sources.

7–23

High-Speed Counter Interrupt Enable (HSE) and Disable (HSD)

✓ ✓

HSE

HSC INTERRUPT ENABLE

COUNTER C5:0

HSD

HSC INTERRUPT DISABLE

COUNTER C5:0

These instructions enable or disable a high-speed counter interrupt when a high preset, low preset, overflow, or underflow is reached. Use the HSD and HSE in pairs to provide accurate execution for your application.

The counter referenced by these instructions have the same address as the HSC instruction counter and is fixed at C5:0.

Using HSE

Operation

When the high-speed counter interrupt is enabled, user subroutine (program file 4) is executed when:

A high or low preset is reached.

An overflow or underflow occurs.

When in Test Single Scan mode and in an idle condition, the high-speed counter interrupt is held off until the next scan trigger is received from the programming device. The high-speed counter accumulator counts while idle.

If the HSE is subsequently executed after the pending bit is set, the interrupt is executed immediately.

The default state of the high-speed counter interrupt is enabled (the IE bit set to 1).

If the high-speed counter interrupt routine is executing and another high-speed counter interrupt occurs, the second high-speed counter interrupt is saved but is considered pending. (The PE bit is set.) The second interrupt is executed immediately after the first one is finished executing. If an high-speed counter interrupt occurs while an high-speed counter interrupt is pending, the most recent high-speed counter interrupt is lost and the LS bit is set.

7–24

Using High-Speed Counter Instructions

Using HSD

Operation

The HSD instruction disables the high-speed counter interrupt, preventing the interrupt subroutine from being executed.

This HSD instruction does not cancel an interrupt, but results in the pending bit

(C5:0/3) being set when:

A high or low preset is reached.

An overflow or underflow occurs.

Update High-Speed Counter

Image Accumulator (OTE)

C5:0

( )

UA

✓ ✓

An OTE bit instruction, when addressed for the high-speed counter (C5:0), causes the UA bit to be set. When this bit is set, the value in the hardware accumulator is written to the value in the image accumulator (C5:0.ACC). This provides you with real-time access to the hardware accumulator value. This is in addition to the automatic transfer from the hardware accumulator to the image accumulator that occurs each time the HSC instruction is evaluated.

Operation

This instruction transfers the hardware accumulator to the instruction accumulator.

When the OTE/UA instruction is executed true, the hardware accumulator is loaded to the instruction image accumulator (C5:0.ACC).

7–25

What Happens to the HSC When Going to REM Run

Mode

Once initialized, the HSC instruction retains its previous state when going through a mode change or power cycle. This means that the HSC Accumulator (C5:0.ACC) and High Preset values are retained. Outputs under the direct control of the HSC also retain their previous state. The Low Preset Reached and High Preset Reached bits (C0/LP and C0/HP) are also retained. They are examined by the HSC instruction during the high-speed counter’s first true evaluation in the REM Run mode to differentiate a retentive REM Run mode entry from an external or initial

Accumulator (C5:0.ACC) modification.

At the first true HSC instruction execution after going-to-run, the Low Preset is initialized to –32,768 and the output mask and high and low output patterns are initialized to zero. Use the HSL instruction during the first pass to restore any values necessary for your application.

You can modify the behavior of the high-speed counter at REM Run mode entry by adjusting the HSC parameters prior to the first true execution of the HSC instruction. The following example ladder rungs demonstrate different ways to adjust the HSC parameters.

7–26

Example 1

Using High-Speed Counter Instructions

To enter the REM Run mode and have the HSC Outputs, ACC, and Interrupt

Subroutine resume their previous state, apply the following:

(Rung 2:0)

No action required. (Remember that all OUT instructions are zeroed when entering the REM Run mode. Use SET/RST instructions in place of OUT instructions in your conditional logic requiring retention.)

| S:1 +HSL–––––––––––––––+ |

|––][–––––––––––––––––––––––––––––––––––+HSC LOAD +–|

| 15 |Counter C5:0| |

| |Source N7:0| |

| |Length 5| |

| +––––––––––––––––––+ |

Rung 2:1

| +HSC––––––––––––––––––––+ |

|–––––––––––––––––––––––––––––+HIGH SPEED COUNTER +–(CU)–|

| |Type Encoder(Res,Hld) +–(CD) |

| |Counter C5:0+–(DN) |

| |High Preset 1000| |

| |Accum 0| |

| +–––––––––––––––––––––––+ |

7–27

Example 2

To enter the REM Run mode and retain the HSC ACC value while having the HSC

Outputs and Interrupt Subroutine reassert themselves, apply the following:

Rung 2:0

Unlatch the C5:0/HP and C5:0/LP bits during the first scan BEFORE the

HSC instruction is executed for the first time.

| S:1 +HSL–––––––––––––––+ |

|––][––––––––––––––––––––––––––––––––––––––––––+HSC LOAD +– |

| 15 |Counter C5:0| |

| |Source N7:0| |

| |Length 5| |

| +––––––––––––––––––+

|

Rung 2:1

| S:1 C5:0 |

|––][–––––––––––––––––––––––––––––––––––––––––––––––––––––+–(U)––+|––|

| 15 | HP | |

| | C5:0 | |

| +––(U)––+ |

| LP |

Rung 2:2

| +HSC––––––––––––––––––––+ |

|–––––––––––––––––––––––––––––––––––––+HIGH SPEED COUNTER +–(CU)–|

| |Type Encoder (Res,Hld)+–(CD) |

| |Counter C5:0+–(DN) |

| |High Preset 1000| |

| |Accum 0| |

| +–––––––––––––––––––––––+ |

7–28

Example 3

Using High-Speed Counter Instructions

To enter the REM Run mode and have the HSC ACC and Interrupt Subroutine resume their previous state, while externally initializing the HSC outputs, apply the following:

Rung 2:0

Unlatch or Latch the output bits under HSC control during the first scan after the HSC instruction is executed for the first time. (Note: you could place this rung before the HSC instruction; however, this is not recommended.)

| S:1 +HSL–––––––––––––––+ |

|––][–––––––––––––––––––––––––––––––––––––––––––+HSC LOAD +–|

| 15 |Counter C5:0| |

| |Source N7:0| |

| |Length 5| |

| +––––––––––––––––––+ |

Rung 2:1

| +HSC––––––––––––––––––––+ |

|–––––––––––––––––––––––––––––––––––––+HIGH SPEED COUNTER +–(CU)–|

| |Type Encoder (Res,Hld)+–(CD) |

| |Counter C5:0+–(DN) |

| |High Preset 1000| |

| |Accum 0| |

| +–––––––––––––––––––––––+ |

Rung 2:2

This rung is programmed with the knowledge of an HSL mask of 0007

(outputs 0–2 are used) and initializes the HSC outputs each REM Run mode entry. Outputs O/0 and O/1 are off, while Output O/2 is on.

| S:1 O:0 |

|––][––––––––––––––––––––––––––––––––––––––––––––––––––––+––(U)––+|––|

| 15 | 0 | |

| | O:0 | |

| +––(U)–––+ |

| | 1 | |

| | O:0 | |

| +––(L)–––+ |

| 2 |

7–29

High-Speed Counter Instructions in the Paper Drilling

Machine Application Example

Drilled

Holes

The ladder rungs in this section demonstrate the use of the HSC instruction in the

paper drilling machine application example started in chapter 4. Refer to

appendix H for the complete paper drilling machine application example.

Drill Home

I:1/5

Drill Depth

I:1/4

Drill On/Off O:3/1

Drill Retract O:3/2

Drill Forward O:3/3

Photo-Eye Reset I:1/2

Counter Hold I:1/3

Quadrature A-B Encoder and Drive

I:1/0 I:1/1

Photo-Eye

Reflector

Conveyor Enable wired in series to the Drive O:3/5

Conveyor Drive Start/Stop wired in series to the Drive O:3/0

20226

The main program file (file 2) initializes the HSC instruction, monitors the machine start and stop buttons, and calls other subroutines necessary to run the machine.

Refer to the comments preceding each rung for additional information.

7–30

Using High-Speed Counter Instructions

Rung 2:0

Initializes the high-speed counter each time the REM Run mode is entered. The high-speed counter data area (N7:5 – N7:9) corresponds with the starting address (source address) of the HSL instruction. The

HSC instruction is disabled each entry into the REM run mode until the first time that it is executed as true. (The high preset was ”pegged” on initialization to prevent a high preset interrupt from occurring during the initialization process.)

| 1’st Output Mask |

| Pass (only use bit 0 |

| ie. O:0/0) |

| S:1 +MOV–––––––––––––––+ |

|––––] [–––––––––––––––––––––––––––––––––––––+–+MOVE +–+–|

| 15 | |Source 1| | |

| | | | | |

| | |Dest N7:5| | |

| | | 0| | |

| | +––––––––––––––––––+ | |

| | High Output Pattern | |

| | (turn off O:0/0) | |

| | | |

| | +MOV–––––––––––––––+ | |

| +–+MOVE +–+ |

| | |Source 0| | |

| | | | | |

| | |Dest N7:6| | |

| | | 0| | |

| | +––––––––––––––––––+ | |

| | High Preset Value | |

| | (counts to next hole)| |

| | |

| | +MOV–––––––––––––––+ | |

| +–+MOVE +–+ |

| | |Source 32767| | |

| | | | | |

| | |Dest N7:7| | |

| | | 0| | |

| | +––––––––––––––––––+ | |

| | Low output pattern | |

| | (turn on O:0/0 | |

| | each reset) | |

| | |

| | +MOV–––––––––––––––+ | |

| +–+MOVE +–+ |

| | |Source 1| | |

| | | | | |

| | |Dest N7:8| | |

| | | 0| | |

| | +––––––––––––––––––+ | |

| | Low preset value | |

| | (cause low preset | |

| | int at reset) | |

| | |

| | +MOV–––––––––––––––+ | |

| +–+MOVE +–+ |

| | |Source 0| | |

| | | | | |

| | |Dest N7:9| | |

| | | 0| | |

| | +––––––––––––––––––+ | |

| | | |

7–31

7–32

| | | |

| | High Speed Counter | |

| | | |

| | +HSL–––––––––––––––+ | |

| + –+HSC LOAD +–+ |

| |Counter C5:0| |

| |Source N7:5| |

| |Length 5| |

| +––––––––––––––––––+ |

Rungs 2.0 and 2.2 are required to write several parameters to the high-speed counter data file area. These two rungs are conditioned by the first pass bit during one scan when the controller is going from REM program to REM Run mode.

Rung 2:1

This HSC instruction is not placed in the high-speed counter interrupt subroutine. If this instruction were placed in the interrupt subroutine, the high-speed counter could never be started or initialized (because an interrupt must first occur in order to scan the high-speed counter interrupt subroutine).

| High Speed Counter |

| +HSC––––––––––––––––––––+ |

|––––––––––––––––––––––––––––––––––––––+HIGH SPEED COUNTER +–(CU)–|

| |Type Encoder (Res,Hld)+–(CD) |

| |Counter C5:0+–(DN) |

| |High Preset 1250| |

| |Accum 1| |

| +–––––––––––––––––––––––+ |

Rung 2:2

Forces a high-speed counter low preset interrupt to occur each REM Run mode entry. An interrupt can only occur on the transition of the high-speed counter accum to a preset value (accum reset to 1, then 0).

This is done to allow the high-speed counter interrupt subroutine sequencers to initialize. The order of high-speed counter initialization is: (1)load high-speed counter parameters (2)execute

HSL instruction (3)execute true HSC instruction (4)(optional) force high-speed counter interrupt to occur.

| 1’st High Speed Counter |

| Pass |

| S:1 +RAC––––––––––––––––––+ |

|––––] [––––––––––––––––––––––––––––––––––+–+RESET TO ACCUM VALUE +–+–|

| 15 | |Counter C5:0| | |

| | |Source 1| | |

| | | | | |

| | +–––––––––––––––––––––+ | |

| | High Speed | |

| | Counter | |

| | C5:0 | |

| +–––(RES)–––––––––––––––––+ |

Using High-Speed Counter Instructions

The high-speed counter is used to control the conveyer position. The high-speed counter counts pulses supplied by the conveyer’s encoder via hardware inputs I:0/0 and I:0/1. Hardware inputs I:0/2 (reset) and I:0/3 (hold) are connected to a photo-switch ensuring the HSC instruction only counts encoder pulses when a manual is in front of the drill and that the high-speed counter is reset at the leading edge of each manual.

The high-speed counter clears the conveyer drive output bit (O:0/0) each time a high preset is reached. As a result, the drive decelerates and stops the conveyer motor.

The high-speed counter clears the output within microseconds ensuring accuracy and repeatability.

The high-speed counter sets the conveyer drive output bit (O:0/0) each time a low preset is reached. As a result, the drive accelerates and maintains the conveyer motor.

When the manual has travelled the specified distance set by the high-speed counter high preset value, the high-speed counter interrupt subroutine signals the main program to perform the drilling sequence. For more information regarding the interrupt subroutine used in this program, refer to the application example in

chapter 12.

This example uses the Quadrature Encoder with reset and hold instruction. The high-speed counter accumulator increments and decrements based on the quadrature relationship of the encoder’s A and B inputs (I:0/0 and I:0/1). The accumulator is cleared to zero when the reset is activated or when the RES instruction is executed.

All presets are entered as a relative offset to the leading edge of a manual. The

presets for the hole patterns are stored in the SQO instructions. (Refer to chapter 6

for the SQO instruction.) The high-speed counter external reset input (I:0/2) and the external hold input (I:0/3) are wired in parallel to prevent the high-speed counter from counting while the reset is active.

The input filter delays for both the high-speed counter A and B inputs (I:0/0 and

I:0/1) as well as the high-speed counter reset and hold inputs (I:0/2 and I:0/3) can be adjusted.

7–33

7–34

Rung 4:5

Interrupt occurred due to low preset reached.

| C5:0 +RET–––––––––––––––+–|

|––––][––––––––––––––––––––––––––––––––––––––––––+RETURN + |

| IL +––––––––––––––––––+ |

Rung 4:6

Signals the main program (file 2) to initiate a drilling sequence. The high-speed counter has already stopped the conveyor at the correct position using its high preset output pattern data (clear O:0/0). This occurred within microseconds of the high preset being reached (just prior to entering this high-speed counter interrupt subroutine). The drill sequence subroutine resets the drill sequence start bit and sets the conveyor drive bit (O:0/0) upon completion of the drilling sequence.

| interrupt occurred | Drill Sequence Start |

| due to high preset reached | |

| C5:0 B3 |

|––––] [––––––––––––––––––––––––––––––––––––––––––––––––––––––(L)–––––|

| IH 32 |

Rung 4:7

| |

|–––––––––––––––––––––––––––––––+END+–––––––––––––––––––––––––––––––––|

| |

SLC Communication Instructions

8

SLC Communication Instructions

This chapter contains general information about the SLC communication instructions. Each of the instructions includes information on:

• what the instruction symbol looks like

• how to use the instruction

• an application example and timing diagrams

Communication Instructions

Mnemonic

Instruction

Name

MSG

Message

Read/Write

SVC

Service

Communications

This instruction transfers data from one node to another on the communication network. When the instruction is enabled, message transfer is pending.

Actual data transfer takes place at the end of scan.

When conditions preceding the SVC instruction in the rung are true, the SVC instruction interrupts the program scan to execute the service communication portion of the operating cycle.

8–2

8–58

8–1

About the Communication Instructions

Use the Message instruction to send and receive data from other processors and devices. Use the SVC instruction to enhance communication performance of your processor.

In this chapter you will find a general overview preceding each type of instruction:

Message instruction for the SLC 5/02 processor

Message instruction for the SLC 5/03 and SLC 5/04 processors

Message instruction for the SLC 5/05 processor

Service Communication instruction for the SLC 5/02 processor

Service Communication instruction for SLC 5/03 and higher processors

SLC 5/02 Message Instruction Overview

MSG

READ/WRITE MESSAGE

Read/write

Target Device

Control Block

Control Block Length 7

Output Instruction

(EN)

(DN)

(ER)

This is an output instruction that allows you to transfer data from one node to another via the DH-485 network. The SLC 5/02 processor can service one message instruction at any given time, although the processor may hold several messages

“enabled and waiting.” Waiting messages are serviced one at a time in sequential order (first in first out).

Operation

The instruction can be programmed as a read or write message. The target device can be another SLC 500 processor on the network, or a non-SLC 500 device, using the common interface file (485CIF file 9 in SLC 500 processors). The 485CIF protocol is also used for PLC-2 type messages.

The data associated with a message write instruction is not sent when you enable the instruction. Rather, it is sent at the end of the scan or at the time a Service

Communication (SVC) or Refresh (REF) instruction in your ladder program is enabled. In some instances, this means that you must buffer data in your application.

When you select the SLC500 as your target device, communication can take place between the SLC 5/02 processor and any other SLC 500 family processor.

8–2

SLC Communication Instructions

Related Status File Bits

Three status file bits are related to the MSG instruction:

Incoming Command Pending Bit (S:2/5) – This bit is set when the processor determines that another node on the network has requested information or supplied a command to it. This bit can become set at any time.

This bit is cleared when the processor services the request (or command).

Use this bit as a condition of an SVC instruction to enhance the communication capability of your processor.

Message Reply Pending Bit (S:2/6) – This bit is set when another node on the network has supplied the information that you requested in the MSG instruction of your processor. This bit is cleared when the processor stores the information and updates your MSG instruction.

Use this bit as a condition of an SVC instruction to enhance the communication capability of your processor.

Outgoing Message Command Pending Bit (S:2/7) – This bit is set when one or more messages in your program are enabled and waiting, but no message is being transmitted at the time. As soon as transmission of a message begins, the bit is cleared. After transmission, the bit is set again if there are further messages waiting, or it remains cleared if there are no further messages waiting.

Use this bit as a condition of an SVC instruction to enhance the communication capability of your processor.

You may also want to use bit S:2/15 Communications Servicing Selection. Refer to

appendix B in this manual for more information.

Available Configuration Options

The following configuration options are available with a SLC 5/02 processor:

Peer-to-Peer Read/Write on a Local network to another SLC 500 processor

Peer-to-Peer Read/Write on a Local network to a 485CIF (PLC2 emulation)

Refer to appendix E for valid parameters when programming the Message

instruction.

8–3

Entering Parameters

Note

After you place the MSG instruction on a rung, specify whether the message is to be a read or write. Then specify the target device and the control block for the MSG instruction.

Read/Write – Read indicates that the local processor (processor in which the instruction is located) is receiving data; write indicates that the processor is sending data.

Target Device identifies the type of device which will receive data. Valid options are:

500CPU, if the target device is another SLC processor

485CIF, if the target device is a non-SLC device (PLC2 emulator)

Control Block is an integer file address that you select. It is a 7-element file, containing the status bits, target file address, and other data associated with the message instruction.

Control Block Length is fixed at seven elements. This field cannot be altered.

The MSG control block length increases from 7 to 14 words when changing from a SLC 5/02 to a SLC 5/03, SLC 5/04 (channel 0, DH-485), or SLC 5/05

(channel 0, DH-485) processor program. Make sure that there are at least 7 unused words following each MSG control block in your program.

8–4

SLC Communication Instructions

Using Status Bits

Read/Write:

Target Device:

Control Block:

Local Destination File Address:

Target Node:

Target File Address:

Message Length in elements

READ

500CPU

N7:0

***

0

***

***

ERROR CODE: 0

Error Code Desc: ignore if timed out: to be retried: awaiting execution: error: message done: message transmitting: message enabled: control bit address:

0 TO

0 NR

0 EW

0 ER

0 DN

0 ST

0 EN

N7:0/8

The right column in the display above lists the various status bits associated with the

SLC 5/02 MSG instruction.

Time Out Bit TO (bit 08) You can set this bit in your application to remove an active message instruction from processor control. Your application must

supply its own timeout value. An example appears on page 8–13.

No Response Bit NR (bit 09) is set if the target processor does not respond to the first message request. The NR bit is reset when the ER, DN, or ST bit is set.

Enabled and Waiting Bit EW (bit 10) is set after the enable bit is set and the message is waiting to be sent.

Error Bit ER (bit 12) is set when message transmission has failed. The ER bit is reset the next time the associated rung goes from false to true.

Done Bit DN (bit 13) is set when the message is transmitted successfully. The

DN bit is reset the next time the associated rung goes from false to true.

Start Bit ST (bit 14) is set when the processor receives acknowledgement from the target device. The ST bit is reset when the DN, ER, or TO bit is set.

Enable Bit EN (bit 15) is set when rung conditions go true and the instruction is being executed. It remains set until the message transmission is complete and the rung goes false.

8–5

Timing Diagram for SLC 5/02 MSG Instruction

The following section describes the timing diagram for a SLC 5/02 MSG instruction.

EN

1

0

EW

1

0

ST

1

0

DN

ER

1

0

1

0

NR

1

0

TO

1

0

Rung goes True.

Target node receives packet.

➀ ➁ ➂

Target node processes packet successfully and returns data

(read) or writes data (success).

1.

When the MSG rung becomes true and the MSG is scanned, the EN bit is set and remains set until either the DN, ER, or TO bit is set. The EW bit is set, indicating that the MSG instruction has been placed in the MSG Queue. (The

SLC 5/02 processor always has room in the MSG Queue.) The queue works on a first-in-first-out basis that allows the SLC 5/02 processor to remember the order the MSG instructions were enabled. Note that the program does not have access to the SLC 5/02 MSG Queue.

2.

At the next end of scan or Service Communication instruction (SVC), the

SLC 5/02 processor determines if it should examine the MSG Queue for

“something to do.” The processor bases its decision on the state of bit S:2/15,

DH-485 communication requests from other nodes, and if a previous MSG instruction is already in progress. If the 5/02 processor determines that it should not access the queue, the EN and EW bits remain set until the next end of scan or SVC.

8–6

Note

SLC Communication Instructions

If the SLC 5/02 processor determines that it has “something to do” it uses the first message queue entry to build a DH-485 packet. If a packet can be successfully built, it is placed in the transmit buffer. If a packet cannot be successfully built, the ER bit is set and a code is placed in the MSG block to inform you of the error.

If this were a MSG Write instruction, the source data would be transferred to the transmit buffer at this time.

The SLC 5/02 processor then exits the end of scan or SVC portion of the scan.

The processor’s background communication function sends the transmitted buffer packet to the Target Node that you specified in your MSG instruction.

3.

If the Target Node successfully receives the DH-485 packet, it sends back an

ACK (an acknowledge). The ACK causes the processor to clear the EW bit and set the ST bit. Note that the Target Node has not yet examined the DH-485 packet to see if it understands your request.

Once the ST bit is set, the processor waits indefinitely for a reply from the

Target Node. The Target Node is not required to respond within any give time frame. At this time, no other MSG instruction will be serviced.

If the Target Node faults or power cycles during this time frame of a MSG transaction, you will never receive a reply. This is why it is recommended you use a timer instruction in conjunction with the TO bit. Refer to the example on

page 8–13.

Step 4 is not shown in the timing diagram.

4.

If you do not receive an ACK, step 3 does not occur. Instead a NAK (no acknowledge) is received. When this happens, the ST bit remains clear. A

NAK indicates:

• either the Target Node is not there,

• it does not respond

• it is too busy, or

• it receives a corrupt DH-485 packet.

When a NAK occurs, the EW bit is cleared and the NR bit is set for one scan.

The next time the MSG instruction is scanned, the ER bit is set and the NR bit is cleared. This indicates that the MSG instruction failed. Note that if the

Target Node is too busy, the ER bit is not set. Instead, the MSG instruction re-queues itself for re-transmission.

8–7

5.

Following the successful receipt of the packet, the Target Node sends a reply packet. The reply packet will contain one of the following responses:

I have successfully performed your write request.

I have successfully performed your read request, and here is your data.

I have not performed your request, you are in error.

At the next end of scan or SVC, following the Target Node’s reply, the SLC

5/02 processor examines the DH-485 packet from the target device. If the reply contains “I have successfully performed your write request,” the DN bit is set and the ST bit is cleared. The MSG instruction function is complete. If the

MSG rung is false, the EN bit is cleared the next time the MSG instruction is scanned.

If the reply contains “I have successfully performed your read request, and here is your data,” the data is written to the data table, the DN bit is set and the ST bit is cleared. The MSG instruction function is complete. If the MSG rung is false, the EN bit is cleared the next time the MSG instruction is scanned.

If the reply contains “I have not performed your request, you are in error,” the

ER bit is set and the ST bit is cleared. The MSG instruction function is complete. If the MSG rung is false, the EN bit is cleared the next time the MSG instruction is scanned.

Control Block Layout

The control block layout is shown below if you select a 500CPU as the target device:

Control Block Layout – 500CPU

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

EN ST DN ER EW NR TO Error Code

Node Number

Reserved for length in words

File Number

File Type (S, B, T, C, R, N)

Element Number

Reserved

2

3

4

Word

0

1

5

6

8–8

SLC Communication Instructions

The control block layout is shown below if you select a 485 CIF as the target device:

Control Block Layout – 485 CIF

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

EN ST DN ER EW NR TO Error Code

Offset elements

Reserved for length in elements

Node Number

Not used

Not used

Not used

Word

0

3

4

1

2

5

6

Application Examples for SLC 5/02 Processors

Example 1

0

1

2

Application example 1 shows how you can implement continuous operation of a message instruction.

B3

] [

1

MSG

READ/WRITE MESSAGE

Read/write

Target Device

WRITE

500CPU

Control Block N7:0

Control Block Length 7

(EN)

(DN)

(ER)

N7:0

] [

13*

N7:0

] [

12*

N7:0

(U)

15*

* MSG instruction

status bits:

12 = ER

13 = DN

15 = EN

END

Operation Notes

Bit B3/1 enables the MSG instruction. When the MSG instruction done bit is set, it unlatches the MSG enable bit so that the MSG instruction is enabled in the next scan. This provides continuous operation.

The MSG error bit also unlatches the enable bit. This provides continuous operation regardless of errors.

8–9

Example 2 – Program File 2 of SLC 5/02 Processor

This example involves an SLC 5/02 processor and an SLC 5/01 processor communicating on a DH-485 network. Interlocking is provided to verify data transfer and to shut down both processors if communication fails.

A temperature-sensing device, connected as an input to the SLC 5/02 processor, controls the on-off operation of a cooling fan, connected as an output to the

SLC 5/01 processor. The SLC 5/02 and SLC 5/01 ladder programs are explained in

the figure on page 8–12.

8–10

SLC Communication Instructions

0

Temperature-sensing

Input Device

First Pass Bit

1

First Pass Bit

1280 ms Clock Bit

Message Write

Done Bit

Message Read

Done Bit

2

3

4

S:1

] [

15

S:4

] [

6

B3

] [

0

N10:0

] [

13*

5

6

7

I:1.0

] [

5

S:1

] [

15

T4:0

] [

DN

N7:0

( )

1

T4:0

(RES)

N7:0

(L)

0

TON

TIMER ON DELAY

Timer T4:0

Time Base

Preset

Accum

0.01

400

0

B3

(U)

0

(EN)

(DN)

MSG

READ/WRITE MESSAGE

Read/write

Target Device

Control Block

WRITE

500CPU

Control Block Length

N10:0

7

(EN)

(DN)

(ER)

MSG

READ/WRITE MESSAGE

Read/write

Target Device

Control Block

READ

500CPU

Control Block Length

N11:0

7

B3

(L)

0

(EN)

(DN)

(ER)

B3

(L)

10

N11:0

] [

13*

N7:0

]/[

0

END

Operation notes appear on the following page.

T4:0

(RES)

N7:0

(U)

0

B3

(U)

0

N11:0

(U)

15*

N10:0

(U)

15*

Bit 1 of the message word. Used for fan control.

Bit 0 of the message word.

This is the interlock bit.

4-second Timer

Write message instruction. The source and target file addresses are N7:0

Target node: 3

Message length: 1 word.

Read message instruction. The destination and target file addresses are N7:0

Target node: 3

Message length: 1 word.

Latch – This alarm instruction notifies the application if the interlock bit N7:0/0 remains set for more than 4 seconds.

* MSG instruction

status bits:

13 = DN

15 = EN

8–11

Program File 2 of SLC 5/01 Processor at Node 3

0

S:1

] [

15

First Pass Bit

1

TON

TIMER ON DELAY

Timer T4:0

Time Base

Preset

Accum

0.01

400

0

N7:0

(U)

0

T4:0

(RES)

(EN)

(DN)

Bit 1 of the message word. Used for fan control.

2

3

4

T4:0

] [

DN

N7:0

] [

0

B3

] [

1

B3

[OSR]

0

5

N7:0

] [

1

6

END

B3

(L)

10

B3

( )

1

N7:0

(U)

0

T4:0

(RES)

O:1.0

( )

0

Bit 0 of the message word. This is the interlock bit.

4-second Timer

Latch Instruction –

This alarm notifies the application if the interlock bit N7:0/0 is not set after

4 seconds.

O:1/0 energizes cooling fan.

Operation Notes, SLC 5/02 and SLC 5/01 programs

Message instruction parameters: N7:0 is the message word. It is the target file address (SLC 5/01 processor) and the local source and destination addresses (SLC 5/02 processor) in the message instructions.

N7:0/0 of the message word is the interlock bit; it is written to the 5/01 processor as a 1 (set) and read from the SLC 5/01 processor as a 0 (reset).

N7:0/1 of the message word controls cooling fan operation; it is written to the SLC 5/01 processor as a 1 (set) if cooling is required or as a 0 (reset) if cooling is not required. It is read from the SLC 5/01 processor as either 1 or 0.

Word N7:0 should have a value of 1 or 3 during the message write execution. N7:0 should have a value of 0 or 2 during the message read execution.

Program initialization: The first pass bit S:1/15 initializes the ladder programs on run mode entry.

SLC 5/02 processor: N7:0/0 is latched; timer T4:0 is reset; B3/0 is unlatched (rung 1), then latched (rung 3). SLC 5/01 processor: N7:0/0 is unlatched; timer T4:0 is reset.

Message instruction operation: The message write instruction in the SLC 5/02 processor is initiated every 1280 ms by clock bit

S:4/6. The done bit of the message write instruction initiates the message read instruction.

B3/0 latches the message write instruction. B3/0 is unlatched when the message read instruction done bit is set, provided that the interlock bit N7:0/0 is reset.

Communication failure: In the SLC 5/02 processor, bit B3/10 becomes set if interlock bit N7:0/0 remains set (1) for more than

4 seconds. In the SLC 5/01 processor, bit B3/10 becomes set if interlock bit N7:0/0 remains set (1) for more than 4 seconds.

Your application can detect this event, take appropriate action, then unlatch bit B3/10.

8–12

SLC Communication Instructions

Example 3

B3/1 is latched

(external to this example) to initiate the message instruction.

1

0

This example shows you how to use the timeout bit to disable an active message instruction. In this example, an output is energized after five unsuccessful attempts

(two seconds duration) to transmit a message.

1

[LBL]

B3

] [

1

MSG

READ/WRITE MESSAGE

Read/write

Target Device

Control Block

Control Block Length

WRITE

500CPU

N7:0

7

(EN)

(DN)

(ER)

B3

] [

1

T4:0

]/[

DN

TON

TIMER ON DELAY

Timer T4:0

Time Base

Preset

Accum

0.01

200

0

(EN)

(DN)

2-second timer. Each attempt at transmission has a 2–second duration.

2

T4:0

] [

DN

CTU

COUNT UP

Counter

Preset

Accum

C5:0

5

0

(CU)

(DN)

Counter allows 5 attempts.

3

N7:0

] [

8

*

N7:0

] [

12

CLR

CLEAR

Dest N7:0

0

Clear the control word and jump back to rung 0 for another attempt.

1

(JMP)

4

5

T4:0

] [

DN

C5:0

] [

DN

N7:0

(L)

8

O:1.0

(L)

0

N7:0/8 is the message instruction timeout bit

(/TO).

The fifth attempt latches

O0:1/0.

6

N7:0

] [

13*

C5:0

(RES)

O:1.0

(U)

0

B3

(U)

1

* MSG instruction

status bits:

8 = TO

13 = DN

7

END

Operation Notes

The timeout bit is latched (rung 4) after a period of 2 seconds.

This clears the message instruction from processor control on the next scan. The message instruction is then re-enabled for a second attempt at transmission. After 5 attempts, O:1/0 is latched.

A successful attempt at transmission resets the counter, unlatches

O:1/0, and unlatches B3/1.

8–13

Example 4

This example shows you how to link message instructions together to transmit serially, one after another. In this example a MSG Write is followed by a MSG

Read which causes the serial transmission.

Rung 2:0

The MSG instruction energizes upon entry into the REM Run or RUN mode, and after the second MSG instruction completes.

S:1

] [

15

N7:20

] [

12

MSG

READ/WRITE MESSAGE

Read/write

Target Device

Control Block

Control Block Length

WRITE

500CPU

N7:0

7

N7:20

] [

13

(EN)

(DN)

(ER)

Rung 2:1

The MSG instruction is energized when the previous MSG instruction completes.

N7:0

] [

12

N7:0

] [

13

MSG

READ/WRITE MESSAGE

Read/write

Target Device

Control Block

READ

500CPU

Control Block Length

N7:20

7

(EN)

(DN)

(ER)

Rung 2:2 END

8–14

SLC Communication Instructions

SLC 5/03 and SLC 5/04

Message Instruction Overview

✓ ✓

MSG

READ/WRITE MESSAGE

Type

Read/write

Target Device

Local/Remote

Control Block

Control Block Length 14

(EN)

(DN)

(ER)

Data associated with a message write instruction is buffered when you enable the instruction. The SLC 5/03 with OS300 has four transmit buffers. The SLC 5/03

(OS301 and higher) and the SLC 5/04 processors service up to four message instructions per channel, for a maximum of eight message instructions.

Output Instruction

To invoke the MSG instruction, toggle the MSG instruction rung from false-to-true.

Do not toggle the rung again until the MSG instruction has successfully or unsuccessfully completed the previous message, indicated by the processor setting either the DN or ER bit.

Operation

Note

SLC 5/03 OS300 – If a MSG instruction has entered one of the four “channel independent” transmission buffers and is waiting to be transmitted, its control block will have status bits EN and EW set. If more than four MSG instructions are enabled at one time, a “channel dependent” overflow queue is used to store the

MSG instruction header blocks (not the data for a MSG write) from the fifth instruction to the fourteenth.

SLC 5/03( OS301 and higher) and SLC 5/04 – If a MSG instruction has entered one of the four “channel dependent” transmission buffers and is waiting to be transmitted, its control block will have status bits EN and EW set. If more than four

MSG instructions for that channel are enabled at one time, a “channel dependent” overflow queue is used to store the MSG instruction header blocks (not the data for a MSG write) from the fifth instruction to the fourteenth. These instructions, queued in a FIFO order, will only have control block status bit EN set.

If more than 14 MSG instructions are enabled at one time for any one channel, only control block status bit WQ is set, as there is no room available to currently queue the instruction. This instruction must be re-scanned with true rung conditions until space exists in the overflow queue.

If you consistently enable more MSG instructions than the buffers and queues can accomodate, the order in which MSG instructions enter the queue is determined by the order in which they are scanned. This means MSG instructions closest to the beginning of the program enter the queue regularly and MSG instructions later in the program may not enter the queue.

8–15

You can use the timeout control similar to the SLC 5/02 MSG instruction or use the built in timeout control (recommended). If the timeout value is set to 0, which is the default, the functionality is similar to the SLC 5/02 MSG instruction. It differs in that once the TO bit is set, it will be reset automatically along with the ER bit on the next MSG rung false-to-true transition. We highly recommend setting the internal timeout value to something other than zero.

When using an SLC 5/03 or SLC 5/04 processor the message instruction:

• initiates reads and writes through RS-232 Channel 0 when configured for the following protocols:

DF1 Full-Duplex (Point-to-Point)

DF1 Half-Duplex Master/Slave (Point-to-Multipoint)

DH-485

• initiates reads and writes through:

DH-485 channel 1 (SLC 5/03 processors only)

DH

+

channel 1 (SLC 5/04 processors only)

Related Status File Bits

Channel 1

S:2/5 Incoming Command Pending Bit

S:2/6 Message Reply Pending Bit

Channel 0

S:33/0 Incoming Command Pending

S:33/1 Message Reply Pending

S:2/7 Outgoing Message Command Pending

Bit

S:33/2 Outgoing Message Command

Pending

S:2/15 Communications Servicing Selection Bit S:33/5 Communications Servicing Selection

S:33/7 Message Servicing Selection S:33/6 Message Servicing Selection

Refer to appendix B in this manual for more information on the above status file

bits.

8–16

SLC Communication Instructions

Available Configuration Options

The following configuation options are available when using an SLC 5/03 or

SLC 5/04 processor. Refer to appendix E for valid parameters when programming

the Message instruction.

Peer-to-Peer Read/Write on a Local network to another SLC 500 processor

Peer-to-Peer Read/Write on a Local network to a 485CIF

Peer-to-Peer Read/Write on a Local network to a PLC-5

Peer-to-Peer Read/Write on a Remote network to another SLC 500 processor

Peer-to-Peer Read/Write on a Remote network to a 485CIF (PLC2 emulation)

Peer-to-Peer Read/Write on a Remote network to a PLC-5 processor

Applies to SLC 5/03 (OS301 and higher) and SLC 5/04 processors.

Entering Parameters

Note

Enter the following parameters when programming this instruction:

Read/Write – Read indicates that the local processor (processor in which the instruction is located) is receiving data; write indicates that it is sending data.

Target Device identifies the type of device which will receive data. Valid options are:

500CPU, if the target device is another SLC processor

485CIF, if the target device is a non–SLC device on the DH-485 network

PLC-5, if the target device accepts PLC-5 commands

Local or Remote identifies if the message is sent to a device on a local DH-485 or DH

+

network, or to a remote device on another network through a bridge.

Valid options are:

Local, if the target device is on the local network

Remote, if the target device is on a remote network

Control Block is an integer file address that you select. It is a 14-word integer file, containing the status bits, target file address, and other data associated with the message instruction.

Control Block Length is fixed at 14 elements. This field cannot be altered.

The MSG control block length increases from 7 to 14 words when changing from a SLC 5/02 to a SLC 5/03 or SLC 5/04 (channel 0, DH-485) processor program. Make sure that there are at least 7 unused words following each MSG control block in your program.

8–17

Using Status Bits

Type:

Read/Write:

Target Device:

Local/Remote:

Control Block:

Channel:

Target Node:

The right column in the display below lists the various status bits associated with the

SLC 5/03 and SLC 5/04 MSG instruction.

Peer–to–Peer

READ

500CPU

Local

N10:0

1

2 ignore if timed out: 0 TO to be retried: 0 NR awaiting execution: 0 EW continuous run: 0 CO error: 0 ER message done: 0 DN message transmitting: 0 ST message enabled: 0 EN waiting for queue space: 0 WQ Destination File Addr:

Target Source File Address:

Message Length In Elements:

Message Timeout (seconds):

ERROR CODE: 0

Error Code Desc:

N7:0

N7:50

10

5 control bit address: N10:0/8

Note

Timeout Bit TO (word 0, bit 08) Set this bit in your application to remove an active message instruction from processor control. You can use either your own timeout control routine similiar to the SLC 5/02 MSG instruction or the internal timeout control. We recommend using the built in timeout control because it simplifies the user program.

To utilize the internal timeout control, a value greater than 0 (typical values are

4 or 5 seconds) must be entered for the MSG instruction time-out parameter. A time-out value of 0 means no time-out value. In other words, if communication is interrupted, the processor will wait forever for a reply. If an ACK is received

(as indicated by the ST bit being set), but the reply is not received, the MSG instruction will appear to be locked up, although it is merely waiting for the reply.

When a value greater than 0 is entered for the MSG time-out parameter and communication is interrupted, the MSG instruction will time-out and error after the time expires, allowing the user program to retry the same message if desired.

When programming timeout control, omit the Timeout Bit manual reset rung. This rung must also be removed from existing (SLC 5/03 OS300) programs when upgrading to new firmware (OS301 or higher).

No Response Bit NR (bit 09) is set if the target processor responds to the

MSG instruction with a target node busy negative acknowledgement for

DH-485 protocol only. This means that the target device cannot service the packet at that time and should be retried. The NR bit is reset when the ER or

ST bit is set. Do not set or reset this bit. It is informational only.

8–18

SLC Communication Instructions

Enabled and Waiting Bit EW (bit 10) is set after the enable bit is set and the message is buffered and waiting to be sent in the buffer. Do not set or reset this bit. It is informational only.

Continuous Operation CO (bit 11) Set this bit if you wish to continually send the MSG instruction. We recommend that internal timeout control be used for this option and the rung be unconditionally true. Use this bit to turn the mode on and off. A MSG instruction occupies one of the four channel transmission buffers when its CO bit is set. Therefore, a maximum of four

MSG instructions per channel may have their CO bit set.

This mode will continuously operate provided that the rung is continually scanned. If the instruction errors prior to the MSG timeout, it will automatically retry until it is successful. If it times out and is rescanned, the mode will stop.

The EN bit must be cleared to resume operation.

Error Bit ER (bit 12) is set when message transmission has failed. The ER bit is reset the next time the associated rung goes from false to true. Do not set or reset this bit. If is informational only.

Done Bit DN (bit 13) is set when the message is transmitted successfully. The

DN bit is reset the next time the associated rung goes from false to true. Do not set or reset this bit. It is informational only.

Start Bit ST (bit 14) is set when the processor receives acknowledgement

(ACK) from the target device. The ST bit is reset when the DN, ER, or TO bit is set. Do not set or reset this bit. It is informational only.

For SLC 5/05 Ethernet (channel 1) communications, the ST bit indicates internally that the Ethernet daughterboard has received a command and it is acceptable for a transmission attempt. The command has not yet been transmitted.

Enable Bit EN (bit 15) is set when rung conditions go true and there is space available in either the MSG buffer or MSG queue. It remains set until message transmission is completed and the rung goes false. You may reset this bit once either the ER or DN bit is set in order to retrigger a MSG instruction with true rung conditions on the next scan. Do not set this bit.

Waiting for Queue Space Bit WQ (Word 7, bit 0) is set when the queue is full. This bit is cleared when space is available in the active queue. Do not set or reset this bit. It is informational only.

8–19

Note

Note

When the WQ bit is set, or when only the EN bit is set, and you are using a MSG

Write instruction, your source data is unbuffered. If your application requires buffered (or “snapshot”) data, wait until the EW bit is set before overwriting your source data.

EN = 1 and EW = 1 when MSG gets in the buffer

EN = 1 when MSG gets into queue

WQ = 1 when queue (which holds 10 MSGs) is full: buffer – holds 4 messages with data queue – stores pointer (waiting list)

If your program contains four message instructions assigned to the same channel with the Continuous Operation (CO) bit set, no other message instructions can be executed out that same channel, including message instructions which may be in the fault routine.

The amount of data transferred via a MSG instruction is determined by the size of the destination data type. The limit is 103 words (206 bytes) of data. If a read is used, then the data type in the processor determines the number of elements. If a write, is used then the data type in the remote device determines the number of elements. For example, if a read of counter values from a remote device is done and the destination in the processor is an integer file, then the maximum number of elements that can be requested are 103. The data will come from the first 103 words of the remote counter file.

In contrast, if a read of counter values from a remote device is done and the destination in the processor is a counter file, the maximum number of elements that can be requested is 34, because each counter element contains 3 words.

8–20

SLC Communication Instructions

MSG Instruction Control Block

Limitations for Manipulating the Control Block Bits

Do not manipulate the MSG instruction control block values except as noted below.

For example, do not clear the first word of the control block, do not unlatch the time-out control bit, and so on.

The only MSG instruction control bits that may be manipulated by the ladder program without adversely affecting the operation of the instruction are the CO, EN, and TO bits. The enable bit (EN = bit 15) may be unlatched, but only when the done bit (DN = bit 13) or error bit (ER = bit 12) has been set, indicating the successful or unsuccessful completion of the previous message.

In addition, when a MSG is in progress and the ladder program wishes to terminate it for any reason, this may be done by enabling the time-out bit (TO = bit 8). The next time the processor scans the MSG instruction with the TO bit set, it will error the MSG (ER = 1). The MSG instruction may then be re-enabled with a false-to-true transition on the next program scan.

Control Block Layouts

The control block layout is shown below for 500CPU or PLC-5 as the target device:

Read or Write, Local or Remote to a 500CPU or PLC-5

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

EN ST DN ER CO EW NR TO Error Code

Node Number

Reserved for length in words

File Number

File Type (O, I, S, B, T, C, R, N, F, St, A)

Element Number

Subelement Number

Reserved (Internal Messaging Bits)

Message Timer Preset

Message Timer Scaled Zero

Message Timer Accumulator

Reserved (Internal use only)

Reserved (Internal use only)

Reserved (Internal use only)

WQ 7

8

9

10

11

12

13

4

5

2

3

Word

0

1

6

8–21

8–22

The control block layout is shown below for 485CIF as the target device:

Read or Write, Local or Remote to a 485CIF

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

EN ST DN ER CO EW NR TO Error Code

Node Number

Reserved for length in words

Offset in Words

Not Used

Not Used

Not Used

Reserved (Internal Messaging Bits) WQ

6

7

4

5

Word

0

1

2

3

Message Timer Preset

Message Timer Scaled Zero

Message Timer Accumulator

Reserved (Internal use only)

Reserved (Internal use only)

Reserved (Internal use only)

11

12

13

8

9

10

SLC Communication Instructions

SLC 5/05 Message Instruction Overview

Operation

For SLC 5/05 processor Channel 0 communications, the MSG instruction operates the same as it does for the SLC 5/04 (OS401, FRN5 or later) except that the

SLC 5/05 also supports logical ASCII addressing for PLC-5 typed read and write messages, which increases the control block size from 14 to 56 words. The

SLC 5/05 Channel 1 is dedicated to Ethernet communications and functions as described in the following sections.

Ethernet Connections

TCP/IP is the mechanism used to transport Ethernet messages. On top of TCP, the

Client/Server Protocol is required to establish sessions and to send the MSG commands. Connections can be initiated by either a client program

(INTERCHANGE or RSLinx application) or a processor.

Important:

The client program or processor must first establish a connection to the SLC 5/05 to enable the SLC 5/05 to receive solicited messages from a client program or another processor. The client program must also establish a connection to the SLC 5/05 to enable the SLC 5/05 to send unsolicited messages to a client program.

In order to send a peer message, the SLC 5/05 must first establish a connection with the destination node at a specified IP address on the Ethernet network. A connection is established when a MSG instruction executes and no previous connection to the same device exists. When a MSG instruction executes, the

SLC 5/05 checks to see whether a connection has been established with the destination node. If a connection has not been established, the SLC 5/05 attempts to establish a connection of the peer type. The SLC 5/05 supports a maximum of 16 connections, allowing simultaneous communication with up to 16 other devices or applications. The connections are dedicated as follows:

Number of Connections

Dedicated to:

4

4 peer messages client messages

8 either peer or client messages

Connections established by an INTERCHANGE client, RSLinx client, and peers are all included when counting the number of connections.

For peer connections, no more that one connection per destination node is established. If multiple MSG instructions use the same destination node, they share the same connection.

8–23

Ethernet MSG Instruction Parameters

The control block is where all of the information relating to the message is stored.

As will be ilustrated, the Ethernet MSG control block length exceeds the normal 14 words used for DH+, DH-485, and serial link MSG instructions.

Attention: While configuring MSG instructions for the DH+ and serial links,

keep in mind the files used for Ethernet MSG control blocks.

If you choose a file being used as an Ethernet control block, the programming software prompts you to choose whether you want to overwrite the file. If you choose to overwrite the file, unpredictable machine operation could occur.

After entering the control block, the programming terminal automatically displays a data entry screen, from which you enter instruction parameters that are stored at the control block address.

The table below describes MSG instruction parameters for Ethernet.

Parameter

Supported MSG Commands

Message Sizes (Channel 1)

Modifying Connections

Value

485 CIF Read

485 CIF Write

PLC5 Typed Read

PLC5 Typed Write

SLC 500 CPU Read

SLC 500 CPU Write

256 words maximum, with two exceptions:

PLC5 Type MSG, Timer File – 201 elements maximum

All MSG Types, String File – 23 elements maximum

The user may change a MSG instruction destination while the processor is in the RUN mode. If a MSG instruction’s destination node changes, the next time the MSG instruction executes, a new connection is established with the new destination node. The old connection will remain open as long as either another MSG instruction was sharing it, or the connection inactive timer has not expired.

8–24

SLC Communication Instructions

MSG Instruction Control Block

Limitations for Manipulating the Control Block Bits

Do not manipulate the MSG instruction control block values except as noted below..

For example, do not clear the first word of the control block, do not unlatch the time-out control bit, and so on.

The only MSG instruction control bits that may be manipulated by the ladder program without adversely affecting the operation of the instruction are the CO, EN, and TO bits. The enable bit (EN = bit 15) may be unlatched, but only when the done bit (DN = bit 13) or error bit (ER = bit 12) has been set, indicating the successful or unsuccessful completion of the previous message.

In addition, when a MSG is in progress and the ladder program wishes to terminate it for any reason, this may be done by enabling the time-out bit (TO = bit 8). The next time the processor scans the MSG instruction with the TO bit set, it will error the MSG (ER = 1). The MSG instruction may then be re-enabled with a false-to-true transition on the next program scan.

Control Block Layouts

The SLC 5/05 MSG control block length varies with the type of communication and with the addressing you use. Control block layouts are shown for:

SLC 5/05 Channel 0 (RS-232 port)

MSG Control Block without Logical ASCII Addressing

SLC 5/05 Channel 0 (RS-232 port)

MSG Control Block with Logical ASCII Addressing

valid for PLC-5 typed read or write only

SLC 5/05 Channel 1 (Ethernet port)

MSG Control Block without Logical ASCII Addressing

SLC 5/05 Channel 1 (Ethernet port)

MSG Control Block with Logical ASCII Addressing

valid for PLC-5 typed read or write only

The AO bit (word 12, bit 15) is used for PCL-5 type reads and writes. If AO bit is reset to 0, then logical binary addressing is used for PLC-5 type reads and writes. If

AO is set to 1, then logical ASCII addressing is selected; in this case the processor expects the ASCII address string information to be stored in words 14 to 55 of the

MSG control block (see control block layouts on pages 8–26 and 8–28). The AO bit

has no meaning for 485CIF and 500CPU types of reads and writes.

8–25

8–26

SLC 5/05 Channel 0 (RS-232 port)

MSG Control Block without Logical ASCII Addressing

WORD 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

0

EN ST DN ER CO EW NR TO Error Code

1

Target Node

2

Number of Elements

3

Not Used

4

File Type (based on local source or destination address)

5

Not Used

6

Not Used

7

Reserved (Internal Messaging Bits)

8

Message Timer Preset

9

Message Timer Scaled Zero

10

Message Timer Accumulator

11

Data Length in Bytes

12

AO=0

13

Reserved

Reserved (Internal Messaging Bits) Internal Use Only

WQ

SLC 5/05 Channel 0 (RS-232 port)

MSG Control Block with Logical ASCII Addressing

valid for PLC-5 typed read or write only

WORD 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

0

EN ST DN ER CO EW NR TO Error Code

1

Target Node

2

Number of Elements

3

Not Used

4

File Type (based on local source or destination address)

5

Not Used

6

Not Used

7

Reserved (Internal Messaging Bits)

8

Message Timer Preset

9

Message Timer Scaled Zero

10

Message Timer Accumulator

11

Data Length in Bytes

12

AO=1 Reserved (Internal Messaging Bits)

15

First Byte of Address String

16

Third Byte of Address String

55

Eighty-First Byte of ASCII Address String

Internal Use Only

13

Reserved

14

Logical ASCII Address String Length including NULL Termination Character (bytes)

Second Byte of Address String

NULL Byte of Longest ASCII Address String

WQ

SLC Communication Instructions

SLC 5/05 Channel 1 (Ethernet port)

MSG Control Block without Logical ASCII Addressing

WORD 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

0

EN ST DN ER CO EW NR TO Error Code

1

Reserved (Target Node Not Used)

2

Number of Elements

3

Not Used

4

File Type (based on local source or destination address)

5

Not Used

6

Not Used

7

Reserved (Internal Messaging Bits)

8

Message Timer Preset

9

Message Timer Scaled Zero

10

Message Timer Accumulator

11

Data Length in Bytes

WQ

Reserved

12

AO=0 Reserved (Internal Messaging Bits)

13

Reserved

14

First Byte of IP Address String

15

Third Byte of IP Address String

34

Forty-First Byte of IP Address String

35

Reserved

36–50

Reserved for Future Use

Second Byte of IP Address String

NULL Byte of Longest IP Address String

Reserved (Ethernet Message Type); must be 0

The IP Address string format is up to 42 ASCII characters including a terminating NULL character. The first byte in the array is the left most character in the string as written. For example: If the IP Address is 423.156.78.012, the first byte is the ASCII character “4”. If the MSG destination is an INTERCHANGE client on a host computer, the destination is specified as “client” and stored as a NULL terminated string.

8–27

8–28

SLC 5/05 Channel 1 (Ethernet port)

MSG Control Block with Logical ASCII Addressing

valid for PLC-5 typed read or write only

14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 WORD 15

0

EN ST DN ER CO EW NR TO

1

Reserved (Target Node Not Used)

Error Code

2

Number of Elements

3

Not Used

4

File Type (based on local source or destination address)

5

Not Used

6

Not Used

7

Reserved (Internal Messaging Bits)

8

Message Timer Preset

9

Message Timer Scaled Zero

10

Message Timer Accumulator

11

Data Length in Bytes

12

AO=1 Reserved (Internal Messaging Bits)

15

First Byte of ASCII Address String

16

Third Byte of ASCII Address String

55

Eighty-First Byte of ASCII Address String

56

First Byte of IP Address String

Reserved

13

Reserved

14

Logical ASCII Address String Length including NULL Termination Character (bytes)

Second Byte of ASCII Address String

NULL Byte of Longest ASCII Address String

57

Third Byte of IP Address String

76

Forty-First Byte of IP Address String

77

Reserved

78–92

Reserved for Future Use

Second Byte of IP Address String

NULL Byte of Longest IP Address String

Reserved (Ethernet Message Type); must be 0

WQ

The IP Address string format is up to 42 ASCII characters including a terminating NULL character. The first byte in the array is the left most character in the string as written. For example: If the IP Address is 423.156.78.012, the first byte is the ASCII character “4”. If the MSG destination is an INTERCHANGE client on a host computer, the destination is specified as “client” and stored as a NULL terminated string.

SLC Communication Instructions

Interpreting Ethernet Status Data

Monitor the status of SLC 5/05 processors by accessing the Ethernet channel 1 status screen of your programming software.

Ethernet

Channel 1 Diagnostic Counters

Commands

sent: received:

Replies

sent: received

sent with error: received with error:

timed out:

Ethernet

In Octets: Out Octets:

In Packets: Out Packets:

alignment errors: FCS errors:

carrier sense errors excessive collisions:

excessive deferrals MAC receive errors:

MAC transmit errors single collisions

multiple collisions deferred transmission:

late collisions

The diagnostic counter data displayed is stored in the diagnostic file defined on the

Ethernet channel 1 configuration screen.

8–29

Status field:

Commands sent

Replies received sent

Ethernet received sent with error received with error timed out

In Octets

Out Octets

In Packets

Out Packets alignment errors

FCS errors carrier sense excessive excessive

MAC

MAC single multiple deferred late errors collisions deferrals receive transmit errors collisions collisions transmission collisions errors

Bytes: Displays the number of:

0-3 Commands sent by the channel

4-7

8-11

Commands received by the channel

Replies sent by the channel

12-15

16-19

20-23

24-27

28-31

32-35

36-39

40-43

44-47

48-51

52-55

56-59

60-63

64-67

Replies received by the channel

Replies containing errors sent by the channel

Replies containing errors received by the channel

Replies not received within the specified timeout period

Octets received on the channel

Octets sent on the channel

Packets received on the channel, including broadcast packets

Packets sent on the channel, including broadcast packets

Frames received on the channel that are not an integral number of octets in length

Frames received on the channel that do not pass the FCS check

Times that the carrier sense condition was lost or never asserted while trying to transmit a frame

Frames for which a transmission fails due to excessive collisions

Frames for which transmission is deferred for an excessive period of time

68-71

72-75

76-79

80-83

84-87

Frames for which reception on an interface fails due to internal MAC sublayer receive error

Frames for which reception on an interface fails due to internal MAC sublayer transmit error

Successfully transmitted frames for which transmission was delayed because of collision.

Successfully transmitted frames for which transmission was delayed more than once because of collision.

Frames for which the first transmission attempt is delayed because the medium is busy

Times that a collision is detected later than 512 bit-times into the transmission of a packet

8–30

SLC Communication Instructions

MSG Instruction Error Codes

When the processor detects an error during the transfer of message data, the processor sets the .ER bit and enters an error code that you can monitor from your programming software.

20H

30H

37H

38H

40H

50H

60H

70H

04H

15H

16H

17H

18H

19H

10H

11H

12H

13H

05H

06H

07H

08H

09H

0AH

0BH

0CH

Error

Code

02H

03H

Description of Error Condition

Target node is busy. The MSG instruction will automatically reload. If other messages are waiting, the message is placed at the bottom of the stack.

Target node cannot respond because message is too large.

Target node cannot respond because it does not understand the command parameters OR the control block may have been inadvertently modified.

Local processor is offline (possible duplicate node situation).

Target node cannot respond because requested function is not available.

Target node does not respond.

Target node cannot respond.

Local modem connection has been lost.

Buffer unavailable to receive SRD reply.

Target node does not accept this type of MSG instruction.

Received a master link reset (one possible source is from the DF1 master).

Target node cannot respond because of incorrect command parameters or unsupported command.

Local file has constant file protection.

Local channel configuration protocol error exists.

Local MSG configuration error in the Remote MSG parameters.

Local channel configuration parameter error exists.

Target or Local Bridge address is higher than the maximum node address.

Local service is not supported.

Broadcast (Node Address 255) is not supported.

Improperly formatted Logical ASCII Address string. String not properly terminated with a NULL character or the string length does not match the value in the length parameter.

PCCC Description: Host has a problem and will not communicate.

PCCC Description: Remote station host is not there, disconnected, or shutdown.

Message timed out in local processor.

Message disabled pending link response.

PCCC Description: Host could not complete function due to hardware fault.

Target node is out of memory.

Target node cannot respond because file is protected.

PCCC Description: Processor is in Program Mode.

8–31

8–32

E9H

EAH

EBH

ECH

EDH

EEH

EFH

F0H

D8H

D9H

DAH

E1H

E2H

E3H

E4H

E5H

D1H

D2H

D3H

D4H

D5H

D7H

Error

Code

80H

90H

B0H

C0H

D0H

E6H

E7H

E8H

Description of Error Condition

PCCC Description: Compatibility mode file missing or communication zone problem.

PCCC Description: Remote station cannot buffer command.

PCCC Description: Remote station problem due to download.

PCCC Description: Cannot execute command due to active IPBs.

No IP address configured for the network, -or-

Bad command – unsolicited message error, -or-

Bad address – unsolicited message error, -or-

No privilege – unsolicited message error

Maximum connections used – no connections available

Invalid internet address or host name

No such host / Cannot communicate with the name server

Connection not completed before user-specified timeout

Connection timed out by the network

Connection refused by destination host

Connection was broken

Reply not received before user-specified timeout

No network buffer space available

PCCC Description: Illegal Address Format, a field has an illegal value.

PCCC Description: Illegal Address format, not enough fields specified.

PCCC Description: Illegal Address format, too many fields specified.

PCCC Description: Illegal Address, symbol not found.

PCCC Description: Illegal Address Format, symbol is 0 or greater than the maximum number of characters support by this device.

PCCC Description: Illegal Address, address does not exist, or does not point to something usable by this command.

Target node cannot respond because length requested is too large.

PCCC Description: Cannot complete request, situation changed (file size, for example) during multi-packet operation.

PCCC Description: Data or file is too large. Memory unavailable.

PCCC Description: Request is too large; transaction size plus word address is too large.

Target node cannot respond because target node denies access.

Target node cannot respond because requested function is currently unavailable.

PCCC Description: Resource is already available; condition already exists.

PCCC Description: Command cannot be executed.

PCCC Description: Overflow; histogram overflow.

PCCC Description: No access

Note

SLC Communication Instructions

F7H

F8H

F9H

FAH

FBH

FCH

FDH

Error

Code

F1H

F2H

F3H

F4H

F5H

F6H

FFH

Description of Error Condition

Local processor detects illegal target file type.

PCCC Description: Invalid parameter; invalid data in search or command block.

PCCC Description: Address reference exists to deleted area.

PCCC Description: Command execution failure for unknown reason; PLC-3 histogram overflow.

PCCC Description: Data conversion error.

PCCC Description: The scanner is not able to communicate with a 1771 rack adapter. This could be due to the scanner not scanning, the selected adapter not being scanned, the adapter not responding, or an invalid request of a “DCM BT (block transfer)”.

PCCC Description: The adapter is not able to communicate with a module.

PCCC Description: The 1771 module response was not valid – size, checksum, etc.

PCCC Description: Duplicated Label.

Target node cannot respond because another node is file owner (has sole file access).

Target node cannot respond because another node is program owner (has sole access to all files).

PCCC Description: Disk file is write protected or otherwise inaccessible (off-line only).

PCCC Description: Disk file is being used by another application; update not performed (off-line only).

Local communication channel is shut down.

For 1770–6.5.16 DF1 Protocol and Command Set Reference Manual users:

The MSG error code reflects the STS field of the reply to your MSG instruction.

Codes E0 – EF represent EXT STS codes 0 – F.

Codes F0 – FC represent EXT STS codes 10 – 1C.

8–33

Timing Diagram for SLC 5/03, SLC 5/04, and SLC 5/05

MSG Instruction

The following section describes the timing diagram for a SLC 5/03, SLC 5/04, or

SLC 5/05 MSG instruction.

Rung goes True Target node receives packet

Target node processes packet successfully and returns data (read) or writes data (success)

EN

1

0

EW

1

0

ST

1

0

DN

ER

1

0

1

0

NR

1

0

TO

WQ

1

0

1

0

1.

When the MSG rung becomes true and the MSG is scanned, if there is room in any of the four active MSG buffers, the EN and EW bits are set. If this were a

MSG Write instruction, the source data would be transferred to the MSG buffer at this time. If there is no room in the four MSG buffers, but a position is available in the 10-position MSG Queue, only the EN bit is set. The

10-position MSG Queue works on a first-in-first-out basis that allows the SLC processor to remember the order the MSG instructions were enabled. Note that the program does not have access to the SLC MSG Queue.

If there is no room in any of the four MSG buffers and no room in the

10-position MSG Queue, only the WQ bit is set. Note that when the WQ bit is set, the MSG instruction must be re-scanned with true rung conditions at a later time when there is room in either the four MSG buffers or the 10-position MSG

Queue.

8–34

SLC Communication Instructions

Once the EN bit is set, it remains set until the entire MSG process is complete and either the DN, ER, or TO bit is set. The MSG Timeout period begins timing when the EN bit is set. If the timeout period expires before the MSG instruction completes it function, the ER bit is set and an error code (37H) is placed in the MSG block to inform you of the timeout error.

If you choose to set the CO bit, your MSG instruction will “take up” permanent residence in one of the four active MSG buffers. The MSG instruction continues to re-transmit its data each time the DN or ER bit is set. If this were a

MSG Write instruction, your source data would be updated each MSG cycle.

2.

At the next end of scan or SVC, the SLC processor determines if it should examine the MSG Queue for “something to do.” The processor bases its decision on the state of bits S:2/15, S:33/7, S:33/5, S:33/6, network communication requests from other nodes, and if previous MSG instructions are already in progress. If the SLC processor determines that it should not access the queue, the MSG instruction remains as it was. (Either the EN and EW bits remain set, or only the EN bit is set, or only the WQ bit is set until the next end of scan or SVC. If only the WQ bit is set, the MSG instruction must be re-scanned later with true rung conditions.)

If the SLC processor determines that it has “something to do,” it unloads the

MSG Queue entries into the MSG buffers until all four MSG buffers are full.

Each MSG buffer contains a valid network packet. If a packet cannot be successfully built from the MSG Queue, the ER bit is set and a code is placed in the MSG block to inform you of an error. When a MSG instruction is loaded into a MSG buffer, the EN and EW bits are set.

The SLC processor then exits the end of scan or SVC portion of the scan. The processor’s background communication function sends the packets to the Target

Nodes that you specified in your MSG instruction. Depending on the state of bits S:2/15, S:33/7, S:33/5, and S:33/6 you can have up to four MSG instructions active at any given time (eight MSG instructions for SLC 5/03

OS301 or higher, SLC 5/04, and SLC 5/05 processors).

3.

If the Target Node successfully receives the packet, it sends back an ACK

(acknowledge). The ACK causes the processor to clear the EW bit and set the

ST bit. The Target Node has not yet examined the packet, to see if it understands your request. Note that the Target Node is not required to respond within any give time frame.

For SLC 5/05 Ethernet communication, there is no ACK/NAK mechanism. The

ST bit is set when the Ethernet daughterboard internally indicates it has received the command from the main processor and will send it out. Skip step 4 for

SLC 5/05 processors.

8–35

Note

If the Target Node faults or power cycles during this time frame of a MSG transaction, you will never receive a reply. This is why it is recommended to use a MSG Timeout value in your MSG instruction.

Step 4 not shown in the timing diagram.

4.

If you do not receive an ACK, step 3 does not occur. Instead either no response a NAK (no acknowledge) is received. When this happens, the ST bit remains clear.

No response may be caused by:

• the target node is not there

• the target node does not respond because the packet became too corrupted in tranmission to be properly received

• the response was corrupted in transmission back

A NAK may be caused by:

• target node is too busy

• target node received a corrupt packet.

When a NAK occurs, the EW bit is cleared and the NR bit is set for one scan.

The next time the MSG instruction is scanned, the ER bit is set and the NR bit is cleared. This indicates that the MSG instruction failed. Note that if the

Target Node is too busy, the ER bit is not set. Instead, the MSG instruction re-queues itself for re-transmission.

5.

Following the successful receipt of the packet, the Target Node sends a reply packet. The reply packet will contain one of the following responses:

I have successfully performed your write request.

I have successfully performed your read request, and here is your data.

I have not performed your request, you are in error.

At the next end of scan or SVC, following the Target Node’s reply, the SLC processor examines the packet from the target device. If the reply contains “I have successfully performed your write request,” the DN bit is set and the ST bit is cleared. The MSG instruction function is complete. If the MSG rung is false, the EN bit is cleared the next time the MSG instruction is scanned.

If the reply contains “I have successfully performed your read request, and here is your data,” the data is written to the data table, the DN bit is set and the ST bit is cleared. The MSG instruction function is complete. If the MSG rung is false, the EN bit is cleared the next time the MSG instruction is scanned.

8–36

SLC Communication Instructions

If the reply contains “I have not performed your request, you are in error,” the

ER bit is set and the ST bit is cleared. The MSG instruction function is complete. If the MSG rung is false, the EN bit is cleared the next time the MSG instruction is scanned.

The four MSG buffers are shared between channel 0 and channel 1 for SLC 5/03

OS300 processors. For SLC 5/03 (OS301 and higher), SLC 5/04, and SLC 5/05 processors, there are four MSG buffers per channel. Each channel has its own

10-position MSG Queue. The SLC processor unloads the two MSG queues into the

MSG buffers evenly at end of scan or SVC. This allows both channels equal access to communications. If you program a SVC instruction that is configured to service only one channel, then only that channel will have its MSG Queue unloaded into the

MSG buffers (until the next end of scan or SVC when both channels will again be unloaded evenly).

Examples: Ladder Logic

Enabling the MSG Instruction Via Ladder Logic

0000

The MSG instruction will be enabled during the initial processor program scan, and each time the MSG completes, i.e. when the DN or ER bit is set.

MSG

Read/Write Message

Type

Read/Write

Peer-to-Peer

Target Device

Local/Remote

Read

500CPU

Local

Control Block N7:0

Control Block Length 14

Setup Screen

(EN)

(DN)

(ER)

0001

MSG Done Bit

N7:0

] [

13

MSG Error Bit

N7:0

] [

12

MSG Enable Bit

N7:0

(U)

15

0002

END

8–37

Enabling the MSG Instruction Via User Supplied Input

0000

As long as input I:1/0 is set, or anytime it becomes set, the MSG instruction in the next rung will be enabled. This program is an example of controlling when the MSG instruction operates. Input I:1/0 could be any user supplied bit used to control when MSGs are sent.

I:1

] [

0

MSG Enable Bit

N7:0

]/[

15

B3:0

(L)

0

0001

0002

0003

The MSG instruction will be enabled with each false-to-true transition of bit B3:0/0.

B3:0

] [

0

MSG

Read/Write Message

Type

Read/Write

Peer-to-Peer

Target Device

Local/Remote

500CPU

Local

Control Block N7:0

Control Block Length 14

Setup Screen

Read

MSG Done Bit

N7:0

] [

13

B3:0

(U)

0

(EN)

(DN)

(ER)

MSG Error Bit

N7:0

] [

12

END

8–38

SLC Communication Instructions

Using Local Messaging

Example 1 – Local Read from a 500CPU

Type:

Read/Write:

Target Device:

Local/Remote:

Control Block:

Channel:

Target Node (decimal):

Peer–to–Peer

READ

500CPU

Local

N10:0

0

2

Destination File Addr:

Target Source File Address:

Message Length In Elements:

Message Timeout (seconds):

ERROR CODE: 0

Error Code Desc:

N7:0

N7:50

10

5 ignore if timed out: 0 TO to be retried: 0 NR awaiting execution: 0 EW continuous run: 0 CO error: 0 ER message done: 0 DN message transmitting: 0 ST message enabled: 0 EN waiting for queue space: 0 WQ control bit address: N10:0/8

Function Key

Target Node

Message Length

Message Timeout

Channel

In the display above the SLC 5/03 or SLC 5/04 processor reads 10 elements from

Target Node 2’s N7 file, starting at word N7:50. The 10 words are placed in your integer file starting at word N7:0. If five seconds elapse without a reply, error bit

N10:0/12 is set, indicating that the instruction timed out. The device at node 2 understands the SLC 500 processor family (SLC 500, SLC 5/01, SLC 5/02,

SLC 5/03, SLC 5/04, SLC 5/05 and MicroLogix 1000) protocol.

Description

Specifies the node number of the processor that is receiving the message. Valid range is 0–31 for

DH–485 protocol, or 0–254 for DF1 protocol.

For a Read (Destination) this is the address in the initiating processor which is to receive data.

For a Write (Source) this is the address in the initiating processor which is to send data.

Valid file types are S, B, T, C, R, N, I, O, M0, M1, F, ST, and A.

For a Read (Source) this is the address in the target processor which is to send data.

For a Write (Destination) this is the address in the target processor which is to receive data.

Valid file types are S, B, T, C, R, N, I, O, M0, M1, F, ST and A.

Defines the length of the message in elements. One word elements are limited to a maximum length of 1–103. Three word elements are limited to a maximum length of 1–37.

Defines the length of the message timer in seconds. A timeout of 0 seconds means that there is no timer and the message will wait indefinitely for a reply. Valid range is 0–255 seconds.

Identifies the physical channel used for the message communication. Available channels:

SLC 5/03 – (Channel 0, RS–232) or (Channel 1, DH–485)

SLC 5/04 – (Channel 0, RS–232) or (Channel 1, DH

+

)

SLC1 5/05 – (Channel 0, RS-232) or (Channel 1, Ethernet)

8–39

Example 2 – Local Read from a 485CIF

Type:

Read/Write:

Target Device:

Local/Remote:

Control Block:

Channel:

Target Node (decimal):

Peer–to–Peer

READ

485CIF

Local

N10:0

0

2

Destination File Addr:

Target Offset:

Message Length In Elements:

Message Timeout (seconds):

ERROR CODE: 0

Error Code Desc:

N7:0

20

5

15 ignore if timed out: 0 TO to be retried: 0 NR awaiting execution: 0 EW continuous run: 0 CO error: 0 ER message done: 0 DN message transmitting: 0 ST message enabled: 0 EN waiting for queue space: 0 WQ control bit address: N10:0/8

Function Key

Target Node

Target Offset

Message Length

Message Timeout

Channel

In the display above the SLC processor reads five elements (words) from Target

Node 2’s CIF file, starting at word 20 (or byte 20 for non–SLC 500 devices). The five elements are placed in your integer file starting at word N7:0. If 15 seconds elapse without a reply, error bit N10:0/12 is set, indicating that the instruction timed out. The device at node 2 understands the 485CIF (PLC–2 emulation) protocol.

Description

Specifies the node number of the processor that is receiving the message. Valid range is 0–31 for

DH-485 protocol, or 0–254 for DF1 protocol.

For a Read (Destination) this is the address in the initiating processor which is to receive data.

For a Write (Source) this is the address in the initiating processor which is to send data.

Valid file types are S, B, T, C, R, N, I, O, M0, M1, F, ST, and A.

For a Read or Write this is the word offset value in the common interface file (byte offset for non–SLC device).

When using a 485CIF Message instruction, the message length is the number of 16-bit words. You can specify 1 to 103 elements (words of information).

Defines the length of the message timer in seconds. A timeout of 0 seconds means that there is no timer and the message will wait forever for a reply. Valid range is 0–255 seconds.

Identifies the physical channel used for the message communication. Available channels:

SLC 5/03 – (Channel 0, RS–232) or (Channel 1, DH–485)

SLC 5/04 – (Channel 0, RS–232) or (Channel 1, DH

+

)

SLC 5/05 – (Channel 0, RS-232) or (Channel 1, Ethernet)

8–40

SLC Communication Instructions

Example 3 – Local Read from a PLC-5

Type:

Read/Write:

Target Device:

Local/Remote:

Control Block:

Channel:

Target Node (decimal):

Peer–to–Peer

READ

PLC5

Local

N10:0

0

2

Destination File Addr:

Target Src/Dst File Address:

Message Length In Elements:

Message Timeout (seconds):

ERROR CODE: 0

Error Code Desc:

N7:0

N7:50

10

5 ignore if timed out: 0 TO to be retried: 0 NR awaiting execution: 0 EW continuous run: 0 CO error: 0 ER message done: 0 DN message transmitting: 0 ST message enabled: 0 EN waiting for queue space: 0 WQ control bit address: N10:0/8

Function Key

Target Node

Message Length

Message Timeout

Channel

In the display above the SLC 5/03 or SLC 5/04 processor reads 10 elements from

Target Node 2’s N7 file, starting at word N7:50. The 10 words are placed in your integer file starting at word N7:0. If five seconds elapse without a reply, error bit

N10:0/12 is set, indicating that the instruction timed out. The device at node 2 understands the PLC-5 processor protocol.

Description

Specifies the node number of the processor that is receiving the message. Valid range is 0–31 for

DH-485 protocol, or 0–254 for DF1 protocol.

For a Read (Destination) this is the address in the initiating processor which is to receive data.

For a Write (Source) this is the address in the initiating processor which is to send data.

Valid file types are S, B, T, C, R, N, I, O, F, ST, and A.

For a Read (Source) this is the address in the target processor which is to send data.

For a Write (Destination) this is the address in the target processor which is to receive data.

Valid file types are S, B, T, C, R, N, I, O, F, ST, and A.

Defines the length of the message in elements. One word elements are limited to a maximum length of 1–103. Three word elements are limited to a maximum length of 1–37.

Defines the length of the message timer in seconds. A timeout of 0 seconds means that there is no timer and the message will wait indefinitely for a reply. Valid range is 0–255 seconds.

Identifies the physical channel used for the message communication. Available channels:

SLC 5/03 – (Channel 0, RS–232) or (Channel 1, DH–485)

SLC 5/04 – (Channel 0, RS–232) or (Channel 1, DH

+

)

SLC 5/05 – (Channel 0, RS-232) or (Channel 1, Ethernet)

8–41

Using Remote Messaging

The SLC 5/03 and higher processors can pass a MSG instruction through one remote network to its target destination. (You can make one hop across a network.)

The SLC 5/03 and higher processors can also pass a MSG instruction to the network that exists on the other side of the local bridge.

Example 1 – Communicating with A–B processors using a 1785-KA5

Node 1

(oct)

Device A

Node 2

Device B

DH-485 Node 7

SLC 5/04

Modular I/O Controller

DH

+

Link ID = 2

(57.6KBaud)

Node 3

(oct)

DH+ Node 6

(oct)

DH-485

Link ID = 1

(19.2KBaud)

PLC–5/40 with1785–KA5

Module

DH

+

Link ID = 2

(57.6KBaud)

Device C

SLC 5/03

Modular I/O Controller

8–42

SLC 5/04 Processor (A) to SLC 5/03 Processor (C) via 1785-KA5

Type:

Read/Write:

Target Device:

Local/Remote:

Control Block:

Channel:

Target Node (decimal):

Remote Bridge Link Id <dec>:

Remote Bridge Node Address <dec>:

Local Bridge Node Address <dec>:

Destination/Source File Addr:

Target Src/Dst File Address:

Message Length In Elements:

Message Timeout (seconds):

Peer–to–Peer

Read

500 CPU

Remote user specified

1

2

1

0

6 user specified user specified user specified user specified

SLC Communication Instructions

Comments

Channel is set to 1 since the originating command is initiated by an SLC 5/04 processor on the DH+ (Link ID 2).

Target Node is the SLC 5/03 processor at node address 2.

Remote Bridge Link ID is the link ID of the remote DH-485 network with the

1785-KA5 and SLC 5/03 processor (Link ID 1).

Remote Bridge Node Address is set to 0 (not used) because communication is from one Internet-capable device to another Internet-capable device.

Local Bridge Node Address is set to 6 since this is the DH+ node address used by the 1785-KA5 communication interface module.

8–43

SLC 5/03 Processor (C) to SLC 5/04 Processor (A) via 1785-KA5

Type:

Read/Write:

Target Device:

Local/Remote:

Control Block:

Channel:

Target Node (decimal):

Remote Bridge Link Id <dec>:

Remote Bridge Node Address <dec>:

Local Bridge Node Address <dec>:

Destination/Source File Addr:

Target Src/Dst File Address:

Message Length In Elements:

Message Timeout (seconds):

Peer–to–Peer

Read

500 CPU

Remote user specified

1

1

2

0

7 user specified user specified user specified user specified

Comments

Channel is set to 1 since the originating command is initiated by an SLC 5/03 processor on the DH-485 (Link ID 1).

Target Node is the SLC 5/04 processor at node address 1.

Remote Bridge Link ID is the link ID of the remote DH+ network with the

1785-KA5 and the SLC 5/04 processor (Link ID 2).

Remote Bridge Node Address is set to 0 (not used) because communication is from one Internet-capable device to another Internet-capable device.

Local Bridge Node Address is set to 7 since this is the DH-485 node address used by the 1785-KA5 communication interface module.

8–44

SLC Communication Instructions

SLC 5/03 Processor (C) to a PLC-5 (B) via 1785-KA5

Type:

Read/Write:

Target Device:

Local/Remote:

Control Block:

Channel:

Target Node (decimal):

Remote Bridge Link Id <dec>:

Remote Bridge Node Address <dec>:

Local Bridge Node Address <dec>:

Destination/Source File Addr:

Target Src/Dst File Address:

Message Length In Elements:

Message Timeout (seconds):

Peer–to–Peer

Write

PLC5

Remote user specified

1

3

2

0

7 user specified user specified user specified user specified

Comments

Channel is set to 1 since the originating command is initiated by an SLC 5/03 processor on the DH-485 (Link ID 1).

Target Node is the PLC-5 processor at node address 3.

Remote Bridge Link ID is the link ID of the remote DH+ network with the

1785-KA5 and the PLC-5 processor (Link ID 2).

Remote Bridge Node Address is set to 0 (not used) because communication is from one Internet-capable device to another Internet-capable device.

Local Bridge Node Address is set to 7 since this is the DH-485 node address used by the 1785-KA5 communication interface module.

8–45

Example 2 – Communicating with A–B processors using two 1785-KAs

Device A

Node 22

(oct)

Device C

Node 220

(1785–KA)

Node 13

(oct)

SLC 5/04

Modular I/O Controller

DH

+

57.6KBaud

Node 3

(oct)

Device B

SLC 5/04

Modular I/O Controller

DH

+

57.6KBaud

PLC–5/40 with1785–KA

Module

Node 3

(oct)

Data Highway

Node 110

(1785-KA)

PLC–5/40 with1785–KA

Module

SLC 5/04 Processor (B) to PLC5 Processor (C) via two 1785–KAs

Type:

Read/Write:

Target Device:

Local/Remote:

Control Block:

Channel:

Target Node (decimal):

Remote Bridge Link Id <dec>:

Remote Bridge Node Address <dec>:

Local Bridge Node Address <dec>:

Destination/Source File Addr:

Target Src/Dst File Address:

Message Length In Elements:

Message Timeout (seconds):

Peer–to–Peer

Write

PLC5

Remote user specified

1

0

0

131

8 user specified user specified user specified user specified

Comments

Channel is set to 1 since the originating command is initiated by an SLC 5/04 processor on the DH+ network.

Target Node is the PLC-5 processor at node address 0. (This is actually node address 3, but the node address is set to 0 because the Remote Bridge Node address handles the addressing structure.)

Remote Bridge Link ID is set always set to 0 when using this addressing structure.

Remote Bridge Node Address is set to 131. The remote bridge node address consists of the most significant digit (octal) of the remote 1785-KA (220) plus the target node address. For example, 200 + 3 = 203 octal (131 decimal).

Local Bridge Node Address is set to 8 since this is the decimal equivalent of the two least significant digits of the 1785-KA address (10 octal).

8–46

SLC Communication Instructions

SLC 5/04 Processor (B) to SLC 5/04 Processor (A) via two 1785–KAs

Type:

Read/Write:

Target Device:

Local/Remote:

Control Block:

Channel:

Target Node (decimal):

Remote Bridge Link Id <dec>:

Remote Bridge Node Address <dec>:

Local Bridge Node Address <dec>:

Destination/Source File Addr:

Target Src/Dst File Address:

Message Length In Elements:

Message Timeout (seconds):

Peer–to–Peer

Write

500 CPU

Remote user specified

1

0

0

146

8 user specified user specified user specified user specified

Comments

Channel is set to 1 since the originating command is initiated by an SLC 5/04 processor on the DH+ network.

Target Node is the SLC 5/04 processor at node address 0. (This is actually node address 22, but the node address is set to 0 because the Remote Bridge Node address handles the addressing structure.)

Remote Bridge Link ID is always set to 0 when using this addressing structure.

Remote Bridge Node Address is set to 146. The remote bridge node address consists of the most significant digit (octal) of the remote 1785-KA plus the address of the target device. For example, 200 + 22 = 222 (146 decimal).

Local Bridge Node Address is set to 8 since this is the decimal equivalent of the two least significant digits of the 1785-KA address (10 octal).

8–47

Example 3 – Passthru via DH-485 Channel 0 of the SLC 5/04 Processor

Device B

Node 3

(oct)

Node 1

(oct)

PLC–5/40

Device A

DH

+

Link ID = 2

(57.6KBaud)

DH+ Node 2

(oct)

DH-485

Node 1

Device C

SLC 5/04

Modular I/O Controller

RS-232

1747–PIC

Interface Converter

DH-485

Link ID = 1

(19.2KBaud)

Node 2

(oct)

SLC 5/04

Modular I/O Controller

Device D

SLC 5/03

Modular I/O Controller

SLC 5/04 Processor (A) to SLC 5/03 Processor (D) via an SLC 5/04 Processor (C)

(Passthru using Channel 0 DH-485)

Type:

Read/Write:

Target Device:

Local/Remote:

Control Block:

Channel:

Target Node (decimal):

Remote Bridge Link Id <dec>:

Remote Bridge Node Address <dec>:

Local Bridge Node Address <dec>:

Destination/Source File Addr:

Target Src/Dst File Address:

Message Length In Elements:

Message Timeout (seconds):

Peer–to–Peer

Read

500 CPU

Remote user specified

1

2

1

0

2 user specified user specified user specified user specified

Comments

Channel is set to 1 since the originating command is initiated by an SLC 5/04 processor on the DH+ network.

Target Node is the SLC 5/03 processor at node address 2.

Remote Bridge Link ID is the link ID of the remote DH-485 network with the

SLC 5/04 processor (Channel 0, Link ID 1) and the SLC 5/03 processor (Channel 0,

Link ID 1).

Remote Bridge Node Address is set to 0 (not used) because communication is from one Internet-capable device to another Internet-capable device.

Local Bridge Node Address is set to 2 since this is the DH+ node address used by the passthru SLC 5/04 processor.

8–48

SLC Communication Instructions

SLC 5/03 Processor (D) to SLC 5/04 Processor (A) via an SLC 5/04 Processor (C)

(Passthru using Channel 0 DH–485)

Type:

Read/Write:

Target Device:

Local/Remote:

Control Block:

Channel:

Target Node (decimal):

Remote Bridge Link Id <dec>:

Remote Bridge Node Address <dec>:

Local Bridge Node Address <dec>:

Destination/Source File Addr:

Target Src/Dst File Address:

Message Length In Elements:

Message Timeout (seconds):

Peer–to–Peer

Read

500 CPU

Remote user specified

1

3

2

0

1 user specified user specified user specified user specified

Comments

Channel is set to 1 since the originating command is initiated by an SLC 5/03 processor on the DH-485 network.

Target Node is the SLC 5/04 processor at node address 1.

Remote Bridge Link ID is the link ID of the remote DH+ network with both

SLC 5/04 processors (Channel 1, Link ID 2).

Remote Bridge Node Address is set to 0 (not used) because communication is from one Internet-capable device to another Internet-capable device.

Local Bridge Node Address is set to 1 since this is the DH-485 node address used by the passthru SLC 5/04 processor.

8–49

SLC 5/03 Processor (D) to PLC-5 (B) via an SLC 5/04 Processor

(Passthru using Channel 0 DH-485)

Type:

Read/Write:

Target Device:

Local/Remote:

Control Block:

Channel:

Target Node (decimal):

Remote Bridge Link Id <dec>:

Remote Bridge Node Address <dec>:

Local Bridge Node Address <dec>:

Destination/Source File Addr:

Target Src/Dst File Address:

Message Length In Elements:

Message Timeout (seconds):

Peer–to–Peer

Write

PLC5

Remote user specified

1

3

2

0

1 user specified user specified user specified user specified

Comments

Channel is set to 1 since the originating command is initiated by an SLC 5/03 processor on the DH-485 network.

Target Node is the PLC-5 processor at node address 3.

Remote Bridge Link ID is the link ID of the remote DH+ network with the

SLC 5/04 processor (Channel 1, Link ID 2) and PLC-5 processor (Channel 1A, Link

ID 2).

Remote Bridge Node Address is set to 0 (not used) because communication is from one Internet-capable device to another Internet-capable device.

Local Bridge Node Address is set to 1 since this is the DH-485 node address used by the passthru SLC 5/04 processor.

8–50

SLC Communication Instructions

Remote Messaging (SLC 5/03 to a SLC 500, SLC 5/01, or SLC 5/02, or MicroLogix 1000)

The following illustration shows the connectivity for a remote message.

Node 2

1747–AIC

SLC 5/02

Modular I/O Controller

Node 6

1747–AIC

SLC 5/03

Modular I/O Controller

PLC with1785–KA5

Module

Node 1

Link ID = 1

Node 4

Node 7

Link ID = 3

Node 9

(11 octal)

PLC–5 with 1785–KA5

Module

Link ID = 2

Link ID = 3

Node 8

(10 octal)

Node 5

1747–AIC

Node 3

PLC–5

Node 2

T60

Industrial

Computer

1747–AIC

Node 1

Node 3

SLC 5/02

Modular I/O Controller

SLC 5/01

Modular I/O Controller

DH–485 Network maximum length 1200m (4,000 ft.)

DH

+

Network

The following callouts depict addressing parameters of a SLC 5/03 to a remote

SLC 5/02 processor.

This is the orginating node of the MSG instruction. You do not need to specify its address.

This is the Local Bridge Node Address.

This is the remote node address of the local bridge. You do not need to specify its address.

This is the Remote Bridge Node Address.

This is the remote node address of the remote bridge. You do not need to specify its address.

This is the Remote Link ID.

This is the Target Node Address.

8–51

8–52

Type:

Read/Write:

Target Device:

Local/Remote:

Control Block:

Channel:

Target Node (decimal):

Remote Bridge Link Id:

Remote Bridge Node Address <dec>:

Local Bridge Node Address <dec>:

Destination/Source File Addr:

Target Src/Dst File Address:

Message Length In Elements:

Message Timeout (seconds):

Peer–to–Peer

Read

500 CPU

Remote user specified

1

3

2

8

4 user specified user specified user specified user specified

SLC Communication Instructions

Example 4 – Passthru via DF1 Full-Duplex Channel 0 of the SLC 5/04 Processor

Device A Device B Device C

DH+

Node 0

(oct)

DH+

Node 2

(oct)

DH+

Node 35

(oct)

DH+

Node 77

(oct)

Device D

SLC 5/04

Modular I/O Controller

DH

+

Link ID = 2

(57.6KBaud)

SLC 5/04

Modular I/O Controller

S:34/5 = 1

DF1

(RS-232)

Link ID = 1

(19.2KBaud)

SLC 5/04

Modular I/O Controller

S:34/5 = 1

DH

+

Link ID = 3

(57.6KBaud)

SLC 5/04

Modular I/O Controller

SLC 5/04 Processor (A) to SLC 5/04 Processor (D) via two SLC 5/04 Processors

(Passthru using Channel 0 DF1 Full-Duplex)

Type:

Read/Write:

Target Device:

Local/Remote:

Control Block:

Channel:

Target Node (decimal):

Remote Bridge Link Id:

Remote Bridge Node Address <dec>:

Local Bridge Node Address <dec>:

Destination/Source File Addr:

Target Src/Dst File Address:

Message Length In Elements:

Message Timeout (seconds):

Peer–to–Peer

Read

500 CPU

Remote user specified

1

63

1

0

2 user specified user specified user specified user specified

Note

Improper configuration may cause data to be written to or read from an unintended processor. Make sure that all parameters and channel link IDs are set correctly, as well as bit S:34/5 being set in both passthru processors..

Comments

Channel is set to 1 since the originating command is initiated by an SLC 5/04 processor on the DH+ network.

Target Node is the SLC 5/04 processor at node address 77 (63 decimal).

Remote Bridge Link ID is the link ID of the DF1 full-duplex RS-232 connection between the passthru SLC 5/04 processors’ channel 0 (Link ID 1).

Remote Bridge Node Address is set to 0 (not used) because Channel 0 is DF1 full-duplex.

Local Bridge Node Address is set to 2 since this is the DH+ node address used by the local SLC 5/04 passthru processor.

8–53

Example 5 – Passthru via DH+ Channel 0 of the SLC 5/04 Processor

Device A Device B Device C

DH+

Node 77

(oct)

DH+

Node 2

(oct)

DH+

Node 35

(oct)

SLC 5/04

Modular I/O Controller

DH

+

Link ID = 2

(57.6KBaud)

SLC 5/04

Modular I/O Controller

S:34/5 = 1

DF1

(RS-232)

Link ID = 1

(19.2KBaud)

SLC 5/04

Modular I/O Controller

Note

Device B has S:34/5 set to 1. Device C must have S:34/5 cleared. Otherwise,

Device C would attempt to passthru this message packet to node 0 on its Channel 1

DH+ network instead of responding to the message.

SLC 5/04 Processor (A) to SLC 5/04 Processor (C) via a single SLC 5/04 Processor

(Passthru using Channel 0 DF1)

Type:

Read/Write:

Target Device:

Local/Remote:

Control Block:

Channel:

Target Node:

Remote Bridge Link Id <dec>:

Remote Bridge Node Address:

Local Bridge Node Address:

Destination/Source File Addr:

Target Src/Dst File Address:

Message Length In Elements:

Message Timeout (seconds):

Peer–to–Peer

Read

500 CPU

Remote user specified

1

0

1

0

2 user specified user specified user specified user specified

Comments

Channel is set to 1 since the originating command is initiated by an SLC 5/04 processor on the DH+ network.

Target Node is the SLC 5/04 processor at node address 0 (with DF1 full-duplex, any valid node address would work here).

Remote Bridge Link ID is the link ID of the passthru SLC 5/04 processor’s channel 0 (Link ID 1).

Remote Bridge Node Address is set to 0 (not used) because Channel 0 is DF1 full-duplex.

Local Bridge Node Address is set to 2 since this is the DH+ node address used by the local SLC 5/04 passthru processor.

8–54

SLC Communication Instructions

SLC 5/04 Processor (C) to SLC 5/04 Processor (A) via a single SLC 5/04 Processor

(Passthru using Channel 0 DF1)

Type:

Read/Write:

Target Device:

Local/Remote:

Control Block:

Channel:

Target Node (decimal):

Destination/Source File Addr:

Target Src/Dst File Address:

Message Length In Elements:

Message Timeout (seconds):

Peer–to–Peer

Read

500 CPU

Local user specified

0

63 user specified user specified user specified user specified

Comments

Channel is set to 0 since the originating command is initiated by an SLC 5/04 processor, connected via DF1 full-duplex.

Target Node is the SLC 5/04 processor at node address 63 decimal (77 octal).

SLC 5/04 Processor (C) to SLC 5/04 Processor (B) when Channel 0 DF1 Passthru is

Enabled

Type:

Read/Write:

Target Device:

Local/Remote:

Control Block:

Channel:

Target Node (decimal):

Peer–to–Peer

Read

500 CPU

Local user specified

0

2

Destination/Source File Addr:

Target Src/Dst File Address:

Message Length In Elements:

Message Timeout (seconds): user specified user specified user specified user specified

Comments

Channel is set to 0 since the originating command is initiated by an SLC 5/04 processor, connected via DF1 full-duplex.

Target Node is the SLC 5/04 processor at DH+ node address 2.

8–55

Example 6 – Passthu using a Pyramid Integrator for Routing a message instruction

Device A

Node 7

(oct)

SLC 5/04

Modular I/O Controller

DH

+

Link ID = 1

(57.6KBaud)

Station 3

Device B

Station 15

(oct)

DH

+

Link ID = 2

(57.6KBaud)

Node 1

(oct)

SLC 5/04

Modular I/O Controller

SLC 5/04 Processor (B) to SLC 5/04 Processor (A) via Pyramid Integrator using PI routing

Type:

Read/Write:

Target Device:

Local/Remote:

Control Block:

Channel:

Target Node:

Remote Bridge Link Id <dec>:

Remote Bridge Node Address:

Local Bridge Node Address:

Destination/Source File Addr:

Target Src/Dst File Address:

Message Length In Elements:

Message Timeout (seconds):

Peer–to–Peer

Read

500 CPU

Remote user specified

1

7

1

0

13 user specified user specified user specified user specified

Comments

Channel is set to 1 since the originating command is initiated by an SLC 5/04 processor on the DH+ network.

Target Node is the SLC 5/04 processor at node address 7.

Remote Bridge Link ID is the link ID of the remote DH+ network with the

SLC 5/04 processor (Channel 1, Link ID 1) and the Pyramid Integrator.

Remote Bridge Node Address is set to 0 (not used) because communication is from one Internet-capable device to another Internet-capable device.

Local Bridge Node Address is set to 13 decimal (15 octal) since this is the DH+ node address of the Pyramid Integrator on the local DH+ network.

8–56

SLC Communication Instructions

Example 7 – Passthu using Two 1785-KA5s

Device A

Node 10

SLC 5/03

Modular I/O Controller

Link ID = 6

DH-485

19.2KBaud

PLC–5/40 with1785–KA5

Module

Device D

Node 20

(1785–KA5)

Node 3

(oct)

Node 2

Device B

SLC 5/03

Modular I/O Controller

Link ID = 8

DH-485

19.2K baud

Link ID=4

DH+

57.6K baud

Device C

Node 10

(1785-KA5)

PLC–5/40 with1785–KA5

Module

SLC 5/03 Processor (A) to an SLC 5/03 Processor (B) (Using two 1785–KA5s)

Type:

Read/Write:

Target Device:

Local/Remote:

Control Block:

Channel:

Target Node:

Remote Bridge Link Id:

Remote Bridge Node Address:

Local Bridge Node Address:

Destination/Source File Addr:

Target Src/Dst File Address:

Message Length In Elements:

Message Timeout (seconds):

Peer–to–Peer

Read or Write

485CIF or 500 CPU

Remote user specified

1

2

8

0

20 user specified user specified user specified user specified

Comments

Channel is set to 1 since the command is sent from the SLC 5/03’s DH-485 channel onto local Link ID 4.

Target Node is set to 2 since this is the DH-485 address the destination device resides at on the destination link (Link ID 8).

Remote Bridge Link ID is set to 8 since this is the destination link that the destination device resides on.

Remote Bridge Node Address is set to 0 (not used) because communication is from one Internet-capable device to another Internet-capable device.

Local Bridge Node Address is set to 20 since it is the bridge device (Link ID 4) that the command is to be sent through (device D).

8–57

Service Communications (SVC)

✓ ✓ ✓ ✓ ✓

Using an SLC 5/02 Processor

(SVC)

Output Instruction

The SVC instruction is an output instruction that has no programming parameters.

When it is evaluated as true, the program scan is interrupted to execute the service communications part of the operating cycle. The scan then resumes at the instruction following the SVC instruction. Use this instruction to enhance the communication performance of your SLC 5/02 processor.

You are not allowed to place an SVC instruction in a STI interrupt, I/O interrupt, or user fault subroutine.

The following status bits allow you to customize or monitor communications

servicing. Refer to chapter 1 in this manual for additional information on the status

file.

S:2/5 DH-485 Incoming Command Pending

S:2/6 DH-485 Message Reply Pending

S:2/7 DH-485 Outgoing Message Command Pending

S:2/15 DH-485 Communications Servicing Selection

8–58

SLC Communication Instructions

Using SLC 5/03 and Higher Processors

SVC

SERVICE COMMUNICATIONS

Channel 0

Channel 1

Output Instruction

When using SLC 5/03 and higher processors, the SVC instruction operates as described above. These processors also allow you to select a specific communication channel (0, 1, or both) to be serviced. You are not allowed to place an SVC instruction in a Fault, DII, STI, or I/O Event subroutine.

SLC 5/03 processor

– channel 0 is RS-232/DF1 Full-Duplex or Half-Duplex (master or slave),

DH-485, or ASCII

– channel 1 is DH-485

SLC 5/04 processor

– channel 0 is RS-232/DF1 Full-Duplex or Half-Duplex (master or slave),

DH-485, or ASCII

– channel 1 is DH

+

SLC 5/05 processor

– channel 0 is RS-232/DF1 Full-Duplex or Half-Duplex (master or slave),

DH-485, or ASCII

– channel 1 is Ethernet

The following status bits allow you to customize or monitor communications

servicing. Refer to appendix B in this manual for additional information about the

status file.

S:2/5

S:2/6

Channel 1

Incoming Command Pending Bit

Message Reply Pending Bit

S:2/7 Outgoing Message Command

Pending Bit

S:2/15 Communications Servicing

Selection Bit

S:33/7 Message Servicing Selection Bit

Channel 0

S:33/0 Incoming Command Pending

S:33/1 Message Reply Pending

S:33/2 Outgoing Message Command

Pending

Selection

S:33/6 Message Servicing Selection

8–59

Channel Servicing

When a channel is not selected to be serviced by the SVC instruction, that channel is serviced normally at the end of the scan.

Application Example

The SVC instruction is used when you want to execute a communication function, such as transmitting a message, prior to the normal service communication portion of the operating scan. The following example shows how to selectively use the

SVC instruction.

Outgoing Message

Command Pending Bit

S:2

] [

7

(SVC)

Note

You can place this rung after a message write instruction. S:2/7 is set when the message instruction is enabled and waiting (provided no message is currently being transmitted). When S:2/7 is set, the SVC instruction is evaluated as true and the program scan is interrupted to execute the service communications portion of the operating scan. The scan then resumes at the instruction following the SVC instruction.

This simple example assumes that the Comms Servicing Selection bit S:2/15 is clear and that this is the only active MSG instruction.

You may program the SVC instruction unconditionally across the rungs. This is the normal programming technique for the SVC instruction.

8–60

MicroLogix Communication Instruction

9

MicroLogix Communication

Instruction

Note

This chapter contains information about communications and the message (MSG) instruction. Specifically, this chapter contains information on:

• types of communication

• what the MSG instruction symbol looks like

• typical execution time for the MSG instruction

• how to use the MSG instruction

• application examples and timing diagrams

Only Series C or later MicroLogix 1000 controllers and Series A or later

MicroLogix 1000 analog controllers support the MSG instruction.

Message Instruction

Mnemonic

Instruction

Name

MSG

Message

Read/Write

This instruction transfers data from one node to another via the communication port. When the instruction is enabled, the message is sent to a communication buffer. Replies are processed at the end of scan.

9–2

9–1

Types of Communication

Communication is the ability of a device to send data or status to other devices.

This capability typically falls into one of two categories: master/sender or slave/receiver. Each of these are described below:

Initiator (Master) Communication

Initiator products can initiate communication, which includes requesting information from other devices (reading) or sending information to other products

(writing). In addition, initiator products are usually capable of replying to other devices when they make requests to read information. The Series C or later

MicroLogix 1000 controllers and the Series A or later MicroLogix 1000 analog controllers are in this class.

Initiator products can initiate communication with other intitiator products

(peer-to-peer communication) or with responder products (initiator-to-responder communication).

Responder (Slave) Communication

Responder products can only reply to other products. These devices are not capable of initiating an exchange of data; they only reply to requests made from initiator products. The Series A and B MicroLogix 1000 controllers are in this class.

Message Instruction (MSG)

MSG

READ/WRITE MESSAGE

Read/write

Target Device

Control Block

Control Block Length 7

Execution Times

(µ sec

) when:

True False

180

48

(EN)

(DN)

(ER)

The MSG is an output instruction that allows the controller to initiate an exchange of data with other devices. The relationship with the other devices can be either peer-to-peer communication or master-to-slave communication. The type of communication required by a particular application determines the programming configuration requirements of the MSG instruction.

This only includes the amount of time needed to set up the operation requested. It does not include the time it takes to service the actual communication, as this time varies with each network configuration. As an example, 144ms is the actual communication service time for the following configuration: 3 nodes on DH-485 (2=MicroLogix 1000 programmable controllers and 1=PLC-500 A.I. Series t

programming software), running at 19.2K baud, with 2 words per transfer.

9–2

MicroLogix Communication Instruction

Entering Parameters

Note

After you place the MSG instruction on a rung, specify whether the message is to be a read or write. Then specify the target device and the control block for the MSG instruction.

Read/Write – read indicates that the local processor (processor in which the instruction is located) is receiving data; write indicates that the processor is sending data.

Target Device – identifies the type of command used to establish communication. The target device can be a MicroLogix 1000 controller or SLC family processor using SLC commands, or a common interface file by selecting the CIF format. Valid options are:

SLC500/ML1000 – Allows communication between a MicroLogix 1000 controller and any other MicroLogix 1000 controller or SLC 500 family processor.

485CIF – (common interface file) Allows communication between a

MicroLogix 1000 controller and a non-MicroLogix 1000/SLC 500 device. The CIF data is automatically delivered to integer file 9 in SLC

500 processors or file 7 in MicroLogix 1000 controllers. The 485CIF protocol is also used for PLC-2 type messages.

Control Block Address – an integer file address that you select. It consists of 7 integer words, containing the status bits, target file address, and other data associated with the MSG instruction.

Control Block Length – fixed at seven elements. This field cannot be altered.

When running a MicroLogix 1000 program on an SLC 5/03 or SLC 5/04 processor, the MSG control block length increases from 7 to 14 words. If you plan to run a MicroLogix 1000 program with one of these processors, make sure that the program has at least 7 unused words following each MSG control block.

9–3

9–4

The table that follows illustrates combinations of message types and target devices and their valid file types.

Command Type

Message

Type

SLC500/ML1000 Write

SLC500/ML1000 Read

CIF

CIF

Write

Read

SLC500/ML1000 Write

SLC500/ML1000 Read

CIF

CIF

Write

Read

Initiating

Device

Valid File

Types

Target

Device

➀➁➂

Valid File Types

MicroLogix 1000 O,I,S,B,T,C,R,N MicroLogix 1000 O,I,S,B,T,C,R,N

MicroLogix 1000 O,I,S,B,T,C,R,N MicroLogix 1000 O,I,S,B,T,C,R,N

MicroLogix 1000 O,I,S,B,T,C,R,N MicroLogix 1000 N7

MicroLogix 1000 O,I,S,B,T,C,R,N MicroLogix 1000 N7

MicroLogix 1000

MicroLogix 1000

O,I,S,B,T,C,R,N

O,I,S,B,T,C,R,N

SLC 500

SLC 500

O

,I

,S,B,T,C,R,N

O

,I

,S,B,T,C,R,N

MicroLogix 1000 O,I,S,B,T,C,R,N SLC 500

MicroLogix 1000 O,I,S,B,T,C,R,N SLC 500

N9

N9

The DF1 Full-Duplex protocol can be used if the target device supports it. Such devices include MicroLogix 1000 controllers (any series), SLC 5/03 and SLC 5/04 processors, and PLC-5 processors (CIF command type only).

The DH-485 protocol can be used if the target device supports it. Such devices include MicroLogix 1000 controllers

(except for Series A and B controllers) and SLC 500, SLC 5/01, SLC 5/02, SLC 5/03, or SLC 5/04 processors.

The DF1 Half-Duplex protocol can also be used with Series D and analog MicroLogix 1000 controllers, as well as

SLC 5/03 and SLC 5/04 processors, but a master is required.

SLC 500, SLC 5/01, and SLC 5/02 processors do not support O or I file access from a MSG instruction. SLC 5/03 and SLC 5/04 processors do support O and I file access, but only when unprotected.

MicroLogix Communication Instruction

Control Block Layout

The control block layouts shown below illustrate SLC500/ML1000 type messages.

Control Block Layout – SLC500/ML1000

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

EN ST DN ER EW NR TO Error Code

Node Number

Reserved for length (in elements)

File Number

File Type (O, I, S, B, T, C, R, N)

Element Number

Subelement Number

4

5

6

Word

0

1

2

3

Control Block Layout – 485CIF

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

EN ST DN ER EW NR TO Error Code

Node Number

Reserved for Length (in elements)

Offset Bytes

Not used

Not used

Not used

4

5

6

Word

0

1

2

3

9–5

Using Status Bits

Read/Write:

Target Device:

Control Block:

Local Destination File Address:

READ

SLC500/ML1000

N7:0

***

Target Node:

Target File Address:

Message Length in elements

0

***

*** ignore if timed out: to be retried: awaiting execution: error: message done: message transmitting: message enabled: control bit address:

0 TO

0 NR

0 EW

0 ER

0 DN

0 ST

0 EN

N7:0/8

ERROR CODE: 0

Error Code Desc:

MSG Instruction Status Bits

Note

The right column in the display above lists the various MSG instruction status bits.

These are explained below:

Time Out Bit TO (bit 08) Temporarily set this bit (1) to clear an existing

MSG instruction. This bit has no effect unless the ST bit has first been set due to receiving an ACK (acknowlege). Your application must supply its own timeout value. This bit is reset on any false-to-true rung transition.

Negative Response Bit NR (bit 09) is set if the target processor is responding to your message, but can not process the message at the present time. The NR bit is reset at the next false-to-true rung transition that has a transmit buffer available. It is used to determine when to send retries. The ER bit is also set at this time. Use this feedback to initiate a retry of your message at a later time.

Enabled and Waiting Bit EW (bit 10) is set on any false-to-true transition.

This bit is reset when an ACK or NAK (no acknowledge) is received, or on any false rung instruction execution.

The operation of the EW bit has changed since Series C.

Error Bit ER (bit 12) is set when message transmission has failed. The ER bit is reset the next time the rung goes from false to true.

Done Bit DN (bit 13) is set when the message is transmitted successfully. The

DN bit is reset (cleared) the next time the rung goes from false to true.

9–6

MicroLogix Communication Instruction

Start Bit ST (bit 14) is set when the processor receives acknowledgement from the target device. This identifies that the target device has started to process the MSG request. The ST bit is reset when the DN, ER, or TO bit is set or on a false-to-true rung transition.

Enable Bit EN (bit 15) is set only if the transmit buffer is available. If the transmit buffer is not available, the EN flag remains false. When the transmit buffer becomes available, the EN flag goes true. It remains set until the next false rung execution after the MSG completes (DN bit set) or an error occurs

(ER bit set).

The operation of the EN bit has changed with Series C controllers.

Note

Controller Communication Status Bit

When using the MSG instruction, you should also use the following controller communication status bit:

Active Protocol Bit (S:0/11) – This is a read-only bit that indicates which communication protocol is currently enabled or functioning; where 0 = DF1

(default) and 1 = DH-485. Use this bit in your program to restrict message operation to the specific protocol in use.

9–7

Timing Diagram for a Successful MSG Instruction

Control Block Status Bits

Bit 10 EW

Enabled and Waiting

Bit 15 EN

Enabled

Bit 14 ST

Start

1

0

1

0

1

0

Bit 13 DN

Done

1

0

Bit 9 NR

Negative Response

Bit 8 TO

Time Out

1

0

1

0

The following section illustrates a successful timing diagram for a MicroLogix 1000

Series D or later, or analog Series A, MSG instruction.

Rung goes True.

Target node receives packet.

Target node sent reply.

Target node processes packet successfully and returns data

(read) or writes data (success).

The EW bit is set (1) and the ST, DN, NR, and TO flags are cleared. If the transmit buffer is not available, the EN flag remains false (0).

When rung conditions go true and the transmit buffer becomes available, the

EN flag goes true (1). The EN bit remains set until either the DN, ER, or TO bit is set. The TO bit has no effect unless the ST bit has first been set.

9–8

Note

MicroLogix Communication Instruction

If the Target Node successfully receives the MSG packet, it sends back an ACK

(an acknowledge). The ACK causes the processor to clear bit S:2/7. Note that the Target Node has not yet examined the MSG packet to see if it understands your request. It is replying to the initial connection.

At the next end of scan, the EW bit is cleared (0) and the ST bit is set (1). Once the ST bit is set, the processor will wait indefinitely for a reply from the Target

Node. The Target Node is not required to respond within any given time frame.

At this time, no other MSG instruction will be serviced.

If the Target Node faults or power cycles during the time frame of a MSG transaction, you will never receive a reply. This is why it is recommended you use a timer in conjunction with the TO bit to clear any pending instructions.

(When the TO bit is set [1] it clears pending messages.) Typically message transactions are completed within a couple of seconds. It is up to the programmer to determine how long to wait before clearing the buffer and then re-transmitting.

Step 4 is not shown in the timing diagram.

If you do not receive an ACK, step 3 does not occur. Instead a NAK (no acknowledge) is received. When this happens, the ST bit remains clear. A

NAK indicates:

• either the Target Node is not there,

• it does not respond,

• it is too busy, or

• it received a corrupt MSG packet.

When a NAK occurs, the EW bit is cleared. (Note that the NR bit will only be set for DH-485 and NAK conditions. An crror code 02H, Target Node is busy, is received which causes the NR bit to be set.) The ER bit is also set which indicates that the MSG instruction failed.

Monitor the NR bit. If it is set, indicating that the Target Node is busy, you may want to initiate some other process (e.g., an alarm or a retry later). The NR bit is cleared when the rung logic preceding the MSG changes from false to true.

When an ACK occurs, the Target Node sends one of three responses shown in

Step 6.

9–9

Following the successful receipt of the packet, the Target Node sends a reply packet. The reply packet will contain one of the following responses:

I have successfully performed your write request.

I have successfully performed your read request, and here is your data.

I have not performed your request because of an error.

At the next end of scan, following the Target Node’s reply, the MicroLogix 1000 controller examines the MSG packet from the target device. If the reply contains “I have successfully performed your write request,” the DN bit is set and the ST bit is cleared. The MSG instruction is complete. If the MSG rung is false, the EN bit is cleared the next time the MSG instruction is scanned.

If the reply contains “I have successfully performed your read request, and here is your data,” the data is written to the appropriate data table, the DN bit is set, and the ST bit is cleared. The MSG instruction function is complete. If the

MSG rung is false, the EN bit is cleared the next time the MSG instruction is scanned.

If the reply contains “I have not performed your request, because of an error,” the ER bit is set and the ST bit is cleared. The MSG instruction function is complete. If the MSG rung is false, the EN bit is cleared the next time the MSG instruction is scanned.

MSG Instruction Error Codes

Note

Any MSG instruction that is in progress during a network protocol switch will not be processed and will be discarded.

When an error condition occurs, the error code is stored in the lower byte of the first control word assigned to the MSG instruction.

9–10

Note

MicroLogix Communication Instruction

Error

Code

02H Target node is busy.

Description of Error Condition

03H Target node cannot respond because message is too large.

04H

Target node cannot respond because it does not understand the command parameters OR the control block may have been inadvertently modified.

05H Local processor is offline (possible duplicate node situation).

06H Target node cannot respond because requested function is not available.

07H Target node does not respond.

08H Target node cannot respond.

09H Local modem connection has been lost.

0AH Buffer unavailable to receive SRD reply.

0BH Target node does not accept this type of MSG instruction.

0CH Received a master link reset.

10H

Target node cannot respond because of incorrect command parameters or unsupported command.

15H Local channel configuration parameter error exists.

18H Broadcast (Node Address 255) is not supported.

1AH

Target node cannot respond because another node is file owner (has sole file access).

1BH

Target node cannot respond because another node is program owner (has sole access to all files).

37H Message timed out in local processor.

39H Message was discarded due to a communication protocol switch.

3AH Reply from target is invalid.

50H Target node is out of memory.

60H Target node cannot respond because file is protected.

E7H Target node cannot respond because length requested is too large.

EBH Target node cannot respond because target node denies access.

ECH Target node cannot respond because requested function is currently unavailable.

FAH Target node cannot respond because another node is file owner (has sole file access).

FBH

Target node cannot respond because another node is program owner (has sole access to all files).

Error codes 1A and 1B valid for Series C only.

For 1770–6.5.16 DF1 Protocol and Command Set users:

The MSG error code reflects the STS field of the reply to your MSG instruction.

Codes E0 – EF represent EXT STS codes 0 – F.

Codes F0 – FC represent EXT STS codes 10 – 1C.

9–11

Application Examples that Use the MSG Instruction

Example 1

Application example 1 shows how you can implement continuous operation of a message instruction.

0

1

2

S:0

] [

11

S:1

] [

7

B3

] [

1

MSG

READ/WRITE MESSAGE

Read/write WRITE

Target Device

SLC500/ML1000

Control Block N7:0

Control Block Length 7

(EN)

(DN)

(ER)

N7:0

] [

13*

N7:0

] [

12*

N7:0

(U)

15*

END

* MSG instruction

status bits:

12 = ER

13 = DN

15 = EN

Operation Notes

Bit S:0/11 ensures that the MSG instruction is only processed when the active protocol is DH-485. Bit S:1/7 ensures that DH-485 is communicating before sending the MSG. Bit B3/1 enables the MSG instruction. When the

MSG instruction done bit (N7:0/13) is set, it unlatches the MSG enable bit

(N7:0/15) so that the MSG instruction is re-enabled in the next scan. This provides continuous operation.

The MSG error bit also unlatches the enable bit. This provides continuous operation even if an error occurs.

9–12

Example 2

MicroLogix Communication Instruction

Application example 2 involves a MicroLogix 1000 controller transmitting its first input word to another MicroLogix 1000 controller. This is commonly referred to as

“change of state” or “report on exception” messaging. Using this type of logic significantly reduces network traffic, which in turn significantly improves network throughput.

2.0

This is the message control rung. The logic preceding the MSG instruction on this rung dictates when the

MSG instruction is processed. In this example, the MSG instruction is only processed when the active protocol is DH-485 and when there is no other communication. Once the MSG instruction is enabled, it locks itself into operation regardless of the preceding logic on the rung.

DH-485

Active

S:0

] [

11

Comms

Active

S:1

]/[

7

If the input status has changed, enable the MSG

NEQ

Not Equal

Source A

Source B

I:1.0

0

N7:10

0

MSG

READ/WRITE MESSAGE

Read/write READ

Target Device

SLC500/ML1000

Control Block

Control Block Length

N7:50

7

(EN)

(DN)

(ER)

2.1

This rung controls when the MSG instruction is unlatched or reset. The MSG instruction must be reset before it can re-transmit new information. Either of the following two conditions resets the MSG instruction: 1) when communication to the target device have been completed successfully, or 2) when an error is detected in the communication sequence (occurs after all retries have been exhausted). Using the error bit to reset the MSG is primarily used to stop the MSG instruction from being totally locked out.

MSG Done

N7:50

] [

13

MSG Enabled

N7:50

( )

15

MSG Error

N7:50

] [

12

2.2

This rung is used to setup the “report by exception” operation. This move command updates N7:10, by making it identical to I:1.0. When the processor starts a new scan sequence (when rung 2.0 is scanned,) it updates (reads) the input image. If an input has changed from the previous scan, the NEQ instruction is true and MSG is processed. The MSG Enabled bit ensures that the MOV is not processed until after the MSG is successfully completed. This minimizes the chances that input changes are missed during MSG operation.

DH-485

Active

S:0

] [

11

Comms

Active

S:1

]/[

7

MSG

Enabled

N7:50

]/[

15

MOV

MOVE

Move

Dest

I:1.0

0

N7:10

0

2.3

END

9–13

Example 3

Application example 3 involves a MicroLogix 1000 controller and an SLC 5/01 processor communicating on a DH-485 network. Interlocking is provided to verify data transfer and to shut down both processors if communication fails.

A temperature-sensing device, connected as an input to the MicroLogix 1000 controller, controls the on-off operation of a cooling fan, connected as an output to the SLC 5/01 processor. The MicroLogix 1000 and SLC 5/01 ladder programs are explained on the following pages.

9–14

Temperature-sensing

Input Device

0

I:1.0

] [

5

MicroLogix Communication Instruction

N7:0

( )

1

Bit 1 of the message word. Used for fan control.

First Pass Bit

First Pass Bit

1

2

S:1

] [

15

T4:0

(RES)

N7:0

(L)

0

TON

TIMER ON DELAY

Timer T4:0

Time Base

Preset

Accum

0.01

400

0

B3

(U)

0

(EN)

(DN)

MSG

READ/WRITE MESSAGE

Read/write WRITE

Target Device

SLC500/ML1000

Control Block

Control Block Length

N7:10

7

(EN)

(DN)

(ER)

DH-485 Active

Protocol Bit

1280 ms Clock Bit

DH-485 Active

Protocol Bit

Message Write

Done Bit

3

4

S:0

] [

11

S:0

] [

11

S:1

] [

15

S:4

] [

6

B3

] [

0

N7:10

] [

13*

5

T4:0

] [

DN

Message Read

Done Bit

6

7

MSG

READ/WRITE MESSAGE

Read/write READ

Target Device

SLC500/ML1000

Control Block

Control Block Length

N7:21

7

B3

(L)

0

(EN)

(DN)

(ER)

B3

(L)

10

N7:21

] [

13*

N7:0

]/[

0

END

Operation notes appear on the following page.

T4:0

(RES)

N7:0

(U)

0

B3

(U)

0

N7:21

(U)

13*

N7:10

(U)

15*

Bit 0 of the message word.

This is the interlock bit.

4-second Timer

Write message instruction. The source and target file addresses are N7:0

Target node: 3

Message length: 1 word.

Read message instruction. The destination and target file addresses are N7:0

Target node: 3

Message length: 1 word.

Latch – This alarm instruction notifies the application if the interlock bit N7:0/0 remains set for more than 4 seconds.

* MSG instruction

status bits:

13 = DN

15 = EN

9–15

Program File 2 of SLC 5/01 Processor at Node 3

0

S:1

] [

15

First Pass Bit

1

TON

TIMER ON DELAY

Timer T4:0

Time Base

Preset

Accum

0.01

400

0

N7:0

(U)

0

T4:0

(RES)

(EN)

(DN)

2

3

4

T4:0

] [

DN

N7:0

] [

0

B3

] [

1

B3

[OSR]

0

Bit 1 of the message word.

Used for fan control.

5

N7:0

] [

1

6

END

B3

(L)

10

B3

( )

1

N7:0

(U)

0

T4:0

(RES)

O:1.0

( )

0

Bit 0 of the message word. This is the interlock bit.

4-second Timer

Latch Instruction –

This alarm notifies the application if the interlock bit N7:0/0 is not set after

4 seconds.

O:1/0 energizes cooling fan.

Operation Notes, MicroLogix 1000 and SLC 5/01 programs

Message instruction parameters: N7:0 is the message word. It is the target file address (SLC 5/01 processor) and the local source and destination addresses (MicroLogix 1000 controller) in the message instructions.

N7:0/0 of the message word is the interlock bit; it is written to the 5/01 processor as a 1 (set) and read from the SLC 5/01 processor as a 0 (reset).

N7:0/1 of the message word controls cooling fan operation; it is written to the SLC 5/01 processor as a 1 (set) if cooling is required or as a 0 (reset) if cooling is not required. It is read from the SLC 5/01 processor as either 1 or 0.

Word N7:0 should have a value of 1 or 3 during the message write execution. N7:0 should have a value of 0 or 2 during the message read execution.

Program initialization: The first pass bit S:1/15 initializes the ladder programs on run mode entry.

MicroLogix 1000 controller: N7:0/0 is latched; timer T4:0 is reset; B3/0 is unlatched (rung 1), then latched (rung 3).

SLC 5/01 processor: N7:0/0 is unlatched; timer T4:0 is reset.

Message instruction operation: The message write instruction in the MicroLogix 1000 controller is initiated every 1280 ms by clock bit S:4/6. The done bit of the message write instruction initiates the message read instruction.

B3/0 latches the message write instruction. B3/0 is unlatched when the message read instruction done bit is set, provided that the interlock bit N7:0/0 is reset.

Communication failure: In the MicroLogix 1000 controller, bit

B3/10 becomes set if interlock bit N7:0/0 remains set (1) for more than 4 seconds. In the SLC 5/01 processor, bit B3/10 becomes set if interlock bit N7:0/0 remains set (1) for more than

4 seconds. Your application can detect this event, take appropriate action, then unlatch bit B3/10.

9–16

MicroLogix Communication Instruction

Example 4

DH-485 Active

Protocol Bit

B3/1 is latched

(external to this example) to initiate the message instruction.

1

2

0

Application example 4 shows you how to use the timeout bit to disable an active message instruction. In this example, an output is energized after five unsuccessful attempts (two seconds duration) to transmit a message.

S:0

] [

11

B3

] [

1

MSG

READ/WRITE MESSAGE

Read/write WRITE

Target Device

SLC500/ML1000

Control Block

Control Block Length

N7:0

7

(EN)

(DN)

(ER)

B3

] [

1

T4:0

] [

DN

N7:0

] [

14

TON

TIMER ON DELAY

Timer T4:0

Time Base

Preset

Accum

0.01

200

0

(EN)

(DN)

CTU

COUNT UP

Counter

Preset

Accum

C5:0

5

0

(CU)

(DN)

2-second timer. Each attempt at transmission has a 2-second duration.

Counter allows 5 attempts.

3

N7:0

] [

8

*

N7:0

] [

12

N7:0

(U)

15

After timeout error, unlatch the MSG EN bit to retrigger for another attempt.

4

5

T4:0

] [

DN

C5:0

] [

DN

N7:0

(L)

8

O:1.0

(L)

0

B3

(U)

1

N7:0/8* is the message instruction timeout bit.

The fifth attempt latches

O0:1/0 and unlatches the initiate message instruction bit.

6

N7:0

] [

13*

C5:0

(RES)

O:1.0

(U)

0

B3

(U)

1

* MSG instruction

status bits:

8 = TO

12 = ER

13 = DN

7

END

Operation Notes

The timeout bit is latched (rung 4) after a period of 2 seconds.

This clears the message instruction from processor control on the next scan. The message instruction is then re-enabled for a second attempt at transmission. After 5 attempts, O:1/0 is latched and B3/1 is unlatched.

A successful attempt at transmission resets the counter, unlatches

O:1/0, and unlatches B3/1.

9–17

Example 5

Application example 5 shows you how to link message instructions together to transmit serially, one after another. In this example, a MSG Write is followed by a

MSG Read, which causes the serial transmission.

2.0

2.1

This rung starts messaging each REM Run or RUN mode entry by clearing the EN bit of the first MSG instruction.

S:1

] [

15

N7:0

(U)

15

This rung sets the timeout value. (When using a SLC 5/03 or SLC 5/04 processor, this rung and rung 2:2 are not required because you can enter the value 6 into the Timeout value field in the MSG instruction block.)

N7:0

] [

15

N7:0

]/[

12

N7:0

]/[

13

TON

TIMER ON DELAY

Timer T4:0

Time Base

Preset

Accum

0.01

600

0

(EN)

(DN)

2.2

2.3

Same as above rung.

N7:20

] [

15

N7:20

]/[

12

N7:20

]/[

13

T4:0

] [

DN

N7:0

(L)

8

TON

TIMER ON DELAY

Timer T4:1

Time Base

Preset

Accum

0.01

600

0

(EN)

(DN)

T4:1

] [

DN

N7:20

(L)

8

The MSG instruction energizes upon entry into the REM Run or RUN mode. No input conditions are required.

S:0

] [

11

MSG

READ/WRITE MESSAGE

Read/write WRITE

Target Device

SLC500/ML1000

Control Block

Control Block Length

N7:0

7

(EN)

(DN)

(ER)

2.4

2.5

2.6

The MSG instruction is energized when the previous MSG instruction completes.

S:0

] [

11

N7:0

] [

12

N7:0

] [

MSG

READ/WRITE MESSAGE

Read/write READ

Target Device

SLC500/ML1000

Control Block

Control Block Length

N7:20

7

13

This rung resets all MSG instructions when the last MSG instruction has completed.

] [

N7:0

(U)

12

15

N7:20

] [

13

N7:20

(U)

15

END

(EN)

(DN)

(ER)

9–18

Proportional Integral Derivative Instruction

10

Proportional Integral Derivative

Instruction

This chapter describes the Proportional Integral Derivative (PID) instruction.

Overview

PID

PID

Control Block

Process Variable

Control Variable

Control Block Length 23

Output Instruction

✓ ✓ ✓ ✓

This is an output instruction that controls physical properties such as temperature, pressure, liquid level, or flow rate using process loops.

The PID instruction normally controls a closed loop using inputs from an analog input module and providing an output to an analog output module. For temperature control, you can convert the analog output to a time proportioning on/off output for

driving a heater or cooling unit. An example appears on pages 10–14 through

10–16.

The PID instruction can be operated in the timed mode or the STI mode. In the timed mode, the instruction updates its output periodically at a user-selectable rate.

In the STI mode, the instruction should be placed in an STI interrupt subroutine. It then updates its output every time the STI subroutine is scanned. The STI time interval and the PID loop update rate must be the same in order for the equation to execute properly.

10–1

The PID Concept

PID closed loop control holds a process variable at a desired set point. A flow rate/fluid level example is shown below.

Feed Forward or Bias

Set Point

Flow Rate

Error

PID

Equation

Process

Variable

Control

Output

Level

Detector

Control Valve

The PID equation controls the process by sending an output signal to the control valve. The greater the error between the setpoint and process variable input, the greater the output signal, and vice versa. An additional value (feed forward or bias) can be added to the control output as an offset. The result of PID calculation

(control variable) drives the process variable you are controlling toward the set point.

10–2

Proportional Integral Derivative Instruction

The PID Equation

The PID instruction uses the following algorithm:

Standard equation with dependent gains:

Output

+

K

C

[( E)

)

1 ń

T

I ŕ

( E)dt

)

T

D

· D(PV) ń dt]

) bias

Standard Gains constants are:

Term

Controller Gain K

C

Reset Term 1/T

I

Rate Term T

D

Range (Low to High)

0.1 to 25.5 (dimensionless)

0.01 to 327.67 (dimensionless)

25.5 to 0.1 (minutes per repeat)

327.67 to 0.01 (minutes per repeat)

0.01 to 2.55 (minutes)

0.01 to 327.67 (minutes)

Reference

Proportional

Integral

Derivative

Applies to SLC 5/03 and higher processors PID ranges when bit Reset and Gain Range (RG) bit is set to 1.

The derivative term (rate) provides smoothing by means of a low-pass filter. The cutoff frequency of the filter is 16 times greater than the corner frequency of the derivative term.

Entering Parameters

Note

Normally, you place the PID instruction on a rung without conditional logic. The output remains at its last value when the rung is false. The integral term is also cleared when the rung is false.

The PID instruction is an integer-only type of PID algorithm and does not allow you to enter floating point values for any of its parameters. So, if you attempt to move a floating point value to one of the PID parameters using ladder logic, a floating point-to-integer conversion occurs.

10–3

10–4

During programming, you enter the Control Block, Process Variable, and Control

Variable addresses after you have placed the PID instruction on a rung:

Control Block is a file that stores the data required to operate the instruction.

The file length is fixed at 23 words and should be entered as an integer file address. For example, an entry of N10:0 will allocate elements N10:0 through

N10:22. The control block layout is shown on page 10–10.

Do not write to control block addresses with other instructions in your program except as described later in this chapter. If you are re-using a block of data which was previously allocated for some other use, it is good practice to first zero the data. We recommend that you use a unique data file to contain your

PID control blocks (for example, N10:0). This avoids accidental re-use of the

PID control block addresses by other instructions in your program.

Process Variable PV is an element address that stores the process input value.

This address can be the location of the analog input word where the value of the input A/D is stored. This value could also be an integer value if you choose to pre-scale your input value to the range 0–16383.

Control Variable CV is an element address that stores the output of the PID instruction. The output value ranges from 0 to 16383, with 16383 being the

100% “on” value. This is normally an integer value, so that you can scale the

PID output range to the particular analog range your application requires.

The figure below shows a PID instruction with typical addresses for these parameters entered:

PID

PID

Control Block

Process Variable

Control Variable

Control Block Length

N10:0

N10:28

N10:29

23 auto/manual: MANUAL

mode: TIMED

control: E=SP–PV

setpoint (SP): process (PV): scaled error:

0

0

0

deadband: output (CV):

0

0 %

loop update: gain: reset: rate: min scaled: max scaled: output (CV) limit: output (CV) min: output (CV) max:

0 [.01 secs]

0 [/10]

0 [/10 m/r]

0 [/100 min]

0

0

NO

0 %

0 % time mode Bit: 1 TM auto/manual bit: 1 AM control mode bit: 0 CM

0output limiting enabled bit: 0 OL reset and gain range: 0 RG scale setpoint flag: 0 SC loop update time too fast: 0 TF derivitive (rate) action: 0 DA

DB, set when error is in DB: 0 DB output alarm, upper limit: 0 UL output alarm, lower limit: 0 LL setpoint out of range: 0 SP process var out of range: 0 PV

PID done: 0 DN

PID enabled: 0 EN

Note

Proportional Integral Derivative Instruction

The left column in the display above lists further PID instruction parameters you must enter.

Auto/Manual AM (word 0, bit 1) toggles between Auto and Manual. Auto indicates that the PID is controlling the output. (The bit is clear.) Manual indicates that the user is setting the output value. (The bit is set.) When tuning, we recommend that changes be made in the Manual mode, followed by a return to Auto. Output limiting is also applied in the Manual mode.

Mode TM (word 0, bit 0) toggles values Timed and STI. Timed indicates that the PID updates its output at the rate specified in the loop update parameter.

When using the timed mode, your processor scan time should be at least ten times faster than the loop update time to prevent timing inaccuracies or disturbances.

STI indicates that the PID updates its output every time it is scanned. When you select STI, the PID instruction should be programmed in an STI interrupt subroutine, and the STI routine should have a time interval equal to the setting of the PID “loop update” parameter. Set the STI period in word S:30. For example, if the loop update time contains the value 10 (for 100 ms), then the

STI time interval must also equal 10 (for 10 ms).

Control CM (word 0, bit 2) toggles values E=SP–PV and E=PV–SP. Direct acting (E=PV–SP) causes the output CV to increase when the input PV is larger than the setpoint SP (for example, a cooling application). Reverse acting

(E=SP–PV) causes the output CV to increase when the input PV is smaller than the setpoint SP (for example, a heating application).

Setpoint SP (word 2) is the desired control point of the process variable.

You can change this value with instructions in your ladder program. Write the value to the third word in the control block (for example write the value to N10:2 if your control block is N10:0). Without scaling, the range of this value is 0–16383. Otherwise, the range is minimum scaled (word 8) to maximum scaled (word 7).

Gain K c

(word 3) is the Proportional gain, ranging from 0.1 to 25.5. A rule of thumb is to set this gain to one half the value needed to cause the output to oscillate when the reset and rate terms (below) are set to zero.

SLC 5/03 and higher processors – The valid range is 0 to 3276.7.

Reset T i

(word 4) is the Integral gain, ranging from 0.1 to 25.5 minutes per repeat. A rule of thumb is to set the reset time equal to the natural period measured in the above gain calibration.

SLC 5/03 and higher processors – The valid range is 0 to 3276.7

minutes/repeat. Note that the value 1 will add the minimum integral term possible into the PID equation.

10–5

Note

Rate T d

(word 5) is the Derivative term. The adjustment range is 0.01 to

2.55 minutes. A rule of thumb is to set this value to 1/8 of the integral time above.

SLC 5/03 and higher processors – The valid range is 0 to 327.67 minutes.

This word is not effected by the RG bit.

Maximum Scaled Smax (word 7) – If the setpoint is to read in engineering units, then this parameter corresponds to the value of the setpoint in engineering units when the control input is 16383. Valid range is

16383 to

+

16383.

SLC 5/03 and higher processors – The valid range is

32768 to

+

32767.

Minimum Scaled Smin (word 8) – If the setpoint is to read in engineering units, then this parameter corresponds to the value of the setpoint in engineering units when the control input is zero. Valid range is

16383 to

+

16383.

SLC 5/03 and higher processors – The valid range is

32768 to

+

32767.

Smin – Smax scaling allows you to enter the setpoint in engineering units.

The deadband, error, and PV will be displayed in engineering units. The process variable, PV, is still be expected to be within the range of 0 to

16383. Use of Smin – Smax does not minimize PID PV resolution.

SLC 5/03 and higher processors: Scaled errors larger than

+

32767 or smaller than

32768 cannot be represented. If the scaled error is larger than

+

32767, it is represented as

+

32767. If the scaled error is smaller than

32768, it is represented as

32768.

Deadband DB (word 9) is a non-negative value. The deadband extends above and below the setpoint by the value you enter. The deadband is entered at the zero crossing of the process variable PV and the setpoint SP.

This means that the deadband is in effect only after the process variable PV enters the deadband and passes through the setpoint SP. The valid range is

0 to scaled maximum, or 0 to 16383 when no scaling exists.

Loop Update (word 13) is the time interval between PID calculations. The entry is in 0.01 second intervals. A rule of thumb is to enter a loop update time five to ten times faster than the natural period of the load (determined by setting the reset and rate parameters to zero and then increasing the gain until the output begins to oscillate). When in the STI mode, this value must equal the STI time interval value S:30. Valid range is 1 to 2.55 seconds.

SLC 5/03 and higher processors – The valid range is 0.01 to 10.24 seconds.

10–6

Proportional Integral Derivative Instruction

Note

output CV%

min max

Scaled Process PV (word 14) is for display only. This is the scaled value of the Process Variable (the analog input). Without scaling, the range of this value is 0–16383. Otherwise, the range is minimum scaled (word 8) to maximum scaled (word 7).

Scaled Error (word 15) is for display only. This is the scaled error as selected by the control mode parameter. Range: scaled maximum to

–scaled maximum, or 16383 to –16383 when no scaling exists.

SLC 5/03 and higher processors specific: Scaled errors larger than

+

32767 or smaller than

32768 cannot be represented. If the scaled error is larger than

+

32767, it is represented as

+

32767. If the scaled error is smaller than

32768, it is represented as

32768.

Output CV% (word 16) Displays the actual 0 to 16383 CV output in terms of percentage. (Range is 0 to 100%.) If you selected the AUTO mode with your programming software, this is for display only. If you selected manual mode and you are using your programming software’s data monitor, you can change output CV% and the change is applied to CV.

Writing to output CV% with your user program or a non-intelligent programming device does not affect the CV. When using a non-RSI programming software, you must write directly to CV, which ranges from 0 to 16383.

Output (CV) Limit OL (word 0, bit 3) toggles between Yes and No. Select

Yes if you want to limit the output to minimum and maximum values.

YES (1) output CV% limiting selected

The value you enter is the minimum output percent that the control variable CV attain.

If CV drops below this minimum value, the following occurs:

CV is set to the value you entered, and

The output alarm, lower limit LL bit is set.

The value you enter is the maximum output percent that the control variable CV will attain.

If CV exceeds this maximum value, the following occurs:

CV is set to the value you entered, and

The output alarm, upper limit UL bit is set.

NO (0) output CV% limiting deselected

The value you enter determines when the output alarm, lower limit bit is set.

If CV drops below this minimum value, the output alarm, lower limit (LL) bit is set.

The value you enter determines when the output alarm, upper limit bit is set.

If CV exceeds this maximum value, the output alarm, upper limit (UL) bit is set.

10–7

PID Instruction Flags

auto/manual: AUTO

mode: STI

control: E=SP–PV

setpoint (SP): process (PV): scaled error:

500

0

0 deadband: output (CV):

5

0 %

loop update: gain: reset: rate: min scaled: max scaled: output (CV) limit: output (CV) min: output (CV) max:

50 [.01 secs]

25 [/10]

10 [/10 m/r]

1 [/100 min]

0

1000

NO

0 %

0 % time mode Bit: 1 TM auto/manual bit: 0 AM control mode bit: 0 CM

0output limiting enabled bit: 1 OL reset and gain range: 0 RG scale setpoint flag: 0 SC loop update time too fast: 0 TF derivitive (rate) action: 0 DA

DB, set when error is in DB: 0 DB output alarm, upper limit: 0 UL output alarm, lower limit: 0 LL setpoint out of range: 0 SP process var out of range: 0 PV

PID done: 0 DN

PID enabled: 0 EN

The right column of the display above shows various flags associated with the PID instruction. The following section describes those flags:

Time Mode Bit TM (word 0, bit 0) specifies the PID mode. It is set when the

TIMED mode is in effect. It is cleared when the STI mode is in effect. This bit can be set or cleared by instructions in your ladder program.

Auto/Manual Bit AM (word 0, bit 01) specifies automatic operation when it is cleared and manual operation when it is set. This bit can be set or cleared by instructions in your ladder program.

Control Mode Bit CM (word 0, bit 02) is cleared if the control is E=SP–PV.

It is set if the control is E=PV–SP. This bit can be set or cleared by instructions in your ladder program.

Output Limiting Enabled Bit OL (word 0, bit 03) is set when you have selected to limit the control variable using function key [F4]. This bit can be set or cleared by instructions in your ladder program.

SLC 5/03 and higher processors – Reset and Gain Range Enhancement Bit

RG (word 0, bit 4) When set, this bit causes the Reset Minute/Repeat value and the gain multiplier to be enhanced by a factor of 10, (reset multiplier of .01

and gain multiplier of .01).

Example with bit 4 set: The Reset value of 1 indicates that the Integral value of

0.01 minutes/repeat (0.6 seconds/repeat) will be applied to the PID Integral algorithm. The gain value of 1 indicates that the error will be multiplied by 0.01

and applied to the PID algorithm.

10–8

Proportional Integral Derivative Instruction

When clear, this bit allows the Reset Minutes/Repeat value and the Gain multiplier value to be evaluated in the same units as the 5/02 PID instruction,

(reset multiplier of 0.1 and gain multiplier of 0.1).

Example with bit 4 clear: The Reset value of 1 indicates that the Integral value of 0.1 minutes/repeat (6.0 seconds/repeat) will be applied to the PID Integral algorithm. The gain value of 1 indicates that the error will be multiplied by 0.1

and applied to the PID algorithm.

Note that the Rate multiplier is not affected by this selection. (The initial release software, version 4.0, may not allow you to enter this bit. However, you may alter the state of this bit directly in the control block.)

Scale Setpoint Flag SC (word 0, bit 05) is cleared when setpoint scaling values are specified.

Loop Update Time Too Fast TF (word 0, bit 06) is set by the PID algorithm if the loop update time you have specified cannot be achieved by the given program (because of scan time limitations).

If this bit is set, try to correct the problem by updating your PID loop at a slower rate or move the PID instruction to an STI interrupt routine. Reset and rate gains will be in error if the instruction operates with this bit set.

Derivitive (Rate) Action Bit DA (word 0, bit 07) When set, this bit causes the Derivitive (Rate) calculation to be evaluated on the Error instead of the PV.

When clear, this bit allows the Derivitive (Rate) calculation to be evaluated the same as the 5/02 PID instruction, (where derivitive is performed on the PV).

This bit is only used by SLC 5/03 and higher processors.

DB, Set When Error is in DB (word 0, bit 08) is set when the process variable is within the 0 crossing deadband range.

Output Alarm, Upper Limit UL (word 0, bit 09) is set when the calculated control output CV exceeds the upper CV limit.

Output Alarm, Lower Limit LL (word 0, bit 10) is set when the calculated control output CV is less than the lower CV limit.

Setpoint Out of Range SP (word 0, bit 11) is set when the setpoint exceeds the maximum scaled value or is less than the minimum scaled value.

Process Var Out of Range PV (word 0, bit 12) is set when the unscaled (or raw) process variable exceeds 16383 or is less than zero.

PID Done DN (word 0, bit 13) is set on scans where the PID algorithm is computed. It is computed at the loop update rate.

PID Enabled EN (word 0, bit 15) is set while the rung of the PID instruction is enabled.

10–9

Control Block Layout

The control block length is fixed at 23 words and should be programmed as an integer file. PID instruction flags (word 0) and other parameters are located as follows:

Control Block Layout

➁ ➁

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

EN DN PV SP LL UL DB DA TF SC RG OL CM AM TM

*

*

*

*

*

*

*

PID Sub Error Code (MSbyte)

Setpoint SP

Gain K

C

Reset T i

Rate T d

Feed Forward Bias

Setpoint Max (Smax)

* Setpoint Min (Smin)

*

Deadband

INTERNAL USE DO NOT CHANGE

*

*

Output Max

Output Min

* Loop Update

Scaled Process Variable

Scaled Error SE

Output CV% (0–100%)

MSW Integral Sum

LSW Integral Sum

5/03 MSW Integral Sum

5/03 LSW Integral Sum

INTERNAL USE

DO NOT CHANGE

18

19

20

13

14

15

16

17

21

22

10

11

12

8

9

6

7

4

5

2

3

Word

0

1

OL, CM,

AM, TM

You may alter the state of these values with your ladder program.

Applies to the SLC 5/03 and higher processors.

Do not alter the state of any PID control block value unless you fully understand its function and related effect on your process.

10–10

Proportional Integral Derivative Instruction

Runtime Errors

Error Code

11H

12H

13H

14H

21H

(SLC 5/02 only)

22H

(SLC 5/02 only)

23H

Error code 0036 appears in the status file when a PID instruction runtime error occurs. Code 0036 covers the following PID error conditions, each of which has been assigned a unique single byte code value that appears in the MSbyte of the second word of the control block.

Description of Error Condition or Conditions

SLC 5/02

1) Loop update time

D t

> 255, or

SLC 5/03 and higher

1) Loop update time

D t

> 1024

Corrective Action

SLC 5/02

Change loop update time D

t

to 0 < D

t

< 255

SLC 5/03 and higher

Change loop update time Dt to

0 < D

t

< 1024

2) Loop update time

D t

= 0

SLC 5/02

1) Proportional gain

K c

> 255, or

2) Loop update time

D t

= 0

SLC 5/03 and higher

1) Proportional gain

K c

< 0

SLC 5/02

Change proportional gain K

c

to

0 < K

c

< 255

SLC 5/03 and higher

Change proportional gain Kc to

0 < K

c

2) Proportional gain

K c

= 0

SLC 5/02

Integral gain (reset)

T i

> 255

SLC 5/03 and higher

Integral gain (reset)

T i

< 0

SLC 5/02

Derivative gain (rate)

T d

> 255

SLC 5/03 and higher

Derivative gain (rate)

T d

< 0

1) Scaled setpoint max Smax > 16383, or

2) Scaled setpoint max Smax < –16383

1) Scaled setpoint min Smin > 16383, or

2) Scaled setpoint min Smin < –16383

Scaled setpoint min

Smin > Scaled setpoint max Smax

SLC 5/02

Change integral gain

(reset) T

i

to

0 < T

i

< 255

SLC 5/02

SLC 5/03 and higher

Change integral gain

(reset) Ti to 0 < T

i

SLC 5/03 and higher

Change derivative gain

(rate) T

d

to

0 < T

d

< 255

Change derivative gain

(rate) T

d

to

0 < T

d

Change scaled setpoint max Smax to

–16383 < Smax < 16383

Change scaled setpoint min Smin to

–16383 < Smin < Smax < 16383

Change scaled setpoint min Smin to

–16383 < Smin < Smax < 16383

(SLC 5/03 and higher –32768 to

+

32767)

10–11

51H

52H

53H

60H

Error Code

31H

41H

Description of Error Condition or Conditions

If you are using setpoint scaling and

Smin > setpoint SP > Smax, or

Corrective Action

If you are using setpoint scaling, then change the setpoint SP to Smin < SP < Smax, or

If you are not using setpoint scaling and

0 > setpoint SP > 16383,

If you are not using setpoint scaling, then change the setpoint SP to 0 < SP < 16383.

then during the initial execution of the PID loop, this error occurs and bit 11 of word 0 of the control block is set. However, during subsequent execution of the PID loop if an invalid loop setpoint is entered, the PID loop continues to execute using the old setpoint, and bit 11 of word 0 of the control block is set.

Scaling Selected

1) Deadband < 0, or

Scaling Deselected

1) Deadband < 0, or

Scaling Selected

Change deadband to

0 < deadband <

(Smax – Smin) <

16383

Scaling Deselected

Change deadband to

0 < deadband < 16383

2) Deadband >

(Smax - Smin), or

3) Deadband > 16383

(5/02 specific)

2) Deadband > 16383

1) Output high limit < 0, or

2) Output high limit > 100

1) Output low limit < 0, or

2) Output low limit > 100

Output low limit > output high limit

Change output high limit to

0 < output high limit < 100

Change output low limit to

0 < output low limit < output high limit < 100

Change output low limit to

0 < output low limit < output high limit < 100

SLC 5/02 – PID is being entered for the second time. (PID loop was interrupted by an I/O interrupt, which is then interrupted by the PID STI interrupt.)

You have at least three PID loops in your program: One in the main program or subroutine file, one in an I/O interrupt file, and one in the STI subroutine file. You must alter your ladder program and eliminate the potential nesting of PID loops.

10–12

Proportional Integral Derivative Instruction

PID and Analog I/O Scaling

For the SLC 500 PID instruction, the numerical scale for both the process variable

(PV) and the control variable (CV) is 0 to 16383. To use engineering units, such as

PSI or degrees, you must first scale your analog I/O ranges within the above numerical scale. To do this, use the Scale (SCL) instruction and follow the steps described below.

1.

Scale your analog input by calculating the slope (or rate) of the analog input range to the PV range (0 to 16383.) For example, an analog input with a range of 4 to 20mA has a decimal range of 3277 to 16384. The decimal range must be scaled across the range of 0 to 16383 for use as PV.

2.

Scale the CV to span evenly across your analog output range. For example, an analog output which is scaled at 4 to 20mA has a decimal range of 6242 to

31208. In this case, 0 to 16383 must be scaled across the range of 6242 to

31208.

Once you have scaled your analog I/O ranges to/from the PID instruction, you can enter the minimum and maximum engineering units that apply to your application. For example, if the 4 to 20mA analog input range represents 0 to

300 PSI, you can enter 0 and 300 as the minimum (Smin) and maximum (Smax) parameters respectively. The Process Variable, Error, Setpoint, and Deadband are displayed in engineering units in the PID Data Monitor screen. Setpoint and

Deadband can be entered into the PID instruction using engineering units.

The following equations show the linear relationship between the input value and the resulting scaled value.

Scaled value

=

(input value x slope)

+

offset

Slope

=

(scaled max.

scaled min.) / (input max.

input min)

Offset

=

scaled min.

(input min. x slope)

Using the SCL Instruction

Use the following values in an SCL instruction to scale common analog input ranges to PID process variables.

Parameter

Rate/10,000

Offset

4 to 20mA

12,499

–4096

0 to 5V

10,000

0

0 to 10V

5,000

0

10–13

Using the SCP Instruction

Use the following values in an SCP instruction to scale your analog inputs to the PV range and scale the CV range to your analog output.

Parameter

Input minimum

Input maximum

Scaled minimum

Scaled maximum

4 to 20mA

0

16384

0

16383

0

16384

0 to 5V

0

16383

0 to 10V

0

32767

0

16383

Use the following values in an SCP instruction to scale control variables to common analog outputs.

Parameter

Input minimum

Input maximum

Scaled minimum

Scaled maximum

4 to 20mA

3277

16383

6242

31208

0

16383

0

16384

0 to 5V 0 to 10V

0

16383

0

32764

Example

Use the following values in an SCL instruction to scale control variables to common analog outputs.

Parameter

Rate/10,000

Offset

4 to 20mA

15,239

6242

0 to 5V

10,000

0

0 to 10V

19,999

0

The following ladder diagram shows a typical PID loop that is programmed in the

STI mode. This example is provided primarily to show the proper scaling techniques. It shows a 4 to 20mA analog input and a 4 to 20mA analog output. The following parameters are used:

STI subroutine file (S:31) = 3

STI Setpoint (S:30) = 10

STI Enabled bit (S:2/1) = 1

10–14

Proportional Integral Derivative Instruction

This rung immediately updates the analog input used for PV.

Rung

3:0

IIM

IMMEDIATE IN w MASK

Slot I:1.0

Mask FFFF

Rung

3:1

Rung

3:2

Rung

3:3

These two rungs ensure the analog input value to be scaled remains within the limits of 3277 to 16384. This is necessary to prevent “out of range” conversion errors in both the SCL and PID instructions. The latch bits can be used elsewhere in your program to identify the particular out of range condition that occurred.

Under range

LES

LESS THAN

B3

(L)

Source A I:1.0

0

0

Source B 3277

MOV

MOVE

Source 3277

Dest I:1.0

0

GRT

GREATER THAN

Source A

Source B

I:1.0

0

16384

Over range

B3

(L)

1

MOV

MOVE

Source

Dest

16384

I:1.0

0

The source to be scaled is the input I:1 and its destination is the process variable of the PID instruction. These values are calculated knowing that the input range is 3277 to 16384, while the scaled range (PV) is 0 to 16383.

SCL

SCALE

Source

Rate [/10000]

I:1.0

0

12499

Offset

Dest

–4096

N10:28

0

Rung

3:4

PID

PID

Control Block

Process Variable

Control Variable

Control Block Length

N10:0

N10:28

N10:29

23

10–15

10–16

Rung

3:5

Rung

3:6

The PID control variable is the input for the scale instruction. The PID instruction guarantees that the CV remains within the range of 0 to 16383. This value is to be scaled to the range of 6242 to 31208, which represents the numeric range that is needed to produce 4 to 20mA analog output signal.

SCL

SCALE

Source

Rate [/10000]

N10:29

0

15239

Offset

Dest

6242

O:1.0

0

This rung immediately updates the analog output card that is driven by the PID control variable value.

IOM

IMMEDIATE OUT w MASK

Slot O:1.0

Mask FFFF

END

The STI routine should have a time interval equal to the setting of the PID “loop update” parameter.

Proportional Integral Derivative Instruction

Application Notes

The following paragraphs discuss:

Input/Output Ranges

Scaling to Engineering Units

Zero-crossing Deadband

Output Alarms

Output Limiting with Anti-reset Windup

The Manual Mode

Feed Forward

Time Proportioning Outputs

Input/Output Ranges

The input module measuring the process variable (PV) must have a full scale binary range of 0 to 16383. If this value is less than 0 (bit 15 set), then a value of zero is used for PV and the “Process var out of range” bit is set (bit 12 of word 0 in the control block). If the process variable is >16383 (bit 14 set), then a value of 16383 is used for PV and the “Process var out of range” bit is set.

The Control Variable, calculated by the PID instruction, has the same range of 0 to

16383. The Control Output (word 16 of the control block) has the range of 0 to

100%. You can set lower and upper limits for the instruction’s calculated output values (where an upper limit of 100% corresponds to a Control Variable limit of

16383).

Scaling to Engineering Units

Scaling lets you enter the setpoint and zero-crossing deadband values in engineering units, and display the process variable and error values in the same engineering units. Remember, the process variable PV must still be within the range 0–16383.

The PV is displayed in engineering units, however.

10–17

10–18

Select scaling as follows:

1.

Enter the maximum and minimum scaling values Smax and Smin in the PID

control block. Refer to the control block of the PID instruction on page 10–10.

The Smin value corresponds to an analog value of zero for the lowest reading of the process variable, and Smax corresponds to an analog value of 16383 for the highest reading. These values reflect the process limits. Setpoint scaling is selected by entering a non-zero value for one or both parameters. If you enter the same value for both parameters, setpoint scaling is disabled.

For example, if measuring a full scale temperature range of – 73 (PV=0) to

+

1156

°

C (PV=16383), enter a value of –73 for Smin and 1156 for Smax. Remember that inputs to the PID instruction must be 0 to 16383. Signal conversions could be as follows:

Process limits

Transmitter output (if used)

Output of analog input module

PID instruction, Smin to Smax

73 to

+

1156

°

C

+4 to +20 mA

0 to 16383

73 to

+

1156

°

C

2.

Enter the setpoint (word 2) and deadband (word 9) in the same scaled engineering units. Read the scaled process variable and scaled error in these units as well. The control output percentage (word 16) is displayed as a percentage of the 0 to 16383 CV range. The actual value transferred to the CV output is always between 0 and 16383.

When you select scaling, the instruction scales the setpoint, deadband, process variable, and error. You must consider the effect on all these variables when you change scaling.

Proportional Integral Derivative Instruction

Zero–crossing Deadband DB

The adjustable deadband lets you select an error range above and below the setpoint where the output does not change as long as the error remains within this range.

This lets you control how closely the process variable matches the setpoint without changing the output.

+DB

SP

–DB

Error range

Time

Zero-crossing is deadband control that lets the instruction use the error for computational purposes as the process variable crosses into the deadband until it crosses the setpoint. Once it crosses the setpoint (error crosses zero and changes sign) and as long as it remains in the deadband, the instruction considers the error value zero for computational purposes.

Select deadband by entering a value in the deadband storage word (word 9) in the control block. The deadband extends above and below the setpoint by the value you enter. A value of zero inhibits this feature. The deadband has the same scaled units as the setpoint if you choose scaling.

Output Alarms

You may set an output alarm on the control output (CO) at a selected value above and/or below a selected output percent. When the instruction detects that the output

(CO) has exceeded either value, it sets an alarm bit (bit 10 for lower limit, bit 9 for upper limit) in word 0 of the PID control block. Alarm bits are reset by the instruction when the output (CO) comes back inside the limits. The instruction does not prevent the output (CO) from exceeding the alarm values unless you select output limiting.

Select upper and lower output alarms by entering a value for the upper alarm (word

11) and lower alarm (word 12). Alarm values are specified as a percentage of the output. If you do not want alarms, enter zero and 100% respectively for lower and upper alarm values and ignore the alarm bits.

10–19

Output Limiting with Anti-Reset Windup

You may set an output limit (percent of output) on the control output. When the instruction detects that the output (CO) has exceeded a limit, it sets an alarm bit (bit

10 for lower limit, bit 9 for upper limit) in word 0 of the PID control block, and prevents the output (CO) from exceeding either limit value. The instruction limits the output (CO) to 0 and 100% if you choose not to limit.

Select upper and lower output limits by setting the limit enable bit (bit 3 of control word 0), and entering an upper limit (word 11) and lower limit (word 12). Limit values are a percentage (0 to 100%) of the control output (CO).

The difference between selecting output alarms and output limits is that you must select output limiting to enable limiting. Limit and alarm values are stored in the same words. Entering these values enables the alarms, but not limiting. Entering these values and setting the limit enable bit enables limiting and alarms.

Anti-reset windup is a feature that prevents the integral term from becoming excessive when the output (CO) reaches a limit. When the sum of the PID and bias terms in the output (CO) reaches the limit, the instruction stops calculating the integral sum until the output (CO) comes back in range. The integral sum is contained in words 17 and 18 of the control block.

The Manual Mode

In the manual mode, the PID algorithm does not compute the value of the control variable. Rather, it uses the value as an input to adjust the integral sum (words 17 and 18) so that a bumpless transfer takes place upon re-entering the AUTO mode.

In the manual mode, the programmer allows you to enter a new CV value from 0 to

100%. This value is converted into a number from 0 to 16383 and written to the

Control Variable address. If you are using an analog output module for this address, you must save (compile) the program with the File Protection option set to None.

This allows writing to the output data table. If you do not perform this save operation, you are not able to set the output level in the manual mode. If your ladder program sets the manual output level, design your ladder program to write to the CV address when in the manual mode. Note that this number is in the range of 0 to 16383, not 0 to 100. Writing to the CV percent (word 16) with your ladder program has no effect in the manual mode.

The example on the next page shows how you can manually control the control variable (CV) output with your ladder program.

10–20

Proportional Integral Derivative Instruction

PID Rungstate

If the PID rung is false, the integral sum (words 17 and 18) is cleared and CV remains in its last state.

Manual

I:2.0

] [

2

Auto

I:2.0

] [

1

A/M Bit

N7:10

(L)

1

A/M Bit

N7:10

(U)

1

A/M Bit

N7:10

] [

1

Accept CV

I:2.0

] [

0

B3

[OSR]

0

FRD

FROM BCD

Source

Dest

I1:1.0

N7:0

LIM

LIMIT TEST

Low Lim

Test

High Lim

0

N7:0

100

MUL

MULTIPLY

Source A

Source B

Dest

N7:0

16384

N7:2

DDV

DOUBLE DIVIDE

Source

Dest

100

N7:8

Notes on Operation

A 3-digit BCD thumbwheel is wired to an input module at I1:1.0 (range 0–100).

A pushbutton wired to I1:2.0/0 accepts the thumbwheel value.

A selector switch for auto/manual mode is wired to I1:2.0/1 (auto) and I1:2.0/2

(manual).

N7:0 stores the value entered on the thumbwheel switch.

N7:2 stores an intermediate calculation.

N7:8 is the PID control variable address.

N7:10 is the control block address of the

PID instruction.

N7:26 Percent output is updated automatically by the PID instruction.

LIM

LIMIT TEST

Low Lim

Test

High Lim

101

N7:0

–1

S:5

(U)

0

Error – Out of Range

B3

( )

3

10–21

Feed Forward or Bias

Applications involving transport lags may require that a bias be added to the CV output in anticipation of a disturbance. This bias can be accomplished using the processor by writing a value to the Feed Forward Bias element, the seventh element

(word 6) in the control block file. (See page 10–10.) The value you write is added

to the output, allowing a feed forward action to take place. You may add a bias by writing a value between

16383 and

+

16383 to word 6 with your programming terminal or ladder program.

Time Proportioning Outputs

For heating or cooling applications, the Control Variable analog output is typically converted to a time-proportioning output. While this cannot be done directly with the processor, you can use the program on the following page to convert the Control

Variable to a time proportioning output. In this program, cycle time is the preset of timer T4:0. Cycle time relates to % on-time as follows:

T4:0.PRE is the cycle time

% on–time

100% output on–time

10–22

Proportional Integral Derivative Instruction

Example – Time proportioning outputs

PID

PID

Control Block

Process Variable

Control Variable

Control Block Length

N7:2

N7:0

N7:1

23

TON

TIMER ON DELAY

Timer T4:0

Time Base

Preset

Accum

0.01

1000

0

(EN)

(DN)

GRT

GREATER THAN

Source A T4:0.ACC

Source B

0

N7:25

0

T4:0

] [

DN

O:1.0

(U)

0

NEQ

NOT EQUAL

Source A

Source B

N7:25

0

0

T4:0

(RES)

O:1.0

(L)

0

Cycle Time of Output

Time Proportioning

Output Contacts

PID Instruction

Done Bit

N7:2

] [

13

MUL

MULTIPLY

Source A N7:1

0

Source B T4:0.PRE

1000

Dest N7:25

0

DDV

DOUBLE DIVIDE

Source 16383

Dest N7:25

0

CLR

CLEAR

Dest S:5

0

Control Variable

Output as a Fraction of

Cycle Time

Clears Minor Error Flag

END

10–23

PID Tuning

Note

Note

PID tuning requires a knowledge of process control. If you are inexperienced, it will be helpful if you obtain training on the process control theory and methods used by your company.

There are a number of techniques that can be used to tune a PID loop. The following PID tuning method is general, and is limited in terms of handling load disturbances. When tuning, we recommend that changes be made in the MANUAL mode, followed by a return to AUTO. Output limiting is applied in the MANUAL mode.

This method requires that the PID instruction controls a non-critical application in terms of personal safety and equipment damage.

The PID tuning procedure may not work for all cases. It is strongly recommended to use a PID Loop tuner package for the best result (ex. RSTune, Catalog

#9323-1003D, PID Logistic for PLC 500 A.I Series or P/N 9323-S5250D or PID

Logistic for PLC 500 A.I Series Stand Alone Package P/N 9323–S5255D).

Procedure

Note

1.

Create your ladder program. Make certain that you have properly scaled your analog input to the range of the process variable PV and that you have properly scaled your control variable CV to your analog output.

2.

Connect your process control equipment to your analog modules. Download your program to the processor. Leave the processor in the program mode.

Ensure that all possibilities of machine motion have been considered with respect to personal safety and equipment damage. It is possible that your output CV may swing between 0 and 100% while tuning.

If you want to verify the scaling of your continuous system and/or determine the

initial loop update time of your system, go to the procedure on page 10–26.

3.

Enter the following values: the initial setpoint SP value, a reset T i

of 0, a rate

T d

of 0, a gain K c

of 1, and a loop update of 5.

Set the PID mode to STI or Timed, per your ladder diagram. If STI is selected, ensure that the loop update time equals the STI time interval.

Enter the optional settings that apply (output limiting, output alarm,

Smax – Smin scaling, feedforward).

10–24

Proportional Integral Derivative Instruction

4.

Get prepared to chart the CV, PV, analog input, or analog output as it varies with time with respect to the setpoint SP value.

5.

Place the PID instruction in the MANUAL mode, then place the processor in the Run mode.

6.

While monitoring the PID display, adjust the process manually by writing to the

CO percent value.

7.

When you feel that you have the process under control manually, place the PID instruction in the AUTO mode.

8.

Adjust the gain while observing the relationship of the output to the setpoint over time.

When using the SLC 5/02 processor, gain adjustments disrupt the process when you change values. To avoid this disruption, switch to the MANUAL mode prior to making your gain change, then switch back to the AUTO mode. When using an SLC 5/03 or higher processor, gain changes do not disrupt the process; therefore, you do not need to switch to the MANUAL mode.

9.

When you notice that the process is oscillating above and below the setpoint in an even manner, record the time of 1 cycle. That is, obtain the natural period of the process.

Natural Period

4x deadtime

Record the gain value. Return to the MANUAL mode (stop the process if necessary).

10. Set the loop update time (and STI time interval if applicable) to a value of 5 to

10 times faster than the natural period.

For example, if the cycle time is 20 seconds, and you choose to set the loop update time to 10 times faster than the natural rate, set the loop update time to

200, which would result in a 2-second rate.

11. Set the gain K c

value to 1/2 the gain needed to obtain the natural period of the process. For example, if the gain value recorded in step 9 was 80, set the gain to 40.

12. Set the reset term T i

to approximate the natural period. If the natural period is

20 seconds, as in our example, you would set the reset term to 3 (0.3 minutes per repeat approximates 20 seconds).

10–25

13. Now set the rate T d

equal to a value 1/8 that of the reset term. For our example, the value 4 will be used to provide a rate term of 0.04 minutes per repeat.

14. Place the process in the AUTO mode. If you have an ideal process, the PID tuning will be complete.

15. To make adjustments from this point, place the PID instruction in the

MANUAL mode, enter the adjustment, then place the PID instruction back in the AUTO mode.

This technique of going to MANUAL, then back to AUTO ensures that most of the “gain error” is removed at the time each adjustment is made. This allows you to see the effects of each adjustment immediately. Toggling the PID rung allows the PID instruction to restart itself, eliminating all of the “integral buildup.” You may want to toggle the PID rung false while tuning to eliminate the effects of previous tuning adjustments.

Verifying the Scaling of Your Continuous System

To ensure that your process is linear, and that your equipment is properly connected and scaled, do the following:

1.

Place the PID instruction in manual and enter the following parameters:

• type:

0

for Smin

• type:

100

for Smax

• type:

0

for CO%

2.

Enter the REM Run mode and verify that PV=0.

3.

Type:

20

in CO%

4.

Record the PV = _______

5.

Type:

40

in CO%.

6.

Record the PV = _______

7.

Type:

60

in CO%.

8.

Record the PV = _______

9.

Type:

80

in CO%.

10. Record the PV = _______

10–26

Proportional Integral Derivative Instruction

11. The values you recorded should be offset from CO% by the same amount. This proves the linearity of your process. The following example shows an offset progression of fifteen.

CO 20% = PV 35%

CO 40% = PV 55%

CO 60% = PV 75%

CO 80% = PV 95%

If the values you recorded are not offset by the same amount:

Either your scaling is incorrect, or

• the process is not linear, or

• your equipment is not properly connected and/or configured.

Make the necessary corrections and repeat steps 2–10.

Determining the Initial Loop Update Time

To determine the approximate loop update time that should be used for your process, perform the following:

1.

Place the normal application values in Smin and Smax.

2.

Type:

50

in CO%.

3.

Type:

60

in CO% and immediately start your stopwatch.

4.

Watch the PV. When the PV starts to change, stop your stopwatch. Record this value. It is the deadtime.

5.

Multiply the deadtime by 4. This value approximates the natural period. For example, if: deadtime = 3 seconds, then 4 3 = 12 seconds (

natural period)

6.

Divide the value obtained in step 5 by 10. Use this value as the loop updated time. For example, if: natural period

=

12 seconds , then 12 10 = 1.2 seconds .

Therefore, the value 120 would be entered as the loop update time.

(

120 10 ms

=

1.2 seconds

)

10–27

10–28

7.

Enter the following values: the initial setpoint SP value, a reset T i

of 0, a rate

T d

of 0, a gain K c

of 1, and the loop update time determined in step 17.

Set the PID mode to STI or Timed, per your ladder diagram. If STI is selected, ensure that the loop update time equals the STI time interval.

Enter the optional settings that apply (output limiting, output alarm,

Smax – Smin scaling, feedforward).

8.

Return to page 10–25 and complete the tuning procedure starting with step 4.

ASCII Instructions

11

ASCII Instructions

This chapter contains general information about the ASCII instructions and explains how they function in your application program. Each of the instructions includes information on:

• what the instruction symbol looks like

• how to use the instruction

ASCII Instructions

Mnemonic

Instruction

Name

ABL

ACB

ACI

Test Buffer for Line Determine the number of characters in the buffer, up to and including the end of line character.

Number of

Characters in

Buffer

Determine the total number of characters in the buffer.

String to Integer Convert a string to an integer value.

ACL

ACN

AEX

AHL

ASCII Clear

Receive and/or

Send Buffer

Clear the receive and/or transmit buffers.

String Concatenate Link two strings into one.

String Extract Extract a portion of a string to create a new string.

Set or reset modem handshake lines.

AIC

ARD

ASCII Handshake

Lines

Integer to String

ASCII Read

Characters

Convert an integer value to a string.

Read characters from the input buffer and place them into a string.

11–6

11–7

11–9

11–10

11–11

11–12

11–13

11–14

11–15

continued on next page

11–1

Mnemonic

Instruction

Name

ARL

ASCII Read Line

ASC

ASR

AWA

AWT

String Search

ASCII String

Compare

ASCII Write with

Append

ASCII Write

Read one line of characters from the input buffer and place them into a string.

Search a string.

Compare two strings.

Write a string with user-configured characters appended.

Write a string.

11–18

11–20

11–21

11–22

11–25

ASCII Instruction Overview

ASCII instructions are available in SLC 5/03 OS301 and above processors, and all

SLC 5/04 and SLC 5/05 processors. There are two types of ASCII instructions:

ASCII port control – these include instructions that use or alter the communication channel for receiving or transmitting data. When using these instructions, the system configuration must be set to “User mode.”

(ABL, ACB, ACL, AHL*, ARD, ARL, AWA*, AWT*)

*must be in user or system mode

ASCII port control instructions are queued in the order that they are executed and are dependent on one another to execute (except ACL which executes immediately). For example, if you have an ARD (ASCII Read instruction) and then an AWT (ASCII Write instruction), the Done bit or the Error bit of the

ARD must be set before the AWT can begin executing (even if the AWT was enabled while the processor was executing the ARD). A second ASCII port control instruction cannot begin executing until the first has completed.

However, the processor does not wait for an ASCII port control instruction to complete before continuing to execute your ladder program.

ASCII string control – these include instructions that manipulate string data.

(ACI, ACN, AEX, AIC, ASC, ASR)

ASCII string control instructions execute immediately. They are never sent to the queue to wait their turn for execution.

11–2

ASCII Instructions

Protocol Parameter Overview

Listed below are the ASCII protocol parameters that you set via the Channel 0 configuration screens in your programming software.

Description

Baud Rate

Start Bits

Stop Bits

Parity

Data Bits

Termination Characters

Append Characters

Specification

Toggles between 110, 300, 600, 1.2K, 2.4K, 4.8K, 9.6K, and 19.2K

(additional rate of 38.4K for SLC 5/05 only). The default is 1.2K

(19.2K for SLC 5/05 only).

The default is 1 and cannot be changed.

Options include 1, 1.5, and 2 The default is 1.

Toggles between None, Odd, and Even. The default is None.

Toggles between 7 and 8. The default is 8.

Allows you to configure up to 2 ASCII characters. The default is

CR.

Allows you to configure up to 2 ASCII characters. The AWA instruction adds the characters to the end of every string to serve as termination characters for the receiving device. The default is

CR LF.

Using the ASCII Data File Type

These are 1-word elements. Assign ASCII addresses as follows:

Format

Af:e/b

Explanation

A ASCII file f File number. A file number between 9- 255 can be used.

: Element delimiter e

Element number

Ranges from 0- 255. This is a 1-word element.

/ Bit delimiter b Bit number Bit location within the element. Ranges from 0- 15.

Examples:

A9:2

A10:0/7

Element 2, ASCII file 9

Bit 7, Element 0, ASCII file 10

11–3

Using the String (ST) Data File Type

Note

This file type is valid for SLC 5/03 OS301 and higher, SLC 5/04, and SLC 5/05 processors. These are 42-word elements. You can address string lengths by adding a .LEN to any string address (for example, ST17:1.LEN). Valid string data file numbers are 9–255.

String lengths must be between 0 and 82. In general, lengths that are outside of this range cause the processor to set the ASCII Error bit (S:5/15) and the instruction is not executed.

You configure append or end-of-line characters via the Channel Configuration screen. The default append characters are carriage return and line feed; the default end-of-line (termination) character is a carriage return.

All instructions except ACL and AHL will error if the port is disabled.

Assign string addresses as follows:

Format Explanation

STf:e.s/b

ST String file f File number. A file number between 9- 255 can be used.

: Element delimiter e b

Element number

Bit number

Ranges from 0- 255. These are 42-word elements.

16 bits per element.

.

Subelement delimiter s

Subelement number

Ranges from 0 - 41. Word 0 is the length, .LEN.

/ Bit delimiter

Bit location within the element. Ranges from 0- 15.

Bit level addressing is not available for Word 0 of string elements.

Examples:

ST9:2

ST10:2.3/8

Element 2, string file 9

Bit 8 in subelement 3 of element 2, string file 10

11–4

ASCII Instructions

Entering Parameters

The control element for ASCII instructions includes eight status bits, an error code byte, and two character words:

Word 0

Word 1

Word 2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EN EU DN EM ER UL IN FD | Error Code

Number of characters for sending or receiving (LEN)

Number of characters sent or received (POS)

EN = Enable Bit

EU = Queue Bit

DN = Asynchronous Done Bit

EM = Synchronous Done Bit

ER = Error Bit

UL = Unload Bit

IN = Running Bit (This bit is the IN bit in the control data file [R6:].)

FD = Found Bit

Found Bit FD (bit 8) indicates that the instruction found the end of characters or termination characters in the buffer (applies to ABL and ACB instructions)

Running Bit IN (bit 9) indicates that a queued instruction is executing.

Unload Bit UL (bit 10) ceases instruction operation before (may be queued) or during execution. If this bit is set while an instruction is executing, any data already processed is sent to the destination. Note that the instruction is not removed from the queue; any remaining data is just not processed. You set this bit.

Error Bit ER (bit 11) indicates that an error occurred while executing the instruction, such as a mode change via channel 1, or the instruction was cancelled using the UL bit or ACL instruction.

Synchronous Done Bit EM (bit 12) is set concurrently to a program scan to indicate the completion of an ASCII instruction.

Asynchronous Done Bit DN (bit 13) is set opposite to a program scan when an instruction successfully completes its operation. Note that an instruction can take longer than one program scan to finish executing.

Queue Bit EU (bit 14) indicates that an ASCII instruction was placed in the

ASCII queue. This action is delayed if the queue is already filled. The queue may contain up to 16 instructions.

Enable Bit EN (bit 15) indicates that an instruction is enabled due to a false-to-true transition. This bit remains set until the instruction has completed executing or errors.

11–5

Test Buffer for Line (ABL)

✓ ✓ ✓

ABL

ASCII TEST FOR LINE

Channel

Control

Characters

Error

0

(EN)

(DN)

(ER)

Output Instruction

Use the ABL instruction to determine the total number of characters in the input buffer, up to and including the end-of-line characters (termination). This instruction looks for two termination characters that you configure via the ASCII port configuration screen. On a false-to-true transition, the processor reports the number of characters in the POS field of the ASCII control block. The serial port must be configured for User mode.

Entering Parameters

Enter the following parameters when programming this instruction:

Channel is the number of the RS-232 port (Channel 0).

Control is the area that stores the control register required to operate the instruction.

Characters are the number of characters in the buffer that the processor finds

(0–1024). This parameter is display only and resides in word 2 of the control block.

Error displays the hexadecimal error code that indicates why the ER bit was set

in the control data file (R6:). See page 11–27 for error code descriptions.

Example

[

I:1

[

10

If input slot 1, bit 10 is set, the processor performs an ABL operation for channel 0.

ABL

ASCII TEST FOR LINE

Channel

Control

Characters

Error

0

R6:32

0

EN

DN

ER

When the rung goes from false-to-true, the Enable bit (EN) is set. The instruction is put in the ASCII instruction queue, the Queue bit (EU) is set, and program scan continues. The instruction is then executed outside of the program scan. However, if the queue is empty the instruction executes immediately. Upon execution, the

Run bit (RN) is set.

11–6

ASCII Instructions

The processor determines the number of characters (up to and including the end-of-line/termination characters) and puts this value in the position field. The

Done bit (DN) is then set.

If a zero appears in the POS field, no end-of-line/termination characters were found.

The Found bit (FD) is set if the position field was set to a non-zero value.

When the program scans the instruction and finds the Done bit (DN) set, the processor then sets the Synchronous Done bit (EM). The EM bit acts as a secondary done bit corresponding to the program scan.

The Error bit (ER) is set during the execution of the instruction if:

• the instruction is aborted – serial port not in User mode

• the instruction is aborted due to channel mode change

• the Unload bit (UL) is set and the instruction is not executed

Number of Characters

In Buffer (ACB)

✓ ✓ ✓

ACB

ASCII CHARS IN BUFFER

Channel

Control

Characters

Error

0

(EN)

(DN)

(ER)

Use the ACB instruction to determine the total characters in the buffer. On a false-to-true transition, the processor determines the total number of characters and records it in the position field of the ASCII control block. The serial port must be in

User mode.

Output Instruction

Entering Parameters

Enter the following parameters when programming this instruction:

Channel is the number of the RS-232 port (Channel 0).

Control is the area that stores the control register required to operate the instruction.

Characters are the number of characters in the buffer that the processor finds

(0–1024). This parameter is display only.

Error displays the hexadecimal error code that indicates why the ER bit was set

in the control data file (R6:). See page 11–27 for error descriptions.

11–7

Example

[

I:1

[

10

If input slot 1, bit 10 is set, the processor performs an ACB operation for channel 0.

ACB

ASCII CHARS IN BUFFER

Channel

Control

Characters

Error

0

R6:32

0

EN

DN

ER

When the rung goes from false-to-true, the Enable bit (EN) is set. When the instruction is placed in the ASCII queue, the Queue bit (EU) is set. The Running bit

(RN) is set when the instruction is executing. The Done bit (DN) is set on completion of the instruction.

The processor determines the number of characters in the buffer and puts this value in the position field of the control block. The Done bit (DN) is then set. If a zero appears in the characters field, no characters were found.

When the program scans the instruction and finds the Done bit (DN) set, the processor then sets the Synchronous bit (EM). The EM bit acts as a secondary done bit corresponding to the program scan.

The Error bit (ER) is set during the execution of the instruction if:

• the instruction is aborted – serial port not in User mode

• the instruction is aborted due to channel mode change

• the Unload bit (UL) is set and the instruction is not executed

11–8

ASCII Instructions

String to Integer (ACI)

ACI

STRING TO INTEGER

Source

Dest

Output Instruction

Example

✓ ✓ ✓

Use the ACI instruction to convert an ASCII string to an integer value between

–32,768 and 32,767.

[

I:1

[

10

If input slot 1, bit 10 is set, convert the string in

ST38:90 to an integer and store the result in N7:123

ACI

STRING TO INTEGER

Source

Destination

ST38:90

N7:123

75

The processor searches the source (file type ST) for the first character between 0 and 9. All numeric characters are extracted until a non-numeric character or the end of the string is reached. Action is taken only if numeric characters are found. If the string contains an invalid length ( t

0 or u

82) the ASCII Error bit S:5/15 is set.

Commas and signs (

+,

–) are allowed in the string. However, only the minus sign is displayed in the data table.

The extracted numeric string is then converted to an integer. The ASCII Error bit

S:5/15 is set if the string contains an invalid string length. The value of 32,767 is returned as the result.

This instruction also sets the arithmetic flags (found in word 0, bits 0–3 in the processor status file S:0):

S:0/0

S:0/1

S:0/2

S:0/3

With this Bit:

Carry (C)

Overflow (V)

Zero (Z)

Sign (S)

The Processor:

is reserved.

sets if the integer value is outside of the valid range.

sets if the integer value is zero.

sets if the result is negative.

11–9

ASCII Clear Receive and/or

Send Buffer (ACL)

✓ ✓ ✓

ACL

ASCII CLEAR BUFFER

Channel

Clear Receive Buffer

Clear Send Buffer

Output Instruction

Use this instruction to clear an ASCII buffer. ASCII instructions are removed from the queue and then the Error bit (ER) is set. This instruction executes immediately upon the rung transitioning to a true state. The instruction works when the channel is in User Mode or System Mode. In System Mode, only clearing the send buffer will operate and then only if DF1 is selected as the System Mode protocol.

Entering Parameters

Enter the following parameters when programming this instruction:

Channel is the number of the RS-232 port (Channel 0).

Clear Receive Buffer clears the receive buffer and removes the ARD and ARL instructions from the queue. The Error bit (ER) is set in each of these instructions.

Clear Send Buffer clears the send buffer and removes the AWA and AWT instructions from the queue. The Error bit (ER) is set in each of these instructions.

When Clear Receive Buffer and Clear Send Buffer are both set to Yes, all instructions are removed from the queue.

Example

[

I:1

[

10

If input slot 1, bit 10 is set, then only clear the receive buffer for channel 0.

ACL

ASCII CLEAR BUFFER

Channel

0

Clear Receive Buffer Y

Clear Send Buffer N

When the rung goes true, the selected buffer(s) will be cleared and the ASCII instruction(s) are removed from the ASCII instruction queue.

11–10

ASCII Instructions

String Concatenate (ACN)

✓ ✓ ✓

ACN

STRING CONCATENATE

Source A

Source B

Dest

Output Instruction

The ACN instruction combines two strings using ASCII strings as operands. The second string is appended to the first and the result stored in the destination.

Entering Parameters

Enter the following parameters when programming this instruction:

Source A is the first string in the concatenation procedure.

Source B is the second string in the concatenation procedure.

Destination is where the result of Source A and B is stored.

Example

[

I:1

[

10

If input slot 1, bit 10 is set, concatenate the string in ST37:42 with the string in ST38:91 and store the result in ST52:76.

ACN

STRING CONCATENATE

Source A

Source B

Destination

ST37:42

ST38:91

ST52:76

Only the first 82 characters (0 – 81) are written to the destination.

If the result is t

0 or u

82 the ASCII Error bit S:5/15 is set.

11–11

String Extract (AEX)

AEX

STRING EXTRACT

Source

Index

Number

Dest

Output Instruction

✓ ✓ ✓

Use the AEX instruction to create a new string by taking a portion of an existing string and linking it to a new string.

Entering Parameters

Enter the following parameters when programming this instruction:

Source is the existing string. The source value is not affected by this instruction.

Index is the starting position (from 1 to 82) of the string you want to extract.

(An index of 1 indicates the left-most character of the string.)

Number is the number of characters (from 1 to 82) you want to extract, starting at the indexed position. If the index plus the number is greater than the total characters in the source string, the destination string will be the characters from the index to the end of the source string.

Destination is the string element (ST) where you want the extracted string stored.

Example

[

I:1

[

10

If input slot 1, bit 10 is set, extract 10 characters starting at the 43rd character of ST38:40 and store the result in ST52:75.

AEX

STRING EXTRACT

Source

Index

Number

Destination

ST38:40

42

10

ST52:75

The following conditions cause the processor to set the ASCII Error bit (S:5/15):

• invalid source string length or string length of zero

• index or number values outside of range

• index value greater than the length of the source string

The destination string is not changed in any of the above error conditions. However, the destination will be changed if the index value plus the number value are greater than the string length. Note that the ASCII Error bit (S:5/15) is not set.

11–12

ASCII Instructions

ASCII Handshake Lines (AHL)

✓ ✓ ✓

AHL

ASCII HANDSHAKE LINES

Channel

AND Mask

OR Mask

Control

Channel Status

Error

(EN)

(DN)

(ER)

Use the AHL instruction to set or reset the RS-232 Data Terminal Ready (DTR) and

Request to Send (RTS) handshake control lines for your modem. On a false-to-true transition, the processor uses the two masks to determine whether to set or reset the

DTR and RTS lines, or leave them unchanged. This instruction will operate when the port is in either mode or is disabled.

Output Instruction

Note

Make sure the automatic modem control used by the port does not conflict with this instruction.

Entering Parameters

Enter the following parameters when programming this instruction:

Channel is the number of the RS-232 port (Channel 0).

AND Mask is the type of mask used to reset the DTR and RTS control lines.

Bit 0 corresponds to the DTR line and bit 1 corresponds to the RTS control line.

A 1 at the mask bit causes the line to be reset; a 0 leaves the line unchanged.

Note that mask values do not have a one-to-one correspondence to the modem control lines.

OR Mask is the type of mask used to set the DTR and RTS control lines. Bit 0 corresponds to the DTR line and bit 1 corresponds to the RTS control line. A 1 at the mask bit causes the line to be set; a 0 leaves the line unchanged. Note that mask values do not have a one-to-one correspondence to the modem control lines.

Control is the area that stores the control register required to operate the instruction.

Channel Status displays the current status (0000 to 001F) of the handshake lines for the channel, specified above. This field is display only and resides in word 2 of the control element.

Error displays the hexadecimal error code that indicates why the ER bit was set

in the control data file (R6:). See page 11–27 for error code descriptions.

Bit

Line

Example: The following shows the channel status as 001F.

00

1 because bit

4 is set

F since all bits are set

15 –––8

–reserved

7 6 5 4 3 2 1 0

DTR DCD DSR RTS CTS

1 1 1 1 1

11–13

Example

[

I:1

[

10

If input slot 1, bit 10 is set, bit 0 of the AND mask is set to clear the DTR line. If bits 0 and 1 of the

OR mask are set then set the DTR and RTS lines.

AHL

ASCII HANDSHAKE LINES

Channel

AND Mask

OR Mask

Control

0

ABCD

DACB

R6:23

Channel Status

Error

001F

00

EN

DN

ER

The Error bit (ER) is set during the execution of the instruction if:

• the instruction is aborted due to channel mode change

• the Unload bit (UL) is set and the instruction is not executed

Integer to String (AIC)

AIC

INTEGER TO STRING

Source

Dest

Output Instruction

Example

✓ ✓ ✓

The AIC instruction converts an integer value (–32,768 and 32,767) to an ASCII string. The source can be a constant or an integer address.

[

I:1

[

10

If input slot 1, bit 10 is set, convert the value

867 to a string and store the result in ST38:42.

AIC

INTEGER TO STRING

Source

Destination

867

ST38:42

11–14

ASCII Instructions

ASCII Read Characters (ARD)

✓ ✓ ✓

ARD

ASCII READ

Channel

Dest

Control

String Length

Characters Read

Error

Output Instruction

(EN)

(DN)

(ER)

Use the ARD instruction to read characters from the buffer and store them in a string. To repeat the operation, the rung must go from false-to-true.

Entering Parameters

Enter the following parameters when programming this instruction:

Channel is the number of the RS-232 port (Channel 0).

Destination is the string element where you want the characters stored.

Control is the address of the control block used to store data for the ARD instruction.

String Length (.LEN) is the number of characters you want to read from the buffer. The maximum is 82 characters. If you specify a length larger than 82, only the first 82 characters will be read. (A 0 defaults to 82.) This is word 1 in the control block.

Characters Read (.POS) are the number of characters that the processor moved from the buffer to the string (0 to 82). This field is updated during the execution of the instruction and is display only. This is word 2 in the control block.

Error displays the hexadecimal error code that indicates why the ER bit was set

in the control data file (R6:). See page 11–27 for error code descriptions.

Example

[

I:1

[

10

If input slot 1, bit 10 is set, read 50 characters from the buffer and move to ST52:76.

ARD

ASCII READ

Channel

Destination

Control

String Length

0

ST52:76

R6:23

50

Characters Read 0

Error 00

EN

DN

ER

11–15

11–16

When the rung goes from false-to-true, the Enable bit (EN) is set. When the instruction is placed in the ASCII queue, the Queue bit (EU) is set. The Running bit

(RN) is set when the instruction is executing. The DN bit is set on completion of the instruction.

Once the requested number of characters are in the buffer, the characters are moved to the destination string. The number of characters moved is put in the POS field of the control block. The number in the Characters Read field is continuously updated and the Done bit (DN) is not set until all of the characters are read.

When the program scans the instruction and finds the Done bit (DN) set, the processor then sets the Synchronous Done bit (EM). The EM bit acts as a secondary done bit corresponding to the program scan.

The Error bit (ER) is set during the execution of the instruction if:

• the instruction is aborted – serial port is not in User mode

• the modem is disconnected (control line selection is other than “NO

HANDSHAKING”)

• the instruction is aborted due to channel mode change

• the Unload bit (UL) is set. The instruction stops executing, but received characters are sent to the destination.

• an ACL to clear the receive buffer is executed, removing the ARD instruction from the ASCII queue

ASCII Instructions

Timing Diagram for a Successful ARD, ARL, AWA, and AWT Instruction

Rung Condition

ON

OFF

Enable Bit (EN)

ON

OFF

Queue Bit (EU)

ON

OFF

Running Bit (RN) ON

OFF

Done Bit

Error Bit

(DN or ER)

ON

OFF

Synchronous Done Bit (EM)

ON

OFF

1 2

6

3 4

1 - rung goes true

2 - instruction successfully queued

3 - instruction execution complete

4 - instruction scanned for the first time after execution is complete

5 - rung goes false

6 - either the instruction is not in the queue or it is being executed

5 1 5 2

6

3 4

11–17

ASCII Read Line (ARL)

✓ ✓ ✓

ARL

ASCII Read Line

Channel

Dest

Control

String Length

Characters Read

Error

Output Instruction

(EN)

(DN)

(ER)

Use the ARL instruction to read characters from the buffer, up to and including the end-of-line (termination) characters, and store them in a string. The end-of-line characters are specified via the ASCII Configuration screen.

Entering Parameters

Enter the following parameters when programming this instruction:

Channel is the number of the RS-232 port (Channel 0).

Destination is the string element where you want the characters stored.

Control is the address of the control block used to store data for the ARL instruction.

String Length (LEN) is the number of characters you want to read from the buffer. The maximum is 82 characters. If you specify a length larger than 82, only the first 82 characters are read and moved to the destination. (A 0 defaults to 82.) This is word 1 in the control block.

Characters Read (POS) are the number of characters that the processor moved from the buffer to the string (0 to 82). This field is display only and resides in word 2 of the control block.

Error displays the hexadecimal error code that indicates why the ER bit was set

in the control data file (R6:). See page 11–27 for error code descriptions.

Example

[

I:1

[

10

If input slot 1, bit 10 is set, read 18 characters

(or until end-of-line) from the buffer and move to

ST52:72.

ARL

ASCII READ LINE

Channel

Destination

Control

0

ST52:72

String Length

Characters Read

R6:23

18

0

Error

00

EN

DN

ER

11–18

Note

ASCII Instructions

When the rung goes from false-to-true, the control element Enable (EN) bit is set.

When the instruction is placed in the ASCII queue, the Queue bit (EU) is set. The

Running bit (RN) is set when the instruction is executing. The DN bit is set on completion of the instruction.

Once the requested number of characters are in the buffer, all characters (including the end-of-line characters) are moved to the destination string. The number of characters moved is stored in the POS word of the control block. The number in the

Characters Read field is continuously updated and the Done bit (DN) is not set until all of the characters have been read. Exception: If the processor finds termination characters before done reading, the Done bit (DN) is set and the number of characters found is stored in the POS word of the control block.

When the program scans the instruction and finds the Done bit (DN) set, the processor then sets the Synchronous bit (EM). The EM bit acts as a secondary done bit corresponding to the program scan.

The Error bit (ER) is set during the execution of the instruction if:

• the instruction is aborted – serial port is not in User mode

• the modem is disconnected (control line selection is other than “NO

HANDSHAKING”)

• the instruction is aborted due to channel mode change

• the Unload bit (UL) is set. The instruction stops executing, but received characters are sent to the destination.

• an ACL to clear the receive buffer is executed, removing the ARL instruction from the ASCII queue

For information on the timing of this instruction, refer to the timing diagram on

page 11–17.

11–19

String Search (ASC)

✓ ✓ ✓

ASC

STRING SEARCH

Source

Index

Search

Result

Output Instruction

Use the ASC instruction to search an existing string for an occurrence of the source string.

Entering Parameters

Enter the following parameters when programming this instruction:

Source is the string you want to find when examining the search string.

Index is the starting position (from 1 to 82) of the portion of the string you want to find. (An index of 1 indicates the left-most character of the string.)

Search is the string you want to examine.

Result is an integer where the processor stores the position of the search string where the source string begins. If no match is found, result is set equal to zero.

Example

[

I:1

[

10

If input slot 1, bit 10 is set, search the string in

ST52:80 starting at the 36th character, for the string found in ST38:40. In this example, the result is stored in N10:0.

ASC

STRING SEARCH

Source

Index

Search

Result

ST38:40

35

ST52:80

N10:0

The following conditions cause the processor to set the ASCII Error bit (S:5/15).

• invalid string length or string length of zero

• index value outside of range

• index value greater than the length of the source string

The destination is not changed in any of the above conditions.

11–20

ASCII Instructions

ASCII String Compare (ASR)

✓ ✓ ✓

ASR

ASCII STRING COMPARE

Source A

Source B

Input Instruction

Use the ASR instruction to compare two ASCII strings. The system looks for a match in length and upper/lower case characters. If two strings are identical, the rung is true; if there are any differences, the rung is false.

Entering Parameters

Enter the following parameters when programming this instruction:

Source A is string one for comparison.

Source B is string two for comparison.

Example

ASR

ASCII STRING COMPARE

Source A

Source B

ST37:42

ST38:90

O:1

If the string in ST37:42 is identical to the string in ST38:90, set output bit O:1/1.

1

An invalid string length causes the processor to set ASCII Error bit S:5/15, and the rung goes false.

11–21

ASCII Write with Append (AWA)

✓ ✓ ✓

AWA

ASCII WRITE APPEND

Channel

Source

Control

String Length

Characters Sent

Error

Output Instruction

(EN)

(DN)

(ER)

Use the AWA instruction to write characters from a source string to an external device. This instruction adds the two appended characters that you configure on the

ASCII Configuration screen. The default is a carriage return and line feed appended to the end of the string. When using this instruction you can also perform in-line

indirection. See page 11–24 for more information.

Entering Parameters

Enter the following parameters when programming this instruction:

Channel is the number of the RS-232 port (Channel 0).

Source is the string element you want to write.

Control is the area that stores the control register required to operate the instruction.

String Length (.LEN) is the number of characters you want to write from the source string (0 to 82). If you enter a 0, the entire string will be written. This is word 1 in the control block.

Characters Sent (.POS) are the number of characters that the processor sent to the display area (0 to 82). This field is continuously updated during the execution of the instruction. This value can be greater than the string length if appended characters or inserted values from in-line indirection are used. If the string length is greater than 82, the string written to the destination is truncated to 82 characters. This is word 2 in the control block.

Error displays the hexadecimal error code that indicates why the ER bit was set

in the control data file (R6:). See page 11–27 for error code descriptions.

Example

[

I:1

[

10

If input slot 1, bit 10 is set, read 25 characters from

ST37:42 and write it to the display device. Then write a carriage return and line feed (default).

AWA

ASCII WRITE APPEND

Channel

Source

Control

String Length

0

ST37:42

R6:23

25

Characters Sent

Error

0

00

EN

DN

ER

11–22

Note

ASCII Instructions

When the rung goes from false-to-true, the control element Enable (EN) bit is set.

When the instruction is placed in the ASCII queue, the Queue bit (EU) is set. The

Running bit (RN) is set when the instruction is executing. The DN bit is set on completion of the instruction.

The system sends 25 characters from the start of string ST37:42 to the display device and then sends user-configured append characters. The Done bit (DN) is set and a value of 27 is present in .POS word of the ASCII control block.

When the program scans the instruction and finds the Done bit (DN) set, the processor then sets the Synchronous Done bit (EM) to act as a secondary done bit corresponding to the program scan.

The Error bit (ER) is set during execution of the instruction if:

• the modem is disconnected (control line selection is other than “NO

HANDSHAKING”)

• port is in System Mode and is configured for DH485

• the Unload bit (UL) is set. The instruction stops executing, but received characters are sent to the destination.

• an ACL to clear the send buffer is executed, removing the AWA instruction from the ASCII queue

For information on the timing of this instruction, refer to the timing diagram on

page 11–17.

11–23

Using In-line Indirection

This allows you to insert integer and floating point values into ASCII strings. The

Running bit (RN) must be set before the string value can be used.

The following conditions apply to performing in-line indirection:

• all valid integer (N) and floating point (F) files can be used.

Valid ranges include 7, 8, and 9–255.

• file types are not case sensitive and can include either a colon (:) or semicolon (;)

• positive values and leading zeros are not printed. Negative values are printed with a leading minus sign.

Examples

Note

For the following examples:

N7:0 = 250

N7:1 = –37

F8:0 = 2.015000

F8:1 = 0.873000

Valid in-line indirection:

Input: Flow rate is currently [N7:0] GPH and contains [F8:0] PPM contaminants.

Output: Flow rate is currently 250 GPH and contains 2.015000 PPM contaminants.

Input: Current position is [N7:1] at a speed of [F8:1] RPM.

Output: Current position is –37 at a speed of 0.873000 RPM.

Invalid in-line indirection:

Input: Current position is [N5:1] at a speed of [F8:1] RPM.

Output: Current position is [N5:1] at a speed of 0.873000 RPM.

Truncation occurs in the output string if the indirection causes the output to exceed

80 characters. The appended characters are always applied to the output.

11–24

ASCII Instructions

ASCII Write (AWT)

AWT

ASCII WRITE

Channel

Source

Control

String Length

Characters Sent

Error

Output Instruction

✓ ✓ ✓

(EN)

(DN)

(ER)

Use the AWT instruction to write characters from a source string to an external device. To repeat the instruction, the rung must go from false-to-true. When using

this instruction you can also perform in-line indirection. See page 11–24 for more

information.

Entering Parameters

Enter the following parameters when programming this instruction:

Channel is the number of the RS-232 port (Channel 0).

Source is the string element you want to write.

Control is the area that stores the control register required to operate the instruction.

String Length (LEN) is the number of characters you want to write from the source string (0 to 82). If you enter a 0, the entire string will be written.

Characters Sent (POS) is the number of characters that the processor sent to the display area (0 to 82). Only after the entire string is sent is this field updated (no running total for each character is stored). This field is display only. This value can be greater than the string length if inserted values from in-line indirection are used. If the string length is greater than 82, the string written to the destination is truncated to 82 characters.

Error displays the hexadecimal error code that indicates why the ER bit was set

in the control data file (R6:). See page 11–27 for error code descriptions.

Example

[

I:1

[

10

If input slot 1, bit 10 is set, write 40 characters from ST37:20 to the display device.

AWT

ASCII WRITE

Channel

Source

0

ST37:20

Control

String Length

Characters Sent

R6:23

40

Error

EN

DN

ER

11–25

Note

When the rung goes from false-to-true, the control element Enable (EN) bit is set.

When the instruction is placed in the ASCII queue, the Queue bit (EU) is set. The

Running bit (RN) is set when the instruction is executing. The DN bit is set on completion of the instruction.

Forty characters from string ST37:40 are sent through channel 0. The Done bit

(DN) is set and a value of 40 is present in the POS word of the ASCII control block.

When the program scans the instruction and finds the Done bit (DN) set, the processor then sets the Synchronous Done bit (EM) to act as a secondary done bit corresponding to the program scan.

The Error bit (ER) is set during execution of the instruction if:

• the modem is disconnected (control line selection is other than “NO

HANDSHAKING”)

• port is in System Mode and is configured for DH485

• the Unload bit (UL) is set. The instruction stops executing, but received characters are sent to the destination.

• an ACL to clear the send buffer is executed, removing the AWT instruction from the ASCII queue

For information on the timing of this instruction, refer to the timing diagram on

page 11–17.

11–26

ASCII Instructions

ASCII Instruction Error Codes

Error Code

(HEX)

00

02

03

04

05

07

08

09

0A

0B

0C

0D

0E

0F

The following error codes indicate why the Error bit (ER) is set in the control data file (R6:).

Conditions Resulting in the

Setting of the ER Bit

No error. The instruction completed successfully.

Recommended Action

Operation cannot be completed because the modem went offline.

Transmission cannot be completed because the Clear-to-Send signal was lost.

Cannot perform ASCII receives because the communication channel is configured for System Mode.

While attempting to perform ASCII transmission, System Mode (DF1) communication was detected.

Cannot perform ASCII send or receive because channel configuration has been shut down via the channel configuration menu.

Cannot perform ASCII write due to an ASCII transmission already in progress.

ASCII communication requested is not supported by current channel configuration. (Channel 0 is configured for DH-485 while trying to initiate an ASCII transmission or modem handshake control.)

The Unload bit (UL) was set, stopping instruction execution.

The requested length for the string is either invalid, a negative number, greater than 82, or 0. Applies to ARD and ARL instructions.

The length of the source string is either invalid, a negative number, greater than 82, or 0. Applies to AWA and AWT instructions.

The requested length (.LEN) in the control block is a negative number or a value greater than the string size stored with the source string. Applies to AWA and AWT instructions.

The ACL instruction was aborted.

The channel configuration mode was changed.

None required.

Check modem cabling to communication channel. If the channel is configured for modem handshaking, both the DCD

(Data-Carrier-Detect) and DSR

(Data-Set-Ready) lines to the channel must be active for the modem to be online.

Check modem and modem cabling connections.

Reconfigure the communication channel for User Mode.

Verify that the modem is online and communicating with required devices.

Reconfigure the channel configuration menu and retry operation.

Resend the transmission.

Configure channel 0 for DF1,

Full-Duplex.

None required.

Enter a valid string length and retry operation.

Enter a valid string length and retry operation.

Enter a valid length and retry operation.

None required.

None required.

11–27

ASCII Conversion Table

The table below lists the decimal, hexadecimal, octal, and ASCII conversions.

Column 1 Column 2 Column 3 Column 4

DEC HEX OCT ASC DEC HEX OCT ASC DEC HEX OCT ASC DEC HEX OCT ASC

28

29

30

31

24

25

26

27

20

21

22

23

16

17

18

19

12

13

14

15

08

09

10

11

04

05

06

07

00

01

02

03

1C

1D

1E

1F

18

19

1A

1B

14

15

16

17

10

11

12

13

0C

0D

0E

0F

08

09

0A

0B

04

05

06

07

00

01

02

03

030

031

032

033

034

035

036

037

020

021

022

023

024

025

026

027

010

011

012

013

014

015

016

017

000

001

002

003

004

005

006

007

CAN

EM

SUB

ESC

FS

GS

RS

US

DLE

DC1

DC2

DC3

DC4

NAK

SYN

ETB

FF

CR

SO

SI

BS

HT

LF

VT

NUL

SOH

STX

ETX

EOT

ENQ

ACK

BEL

60

61

62

63

56

57

58

59

52

53

54

55

48

49

50

51

44

45

46

47

40

41

42

43

36

37

38

39

32

33

34

35

3C

3D

3E

3F

38

39

3A

3B

34

35

36

37

30

31

32

33

2C

2D

2E

2F

28

29

2A

2B

24

25

26

27

20

21

22

23

070

071

072

073

074

075

076

077

060

061

062

063

064

065

066

067

050

051

052

053

054

055

056

057

040

041

042

043

044

045

046

047

>

?

<

=

;

:

8

9

6

7

4

5

2

3

0

1

/

.

,

*

+

)

(

&

$

%

SP

!

#

92

93

94

95

88

89

90

91

84

85

86

87

80

81

82

83

76

77

78

79

72

73

74

75

68

69

70

71

64

65

66

67

5C

5D

5E

5F

58

59

5A

5B

54

55

56

57

50

51

52

53

4C

4D

4E

4F

48

49

4A

4B

44

45

46

47

40

41

42

43

130

131

132

133

134

135

135

137

120

121

122

123

124

125

126

127

110

111

112

113

114

115

116

117

100

101

102

103

104

105

106

107

^

_

]

\

[

Z

X

Y

T

U

V

W

R

S

P

Q

L

M

N

O

J

K

H

I

D

E

F

G

@

A

B

C

120

121

122

123

124

125

126

127

112

113

114

115

116

117

118

119

104

105

106

107

108

109

110

111

100

101

102

103

96

97

98

99

7C

7D

7E

7F

78

79

7A

7B

74

75

76

77

70

71

72

73

6C

6D

6E

6F

68

69

6A

6B

64

65

66

67

60

61

62

63

170

171

172

173

174

175

176

177

160

161

162

163

164

165

166

167

150

151

152

153

154

155

156

157

140

141

142

143

144

145

146

147

}

.

~

DEL z

{ x y

v w

t u

r

s p q l m

n o j

k i h d e

f

g b c a

\

11–28

Understanding Interrupt Routines

12

Understanding Interrupt

Routines

This chapter contains general information about interrupt routines and explains how they function in your logic program. Each interrupt routine includes:

• an overview

• programming procedure

• operational description

• associated bit description

In addition, each interrupt routine contains an application example that shows the interrupt routine in use.

Interrupt Routines

Mnemonic

Instruction

Name

STI

DII

ISR

User Fault Routine Provides the option of preventing a processor shutdown.

Selectable Timed

Interrupt

Allows you to interrupt the scan of the main program file automatically, on a periodic basis, to scan a specified subroutine file.

Discrete Input

Interrupt

I/O Interrupt

Allows the processor to execute a subroutine when the input bit pattern of a discrete I/O card matches a compare value that you programmed.

Allows a specialty I/O module to interrupt the normal processor operating cycle in order to scan a specified subroutine file.

12–2

12–7

12–17

12–27

12–1

User Fault Routine Overview

✓ ✓ ✓ ✓ ✓

The user fault routine gives you the option of preventing a processor shutdown when a specific user fault occurs. The file is executed when any recoverable or non-recoverable user fault occurs. The file is not executed for non-user faults.

You do this by programming a ladder subroutine, then specifying that subroutine as the fault routine in word S:29 in the status file. You can handle a number of user

faults in this way, as the example on page 12–4 shows.

Faults are classified as recoverable and non-recoverable user faults, and non-user

faults. A complete list of faults appear in appendix A and B for the

MicroLogix 1000 controllers and the SLC processors respectively.

Non–User Fault

The Fault Routine does not execute.

Non–Recoverable User Fault

The Fault Routine executes for 1 pass.

Note: You may initiate a MSG instruction to another node to identify the fault condition of the processor.

Recoverable User Fault

The Fault Routine may clear the fault by clearing bit

S:1/13.

Status File Data Saved

Data in the following words is saved on entry to the user fault subroutine and re-written upon exiting the subroutine.

S:0 Arithmetic flags

S:13 and S:14 Math register

S:24 Index register

Creating a User Fault Subroutine

Note

To use the user fault subroutine:

1.

Create a subroutine file:

SLC processor valid range is 3–255

Micro Logix 1000 designates File 3

2.

Enter the file number in word S:29 of the status file.

No action is required for MicroLogix 1000 users. S:29 is reserved.

12–2

Understanding Interrupt Routines

SLC Processor Operation

Note

The occurrence of recoverable or non-recoverable user faults causes the processor to read S:29 and execute the subroutine number contained in S:29. If the fault is recoverable, the routine can be used to correct the problem and clear the fault bit

S:1/13. The processor then continues in the REM Run mode.

The routine does not execute for non-user faults.

Words S:20 and S:21 can be examined in your fault routine to pinpoint the file and rung number where the fault occurred. If the fault occurred outside of the ladder scan, this value will contain the rung number where the TND, END, or REF instruction is located. Use words S:20 and S:21 with your powerup protection fault routine to determine the exact point that the previous power down occurred. Refer

to appendix B for more information about the Startup Protection Fault bit, S:1/9.

For SLC 5/02 processors, you must save your program with test single step selected in order for S:20 and S:21 to be activated.

For SLC 5/03 and higher processors, if your program contains four message instructions with the Continuous Operation (CO) bit set, the fault routine’s message instruction is not executed.

MicroLogix Controller Operation

The occurrence of recoverable or non-recoverable user faults causes file 3 to be executed. If the fault is recoverable, the routine can be used to correct the problem and clear the fault bit S:1/13. The processor then continues in the REM Run mode.

The routine does not execute for non-user faults.

12–3

User Interrupt Routine Application Example

Suppose you have a program in which you want to control major errors 0020

(MINOR ERROR AT END OF SCAN)

and 0034

(NEGATIVE VALUE IN

TIMER PRE OR ACC)

under the following conditions:

Prevent a processor shutdown if the overflow trap bit S:5/0 is set. Permit a processor shutdown when S:5/0 is set more than five times.

Prevent a processor shutdown if the accumulator value of timer T4:0 becomes negative. Reset the negative accumulator value to zero. Energize an output to indicate that the accumulator has gone negative one or more times.

Allow a processor shutdown for all other user faults.

A possible method of accomplishing this is shown in the following examples. The user fault routine is designated as file 3.

When a recoverable or non-recoverable user error occurs, the processor scans subroutine file 3. The processor jumps to file 4 if the error code is 0020 and it jumps to file 5 if the error code is 0034. For all other recoverable and non-recoverable errors, the processor exits the fault routine and halts operation in the fault mode.

Fault Routine – Subroutine File 3

Word S:6 is the fault code

(in decimal).

EQU

EQUAL

Source A

Source B

S:6

0

32

Fault Code 0020

(Enter &H20. Decimal equivalent 32 appears.)

EQU

EQUAL

Source A

Source B

S:6

0

52

Fault Code 0034

(Enter &H34. Decimal equivalent 52 appears.)

END

JSR

JUMP TO SUBROUTINE

SBR file number 4

JSR

JUMP TO SUBROUTINE

SBR file number 5

12–4

Understanding Interrupt Routines

Subroutine File 4 – Executed for Error 0020

SBR

SUBROUTINE

S:5

] [

0

CTU

COUNT UP

Counter

Preset

Accum

RET

RETURN

C5:0

120

0

C5:0

(U)

CU

(CU)

(DN)

GRT

GREATER THAN

Source A C5:0.ACC

Source B

0

5

S:5

] [

0

S:5

(U)

0

S:1

(U)

13

RET

RETURN

END

If the overflow trap bit, S:5/0 is set, counter C5:0 increments.

If the count of C5:0 is 5 or less, the overflow trap, S:5/0 is cleared, the major error halted bit S:1/13 is cleared, and the processor remains in the REM Run mode. If the count is greater than 5, the processor sets S:5/0 and S:1/13 and enters the Fault mode.

This subroutine file is also executed if the control register error bit S:5/2 is set. In this case, the processor is placed in the Fault mode.

12–5

Subroutine File 5 – Executed for Error 0034

SBR

SUBROUTINE

LES

LESS THAN

Source A T4:0.ACC

0

Source B 0

S:1

(U)

13

CLR

CLEAR

Dest

RET

RETURN

T4:0.ACC

0

O:3.0

( )

3

END

If the accumulator value of timer T4:0 is negative, the major error halted bit, S:1/13 is unlatched, preventing the processor from entering the Fault mode. At the same time, the accumulator value T4:0 ACC is cleared to zero and output O:3.0/3 is energized. Fault code 0034 is displayed in the status file.

If the preset of timer T4:0 is negative, S:1/13 remains set and the processor enters the Fault mode (O:3.0/3 will be reset if previously set). Also, if either the preset or accumulator value of any other timer in the program is negative, S:1/13 is set and the processor enters the Fault mode. If previously set, O:3.0/3 is reset.

12–6

Understanding Interrupt Routines

Selectable Timed Interrupt Overview

✓ ✓ ✓ ✓ ✓

This function allows you to interrupt the scan of the processor automatically, on a periodic basis, to scan a specified subroutine file. Afterward, the processor resumes executing from the point where it was interrupted.

This section describes:

STI programming procedure

STI operation and parameters

STD and STE instructions

STS instruction

Basic Programming Procedure for the STI Function

Note

To use the STI function in your application file:

1.

Create a subroutine file and enter the desired ladder rungs. This is your STI subroutine file.

SLC processors valid range is 3–255

MicroLogix 1000 controllers designate File 5

2.

SLC processors – Enter the STI subroutine file number in word S:31 of the

status file. Refer to page B–48 in this manual for more information. A file

number of zero disables the STI function.

3.

Enter the setpoint (the time between successive interrupts) in word S:30 of the

status file. Refer to page A–20 for MicroLogix 1000 controllers or B–47 for

SLC processors for more information.

For SLC 5/02 and MicroLogix 1000 controllers, the range is 10–2550 ms

(entered in 10 ms increments). A setpoint of zero disables the STI function.

For SLC 5/03 and higher processors, the range is from 1–32,767 ms

(entered in 1 ms increments). A setpoint of zero disables the STI function.

Refer to appendix B in this manual for more information about the STI

Resolution bit S:2/10.

The setpoint value must be a longer time than the execution time of the STI subroutine file, or a minor error bit is set. For all processors, the STI Pending bit and STI Overrun bit will be set. Additionally, for the SLC 5/03 and higher processors, and MicrLogix 1000 controllers, the STI Last bit may be set.

12–7

Operation

After you restore your program and enter the REM Run mode, the STI begins operation as follows:

1.

The STI timer begins timing.

2.

When the STI interval expires, the STI timer is reset, the processor scan is interrupted and the STI subroutine file is scanned.

3.

If while executing the STI subroutine, another STI interrupt occurs, the STI pending bit is set.

4.

If while an STI is pending, the STI timer expires, the STI lost bit is set. (For

SLC 5/02 processors, the Overrun bit is set.)

5.

When the STI subroutine scan is completed, scanning of the main program file resumes at the point where it left off, unless an STI is pending. In this case, the subroutine is immediately scanned again.

6.

The cycle repeats.

For identification of your STI subroutine, include an INT instruction as the first instruction on the first rung of the file.

STI Subroutine Content

The STI subroutine contains the rungs of your application logic. You can program any instruction inside the STI subroutine except a TND, REF, or SVC instruction.

IIM or IOM instructions are needed in an STI subroutine if your application requires immediate update of input or output points. End the STI subroutine with an RET instruction.

JSR stack depth is limited to 3. You may call other subroutines to a level 3 deep from an STI subroutine.

12–8

Understanding Interrupt Routines

Interrupt Latency and Interrupt Occurrences

Interrupt latency is the interval between the STI timeout and the start of the interrupt subroutine. STI interrupts can occur at any point in your program, but not necessarily at the same point on successive interrupts. The tables below show the interaction between an interrupt and the processor operating cycle.

SLC Processors

Input Scan

Program Scan

Output Scan

Communications

Processor Overhead

Events in the Processor Operating Cycle

MicroLogix Controller

SLC 5/02 STI

SLC 5/03 and Higher

STI with Bit S:33/8 set

Between word updates Between slot updates

Between instruction updates

Between slot updates

Between communication packets

At start and end

Between word updates

Between word updates

Between word packet updates

Between word updates

SLC 5/03 and Higher

STI with Bit S:33/8 cleared

Between slot updates

Between rung updates

Between slot updates

Between communication packets

Between word updates

Input Scan

Program Scan

Output Scan

Communication

Controller Overhead

Events in the processor operating cycle

STI

Between instruction updates

Between communication packets

At start and end

12–9

Note that STI execution time adds directly to the overall scan time. During the latency period, the processor is performing operations that cannot be disturbed by the STI interrupt function.

Latency periods are:

SLC 5/02 processors and MicroLogix 1000 controllers interrupts are serviced within 2.4 ms maximum.

SLC 5/03 and higher processors – If an interrupt occurs while the processor is performing a multi–word slot update and your interrupt subroutine accesses that same slot, the multi–word transfer finishes to completion prior to performing the interrupt subroutine slot access. The Interrupt Latency Control bit (S:33/8) functions as follows:

When the bit is set (1), interrupts are serviced within the interrupt latency

time. Refer to appendix D for more information on how to calculate the

interrupt latency.

When the bit is clear (0), INTs are serviced per rung, slot, and packet execution time.

The default state is cleared (0). To determine the interrupt latency with S:33/8 clear, you must calculate the execution time of each and every rung in your program. Use the longest calculated execution time plus 500

µ s as your maximum interrupt latency.

Interrupt Priorities

Interrupt priorities for the processors are:

MicroLogix 1000 Controller

1. User Fault Routine

SLC 5/02 Processor

1. User Fault Routine

SLC 5/03 and Higher Processors

1. User Fault Routine

2. High–Speed Counter 2. Selectable Timed Interrupt Subroutine 2. Discrete Input Interrupt (DII)

3. Selectable Timed Interrupt Subroutine 3. Interrupt Subroutine (ISR) 3. Selectable Timed Interrupt Subroutine

4. Interrupt Subroutine (ISR)

An executing interrupt can only be interrupted by an interrupt having higher priority.

12–10

Understanding Interrupt Routines

Status File Data Saved

Data in the following words is saved on entry to the STI subroutine and re-written upon exiting the STI subroutine.

S:0 Arithmetic flags

S:13 and S:14 Math register

S:24 Index register

STI Parameters

The following parameters are associated with the STI function. These parameters

have status file addresses that are described here and also in appendix A and

appendix B of this manual.

STI file number (Word S:31) – This can be any number from 3–255. A value of zero disables the STI function. An invalid number generates fault

0023. This word does not apply to MicroLogix 1000 controllers.

Setpoint (Word S:30) This is the time between the starting point of successive scans of the STI file. It can be any value from 10 to 2550 milliseconds. You enter a value of 1 to 255, which results in a

10–2550 ms setpoint. A value of zero disables the STI function. An invalid time generates fault 0024.

If the STI is initiated while in the REM Run mode by loading the status registers, the interrupt will start timing from the end of the program scan in which the status registers were loaded.

SLC 5/03 and higher processors – If S:2/10 is set, time is in 1 ms increments. If this bit is clear, time is in 10 ms increments.

STI Pending Bit (S:2/0) – This bit is set when the STI timer has timed out and the STI routine is waiting to be executed. This bit is reset upon starting the

STI routine, execution of a true STS instruction, powerup, or exit from the

REM Run or Test mode.

SLC 5/02 specific – The STI pending bit is not set if the STI timer expires while executing the fault routine.

SLC 5/03 and higher processors – This bit is set if the STI timer expires while executing the DII subroutine or fault routine.

12–11

12–12

STI Enable Bit (S:2/1) The default value is 1 (set). When a file number between 3 and 255 is present in word S:31 and a setpoint value between 1 and

255 is present in word S:30, a set enable bit allows scanning of the STI file. If the bit is reset by an STD instruction, scanning of the STI file no longer occurs.

If the bit is set by an STE or STS instruction, scanning is again allowed. The enable bit only enables/disables the scanning of the STI subroutine. It does not affect the STI timer. The STS instruction affects both the enable bit and the STI timer. The default state is enabled. If this bit is set or reset using the STE,

STD, or STS instruction, enable/disable takes effect immediately. If this bit is set in the user program using an instruction other than STE, STD, or STS, it takes effect at the next end of scan.

MicroLogix 1000 controller – This bit is set or reset using an STS, STE, or STD instruction. If set, it allows execution of the STI if the STI setpoint S:30 is non–zero. If clear, when an interrupt occurs, the STI subroutine does not execute and the STI Pending bit is set.

SLC 5/02 specific – If this bit is set or reset by the user program or communications, it does not take effect until the next end of scan.

SLC 5/03 and higher processors – If this bit is set or reset by the user program or communications, it takes effect upon the STI timer expiration or next end of scan (whichever occurs first).

STI Executing Bit (S:2/2) – This bit is set when the STI file is being scanned and cleared when the scan is completed. The bit is also cleared on powerup and entry into the REM Run mode.

STI Resolution Selection Bit (S:2/10) – This bit is clear by default. When clear, this bit selects a 10 ms increment for the STI Setpoint (S:30) value. When set, this bit selects a 1 ms increment for the STI Setpoint (S:30) value. To program this feature, use the data monitor function to set/clear this bit, or address this bit with your ladder program.

This bit is user configurable and takes effect on a REM PROG to REM RUN mode transition.

Overrun Bit (S:5/10) – This minor error bit is set whenever the STI timer expires while the STI routine is executing or disabled while the pending bit is set. When this occurs, the STI timer continues to operate at the rate present in word S:30. If the overrun bit becomes set, take the corrective action your application dictates, then clear the bit.

Understanding Interrupt Routines

STI Lost Bit (Word S:36/9) – This bit is set anytime an STI interrupt occurs while the STI Pending bit is also set. When set, you are notified that a STI interrupt has been lost. For example, the interrupt is lost because a previous interrupt was already pending and waiting execution. Examine this bit in your user program and take appropriate action if your application cannot tolerate this condition. Then clear this bit with your user program in order to prepare for the next possible occurrence of this error.

Use the following rungs to initialize and measure the amount of time between two consecutive STI subroutine executions. The 10

µ s timer is also available in the DII interrupt and I/O interrupt. This application example can also be used for the Event

I/O interrupt or the DII interrupt by replacing S:43 with either S:44 or S:45 respectively.

Program Listing Processor File: FREESTI.ACH Rung 2:0

Rung 2:0

Place this rung as the first rung of your main ladder program (file 2 rung 0).

This rung ensures that the interrupt measurement is initialized each time the run mode is entered.

| 1st Indicate |

| Pass measurment |

| initialization |

| |

| S:1 B3 |

|––––] [––––––––––––––––––––––––––––––––––––––––––––––+––––(U)–––––––––––––––+–|

| 15 | 0 | |

| | Clear | |

| | 10 uS | |

| | ”tick” | |

| | Register | |

| | +MOV–––––––––––––––+ | |

| +–+MOVE +–+ |

| |Source 0| |

| | | |

| |Dest N10:2| |

| | 0| |

| +––––––––––––––––––+ | ladder program continued on next page

12–13

Rung 4:0

This rung measures the time between consecutive interrupt subroutine executions.

Integer N10:2 contains the number of 10 microsecond ”ticks” that have occured.

Note that the largest amount of time that can be measured is 0.32767 seconds.

| Determine number |

| of 10 uS ”ticks” |

| When valid since last |

| measurement |

| B3 +SUB–––––––––––––––+ |

|––––––––+––––] [–––––+––––––––––––+SUBTRACT +–+––––––––––––––––––––+–|

| | 0 | |Source A S:43| | | |

| | | | 0| | | |

| | | |Source B N10:1| | | |

| | | | 0| | | |

| | | |Dest N10:2| | | |

| | | | 0| | | |

| | | +––––––––––––––––––+ | | |

| | | | | |

| | | | | |

| | | If rollover | | |

| | | has occurred Normalize the | | |

| | | in timebase result | | |

| | | S:0 +ADD–––––––––––––––+ | | |

| | +––––] [–––––+ADD +–+ | |

| | 3 |Source A 32767| | |

| | | | | |

| | |Source B N10:2| | |

| | | 0| | |

| | |Dest N10:2| | |

| | | 0| | |

| | +––––––––––––––––––+ Store present | |

| | value as last | |

| | value | |

| | +MOV–––––––––––––––+ | |

| +––––––––––––––––––––––––––––––––––––––––––––––+MOVE +–+ |

| | |Source S:43| | |

| | | 0| | |

| | |Dest N10:1| | |

| | | 0| | |

| | +––––––––––––––––––+ | |

| | | |

| | Clear overflow | |

| | error bit | |

| | S:5 | |

| +–––––––––––––––––––––––––––––––––––––––––––––––––(U)–––––––––––––––+ |

| 0 |

Rung 4:99

Place this rung as the last rung of your interrupt subroutine. This way your interrupt subroutine will know when the value in N10:2 is valid.

| |

| Indicate valid |

| measurement |

| B3 |

|––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––(L)–––––|

| 0 |

Note

The math overflow selection bit (S:2/14) must be set prior to entering RUN mode.

12–14

Understanding Interrupt Routines

STD and STE Instructions

✓ ✓ ✓ ✓ ✓

The STD and STE instructions are used to create zones in which STI interrupts

cannot occur.

Selectable Timed Disable – STD

STD

SELECTABLE TIMED DISABLE

When true, this instruction resets the STI enable bit and prevents the STI subroutine from executing. When the rung goes false, the STI enable bit remains reset until a true STS or STE instruction is executed. The STI timer continues to operate while the enable bit is reset.

Selectable Timed Enable – STE

STE

SELECTABLE TIMED ENABLE

This instruction, upon a false-true transition of the rung, sets the STI enable bit and allows execution of the STI subroutine. When the rung goes false, the STI enable bit remains set until a true STD instruction is executed. This instruction has no effect on the operation of the STI timer or setpoint. When the enable bit is set, the first execution of the STI subroutine can occur at any fraction of the timing cycle up to a full timing cycle later.

STD/STE Zone Example

In the program that follows, the STI function is in effect. The STD and STE instructions in rungs 6 and 12 are included in the ladder program to avoid having

STI subroutine execution at any point in rungs 7 through 11.

The STD instruction (rung 6) resets the STI enable bit and the STE instruction (rung

12) sets the enable bit again. The STI timer increments and may time out in the

STD zone, setting the pending bit S:2/0 and overrun bit S:5/10.

The first pass bit S:1/15 and the STE instruction in rung 0 are included to insure that the STI function is initialized following a power cycle. You should include this rung any time your program contains an STD/STE zone or an STD instruction.

12–15

12–16

Program File 3

STI interrupt execution does not occur between STD and STE.

7

8

9

10

11

0

3

4

1

2

5

6

S:1

] [

15

] [ ] [

STE

SELECTABLE TIMED ENABLE

( )

] [

] [

] [

] [

STD

SELECTABLE TIMED DISABLE

( )

( )

STE

SELECTABLE TIMED ENABLE

12

13

14

15

16

17

] [ ] [

END

( )

Understanding Interrupt Routines

Selectable Timed Start (STS)

✓ ✓ ✓ ✓ ✓

STS

SELECTABLE TIMED START

File

Time [x 10ms]

Note

Use the STS instruction to condition the start of the STI timer upon entering the

REM Run mode – rather than starting automatically. You can also use it to set up or change the file number or setpoint/frequency of the STI routine that is executed when the STI timer expires.

This instruction is not required to configure a basic STI interrupt application.

The STS instruction requires you to enter two parameters, the STI file number and the STI setpoint. Upon a true execution of the rung, this instruction enters the file number and setpoint in the status file (S:31, S:30), overwriting the existing data. At the same time, the STI timer is reset and begins timing; at timeout, the STI subroutine execution occurs. When the rung goes false, the STI function remains enabled at the setpoint and file number you’ve entered in the STS instruction.

SLC 5/03 and higher processors –The STS instruction uses the setting of the STI resolution bit S:2/10 to determine the timebase to be used upon STS instruction execution.

Discrete Input Interrupt Overview

✓ ✓ ✓

Use the Discrete Input Interrupt (DII) for high–speed processing applications or any application that needs to respond to an event quickly. This instruction allows the processor to execute a ladder subroutine when the input bit pattern of a discrete I/O card matches a compare value that you programmed.

The status file contains six bit values and six word values used to program and monitor the DII function. The DII does not require ladder logic instructions for configuration. You program the DII to examine the input bit pattern of any single

I/O slot, which contains any discrete input card (such as IG16, IV16, IB8, IB32).

When the input bit pattern matches the compare value, the accumulator is incremented. The DII accumulator counts to the preset value and, once the interrupt is generated, it immediately wraps around and begins counting again at zero.

12–17

Basic Programming Procedure for the DII Function

Note

To use the DII function with your main program file, do the following:

1.

Create a subroutine file (range is from 3 to 255) and enter the desired ladder rungs. This is your DII subroutine file.

2.

Enter the Input Slot number (word S:47).

3.

Enter the Bit Mask (word S:48).

4.

Enter the Compare Value (word S:49).

5.

Enter the Preset Value (word S:50).

6.

Enter the DII subroutine file number in word S:46 of the status file. (See page

B–58.) A zero value disables the DII function.

PLC users – The main difference between the DII and the PLC 5/40 PII is that the

DII requires all stated transitions to occur prior to generating a count, while the PII requires that only one of the stated transitions occur. Also, the PLC term “count” is referred to as “preset” in the DII.

Example

While scanning the DII subroutine, you can reconfigure the DII to look for an entirely different event. This facilitates DII sequencing. The DII can be programmed to compare each input point to either a high (1) or low (0) state. The accumulator is incremented on the input transition that causes the input points to match the compare value.

IIM or IOM instructions are needed in the DII subroutine if your application requires immediate update of input or output points. End the DII subroutine with an

RET instruction.

The DII can be programmed to count items on a high–speed conveyer. Each time

100 items pass a photo-switch, the DII subroutine is executed. The DII subroutine then uses Immediate I/O instructions to package the products.

12–18

Understanding Interrupt Routines

Operation

After you restore your program and enter the REM Run mode, the DII begins operation as follows:

Counter Mode

This mode is active when the preset value (S:50) contains a value greater than 1.

1.

The DII reads the first byte of input data of a selected discrete input card at least once every 100

µ s.

Note that this “polling” of the input data has no effect on processor scan time.

2.

When the input data matches the programmed masked value, the accumulator is incremented by one. The next count occurs when input data transitions to non–matched and then back to matched.

3.

When the accumulator reaches or exceeds the preset value, between 1 and

32,767, the interrupt is generated and the accumulator is reset to zero.

4.

The DII subroutine is executed.

5.

The cycle repeats.

Event Mode

This mode is active when the preset value (S:50) contains a 0 or 1.

1.

The DII reads the first byte of input data of a selected discrete input card at least once every 100

µ s.

Note that this “polling” of the input data has no effect on processor scan time.

2.

When the input data matches the programmed masked value, the interrupt is generated.

3.

The DII subroutine is executed.

4.

The cycle repeats.

You must add interrupt latency time to the final transition or count that causes the interrupt subroutine to execute.

See page D–3 for calculating DII latency.

The DII continues to compare the input data to the programmed masked value while executing the DII subroutine.

12–19

DII Subroutine Content

For identification of your DII subroutine, use the INT instruction as the first instruction in your first rung.

The DII subroutine contains the rungs of your application logic. You can program any instruction inside the DII subroutine except a TND, REF, or SVC instruction.

IIM or IOM instructions are needed in a DII subroutine if your application requires immediate update of input or output points. End the DII subroutine with an RET instruction.

JSR stack depth is limited to 3. You may call other subroutines to a level 3 deep from an DII subroutine.

Interrupt Latency and Interrupt Occurrences

Interrupt latency is the interval between DII detection and the start of the interrupt subroutine. DII interrupts can occur at any point in your program, but not necessarily at the same point on successive interrupts. Interrupts can occur between instructions in your program, inside the I/O scan (between slots), or between the servicing of communications packets. The table below shows the interaction between an interrupt and the processor operating cycle.

Input Scan

Program Scan

Output Scan

Communications

Processor Overhead

DII

Between slot updates

Between instruction updates

Between slot updates

Between communication packets

At start and end

DII with

Bit S:33/8 set

Between word updates

Between word updates

Between word updates

Between word packet updates

Between word updates

DII with

Bit S:33/8 cleared

Between slot updates

Between rung updates

Between slot updates

Between communication packets

Between word updates

Events in the Processor

Operating Cycle

If an interrupt occurs while the SLC 5/03 (or higher) processor is performing a multi-word slot update and your interrupt subroutine accesses that same slot, the multi-word transfer completes prior to performing the interrupt subroutine slot access.

12–20

Understanding Interrupt Routines

Note that DII execution time adds directly to the overall scan time. During the latency period, the processor is performing operations that cannot be disturbed by the DII interrupt function. The Interrupt Latency Control Bit (S:33/8) functions as follows:

When the bit is set (1) interrupts are serviced within the minumum time possible. The time will vary depending upon which processor and

communication protocol you are using. Refer to appendix D for information on

how to calculate interrupt latency when S:33/8 = 1.

The default state is cleared (0). When S:33/8 is clear (0), user interrupts occur between rungs and I/O slot updates. To determine the interrupt latency with

S:33/8 clear, you must calculate the execution time of each and every rung of your program, then the add the execution time of the longest rung to the latency time.

Interrupt Priorities

Interrupt priorities for the SLC 5/03 and higher processors are:

1.

User fault routine

2.

Discrete Input Interrupt (DII)

3.

STI Subroutine

4.

I/O Interrupt Subroutine

An executing interrupt subroutine can only be interrupted by the fault routine.

Status File Data Saved

Data in the following words is saved on entry to the DII subroutine and re-written upon exiting the DII subroutine.

S:0 Arithmetic flags

S:13 and S:14 Math register

S:24 Index register

12–21

Reconfigurability

You can reconfigure the DII entirely or in part, depending on the particular parameter(s) you choose. You can reconfigure some of the parameters simply by writing the new value over the old value. Other values require you to set the reconfiguration bit in addition to writing the new value. The DII is non–retentive and always reconfigures itself upon entry into the REM Run mode. Refer to the next section “DII Parameters” for details on reconfiguring each parameter.

Example

The DII can be programmed to count items on a high–speed conveyer. Each time

100 items pass a photo-switch, the DII subroutine is executed. The DII subroutine then uses Immediate I/O instructions to package the products.

If you want to vary the number of items that are packaged together, simply change the number in the DII preset parameter using a MOV instruction.

12–22

Understanding Interrupt Routines

DII Parameters

The following parameters are associated with the DII function. These parameters

have status file addresses that are described here and also in appendix B.

DII Pending Bit (S:2/11) – When set, this bit indicates that the DII accumulator (S:52) equals the DII preset (S:50) and the ladder file number specified by the DII file number (S:46) is waiting to be executed. It is cleared when the DII file number (S:46) begins executing, or on exit from the REM

Run or REM Test mode.

DII Enable Bit (S:2/12) – To program this feature, use the data monitor function to set/clear this bit, or address this bit with your ladder program. This bit is set in its default condition. If set, it allows execution of the DII subroutine if the DII file (S:46) is non–zero. If clear, when the interrupt occurs, the DII subroutine will not execute and the DII Pending bit is be set. The DII function continues to run anytime the DII file (S:46) is non–zero. If the pending bit is set, the enable bit is examined at the next end of scan.

DII Executing Bit (S:2/13) – When set, this bit indicates that the DII interrupt has occurred and the DII subroutine is currently being executed. This bit is cleared on completion of the DII routine, powerup, or REM Run mode entry.

DII Overflow Bit (S:5/12) – This bit is set whenever the DII interrupt occurs while still executing the DII subroutine or whenever the DII interrupt occurs while pending or disabled.

Reconfigure Bit (S:33/10) – When this bit is set (1), it indicates that at the next end of scan (END, TND, or REF), fault routine exit, STI ISR exit, Event

ISR exit, or next DII ISR exit the:

DII accumulator is cleared,

– values at status words S:47 to S:50 are applied,

– the pending bit is cleared, and

– the DII Reconfigure bit is cleared.

DII Lost Bit (S:36/8) – This bit is set if a DII interrupt occurs while the DII

Pending bit is set.

File Number (Word S:46) – You enter a program file number (3 to 255) to be used as the discrete input interrupt subroutine. Write a 0 value to disable the function. This value is applied upon detection of a DII Reconfigure bit, each

DII ISR exit, and each end of scan (END, TND, or REF). A zero disables operation.

Slot Number (Word S:47) – You enter the slot number (1 to 30) to be used as the discrete input interrupt subroutine. A zero value disables the function. This value is applied on detection of the DII Reconfigure bit, or on entry into the

REM Run mode.

12–23

12–24

Bit Mask (Word S:48) – You enter the bit-mapped value that corresponds to the bits you wish to monitor on the discrete I/O module. Only bits 0 to 7 are used in the DII function. Setting a bit indicates that you wish to include the bit in the comparison of the discrete I/O card’s bit pattern to the DII compare value

(S:49). This value is applied on detection of the DII Reconfigure bit, each DII

ISR exit, and at each end of scan (END, TND, or REF).

Compare Value (Word S:49) – You enter a bit-mapped value that corresponds to the bit pattern that must occur on the discrete I/O card for a count or interrupt to occur. Only bit 0 to 7 are used in the DII function. The bit must be set (1) or cleared (0) in order to satisfy the compare condition for that bit. An interrupt or count is generated upon the last bit transition of the compare value. This value is applied on detection of DII Reconfigure bit, each

DII ISR exit, and at each end of scan (END, TND, or REF).

To provide protection from inadvertent data monitor alteration of your selection, program an unconditional MOV instruction containing the compare value of the

DII to S:49.

Preset (Word S:50) – When this value is equal to 0 or 1, an interrupt is generated each time the comparison specified in words S:48 and S:49 is satisfied. When this value is between 2 and 32767, a count occurs each time the bit comparison is satisfied. An interrupt is generated when the accumulator value reaches 1 or exceeds the preset value. This value is applied on detection of DII Reconfigure bit, each DII ISR exit, and at each end of scan (END, TND, or REF).

To provide protection from inadvertent data monitor alteration of your selection, program an unconditional MOV instruction containing the preset value of the

DII to S:50.

Return Mask (Word S:51) – The Return Mask is updated immediately preceding entry into the DII subroutine. This value contains the bit map of the last bit transition that caused the interrupt. If more than one bit transitions in the same 100

µ s DII sample period, it is included in the return mask. This bit is cleared by the processor on exit from the DII subroutine. Use this value to validate the last interrupt transition that caused the input pattern to match the compare value. Or when dynamically reconfiguring (sequencing) the DII, use this value inside of your DII’s subroutine to help determine/validate its position of the sequence.

Accumulator (Word S:52) – The DII accumulator contains the number of counts that have occurred. When a count occurs and the accumulator is greater than or equal to the preset value, a DII interrupt is generated and the accumulator is cleared.

For applications that measure the rate of incoming DII pulses while using a STI

(Selectable Timed Interrupt), SLC 5/03 OS301 and above updates the DII accumulator prior to executing the first rung of the STI subroutine.

Understanding Interrupt Routines

Discrete Input Interrupt Application Example

The following example shows how to use the Discrete Input Interrupt to control a high–speed application. In the example, the DII is used to ensure that all bottles exiting a filling and capping machine have their caps installed.

The bottle proximity switch is used as the DII input. When a bottle passes the proximity switch, the processor executes the DII subroutine. In the subroutine the processor reads the state of the cap proximity switch. If the cap is installed, the chute solenoid does not energize; allowing the bottle to continue down the line. If the cap is missing, the chute solenoid energizes, causing the defective bottle to divert down the chute and into the reject bin.

Cap Proximity (I:1/8)

Bottle Proximity (I:1/0)

Chute (O:2/0)

Reject Bin

The following parameters are used to program the DII for the above application:

S:33/8 Interrupt Latency Control Bit = 1

S:46 File = 3

S:47 Slot = 1

S:48 Mask = 00000001

S:49 Compare = 00000001

S:50 Preset = 1

12–25

Ladder Diagram for the Bottling Application

Rung 3:0

This rung uses the state of the proximity switch to sense the presence or absence of a bottle cap.

INT

I/O INTERRUPT

Bit 8 is the cap proximity switch.

IIM

IMMEDIATE IN w MASK

Slot I:1.0

Mask 0100

Rung 3:1

If a bottle cap is present, and the chute is in the reject position, set the chute position to normal.

If prox. switch detects bottle cap installed

And if the chute is in the reject position

Move chute to normal position.

I:1.0

] [

8

O:2.0

] [

0

O:2.0

(U)

0

Update chute position.

IOM

IMMEDIATE OUT w MASK

Slot O:2.0

Mask 0001

Rung 3:2

If no bottle cap is present, set the chute position to reject.

If proximity switch detects a missing bottle cap

I:1.0

]/[

8

Move chute to reject position.

O:2.0

(L)

0

Update chute position.

IOM

IMMEDIATE OUT w MASK

Slot O:2.0

Mask 0001

Rung 3:3

RET

RETURN

Rung 3:4

END

Refer to appendix H for another application example using the DII to count pulses

from an encoder.

12–26

Understanding Interrupt Routines

I/O Interrupt Overview

✓ ✓ ✓ ✓

This function allows a specialty I/O module to interrupt the normal processor operating cycle in order to scan a specified subroutine file. Interrupt operation for a specific module is described in the user’s manual for the module.

Not all specialty I/O modules are capable of generating I/O interrupts. Refer to the user manual of the specific specialty I/O module to see if it supports this feature.

For example, you cannot use a standard discrete I/O module to accomplish an I/O event–driven interrupt.

This section describes:

I/O operation

I/O interrupt parameters

IID and IIE instructions

RPI instruction

INT instruction

Basic Programming Procedure for the I/O Interrupt Function

When you are configuring the specialty I/O module slot with the programming device, make sure you program the “ISR” (interrupt subroutine) program file number (range 3 to 255) that you want the processor to execute when the module generates an interrupt. Specialty I/O modules that create interrupts should be configured in the lowest numbered I/O slots.

Create the subroutine file that you have specified as the ISR number in the I/O module slot configuration.

12–27

Operation

When you restore your program and enter the REM Run mode, the I/O interrupt begins operation as follows:

1.

The specialty I/O module determines that it needs servicing and generates an interrupt request to the SLC processor.

2.

The processor is interrupted from what it is doing, and the specified interrupt subroutine file (ISR) is scanned.

3.

When the ISR scan is completed, the specialty I/O module is notified. This informs the specialty I/O module that it is allowed to generate a new interrupt.

4.

The processor resumes normal operation from where it left off.

Interrupt Subroutine (ISR) Content

The Interrupt Subroutine (INT) instruction should be the first instruction in your

ISR. This identifies the subroutine file as an I/O interrupt subroutine.

The ISR contains the rungs of your application logic. You can program any instruction inside an ISR except a TND, REF, or SVC instruction. IIM or IOM instructions are needed in an ISR if your application requires immediate update of input or output points. Terminate the ISR with an RET (return) instruction.

JSR stack depth is limited to 3. That is, you may call other subroutines to a level 3 deep from an ISR.

12–28

Understanding Interrupt Routines

Interrupt Latency and Interrupt Occurrences

Interrupt latency is the interval between the I/O module’s request for service and the start of the interrupt subroutine. I/O interrupts can occur at any point in your program, but not necessarily at the same point on successive interrupts. Interrupts can only occur between instructions in your program, inside the I/O scan (between slots), or between the servicing of communication packets. The following table shows the interaction between an interrupt and the processor operating cycle.

Input Scan

Program Scan

Output Scan

Communications

Processor Overhead

SLC 5/02 I/O Interrupts

5/03 and Higher

I/O Interrupts with Bit

S:33/8 set

Between word updates Between slot updates

Between instruction updates

Between slot updates

Between communication packets

At start and end

Between word updates

Between word updates

Between word packet updates

Between word updates

5/03 and Higher

I/O Interrupts with Bit

S:33/8 cleared

Between slot updates

Between rung updates

Between slot updates

Between communication packets

Between word upates

Events in the Processor

Operating Cycle

Note that ISR execution time adds directly to the overall scan time. During the latency period, the processor is performing operations that cannot be disturbed by the STI interrupt function. Latency periods are:

SLC 5/02 interrupts are serviced within 2.4ms maximum.

SLC 5/03 and higher processors – If an interrupt occurs while the processor is performing a multi-word slot update and your interrupt subroutine accesses that same slot, the multi-word transfer finishes to completion prior to performing the interrupt subroutine slot access. The Interrupt Latency Control bit (S:33/8) functions as follows:

When the bit is set (1) interrupts are serviced within the interrupt latency

time. Refer to appendix D for more information on how to calculate the

interrupt latency.

When S:33/8 is clear (0), user interrupts occur between rungs and I/O slot updates.

The default state is cleared (0). To determine the interrupt latency with S:33/8 clear, you must calculate the execution time of each and every rung in your program.

12–29

Interrupt Priorities

Interrupt priorities are as follows:

SLC 5/02 Processor

1. Fault Routine

2. STI Subroutine

3. I/O Interrupt Subroutine (ISR)

SLC 5/03 and Higher Processors

1. Fault routine

2. Discrete Input Interrupt (DII)

3. STI Subroutine

4. I/O Interrupt Subroutine (ISR)

Note

Note

An executing interrupt can only be interrupted by an interrupt having higher priority. The I/O interrupt cannot interrupt an executing fault routine, an executing

DII subroutine, an executing STI subroutine, or another executing I/O interrupt subroutine. If an I/O interrupt occurs while the fault routine, DII, or STI subroutine is executing, the processor waits until the higher priority interrupts are scanned to completion. The I/O interrupt subroutine is then scanned.

SLC 5/02 specific – It is important to understand that the I/O Pending bit associated

with the interrupting slot remains clear during the time that the processor is waiting

for the fault routine or STI subroutine to finish.

SLC 5/03 and higher processors – The I/O pending bit is always set when the interrupt occurs. You can examine the state of these bits within your higher priority interrupt routines.

If a major fault occurs while executing the I/O interrupt subroutine, execution immediately switches to the fault routine. If the fault was recovered by the fault routine, execution resumes at the point that it left off in the I/O interrupt subroutine.

Otherwise, the fault mode is entered.

If a DII interrupt occurs while executing the I/O interrupt subroutine, execution immediately switches to the DII subroutine. When the DII subroutine is scanned to completion, execution resumes at the point that it left off in the I/O interrupt subroutine.

If the STI timer expires while executing the I/O interrupt subroutine, execution immediately switches to the STI subroutine. When the STI subroutine is scanned to completion, execution resumes at the point that it left off in the I/O interrupt subroutine.

If two or more I/O interrupt requests are detected by the processor at the same instant, or while waiting for a higher or equal priority interrupt subroutine to finish, the interrupt subroutine associated with the specialty I/O module in the lowest slot number is scanned first. For example, if slot 2 (ISR 20) and slot 3 (ISR 11) request interrupt service at the same instant, the processor first scans ISR 20 to completion, then ISR 11 to completion.

12–30

Understanding Interrupt Routines

Status File Data Saved

Data in the following words is saved on entry to the I/O interrupt subroutine and re-written upon exiting the I/O interrupt subroutine.

S:0 Arithmetic flags

S:13 and S:14 Math register

S:24 Index register

I/O Interrupt Parameters

The I/O interrupt parameters below have status file addresses. They are described

here and also in appendix B of this manual.

ISR Number – Specifies the subroutine file number that will be executed when an I/O interrupt is generated by an I/O module. The ISR Numbers are not part of the status file, but they are part of the I/O configuration for each slot in the

SLC system.

I/O Slot Enables (Words S:11 and S:12) – These words are bit mapped to the 30 I/O slots. Bits S:11/1 through S:12/14 refer to slots 1 through 30. Bits

S:11/0 and S:12/15 are reserved.

The enable bit associated with an interrupting slot must be set when an interrupt occurs. Otherwise a major fault will occur. Changes made to these bits using the Data Monitor function take effect at the next end of scan.

I/O Interrupt Pending Bits (Words S:25 and S:26) – These words are bit mapped to the 30 I/O slots. Bits S:25/1 through S:26/14 refer to slots 1 through

30. Bits S:25/0 and S:26/15 are reserved. The pending bit associated with an interrupting slot is set when the corresponding I/O slot interrupt enable bit is clear at the time of an interrupt request. It is cleared when the corresponding

I/O event interrupt enable bit is set, or when an associated RPI instruction is executed. The pending bit for an executing I/O interrupt subroutine remains clear when the ISR is interrupted by a DII, STI, or fault routine.

SLC 5/02 specific – Likewise, the pending bit remains clear if interrupt service is requested at the time that a higher or equal priority interrupt is executing

(fault routine, STI, or other ISR).

SLC 5/03 and higher processors – This bit is set if interrupt service is requested at the time a higher or equal priority interrupt is executing (fault routine, DII,

STI, or other ISR).

12–31

12–32

I/O Interrupt Enables (Words S:27 and S:28) These words are bit mapped to the 30 I/O slots. Bits S:27/1 through S:28/14 refer to slots 1 through

30. Bits S:27/0 and S:28/15 are reserved. The enable bit associated with an interrupting slot must be set when the interrupt occurs to allow the corresponding ISR to execute. Otherwise the ISR will not execute and the associated I/O slot interrupt pending bit will be set.

SLC 5/02 specific – Changes made to these bits using the data monitor function or ladder instruction take effect at the next end of scan.

SLC 5/03 and higher processors – Changes made to these bits using the data monitor function or ladder instruction take effect immediately.

I/O Interrupt Executing (Word S:32) – This word contains the slot number of the specialty I/O module that generated the currently executing ISR. This value is cleared upon completion of the ISR, run mode entry, or upon power up.

You can interrogate this word inside of your DII or STI subroutine or fault routine if you wish to know if these higher priority interrupts have interrupted an executing ISR. You may also use this value to discern interrupt slot identity when multiplexing two or more specialty I/O module interrupts to the same

ISR.

Understanding Interrupt Routines

I/O Interrupt Disable (IID) and

I/O Interrupt Enable (IIE)

✓ ✓ ✓ ✓

These instructions are generally used in pairs to prevent I/O interrupts from occurring during time-critical or sequence-critical portions of your main program or subroutine. The I/O Event-Driven Interrupt function is used with specialty I/O modules capable of generating an interrupt.

IID

I/O INTERRUPT DISABLE

Slots: 1,2,7

IIE

I/O INTERRUPT ENABLE

Slots: 1,2,7

Use these instructions together to create a zone in your main ladder program file or subroutine file in which I/O interrupts cannot occur. Both instructions take effect immediately upon execution. You must specify a subroutine to be executed upon receipt of such an interrupt.

SLC 5/02 specific – Setting/clearing the I/O interrupt enable bits (S:27 and S:28) with a programming device or standard instruction such as MVM takes effect at the

END of the scan only.

SLC 5/03 and higher processors – Setting/clearing the I/O interrupt enable bits

(S:27 and S:28) with a programming device or standard instruction such as MVM takes effect immediately.

IID Operation

When true, this instruction clears the I/O interrupt enable bits (S:27/1 through

S:28/14) corresponding to the slots parameter of the instruction (slots 1, 2, 7 in the example above). Interrupt subroutines of the affected slots are not able to execute when an interrupt request is made. Instead, the corresponding I/O pending bits

(S:25/1 through S:26/14) are set. The ISR is not executed until an IIE instruction with the same slot parameter is executed, or until the end of the scan during which you use a programming device to set the corresponding status file bit.

IIE Operation

When true, this instruction sets the I/O interrupt enable bits (S:27/1 through

S:28/14) corresponding to the slots parameter of the instruction (slots 1, 2, 7 in the example above). Interrupt subroutines of the affected slots regain the ability to execute when an interrupt request is made. If an interrupt was pending (S:25/1 through S:26/14) and the pending slot corresponds to the IIE slots parameter, the

ISR associated with that slot executes immediately.

12–33

IID/IIE Zone Example

In the program below, slots 1, 2, and 7 are capable of generating I/O interrupts. The

IID and IIE instructions in rungs 6 and 12 are included to avoid having I/O interrupt

ISRs execute as a result of interrupt requests from slots 1, 2, or 7. This allows rungs

7 through 11 to execute without interruption.

The first pass bit S:1/15 and the IIE instruction in rung 0 are included to insure that the I/O interrupt function is initialized following a power cycle. You should include a rung such as this any time your program contains an

IID/IIE zone or an IID instruction.

The IID instruction in rung 6 clears the I/O interrupt enable bits associated with slots 1, 2, and 7 (S:27/1,

S:27/2, and S:27/7). The IIE instruction in rung 12 sets these same bits. If an I/O interrupt is detected by the processor while the processor is executing rungs 7–11, the interrupt will be marked as pending. (S:25/1, S:25/2, and/or S:25/7 will be set.) All interrupts marked as pending are serviced upon execution of rung 12. The lowest numbered slot is serviced first when multiple pending bits are set.

0

3

4

1

2

5

6

S:1

] [

15

] [ ] [

Program File 2

IIE

I/O INTERRUPT ENABLE

Slots: 1,2,7

( )

IID

I/O INTERRUPT DISABLE

Slots: 1,2,7

ISR execution will not occur between IID and IIE instructions.

7

8

9

10

11

12

] [ ] [

] [ ] [

( )

( )

IIE

I/O INTERRUPT ENABLE

Slots: 1,2,7

( )

13

14

15

16

17

] [ ] [

END

12–34

Understanding Interrupt Routines

Reset Pending Interrupt (RPI)

RPI

RESET PENDING INTERRUPT

Slots: 1–30

✓ ✓ ✓ ✓

This instruction resets the pending status of the specified slots and informs the corresponding I/O modules that you have aborted their interrupt requests. This instruction is not required to configure a basic I/O interrupt application.

When true, this instruction clears the I/O pending bits (S:25/1 through S:26/14) corresponding to the slots parameter of the instruction. In addition, the processor notifies the specialty I/O modules in those slots that their interrupt request was aborted. Following this notice, the slot may once again request interrupt service.

This instruction does not affect the I/O slot interrupt enable bits (S:27/1 through

S:28/14).

Entering Parameters

Enter the I/O slot numbers (1 to 30) involved. Examples:

6 indicates slot 6

6,8

6–8

1–30 indicates slots 6 and 8 indicates slots 6, 7, and 8 indicates all slots

Interrupt Subroutine (INT)

INT

INTERRUPT SUBROUTINE

✓ ✓ ✓ ✓ ✓

Use the INT instruction in I/O event-driven interrupt subroutines (ISRs) and STIs for identification purposes. Use of this instruction is optional.

This instruction has no control bits and is always evaluated as true. When used, the

INT should be programmed as the first instruction of the first rung of the ISR.

12–35

12–36

SLC Communication Protocols

13

SLC Communication Protocols

Use the information in this chapter to understand the differences in the communication protocols. The following protocols are supported:

DH-485 Communication Protocol

Data Highway Plus Communication Protocol

DF1 Via RS-232 Communication Protocol

ASCII Communication Protocol

Ethernet Communication Protocol

In addition, operation of the Global Status Word (S:99) is provided.

Overview

DH-485 Protocol — The SLC 500 processors have a DH-485 channel that supports the DH-485 communication network. This network is a multi-master, token-passing network protocol capable of supporting up to 32 devices (nodes). This protocol allows:

• monitoring of data and processor status, along with program uploading and downloading of any device on the network from one location

SLC processors to pass data to each other (peer-to-peer communication)

• operator interface devices on the network to access data from any SLC processor on the network

Data Highway Plus (DH

+

) Protocol — The Data Highway Plus protocol is used by the SLC 5/04 processor. This protocol is similar to DH-485, except that it can support up to 64 devices (nodes) and runs at faster communication (baud) rates.

13–1

Note

DF1 Full-Duplex Protocol — DF1 Full-Duplex protocol (also referred to as DF1 point-to-point protocol) allows two devices to communicate with each other at the same time. This protocol allows:

• transmission of information across modems (dial-up, leased line, radio, or direct cable connections)

• communication to occur between Allen-Bradley products and third-party products

You can connect to a DeviceNet network using the DeviceNet Interface (DNI), catalog number 1761-NET-DNI. The DNI provides a single DeviceNet connection point and a single RS-232 connection. The DNI is a DeviceNet to DF1 protocol conversion device that allows DF1 devices to communicate on DeviceNet.

For additional information on using the DNI, see the DeviceNet Interface (DNI)

Overview, publication 1761-1.23, or the DeviceNet Interface (DNI) User Manual, publication 1761-6.5.

DF1 Half-Duplex Protocol (Master and Slave) — DF1 Half-Duplex protocol provides a multi-drop single master/multiple slave network capable of supporting up to 255 devices (nodes). This protocol also provides modem support and is ideal for

SCADA (Supervisory Control and Data Acquisition) applications because of the network capability.

ASCII Protocol — The ASCII protocol provides connection to other ASCII devices, such as bar code readers, weigh scales, serial printers, and other intelligent devices.

Ethernet TCP/IP Protocol — The Ethernet protocol is used by the SLC 5/05 processor. Standard Ethernet, utilizing the TCP/IP protocol, is used as the backbone network in many office and industrial buildings. Ethernet is a local area network that provides communication between various devices at 10 Mbps. This network provides the same capabilities as DH+ or DH-485 networks, plus:

SNMP support for Ethernet network management

• optional dynamic configuration of IP addresses using a BOOTP utility

SLC 5/05 Ethernet data rate up to 40 times faster than SLC 5/04 DH+ messaging

• ability to message entire SLC 5/05 data files

• an unlimited number of nodes on a single network are possible compared to

DH-485 (32) and DH+ (64)

13–2

SLC Communication Protocols

The following table summarizes the communication options for the SLC 500 processor family.

Protocol Fixed

DH485 peer-to-peer receive only

SLC 5/01

receive only

Processor

SLC 5/02 SLC 5/03

receive and initiate receive and initiate

–– receive and initiate

––

SLC 5/04

––

SLC 5/05

DH485 via RS232 port

–– –– receive and initiate

➀ receive and initiate

DF1 via RS232 port

(full-duplex or half-duplex master or slave)

ASCII via RS232 port

Data Highway Plus

(DH+) receive only

–– receive only

➂ receive only

–– receive only

➂ receive only

–– receive only

➁ receive

➂ and initiate receive and initiate receive and initiate

➃ receive and initiate receive and initiate receive and initiate receive and initiate receive and initiate receive and initiate

Ethernet –– –– –– –– –– receive and initiate

If using 1747-AIC for isolation, connect to DH-485 network using 1747-PIC; if using 1761-NET-AIC for isolation, directly connect to DH-485 network with 1747-CP3 serial cable (or equivalent RS-232 null-modem cable).

A 1747-KE or 1770-KF3 is required to bridge from DF1 (full-duplex or half-duplex slave only) to DH485.

A 1785-KA5 is required to bridge from DH+ to DH485.

Either a 1785-KA5 is required to bridge from DH+ to DH485 or the SLC-5/04’s channel-to-channel passthru feature may be used to bridge between DH+ and DH485 or between DH+ and DF1 Full-Duplex (DH+ -to- DF1 Full-Duplex passthru available starting with OS401). Another option is to use the 1785-KE to bridge between DH+ and DF1 Full-Duplex or DH+ and a DF1 Half-Duplex Master/Slave network.

Note

The 1785-KA5 and 1785-KE modules require use of a 1771-series chassis and power supply.

13–3

DH-485 Communication Protocol

✓ ✓

The DH-485 network offers:

• interconnection of 32 devices

• multi-master capability

• token passing access control

• the ability to add or remove nodes without disrupting the network

• maximum network length of 1219 m (4,000 feet)

✓ ✓ ✓ ✓

DH-485 Network Protocol

The following section describes the protocol used to control message transfers on the DH-485 network. The protocol supports two classes of devices: initiators and responders. All initiators on the network get a chance to initiate message transfers.

To determine which initiator has the right to transmit, a token passing algorithm is used.

DH-485 Token Rotation

A node holding the token can send valid packets onto the data link. The token hold parameter determines the number of transmissions (plus retries) each time the node receives the token.

After a node sends one message packet, it attempts to give the token to its successor by sending a “token pass” packet. If no network activity occurs, the initiator attempts to find a new successor.

Note

Note

The node address range for an initiator is 0-31. The node address range for all responders is 1-31. There must be at least one initiator on the network.

The maximum address that the initiator searches for before wrapping to zero is the value in the configurable parameter “maximum node address.” The default value of this parameter is 31 for all initiators and responders.

The fixed, SLC 500 processors do not allow node address zero to be applied. If you attempt to apply a zero, node address one becomes the processor node address.

Node address zero is reserved for a programming device, such as the Hand-Held

Terminal (HHT) or personal computer running programming software.

13–4

SLC Communication Protocols

DH-485 Network Initialization

Network initialization begins when a period of inactivity exceeds the time of a “link dead timeout.” When the time for the “link dead timeout” is exceeded, usually the initiator with the lowest address claims the token.

Building a network begins when the initiator that claimed the token tries to pass the token to the successor node. If the attempt to pass the token fails, or if the initiator has no established successor (for example, when it powers up), it begins a linear search for a successor starting with the node above it. It will wrap to node 0 upon reaching its maximum node address value.

When the initiator finds another active initiator, it passes the token to that node, which repeats the process until the token is passed all the way around the network to the first node. At this point, the network is in a state of normal operation.

Software Considerations

Software considerations include the configuration of the network and the parameters that can be set to the specific requirements of the network. The following are major configuration factors that have a significant effect on network performance:

• number of nodes on the network

• addresses of those nodes

• baud rate

• maximum node address selection

SLC 5/03 and higher – token hold factor

• maximum number of communicating devices

The following sections explain network considerations and describe ways to select parameters for optimum network performance (speed).

Number of Nodes

The number of nodes on the network directly affects the data transfer time between nodes. Unnecessary nodes (such as a second programming terminal that is not being used) slow the data transfer rate. The maximum number of nodes on the network is 32.

13–5

Setting Node Addresses

The best network performance occurs when node addresses start at 0 and are assigned in sequential order. SLC 500 processors default to node address 1. The node address is stored in the processor status file (S:15L). Processors cannot be node 0. Also, initiators such as personal computers should be assigned the lowest numbered addresses to minimize the time required to initialize the network.

If some nodes are connected on a temporary basis, do not assign addresses to them.

Simply create nodes as needed and delete them when they are no longer required.

Setting Processor Baud Rate

The best network performance occurs at the highest baud rate. All devices must be at the same baud rate. The default DH-485 baud rate for SLC 500 devices is 19.2K

baud. The baud rate is stored in the processor status file (S:15H).

Maximum Node Address Setting

The maximum node address parameter should be set as low as possible. This minimizes the amount of time used in soliciting successors when initializing the network. If all nodes are addressed in sequence from 0, and the maximum node address is equal to the address of the highest addressed node, the token rotation will improve by the amount of time required to transmit a solicit successor packet plus the slot timeout value.

Maximum Number of Communicating Devices

SLC 500 fixed and SLC 5/01 processors can be selected by two initiators, maximum at the same time. Using more than two initiators to select the same SLC 500 fixed and SLC 5/01 processors at the same time can cause communication timeouts.

13–6

Catalog Number

1746-BAS

1747-KE

1770-KF3

SLC Communication Protocols

DH-485 Configuration Parameters

When the system mode driver for channel 0 or channel 1 is DH-485 Master, the following parameters can be changed:

Parameter

Diagnostic File

Baud Rate

Node Address

Max Node Address

Token Hold Factor

Description

Reserved for future use.

Toggles between the communication rate of 110, 300, 600, 1200, 2400,

4800, 9600, and 19200. The default is 19200.

This is the node address of the processor on the DH-485 network. The valid range is 1–31. The default is 1.

This is the maximum node address of an active processor. The valid range is 1–31. The default is 31.

Determines the number of transactions allowed to make each DH-485 token rotation. Increasing this value allows your processor to increase its DH-485 throughput. This also decreases throughput to other processors on the

DH-485 link. The valid range is 1–4. The default is 1. The SLC 5/01 and

SLC 5/02 processors are factory set to 1.

The following devices use the DH-485 network:

Description

BASIC

Module

DH-485/DF1

Interface

Module

DH-485/DF1

Interface

Module

Installation

Requirement

Function

SLC Chassis Provides an interface for SLC 500 devices to foreign devices. Program in BASIC to interface the 3 ports (2 RS-232 and 1 DH-485) to printers, modems, or the DH-485 network for data collection.

SLC Chassis Provides a non-isolated DH-485 interface for SLC

500 to host computers over RS-232 using full- or half-duplex DF1 protocol. Enables remote programming using your programming software to an SLC 500 processor or the DH-485 network through modems. Ideal for low cost RTU/SCADA applications.

Standalone

“desktop”

Provides an isolated DH-485 interface for SLC

500 devices to host computers over RS-232 using full- or half-duplex DF1 protocol. Enables remote programming using your programming software to an SLC 500 processor or the DH-485 network through modems.

Publication

1746-6.1

1746-6.2

1746-6.3

1747-6.12

1770-6.5.18

13–7

Catalog Number

1784-KR

1785-KA5

2760-RB

1747-DTAM,

2707-L8P1, -L8P2,

-L40P1, -L40P2,

-V40P1, -V40P2,

-V40P2N, -M232P3, and -M485P3

2711-K5A2, -B5A2,

-K5A5, -B5A5, -K5A1,

-B5A1, -K9A2, -T9A2,

-K9A5, -T9A5, -K9A1, and -T9A1

Description

PC DH-485

Interface

DH

Module

+

/DH485

Gateway

Flexible

Interface

Module

Installation

Requirement

IBM XT/AT

Computer Bus

(1771) PLC I/O

Chassis

(1771) PLC

Chassis

Function

Provides an isolated DH-485 port on the back of the computer. When used with APS software, it improves communication speed and eliminates use of the Personal Interface Converter

(1747-PIC). The Standard Driver allows you to write “C” programs for data acquisition applications.

Provides communication between stations on the

PLC-5 (DH

+

) and

SLC 500 (DH-485) networks.

Provides an interface for SLC 500 (using protocol cartridge 2760-SFC3) to other A-B PLC processors and devices. Three configurable ports are available to interface with Bar Code,

Vision, RF, Dataliners, and PLC systems.

Publication

1784-2.23

6001-6.5.5

1785-6.5.5

1785-1.21

2760-ND00

1

DTAM,

DTAM Plus, and DTAM

Micro

Operator

Interfaces

PanelView

550 and

PanelView

900 Operator

Terminals

Panel Mount

Panel Mount

Provides electronic operator interface for

SLC 500 processors.

Provides electronic operator interface for SLC

500 processors.

1747-ND01

3

2707-800,

2707-803

2711-802,

2711-816

13–8

SLC Communication Protocols

Data Highway Plus

Communication Protocol

Important

Data Highway Plus implements peer-to-peer communication with a token-passing scheme to rotate link mastership among a maximum of 64 nodes. Since this method does not require polling, it helps provide time-efficient reliable data transport. The

DH

+

features:

• remote programming of PLC-2, PLC-3, PLC-5 and SLC 500 processors on your network

• direct connections to PLC-5 processors and industrial programming terminals

• easy re-configuration and expansion if you want to add more nodes later

• communication rates of 57.6K baud, 115.2K baud, or 230.4K baud

A programming device, such as an IBM compatible PC, using a 1784-KT

Communication Interface module does not operate faster than 57.6K baud. The

1784-KTXD can operate at all three communication rates.

The DH

+

uses factory set timeouts to restart token-passing communication if the token is lost because of a defective node.

Example

The example below shows the connectivity of an SLC 5/04 processor to a PLC-5 processor using the DH+ protocol. A communication rate of 57.6K baud is used.

IBM compatible 386SX or later with one of the following

1784-KT

1784-KT2 (PS2)

1784-KTX

1784-KL (T47)

PLC–5/15

DH

+

Network

SLC 5/04

Modular I/O Controller

13–9

Example

Note

The example below shows a DH+ protocol using two SLC 5/04 controllers using the high baud rates of 115.2K baud or 230K baud.

DH+ communication rates 115.2K baud and 230K baud are not available for the programming terminal unless a 1784-KTX card is used together with WINtelligent

LINX or RSLinx. In the example below the programming terminal is connected to the serial port of the SLC 5/04 processor to enter the higher baud rate. This method uses the DF1 to DH+ passthru feature. For more information on passthru see

chapter 8.

SLC 5/04

Modular I/O Controller

DH

+

Network

SLC 5/04

Modular I/O Controller

DH

+

Channel 1 Configuration Parameters (SLC 5/04 processors only)

When the system mode driver is DH

+

for channel 1 the following parameters can be changed:

Baud Rate

Parameter

Node Address

Global Status Word Transmit Enable

Global Status Word Receive Enable

Description

Toggles between the communication rate of 57.6K,

115.2K, and 230.4K. The default is 57.6K. Make sure all devices on your DH+ link are configured for the same communication rate.

Valid range is 0–77 octal. The default is 1.

Toggles between 0 and 1. The default is 0.

Toggles between 0 and 1. The default is 0.

This parameter is only available for SLC 5/04 (OS401) processors.

13–10

SLC Communication Protocols

Global Status Word Overview

Note

When a processor passes the DH+ token to the next node, it also sends a 16-bit word called the Global Status Word (GSW). Every node on the network sees the token pass message, but only the “next” node on the network accepts the token. However, all of the nodes on the network read the Global Status Word sent with each token pass and save it to memory. Each processor on the DH+ network has a table in memory to store Global Status Word(s) it receives from other nodes. In each

SLC 5/04 processor’s status file, there is a designation for the:

Global Transmit Word

This word is located in memory at S:99. If, in your ladder program you move data to this memory location, it is transmitted every time the processor passes the DH+ token. Note that all other DH+ nodes see this data.

Global Status File

This file is located in memory at S:100 to S:163, representing one memory location for each of the 64 possible nodes on the DH+ network. As other nodes transmit Global Status information with their token passes, the SLC 5/04 processor collects this information and stores it in the Global Status File.

Memory location S:100 corresponds to node #0 (octal), S:101 corresponds to node #2 (octal), and S:163 corresponds to node #77 (octal).

One word of every node’s Global Status File is updated each token pass. This can function as a high-speed broadcast message, useful for status passing and synchronization of processors.

If the Global Status Word Transmit Enable bit (S:34/3) and Global Status Word

Receive bit (S:34/4) are never set, you can use the Global Status File (S:100 to

S:163) for other storage uses. If these bits are used and then reset, the area in the

System Status File is never altered by the SLC 5/04 processor, even after a power cycle to the processor.

The System Status File must be at least 164 words in length for Global Status Word transmissions and receptions to take place. This means a user program for use with

OS400 will not support the Global Status Word feature.

13–11

S:34/3 Global Status Word Transmit Enable Bit

(SLC 5/04 with OS401)

Transmission of the Global Status Word is enabled by setting bit S:34/3 in the status file. If this bit is set (1), the processor transmits the data in S:99 with every DH+ token pass. If this bit is not set (0), the processor passes the token and does not attach the Global Status Word. This bit is dynamically configurable and the default setting is zero. Keep the following guidelines in mind when using the Global Status

Word Transmit Enable bit:

If this bit is not set, the DH+ Token Pass transmitted out Channel 1 will contain no Global Status Word bytes

If this bit is set, but the SLC 5/04 is not in RUN mode, REMote Run, or one of the three test modes, the DH+ Token Pass transmission will contain a 2-byte

Global Status Word of 0x0000.

If this bit is set and the SLC 5/04 is in RUN mode, REMote Run, or one of the three tests modes the DH+ Token Pass transmission will contain a 2-byte GSW equal to the value in S:99 (Global Status Word). The word is also placed in the

64-word Global Status File (S:100 to S:163) in the location corresponding to the

DH+ node address associated with the SLC 5/04 processor.

For example, if the SLC 5/04 processor is operating at octal address 22 (18 decimal), the transmitted GSW is written to word S:118.

The word in the Global Status File corresponding to the SLC 5/04 processor’s

DH+ address will be set to 0x0000 if any thing is done to inhibit the transmission of the Global Status Word from S:99. This includes:

– clearing S:34/3, Global Status Word Transmit Enable bit

– placing the SLC 5/04 into a mode other than Run mode or Test mode

– disabling Channel 1

– an error occurring on the DH+ link to cause the Channel 1 LED to flash red or go solid red (This could be caused by a duplicate node address.)

– not having an OS401 user program downloaded to the SLC 5/04 processor

If S:34/3 is not set from the time the SLC 5/04 is powered up, the word corresponding to its DH+ address in the Global Status File will never be written to during the end-of-scan.

13–12

SLC Communication Protocols

S:34/4 Global Status Word Receive Enable Bit

(SLC 5/04 with OS401)

Receiving the Global Status Words of other processors on the network is enabled by setting bit S:34/4 in the status file. If this bit is set (1), the processor fills in the

Global Status File with Global Status Words transmitted by other processors on the network. If this bit is not set (0), the processor ignores any Global Status Word activity on the network. This bit is dynamically configurable and the default setting is zero. Note that transmitting and receiving Global Status Words are independent of each other.

Keep the following guidelines in mind when using the Global Status Word Receive

Enable bit:

If this bit is not set, the Global Status File (S:100 to S:163) is not updated with

Global Status Word information being passed on the link.

An error occurring on the DH+ link to cause the Channel 1 LED to flash red or go solid red disables Global Status Word receptions. (This could be caused by a duplicate node address.)

Global Status File (S:100-S:163) support is enabled when the following four conditions are met:

Channel 1 is configured for DH+ protocol communication

– the System Status File is at least 164 words in length

– the Global Status Word Receive Enable bit (S:34/3) is set

– operation on the DH+ link is working (Channel 1 LED is green)

The only processor mode that Global Status Word reception will not operate in is while downloading a program.

13–13

Note

Note that all 164 words are updated during each end-of-scan. The following table describes possible states of the DH+ node address and the value written to the

Global Status Word (S:99).

State of the DH+ Node Address

Device is not active on the DH+ link

Device is active on the DH+ link, but not sending

GSW bytes in its Token Pass

Device is active on the DH+ link and is sending 1 byte of GSW data in its Token Pass

Value written into S:99 by the SLC 5/04 processor

0x0000

0x0000

Device is active on the DH+ link and is sending 2 bytes of GSW data in its Token Pass

Device is active on the DH+ link and is sending 3 or 4 bytes of GSW data in its Token Pass

High byte is set to 0x00; Low byte is set equal to

1 byte of GSW data

High byte is set equal to the second byte; Low byte is set equal to the first byte (or High and

Low bytes are set equal to each other)

High byte is set equal to the second byte; Low byte is set equal to the first byte, and the third and fourth bytes are ignored

If the Global Status File (S:100-S:163) is working and then Channel 1 is disabled, the entire Global Status File is zeroed out.

If the Global Status File (S:100-S:163) is working and bit S:34/4 is reset, the entire Global Status File is zeroed out except for the one word corresponding to the Channel 1 DH+ node address.

If the Global Status File (S:100-S:163) is working and then a DH+ link error occurs, the entire Global Status File is zeroed out. If the SLC 5/04 processor recovers from the error on its own, then the Global Status File updating resumes automatically.

If the Global Status File (S:100-S:163) is working and then a user program with a System Status File of less than 164 words is downloaded, the SLC 5/04 processor detects this before any further updating of the Global Status File is attempted. In other words, no corruption of the user program results even if all other criteria are still met to support the GSW reception table feature.

The SLC 5/04 processor maintains a working Global Status Word table regardless if

Channel 1 DH+ Active Node Table operation is enabled, (by setting S:34/1). To view the Global Status Word table using your programming software, S:34/1 must be set in addition to meeting all of the above requirements.

13–14

SLC Communication Protocols

PLC–5 to SLC 500 Communication Using PLC–2

Type MSG Commands

Note

The SLC processors can send MSGs to a PLC-5 processor two ways:

If you are using this release:

SLC 5/03 OS300

SLC 5/03 OS301 and later

SLC 5/04

SLC 5/05

Use this MSG instruction to communicate to a PLC-5 processor:

type 485CIF (PLC-2 emulation)

For information, see this section.

type PLC-5 (the preferred method)

type 485CIF (PLC-2 emulation)

For information, see page 13–18

Program a PLC-5 message instruction as type PLC-2 when accessing an SLC 500 processor. Newer enhanced PLC-5 processors also support SLC typed read and write messages in their message instruction.

PLC-2 Unprotected Reads and Writes are not really implemented as “unprotected” in the SLC processor. They are subject to the SLC’s file protection schemes. For instance, they are rejected if a download is in process or the Common Interface File,

(CIF) is already open by another device. These types of read and write commands are somewhat “universal” in that they are implemented in many other Allen-Bradley programmable controllers.

The CIF is actually like any of the other SLC data files except that it is designated as the target file for all PLC-2 Unprotected Read and Unprotected Write commands that are received by the SLC. It is always File #9. The CIF can be defined as Bit,

Integer, Timer, Counter, or Control Data types. However, only Bit or Integer files should be used to make addressing easier.

You cannot use the SLC 5/02 message instruction to send a message through a

1785-KA5 module. However, you can use the SLC 5/03 message instruction to send a message to the 1785-KA5 module. The SLC 5/03 processor has the ability to respond to data read/write requests when the 1785-KA5 is in the “router mode.”

The fixed SLC 500, SLC 5/01, and SLC 5/02 processors cannot respond to data read/write requests. When the 1785-KA5 is in the gateway mode, all SLC 500 processors can respond to Data Highway Plus data read/write requests.

File #9 must be created and defined at the time that the SLC is programmed. File

#9 must also be made large enough to include the Unprotected Read and Write addressing space. Otherwise, all Unprotected Reads and Writes will be rejected by the SLC.

13–15

How the PLC-5 Processors Address Data

When programming a PLC-2 type of MSG instruction on the PLC-5, the

“Destination Address” is entered in octal. The PLC-5 processor automatically translates the octal address to a byte address by doubling the decimal equivalent.

Therefore, 010

8

becomes 16 and 177

8

becomes 254. You cannot enter an octal address less than 010

8

in a PLC-2 type PLC-5 Message instruction.

Using the SLC 500 CIF File (PLC-2 Emulation)

The CIF can be thought of as a data buffer between all the other SLC data files and the DH-485 channel. The SLC must be programmed, using ladder logic, to transfer data between the CIF and the other data files as shown here.

Note

SLC Ladder

Program

Data Files

#0 - #8,

CIF (File #9)

DH-485

Unprotected Read

Unprotected Write

SLC 500

#10 - #255

The CIF can be managed by designating areas to be written to and areas to be read from. If it is desired to know when data has changed in the CIF, use ladder logic to program handshaking bits in your CIF data.

Although the format of the Unprotected Reads and Writes is the same as used in other PLC processors, the implementation of the address parameter is different. In

Allen-Bradley’s PLC products, the address is interpreted as a byte address. In some

SLC 500 products, the address is interpreted as a word address.

The SLC 500 and SLC 5/01 processors use word addressing exclusively.

The SLC 5/02, prior to Series C FRN 3 processors, also use word addressing

exclusively.

The SLC 5/02, SLC 5/03, SLC 5/04, and SLC 5/05 processors have a selection

bit, S:2/8, which allows selection of either word or byte addressing.

The DTAM for the SLC uses word addressing exclusively.

13–16

SLC Communication Protocols

Programming to Handle the Word/Byte Addressing Differences

SLC 500 processors use word addressing while PLC-5 processors use byte addressing. One byte in the PLC-5 processors equals two words in the SLC 500 processor.

The following section describes the differences between word and byte addressing when sending messages to/from a PLC-5 processor via PLC-2 commands.

Sending a PLC-2-Type Message to a PLC-5 Processor by Using SLC “Word” Addressing

(S:2/8 = 0)

The PLC-5 Message instruction’s PLC-2 type octal “Destination Address” must be between 010

8

and 177

8

. This range corresponds to word 16 through word 254 (even words only) when S:2/8 equals zero.

Sending a PLC-2 Type Message to a PLC-5 Processor Using SLC “Byte” Addressing

(S:2/8 = 1)

Note

The byte addressing mode is selected in the SLC by setting bit S:2/8 to 1. The

default is S:2/8 = 0 for word addressing. This selection bit is not available in the

SLC fixed or SLC 5/01 processors. This setting applies to the offset byte/word.

The PLC-5 Message instruction’s octal “Destination Address” must be between

010

8

and 377

8

. This range corresponds to word 8 through word 254 when S:2/8 equals 1.

200

...

377

e na on ddre Oc al

010

011

...

177

SLC Address

Word Mode (S:2/8=0) Byte Mode (S:2/8=1)

N9:16 N9:8

N9:18

...

N9:254

N9:9

...

N9:127

N9:128

...

N9:255

The maximum value for the PLC-5 processor PLC-2-type instruction “Size in

Elements” parameter is 41 for a SLC 5/02 processor and 110 for a SLC 5/03 processor (assuming 1 word elements).

13–17

Example - Sending a PLC-2 Type Message to a PLC-5 Processors Using “word” addressed

SLC processors (S:2/8 = 0)

As an example, write 10 words from N7 in a PLC-5 to an SLC 5/02:

1.

Set up the source address in the message instruction as N7:0.

2.

Set the “Size in elements” to 10.

3.

Set up the “Command Type” as “PLC-2 Unprotected Write.”

4.

Set up the “Destination Address” as 010

8

. This corresponds to the SLC address,

N9:16.

Since 10 words are written, make sure that the N9 file in the SLC is created to at least N9:25.

It is assumed that the MSG instruction will be set up for a remote destination, since there must be a bridge between the PLC-5 and the SLC 5/02, such as a 1784-KA5

(in gateway mode) linking a DH

+

and a DH-485 network.

Example - Sending a PLC-2 Type Message to a PLC-5 Processor using “byte” addressed

SLC processors (S:2/8 = 1)

As an example, write 10 words from N7 in a PLC-5 to an SLC 5/02:.

1.

Set up the source address in the message instruction as N7:0.

2.

Set the “Size in elements” to 10.

3.

Set up the “Command Type” as “PLC-2 Unprotected Write.”

4.

Set up the “Destination Address” as 010

8

. This corresponds to the SLC address,

N9:7.

Since 10 words will be written, make sure that the N9 file in the SLC is created to at least N9:17.

SLC 5/03, SLC 5/04, and SLC 5/05 Processors to PLC-5

Communication Using SLC 500 or PLC-5 MSG Commands

The SLC 5/03 (OS301), SLC 5/04, and SLC 5/05 processors support PLC-5 type

MSG commands. This eliminates having to program PLC-2 type MSGs.

13–18

SLC Communication Protocols

When you want to access:

PLC-5 processors

1785-KA5 communication interface module

SLC 5/03

SLC 5/04

SLC 5/05

Program the MSG instruction as:

type PLC-5 MSG type SLC 500

The SLC 5/03 (OS301), SLC 5/04, and SLC 5/05 processors accept PLC-5 type

MSG commands to read and write the status, bit, timer, counter, control, integer, floating point, string, and ASCII data files. However, the SLC 5/03 (OS301),

SLC 5/04, and SLC 5/05 processors do not accept PLC-5 type MSG commands to read or write to/from input and output files due to the difference between the PLC-5 processor’s chassis/group addressing structure and the SLC 500’s slot/word addressing structure. Additionally, the PLC-5 processor currently does not accept any SLC 500 MSG commands.

When programming a PLC-5 type MSG instruction, the source and destination data types should match. For consistency in the data transfer, we recommend that the destination and source data types match when you are transferring data between the

PLC-5 processors and SLC 5/03 (OS301), SLC 5/04, and SLC 5/05 processors.

When programming an SLC MSG instruction, the source and destination data types do not have to match.

The destination data type determines the number of words per element to transfer.

For example, T4:0 destination and a N7:0 source with a length of 3 results in a transfer of 9 integer words due to a Timer element size of 3 words per element.

13–19

DF1 Via RS-232 Communication Protocol

✓ ✓ ✓

The SLC 5/03, SLC 5/04, and SLC 5/05 processors support DF1 Full-Duplex protocol and DF1 Half-Duplex master/slave protocol via the RS-232 connection to a host computer (using DF1 channel). Refer to DF1 Protocol and Command Set

Reference Manual, publication 1770-6.5.16, for more information on these communication protocols.

For more information about using the SLC 500 processors in SCADA applications, see the:

SCADA System Selection Guide, publication AG-2.1

SCADA System Application Guide, publication AG-6.5.8

DF1 Full-Duplex Protocol

DF1 Full-Duplex protocol (also referred to as DF1 point-to-point protocol) is provided for applications where RS-232 point-to-point communication is required.

This type of protocol supports simultaneous transmissions between two devices in both directions. You can use channel 0 as a programming port, or as a peer-to-peer port using the MSG instruction.

In full-duplex mode, the SLC 5/03 (or higher) processor can send and receive messages. When the processor receives messages, it acts as an end device — a device that stops the transmission of data packets. The processor ignores the destination and source addresses received in the data packets. However, the processor exchanges these addresses in the reply that it transmits in response to any command data packet that it has received.

If you use a modem with DF1 channel 0 in the full-duplex mode, it must be capable of operating in full-duplex mode. Typically, a dial-up modem is used for communication over telephone lines.

DF1 Full-Duplex Channel 0 Configuration Parameters

When the system mode driver is a DF1 Full-Duplex for channel 0 the following parameters can be changed:

13–20

SLC Communication Protocols

Parameter

Diagnostic File

Baud Rate

Description

Reserved for future use.

Toggles between the communication rate of 110, 300, 600, 1.2K, 2.4K, 4.8K, 9.6K, and 19.2K

(additional rate of 38.4K for SLC 5/05 only).

The default is 1.2K for SLC 5/03 and SLC 5/04, and 19.2K for the SLC 5/05.

Parity

Stop Bits

Toggle between None and Even. The default is None.

Toggles between 1, 1.5, and 2. The default is 1.

Duplicate Packet Detection Toggles between Disabled and Enabled. The default is Enabled.

Error Detection Toggles between CRC and BCC. The default is CRC.

ACK Timeout

NAK Retries

ENQ Retries

Control Line

Embedded Responses

Source ID

Valid range is 2–65535 (in 20 ms increment) The default is 50.

Valid range is 0–255. The default is 3.

Valid range is 0–255. The default is 3.

Toggles between No Handshaking and Full-Duplex modem. The default is No Handshaking.

Toggles between Enabled and Auto-Detect. The default is Enabled.

Specify the address of the sender in this field. Valid range is 0–254. The default is 9.

Full-Duplex (Point-to-Point)

Channel 1

DH-485

SLC 5/03 CPU

(1747-L532)

Full-Duplex (Point-to-Point)

Full-Duplex

Modem

DF1 Protocol

Modem

Channel 1

DH-485

SLC 5/03 CPU

(1747-L532)

Channel 0

RS-232

1747-CP3

Channel 0

RS-232

13–21

Full-Duplex (Network)

Host computer capable of calling and interfacing with one network at a time.

Modem

Modem

SLC 5/03 CPU

(1747-L532)

Channel 1

DH-485

Channel 0

RS-232

13–22

Interface Module

(1747-KE)

SLC 5/03 CPU

(1747-L532)

Modem

Link Coupler

(1747-AIC)

1747-AIC

1747-AIC

Modem

This configuration allows the host to call more than one remote network.

Each remote network can consist of up to 31 SLC nodes.

SLC Communication Protocols

DF1 Half-Duplex Master/Slave Protocol

DF1 Half-Duplex Master/Slave protocol provides a multi-drop single master/multiple slave network. In contrast to DF1 full-duplex, communication takes place in one direction at a time. You can use channel 0 as a programming port, or as a peer-to-peer port using the MSG instruction.

The master device initiates all communication by “polling” each slave device. The slave device may only transmit data packets when it is polled by the master. It is the master’s responsibility to poll each slave on a regular and sequential basis to collect data. During a polling sequence, the master polls a slave repeatedly until the slave indicates that it has no more data packets to transmit. The master then transmits the data packets for that slave.

Several Allen-Bradley products support half-duplex master protocol. They include the enhanced PLC-5 processors, SLC 5/03 (OS301 and higher), SLC 5/04, and

SLC 5/05 processors. WINtelligent Linx and RSLinx (V2.0 and higher) software also support half-duplex master protocol.

Typically, the master keeps two separate tables -– one for online slaves and one for offline slaves. The online slaves are polled on a regular basis. The offline slaves are polled occasionally to see if they have come back online.

A master device supports routing of data packets from one slave to another.

DF1 half-duplex supports up to 255 slave devices (address 0 to 254) with address

255 reserved for master broadcasts. Either half-duplex or full-duplex modem types can be used for DF1 half-duplex network. The SLC 5/03, SLC 5/04, and SLC 5/05 support broadcast reception, but cannot initiate a broadcast command.

13–23

DF1 Half-Duplex Slave Channel 0 Configuration Parameters

When the system mode driver is DF1 Half-Duplex Slave for channel 0 the following parameters can be changed:

Parameter

Diagnostic File

Baud Rate

Parity

Stop Bits

Station Address

Duplicate Packet Detection

Error Detection

RTS Off Delay

RTS Send Delay

Poll Timeout

Pre-send Time Delay

Message Retries

Control Line

EOT Suppression

Description

Reserved for future use.

Toggles between the communication rate of 110, 300, 600, 1.2K,

2.4K, 4.8K, 9.6K, and 19.2K (additional rate of 38.4K for SLC 5/05 only). The default is 1.2K for SLC 5/03 and SLC 5/04, and 19.2K

for the SLC 5/05.

Toggles between None and Even. The default is None.

Toggles between 1, 1.5, and 2. The default is 1.

The valid range is 0–254 decimal. The default is 1.

Toggles between Enabled and Disabled. The default is Enabled.

Toggles between CRC and BCC. The default is CRC.

Allows you to select the RTS off delay value in increments of

20 ms. The valid range is 0–65535. The default is 0.

Allows you to select the RTS send delay value in increments of

20 ms. The valid range is 0–65535. The default is 0.

Allows you to select the master poll timeout value in increments of

20 ms. The default is 50. The valid range is 0–65535.

Allows you to select the RTS pre-transmit time delay in increments of 20 ms. The valid range is 0–65535. The default is 0.

Allows you to select the message retries value. The valid range is

0–255. The default is 3.

Toggles between No Handshaking, Half-Duplex with continuous carrier, and Half-Duplex without continuous carrier. The default is

No Handshaking.

Toggles between Yes and No. The default is No.

13–24

SLC Communication Protocols

DF1 Half-Duplex Master Channel 0 Configuration Parameters

When the system mode driver is DF1 Half-Duplex Master for channel 0, the following parameters can be changed:

Parameter

Diagnostic File

Baud Rate

Parity

Stop Bits

Station Address

Duplicate Packet Detection

Error Detection

ACK Timeout

RTS Off Delay

Message Retries

RTS Send Delay

Pre-send Time Delay

Control Line

Polling Mode

Priority Polling – Low

Normal Polling – Low

Priority Polling – High

Normal Polling – High

Reply Message Wait Time

Normal Poll Group Size

Description

Reserved for future use.

Toggles between the communication rate of 110, 300, 600, 1.2K,

2.4K, 4.8K, 9.6K, and 19.2K (additional rate of 38.4K for SLC 5/05 only). The default is 1.2K for SLC 5/03 and SLC 5/04, and 19.2K

for the SLC 5/05.

Toggles between None and Even. The default is None.

Toggles between 1, 1.5, and 2. The default is 1.

The valid range is 0–254 decimal. The default is 1.

Toggles between Enabled and Disabled. The default is Enabled.

Toggles between CRC and BCC. The default is CRC.

Allows you to select the ACK timeout value in increments of 20 ms.

The valid range is 0–65535. The default is 50.

Allows you to select the RTS off delay value in increments of

20 ms. The valid range is 0–65535. The default is 0.

Allows you to select the message retries value. The valid range is

0–255. The default is 3.

Allows you to select the RTS send delay value in increments of

20 ms. The valid range is 0–65535. The default is 0.

Allows you to select the RTS pre-transmit time delay in increments of 20 ms. The valid range is 0–65535. The default is 0.

Toggles between No Handshaking, Full-Duplex Modem, and

Half-Duplex Without Continuous Carrier.

Toggles between Message Based (Do Not Allow Slave to Initiate

Messages), Message Based (Allow Slave to Initiate Messages),

Standard (Single Message Transfer Per Node Scan), and Standard

(Multiple Message Transfer Per Node Scan).

Allows you to select the Priority Polling Range Low Address. The valid range is 0–255.

Allows you to select the Normal Polling Range Low Address. The valid range is 0–255.

Allows you to select the Priority Polling Range High Address. The valid range is 0–254.

Allows you to select the Normal Polling Range High Address. The valid range is 0–254.

Allows you to select the Reply Message Wait Time setting in increments of 20 ms. The valid range is 0–65535.

Allows you to select the Normal Poll Group Size. The valid range is 0–255.

13–25

DF1 Half-Duplex Master

RS-232

(DF1 Half-Duplex

Protocol)

Modem

WINtelligent Linx or RSLinx (V2.0 or higher)

Running DF1 Half-Duplex Protocol (Master)

Modem Modem Modem

Modem

Modem

SLC 5/02 Processor

Modular Controller with 1747-KE

Interface Module

SLC 5/03 Processor

Modular Controller

SLC 5/03 Processor

Modular Controller

SLC 5/01 Processor

Modular Controller with 1747-KE

Interface Module

SLC 500

Fixed I/O Controller with 1747-KE

Interface Module

13–26

SLC Communication Protocols

DF1 Half-Duplex with

Slave-to-Slave Routing

RS-232

(DF1 Half-Duplex

Protocol)

Modem

WINtelligent Linx or RSLinx

(V2.0 or higher)

Running DF1 Half-Duplex

Protocol (Master)

Leased Line

Modem Modem

SLC 5/03 Processor

Modular Controller

SLC 5/03 Processor

Modular Controller

13–27

DF1 Half-Duplex to DH-485

Multi-Drop Link

RS-232

(DF1 Half-Duplex

Protocol)

Modem

WINtelligent Linx or

RSLinx

(V2.0 or higher)

Running DF1 Protocol

(Master)

Modem

1747-KE

Interface Module

1747–AIC

SLC 5/02 Processor

Modular Controller with

1747-KE Interface Module

(Slave)

1747–AIC

SLC 5/01 Processor

Modular Controller

1747–AIC

SLC 500

Fixed I/O Controller

Considerations When Communicating as a DF1 Slave on a Multi–drop Link

When communication is between either your programming software and an SLC processor or between two SLC processors via a slave-to-slave connection on a larger multi-drop link, the devices depend on a DF1 Master to give each of them polling permission to transmit in a timely manner. As the number of slaves increase on the link (up to 254), the time between when your programming software or the SLC processor is polled also increases. This increase in time may become larger if you are using low baud rates.

As these time periods grow, the following values may need to be changed to avoid loss of communication:

• programming software - poll timeout and reply timeout values

SLC processor - poll timeout and edit resource/file owner timeout values. If you are using MSG instructions between SLC processors, the MSG timeout value shown in the control block may also need to be changed for reliable slave-to-slave communication on the multi-drop network.

13–28

SLC Communication Protocols

Using Modems that Support DF1 Communication

Protocols

The types of modems that you can use with SLC processors include dial-up phone modems, leased-line modems, radio modems and line drivers. For point-to-point full-duplex modem connections, use DF1 full-duplex protocol. For point-to-multipoint modem connections, use DF1 half-duplex master and slave protocols. In this case, one (and only one) of the other devices must be configured for DF1 half-duplex master protocol. Do not attempt to use DH-485 protocol

through modems under any circumstance.

Dial-Up Phone Modems

Dial-up phone line modems support point-to-point full-duplex communications.

Normally an SLC processor, on the initiating or receiving end of the dial-up connection, will be configured for DF1 full-duplex protocol with the control line

parameter set for “Full-Duplex Modem”. See page 13–31 for details on the

operation of the RS-232 modem control signals when “Full-Duplex Modem” is selected.

When an SLC processor is the initiator of the dial-up connection, use one of the

ASCII write instructions to send out the “AT” dial-up string (for example: ATDT

555-1212). The status file modem lost bit (S:5/14) provides the feedback that the connnection has been successfully made. To hang up the connection, use the ASCII

AHL instruction to temporarily lower the DTR signal.

Leased-Line Modems

Leased-line modems are used with dedicated phone lines that are typically leased from the local phone company. The dedicated lines may be in a point-to-point topology supporting full-duplex communications between two modems or in a point-to-multipoint topology supporting half-duplex communications between three or more modems. In the point-to-point topology, configure the SLC processor for

DF1 full-duplex protocol with the control line parameter set to “Full-Duplex

Modem”. In the point-to-multipoint topology, configure the SLC processors for

DF1 half-duplex master or slave protocol with the control line parameter set to

“Half-Duplex Modem without Continuous Carrier”. See page 13–31 for details on

the operation of the RS-232 modem control signals when “Half-Duplex Modem without Continuous Carrier” is selected.

13–29

Radio Modems

Radio modems may be implemented in a point-to-point topology supporting either half-duplex or full-duplex communications, or in a point-to-multipoint topology supporting half-duplex communications between three or more modems. In the point-to-point topology using full-duplex radio modems, configure the SLC processors for DF1 full-duplex protocol. In the point-to-point topology using half-duplex radio modems, or point-to-multipoint topology using half-duplex radio modems, configure the SLC processors for DF1 half-duplex master or slave protocol. If these radio modems require RTS/CTS handshaking, configure the control line parameter to “Half-Duplex Modem without Continuous Carrier”.

Line Drivers

Line drivers, also called short-haul “modems”, do not actually modulate the serial data, but rather condition the electrical signals to operate reliably over long transmission distances (up to several miles). Allen-Bradley’s AIC+ Advanced

Interface Converter is a line driver that converts an RS-232 electrical signal into an

RS-485 electrical signal, increasing the signal trasmission distance from 50 to 4000 feet. In a point-to-point line driver topology, configure the SLC processor for DF1 full-duplex protocol. In a point-to-multipoint line driver topology, configure the

SLC processors for DF1 half-duplex slave protocol. If these line drivers require

RTS/CTS handshaking, configure the control line parameter to “Half-Duplex

Modem without Continuous Carrier”.

Modem Control Line Operation in SLC 5/03, SLC 5/04 and SLC 5/05 Processors

The following explains the operation of the SLC 5/03, SLC 5/04, and SLC 5/05 processors when you configure the RS232 channel for the following applications.

DF1 Full–Duplex

When you configure the SLC 5/03, SLC 5/04, and SLC 5/05 processors for full-duplex DF1, the following control line operation takes effect:

13–30

SLC Communication Protocols

No Handshaking Selected — DTR is always active and RTS is always inactive.

Receptions and transmissions take place regardless of the states of DSR, CTS, or

DCD inputs. This selection should only be made when the SLC 5/03, SLC 5/04 and

SLC 5/05 processors are directly connected to another DTE device.

Full-Duplex Modem Selected — DTR and RTS are always active except at the following times. If DSR goes inactive, both DTR and RTS are dropped for 1 to 2 seconds then reactivated. The modem lost bit (S:5/14) is turned on immediately.

While DSR is inactive, the state of DCD is ignored. Neither receptions nor transmissions are performed.

If DCD goes inactive while DSR is active, then receptions are not allowed. If DCD remains inactive for 9 to 10 seconds, then DTR is set inactive until DSR goes inactive. At this point, the modem lost bit is also set. If DSR does not go inactive, then DTR is raised again in 5 to 6 seconds.

Transmission requires all three inputs (CTS, DCD, and DSR) to be active.

Whenever DSR and DCD are both active, the modem lost bit is reset.

DF1 Half-Duplex Slave

When you configure the SLC 5/03, SLC 5/04, and SLC 5/05 processors for DF1 half-duplex slave, the following control line operation takes effect:

No Handshaking Selected — DTR is always active and RTS is always inactive.

Receptions and transmissions take place regardless of the states of DSR, CTS, or

DCD inputs. This selection should only be made when the processor is directly connected to another DTE device.

Half-Duplex Modem with Continuous Carrier Selected DTR is always active and RTS is only activated during transmissions (and any programmed delays before or after transmissions). The handling of DCD and DSR are exactly the same as with

Full-Duplex Modem. Transmissions require CTS and DSR to be active.

Half-Duplex Modem without Continuous Carrier Selected — This is exactly the same as Half-Duplex Modem with Continuous Carrier except monitoring of DCD is not performed. DCD is still required for receptions but is not required for transmissions. Transmissions still require CTS and DSR. The modem lost bit will only be set when DSR is inactive.

13–31

DF1 Half-Duplex Master

When you configure the SLC 5/03, SLC 5/04, and SLC 5/05 processors for DR1 half-duplex master, the following control line operation takes effect:

No Handshaking Selected — DTR is always active and RTS is always inactive.

Receptions and transmissions take place regardless of the states of DSR, CTS, or

DCD inputs. This selection should only be made when the processor is directly connected to another DTE device.

Full-Duplex Modem Selected DTR and RTS are always active except at the following times. If DSR goes inactive, both DTR and RTS are dropped for 1 to 2 seconds then reactivated. The modem lost bit (S:5/14) is turned on immediately.

While DSR is inactive, the state of DCD is ignored. Neither receptions nor transmissions are performed.

If DCD goes inactive while DSR is active, then receptions are not allowed. If DCD remains inactive for 9 to 10 seconds, then DTR is set inactive until DSR goes inactive. At this point, the modem lost bit is also set. If DSR does not go inactive, then DTR is raised again in 5 to 6 seconds.

Transmission requires all three inputs (CTS, DCD, and DSR) to be active.

Whenever DSR and DCD are both active, the modem lost bit is reset.

Half-Duplex Modem without Continuous Carrier Selected — DTR is always active and RTS is only active during transmissions (and any programmed delays before and after transmissions). The processor does not monitor DCD.

If DSR goes inactive, RTS is dropped. The modem lost bit (S:5/14) is turned on immediately. While DSR is inactive, neither receptions nor transmissions are performed.

Transmission requires two inputs, CTS and DSR, to be active. Whenever DSR is active, the modem lost bit is resest.

13–32

SLC Communication Protocols

RTS Send Delay and RTS Off Delay Parameters

Note

Through your programming software, the parameters RTS Send Delay and RTS Off

Delay give you the flexibility of selecting modem control during transmissions.

These parameters only apply when you select half-duplex modem with or without continuous carrier.

For use with half-duplex modems that require extra time to “key up” their transmitter even after they have activated CTS, the RTS Send Delay specifies in 20 millisecond increments the amount of delay time after activating RTS to wait before checking to see if CTS has been activated by the modem. If CTS is not yet active,

RTS remains active and as long as CTS is activated within one second, the transmission occurs. After one second, if CTS is still not activated, then RTS is set inactive and the transmission is aborted.

For modems that do not supply a CTS signal at all, tie RTS to CTS and use the shortest delay possible without losing reliable operation.

If an RTS Send Delay of 0 is selected, then transmission starts as soon as CTS is activated. If CTS does not go active within 1 second after RTS is raised, RTS is set inactive and the transmission is aborted.

Certain modems will drop their carrier link when RTS is lost even though the transmission has not been finished yet. The RTS Off Delay parameter specifies in

20 millisecond increments the delay between when the last serial character is sent to the modem and when RTS is deactivated. This gives the modem extra time to transmit the last character of a packet.

13–33

ASCII Communication Protocol

Note

✓ ✓

The SLC 5/03 (OS301 and higher), SLC 5/04, and SLC 5/05 processors support

✓ user-defined ASCII protocol by configuring RS-232 (channel 0) for the User mode.

In the User mode, all received data is placed in a buffer. To access the data, use the

ASCII instructions in your ladder program. See chapter 11 for more information on

ASCII instructions. You can also send ASCII string data to most attached devices that accept ASCII protocol.

Only ASCII instructions can be used when User mode is configured. If you use a

Message (MSG) instruction that references channel 0, an error occurs.

ASCII Channel 0 Parameter Configuration

When the user mode driver is Generic ASCII for channel 0, the following parameters can be changed:

Parameter

Diagnostic File

Baud Rate

Parity

Stop Bits

Data Bits

Delete Mode

Echo

RTS Off Delay

RTS Send Delay

Control Line

XON/XOFF

Termination 1

Termination 2

Append 1

Append 2

Description

Reserved for future use.

Toggles between the communication rate of 110, 300, 600, 1.2K, 2.4K,

4.8K, 9.6K, and 19.2K (additional rate of 38.4K for SLC 5/05 only). The default is 1.2K for SLC 5/03 and SLC 5/04, and 19.2K for the SLC 5/05.

Toggles between None, Odd, and Even. The default is None.

Toggles between 1, 1.5, and 2. The default is 1.

Toggles between 7 and 8. The default is 8.

Toggles between Ignore, CRT, and printer. The default is Ignore. This parameter is dependent on the Echo parameter being Enabled.

Toggles between Disabled and Enabled. The default is Disabled.

Allows you to select the RTS off delay value in increments of 20 ms. Valid range is 0–65535 (in 20 ms increment). The default is 0.

Allows you to select the RTS send delay value in increments of 20 ms.

Valid range is 0–65535 (in 20 ms increment). The default is 0.

Toggles between No Handshaking, Half-Duplex With Continuous Carrier,

Half-Duplex Without Continuous Carrier, and Full-Duplex Modem. The default is No Handshaking.

Toggles between Disabled and Enabled. The default is Disabled.

Specify FF for no termination character.

Specify FF for no append character.

13–34

SLC Communication Protocols

Using the Passthru Features

There are three types of passthru available in the SLC 5/03 and SLC 5/04 processors. Their operation and associated bits are described below.

DH+ to DH-485 Passthru – (All SLC 5/04 processors)

This type allows the SLC 5/04 to act as a bridge between a DH+ network and a

DH-485 network. When bit S:34/0 is reset, communication packets coming into channel 0 (configured for DH-485) that are not intended for the SLC 5/04 processor are resent out channel 1 onto the DH+ network. Also, communication packets coming into channel 1 (DH+) that are not intended for the SLC 5/04 processor are re-sent out channel 0 onto the DH-485 network. This activity has some effect on the scan time of the SLC 5/04 processor’s ladder program, but the effects are not dramatic because only one passthru packet is re-routed per scan.

DF1 to DH+ Passthru – (SLC 5/04 OS401 and above processors)

This type allows you to connect a computer to the SLC 5/04 processor’s serial port

(channel 0 configured for DF1 Full-Duplex) and access any node on the DH+ network, regardless of the baud rate of the DH+ network. You can also connect a modem to the serial port and dial into any node on the DH+ network. Passthru is enabled when bit S:34/5 is set.

Remote I/O Passthru

(SLC 5/03 OS302, SLC 5/04 OS401, and SLC 5/05 processors)

This type allows the SLC processor system to act as a bridge between its channel 0 and/or channel 1 network(s) and the remote I/O network supported by the 1747-SN

Remote I/O module. This allows personal computers on DH+, DH-485, Ethernet, or

DF1 networks to upload or download applications to devices such as

PanelView 550s, PanelView 900s, and DataLiners on the remote I/O network.

13–35

Considerations when DF1 to DH+ Passthru is Enabled

Keep the following information in mind when you are using DF1 to DH+ Passthru.

Going Online with an SLC 5/04 Processor using DF1 Full-Duplex

If you want to go on-line using DF1 full-duplex, make sure the destination address under the Full-Duplex Online Configuration Screen is set to the DH+ node address channel 1 of the target SLC 5/04 processor. If the destination address is not set and the SLC 5/04 processor has the DF1 to DH+ passthru feature enabled, the command packets from the programming software may go to a different SLC 5/04 processor than the intended SLC 5/04 processor.

Sending a Message using DF1 Full-Duplex to an SLC 5/04 Processor with DF1 to DH+

Passthru Enabled

If the receiving SLC 5/04 processor has passthru enabled, make sure the target node parameter is set to the channel 1 DH+ address of the SLC 5/04 processor.

Sending a Message using DF1 Full-Duplex from an SLC 5/04 Processor with DF1 to DH+

Passthru Enabled

If you use an SLC 5/04 processor with DF1 to DH+ passthru enabled to send messages out of channel 0 (configured for DF1 full-duplex), you must make sure that the SLC 5/04 processor’s DH+ node address appears as the DF1 source address under the Channel 0 System Mode Configuration Screen. If the address is not set correctly, responses coming back to the SLC 5/04 processor may be sent to other nodes on the DH+ network instead.

Communicating from an SLC 5/04 Processor using PLC-2

R

addressing

If you use an SLC 5/04 processor with DF1 to DH+ passthru enabled and are trying to send messages out of channel 0 using the MESSAGE instructions, do not use the

485 CIF message type. Use either the 500CPU or PLC5 message types. If you try to use the 485 CIF message type, the SLC 5/04 processor sending the message will not receive replies from the node it is attempting to communicate with.

13–36

SLC Communication Protocols

Ethernet Communication Protocol

This section:

• describes SLC 5/05 performance considerations

• describes Ethernet network connections and media

• explains how the SLC 5/05 establishes node connections

• lists Ethernet configuration parameters and procedures

• describes configuration for subnet masks and gateways

The SLC 5/05 supports Ethernet communication via the Ethernet communication channel 1. Ethernet is a local area network that provides communication between various devices at 10 Mbps. The physical communication media options for the

SLC 5/05 are:

• built-in

– twisted pair (10Base-T)

• with media converters or hubs

– fiber optic

– broadband

– thick-wire coaxial cable (10Base-5)

– thin-wire coaxial cable (10Base-2)

13–37

SLC 5/05 Performance Considerations

Actual performance of an SLC 5/05 processor varies according to:

• size of Ethernet messages

• frequency of Ethernet messages

• network loading

• the implementation of and performance of your processor application program

Optimal Performance: PC to SLC 5/05 Processor (2-node Ethernet network)

Operation

Single Typed Read

Single Typed Reads

Single Typed Reads

Words

1

20

100

MSG per second

140

138

129

ms per MSG

281

287

312

Words per second

140

2760

12,900

13–38

SLC Communication Protocols

SLC 5/05 and PC Connections to the Ethernet Network

TCP/IP is the mechanism used to transport Ethernet messages. On top of TCP, the

Client/Server Protocol is required to establish sessions and to send the MSG commands. Connections can be initiated by either a client program

(INTERCHANGE or RSLinx application) or a processor. See page 8–23 for

information on how connections are established using the MSG instruction

The SLC 5/05 Ethernet connector conforms to ISO/IEC 8802–3 STD 802.3 and utilizes 10Base-T media. Connections are made directly from the SLC 5/05 to an

Ethernet hub. The network setup is simple and cost effective. Typical network topology is pictured below.

Ethernet

Hub

RJ45 connectors on both ends of cable

(10Base-T)

Important:

to PC Ethernet Card to SLC 5/05

Channel 1

The SLC 5/05 processor contains a 10Base-T, RJ45 Ethernet connector which connects to standard Ethernet hubs via 8-wire twisted pair straight-through cable.

To access other Ethernet mediums, use 10Base-T media converters or Ethernet hubs that can be connected together via fiber, thin-wire, or thick-wire coaxial cables, or any other physical media commercially available with Ethernet hubs.

13–39

Configuring the Ethernet Channel on the SLC 5/05

There are two ways to configure the SLC 5/05 Ethernet channel 1. The configuration can be done via a BOOTP request at processor powerup, or by manually setting the configuration parameters using RSLogix 500 Programming

Software. The configuration parameters are shown below and the configuration procedures follow.

Parameter

Diagnostic File

Number

MSG

Connection

Timeout

MSG Reply

Timeout

Inactivity

Timeout

IP Address

Subnet Mask

Broadcast

Address

Gateway

Address

BOOTP Enable

Description

The file number of the diagnostic counter for this channel. A Diagnostic File

Number value of zero means that no diagnostics file was configured for this channel. The Diagnostic File Number must be an integer within the limits of 7,

9–255.

The amount of time (in ms) allowed for a MSG instruction to establish a connection with the destination node. The MSG Connection Timeout has 250 ms resolution and a range from 250 to 65,500.

The amount of time (in ms) that the SLC 5/05 waits for a reply to a command that it has initiated via a MSG instruction. The MSG Reply Timeout has 250 ms resolution and a range from 250 to 65,500.

The amount of time (in minutes) that a MSG connection may remain inactive before it is terminated. The Inactivity Timeout has a 1 minute resolution and a range from 1 to 65,500 minutes.

The SLC 5/05 internet address (in network byte order). The internet address must be specified to connect to the TCP/IP network.

The SLC 5/05 subnet mask (in network byte order). The Subnet Mask is used to interpret IP addresses when the internet is divided into subnets. A Subnet

Mask of all zeros indicates that no subnet mask has been configured.

N

OT SUPPORTED AT THIS TIME

. The SLC 5/05 broadcast address (in network byte order). The Broadcast Address is used in sending multicast messages. A

Broadcast Address of all zeros indicates that no broadcast address had been configured. In this case, the network code chooses a valid broadcast address when needed for that current subnet.

The address of a gateway (in network byte order) that provides connection to another IP network. A Gateway Address of all zeros indicates that no gateway has been configured.

The BOOTP enable switch. When BOOTP is enabled, the SLC 5/05 attempts to learn its network related parameters at powerup via a BOOTP request. There must be a BOOTP server on the network capable of responding to this BOOTP request. When BOOTP is disabled, the SLC 5/05 uses the locally configured network related parameters (IP Address, Subnet Mask, Broadcast Address, etc.).

Hardware

Address

The SLC 5/05 Ethernet hardware address.

0

15,000 ms

3,000 ms

30 minutes

0

0

0

Default

1 (enabled)

Ethernet hardware address

Status

read/write read/write read/write read/write

0 (undefined) read/write read/write read/write read/write read only

13–40

SLC Communication Protocols

Configuration Using RSLogix500 Programming Software

Refer to the documentation provided with your programming software.

Configuration Via BOOTP

Important:

BOOTP is a standard protocol that TCP/IP nodes use to obtain start-up information.

By default, the SLC 5/05 broadcasts BOOTP requests at powerup. The BOOTP

Valid parameter remains clear until a BOOTP reply has been received. BOOTP lets you dynamically assign IP Addresses to processors on the EthernetLink.

To use BOOTP, a BOOTP Server must exist on the local Ethernet subnet. The server is a computer that has BOOTP Server software installed and reads a text file containing network information for individual nodes on the network.

The BOOTP request can be disabled by clearing the BOOTP Enable parameter in the channel Configuration File. When BOOTP Enable is cleared (disabled), the

SLC 5/05 uses the existing channel configuration data.

If BOOTP is disabled, or no BOOTP server exists on the network, you must use

SLC 500 programming software to enter/change the IP address for each processor.

The host system’s BOOTP configuration file must be updated to service requests from SLC 5/05 processors. The following parameters must be configured:

Parameter

IP Address

Subnet Mask

Gateway

Description

A unique IP Address for the SLC 5/05 processor.

Specifies the net and local subnet mask as per the standard on subnetting

RFC 950, Internet Standard Subnetting Procedure.

Specifies the IP address of a gateway on the same subnet as the SLC 5/05 that provides connections to another IP network.

Note:

If you do not have BOOTP Server capabilities on your network, and you want to dynamically configure Channel 1, contact your local Allen-Bradley representative to obtain a free BOOTP Utility diskette.

13–41

BOOTP Operation at Power-Up

When BOOTP is enabled, the following events occur at power-up:

The processor broadcasts a BOOTP-request message containing its hardware address over the local network or subnet.

The BOOTP server compares the hardware address with the addresses in its look-up table in the BOOTPTAB file.

The BOOTP server sends a message back to the processor with the IP address and other network information that corresponds to the hardware address it received.

With all hardware and IP addresses in one location, you can easily change IP addresses in the BOOTP configuration file if your network needs change.

Using DOS/Windows BOOTP

Important:

The optional BOOTP Server diskette contains DOS-based and Windows-based

BOOTP server utilities. Both provide BOOTP services for SLC 5/05 processors.

Regardless of the platform you are using, you must:

• install the boot-server utility

• edit the boot-server configuration file

• run the boot-server utility

Do not use the BOOTP utility disk if you already have INTERCHANGE software installed. Instead, use the boot-server capabilities that came with your

INTERCHANGE software.

Install the DOS/Windows BOOTP server

To install the DOS BOOTP server:

1.

Put the utility disk that came with your processor in your disk drive.

2.

Change directory to the disk drive.

3.

Type

install

, and press

[Enter]

.

4.

The software is installed in C:\ABIC\BIN. Put this directory in the path statement of your AUTOEXEC.BAT file.

13–42

SLC Communication Protocols

Edit the DOS/Windows BOOTP Configuration File

The boot-server configuration file,

BOOTPTAB

, is located in the

C:\ABIC\BIN directory. This file contains the information needed to boot SLC 5/05 processors.

You must edit the

BOOTPTAB

file, which is an ASCII text file, to include the name,

IP address, and hardware address for each SLC 5/05 processor you want the server to boot. To edit this file:

1.

Open the

BOOTPTAB

file using a text editor.

The file contains lines that look like this:

#Default string for each type of Ethernet client defaults5E: ht=1:vm=rfc1048

These are the default parameters for SLC 5/05 processors and must always precede the client lines in the

BOOTPTAB

file.

The file also contains a line that looks like this: plc5name: tc=defaults5E:ip=aa.bb.cc.dd:ha=0000BC1Dxxyy

Important:

Use this line as the configuration template for SLC 5/05 processors.

2.

Make one copy of the SLC 5/05 processor template for every SLC 5/05 processor in your system.

3.

Edit each copy of the template as follows:

a.

Replace plc5name

with the name of the SLC 5/05 processor. Use only letters and numbers; do not use underscores.

b.

Replace aa.bb.cc.dd

with the IP address to be assigned to the processor.

c.

Replace xxyy

with the last four digits of the hardware address. Use only valid hexadecimal digits (0-9, A-F); do not use the hyphens that separate the numbers. (You will find the hardware address on a label affixed to the printed circuit board of the SLC 5/05 processor.

4.

Save, close, and make a backup copy of this file.

13–43

13–44

BOOTP server

HP 9000

(HP-UNIX) computer)

Example

In this example there are three SLC 5/05 processors and an HP 9000 programming terminal. The names and hardware addresses are device specific:

Device

SLC 5/05

SLC 5/05

SLC 5/05

Name

sigma1 sigma2 sigma3

IP Address

12.34.56.1

12.34.56.2

12.34.56.3

Hardware Address

00–00–BC–1D–12–34

00–00–BC–1D–56–78

00–00–BC–1D–90–12

802.3/Ethernet (TCP/IP)

SLC-5/05 processor sigma1

SLC-5/05 processor sigma2

SLC-5/05 processor sigma3

Based on this configuration, the

BOOTPTAB

file looks like:

#

#

# Legend: gw –– gateways

#

# ha –– hardware address ht –– hardware type

#

# ip –– host IP address sm –– subnet mask vm –– BOOTP vendor extensions format

➁ tc –– template host

#Default string for each type of Ethernet client defaults5E: ht=1:vm=rfc1048

#Entries for SLC 5/05 processors: sigma1: tc=defaults5E:ip=12.34.56.1:ha=0000BC1D1234 sigma2: tc=defaults5E:ip=12.34.56.2:ha=0000BC1D5678 sigma3: tc=defaults5E:ip=12.34.56.3:ha=0000BC1D9012

1 = 10MB Ethernet

Use rfc1048

SLC Communication Protocols

Run the Boot Server Utility

You can run either the DOS-based utility or the Windows-based BOOTP utility, but not both.

If you have BOOTP enabled and the message

BOOTP response not received appears, check the cabling connections and the BOOTP server system.

If you’re using this platform

DOS-based

Windows

then invoke this executable from the

DTLBOOTD.EXE

DOS command line

(specify optional parameters if necessary)

DTLBOOTW.EXE

Windows Program Manager

Both utilities are located in the

C:\ABIC\BIN

directory and use the information contained in the

BOOTPTAB

file.

Be sure to place the

BOOTPTAB

file in the directory from which you are running the

BOOTP utility. If this file is not found in that directory, the utility will try to find the file in the directory specified by the environment variable

ABIC_CONFIG

.

Running the DOS-Based Utility

To run the boot-server utility,

DTLBOOTD.EXE

, follow these steps:

1.

At the DOS prompt, type:

DTLBOOTD [–D] [–T <timeout>] [–B <numboots>] [–F <numfiles>]

[ configfile] [logfile]

Parameter

-D

–T <timeout>

–B <numboots>

–F <numfiles> configfile logfile

Description

provide additional information for debug purposes.

exit after <timeout> seconds of inactivity.

exit after answering <numboots> number of boot requests.

exit after answering <numfiles> number of file requests.

name of the boot server configuration file to use. The default configuration file is

%ABIC_CONFIG%\BOOTPTAB.

name of the log file to use. The default log file is

%ABIC_CONFIG%\DTLBOOTD.LOG

.

13–45

13–46

Once you invoke the utility, it runs until the specified exit parameter is satisfied.

Exit any time by pressing

[Esc]

.

2.

Apply power to all chassis containing SLC 5/05 processors.

At power-up, each SLC 5/05 processor broadcasts a

BOOTP

request if BOOTP was enabled at the channel 1 configuration screen. The Ethernet boot server compares the hardware address with those listed in

BOOTPTAB

and responds by sending the corresponding IP address and other configuration data to the client via a

BOOTP reply.

Running the Windows-Based Utility

To run the boot-server utility,

DTLBOOTW.EXE

, follow these steps:

1.

Start Microsoft Windows

, if it is not already running.

2.

Open the Program Manager window, if it is not already open.

3.

Choose File on the menu bar and select Run from the menu.

4.

In the dialog box, type

C:\ABIC\BIN\DTLBOOTW

; then, choose OK or press

[Enter]

.

Once you invoke the utility, it will run until you terminate it by closing the

DTLBOOTW.EXE window and exiting from Windows.

5.

Apply power to all chassis containing and SLC 5/05 processors.

At power-up, each SLC 5/05 processor broadcasts a

BOOTP

request. The

Ethernet boot server compares the hardware address with those listed in

BOOTPTAB

and responds by sending the corresponding IP address and other configuration data to the client via a

BOOTP

reply.

SLC Communication Protocols

Using Subnet Masks and Gateways

Important:

Configure subnet masks and gateways using the Ethernet channel 1 configuration screen:

If BOOTP is enabled, you can’t change any of the advanced Ethernet communications characteristics.

If your network is divided into subnetworks that use gateways or routers, you must indicate the following information when configuring channel 1:

• subnet mask

• gateway address

A subnet mask is a filter that a node applies to IP addresses to determine if an address is on the local subnet or on another subnet. If an address is located on another subnetwork, messages are routed through a local gateway to be transferred to the destination subnetwork.

If your network is not divided into subnets, then leave the subnet mask field at the default.

If you are

manually configuring channel 1 and have a network with subnets using BOOTP to configure channel 1 and have a network with subnets

Then

• be sure the BOOTP enable field is disabled

• use your programming software to enter the subnet mask and gateway address.

• be sure BOOTP is enabled

• configure the BOOTPTAB file to include the subnet mask(s) and gateway address(es)

See page

13–48

13–49

13–47

Manually Configuring Channel 1 for Processors on Subnets

If you are manually configuring channel 1 for a processor located on a subnet, deselect the “BOOTP Enable” option by clicking on the checked box.

See the table below to configure the subnet mask and gateway address fields for each processor via your programming software.

Ethernet Channel 1 Configuration Screen Advanced Functions

This field:

Gateway

Address

Specifies:

Subnet Mask

The processor’s subnet mask.

The subnet mask is used to interpret IP addresses when the internet is divided into subnets.

The IP address of the gateway that provides a connection to another

IP network.

This field is required when you communicate with other devices not on a local subnet.

Configure by doing the following:

Enter an address of the following form: a.b.c.d

Where: a, b, c, d are between 0-255 (decimal)

If your network is not divided into subnets, then leave the subnet mask field at the default. If you change the default and need to reset it, type 0.0.0.0.

Enter an address of the following form: a.b.c.d

Where: a, b, c, d are between 0-255 (decimal)

The default address is

No Gateway

.

13–48

SLC Communication Protocols

Using BOOTP to Configure Channel 1 for Processors on Subnets

Important:

Configure the BOOTPTAB file according to the subnet mask and gateway address for each SLC 5/05 processor on the link. See the example below and the corresponding BOOTPTAB file on the next page.

Because BOOTP requests are seen only on the local subnet, each subnet needs its own BOOTP server and BOOTPTAB file.

personal computer WINDOWS or HP 9000 or VAX computer

SLC 5/05 processor

BOOTP server

Subnet A

BOOTP server

Ethernet TCP/IP network

130.151.194.1

130.151.194.xxx

Hostname:

IP address:

Subnet Mask:

Iota1

130.151.194.19

255.255.255.0

Gateway Address: 130.151.194.1

Ethernet gateway or “router”

130.151.132.1

130.151.138.1

BOOTP server

Subnet B

130.151.132.xxx

SLC 5/05 processor

130.151.138.xxx

SLC 5/05 processor

Subnet C

Hostname:

IP address:

Subnet Mask:

Gateway

Address:

Iota2

130.151.132.110

255.255.255.0

130.151.132.1

Hostname:

IP address:

Subnet Mask:

Gateway

Address:

Iota3

130.151.138.123

255.255.255.0

130.151.138.1

13–49

13–50

The BOOTPTAB files that correspond to the example looks like:

# Legend: gw –– gateways

#

# ha –– hardware address ht –– hardware type

#

# ip –– host IP address sm –– subnet mask

#

# vm –– BOOTP vendor extensions format tc –– template host

#Default string for each type of Ethernet client defaults5E: ht=1:vm=rfc1048:sm=255.255.255.0

#Entries for SLC 5/05 processors: iota1:\ tc=defaults5E:\ gw=130.151.194.1:\ ha=0000BC1D1234:/ ip=130.151.194.19

# Legend: gw –– gateways

# ha –– hardware address

#

# ht –– hardware type ip –– host IP address

#

#

# sm –– subnet mask vm –– BOOTP vendor extensions format tc –– template host

#Default string for each type of Ethernet client defaults5E: ht=1:vm=rfc1048:sm=255.255.255.0

#Entries for SLC 5/05 processors: iota2:\ tc=defaults5E:\ gw=130.151.132.1:\ ha=0000BC1D5678:/ ip=130.151.132.110

# Legend: gw –– gateways

# ha –– hardware address

#

# ht –– hardware type ip –– host IP address

#

#

# sm –– subnet mask vm –– BOOTP vendor extensions format tc –– template host

#Default string for each type of Ethernet client defaults5E: ht=1:vm=rfc1048:sm=255.255.255.0

#Entries for SLC 5/05 processors: iota3:\ tc=defaults5E:\ gw=130.151.138.1:\ ha=0000BC1D9012:/ ip=130.151.138.123

MicroLogix Communication Protocols

14

MicroLogix Communication

Protocols

Use the information in this chapter to understand the differences in communication protocols. The following protocols are supported:

DF1 Full-Duplex and DF1 Half-Duplex Slave

All MicroLogix 1000 controllers support the DF1 protocol from the RS-232 connector.

DH-485

Series C or later MicroLogix 1000 controllers can communicate on DH-485 networks using an AIC+ Advanced Interface Converter.

This chapter starts out with information on automatic protocol switching. This feature allows you easily switch between DF1 and DH-485 protocols. For information about required network connecting equipment, refer to the MicroLogix

1000 Programmable Controllers User Manual, publication 1761-6.3.

14–1

Automatic Protocol Switching

The Series D and MicroLogix 1000 analog controllers perform automatic protocol switching between DH-485 and the configured DF1 protocol. (The controller cannot automatically switch between DF1 full-duplex and DF1 half-duplex slave.)

This feature allows you to switch from active communication on a DF1 half-duplex network to the DH-485 protocol to make program changes.

If the controller is configured for DF1 half-duplex slave and you’d like to switch to

DH-485 protocol to edit your program, simply disconnect the MicroLogix controller from the half-duplex modem and connect it to your personal computer. The controller recognizes the computer is attempting to communicate using the DH-485 protocol and automatically switches to it. When your program changes are complete, you can disconnect your computer, reconnect the modem, and the controller automatically switches back to DF1 half-duplex slave protocol.

The following baud rate limitations affect autoswitching:

If the configured DH-485 baud rate is 19200, the configured DF1 baud rate must be 4800 or greater.

If the configured DH-485 baud rate is 9600, the configured DF1 baud rate must be 2400 or greater.

RS-232 Communication Interface

RS-232 is an Electronics Industries Association (EIA) standard that specifies the electrical, mechanical, and functional characteristics for serial binary communication. It provides you with a variety of system configuration possibilities.

(RS-232 is a definition of electrical characteristics; it is not a protocol.)

One of the biggest benefits of the RS-232 interface is that it lets you integrate telephone and radio modems into your control system. The distance over which you are able to communicate with certain system devices is virtually limitless.

14–2

MicroLogix Communication Protocols

DF1 Full-Duplex Protocol

Note

DF1 Full-Duplex communication protocol (also referred to as DF1 point-to-point protocol) combines data transparency (ANSI — American National Standards

Institute — specification subcategory D1) and 2-way simultaneous transmission with embedded responses (subcategory F1).

The MicroLogix 1000 controllers support the DF1 Full-Duplex protocol via RS-232 connection to external devices, such as computers, the Hand-Held Programmer

(catalog number 1761-HHP-B30), or other MicroLogix 1000 controllers. (For information on connecting to the Hand-Held Programmer, see its user manual, publication 1761-6.2.)

You can connect to a DeviceNet network using the DeviceNet Interface (DNI), catalog number 1761-NET-DNI. The DNI provides a single DeviceNet connection point and a single RS-232 connection. The DNI is a DeviceNet to DF1 protocol conversion device that allows DF1 devices to communicate on DeviceNet.

For additional information on using the DNI, see the DeviceNet Interface (DNI)

Overview, publication 1761-1.23, or the DeviceNet Interface (DNI) User Manual, publication 1761-6.5.

DF1 Full-Duplex Operation

DF1 Full-Duplex protocol (also referred to as DF1 point-to-point protocol) is useful where RS-232 point-to-point communication is required. This type of protocol supports simultaneous transmissions between two devices in both directions. DF1 protocol controls message flow, detects and signals errors, and retries if errors are detected.

DF1 Full-Duplex Channel 0 Configuration Parameters

When the system mode driver is a DF1 Full-Duplex for channel 0 the following parameters can be changed:

14–3

14–4

Parameter

Diagnostic File

Baud Rate

Description

Reserved for future use.

Toggles between the communication rate of 110, 300, 600, 1200, 2400, 4800, 9600, and 19.2K. (additional rate of 38.4K for SLC 5/05 only). The default is 1200 for

SLC 5/05 and SLC 5/04, and 19.2K for the SLC 5/05.

Parity

Stop Bits

Toggle between None and Even. The default is None.

Toggles between 1, 1.5, and 2. The default is 1.

Duplicate Packet Detection Toggles between Disabled and Enabled. The default is Enabled.

Error Detection Toggles between CRC and BCC. The default is CRC.

ACK Timeout

NAK Retries

ENQ Retries

Control Line

Embedded Responses

Source ID

Valid range is 2–65535 (in 20 ms increment) The default is 50.

Valid range is 0–255. The default is 3.

Valid range is 0–255. The default is 3.

Toggles between No Handshaking and Full-Duplex modem. The default is No

Handshaking.

Toggles between Enabled and Auto-Detect. The default is Enabled.

Specify the address of the sender in this field. Valid range is 0–254. The default is 9.

MicroLogix Communication Protocols

Example DF1 Full-Duplex Connections

For information about required network connecting equipment, refer to the

MicroLogix 1000 Programmable Controllers User Manual, publication 1761-6.3.

Personal Computer

Optical Isolator

(recommended)

1761-CBL-PM02

Micro Controller

Personal Computer

Modem

Cable

Modem

Modem

Optical Isolator

(recommended)

1761-CBL-PM02

Micro Controller

We recommend using an AIC+, catalog number 1761-NET-AIC, as your optical isolator.

14–5

DF1 Half-Duplex Slave Protocol

DF1 half-duplex slave protocol provides a multi-drop single master/multiple slave network. In contrast to DF1 full-duplex, communication takes place in one direction at a time. You can use the RS-232 port on the MicroLogix as both a half-duplex programming port, as well as a half-duplex peer-to-peer messaging port.

The master device initiates all communication by “polling” each slave device. The slave device may only transmit message packets when it is polled by the master. It is the master’s responsibility to poll each slave on a regular and sequential basis to allow slaves to send message packets back to the master. During a polling sequence, the master polls a slave either repeatedly until the slave indicates that it has no more message packets to transmit or just one time per polling sequence, depending on how the master is configured.

An additional feature of the DF1 half-duplex protocol is that it is possible for a slave device to enable a MSG instruction in its ladder program to send or request data to/from another slave. When the initiating slave is polled, the MSG instruction command packet is sent to the master. The master recognizes that the command packet is not intended for it but for another slave, so the master immediately rebroadcasts the command packet to the intended slave. When the intended slave is polled, it sends a reply packet to the master with the data the first slave requested.

The master again recognizes that the reply packet is intended for another slave, so the master immediately rebroadcasts the reply packet to that slave. This slave-to-slave transfer is a function of the master device and is also used by programming software to upload and download programs to processors on the DF1 half-duplex link.

Several Allen-Bradley products support half-duplex master protocol. They include the SLC 5/03 t

and 5/04 t

, 1771-KGM module (for PLC-2

®

controllers) and enhanced PLC-5

®

processors. Rockwell Software WINtelligent LINX t

also supports DF1 half-duplex master protocol.

Typically, the master maintains an active node table that indicates which slaves are active (slaves that responded the last time they were polled) and which slaves are inactive (slaves that did not respond the last time they were polled). The active slaves are polled on a regular basis. The inactive slaves are only polled occasionally to check if any have come back online.

DF1 half-duplex supports up to 255 devices (address 0 to 254) with address 255 reserved for master broadcasts. The MicroLogix supports broadcast reception but cannot initiate a broadcast command. The MicroLogix supports half-duplex modems using Request-To-Send/Clear-To-Send (RTS/CTS) hardware handshaking.

14–6

MicroLogix Communication Protocols

DF1 Half-Duplex Slave Configuration Parameters

When the system mode driver is DF1 half-duplex slave the following parameters can be viewed and changed only when the programming software is online with the processor. The DF1 half-duplex slave parameters are not stored as part of the controller downloadable image (with the exception of the baud rate and node

address). If a failed MicroLogix 1000 controller is replaced and the backed-up controller image is downloaded to the replacement controller, these parameters will remain at default until manually changed. Therefore, be sure to fully document any non-default settings to the DF1 half-duplex slave configuration parameters.

Parameter

Baud Rate

Description

Toggles between the communication rate of 300, 600, 1200, 2400, 4800, 9600, 19.2K (additional rate of 38.4K for SLC 5/05 only). The default is 1200 for SLC 5/03 and SLC 5/04, and 19.2K for the SLC 5/05.

Node Address Valid range is 0–254 decimal.

Control Line Toggles between No Handshaking and Half-Duplex Modem.

Default

9600

1

No Handshaking

Duplicate

Packet

Detection

Error

Detection

Detects and eliminates duplicate responses to a message. Duplicate packets may be sent under

“noisy” communication conditions when the sender’s retries are not set to 0. Toggles between

Enabled and Disabled.

Toggles between CRC and BCC.

RTS Off Delay

RTS Send

Delay

Poll Timeout

Pre-send Time

Delay

Message

Retries

EOT

Suppression

Specifies the delay time between when the last serial character is sent to the modem and when

RTS will be deactivated. Gives modem extra time to transmit the last character of a packet. The valid range is 0–255 and can be set in increments of 5 ms.

Specifies the time delay between setting RTS (request to send) until checking for the CTS (clear to send) response. For use with modems that are not ready to respond with CTS immediately upon receipt of RTS. The valid range is 0–255 and can be set in increments of 5 ms.

Poll Timeout only applies when a slave device initiates a MSG instruction. It is the amount of time that the slave device waits for a poll from the master device. If the slave device does not receive a poll within the Poll Timeout, a MSG instruction error is generated, and the ladder program needs to requeue the MSG instruction. The valid range is 0–65535 and can be set in increments of 20 ms. If you are using a MSG instruction, it is recommended that a Poll Timeout value of zero not be used. Poll Timeout is disabled if set to zero.

Delay time before transmission. Required for 1761-NET-AIC physical half-duplex networks. The

1761-NET-AIC needs delay time to change from transmit to receive mode. The valid range is

0–255 and can be set in increments of 5 ms.

Specifies the number of times a slave device attempts to resend a message packet when it does not receive an ACK from the master device. For use in noisy environments where message packets may become corrupted in transmission. The valid range is 0–255.

Slave does not respond when polled if no message is queued. Saves modem transmission power when there is no message to transmit. Toggles between Yes and No.

Enabled

CRC

0

0

3000 (60s)

0

3

No

14–7

Modem

RS-232

(DF1 Protocol)

Modem

Rockwell Software WINtelligent LINX, RSLinx 2.0 (or higher),

SLC 5/03, SLC 5/04 and SLC 5/05, or PLC-5 processors configured for DF1 Half-Duplex Master

Modem Modem

Modem

Modem

MicroLogix 1000

Programmable

Controller (Series D)

SLC 5/03 Processor

Modular Controller

MicroLogix 1000

Programmable

Controller (Series D)

MicroLogix 1000

Programmable

Controller (Series D)

SLC 500 t

Fixed I/O Controller with 1747-KE

Interface Module

Considerations When Communicating as a DF1 Slave on a Multi-drop Link

When communication is between either your programming software and a

MicroLogix 1000 Programmable Controller or between two MicroLogix

Programmable Controllers via a slave-to-slave connection on a larger multi-drop link, the devices depend on a DF1 Master to give each of them polling permission to transmit in a timely manner. As the number of slaves increases on the link (up to

254), the time between when your programming software or the MicroLogix

Controller is polled also increases. This increase in time may become larger if you are using low baud rates.

As these time periods grow, the following values may need to be changed to avoid loss of communication:

• programming software - increase poll timeout and reply timeout values

MicroLogix Programmable Controller - increase poll timeout

14–8

MicroLogix Communication Protocols

Ownership Timeout

When a program download sequence is started by a software package to download a ladder logic program to a MicroLogix controller, the software takes “file ownership” of the processor. File ownership prevents other devices from reading from or writing to the processor while the download is in process. If the controller were to respond to a device’s read commands during the download, the processor could respond with incorrect information. Similarly, if the controller were to accept information from other devices, the information could be lost because the program download sequence could immediately overwrite the information. Once the download is completed, the programming software returns the file ownership to the controller, so other devices can communicate with it again.

With the addition of DF1 half-duplex slave protocol, the controller clears the file ownership if no supported commands are received from the owner within the timeout period. If the file ownership were not cleared after a download sequence interruption, the processor would not accept commands from any other devices because it would assume another device still had file ownership.

If a download sequence is interrupted, due to noise caused by electromagnetic interference, discontinue communications to the controller for the ownership

timeout period and restart the program download. The ownership timeout period is set to 60 seconds as a default for all protocols. However, if you are using DF1 half-duplex, and the poll timeout value is set to greater than 60 seconds, the poll

timeout value will be used instead of the ownership timeout. After the timeout, you can re-establish communications with the processor and try the program download again. The only other way to clear file ownership is to cycle power on the processor.

14–9

Using Modems that Support DF1 Communication Protocols

Note

The types of modems that you can use with MicroLogix 1000 controllers include dial-up phone modems, leased-line modems, radio modems and line drivers. For point-to-point full-duplex modem connections that do not require any modem handshaking signals to operate, use DF1 full-duplex protocol. For point-to-multipoint modem connections, or for point-to-point modem connections that require Request-to-Send/Clear-To-Send (RTS/CTS) handshaking, use DF1 half-duplex slave protocol. In this case, one (and only one) of the other devices must be configured for DF1 half-duplex master protocol. Do not attempt to use

DH-485 protocol through modems under any circumstance.

Only Series D or later MicroLogix 1000 discrete controllers and all MicroLogix

1000 analog controllers support RTS/CTS modem handshaking and only when configured for DF1 half-duplex slave protocol with the control line parameter set to

“Half-Duplex Modem”. No other modem handshaking lines (i.e. Data Set Ready,

Carrier Detect and Data Terminal Ready) are supported by any MicroLogix 1000 controllers.

Dial-Up Phone Modems

Dial-up phone line modems support point-to-point full-duplex communications.

Normally a MicroLogix 1000 controller, on the receiving end of the dial-up connection, will be configured for DF1 full-duplex protocol. The modem connected to the MicroLogix 1000 controller must support auto-answer and must not require any modem handshaking signals from the MicroLogix 1000 (i.e., DTR or RTS) in order to operate. The MicroLogix 1000 has no means to cause its modem to initiate or disconnect a phone call, so this must be done from the site of the remote modem.

Leased-Line Modems

Leased-line modems are used with dedicated phone lines that are typically leased from the local phone company. The dedicated lines may be in a point-to-point topology supporting full-duplex communications between two modems or in a point-to-multipoint topology supporting half-duplex communications between three or more modems. In the point-to-point topology, configure the MicroLogix 1000 controllers for DF1 full-duplex protocol (as long as the modems used do not require

DTR or RTS to be high in order to operate). In the point-to-multipoint topology, configure the MicroLogix 1000 controllers for DF1 half-duplex slave protocol with the control line parameter set to “Half-Duplex Modem”.

14–10

MicroLogix Communication Protocols

Radio Modems

Radio modems may be implemented in a point-to-point topology supporting either half-duplex or full-duplex communications, or in a point-to-multipoint topology supporting half-duplex communications between three or more modems. In the point-to-point topology using full-duplex radio modems, configure the MicroLogix

1000 controllers for DF1 full-duplex protocol (as long as the modems used do not require DTR or RTS to be high in order to operate). In the point-to-point topology using half-duplex radio modems, or point-to-multipoint topology using half-duplex radio modems, configure the MicroLogix 1000 controllers for DF1 half-duplex slave protocol. If these radio modems require RTS/CTS handshaking, configure the control line parameter to “Half-Duplex Modem”.

Line Drivers

Line drivers, also called short-haul “modems”, do not actually modulate the serial data, but rather condition the electrical signals to operate reliably over long transmission distances (up to several miles). Allen-Bradley’s AIC+ Advanced

Interface Converter is a line driver that converts an RS-232 electrical signal into an

RS-485 electrical signal, increasing the signal trasmission distance from 50 to 4000 feet. In a point-to-point line driver topology, configure the MicroLogix 1000 controller for DF1 full-duplex protocol (as long as the line drivers do not require

DTR or RTS to be high in order to operate). In a point-to-multipoint line driver topology, configure the MicroLgoix 1000 controllers for DF1 half-duplex slave protocol. If these line drivers require RTS/CTS handshaking, configure the control line parameter to “Half-Duplex Modem”.

DH-485 Communication Protocol

Note

The information in this section describes the DH-485 network functions, network architecture, and performance characteristics. It will also help you plan and operate the MicroLogix 1000 in a DH-485 network.

Only Series C or later MicroLogix 1000 controllers support the DH-485 network.

14–11

DH-485 Network Description

The DH-485 protocol defines the communication between multiple devices that co-exist on a single pair of wires. This protocol uses RS-485 half-duplex as its physical interface. (RS-485 is a definition of electrical characteristics; it is not a protocol.) RS-485 uses devices that are capable of co-existing on a common data circuit, thus allowing data to be easily shared between devices.

The DH-485 network offers:

• interconnection of 32 devices

• multi-master capability

• token passing access control

• the ability to add or remove nodes without disrupting the network

• maximum network length of 1219 m (4000 ft)

The DH-485 protocol supports two classes of devices: initiators and responders.

All initiators on the network get a chance to initiate message transfers. To determine which initiator has the right to transmit, a token passing algorithm is used.

The following section describes the protocol used to control message transfers on the DH-485 network.

DH-485 Token Rotation

A node holding the token can send any valid packet onto the network. Each node is allowed only one transmission (plus two retries) each time it receives the token.

After a node sends one message packet, it attempts to give the token to its successor by sending a “token pass” packet to its successor.

If no network activity occurs, the initiator sends the token pass packet again. After two retries (a total of three tries) the initiator will attempt to find a new successor.

The allowable range of the node address of an initiator is 0 to 31. The allowable address range for all responders is 1 to 31. There must be at least one initiator on the network.

14–12

MicroLogix Communication Protocols

DH-485 Configuration Parameters

When the system mode driver for channel 0 or channel 1 is DH-485 Master, the following parameters can be changed:

Parameter

Diagnostic File

Baud Rate

Node Address

Max Node Address

Token Hold Factor

Description

Reserved for future use.

Toggles between the communication rate of 110, 300, 600, 1200, 2400,

9600, and 19.2K. The default is 19.2K.

This is the node address of the processor on the DH-485 network. The valid range is 1–31. The default is 1.

This is the maximum node address of an active processor. The valid range is 1–31. The default is 31.

Determines the number of transactions allowed to make each DH-485 token rotation. Increasing this value allows your processor to increase its DH-485 throughput. This also decreases throughput to other processors on the

DH-485 link. The valid range is 1–4. The default is 1. The SLC 5/01 and

SLC 5/02 processors are factory set to 1.

DH-485 Network Initialization

Network initialization begins when a period of inactivity exceeding the time of a link dead timeout is detected by an initiator on the network. When the time for a link dead timeout is exceeded, usually the initiator with the lowest address claims the token. When an initiator has the token it will begin to build the network. The network requires at least one initiator to initialize it.

Building a network begins when the initiator that claimed the token tries to pass the token to the successor node. If the attempt to pass the token fails, or if the initiator has no established successor (for example, when it powers up), it begins a linear search for a successor starting with the node above it in the addressing.

When the initiator finds another active initiator, it passes the token to that node, which repeats the process until the token is passed all the way around the network to the first node. At this point, the network is in a state of normal operation.

14–13

Devices that use the DH-485 Network

Note

In addition to the Series C or later MicroLogix 1000 controllers, the devices shown in the following table also support the DH-485 network.

You cannot connect the Hand-Held Programmer, 1761-HHP-B30, to the AIC+.

Catalog Number

1747-L511, -L514, -L524,

-L531, -L532 -L541, -L542,

-L543, -L551, -L552, -L553

Description

Installation

Requirement

SLC 500

Processors

SLC Chassis

Function

These processors support a variety of I/O requirements and functionality.

Publication

1747-6.2

1746-BAS

1785-KA5

2760-RB

BASIC Module

DH

+ t

5 Gateway

Flexible

Interface

Module

/DH-48

SLC Chassis

(1771) PLC

Chassis

(1771) PLC

Chassis

1784-KTX, -KTXD

1784-PCMK

1747-PT1

PC DH-485 IM

PCMCIA IM

IBM XT/AT

Computer Bus

PC and

Interchange

Hand-Held

Terminal

NA

1747-DTAM, 2707-L8P1, -L8P2,

-L40P1, -L40P2, -V40P1, -V40P2,

-V40P2N, -M232P3, -M485P3

2711-K5A2, -B5A2, -K5A5, -B5A5,

-K5A1, -B5A1, -K9A2, -T9A2,

-K9A5, -T9A5, -K9A1, -T9A1

DTAM,

DTAM Plus,

DTAM Micro

PanelView 550 and 900

NA = Not Applicable

Panel Mount

Panel Mount

Provides an interface for SLC 500 devices to foreign devices. Program in BASIC to interface the

3 channels (2 RS232 and 1 DH-485) to printers, modems, or the DH-485 network for data collection.

Provides communication between stations on the

PLC-5 r

(DH

+

) and SLC 500 (DH-485) networks.

Enables communication and data transfer from

PLC r

to SLC 500 on DH-485 network. Also enables programming software programming or data acquisition across DH+ to DH-485.

Provides an interface for SLC 500 (using protocol cartridge 2760-SFC3) to other A-B PLCs and devices. Three configurable channels are available to interface with Bar Code, Vision, RF, Dataliner t

, and PLC systems.

1746-6.1

1746-6.2

1746-6.3

1785-6.5.5

1785-1.21

2760-ND001

Provides DH-485 using RSLinx 1784-6.5.22

Provides DH-485 using RSLinx

1784-6.5.19

Provides hand-held programming, monitoring, configuring, and troubleshooting capabilities for

SLC 500 processors.

Provides electronic operator interface for SLC 500 processors.

Provides electronic operator interface for SLC 500 processors.

1747-NP002

1747-ND013

2707-800,

2707-803

2711-802,

2711-816

14–14

MicroLogix Communication Protocols

Important DH-485 Network Planning Considerations

Carefully plan your network configuration before installing any hardware. Listed below are some of the factors that can affect system performance:

• amount of electrical noise, temperature, and humidity in the network environment

• number of devices on the network

• connection and grounding quality in installation

• amount of communication traffic on the network

• type of process being controlled

• network configuration

The major hardware and software issues you need to resolve before installing a network are discussed in the following sections.

Hardware Considerations

You need to decide the length of the communication cable, where you route it, and how to protect it from the environment where it will be installed.

When the communication cable is installed, you need to know how many devices are to be connected during installation and how many devices will be added in the future. The following sections will help you understand and plan the network.

Number of Devices and Length of Communication Cable

You must install an AIC+ Advanced Interface Converter, catalog number

1761-NET-AIC, for each node on the network. If you plan to add nodes later, provide additional advanced interface converters during the initial installation to avoid recabling after the network is in operation.

The maximum length of the communication cable is 1219 m (4000 ft). This is the total cable distance from the first node to the last node on the network.

14–15

14–16

Planning Cable Routes

Follow these guidelines to help protect the communication cable from electrical interference:

Keep the communication cable at least 1.52 m (5 ft) from any electric motors, transformers, rectifiers, generators, arc welders, induction furnaces, or sources of microwave radiation.

If you must run the cable across power feed lines, run the cable at right angles to the lines.

If you do not run the cable through a contiguous metallic wireway or conduit, keep the communication cable at least 0.15 m (6 in.) from ac power lines of less than 20A, 0.30 m (1 ft) from lines greater than 20A, but only up to 100k VA, and 0.60 m (2 ft) from lines of 100k VA or more.

If you run the cable through a contiguous metallic wireway or conduit, keep the communication cable at least 0.08 m (3 in.) from ac power lines of less than

20A, 0.15 m (6 in.) from lines greater than 20A, but only up to 100k VA, and

0.30 m (1 ft) from lines of 100k VA or more.

Running the communication cable through conduit provides extra protection from physical damage and electrical interference. If you route the cable through conduit, follow these additional recommendations:

Use ferromagnetic conduit near critical sources of electrical interference. You can use aluminum conduit in non-critical areas.

Use plastic connectors to couple between aluminum and ferromagnetic conduit. Make an electrical connection around the plastic connector

(use pipe clamps and the heavy gauge wire or wire braid) to hold both sections at the same potential.

Ground the entire length of conduit by attaching it to the building earth ground.

Do not let the conduit touch the plug on the cable.

Arrange the cables loosely within the conduit. The conduit should contain only serial communication cables.

Install the conduit so that it meets all applicable codes and environmental specifications.

For more information on planning cable routes, see Industrial Automation Wiring

and Grounding Guidelines, Publication Number 1770-4.1.

MicroLogix Communication Protocols

Software Considerations

Software considerations include the configuration of the network and the parameters that can be set to the specific requirements of the network. The following are major configuration factors that have a significant effect on network performance:

• number of nodes on the network

• addresses of those nodes

• baud rate

The following sections explain network considerations and describe ways to select parameters for optimum network performance (speed). See your programming software’s user manual for more information.

Number of Nodes

The number of nodes on the network directly affects the data transfer time between nodes. Unnecessary nodes (such as a second programming terminal that is not being used) slow the data transfer rate. The maximum number of nodes on the network is 32.

Setting Node Addresses

The best network performance occurs when node addresses are assigned in sequential order. Initiators, such as personal computers, should be assigned the lowest numbered addresses to minimize the time required to initialize the network.

The valid range for the MicroLogix 1000 controllers is 1–31 (controllers cannot be node 0). The default setting is 1. The node address is stored in the controller status file (S:16L).

If some nodes are connected on a temporary basis, do not assign addresses to them.

Simply create nodes as needed and delete them when they are no longer required.

Setting Controller Baud Rate

The best network performance occurs at the highest baud rate, which is 19.2K. This is the default baud rate for a MicroLogix 1000 devices on the DH-484 network. All devices must be at the same baud rate. This rate is stored in the controller status file

(S:16H).

14–17

Example DH-485 Connections

The following network diagrams provide examples of how to connect Series C or later MicroLogix 1000 controllers to the DH-485 network using the AIC+.

DH-485 Network with a MicroLogix 1000 Controller

MicroLogix 1000 (Series C or later)

PC

APS

connection from port 1 or port 2 to MicroLogix

1761-CBL-AM00 or

AIC+

(1761-NET-AIC)

1761-CBL-

HM02

24V dc

(user supply needed if not connected to a MicroLogix 1000 controller)

MicroLogix DH-485 Network

1761-CBL-AP00 or

1761-CBL-PM02

AIC+

(1761-NET-AIC)

1761-CBL-AP00 or

1761-CBL-PM02

24V dc

(user supplied)

PC to port 1 or port 2

1747-CP3 or

1761-CBL-AC00

Typical 3-Node Network

DB-9 RS-232 port mini-DIN 8 RS-232 port

DH-485/DF1 port

RJ45 port

1761-CBL-AS09 or

1761-CBL-AS03

3-Node Network

(not expandable)

PanelView t

550

AIC+

(1761-NET-AIC)

1761-CBL-AM00 or

1761-CBL-

HM02

PC

MicroLogix 1000

(Series C or later)

APS

Selection Switch Up

24V dc

(Not needed in this configuration since the

MicroLogix 1000 provides power to the AIC+ via port 2.)

1747-CP3 or 1761-CBL-AC00

14–18

Networked Operator Interface Device and MicroLogix Controller

PanelView 550

MicroLogix Communication Protocols

PC

APS

RS-232 port

NULL modem adapter

PC to port 1 or port 2

1761-CBL-AP00 or

1761-CBL-PM02

AIC+

(1761-NET-AIC)

connection from NULL modem adapter to port 1 or port 2

1747-CP3 or

1761-CBL-AC00

AIC+

(1761-NET-AIC)

1761-CBL-AP00 or

1761-CBL-PM02

24V dc

(user supplied)

1747-CP3 or

1761-CBL-AC00

24V dc

(user supplied)

DH-485 Network

1747-AIC

AIC+

(1761-NET-AIC)

Selection

Switch Up

24V dc

(Not needed in this configuration since the

MicroLogix 1000 provides power to the

AIC+ via port 2.)

1761-CBL-AM00 or

1761-CBL-HM02

MicroLogix 1000

(Series C or later)

SLC 5/03 processor

DB-9 RS-232 port mini-DIN 8 RS-232 port

DH-485/DF1 port

14–19

MicroLogix Remote Packet Support

Series D MicroLogix can respond to communication packets (or commands) that do not originate on the local DH-485 network. This is useful in installations that utilize different Allen-Bradley communication networks, such as DH+ and DH-485.

The example below shows how to send messages from a PLC device or a PC on the

DH+ network to a MicroLogix 1000 controller on the DH-485 network. This method uses an SLC 5/04 processor bridge connection.

When using this method:

PLC-5 devices can send read and write commands to MicroLogix controllers.

MicroLogix 1000 controllers can respond to MSG instructions received. The

MicroLogix controllers cannot initiate MSG instructions to devices on the DH+ network.

PC can send read and write commands to MicroLogix controllers.

PC can do remote programming of MicroLogix controllers.

PLC-5

DH

+

Network

14–20

SLC 5/03 System

SLC 5/04

Modular I/O Controller

MicroLogix 1000

Programmable

Controller

MicroLogix 1000

Programmable

Controller

DH-485 Network

MicroLogix 1000

Programmable

Controller

PLC-5

Troubleshooting Faults

15

Troubleshooting Faults

This chapter lists the major error fault codes, indicates the probable causes of faults, and recommends corrective action. This chapter also explains the operating system download faults for the SLC 5/03 (and higher) processors and MicroLogix 1000 controllers.

Automatically Clearing Faults

The following section describes the different ways to automatically clear a fault using your programming software.

SLC Processors

Set the Fault Override at Powerup Bit S:1/8 in the status file to clear the fault when power is cycled, assuming the user program is not corrupt.

Set one of the autoload bits S:1/10, S:1/11, or S:1/12 in the status file of the program in an EEPROM to automatically transfer a new non-faulted program from the memory module to RAM when power is cycled.

Note

Refer to appendix B in this manual for more information on status bits S:1/13, S:1/8,

S:1/10, S:1/11, S:1/12, S:5/0–7, and S:36/0–7.

You can declare your own application-specific major fault by writing your own unique value to S:6 and then setting bit S:1/13.

15–1

MicroLogix 1000 Controllers

You can automatically clear a fault when cycling power to the controller by setting either one or both of the following status bits in the status file:

Fault Override at Powerup bit (S:1/8)

Run Always bit (S:1/12)

Note

Clearing a fault using the Run Always bit (S:1/12) causes the controller to immediately enter the REM Run mode. Make sure you fully understand the

use of this bit before incorporating it into your program. Refer to page A–6

for more information. Also refer to chapter 1 for information pertaining to

retentive data.

You can declare your own application-specific major fault by writing your own unique value to S:6 and then setting bit S:1/13 to prevent reusing system defined

codes. The recommended values for user defined faults is FF00 to FF0F.

Manually Clearing Faults (SLC Processors)

The following section describes the different ways to manually clear a fault when using an SLC processor.

Manually clear the major fault bit S:1/13, and the minor and major error bits

S:5/0–7 in the status file, using a programming device or a Data Table Access

Module. Place the processor in the REM Program mode. Correct the condition causing the fault, then return the processor to either REM Run or any of the

REM Test modes.

SLC 5/03 and higher processors – Toggle the keyswitch from RUN to

PROGram and then back to RUN.

SLC 5/03 and higher processors – Clearing these bits with the keyswitch in the

RUN position causes the processor to immediately enter the Run mode.

If you are online with a SLC 5/03 (or higher) processor with the keyswitch position is in RUN and you press the clear major fault function key, you are warned that the processor will enter the Run mode once you clear the fault.

15–2

Troubleshooting Faults

Using the Fault Routine

SLC Processors

When designating a subroutine file, the occurrence of recoverable or non-recoverable user faults causes the designated subroutine to be executed for one scan. If the fault is recoverable, the subroutine can be used to correct the problem and clear the fault bit S:1/13. The processor then continues in the run mode. If the fault is non-recoverable, the subroutine can send a message via the Message instruction to another node with error code information and/or does an orderly shutdown of the process.

The subroutine does not execute for non-user faults. The user fault routine is

discussed in chapter 12.

MicoLogix 1000 Controllers

The occurrence of recoverable or non-recoverable user faults causes file 3 to be executed. If the fault is recoverable, the subroutine can be used to correct the problem and clear the fault bit S:1/13. The controller then continues in the REM

Run mode. The subroutine does not execute for non-user faults.

Fault Messages

This section contains fault messages that can occur during operation for the

MicroLogix 1000 controllers and the SLC processors. Each table lists the error code description, the probable cause, and the recommended corrective action.

MicroLogix 1000 Controller Faults

The controller faults are divided into the following types:

• powerup errors

• going-to-run errors

• run errors

• download errors

15–3

Powerup Errors

Error Code

(Hex)

0001

0002

0003

0005

Advisory Message

DEFAULT PROGRAM

LOADED

UNEXPECTED RESET

EEPROM MEMORY IS

CORRUPT

RETENTIVE DATA HAS BEEN

LOST

Description

The default program is loaded to the controller memory. This occurs:

• on power-up if the power down occurred in the middle of a download

• if the user program is corrupt at power-up, the default program is loaded.

The controller was unexpectedly reset due to a noisy environment or internal hardware failure. If the user program downloaded to the controller is valid, the initial data downloaded with the program is used. The Retentive Data Lost Bit

(S:5/8) is set. If the user program is invalid, the default program is loaded.

The user program is corrupt and the default program is loaded.

The data files (input, output, timer, counter, integer, binary, control, and status) are corrupt.

Recommended Action

Re–download the program and enter the REM Run mode.

Contact your local Allen–Bradley representative if the error persists.

Refer to proper grounding guidelines in the

MicroLogix 1000 Programmable

Controllers User Manual, publication 1761-6.3.

Contact your local Allen–Bradley representative if the error persists.

While power cycling to your controller, a noise problem may have occurred. Try cycling power again. Your program may be valid, but retentive data will be lost.

Contact your local Allen–Bradley representative if the error persists.

Cycle power on your unit.

Download your program and re–initialize any necessary data.

Start up your system.

Contact your local Allen–Bradley representative if the error persists.

15–4

Troubleshooting Faults

Going-to-Run Errors

Error Code

(Hex)

0008

0009

0010

0016

0018

Advisory Message

FATAL INTERNAL

SOFTWARE ERROR

FATAL INTERNAL

HARDWARE ERROR

INCOMPATIBLE PROCESSOR

STARTUP PROTECTION

AFTER POWERLOSS;

S:1/9 IS SET

USER PROGRAM IS

INCOMPATIBLE WITH

OPERATING SYSTEM

Description

The controller software has detected an invalid condition within the hardware or software after completing power-up processing

(after the first 2 seconds of operation).

The controller software has detected an invalid condition within the hardware during power-up processing (within the first 2 seconds of operation).

The downloaded program is not configured for a micro controller.

The system has powered up in the

REM Run mode. Bit S:1/13 is set and the user–fault routine is run before beginning the first scan of the program.

An incompatible program was downloaded. Either the program does not have the correct number of files or it does not have the correct size data files. The default program is loaded.

Recommended Action

Cycle power on your unit.

Download your program and re–initialize any necessary data.

Start up your system.

Contact your local Allen–Bradley representative if the error persists.

Cycle power on your unit.

Download your program and re–initialize any necessary data.

Start up your system.

Contact your local Allen–Bradley representative if the error persists.

If you want to use a micro controller with the program, reconfigure your controller with

MPS or APS (choose Bul. 1761).

Either reset bit S:1/9 if this is consistent with your application requirements, and change the mode back to REM Run, or

• clear S:1/13, the major fault bit.

Check the configuration and make sure the correct processor is selected.

If you want to use a micro controller with the program, reconfigure your controller with

MPS or APS (choose Bul.

1761), or RSLogix 500.

15–5

Run Errors

Error Code

(Hex)

0004

0020

0022

0024

0025

0027

002A

002B

0030

Advisory Message

RUNTIME MEMORY

INTEGRITY ERROR

MINOR ERROR AT END OF

SCAN, SEE S:5

WATCHDOG TIMER

EXPIRED, SEE S:3

INVALID STI INTERRUPT

SETPOINT, SEE S:30

TOO MANY JSRs IN STI

SUBROUTINE

TOO MANY JSRs IN FAULT

SUBROUTINE

INDEXED ADDRESS TOO

LARGE FOR FILE

TOO MANY JSRs IN HSC

SUBROUTINE NESTING

EXCEEDS LIMIT OF 8

Description

While the controller was in the

RUN mode or any test mode, the

ROM or RAM became corrupt. If the user program is valid, the program and initial data downloaded to the controller is used and the Retentive Data Lost

Bit (S:5/8) is set. If the user program is invalid, error 0003 occurs.

A minor fault bit (bits 0–7) in S:5 was set at the end of scan.

The program is referencing through indexed addressing an element beyond a file boundary.

There are more than 3 subroutines nested in the high–speed counter routine (file 4).

There are more than 8 subroutines nested in the main program file (file

2).

Recommended Action

Cycle power on your unit.

Download your program and re–initialize any necessary data.

Start up your system.

Contact your local Allen–Bradley representative if the error persists.

The program scan time exceeded the watchdog timeout value (S:3H).

An invalid STI interval exists (not between 0 and 255).

There are more than 3 subroutines nested in the STI subroutine

(file 5).

There are more than 3 subroutines nested in the fault routine (file 3).

Enter the status file display, clear the fault and return to REM Run mode.

Verify if the program is caught in a loop and correct the problem.

Increase the watchdog timeout value in the status file.

Set the STI interval between the values of 0 and 255.

Correct the user program to meet the requirements and restrictions for the JSR instruction, then reload the program and enter the REM

Run mode.

Correct the user program to meet the requirements and restrictions for the JSR instruction, then reload the program and enter the REM

Run mode.

Correct the user program to not go beyond file boundaries.

Correct the user program to meet the requirements and restrictions for the JSR instruction, then reload the program and enter the

REM Run mode.

Correct the user program to meet the requirements and restrictions for the main program file, then reload the program and enter the

REM Run mode.

15–6

Troubleshooting Faults

Error Code

(Hex)

0031

0032

0033

0034

0035

0037

0038

0040

Advisory Message

UNSUPPORTED

INSTRUCTION DETECTED

SQO/SQC CROSSED DATA

FILE BOUNDARIES

BSL/BSR/FFL/FFU/LFL/LFU

CROSSED DATA FILE

BOUNDARIES

NEGATIVE VALUE IN TIMER

PRESET OR ACCUMULATOR

ILLEGAL INSTRUCTION

(TND) IN INTERRUPT FILE

INVALID PRESETS LOADED

TO HIGH–SPEED COUNTER

SUBROUTINE RETURN

INSTRUCTION (RET) IN

PROGRAM FILE 2

OUTPUT VERIFY WRITE

FAILURE

Description

Recommended Action

The program contains an instruction(s) that is not supported by the micro controller. For example MSG, SVC, or PID.

A sequencer instruction length/position parameter points past the end of a data file.

The length parameter of a BSL,

BSR, FFL, FFU, LFL, or LFU instruction points past the end of a data file.

A negative value was loaded to a timer preset or accumulator.

Modify the program so that all instructions are supported by the controller, then reload the program and enter the REM Run mode.

Correct the program to ensure that the length and position parameters do not point past the data file.

Reload the program and enter the

REM Run mode.

Correct the program to ensure that the length parameter does not point past the data file. Reload the program and enter the REM Run mode.

If the program is moving values to the accumulated or preset word of a timer, make certain these values are not negative. Correct the program, reload, and enter the

REM Run mode.

Correct the program, reload, and enter the REM Run mode.

The program contains a Temporary

End (TND) instruction in file 3, 4, or

5 when it is being used as an interrupt subroutine.

Either a zero (0) or a negative high preset was loaded to counter

(C5:0) when the HSC was an Up counter or the high preset was lower than or equal to the low preset when the HSC was a

Bidirectional counter.

A RET instruction is in the main program file (file 2).

When outputs were written and read back by the controller, the read failed. This may have been caused by noise.

Check to make sure the presets are valid.

Correct the program, reload, and enter the REM Run mode.

Remove the RET instruction, reload the program and enter the

REM Run mode.

Refer to proper grounding guidelines in the

MicroLogix 1000 Programmable

Controllers User Manual, publication 1761-6.3.

Start up your system.

Contact your local Allen–Bradley representative if the error persists.

15–7

Error Code

(Hex)

0041

Advisory Message

Description

EXTRA OUTPUT BIT(S)

TURNED ON

An extra output bit was set when the Extra Output Select (S:0/8) bit in the status file was reset. For

16–point controllers this includes bits 6–15. For 32–point controllers this includes bits 12–15.

Valid for Series A and Series C discrete controllers only.

Recommended Action

Set S:0/8 or change your application to prevent these bits from being turned on.

Correct the program, reload, and enter the REM Run mode.

Download Error

Error Code

(Hex)

0018

Advisory Message

USER PROGRAM IS

INCOMPATIBLE WITH

OPERATING SYSTEM

Description

An incompatible program was downloaded. Either the program does not have the correct number of files or it does not have the correct size data files. The default program is loaded.

Recommended Action

Check the configuration and make sure the correct processor is selected.

If you want to use a micro controller with the program, reconfigure your controller with

MPS or APS (choose Bul.

1761), or RSLogix 500.

SLC Processor Faults

The processor faults are divided into the following types:

• powerup errors

• going-to-run errors

• run errors

• user program instruction errors

15–8

Troubleshooting Faults

Powerup Errors

Error Code

(Hex)

0001

Description

NVRAM error.

0002

0003

0007

0008

0009

Unexpected hardware watchdog timeout.

Memory module memory error.

This error can also occur when going to the REM Run mode.

Failure during memory module transfer.

Internal software error.

Internal hardware error.

Probable Cause

Either noise,

• lightning,

• improper grounding,

• lack of surge suppression on outputs with inductive loads, or

• poor power source.

Loss of battery or capacitor backup.

Either noise,

• lightning,

• improper grounding,

• lack of surge suppression on outputs with inductive loads, or

• poor power source.

Memory module is corrupted.

Memory module is corrupted.

An unexpected software error occurred due to:

Either noise,

• lightning,

• improper grounding,

• lack of surge suppression on output with inductive loads, or

• poor power source.

An unexpected hardware error occurred due to:

Either noise,

• lightning

• improper grounding,

• lack of surge suppression on output with inductive loads, or

• poor power source.

Recommended Action

Correct the problem, reload the program, and run. You can use the autoload feature with a memory module to automatically reload the program and enter the Run mode.

Correct the problem, reload the program, and run. You can use the autoload feature with a memory module to automatically reload the program and enter the Run mode.

Re-program the memory module. If the error persists, replace the memory module.

Re–program the memory module.

If the error persists, replace the memory module.

Correct the problem, reload the program, and run. You can use the autoload feature with a memory module to automatically reload the program and enter the Run mode.

If the problem re–occurs, contact your RSI representative.

Correct the problem, reload the program, and run. You can use the autoload feature with a memory module to automatically reload the program and enter the Run mode.

If the problem re–occurs, contact your A–B representative.

15–9

Going-to-Run Errors

Error Code

(Hex)

0010

0011

0012

0013

0014

0015

0016

0017

Description Probable Cause Recommended Action

The processor does not meet the required revision level.

The executable program file number 2 is absent.

The ladder program has a memory error.

The required memory module is absent, or

S:1/10 or S:1/11 is not set as required by the program.

Internal file error.

Configuration file error.

Startup protection after power loss.

Error condition exists at powerup when bit S:1/9 is set and powerdown occurred while running.

NVRAM/memory module user program mismatch.

The revision level of the processor is not compatible with the revision level for which the program was developed.

Incompatible or corrupt program is present.

Either noise,

• lightning,

• improper grounding,

• lack of surge suppression on outputs with inductive loads, or

• poor power source.

Either one of the status bits is set in the program but the required memory module is absent, or

• status bit S:1/10 or S:1/11 is not set in the program stored in the memory module, but it is set in the program in the processor memory.

Either noise,

• lightning,

• improper grounding,

• lack of surge suppression on outputs with inductive loads, or

• poor power source.

Either noise,

• lightning,

• improper grounding,

• lack of surge suppression on outputs with inductive loads, or

• poor power source.

Status bit S:1/9 has been set by the user program. Refer to

appendix A for details on the

operation of status bit S:1/9.

Bit S:2/9 is set and the memory module user program does not match the NVRAM user program.

Consult your local A–B representative to purchase an upgrade kit for your processor.

Reload the program or reprogram with RSI approved APS programming software.

Correct the problem, reload the program, and run. If the error persists, be sure to use RSI approved APS programming software to develop and load the program.

Either install a memory module in the processor, or

• upload the program from the processor to the memory module.

Correct the problem, reload the program, and run. If the error persists, be sure to use RSI approved APS programming software to develop and load the program.

Correct the problem, reload the program, and run. If the error persists, be sure to use RSI approved APS programming software to develop and load the program.

Either reset bit S:1/9 if this is consistent with the application requirements, and change the mode back to run, or

• clear S:1/13, the major fault bit, before the end of the first program scan is reached.

Transfer the memory module program to NVRAM then change to

Run mode.

15–10

Troubleshooting Faults

Error Code

(Hex)

0018

0019

Description

Incompatible user program.

Operating system type mismatch.

This error can also occur during powerup.

A duplicate label number was detected.

Probable Cause

The user program is too advanced to be executed in the current operating system.

A duplicate or missing label instruction was found in a subroutine.

Recommended Action

Contact your RSI representative for information about available operating systems for the 5/03 processor.

Either remove the duplicate label, or

• add a label.

Run Errors

Error Code

(Hex)

001F

0004

0020

Description

A program integrity problem occurred during an online editing session.

Memory error occurred while in the

Run mode.

A minor error bit is set at the end of the scan. Refer to S:5 minor error bits (lower byte only).

Probable Cause

Either noise, communication loss, or a power cycle occurred during an online edit session.

Either noise,

• lightning,

• improper grounding,

• lack of surge suppression on outputs with inductive loads, or

• poor power source.

Either a math or FRD instruction overflow has occurred,

• sequencer or shift register instruction error was detected,

• a major error was detected while executing a user fault routine, or

M0–M1 file addresses were referenced in the user program for a disabled slot.

Recommended Action

Reload the program and re–enter your changes.

Correct the problem, reload the program, and run. You can use the autoload feature with a memory module to automatically reload the program and enter the Run mode.

Correct the programming problem, reload the program and enter the run mode. See also minor error

bits S:5 in appendix B.

15–11

Error Code

(Hex)

0021

0022

0023

Description

A remote power failure of an expansion I/O chassis has occurred.

Note: A modular system that encounters an over–voltage or over–current condition in any of its power supplies can produce any of the I/O error codes listed on

pages 15–16 through 15–19

(instead of code 0021). The over–voltage or over–current condition is indicated by the power supply LED being off.

!

Fixed and FRN 1 through 4 SLC 5/01 processors – if the remote power failure occurred while the processor was in the REM Run mode, error 0021 will cause the major error halted bit (S:1/13) to be cleared at the next powerup of the local chassis.

Fixed and FRN 1 to 4 SLC 5/01 processors: Power was removed or the power dipped below specification for an expansion chassis.

SLC 5/02 processors and FRN 5

SLC 5/01 processors: This error code is present only while power is not applied to an expansion chassis. This is the only self-clearing error code. When power is re-applied to the expansion chassis, the fault will be cleared.

Fixed and FRN 1 to 4 SLC 5/01 processors: Cycle power on the local chassis.

SLC 5/02 processors and FRN 5

SLC 5/01 processors: Re-apply power to the expansion chassis.

SLC 5/02 processor and FRN 5

SLC 5/01 processors – power to the local chassis does not need to be cycled to resume the REM Run mode. Once the remote chassis is re–powered, the CPU will restart the system.

The user watchdog scan time has been exceeded.

Invalid or non-existent STI interrupt file.

Probable Cause

Either Watchdog time is set too low for the user program, or

• user program caught in a loop.

Either an STI interrupt file number was assigned in the status file, but the subroutine file was not created, or

• the STI interrupt file number assigned was 0, 1, or 2.

Recommended Action

Either increase the watchdog timeout in the status file

(S:3H), or

• correct the user program problem.

Either disable the STI interrupt setpoint (S:30) and file number

(S:31) in the status file, or

• create an STI interrupt subroutine file for the file number assigned in the status file (S:31). The file number must not be 0, 1, or 2.

15–12

Troubleshooting Faults

Error Code

(Hex)

0024

0025

0026

0027

0028

0029

002A

002B

Description

Invalid STI interrupt interval

(greater than 2550 ms or negative).

Excessive stack depth/JSR calls for the STI routine.

Excessive stack depth/JSR calls for an I/O interrupt routine.

Excessive stack depth/JSR calls for the user fault routine.

negative).

Probable Cause

The STI setpoint is out of range

(greater than 2550 ms or

A JSR instruction is calling for a file number assigned to an STI routine.

A JSR instruction is calling for a file number assigned to an I/O interrupt routine.

A JSR instruction is calling for a file number assigned to the user fault routine.

Invalid or non-existent “startup protection” fault routine file value.

Indexed address reference is outside of the entire data file space (range of B3:0 through the last file).

Either a fault routine file number was created in the status file, but the fault routine file was not physically created, or

• the file number created was 0,

1, or 2.

The program is referencing through indexed addressing an element beyond the allowed range.

The range is from B3:0 to the last element of the last data file created by the user.

!

The SLC 5/02 processor uses an index value of zero for the faulted instruction following error recovery.

Indexed address reference is beyond the specific referenced data file.

The program is referencing through indexed addressing an element beyond a file boundary.

Recommended Action

Either disable the STI interrupt setpoint (S:30) and file number

(S:31) in the status file, or

• create an STI interrupt routine for the file number referenced in the status file (S:31). The file number must not be 0, 1, or 2.

Correct the user program to meet the requirements and restrictions for the JSR instruction, then reload the program and run.

Correct the user program to meet the requirements and restrictions for the JSR instruction, then reload the program and run.

Correct the user program to meet the requirements and restrictions for the JSR instruction, then reload the program and run.

Either disable the fault routine file number (S:29) in the status file, or

• create a fault routine for the file number referenced in the status file (S:29). The file number must not be 0, 1, or 2.

Correct and reload the user program. This problem cannot be corrected by writing to the index register word (S:24).

An invalid file number for an indirect address exists.

The file number exists, but it is not the correct file type or the file number does not exist.

Correct the user program, allocate more data space using the memory map, or re-save the program allowing crossing of file boundaries. Reload the user program. This problem cannot be corrected by writing to the index register word (S:24).

Check the file type or create the file number..

15–13

Error Code

(Hex)

002C

002D

002E

002F

Description

The referenced indirect address element is outside data file limits.

An invalid referenced indirect address subelement exists.

Invalid DII Input slot.

Invalid or non-existent DII interrupt file.

Probable Cause

The indirectly referenced element does not exist, but the file type is correct and it exists.

Either a subelement is referenced incorrectly or an indiret reference has been made to an M-file.

The referenced slot is empty or a non–discrete I/O card is present.

Either an DII interrupt file number was assigned in the status file, but the subroutine file was not created, or

• the DII interrupt file number assigned was 0, 1, or 2.

Recommended Action

Create the indirectly reference element.

Correct the references and try again.

Change the input slot to a discrete

I/O card.

Either disable the DII function by writing a zero to this location, or change the value to a valid ladder file (3–255).

User Program Instruction Errors

Error Code

(Hex)

0030

0031

0032

0033

Description

An attempt was made to jump to one too many nested subroutine files. This code can also mean that a program has potential recursive routines.

An unsupported instruction reference was detected.

A sequencer instruction length/position parameter points past the end of a data file.

The length parameter of an LFU,

LFL, FFU, FFL, BSL, or BSR instruction points past the end of a data file.

Probable Cause

Either more than the maximum of 4 (8 if you are using a 5/02 or 5/03 processor) levels of nested subroutines are called for in the user program, or

• nested subroutine(s) are calling for subroutine(s) of a previous level.

The type or series level of the processor does not support an instruction residing in the user program, or you have programmed a constant as the first operand of a compare instruction.

The program is referencing an element beyond a file boundary set up by the sequencer instruction.

The program is referencing an element beyond a file boundary set up by the instruction.

Recommended Action

Correct the user program to meet the requirements and restrictions for the JSR instruction, then reload the program and run.

Either replace the processor with one that supports the user program, or

• modify the user program so that all instructions are supported by the processor, then reload the program and run.

Correct the user program or allocate more data file space using the memory map, then reload and run.

Correct the user program or allocate more data file space using the memory map, then reload and run.

15–14

Troubleshooting Faults

Error Code

(Hex)

0034

Description Probable Cause

0034

(related to fixed

5/01 HSC instruction)

A negative value for a timer accumulator or preset value was detected.

Fixed processors with 24 VDC input only: A negative or zero HSC preset was detected in a HSC instruction.

A negative or zero HSC preset was detected in an HSC instruction.

The accumulated or preset value of a timer in the user program was detected as being negative.

The preset value for the HSC instruction is out of the valid range.

Valid range is 1–32767.

0035

0036

0038 xx3A

1f39

TND, SVC, or REF instruction is called within an interrupting or user fault routine.

An invalid value is being used for a

PID instruction parameter.

A RET instruction was detected in a non-subroutine file.

An attempt to write to a protected data file occurred.

An invalid string length was detected in a string file.

Recommended Action

If the user program is moving values to the accumulated or preset word of a timer, make certain these values cannot be negative. Correct the user program, reload, and run.

A TND, SVC, or REF instruction is being used in an interrupt or user–fault routine. This is illegal.

An invalid value was loaded into a

PID instruction by the user program or by the user via the data monitor function for this instruction.

A RET instruction resides in the main program.

An attempt was made to write to an indirect address located in a file that has constant data file protection.

The first word of string data contains a negative, zero, or value greater than 82.

If the user program is moving values to the preset word of the

HSC instruction, make certain the values are within the valid range.

Correct the user program, reload, and run.

Correct the user program, reload, and run.

Code 0036 is discussed in

chapter 10 in this manual.

Correct the user program, reload, and run.

Remove the protection and retry the function.

Check the first word of the string data elements for invalid values and correct the user data.

15–15

I/O Errors

ERROR CODES: The characters xx in the following codes represent the slot number, in hexadecimal. If the exact slot cannot be determined, the characters xx become 03 for fixed controllers and 1F for modular controllers.

Refer to the table to the right.

RECOVERABLE I/O FAULTS (SLC 5/02 and higher processors only): Many I/O faults are recoverable. To recover, you must disable the specified slot, xx, in the user fault routine. If you do not disable slot xx, the processor will fault at the end of the scan.

Note: An I/O card that is severly damaged may cause the processor to indicate that an error exists in slot 1 even though the damaged card is installed in a slot other than 1.

SLOT NUMBERS (xx) IN HEXADECIMAL

Slot xx

0 00

1 01

2 02

3 03**

4 04

5 05

6 06

7 07

Slot xx

8 08

9 09

10 0A

11 0B

12 0C

13 0D

14 0E

15 0F

Slot xx

16 10

17 11

18 12

19 13

20 14

21 15

22 16

23 17

Slot xx

24 18

25 19

26 1A

27 1B

28 1C

29 1D

30 1E

1F*

Error Code

(Hex) xx50 xx51 xx52

Description

A chassis data error is detected.

A “stuck” runtime error is detected on an I/O module.

A module required for the user program is detected as missing or removed.

Probable Cause

Either noise,

• lightning,

• improper grounding,

• lack of surge suppression on outputs with inductive loads, or

• poor power source.

If this is a discrete I/O module, this is a noise problem. If this is a specialty I/O module, refer to the applicable user manual for the probable cause.

An I/O module configured for a particular slot is missing or has been removed.

Correct the problem, clear the fault, and re-enter Run mode.

Cycle power to the system. If this does not correct the problem, replace the module.

Recommended Action

Either disable the slot in the status file (S:11 and S:12), or

• insert the required module in the slot.

15–16

Troubleshooting Faults

Error Code

(Hex) xx53 xx54 xx55 xx56 xx57 xx58

Description

When going-to-run, a user program declares a slot as unused, and that slot is detected as having an I/O module inserted.

This code can also mean that an

I/O module has reset itself.

Probable Cause

Either the I/O slot is not configured for a module, but a module is present, or

• the I/O module has reset itself.

Recommended Action

Either disable the slot in the status file (S:11 and S:12), clear the fault and run,

• remove the module, clear the fault and run, or

• modify the I/O configuration to include the module, then reload the program and run.

If you suspect that the module has reset itself, clear the major fault and run.

Disable all slots in the empty chassis (see S:11 and S:12).

SLC 5/03 specific – An attempt was made to enter the run or test mode with an empty chassis.

A module required for the user program is detected as being the wrong type.

A discrete I/O module required for the user program is detected as having the wrong I/O count.

This code can also mean that a specialty card driver is incorrect.

The chassis configuration specified in the user program is detected as being incorrect.

A specialty I/O module has not responded to a Lock Shared

Memory command within the required time limit.

A specialty I/O module has generated a generic fault. The card fault bit is set (1) in the module’s status byte.

A chassis is void of all I/O modules.

An I/O module in a particular slot is a different type than was configured for that slot by the user.

If this is a discrete I/O module, the I/O count is different from that selected in the I/O configuration.

If this is a specialty I/O module, the card driver is incorrect.

The chassis configuration specified by the user does not match the hardware.

The specialty I/O module is not responding to the processor in the time allowed.

Refer to the user manual of the specialty I/O module.

Either replace the module with the correct module, clear the fault, and run, or

• change the I/O configuration for the slot, reload the program, and run.

If this is a discrete I/O module, replace it with a module having the I/O count selected in the I/O configuration. Then, clear the fault and run, or

• change the I/O configuration to match the existing module, then reload the program and run.

If this is a specialty I/O module, refer to the user manual for that module.

Correct the chassis configuration, reload the program and run.

Cycle chassis power. If this does not correct the problem, refer to the user manual for the specialty

I/O module. You may have to replace the module.

Cycle chassis power. If this does not correct the problem, refer to the user manual for the specialty

I/O module. You may have to replace the module.

15–17

Error Code

(Hex) xx59 xx5A

Description

A specialty I/O module has not responded to a command as being completed within the required time limit.

Hardware interrupt problem.

Probable Cause

A specialty I/O module did not complete a command from the processor in the time allowed.

If this is a discrete I/O module, this is a noise problem. If this is a specialty I/O module, refer to the user manual for the module.

xx5B xx5C xx5D xx5E

G file configuration error – user program G file size exceeds the capacity of the module.

M0–M1 file configuration error – user program M0–M1 file size exceeds capacity of the module.

Interrupt service requested is not supported by the processor.

Processor I/O driver (software) error.

Identifies an I/O module specific recoverable major error.

G file is incorrect for the module in this slot.

M0–M1 files are incorrect for the module in this slot.

The specialty I/O module has requested service and the processor does not support it.

Corrupt processor I/O driver software.

Recommended Action

Refer to the user manual for the specialty I/O module. You may have to replace the module.

Cycle chassis power. Check for a noise problem and be sure proper grounding practices are used. If this is a specialty I/O module, refer to the user manual for the module.

You may have to replace the module.

Refer to the user manual for the specialty I/O module. Reconfigure the G file as directed in the manual, then reload and run.

Refer to the user manual for the specialty I/O module. Reconfigure the M0–M1 files as directed in the manual, then reload and run.

Refer to the user manual for the specialty I/O module to determine which processors support use of the module. Change processor to one that supports the module.

Reload program using RSI approved APS software.

xx60 through xx6F xx70 through xx7F xx80 through xx8F xx90

Identifies an I/O module specific non-recoverable major error.

Identifies a specialty I/O module specific non-recoverable major error.

Interrupt problem on a disabled slot.

A specialty I/O module requested service while a slot was disabled.

xx91

A disabled slot has faulted.

A specialty I/O module in a disabled slot has faulted.

Refer to the user manual for the specialty I/O module. You may have to replace the module.

Cycle chassis power. If this does not correct the problem, refer to the user manual for the specialty

I/O module. You may have to replace the module.

15–18

Troubleshooting Faults

Error Code

(Hex) xx92 xx93 xx94

0x01A0

Description

Invalid or non-existent module interrupt subroutine (ISR) file.

Unsupported I/O module specific major error.

A module has been detected as being inserted under power in the run or test mode.

This can also mean that an I/O module has reset itself.

A major fault unique to the

SLC 5/05. The error code indicates communication channel hardware fault has occured.

Probable Cause

The I/O configuration/ISR file information for a specialty I/O module is incorrect.

Recommended Action

Correct the I/O configuration/ISR file information for the specialty I/O module. Refer to the user manual for the module for the correct ISR file information. Then reload the program and run.

Refer to the user manual for the specialty I/O module.

The processor does not recognize the error code from a specialty I/O module.

The module was inserted in the chassis under power, or the module has reset itself.

Ethernet communication fault.

No module should ever be inserted in a chassis under power. If this occurs and the module is not damaged,

Either remove the module, clear the fault and run, or

• add the module to the I/O configuration, reference the module in the user program where required, reload the program, and run.

The fault may be cleared via a write to the System Status File, but

Ethernet communications will be disabled until a power cycle is performed.

Word 15 of the System Status File provides a specific fault code for the Ethernet daughterboard when user fault code 0x01A0 is generated. Recoverable, but

Ethernet communication is disabled.

15–19

Troubleshooting SLC 5/03 and Higher Processors

Between the time you apply power to the processor, and it has a chance to establish communication with a connected programming device, the only form of communication between you and the processor is through the LED display.

Powerup LED Display

When power is applied, all the LEDs flash on momentarily and then off. This is part of the normal power-up sequence. Following the self test by the processor, all of the LEDs flash on again momentarily. If a user program is in a running state, the

RUN LED is illuminated. If a fault exists within the processor, the FLT LED is illuminated.

Identifying Processor Errors while Downloading an Operating System

The download process takes approximately 45 seconds. During this time, watch the

LED display for status information. While the download is in progress, the RUN and FLT LEDs remain off. The RS232, DH485 or DH

+

, Ethernet, FORCE, and

BATT LEDs illuminate in a pre-defined sequence. If the download is successful, the above LEDs are illuminated.

If during the download process of an operating system type memory module or during the normal power-up self test process an error occurs, the FLT LED is illuminated and the four LEDs flash on and off at a rate of 2 seconds.

The following table describes the possible LED combinations that are displayed every other time the LEDs flash on.

ON LED Display

FAULT, FORCE, DH485, DH

+

, or Ethernet

FAULT, FORCE, RS232, DH485 or DH

+

FAULT, BATT

Fatal hardware error exists.

Description

A hardware watchdog timeout exists.

NVRAM error exists.

FAULT, BATT, RS232

FAULT, BATT, DH485 or DH

+

The contents of the operating system memory module are corrupt.

The downloadable operating system is not compatible with the hardware.

FAULT, BATT, RS232, DH485, DH

+

, or Ethernet

An attempt was made to download the operating system onto write–protected memory.

Flash EEPROM failure.

FAULT, BATT, FORCE

FAULT, BATT, FORCE, RS232 Failure during transmission of downloadable operating system.

FAULT, BATT, FORCE, DH485, DH

+

, or Ethernet The operating system is missing or has been corrupted.

15–20

MicroLogix 1000 Controller Status File

A

MicroLogix 1000 Controller

Status File

This appendix discusses the status file functions of MicroLogix 1000 controllers.

A–1

Status File Overview

Note

The status file lets you monitor how your operating system works and lets you direct how you want it to work. This is done by using the status file to set up control bits and monitor both hardware and software faults and other status information.

Do not write to reserved words in the status file. If you intend writing to status file data, it is imperative that you first understand the function fully.

The status file S: contains the following words:

Word

S:0

S:1L (low byte)

S:1H (high byte)

S:2L (low byte)

S:2H (high byte)

S:5

S:6

S:7

S:3L (low byte)

S:3H (high byte)

S:4

Current Scan Time

Watchdog Scan Time

Timebase

Minor Error Bits

Major Error Code

Suspend Code

Function

Arithmetic Flags

Controller Mode Status/Control (low)

Controller Mode Status/Control (Hi)

Controller Alternate Mode Status/Control (low)

Controller Alternate Mode Status/Control (Hi)

S:8 to S:12

S:13, S:14

Reserved

Math Register

S:15L (low byte) DF1 Node Address

S:15H (high byte) DF1 Baud Rate

S:16L (low byte) DH-485 Node Address

S:16H (high byte) DH-485 Baud Rate

S:17 to S:21 Reserved

S:22

S:23

S:24

Maximum Observed Scantime

Reserved

Index Register

S:25 to S:29

S:30

S:31 and S:32

Reserved

STI Setpoint

Reserved

A–19

A–19

A–19

A–19

A–20

A–20

A–20

A–20

A–20

A–11

A–11

A–12

A–12

A–14

A–18

A–3

Page

A–5

A–5

A–8

A–8

A–18

A–18

A–18

A–19

A–2

MicroLogix 1000 Controller Status File

Status File Descriptions

The following tables describe the status file functions, beginning at address S:0 and ending at address S:32.

Each status bit is classified as one of the following:

Status — Use these words, bytes, or bits to monitor controller operation or controller status information. The information is seldom written to by the user program or programming device (unless you want to reset or clear a function such as a monitor bit).

Dynamic Configuration — Use these words, bytes, or bits to select controller options while online with the controller.

Static Configuration — Use these words, bytes, or bits to select controller options while in the offline program mode, prior to downloading the user program.

Address

S:0

S:0/0

S:0/1

Bit

Arithmetic and

Scan Status

Flags

Classification

Carry

Overflow

Status

Status

Description

The arithmetic flags are assessed by the controller following the execution of certain math and data handling instructions. The state of these bits remain in effect until certain math or data handling instructions in the program are executed.

This bit is set by the controller if a mathematical carry or borrow is generated.

Otherwise the bit remains cleared. This bit is assessed as if a function of unsigned math.

When a STI, high-speed counter, or Fault

Routine interrupts normal execution of your program, the original value of S:0/0 is restored when execution resumes.

This bit is set by the controller when the result of a mathematical operation does not fit in its destination. Otherwise the bit remains cleared.

Whenever this bit is set, the overflow trap bit

S:5/0 is also set except for the ENC bit. Refer to S:5/0. When a STI, high-speed counter, or

Fault Routine interrupts normal execution of your program, the original value of S:0/1 is restored when execution resumes.

A–3

A–4

Address

S:0/2

S:0/3

S:0/4 to

S:0/7

S:0/8

S:0/9

S:0/10

S:0/11

S:0/12

S:0/13 to

S:0/15

Zero

Sign

Active

Bit

Reserved

Extend I/O

Configuration

Static

Configuration

Reserved

Primary

Protocol

Protocol

Selected DF1

Protocol

Reserved

Classification

Status

Status

Description

This bit is set by the controller when the result of certain math or data handling instructions is zero. Otherwise the bit remains cleared.

When a STI, high-speed counter, or Fault

Routine interrupts normal execution of your program, the original value of S:0/2 is restored when execution resumes.

This bit is set by the controller when the result of certain math or data handling instructions is negative. Otherwise the bit remains cleared.

When a STI, high-speed counter, or Fault

Routine interrupts normal execution of your program, the original value of S:0/3 is restored when execution resumes.

NA

Static

Configuration

Status

Status

NA

This bit must be set by the user when unused outputs are written to. If reset and unused outputs are turned on the controller will fault

(41H).

NA

This bit defines the protocol that the controller will initially use when attempting to establish communication, where:

0 = DF1 (default setting)

1 = DH-485

This bit is updated by the controller during a protocol switch. It indicates which protocol is currently being used for communication, where:

0 = DF1

1 = DH-485

This bit allows the user to determine which

DF1 protocol is configured, where:

0 = DF1 Full-Duplex (default setting)

1 = DF1 Half-Duplex

NA

Valid for Series A–C discrete only.

MicroLogix 1000 Controller Status File

Address

S:1/0 to

Bit

Controller

Control

S:1/5

S:1/6

S:1/7

S:1/8

Classification

Status

Description

Bits 0–4 function as follows:

Forces

Enabled

Forces

Installed

Status

Status

Comms Active Status

Fault Override at Powerup

Static

Configuration u

T u u

0 1000 = (8) Remote Test single scan mode

This bit is set by the controller (1) to indicate that forces are always enabled.

This bit is set by the controller to indicate that forces have been set by the user.

This bit is set when the controller receives valid data from the programming port. For DF1 protocols, the bit is reset if the controller does not receive valid data from the programming port for 10 seconds.

Note: In DF1 half-duplex mode, simple polls by the DF1 master or replies to received messages will not reset the timer. A poll with a command is required to reset the timer.

For DH-485, the bit is reset as soon as the

DH-485 link layer determines that no other devices are active on the link.

Application Note: For DF1 half-duplex, you can use this bit to enable a timer (via an XIO instruction) to sense whether the DF1 master is actively communicating to the slave. The preset of the timer is determined by the total network timing.

When set, this bit causes the controller to clear the Major Error Halted bit S:1/13 and Minor error bits S:5/0 to S:5/7 on power up if the processor had previously been in the REM Run mode and had faulted. The controller then attempts to enter the REM Run mode. Set this bit using the Data Monitor function offline only.

A–5

A–6

Address

S:1/9

S:1/10 to

S:1/11

S:1/12

Startup

Protection

Fault

Bit Classification

Static

Configuration

Description

When this bit is set and power is cycled while the controller is in the REM Run mode, the controller executes the user–fault routine prior to the execution of the first scan of your program. You have the option of clearing the

Major Error Halted bit S:1/13 to resume operation in the REM Run mode. If user–fault routine does not reset bit S:1/13, the fault mode results.

Program the user-fault routine logic accordingly. When executing the startup protection fault routine, S:6 (major error fault code) will contain the value 0016H.

Reserved

Run Always Static

Configuration

When set, this bit causes the controller to clear

S:1/13 and S:5/0–7 before attempting to enter

RUN mode when power is applied or if an unexpected reset occurs. If this bit is not set, the controller powers up in the previous mode it was in before losing power, unless the controller was in REM test mode. If the controller was in REM test mode when power was removed, the controller enters REM program mode when power is applied.

This bit overrides any faults existing at power down.

Setting the Run Always bit

!

causes the controller to enter the REM Run mode if an unexpected reset occurs, regardless of the mode that the controller was in before the reset occurred. Unexpected resets may occur due to electromagnetic noise, improper grounding, or an internal controller hardware failure. Make sure your application is designed to safely handle this situation.

MicroLogix 1000 Controller Status File

Address

S:1/13

Bit

Major Error

Halted

Classification

Dynamic

Configuration

Description

This bit is set by the controller any time a major error is encountered. The controller enters a fault condition. Word S:6, the Fault Code will contain a code that can be used to diagnose the fault condition. Any time bit S:1/13 is set, the controller:

• either places all outputs in a safe state

(outputs are off) and energizes the fault

LED,

• or enters the user–fault routine with outputs active (if in REM Run mode), allowing the fault routine ladder logic to attempt recovery from the fault condition.

If the user–fault routine determines that recovery is required, clear S:1/13 using ladder logic prior to exiting the fault routine. If the fault routine ladder logic does not understand the fault code, or if the routine determines that it is not desirable to continue operation, the controller exits the fault routine with bit

S:1/13 set. The outputs are placed in a safe state and theFAULT LED is energized.

When you clear bit S:1/13 using a programming device, the controller mode changes from fault to Remote Program. You can move a value to S:6, then set S:1/13 in your ladder program to generate an application-specific major error. All application-generated faults are recoverable regardless of the value used.

Note: Once a major fault state exists, you

must correct the condition causing the fault, and you must also clear this bit in order for the controller to accept a mode change attempt

(into REM Run or REM Test). Also, clear S:6 to avoid the confusion of having an error code but no fault condition.

Note: Do not re-use error codes that are

defined later in this appendix as application-specific error codes. Instead, create your own unique codes. This prevents you from confusing application errors with system errors.

We recommend using error codes FFOO to

FFOF to indicate application-specific major errors.

A–7

A–8

Address

S:1/14

S:1/15

S:2/0

S:2/1

S:2/2

S:2/3 to

S:2/4

Bit

OEM Lock

First Pass

STI Pending

STI Enabled

STI Executing

Reserved

Classification

Static

Status

Status

Status and

Static

Configuration

Status

NA

Description

Using this bit you can control access to a controller file.

To program this feature, select “Future Access

Disallow” when saving your program.

When this bit is cleared, it indicates that any compatible programming device can access the ladder program (provided that password conditions are satisfied).

Use this bit to initialize your program as the application requires. When this bit is set by the controller, it indicates that the first scan of the user program is in progress (following power up in the RUN mode or entry into a REM Run or REM Test mode). The controller clears this bit following the first scan.

This bit is set during execution of the startup protection fault routine. Refer to S:1/9 for more information.

When set, this bit indicates that the STI timer has timed out and the STI routine is waiting to be executed. This bit is cleared upon starting the STI routine, ladder program, exit of the

REM Run or Test mode, or execution of a true

STS instruction.

This bit may be set or reset using the STS,

STE, or STD instruction. If set, it allows execution of the STI if the STI setpoint S:30 is non–zero. If clear, when an interrupt occurs, the STI subroutine does not execute and the

STI Pending bit is set. The STI Timer continues to run when this bit is disabled. The

STD instruction clears this bit.

If this bit is set or reset editing the status file online, the STI is not affected. If this bit is set, the bit allows execution of the STI. If this bit is reset editing the status file offline, the bit disallows execution of the STI.

When set, this bit indicates that the STI timer has timed out and the STI subroutine is currently being executed. This bit is cleared upon completion of the STI routine, ladder program, or REM Run or Test mode.

NA

MicroLogix 1000 Controller Status File

Address

S:2/5

S:2/6

S:2/7

S:2/8 to

S:2/13

Bit

Incoming

Command

Pending Bit

Message

Reply

Pending Bit

Outgoing

Message

Command

Pending Bit

Reserved

Classification

Status

Status

Status

NA

Description

This bit is set when the processor determines that another node on the network has requested information or supplied a command to it. This bit can be set at any time. This bit is cleared when the processor services the request (or command).

This bit is set when another node on the network has supplied the information you requested in the MSG instruction of your processor. This bit is cleared when the processor stores the information and updates your MSG instruction.

This bit is set when one or more messages in your program are enabled and waiting, but no message is being transmitted at the time. As soon as transmission of a message begins, the bit is cleared. After transmission, the bit is set again if there are further messages waiting. It remains cleared if there are no further messages waiting.

NA

Valid for Series C discrete only.

A–9

A–10

Address

S:2/14

S:2/15

Bit

Math Overflow

Selection

Classification

Dynamic

Configuration

Description

Set this bit when you intend to use 32-bit addition and subtraction. When S:2/14 is set, and the result of an ADD, SUB, MUL, or DIV instruction cannot be represented in the destination address (underflow or overflow),

• the overflow bit S:0/1 is set,

• the overflow trap bit S:5/0 is set,

• and the destination address contains the unsigned truncated least significant 16 bits of the result.

The default condition of S:2/14 is reset (0).

When S:2/14 is reset, and the result of an

ADD, SUB, MUL, or DIV instruction cannot be represented in the destination address

(underflow or overflow),

• the overflow bit S:0/1 is set,

• the overflow trap bit S:5/0 is set,

• and the destination address contains

32767 if the result is positive or – 32768 if the result is negative.

Note, the status of bit S:2/14 has no effect on the DDV instruction. Also, it has no effect on the math register content when using MUL and

DIV instructions.

To program this feature, use the Data Monitor function to set or clear this bit. To provide protection from inadvertent data monitor alteration of your selection, program an unconditional OTL instruction at address

S:2/14 to ensure the new math overflow operation. Program an unconditional OTU instruction at address S:2/14 to ensure the original math overflow operation.

Reserved

MicroLogix 1000 Controller Status File

Address

S:3L

S:3H

Bit

Current Scan

Time

Watchdog

Scan Time

Classification

Status

Dynamic

Configuration

Description

The value of this byte tells you how much time elapses in a program cycle. A program cycle includes:

• scanning the ladder program,

• housekeeping,

• scanning the I/O,

• servicing of the communication channel.

The byte value is zeroed by the controller each scan, immediately preceding the execution of rung 0 of program file 2 (main program file).

The byte is incremented every 10 ms thereafter, and indicates, in 10 ms increments, the amount of time elapsed in each scan. If this value ever equals the value in S:3H

Watchdog, a user watchdog major error will be declared (code 0022).

The resolution of the scan time value is

+

0 to

90 ms (–10 ms). Example: The value 9 indicates that 80–90 ms has elapsed since the start of the program cycle.

This byte value contains the number of 10 ms ticks allowed to occur during a program cycle.

The default value is 10 (100 ms), but you can increase this to 255 (2.55 seconds) or decrease it to 1, as your application requires.

If the program scan S:3L value equals the watchdog value, a watchdog major error will be declared (code 0022).

A–11

A–12

Address

S:4

S:5

S:5/0

Bit

Timebase

Minor Error

Bits

Overflow Trap

Classification

Status

Dynamic

Configuration

Description

All 16 bits of this word are assessed by the controller. The value of this word is zeroed upon power up in the REM Run mode or entry into the REM Run or REM Test mode. It is incremented every 10 ms thereafter.

Application note: You can write any value to

S:4. It will begin incrementing from this value.

You can use any individual bit of this word in your user program as a 50% duty cycle clock bit. Clock rates for S:4/0 to S:4/15 are:

20, 40, 80, 160, 320, 640, 1280, 2560, 5120,

10240, 20480, 40960, 81920, 163840, 327680, and 655360 ms.

The application using the bit must be evaluated at a rate more than two times faster than the clock rate of the bit. In the example below, bit

S:4/3 toggles every 80 ms, producing a 160 ms clock rate. To maintain accuracy of this bit in your application, the instruction using bit S:4/3

(O:1/0 in this case) must be evaluated at least once every 79.999 ms.

160 ms

S:4

] [

3

O:1

( )

0

S:4/3 cycles in 160 ms

Both S:4/3 and

Output O:1/0 toggle every 80 ms. O:1/0 must be evaluated at least once every

79.999 ms.

The bits of this word are set by the controller to indicate that a minor error has occurred in your ladder program. Minor errors, bits 0 to 7, revert to major error 0020H if any bit is detected as being set at the end of the scan.

These bits are automatically cleared on a power cycle.

When this bit is set by the controller, it indicates that a mathematical overflow has occurred in the ladder program. See S:0/1 for more information.

If this bit is ever set upon execution of the END or TND instruction, major error (0020) is declared. To avoid this type of major error from occurring, examine the state of this bit following a math instruction (ADD, SUB, MUL,

DIV, DDV, NEG, SCL, TOD, or FRD), take appropriate action, and then clear bit S:5/0 using an OTU instruction with S:5/0.

MicroLogix 1000 Controller Status File

Address

S:5/1

S:5/2

S:5/3

S:5/4 to

S:5/7

S:5/8

S:5/9

S:5/10

S:5/11 to

S:5/12

S:5/13

Bit

Reserved

Control

Register Error

Classification

Dynamic

Configuration

Description

The LFU, LFL, FFU, FFL, BSL, BSR, SQO,

SQC, and SQL instructions are capable of generating this error. When bit S:5/2 is set, it indicates that the error bit of a control word used by the instruction has been set.

If this bit is ever set upon execution of the END or TND instruction, major error (0020) is declared. To avoid this type of major error from occurring, examine the state of this bit following a control register instruction, take appropriate action, and then clear bit S:5/2 using an OTU instruction with S:5/2.

Major Error

Detected

While

Executing user–fault routine

Reserved

Retentive

Data Lost

Dynamic

Configuration

Status

When set, the major error code (S:6) represents the major error that occurred while processing the fault routine due to another major error.

This bit is set whenever retentive data is lost.

This bit remains set until you clear it. While set, this bit causes the controller to fault prior to the first true scan of the program.

Reserved

STI Lost Status This bit is set whenever the STI timer expires while the STI routine is either executing or disabled and the pending bit (s:2/0) is already set.

Reserved

Input Filter

Selection

Modified

Status This bit is set whenever the discrete input filter selection in the controller is made compatible with the hardware.

A–13

A–14

Address

S:5/14 to

S:5/15

S:6

Bit

Reserved

Major Error

Code

Classification

Status

Description

A hexadecimal code is entered in this word by the controller when a major error is declared.

Refer to S:1/13. The code defines the type of fault, as indicated on the following pages. This word is not cleared by the controller.

Error codes are presented, stored, and displayed in a hexadecimal format.

If you enter a fault code as a parameter in an instruction in your ladder program, you must convert the code to decimal.

Application note: You can declare your own application-specific major fault by writing a unique value to S:6 and then setting bit S:1/13.

Interrogate the value of S:6 in the user–fault routine to determine the type of fault that occurred.

Fault Classifications: Faults are classified as

Non-User, Non-Recoverable, and Recoverable.

Error code descriptions and classifications are listed on the following pages. Categories are:

• powerup errors

• going–to–run errors

• run errors

• download errors

Each fault is classified as one of the following:

Non–User — A fault caused by various conditions that cease ladder program execution. The user-fault routine is not run when this fault occurs.

Non–Recoverable — A fault caused by the user that cannot be recovered from.

The user-fault routine is run when this fault occurs. However, the fault cannot be cleared.

Recoverable — A fault caused by the user that can be recovered from in the user–fault routine by resetting major error halted bit (S:1/13). The user-fault routine is run when this fault occurs.

MicroLogix 1000 Controller Status File

Address

S:6

Error

Code

(Hex)

0001

0002

0003

0008

0009

Powerup Errors

The default program was loaded.

Unexpected reset occurred.

EEPROM memory is corrupt.

A fatal internal software error occurred.

A fatal internal hardware error occurred.

Fault Classification

User

Non-User

Non-

Recoverable

Recoverable

X

X

X

X

X

Fault Classification

Address

S:6

Error

Code

(Hex)

0005

0010

0016

User

Going–to–Run (GTR)

Errors

Retentive data is lost.

The downloaded program is not a controller program.

Startup protection after power loss, S:1/9 is set. The user must check for a retentive data lost condition if the user–fault routine was executed with startup protection.

Non-User

Non-

Recoverable

Recoverable

X

X

X

Going–to–Run errors occur when the controller is going from any mode to REM Run mode or from any non–Run mode (PRG, SUS) to Test mode.

A–15

A–16

Address

S:6

Error

Code

(Hex)

0004

0020

0022

0024

0025

0027

002A

002B

0030

0031

0032

0033

0034

0035

0037

0038

Run Errors

A runtime memory integrity error occurred.

A minor error at the end of the scan. Refer to S:5.

The watchdog timer expired.

Refer to S:3H.

Invalid STI interrupt setpoint.

Refer to S:30.

There are excessive JSRs in the STI subroutine (file 5).

There are excessive JSRs in the fault subroutine (file 3).

The indexed address is too large for the file.

There are excessive JSRs in the high-speed counter subroutine (file 4).

The subroutine nesting exceeds a limit of 8 (file 2).

An unsupported instruction was detected.

An SQO/SQC instruction crossed data file boundaries.

The LFU, LFL, FFU, FFL,

BSL, or BSR instruction crossed data file boundaries.

A negative value for a timer accumulator or preset value was detected.

An illegal instruction (TND) occurred in the interrupt file.

Invalid presets were loaded to the high-speed counter.

A RET instruction was detected in program file 2.

Fault Classification

User

Non-User

Non-

Recoverable

Recoverable

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

MicroLogix 1000 Controller Status File

Fault Classification

User

Address

Error

Code

(Hex)

0040

Run Errors

S:6

An output verify write occurred.

0041

Extra output bit(s) turned on.

Valid for Series A–C discrete only.

Non-User

Non-

Recoverable

Recoverable

X

X

Address

S:6

Error

Code

(Hex)

0018

Download Errors

The user program is incompatible with the operating system.

Fault Classification

User

Non-User

Non-

Recoverable

Recoverable

X

A–17

A–18

Address

S:7

S:8 to S:12

S:13 and

S:14

S:15L

Bit

Suspend

Code

Reserved

Math

Register

DF1 Node

Address

Classification

Status

Description

When a non-zero value appears in S:7, it indicates that the SUS instruction identified by this value has been evaluated as true, and the

Suspend Idle mode is in effect. This pinpoints the conditions in the application that caused the

Suspend Idle mode. This value is not cleared by the controller.

Use the SUS instruction with startup troubleshooting, or as runtime diagnostics for detection of system errors.

Status

Status

Use this double register to produce 32–bit signed divide and multiply operations, precision divide or double divide operations, and 5–digit BCD conversions.

These two words are used in conjunction with the

MUL, DIV, DDV, FRD, and TOD math instructions. The math register value is assessed upon execution of the instruction and remains valid until the next MUL, DIV, DDV, FRD, or TOD instruction is executed in the user program.

An explanation of how the math register operates is included with the instruction definitions.

If you store 32-bit signed data values, you must manage this data type without the aid of an assigned 32-bit data type. For example, combine

B3:0 and B3:1 to create a 32-bit signed data value. We recommend that you start all 32-bit values on an even or odd word boundary for ease of application and viewing. Also, we recommend that you design, document, and view the contents of 32-bit signed data in either the hexadecimal or binary radix.

When an STI, high-speed counter, or Fault

Routine interrupts normal execution of your program, the original value of the math register is restored when execution resumes.

This byte value contains the node address of your processor on the DF1 link. It is used when executing Message (MSG) instructions over the

DF1 link. The default node address of a processor is 1. Valid node addresses are 0–254.

To change a processor node address you must use a programming device.

MicroLogix 1000 Controller Status File

Address

S:15H

S:16L

S:16H

S:17 to

S:21

S:22

Bit

DF1 Baud

Rate

DH-485

Node

Address

DH-485

Baud Rate

Reserved

Maximum

Observed

Scantime

Classification

Status

Status

Status

NA

Description

This byte value contains a code used to select the baud rate of the processor on the DF1 link.

The controller baud rate options are:

300

600

1200

2400

4800

9600 (default)

19200

38400

To change the baud rate from the default value you must use a programming device.

This byte value contains the node address of your processor on the DH-485 link. Each device on the DH-485 link must have a unique address between the decimal values 1–31. To change a processor node address, you must use a programming device.

This byte value contains the baud rate of the processor on the DH-485 link.

The controller baud rate options are:

9600

19200 (default)

To change the baud rate from the default value, you must use a programming device.

NA

Dynamic This word indicates the maximum observed interval between consecutive program cycles.

This value indicates, in 10 ms increments, the time elapsed in the longest program cycle of the controller. Refer to S:3L for more information regarding the program cycle. The controller compares each last scan value to the value contained in S:22. If the controller determines that the last scan value is larger than the value stored at S:22, the last scan value is written to

S:22.

Resolution of the maximum observed scan time value is

+

0 to

10 ms. For example, the value 9 indicates that 80–90 ms was observed as the longest program cycle.

Interrogate this value using the Data Monitor function if you need to determine or verify the longest scan time of your program.

A–19

A–20

Address

S:23

S:24

S:25 to

S:29

S:30

Bit

Reserved

Index

Classification

Status

Description

This word indicates the element offset used in indexed addressing.

When an STI, high-speed counter, or Fault

Routine interrupts normal execution of your program, the original value of this register is restored when execution resumes.

Reserved

STI

Setpoint

Dynamic

Configuration

You enter the timebase to be used in the selectable timed interrupt (STI). The time can range from 10 to 2550 ms. (This is in 10ms increments, so valid values are from 0–255.)

Your STI routine executes per the value you enter. Write a zero value to disable the STI.

To provide protection from inadvertent Data

Monitor alteration of your selection, program an unconditional MOV instruction containing the setpoint value of your STI to S:30, or program a

CLR instruction at S:30 to prevent STI operation.

If the STI is initiated while in the REM Run mode by loading the status registers, the interrupt starts timing from the end of the program scan in which the status registers were loaded.

S:31 to

S:32

Reserved

SLC Status File

B

SLC Status File

This appendix lists the:

SLC processor status file overview

• status file detailed word/bit descriptions

This appendix discusses the status file functions of the Fixed, SLC 5/01, SLC 5/02,

SLC 5/03, SLC 5/04 and SLC 5/05 processors. The processors function similarly, but the higher numbered processors utilize more features. The tables in this appendix indicate which functions are supported by each processor.

The appendix starts with an overview listing of the status file. A more detailed description of each status word follows. Use the overview list to find the page number of the detailed description.

B–1

Status File Overview

Note

The status file lets you monitor how your operating system works and lets you direct how you want it to work. This is done by using the status file to set up interrupts, load memory module programs, and monitor both hardware and software faults.

Do not write to status file data unless the word or bit is listed as dynamic/static configuration in the descriptions that follow. If you intend writing to status file data, it is imperative that you first understand the function fully.

The status file S: contains the following words:

Word

S:0

S:1L

S:1H

S:2

S:3L

S:3H

S:4

S:5

S:6

S:7, S:8

S:9

S:10

S:11, S;12

S:13, S:14

S:15L

S:15H

S:16, S:17

S:18, S:19

S:20, S:21

S:22

S:23

Function

Arithmetic and Scan Status Flags

Processor Mode Status/Control

Processor Mode Status/Control

Processor Alternate Mode Status/Control

Current Scan Time

Watchdog Scan Time

Free Running Clock

Minor Error Bits

Major Error Fault Code

Suspend Code/Suspend File

Channel 1 Active Nodes (SLC 5/03)

Unused (SLC 5/04)

Ethernet Daughterboard Firmware Series

(SLC 5/05)

Channel 1 Active Nodes (SLC 5/03)

Unused (SLC 5/04)

Ethernet Daughterboard Firmware Revision

(SLC 5/05)

I/O Slot Enables

Math Register

Channel 1 DH-485 Node Address (SLC 5/03)

Channel 1 DH+ Node Address (SLC 5/04)

Ethernet Daughterboard Fault Code

(SLC 5/05)

Channel 1 DH-485 Baud Rate (SLC 5/03)

Channel 1 DH+ Baud Rate (SLC 5/04)

Ethernet Daughterboard Fault Code

(SLC 5/05)

Word Single Step Rung/File

Single Step Breakpoint Rung/File

Word Fault Powerdown Rung/File

Maximum Observed Scan Time

Average Scan Time

Applies To all processors

B–37

B–37

B–37

B–38

B–39

B–40

B–41

B–42

B–43

B–44

B–44

Page

B–5

B–6

B–6

B–12

B–18

B–19

B–20

B–21

B–24

B–36

B–2

SLC Status File

Word

S:24

S:25, S:26

S:27, S28

S:29

S:30

S:31

S:32

S:33

Function

Index Register

I/O Interrupt Pending

I/O Interrupt Enabled

User Fault Routine File Number

Selectable Timed Interrupt Set Point

Selectable Timed Interrupt File Number

I/O Interrupt Executing

Extended Processor Status and Control

S:34

S:35

S:36

S:37

S:38

S:39

S:40

S:41

S:42

S:43

S:44

S:45

Processor Extended Mode Status/Control

(SLC 5/04 and higher)

Last 1 ms Scan Time

Extended Minor Error Bits Reserved

Clock/Calendar Year

Clock/Calendar Month

Clock/Calendar Day

Clock/Calendar Hours

Clock/Calendar Minutes

Clock/Calendar Seconds

Selectable Timed Interrupt Time

(SLC 5/03 and higher)

I/O Event Interrupt Time (SLC 5/03 and higher)

Discrete Input Interrupt Time

(SLC 5/03 and higher)

Discrete Input Interrupt File Number

Discrete Input Interrupt Input Slot

Discrete Input Interrupt Bit Mask

Discrete Input Interrupt Compare Value

S:46

S:47

S:48

S:49

S:50

S:51

Discrete Input Interrupt Down Count

Discrete Input Interrupt Return Mask

S:52

S:53L

Discrete Input Interrupt Accumulator

Day-of-Week (SLC 5/03 OS302 Series B and higher, SLC 5/04 OS401 Series B and higher, and SLC 5/05)

S:53H and S:54 Reserved

S:55

S:56

S:57

S:58

S:59

Last DII ISR Scan Time

Maximum DII ISR Scan Time

Operating System Catalog Number

Operating System Series

Operating System FRN

Applies To

B–61

B–61

B–61

B–62

B–62

B–62

B–62

B–58

B–58

B–58

B–58

B–59

B–59

B–60

B–60

B–61

B–61

B–54

B–56

B–56

B–57

B–57

B–57

B–58

B–58

B–58

Page

B–45

B–45

B–46

B–47

B–47

B–48

B–48

B–48

B–3

B–4

Word

S:60

S:61

S:62

S:63

S:64

S:65

S:66

S:67 to S:82

S:83 to S:86

S:87 to S:98

S:99

S:100 to S:163

Function

Processor Catalog Number

Processor Series

Processor Revision

User Program Type

User Program Functionality Index

User RAM Size

Flash EEPROM Size

Channel 0 Active Node Table

Channel 1 Active Node Table

Reserved

Global Status Word

Global Status File

Applies To Page

B–62

B–62

B–62

B–62

B–63

B–63

B–63

B–63

B–63

B–63

B–64

B–64

SLC Status File

Status File Details

Conventions Used in the Displays

The following tables describe the status file functions, beginning at address S:0 and ending at address S:163. A bullet (

) indicates that the function applies to the specified processor.

The following classifications are used:

Status – Use these words, bytes, or bits to monitor processor options or processor status information. The information is seldom written to the user program or programming device (unless you want to reset or clear a function such as a minor error bit).

Dynamic Configuration – Use these words, bytes, or bits to select processor options while in the RUN mode.

Static Configuration – Use these words, bytes, or bits to select processor options prior to entering the RUN mode. Note that some options must be selected while in the offline program mode, prior to restoring the user program.

Address Classification

S:0

Description

Fixed

5/01

5/02 5/03 5/04 5/05

• • • •

S:0/0

S:0/1

Status

Status

Arithmetic and Scan Status Flags

The arithmetic flags are assessed by the processor following the execution of any math, logical, or move instruction. The state of these bits remains in effect until the next math, logical, or move instruction in the program is executed.

Carry Bit

This bit is set by the processor if a mathematical carry or borrow is generated. Otherwise the bit remains cleared.

This bit is assessed as if a function of unsigned math.

When a STI, I/O Slot, or Fault Routine interrupts normal execution of your program, the original value of S:0/0 is restored when execution resumes.

When a DII interrupts normal execution of your program, the original value of S:0/0 is restored when execution resumes.

Overflow Bit

This bit is set by the processor when the result of a mathematical operation does not fit in its destination.

Otherwise the bit remains cleared. Whenever this bit is set, the overflow trap bit S:5/0 is also set. Refer to S:5/0.

When a STI, I/O Slot, or Fault Routine interrupts normal execution of your program, the original value of S:0/1 is restored when execution resumes.

• • • •

• • • •

• • •

• • • •

• • • •

B–5

Address

S:0/1 continued

Classification

S:0/2

S:0/3

Status

Status

NA

Description

When a DII interrupts normal execution of your program, the original value of S:0/1 is restored when execution resumes.

Zero Bit

This bit is set by the processor when the result of a math, logical, or move instruction is zero. Otherwise the bit remains cleared.

When a STI, I/O Slot, or Fault Routine interrupts normal execution of your program, the original value of S:0/2 is restored when execution resumes.

When a DII interrupts normal execution of your program, the original value of S:0/2 is restored when execution resumes.

Sign Bit

This bit is set by the processor when the result of a math, logical, or move instruction is negative. Otherwise the bit remains cleared.

When a STI, I/O Slot, or Fault Routine interrupts normal execution of your program, the original value of S:0/3 is restored when execution resumes.

When a DII interrupts normal execution of your program, the original value of S:0/3 is restored when execution resumes.

Reserved S:0/4 to

S:0/15

S:1/0 to

S:1/4

Status Processor Mode Status/Control

Bits 0-4 function as follows:

0 0000 = (0) Remote Download in progress

0 0001 = (1) Remote Program mode (the fault mode exists when bit S:1/13 is set along with mode 0 0001)

0 0011 = (3) Suspend Idle (operation halted by SUS instruction execution) fault mode exists when bit S:1/13 is set along with mode 0

0011

0 0110 = (6) Remote Run mode

0 0111 = (7) Remote Test continuous mode

0 1000 = (8) Remote Test single scan mode

0 1001 = (9) Remote Test single step (step until)

Note: All modes in the fixed, SLC 5/01, and SLC 5/02

processors are considered as remote because they do not have a keyswitch.

Fixed

5/01

5/02 5/03 5/04 5/05

• • •

B–6

SLC Status File

Address

S:1/0 to

S:1/4 continued

Classification

S:1/5

S:1/6

S:1/7

S:1/8

Status

Status

Status

Dynamic

Config

Description

1 0000 = (16) Download in progress

(keyswitch=PROGram)

1 0001 = (17) PROGram mode – the fault mode exists when bit S:1/13 is set along with mode 1

0001

1 1011 = (27) Suspend Idle – the fault mode exists when bit S:1/13 is set along with mode 1 1011

(keyswitch=RUN)

1 1110 = (30) RUN – the fault mode exists when bit S:1/13 is set along with mode 1 1110 (keyswitch =

RUN)

All other values for bits 0-4 are reserved.

Forces Enabled Bit

This bit is set by the processor if you have enabled forces in a ladder program. Otherwise, the bit remains cleared.

The processor Forced I/O LED is on continuously when forces are enabled.

Forces Installed Bit

This bit is set by the processor if you have installed forces in a ladder program. The forces may or may not be enabled. Otherwise the bit remains cleared. The processor Forced I/O LED flashes when forces are installed, but not enabled.

Communications Active Bit (Channel 1)

This bit is set by the processor when at least one other node is present on the network attached to channel 1.

Otherwise, the bit remains cleared. When the node is active, it is a recognized participant in a DH-485 or DH+ token-passing network. For Ethernet communications, this bit is only an indication that the Ethernet daughter board is functioning properly, not necessarily that there are any other active Ethernet nodes, or that channel 1 is connected to an Ethernet network.

Fault Override at Powerup Bit

When set, this bit causes the processor to clear the Major

Error Halted bit S:1/13 and Minor error bits S:5/0 to S:5/7 on power up; if the processor had previously been in the

REM Run mode and had faulted. The processor then attempts to enter the REM Run mode. When this bit remains cleared (default value), the processor remains in a major fault state at power up. To program this feature, set this bit using the Data Monitor function.

Fixed

5/01

5/02 5/03 5/04 5/05

• • •

B–7

Address

S:1/9

S:1/10

Classification Description

Dynamic

Config

Startup Protection Fault Bit

When this bit is set and power is cycled while the processor is in the REM Run mode, the processor executes your fault routine prior to the execution of the first scan of your program. You then have the option of clearing the Major Error Halted bit S:1/13 to resume operation in the REM Run mode. If your fault routine does not reset bit S:1/13, the fault mode results.

To program this feature, use the Data Monitor function, then program your fault routine logic accordingly. When executing the startup protection fault routine, S:6 (major error fault code) will contain the value 0016H.

Static Config Load Memory Module on Memory Error Bit

You can use this bit to transfer a memory module program to the processor in the event that a processor memory error is detected at power-up. A memory error means the processor cannot run the program in the RAM because the program has been corrupted, as detected by a parity or checksum error. This type of error is caused by battery or capacitor drain, noise, or a power problem.

You must set S:1/10 in the status file of the program in the memory module. When a memory module is installed that has bit S:1/10 set, a processor memory error detected at power-up causes the memory module program to be transferred to the processor, and the REM

Run mode to be entered.

When S:1/10 is cleared in the memory module, the processor remains in a major fault condition if a memory error is detected on power-up, regardless if a memory module exists.

When S:1/10 is set in the status file of the user program in RAM memory, the memory module must be installed at all times to enter the REM Run or REM Test modes.

To program this feature, set this bit using the Data

Monitor function. Then store the program in the memory module.

Fixed

5/01

5/02 5/03 5/04 5/05

• • • •

• • • •

B–8

SLC Status File

Address

S:1/11

Classification Description

Static Config

Load Memory Module Always Bit

When this bit is set, you can overwrite a processor program with a memory module program by cycling processor power. A programming device is not required.

The processor mode after powerup is as follows for SLC

5/02 and higher processors:

Mode before

Powerdown

REM Test/Program

REM Run

Fault after REM

Test/Program

Fault after REM Run

REM Idle

REM Download

Mode after

Powerup

REM Program

REM Run

REM Program

REM Run

REM Program

REM Program

Mode before

Powerdown

Run

Program

Idle

Fault after Run

Fault after Program

Mode after Powerup

(same keyswitch position)

RUN

PROGram

RUN

RUN

PROGram

Note: All modes in the fixed, SLC 5/01, and SLC 5/02

processors are considered to be remote because they do not have a keyswitch.

The memory module you install in the processor must have status file bit S:1/11 set. Loading takes place if the master password and/or password in the processor and memory module match. Loading can also take place if the processor has neither a password nor master password.

When S:1/11 is also set in the status file of the user program in RAM, the memory module must be installed at all times to enter the REM Run or REM Test modes.

Fixed

5/01

5/02 5/03 5/04

• • •

5/05

• •

• •

!

The overwriting process, including data tables, is repeated each time you cycle power.

To program this feature, set this bit using the Data

Monitor function. Then store the program in the memory module.

You may choose not to overwrite data files on a per file basis.

• • •

B–9

Address

S:1/12

Classification Description

Static Config Load Memory Module and Run Bit

With this bit, you can overwrite a processor program with a memory module program by cycling processor power. A programming device is not required. The processor will attempt to enter the REM Run mode, regardless of what mode was in effect before cycling power:

Mode before Powerdown

REM Test/Rem Program

REM Run/Rem Fault

REM Idle/Rem Download

Mode after Powerup

REM Run

REM Run

REM Run

Fixed

5/01

5/02 5/03 5/04 5/05

• • • •

• • • •

• • •

Mode before

Powerdown

Run

Idle

Program/Download

Fault after Run

Fault after Program

Mode after Powerup

(same keyswitch position)

RUN

Run

PROGram

RUN

PROGram

Note: All modes in the fixed, SLC 5/01, and SLC 5/02

processors are considered to be remote because they do not have a keyswitch.

The memory module you install in the processor must have status file bit S:1/12 set. Loading takes place if the master password and/or password in the processor and memory module match. Loading can also take place if the processor has neither a password nor master password.

When S:1/12 is set in the status file of the user program in RAM, it does not require the presence of the memory module to enter the REM Run or REM Test mode.

Application example: Set both S:1/11 and S:1/12 to autoload and run every power cycle, and require the presence of the memory module to enter the REM Run or

REM Test modes.

!

If you leave the memory module installed, the overwriting process, including data tables, is repeated each time you cycle power. The mode is changed to REM Run each and every power cycle.

To program this feature, use the Data Monitor function.

Then store the program in the memory module. This feature is particularly useful when you are troubleshooting hardware failures with “spares”

(replacement modules). Use this feature to facilitate application logic upgrades in the field without a programming device.

You may choose not to overwrite data files on a per file basis.

• • • •

• • •

B–10

SLC Status File

Address

S:1/13

Classification

Dynamic

Config

Description

Major Error Halted Bit

This bit is set by the processor any time a major error is encountered. The processor enters a fault condition.

Word S:6, Fault Code will contain a code which can be used to diagnose the fault condition. Any time bit S:1/13 is set, the processor:

• either places all outputs in a safe state and energizes the fault LED, or

• enters the user fault routine with outputs active, allowing the fault routine ladder logic to attempt recovery from the fault condition. If your fault routine determines that recovery is required, clear S:1/13 using ladder logic prior to exiting the fault routine. If the fault routine ladder logic does not understand the fault code, or if the routine determines that it is not desirable to continue operation, exit the fault routine with bit S:1/13 set. The outputs will be placed in a safe state and the fault LED will be energized.

When you clear bit S:1/13 using a programming device, the processor mode changes from fault to either Remote

Program, or Remote Idle Suspend depending on the previous mode of the processor. You can move a value to

S:6, then set S:1/13 in your ladder program to generate an application specific Major Error.

Note: Once a major fault state exists, you must correct

the condition causing the fault, and you must also clear this bit in order for the processor to accept a mode change attempt (into REM Program, REM Run, or REM

Test). Also, clear S:6 to avoid the confusion of having an error code but no fault condition.

Note: Do not re-use error codes that are defined in the

SLC error code list in chapter 15 as application specific

error codes. Instead, create your own unique codes. This prevents you from confusing application errors with system errors. We recommend using error codes FFOO to FFOF to indicate application specific major errors.

When you clear bit S:1/13 using a programming device, the processor mode changes from fault to either

Program, Run, or Idle Suspend depending on the previous mode of the processor. You can move a value to

S:6, then set S:1/13 in your ladder program to generate an application specific major error.

!

If you clear this bit with the keyswitch in RUN, the processor immediately enters the RUN mode.

You can clear faults S:1/13 and S:6 by cycling the keyswitch to PROGram and then to RUN.

Fixed

5/01

5/02 5/03 5/04 5/05

• • • •

• • • •

• • • •

• • •

B–11

Address

S:1/14

Classification

Status

S:1/15

S:2/0

Status

Status

Description

Access Denied Bit (OEM Lock)

You can allow or deny future access to a processor file.

Set this bit to deny access. This indicates that a programming device must have a matching copy of the processor file in its memory in order to monitor the ladder program. A programming device that does not have a matching copy of the processor file is denied access.

To program this feature, select “Future Access Disallow” when saving your program. To provide protection from inadvertent data monitor alteration of your selection, program an unconditional OTL instruction at address

S:1/14, to deny future access. Program an unconditional

OTU instruction at address S:1/14 to allow future access.

When this bit is cleared, it indicates that any compatible programming device can access the ladder program

(provided that password conditions are satisfied).

When access is denied, the programming device (APS or

HHT) may not access the ladder program. Functions such as change mode, clear memory, restore program, and transfer memory module are allowed regardless of this selection. A device such as the DTAM is not affected by this function.

First Pass Bit

Use this bit to initialize your program as the application requires. When this bit is set by the processor, it indicates that the first scan of the user program is in progress

(following power up in the RUN mode or entry into a REM

Run or REM Test mode). The processor clears this bit following the first scan.

When this bit is cleared, it indicates that the program is not in the first scan of a REM Test or REM Run mode.

This bit is set during execution of the startup protection fault routine. Refer to S:1/9 for more information.

STI (Selectable Timed Interrupt) Pending Bit

When set, this bit indicates that the STI timer has timed out and the STI routine is waiting to be executed. This bit is cleared upon starting of the STI routine, power up, exit of the REM Run mode, or execution of a true STS instruction.

The STI pending bit will not be set if the STI timer expires while executing the fault routine.

This bit is set if the STI timer expires while executing the

DII subroutine or fault routine.

Fixed

5/01

5/02 5/03 5/04 5/05

• • • •

• •

B–12

SLC Status File

Address

S:2/1

S:2/2

S:2/3

S:2/4

Classification Description

Static Config STI (Selectable Timed Interrupt) Enabled Bit

This bit is set in its default condition, or when set by the

STE or STS instruction. If set, it allows execution of the

STI if the STI file (S:31) and STI setpoint (S:30) are non-zero. If clear, when an interrupt occurs, the STI subroutine does not execute and the STI Pending bit is set. The STI Timer continues to run when disabled. The

STD instruction clears this bit.

Dynamic

Config

Use the Data Monitor function to set and clear this bit, or address this bit with your ladder logic program. This bit is set in its default condition, or when set by the STE or STS instruction. If set, it allows execution of the STI if the STI file (word 31) and STI rate (word 30) are non-zero. If clear, the STI subroutine does not execute and the STI pending bit is set. The STI timer continues to run. The

STD instruction clears this bit.

Status STI (Selectable Timed Interrupt) Executing Bit

When set, this bit indicates that the STI timer has timed out and the STI subroutine is currently being executed.

This bit is cleared upon completion of the STI routine, powerup, or REM Run mode entry.

Application example: You can examine this bit in your fault routine to determine if your STI was executing when the fault occurred.

Static Config Index Addressing File Range Bit

When clear, the index register can only index within the same data file of the specified base address. When set, the index register can index anywhere from data file B3:0 to the end of the last declared data file. This bit is selected at the time you save your program.

The SLC 5/03 and higher processors allow you to index from 0:0 to the last data file.

Note: Change this bit while in the offline mode only.

Save the program after changing the bit.

Static Config Saved with Single Step Test Enabled Bit

When clear, the Single Step Test mode function is not available. Clear also indicates that debug registers S:16 through S:21 are inoperative. When set, the program can operate in the Single Step Test mode. See descriptions of

S:16 through S:21. When set, your program requires

0.375 instruction words (3 bytes) per rung of additional memory. This bit is selected at the time you save your program.

Note: This bit is not applicable to the SLC 5/03 and

higher processors since its functionality is always available and requires no special compile time selection.

Fixed

5/01

5/02 5/03 5/04 5/05

• • • •

B–13

Address

S:2/5

Classification

Status

S:2/6

S:2/7

S:2/8

Status

Status

Dynamic

Config

Description

Incoming Command Pending Bit (Channel 1)

This bit is set when the processor determines that another node on the network has requested information or supplied a command to it. This bit can be set at any time. This bit is cleared when the processor services the request (or command).

Use this bit as a condition of an SVC instruction to enhance the communication capability of your processor.

Message Reply Pending Bit (Channel 1)

This bit is set when another node on the network has supplied the information you requested in the MSG instruction of your processor. This bit is cleared when the processor stores the information and updates your MSG instruction.

Use this bit as a condition of an SVC instruction to enhance the communication capability of your processor.

Outgoing Message Command Pending Bit (Channel 1)

Th