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Technical Data

MPC8280EC

Rev. 1.0, 2/2004

MPC8280

PowerQUICC II™ Family

Hardware Specifications

Freescale Semiconductor, Inc.

This document contains detailed information about power considerations, DC/AC electrical characteristics, and AC timing specifications for .13µm (HiP7) members of the

PowerQUICC II™ family of integrated communications processors—the MPC8280, the

MPC8275, and the MPC8270 (collectively called 'the MPC8280' throughout this document ).

The following topics are addressed:

Topic

Section 1, “Overview”

Section 2, “Operating Conditions”

Section 3, “DC Electrical Characteristics”

Page

2

7

8

Section 4, “Thermal Characteristics”

Section 5, “Power Dissipation”

Section 6, “AC Electrical Characteristics”

Section 7, “Clock Configuration Modes”

Section 8, “Pinout”

Section 9, “Package Description”

Section 10, “Ordering Information”

Section 11, “Document Revision History”

11

13

13

22

40

70

73

73

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Overview

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1 Overview

Table 1 shows the functionality supported by each device in the MPC8280 family.

Table 1. MPC8280 PowerQUICC II Family Functionality

Devices

Functionality

Serial communications controllers (SCCs)

QUICC multi-channel controller (QMC)

Fast communication controllers (FCCs)

I-Cache (Kbyte)

D-Cache (Kbyte)

Ethernet (10/100)

UTOPIA II Ports

Multi-channel controllers (MCCs)

PCI bridge

Transmission convergence (TC) layer

Inverse multiplexing for ATM (IMA)

Universal serial bus (USB) 2.0 full/low rate

Security engine (SEC)

1

Refer to Table 2.

MPC8270 MPC8275

Package

1

480 TBGA 516 PBGA 516 PBGA

16

3

0

1

4

3

16

Yes

1

16

3

0

1

4

3

16

Yes

1

16

3

2

1

4

3

16

Yes

1

Devices in the MPC8280 family are available in three packages—the standard ZU package and the alternate

VR or ZQ packages—as shown in Table 2. Note that throughout this document references to the MPC8280

and the MPC8270 are inclusive of VR and ZQ package devices unless otherwise specified. For more information on VR and ZQ packages, contact your Motorola sales office. For package ordering information,

refer to Section 10, “Ordering Information.”

Table 2. HiP7 PowerQUICC II Device Packages

Code

(Package)

Device

ZU

(480 TBGA—Leaded)

MPC8280

MPC8270

VR

(516 PBGA—Lead free)

MPC8275VR

MPC8270VR

ZQ

(516 PBGA—Lead spheres)

MPC8275ZQ

MPC8270ZQ

MPC8280

480 TBGA

16

3

2

2

4

3

16

Yes

Yes

Yes

1

2

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Figure 1 shows the block diagram. Shaded portions are device-specific; refer to the notes below.

Overview

16 Kbytes

I-Cache

I-MMU

G2_LE Core

16 Kbytes

D-Cache

D-MMU

Timers

Parallel I/O

Baud Rate

Generators

Communication Processor Module (CPM)

Interrupt

Controller

32 KB

Instruction

RAM

32 KB

Data

RAM

32-bit RISC Microcontroller and Program ROM

IMA

1

Microcode

Serial

DMAs

4 Virtual

IDMAs

System Interface Unit

(SIU)

Bus Interface Unit

60x-to-PCI

Bridge

60x-to-Local

Bridge

Memory Controller

Clock Counter

System Functions

60x Bus

PCI Bus

32 bits, up to 66 MHz or

Local Bus

32 bits, up to 100 MHz

MCC1

1

MCC2 FCC1 FCC2 FCC3 SCC1 SCC2 SCC3 SCC4/ SMC1 SMC2

USB

TC Layer Hardware

1

Time Slot Assigner

Serial Interface

2

SPI

I

2

C

8 TDM Ports

2

3 MII or RMII 2 UTOPIA

Ports Ports

3

Non-Multiplexed

I/O

Notes:

1

MPC8280 only (not on MPC8270, the VR package, nor the ZQ package)

2

MPC8280 has 2 serial interface (SI) blocks and 8 TDM ports. MPC8270 and the VR and ZQ packages have

only 1 SI block and 4 TDM ports (TDM2[A–D]).

3

MPC8280, MPC8275VR, MPC8275ZQ only (not on MPC8270, MPC8270VR, nor MPC8270ZQ)

Figure 1. MPC8280 Block Diagram

1.1

Features

The major features of the MPC8280 are as follows:

• Dual-issue integer (G2_LE) core

— A core version of the EC603e microprocessor

— System core microprocessor supporting frequencies of 166–450 MHz

— Separate 16-Kbyte data and instruction caches:

– Four-way set associative

– Physically addressed

– LRU replacement algorithm

— PowerPC™ architecture-compliant memory management unit (MMU)

— Common on-chip processor (COP) test interface

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Overview

— High-performance (SPEC95 benchmark at 450 MHz; 855 Dhrystones MIPS at 450 MHz)

— Supports bus snooping for data cache coherency

— Floating-point unit (FPU)

• Separate power supply for internal logic and for I/O

• Separate PLLs for G2_LE core and for the CPM

— G2_LE core and CPM can run at different frequencies for power/performance optimization

— Internal core/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 6:1, 7:1,

8:1 ratios

— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1, 8:1 ratios

• 64-bit data and 32-bit address 60x bus

— Bus supports multiple master designs

— Supports single- and four-beat burst transfers

— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

— Supports data parity or ECC and address parity

• 32-bit data and 18-bit address local bus

— Single-master bus, supports external slaves

— Eight-beat burst transfers

— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

• 60x-to-PCI bridge

— Programmable host bridge and agent

— 32-bit data bus, 66.67/83.3/100 MHz, 3.3 V

— Synchronous and asynchronous 60x and PCI clock modes

— All internal address space available to external PCI host

— DMA for memory block transfers

— PCI-to-60x address remapping

• PCI bridge

— PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz

— On-chip arbitration

— Support for PCI-to-60x-memory and 60x-memory-to-PCI streaming

— PCI host bridge or periphera l

capabilities

— Includes 4 DMA channels for the following transfers:

– PCI-to-60x to 60x-to-PCI

– 60x-to-PCI to PCI-to-60x

– PCI-to-60x to PCI-to-60x

– 60x-to-PCI to 60x-to-PCI

— Includes all of the configuration registers (which are automatically loaded from the EPROM and used to configure the MPC8280) required by the PCI standard as well as message and doorbell registers

— Supports the I

2

O standard

— Hot-swap friendly (supports the hot swap specification as defined by PICMG 2.1 R1.0 August

3, 1998)

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Overview

— Support for 66.67/83.33/100 MHz, 3.3 V specification

— 60x-PCI bus core logic that uses a buffer pool to allocate buffers for each port

— Uses the local bus signals, removing need for additional pins

• System interface unit (SIU)

— Clock synthesizer

— Reset controller

— Real-time clock (RTC) register

— Periodic interrupt timer

— Hardware bus monitor and software watchdog timer

— IEEE 1149.1 JTAG test access port

• 12-bank memory controller

— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user- definable peripherals

— Byte write enables and selectable parity generation

— 32-bit address decodes with programmable bank size

— Three user-programmable machines, general-purpose chip-select machine, and page-mode pipeline SDRAM machine

— Byte selects for 64-bus width (60x) and byte selects for 32-bus width (local)

— Dedicated interface logic for SDRAM

• CPU core can be disabled and the device can be used in slave mode to an external core

• Communications processor module (CPM)

— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support for communications protocols

— Interfaces to G2_LE core through an on-chip 32-Kbyte dual-port data RAM, an on-chip

32-Kbyte dual-port instruction RAM and DMA controller

— Serial DMA channels for receive and transmit on all serial channels

— Parallel I/O registers with open-drain and interrupt capability

— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers

— Three fast communications controllers supporting the following protocols:

– 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent interface (MII) or reduced media independent interface (RMII)

– ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5, AAL1,

AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 64 K external connections (no ATM support for the MPC8270)

– Transparent

– HDLC—Up to T3 rates (clear channel)

– FCC2 can also be connected to the TC layer (MPC8280 only)

— Two multichannel controllers (MCCs) (one MCC on the MPC8270)

– Each MCC handles 128 serial, full-duplex, 64-Kbps data channels. Each MCC can be split into four subgroups of 32 channels each.

– Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces up to four TDM interfaces per MCC

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Overview

— Four serial communications controllers (SCCs) identical to those on the MPC860, supporting the digital portions of the following protocols:

– Ethernet/IEEE 802.3 CDMA/CS

– HDLC/SDLC and HDLC bus

– Universal asynchronous receiver transmitter (UART)

– Synchronous UART

– Binary synchronous (BISYNC) communications

– Transparent

— Universal serial bus (USB) controller

– Supports USB 2.0 full/low rate compatible

– USB host mode

–Supports control, bulk, interrupt, and isochronous data transfers

–CRC16 generation and checking

–NRZI encoding/decoding with bit stuffing

–Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and data rate configuration). Note that low-speed operation requires an external hub.

–Flexible data buffers with multiple buffers per frame

–Supports local loopback mode for diagnostics (12 Mbps only)

– Supports USB slave mode

–Four independent endpoints support control, bulk, interrupt, and isochronous data transfers

–CRC16 generation and checking

–CRC5 checking

–NRZI encoding/decoding with bit stuffing

–12- or 1.5-Mbps data rate

–Flexible data buffers with multiple buffers per frame

–Automatic retransmission upon transmit error

— Two serial management controllers (SMCs), identical to those of the MPC860

– Provide management for BRI devices as general circuit interface (GCI) controllers in time- division-multiplexed (TDM) channels

– Transparent

– UART (low-speed operation)

— One serial peripheral interface identical to the MPC860 SPI

— One inter-integrated circuit (I

2

C) controller (identical to the MPC860 I

2

C controller)

– Microwire compatible

– Multiple-master, single-master, and slave modes

— Up to eight TDM interfaces (four on the MPC8270)

– Supports two groups of four TDM channels for a total of eight TDMs (one group of four on the MPC8270 and the MPC8275)

– 2,048 bytes of SI RAM

– Bit or byte resolution

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Operating Conditions

– Independent transmit and receive routing, frame synchronization

– Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN primary rate, Motorola interchip digital link (IDL), general circuit interface (GCI), and user-defined TDM serial interfaces

— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs,

SCCs, SMCs, and serial channels

— Four independent 16-bit timers that can be interconnected as two 32-bit timers

• Inverse multiplexing for ATM capabilities (IMA) (MPC8280 only).Supported by eight transfer transmission convergence (TC) layers between the TDMs and FCC2.

• Transmission convergence (TC) layer (MPC8280 only)

2 Operating Conditions

Table 3 shows the maximum electrical ratings.

Table 3. Absolute Maximum Ratings

1

Rating Symbol Value Unit

Core supply voltage

2

PLL supply voltage

2

I/O supply voltage

3

Input voltage

4

VDD

VCCSYN

VDDH

-0.3 – 2.25

-0.3 – 2.25

-0.3 – 4.0

V

V

V

VIN GND(-0.3) – 3.6

V

Junction temperature T j

120 ˚C

Storage temperature range T

STG

(-55) – (+150) ˚C

1

Absolute maximum ratings are stress ratings only; functional operation (see Table 4) at the maximums is not

guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage.

2

Caution:

VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on reset.

3

Caution:

VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec. VDDH should not exceed VDD/VCCSYN by more than 2.5 V during normal operation.

4

Caution:

VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.

Table 4 lists recommended operational voltage conditions.

Table 4. Recommended Operating Conditions

1

Rating Symbol Value Unit

Core supply voltage

PLL supply voltage

I/O supply voltage

VDD

VCCSYN

VDDH

1.45 – 1.60

1.45 – 1.60

3.135 – 3.465

V

V

V

Input voltage VIN GND (-0.3) – 3.465

V

Junction temperature (maximum) T j

105

2

˚C

Ambient temperature T

A

0–70

2

˚C

1

Caution:

These are the recommended and tested operating conditions. Proper operation outside of these conditions is not guaranteed.

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DC Electrical Characteristics

2

Note that for extended temperature parts the range is (-40)

TA

– 105

Tj

.

NOTE: Core, PLL, and I/O Supply Voltages

After power up sequence is complete, VDDH and VDD/VCCSYN must track each other and both voltages must vary in the same direction. When varying in the positive direction, VDDH may vary up to 5% from nominal or 3.3 + 0.165 = 3.465 V, in which case VDD/VCCSYN must also vary upward by 5% from nominal or 1.525 + 0.075 = 1.6 V. The same applies to the negative direction: VDDH may vary downward up to -5% from nominal or 3.3 –0.165 = 3.135 V, in which case VDD/VCCSYN must vary downward by-5% from nominal or 1.525 –0.075 = 1.45 V. A/C timing specification violation may occur during the time that voltage tracking is not correct.

This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (either GND or V

CC

).

Figure 2 shows the undershoot and overshoot voltage of the 60x and local bus memory interface of the

MPC8280. Note that in PCI mode the I/O interface is different.

V

IH

4 V

GV

DD

+ 5%

GV

DD

V

IL

GND

GND – 0.3 V

GND – 1.0 V

Not to exceed 10% of t

SDRAM_CLK

Figure 2. Overshoot/Undershoot Voltage

3 DC Electrical Characteristics

Table 5 shows DC electrical characteristics.

Table 5. DC Electrical Characteristics

1

Characteristic

Input high voltage— all inputs except TRST and PORESET

2

Input low voltage

CLKIN input high voltage

CLKIN input low voltage

Input leakage current, V

IN

= VDDH

3

Symbol

V

IH

V

IL

V

IHC

V

ILC

I

IN

Min

2.0

GND

2.4

GND

Max

3.465

0.8

3.465

0.4

10

Unit

V

V

V

V

µA

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DC Electrical Characteristics

Table 5. DC Electrical Characteristics

1

(Continued)

Characteristic

Hi-Z (off state) leakage current, V

IN

= VDDH

3

Signal low input current, V

IL

= 0.8 V

Signal high input current, V

IH

= 2.0 V

Output high voltage, I

OH

= –2 mA except UTOPIA mode, and open drain pins

In UTOPIA mode

4

(UTOPIA pins only): I

OH

= -8.0mA

PA[0-31]

PB[4-31]

PC[0-31]

PD[4-31]

In UTOPIA mode

4

(UTOPIA pins only): I

OL

= 8.0mA

PA[0-31]

PB[4-31]

PC[0-31]

PD[4-31]

Symbol

I

OZ

I

L

I

H

V

OH

V

OL

Min

2.4

Max

10

1

1

0.5

Unit

µA

µA

µA

V

V

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DC Electrical Characteristics

Table 5. DC Electrical Characteristics

1

(Continued)

Characteristic

I

OL

= 6.0mA

BR

BG

ABB/IRQ2

TS

A[0-31]

TT[0-4]

TBST

TSIZE[0–3]

AACK

ARTRY

DBG

DBB/IRQ3

D[0-63]

DP(0)/RSRV/EXT_BR2

DP(1)/IRQ1/EXT_BG2

DP(2)/TLBISYNC/IRQ2/EXT_DBG2

DP(3)/IRQ3/EXT_BR3/CKSTP_OUT

DP(4)/IRQ4/EXT_BG3/CORE_SREST

DP(5)/TBEN/EXT_DBG3/IRQ5/CINT

DP(6)/CSE(0)/IRQ6

DP(7)/CSE(1)/IRQ7

PSDVAL

TA

TEA

GBL/IRQ1

CI/BADDR29/IRQ2

WT/BADDR30/IRQ3

L2_HIT/IRQ4

CPU_BG/BADDR31/IRQ5/CINT

CPU_DBG

CPU_BR

IRQ0/NMI_OUT

IRQ7/INT_OUT/APE

PORESET

HRESET

SRESET

RSTCONF

Symbol

V

OL

Min

Max

0.4

Unit

V

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DC Electrical Characteristics

Table 5. DC Electrical Characteristics

1

(Continued)

Characteristic Symbol Min Max Unit

I

OL

= 5.3mA

CS[0-9]

CS(10)/BCTL1

CS(11)/AP(0)

BADDR[27–28]

ALE

BCTL0

PWE[0–7]/PSDDQM[0–7]/PBS[0–7]

PSDA10/PGPL0

PSDWE/PGPL1

POE/PSDRAS/PGPL2

PSDCAS/PGPL3

PGTA/PUPMWAIT/PGPL4/PPBS

PSDAMUX/PGPL5

LWE[0–3]LSDDQM[0–3]/LBS[0–3]/PCI_CFG[0–3]

LSDA10/LGPL0/PCI_MODCKH0

LSDWE/LGPL1/PCI_MODCKH1

LOE/LSDRAS/LGPL2/PCI_MODCKH2

LSDCAS/LGPL3/PCI_MODCKH3

LGTA/LUPMWAIT/LGPL4/LPBS

LSDAMUX/LGPL5/PCI_MODCK

LWR

MODCK[1–3]/AP[1–3]/TC[0–2]/BNKSEL[0–2]

I

OL

= 3.2mA

L_A14/PAR

L_A15/FRAME/SMI

L_A16/TRDY

L_A17/IRDY/CKSTP_OUT

L_A18/STOP

L_A19/DEVSEL

L_A20/IDSEL

L_A21/PERR

L_A22/SERR

L_A23/REQ0

L_A24/REQ1/HSEJSW

L_A25/GNT0

L_A26/GNT1/HSLED

L_A27/GNT2/HSENUM

L_A28/RST/CORE_SRESET

L_A29/INTA

L_A30/REQ2

L_A31

LCL_D[0-31]/AD[0-31]

LCL_DP[0-3]/C/BE[0-3]

PA[0–31]

PB[4–31]

PC[0–31]

PD[4–31]

TDO

QREQ

V

OL

— 0.4

V

1

The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive

DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs.

2

TRST and PORESET should be tied to VDDH via a 2K

Ω external pull-up resistor.

3

The leakage current is measured for nominal VDDH,VCCSYN, and VDD.

4

MPC8280, MPC8275VR, MPC8275ZQ only

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Thermal Characteristics

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4 Thermal Characteristics

Table 6 describes thermal characteristics for both the packages. See Table 2 for information about a given

device’s package. For the discussions sections 4.1 and 4.2, P

D

= (V

DD

× I

DD

) + PI/O, where PI/O is the power dissipation of the I/O drivers.

Table 6. Thermal Characteristics

Value

Characteristic Symbol Unit Air Flow

480 TBGA 516 PBGA

Junction to ambient— single-layer board

1

R

θJA

16 27

°C/W

Natural convection

11 21 1 m/s

Junction to ambient— four-layer board R

θJA

12 19

°C/W

Natural convection

9 16 1 m/s

Junction to board

2

R

θJB

6 11

°C/W

Junction to case

3

R

θJC

2 8

°C/W

Junction-to-package top

4 Ψ

JT

2 2

°C/W

1

Assumes no thermal vias

2

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.

3

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

4

Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

4.1

Estimation with Junction-to-Ambient Thermal

Resistance

An estimation of the chip junction temperature, T

J

, in °C can be obtained from the following equation:

T

J

= T

A

+ (R

θJA

× P

D

) where:

T

A

= ambient temperature (ºC)

R

θJA

= package junction-to-ambient thermal resistance (ºC/W)

P

D

= power dissipation in package

The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. However, the answer is only an estimate; test cases have demonstrated that errors of a factor of two (in the quantity T

J

– T

A

) are possible.

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Thermal Characteristics

4.2

Experimental Determination

To determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter (

Ψ

JT

) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation:

T

J

= T

T

+ (

Ψ

JT

× P

D

) where:

Ψ

JT

= thermal characterization parameter

T

T

= thermocouple temperature on top of package

P

D

= power dissipation in package

The thermal characterization parameter is measured per JEDEC JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the case to avoid measurement errors caused by cooling effects of the thermocouple wire.

4.3

Layout Practices

Each V

CC

pin should be provided with a low-impedance path to the board’s power supply. Each ground pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on chip. The V

CC

power supply should be bypassed to ground using at least four 0.1 µF by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip V

CC

and ground should be kept to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as V

CC

and GND planes.

All output pins on the MPC8280 have fast rise and fall times. Printed circuit (PC) trace interconnection length should be minimized to minimize overdamped conditions and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the V

CC

and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.

Special care should be taken to minimize the noise levels on the PLL supply pins.

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Power Dissipation

5 Power Dissipation

Table 7 provides preliminary, estimated power dissipation for various configurations. Note that suitable

thermal management is required to ensure the junction temperature does not exceed the maximum specified value. Also note that the I/O power should be included when determining whether to use a heat sink. For a

complete list of possible clock configurations, refer to Section 7, “Clock Configuration Modes.”

Table 7. Estimated Power Dissipation for Various Configurations

1

P

INT

(W)

2,3

Bus

(MHz)

CPM

Multiplication

Factor

CPM

(MHz)

CPU

Multiplication

Factor

CPU

(MHz)

Vddl 1.5 Volts

Nominal Maximum

66.67

66.67

66.67

66.67

83.33

83.33

83.33

2.5

2.5

3

3.5

3

3

3.5

166

166

200

233

250

250

292

3.5

4

4

4.5

4

4.5

5

233

266

266

300

333

375

417

0.95

1.0

1.05

1.05

1.25

1.3

1.45

100 3 300 4 400 1.5

1.6

100 3 300 4.5

450 1.55

1

Test temperature = 105

˚

C

2

P

INT

= I

DD

x V

DD

Watts

3

Values do not include I/O. Add the following estimates for active I/O based on the following bus speeds:

66.7 MHz = 0.45 W (nominal), 0.5 W (maximum)

83.3 MHz = 0.5W (nominal), 0.6 W (maximum)

100 MHz = 0.6 W (nominal), 0.7 W (maximum)

1.65

1.0

1.05

1.1

1.15

1.35

1.4

1.55

6 AC Electrical Characteristics

The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and inputs for 66.67/83.33/100 MHz devices. Note that AC timings are based on a 50-pf load. Typical output

buffer impedances are shown in Table 8.

Table 8. Output Buffer Impedances

1

60x bus

Local bus

Memory controller

Output Buffers Typical Impedance (

)

45 or 27

2

45

45 or 27

2

Parallel I/O 45

PCI 27

1

These are typical values at 65˚ C. Impedance may vary by ±25% with process and temperature.

2

On silicon revision 0.0 (mask #: 0K49M), selectable impedance is not available. Impedance is set at 45

Ω.

On all other revisions, impedance value is selected through the SIUMCR[20,21]. Refer to the MPC8280 Addendum to

the MPC8260 PowerQUICC II Family Reference Manual.

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AC Electrical Characteristics

6.1

CPM AC Characteristics

Table 9 lists CPM output characteristics.

Table 9. AC Characteristics for CPM Outputs

1

Spec Number Characteristic Value (ns)

Max Min Maximum Delay Minimum Delay

66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz

sp36a sp37a FCC outputs—internal clock (NMSI) sp36b sp37b FCC outputs—external clock (NMSI) sp38a sp39a SCC/SMC/SPI/I2C outputs—internal clock (NMSI) sp38b sp39b SCC/SMC/SPI/I2C outputs—external clock (NMSI)

6

8

10

8

5.5

8

10

8

5.5

8

10

8

0.5

2

0

2

0.5

2

0

2

0.5

2

0

2 sp40 sp41 TDM outputs/SI sp42 sp43 TIMER/IDMA outputs

11

14

11

11

11

11

2.5

1

2.5

0.5

2.5

0.5

sp42a sp43a PIO outputs 14 11 11 0.5

0.5

0.5

1

Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.

Timings are measured at the pin.

Table 10 lists CPM input characteristics.

Table 10. AC Characteristics for CPM Inputs

1

Spec Number Characteristic Value (ns)

Setup Hold Setup Hold

66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz

sp16a sp17a FCC inputs—internal clock (NMSI) sp16b sp17b FCC inputs—external clock (NMSI) sp18a sp19a SCC/SMC/SPI/I2C inputs—internal clock (NMSI) sp18b sp19b SCC/SMC/SPI/I2C inputs—external clock (NMSI)

6

3

6

5

6

2.5

6

4

6

2.5

6

4

0

2

0

2

0

2

0

2 2 sp20 sp21 TDM inputs/SI 3 3 3 2.5

2.5

2.5

sp22 sp23 PIO/TIMER/IDMA inputs 10 8 8 0.5

0.5

0.5

1

Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.

Timings are measured at the pin.

0

2

0

NOTE

Although the specifications generally reference the rising edge of the clock, the following AC timing diagrams also apply when the falling edge is the active edge.

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AC Electrical Characteristics

Figure 3 shows the FCC internal clock.

BRG_OUT

sp17a

FCC input signals

sp16a sp36a/sp37a

FCC output signals

Note

: When GFMR[TCI] = 0

FCC output signals

Note

: When GFMR.[TCI] = 1

Figure 3. FCC Internal Clock Diagram

Figure 4 shows the FCC external clock.

Serial ClKin

sp17b sp16b

FCC input signals

sp36b/sp37b

FCC output signals

Note

: When GFMR[TCI] = 0

sp36a/sp37a sp36b/sp37b

FCC output signals

Note

: When GFMR[TCI] = 1

Figure 4. FCC External Clock Diagram

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AC Electrical Characteristics

Figure 5 shows the SCC/SMC/SPI/I

2

C external clock.

Serial CLKin

sp18b sp19b

SCC/SMC/SPI/I2C input signals

(See note)

sp38b/sp39b

SCC/SMC/SPI/I2C output signals

(See note)

Note

: There are four possible timing conditions for SCC and SPI:

1. Input sampled on the rising edge and output driven on the rising edge (shown).

2. Input sampled on the rising edge and output driven on the falling edge.

3. Input sampled on the falling edge and output driven on the falling edge.

4. Input sampled on the falling edge and output driven on the rising edge.

Figure 5. SCC/SMC/SPI/I

2

C External Clock Diagram

Figure 6 shows the SCC/SMC/SPI/I

2

C internal clock.

BRG_OUT

sp18a sp19a

SCC/SMC/SPI/I2C input signals

(See note)

sp38a/sp39a

SCC/SMC/SPI/I2C output signals

(See note)

Note

: There are four possible timing conditions for SCC and SPI:

1. Input sampled on the rising edge and output driven on the rising edge (shown).

2. Input sampled on the rising edge and output driven on the falling edge.

3. Input sampled on the falling edge and output driven on the falling edge.

4. Input sampled on the falling edge and output driven on the rising edge.

Figure 6. SCC/SMC/SPI/I

2

C Internal Clock Diagram

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AC Electrical Characteristics

Figure 7 shows TDM input and output signals.

Serial CLKin

sp20 sp21

TDM input signals

sp40/sp41

TDM output signals

Note

: There are four possible TDM timing conditions:

1. Input sampled on the rising edge and output driven on the rising edge (shown).

2. Input sampled on the rising edge and output driven on the falling edge.

3. Input sampled on the falling edge and output driven on the falling edge.

4. Input sampled on the falling edge and output driven on the rising edge.

Figure 7. TDM Signal Diagram

Figure 8 shows PIO and timer signals.

Sys clk

sp23 sp22

PIO/IDMA/TIMER[TGATE assertion] input signals

(See note)

sp23 sp22

TIMER input signal [TGATE deassertion]

(See note)

sp42/sp43

IDMA output signals

sp42/sp43 sp42a/sp43a

TIMER(sp42/43)/ PIO(sp42a/sp43a) output signals

Note

: TGATE is asserted on the rising edge of the clock; it is deasserted on the falling edge.

Figure 8. PIO and Timer Signal Diagram

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AC Electrical Characteristics

6.2

SIU AC Characteristics

NOTE: CLKIN Jitter and Duty Cycle

The CLKIN input to the MPC8280 should not exceed +/– 150 psec. This represents total input jitter—the combination of short term (peak-to-peak) and long term (cumulative). The duty cycle of CLKIN should not exceed the ratio of 40:60.

NOTE: PCI AC Timing

The MPC8280 meets the timing requirements of PCI Specification

Revision 2.2. Refer to Sections 7.2 and 7.3 and “Note: Tval (Output Hold)”

to determine if a specific clock configuration is compliant.

Table 11 lists SIU input characteristics.

Table 11. AC Characteristics for SIU Inputs

1

Characteristic Spec Number

Setup Hold

Value (ns)

Setup Hold

66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz

sp11 sp10 AACK/TA/TS/DBG/BG/BR 6 sp11a sp10 ARTRY/ TEA sp12 sp10 Data bus in normal mode

6

5

5

5

4

3.5

4

3.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

sp13 sp10 Data bus in ECC and PARITY modes sp13a sp10 Pipeline mode—

Data bus in ECC and PARITY modes sp14 sp10 DP pins

7

5

7

5

4

5

3.5

2.5

3.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

sp14a sp10 Pipeline mode—DP pins — 4 2.5

— 0.5

0.5

sp15 sp10 All other pins 5 4 3.5

0.5

0.5

0.5

1

Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin.

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AC Electrical Characteristics

Table 12 lists SIU output characteristics.

Table 12. AC Characteristics for SIU Outputs

1

Characteristic Value (ns) Spec Number

Max Min Maximum Delay Minimum Delay

66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz

sp31 sp30 PSDVAL/TEA/TA sp32 sp30 ADD/ADD_atr./BADDR/CI/GBL/WT sp33a sp30 Data sp33b sp30 DP sp34 sp30 Memory controller signals/ALE

7

8

6.5

6

6

6

6.5

6.5

5.5

5.5

5.5

5.5

5.5

5.5

5.5

1

1

0.7

1

1

1

1

0.7

1

1 sp35 sp30 All other signals 6 5.5

5.5

1 1 1 sp35a sp30 AP 7 7 7 1 1 1

1

Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.

Timings are measured at the pin.

NOTE

Activating data pipelining (setting BRx[DR] in the memory controller) improves the AC timing.

1

1

0.7

1

1

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AC Electrical Characteristics

Figure 9 shows the interaction of several bus signals.

CLKin

sp11 sp10

AACK/TA/TS/

DBG/BG/BR input signals

sp11a sp10

ARTRY/TEA input signals

sp12 sp10

DATA bus normal mode input signal

sp15 sp10

All other input signals

sp30 sp31

PSDVAL/TEA/TA output signals

ADD/ADD_atr/BADDR/CI/

GBL/WT output signals

sp32 sp30 sp33a sp30

DATA bus output signals

sp35 sp30

All other output signals

(except AP)

AP signals

sp35a sp30

Figure 9. Bus Signals

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AC Electrical Characteristics

Figure 10 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).

CLKin

sp10 sp13

DATA bus, ECC, and PARITY mode input signals

sp10 sp13a

Pipeline mode—

DATA bus, ECC, and PARITY mode input signals

sp10 sp14

DP mode input signal

sp10 sp14a

Pipeline mode—

DP mode input signal

sp33b sp30

DP mode output signal

Figure 10. Parity Mode Diagram

Figure 11 shows signal behavior in MEMC mode.

CLKin

V_CLK

sp34/sp30

Memory controller signals

Figure 11. MEMC Mode Diagram

NOTE

Generally, all MPC8280 bus and system output signals are driven from the rising edge of the input clock (CLKin). Memory controller signals, however, trigger on four points within a CLKin cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge, and T3 at the falling edge, of CLKin. However, the spacing of

T2 and T4 depends on the PLL clock ratio selected, as shown in Table 13.

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Clock Configuration Modes

Table 13. Tick Spacing for Memory Controller Signals

Tick Spacing (T1 Occurs at the Rising Edge of CLKin)

PLL Clock Ratio

T2

1:2, 1:3, 1:4, 1:5, 1:6 1/4 CLKin

1:2.5

3/10 CLKin

1:3.5

4/14 CLKin

T3

1/2 CLKin

1/2 CLKin

1/2 CLKin

T4

3/4 CLKin

8/10 CLKin

11/14 CLKin

Figure 12 is a representation of the information in Table 13.

CLKin for 1:2, 1:3, 1:4, 1:5, 1:6

T1 T2 T3 T4

CLKin

T1 T2 T3 T4 for 1:2.5

CLKin for 1:3.5

T1 T2 T3 T4

Figure 12. Internal Tick Spacing for Memory Controller Signals

NOTE

The UPM machine outputs change on the internal tick determined by the memory controller programming; the AC specifications are relative to the internal tick. Note that SDRAM and GPCM machine outputs change on

CLKin’s rising edge.

7 Clock Configuration Modes

The MPC8280 has three clocking modes: local, PCI host, and PCI agent. The clocking mode is set according

to three input pins—PCI_MODE, PCI_CFG[0], PCI_MODCK—as shown in Table 14.

Table 14. MPC8280 Clocking Modes

Pins

PCI_MODE PCI_CFG[0] PCI_MODCK

1

Clocking Mode

1

0

0

0

0

0

1

Local bus

PCI host

0 1 0 PCI agent

0 1 1

1

Determines PCI clock frequency range. Refer to Sections 7.2 and 7.3.

PCI Clock

Frequency Range

(MHZ)

50–66

25–50

50–66

25–50

Reference

Table 15

Table 16

Table 17

Table 18

Table 19

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Clock Configuration Modes

In each clocking mode, the configuration of bus, core, PCI, and CPM frequencies is determined by seven bits during the power-up reset—three hardware configuration pins (MODCK[1–3]) and four bits from hardware configuration word[28–31] (MODCK_H). Both the PLLs and the dividers are set according to the selected MPC8280 clock operation mode as described in the following sections.

7.1

Local Bus Mode

Table 15 lists clock configurations for the MPC8280 in local bus mode. The frequencies listed are for the

purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s device.

NOTE

Clock configurations change only after PORESET is asserted.

Table 15. Clock Configurations for Local Bus Mode

1

Mode

2

Bus Clock

3

(MHz)

MODCK_H-MODCK[1-3] low high

CPM

Multiplication

Factor

4

CPM Clock

(MHz) low high

CPU

Multiplication

Factor

5

CPU Clock

(MHz) low high

0000_000

0000_001

0000_010

0000_011

0000_100

0000_101

0000_110

0000_111

0001_000

0001_001

0001_010

0001_011

0001_100

Default Modes (MODCK_H= 0000)

62.5

133.3

50.0

133.3

62.5

100.0

50.0

100.0

66.7

167.0

66.7

167.0

66.7

160.0

55.5

160.0

3 187.5

3 150.0

4 250.0

4 200.0

400.0

400.0

400.0

400.0

2 133.3

2 133.3

2.5

2.5

166.7

138.7

334.0

334.0

400.0

400.0

66.7

167.0

66.7

167.0

66.7

167.0

Full Configuration Modes

2 133.3

2 133.3

2 133.3

334.0

334.0

334.0

Reserved

Reserved

4 250.0

5 250.0

4 250.0

5 250.0

2.5

166.7

3 200.0

2.5

166.7

3 166.7

533.3

666.7

400.0

500.0

417.5

501.0

400.0

480.0

4 266.7

668.0

5 333.3

835.0

6 396.0

1002.0

0001_101

0001_110

1000_111

0001_111

0010_000

0010_001

62.5

133.3

50.0

133.3

45.5

133.3

44.3

133.3

3 187.5

3 150.0

3 136.4

400.0

400.0

400.0

3 133.3

400.0

Reserved

Reserved

4 250.0

5 250.0

5.5

250.0

6 266.7

533.3

666.7

733.3

800.0

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Clock Configuration Modes

Mode

2

Table 15. Clock Configurations for Local Bus Mode

1

(Continued)

Bus Clock

3

(MHz)

CPM

Multiplication

Factor

4

CPM Clock

(MHz)

MODCK_H-MODCK[1-3] low high low high

CPU

Multiplication

Factor

5

0010_010

0010_011

0010_100

0010_101

0010_110

62.5

100.0

50.0

100.0

41.7

100.0

35.7

100.0

33.3

100.0

4 250.0

4 200.0

4 166.7

4 142.9

4 133.3

400.0

400.0

400.0

400.0

400.0

CPU Clock

(MHz) low

4 250.0

5 250.0

6 250.0

7 250.0

8 266.7

high

400.0

500.0

600.0

700.0

800.0

0101_101

0101_110

0101_111

0110_000

0110_001

0110_010

0110_011

0110_100

0110_101

0110_110

0110_111

0111_000

0111_001

0111_010

0010_111

0011_000

0011_001

0011_010

0011_011

0011_100

0011_101

0011_110

0011_111

0100_000

50.0

41.7

35.7

31.3

80.0

80.0

80.0

80.0

41.7

35.7

31.3

66.7

66.7

66.7

83.3

167.0

66.7

167.0

66.7

167.0

71.4

167.0

62.5

167.0

55.6

167.0

66.7

160.0

55.5

160.0

71.4

160.0

62.5

160.0

55.6

160.0

2.5

2.5

2.5

2.5

2.5

Reserved

5 250.0

5 208.3

400.0

400.0

5 178.6

5 156.3

400.0

400.0

Reserved

Reserved

6 250.0

400.0

6 214.3

6 187.5

400.0

400.0

2 166.7

2 133.3

2 133.3

2 142.9

2 125.0

2 111.1

334.0

334.0

334.0

334.0

334.0

334.0

Reserved

166.7

400.0

138.7

400.0

133.0

400.0

133.0.3

400.0

133.0

400.0

Reserved

Reserved

5 250.0

6 250.0

7 250.0

8 250.0

400.0

480.0

560.0

640.0

6 250.0

7 250.0

8 250.0

400.0

466.7

533.3

2 166.7

2.5

166.7

3 200.0

3.5

250.0

4 250.0

4.5

250.0

334.0

417.5

501.0

584.5

668.0

751.5

2.5

166.7

3 166.7

3.5

250.0

4 250.0

4.5

250.0

400.0

480.0

560.0

640.0

720.0

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Clock Configuration Modes

Mode

2

Table 15. Clock Configurations for Local Bus Mode

1

(Continued)

Bus Clock

3

(MHz)

CPM

Multiplication

Factor

4

CPM Clock

(MHz)

MODCK_H-MODCK[1-3] low high low high

CPU

Multiplication

Factor

5

0111_011

0111_100

0111_101

0111_110

0111_111

55.5

133.3

71.4

133.3

62.5

133.3

55.6

133.3

3 166.7

3 133.0

3 133.0

400.0

400.0

400.0

3 133.0

400.0

Reserved

CPU Clock

(MHz) low

3 166.7

3.5

250.0

4 250.0

4.5

250.0

high

400.0

466.7

533.3

600.0

1000_000

1000_001

1000_010

1000_011

1000_100

1000_101

1000_110

1100_000

1100_001

1100_010

71.4

114.3

62.5

114.3

55.6

114.3

50.0

114.3

45.5

114.3

3.5

3.5

3.5

3.5

3.5

Reserved

Reserved

250.0

400.0

218.8

400.0

194.4

400.0

175.0

400.0

159.1

400.0

Reserved

Reserved

Reserved

3.5

250.0

4 250.0

4.5

250.0

5 250.0

5.5

250.0

400.0

457.1

514.3

571.4

628.6

1101_000 Reserved

1

“Low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency guarantees the required minimum CPU operating frequency. Minimum CPU frequency is determined by the clock mode.

For modes with a CPU multiplication factor

≤ 3, the minimum CPU frequency is 166 MHz. The minimum CPM frequency is 133 MHz.

For modes with a CPU multiplication factor

≥ 3.5, the minimum CPU frequency is 250 MHz. The minimum CPM frequency is as shown in the table.

“High” values are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s device.

2

MODCK_H = hard reset configuration word [28–31]. MODCK[1-3] = three hardware configuration pins.

3

60x and local bus frequency. Identical to CLKIN.

4

CPM multiplication factor = CPM clock/bus clock

5

CPU multiplication factor = Core PLL multiplication factor

7.2

PCI Host Mode

Table 16 and Table 17 show clock configurations for PCI host mode. The frequencies listed are for the

purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s device. In addition, note the following:

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Clock Configuration Modes

NOTE: PCI_MODCK

In PCI mode only, PCI_MODCK comes from the LGPL5 pin and

MODCK_H[0–3] comes from {LGPL0, LGPL1, LGPL2, LGPL3}.

NOTE: Tval (Output Hold)

The minimum Tval = 2 when PCI_MODCK = 1, and the minimum

Tval = 1 when PCI_MODCK = 0. Therefore, designers should use clock configurations that fit this condition to achieve PCI-compliant AC timing.

Mode

3

MODCK_H-

MODCK[1-3]

Table 16. Clock Configurations for PCI Host Mode (PCI_MODCK=0)

1,2

Bus Clock

4

(MHz) low high

CPM

Multiplication

Factor

5

CPM Clock

(MHz) low high

CPU

Multiplication

Factor

6

CPU Clock

(MHz) low high

PCI

Division

Factor

0000_000

0000_001

0000_010

0000_011

0000_100

0000_101

0000_110

0000_111

0001_000

0001_001

0001_010

0001_011

66.7

66.7

66.7

66.7

55.5

80.0

71.4

80.0

62.5

80.0

55.5

66.7

62.5

66.7

50.0

66.7

50.0

66.7

50.0

66.7

50.0

66.7

Default Modes (MODCK_H=0000)

3

3

3

3

2

2

2.5

133.3 133.3

133.3 133.3

150.0 200.0

2.5

3

3

166.7 166.7

200.0 200.0

166.7 240.0

2.5

2.5

178.6 200.0

156.3 200.0

187.5 200.0

3.5

4

4

Full Configuration Modes

250.0 280.0

250.0 320.0

3 166.7 200.0

3 166.7 200.0

PCI host mode (PCI_MODCK=1) only (refer to Table 17)

3 250.0 266.6

150.0 200.0

150.0 200.0

150.0 200.0

150.0 200.0

7

8

5

6

250.0 333.3

300.0 400.0

350.0 466.6

400.0 533.3

3

3

3

3

3

3

3

3

2

2

3

PCI Clock

(MHz) low high

66.7 66.7

66.7 66.7

50.0 66.7

59.5 66.7

52.1 66.7

55.5 66.7

62.5 66.7

50.0 66.7

50.0 66.7

50.0 66.7

50.0 66.7

0010_000

0010_001

0010_010

0010_011

50.0

66.7

50.0

66.7

50.0

66.7

50.0

66.7

0010_100

0010_101

0010_110

75.0

100.0

75.0

100.0

75.0

100.0

0011_000 50.0

66.7

4

4

4

4

4

4

4

5

200.0 266.6

200.0 266.6

200.0 266.6

200.0 266.6

300.0 400.0

300.0 400.0

300.0 400.0

250.0 333.3

5

5.5

6

5

6

7

8

5

250.0 333.3

300.0 400.0

350.0 466.6

400.0 533.3

375.0 500.0

412.5 549.9

450.0 599.9

250.0 333.3

6

6

6

4

4

4

4

5

50.0 66.7

50.0 66.7

50.0 66.7

50.0 66.7

50.0 66.7

50.0 66.7

50.0 66.7

50.0 66.7

27 MOTOROLA

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0100_000

0100_001

0100_010

0100_011

50.0

66.7

50.0

66.7

50.0

66.7

0101_000

0101_001

0101_010

0101_011

0101_100

66.7

66.7

66.7

66.7

66.7

66.7

66.7

66.7

0110_000

0110_001

0110_010

0110_011

0110_100

0110_101

0110_110

66.7

80.0

60.0

80.0

71.4

80.0

62.5

80.0

60.0

80.0

60.0

80.0

60.0

80.0

0111_000

0111_001

0111_010

0111_011

0111_100

55.5

66.7

62.5

66.7

55.6

66.7

1000_000

1000_001

1000_010

1000_011

66.7

88.9

71.4

88.9

66.7

88.9

Freescale Semiconductor, Inc.

Clock Configuration Modes

Mode

3

Table 16. Clock Configurations for PCI Host Mode (PCI_MODCK=0)

1,2

(Continued)

MODCK_H-

MODCK[1-3]

Bus Clock

4

(MHz) low high

CPM

Multiplication

Factor

5

CPM Clock

(MHz) low high

CPU

Multiplication

Factor

6

CPU Clock

(MHz) low high

PCI

Division

Factor

PCI Clock

(MHz) low high

0011_001

0011_010

0011_011

50.0

66.7

50.0

66.7

50.0

66.7

5

5

5

250.0 333.3

250.0 333.3

250.0 333.3

6

7

8

300.0 400.0

350.0 466.6

400.0 533.3

5

5

5

50.0 66.7

50.0 66.7

50.0 66.7

6

6

6

2.5

2.5

2.5

2.5

2.5

2.5

2.5

300.0 400.0

300.0 400.0

300.0 400.0

Reserved

6

7

8

300.0 400.0

350.0 466.6

400.0 533.3

2

2

2 133.3 133.3

2.5

166.7 166.7

2 133.3 133.3

3 200.0 200.0

PCI host mode (PCI_MODCK=1) only (refer to Table 17)

133.3 133.3

133.3 133.3

4

4.5

266.7 266.6

300.0 300.0

2

2

2

2

166.7 200.0

150.0 200.0

178.6 200.0

156.3 200.0

150.0 200.0

150.0 200.0

150.0 200.0

2.5

3

3.5

4

4.5

5

6

166.7 200.0

180.0 240.0

250.0 280.0

250.0 320.0

270.0 360.0

300.0 400.0

360.0 480.0

6

6

6

3

3

3

3

3

3

3

3

3

3

3

3

Reserved

3 166.7 200.0

3 166.7 200.0

PCI host mode (PCI_MODCK=1) only (refer to Table 17)

187.5 200.0

166.7 200.0

4

4.5

250.0 266.6

250.0 300.0

3

3

3

200.0 266.6

214.3 266.6

200.0 266.6

Reserved

3

3.5

4

200.0 266.6

250.0 311.1

266.7 355.5

4

4

4

55.5 66.7

62.5 66.7

55.6 66.7

50.0 66.7

53.6 66.7

50.0 66.7

50.0 66.7

50.0 66.7

50.0 66.7

66.7 66.7

66.7 66.7

66.7 66.7

66.7 66.7

55.5 66.7

50.0 66.7

59.5 66.7

52.1 66.7

50.0 66.7

50.0 66.7

50.0 66.7

28

MPC8280 PowerQUICC II™ Family Hardware Specifications

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Clock Configuration Modes

Mode

3

Table 16. Clock Configurations for PCI Host Mode (PCI_MODCK=0)

1,2

(Continued)

MODCK_H-

MODCK[1-3]

Bus Clock

4

(MHz) low high

CPM

Multiplication

Factor

5

CPM Clock

(MHz) low high

CPU

Multiplication

Factor

6

CPU Clock

(MHz) low high

PCI

Division

Factor

PCI Clock

(MHz) low high

1000_100

1000_101

1000_110

66.7

88.9

66.7

88.9

66.7

88.9

3

3

3

200.0 266.6

200.0 266.6

200.0 266.6

4.5

6

6.5

300.0 400.0

400.0 533.3

433.3 577.7

4

4

4

50.0 66.7

50.0 66.7

50.0 66.7

1001_000

1001_001

1001_010

1001_011

1001_100

66.7

76.2

57.1

76.2

71.4

76.2

62.5

76.2

57.1

76.2

1001_101

1001_110

1001_111

85.7

114.3

85.7

114.3

85.7

114.3

1010_000

1010_001

1010_010

1010_011

1010_100

83.4

100.0

75.0

100.0

75.0

100.0

75.0

100.0

75.0

100.0

1011_000

1011_001

1011_010

1011_011

1011_100

1011_101

80.0

106.7

80.0

106.7

80.0

106.7

80.0

106.7

80.0

106.7

1101_000 100.0 133.3

1101_001 100.0 133.3

1101_010 100.0 133.3

1101_011 100.0 133.3

1101_100 100.0 133.3

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

3.5

3.5

3.5

3.5

3.5

3.5

3.5

3.5

2

2

2

2

2

233.3 266.6

200.0 266.6

250.0 266.6

218.8 266.6

200.0 266.6

300.0 400.0

300.0 400.0

300.0 400.0

2.5

3

3.5

4

4.5

5

5.5

6

166.7 190.5

171.4 228.5

250.0 266.6

250.0 304.7

257.1 342.8

428.6 571.4

471.4 628.5

514.3 685.6

166.7 200.0

150.0 200.0

150.0 200.0

150.0 200.0

150.0 200.0

2

2.5

3

3.5

4

166.7 200.0

187.5 250.0

225.0 300.0

262.5 350.0

300.0 400.0

200.0 266.6

200.0 266.6

200.0 266.6

200.0 266.6

200.0 266.6

Reserved

2.5

3

3.5

4

4.5

200.0 266.6

240.0 320.0

280.0 373.3

320.0 426.6

360.0 480.0

250.0 333.3

250.0 333.3

250.0 333.3

250.0 333.3

250.0 333.3

3

3.5

4

4.5

5

300.0 400.0

350.0 466.6

400.0 533.3

450.0 599.9

500.0 666.6

5

5

5

5

5

4

4

4

4

4

6

6

6

4

4

4

4

4

3

3

3

3

3

58.3 66.7

50.0 66.7

62.5 66.7

54.7 66.7

50.0 66.7

50.0 66.7

50.0 66.7

50.0 66.7

55.5 66.7

50.0 66.7

50.0 66.7

50.0 66.7

50.0 66.7

50.0 66.7

50.0 66.7

50.0 66.7

50.0 66.7

50.0 66.7

50.0 66.7

50.0 66.7

50.0 66.7

50.0 66.7

50.0 66.7

29 MOTOROLA

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Clock Configuration Modes

Mode

3

Table 16. Clock Configurations for PCI Host Mode (PCI_MODCK=0)

1,2

(Continued)

MODCK_H-

MODCK[1-3]

Bus Clock

4

(MHz) low high

CPM

Multiplication

Factor

5

CPM Clock

(MHz) low high

CPU

Multiplication

Factor

6

CPU Clock

(MHz) low high

PCI

Division

Factor

PCI Clock

(MHz) low high

1101_101 125.0 166.7

1101_110 125.0 166.7

2

2

250.0 333.3

250.0 333.3

3

4

375.0 500.0

500.0 666.6

5

5

50.0 66.7

50.0 66.7

1110_000

1110_001

1110_010

1110_011

1110_100

100.0 133.3

100.0 133.3

100.0 133.3

100.0 133.3

100.0 133.3

3

3

3

3

3

300.0 400.0

300.0 400.0

300.0 400.0

300.0 400.0

300.0 400.0

3.5

4

4.5

5

5.5

350.0 466.6

400.0 533.3

450.0 599.9

500.0 666.6

550.0 733.3

6

6

6

6

6

50.0 66.7

50.0 66.7

50.0 66.7

50.0 66.7

50.0 66.7

1100_000 Reserved

1100_001 Reserved

1100_010 Reserved

1

“Low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency guarantees the required minimum CPU operating frequency. Minimum CPU frequency is determined by the clock mode.

For modes with a CPU multiplication factor

≤ 3, the minimum CPU frequency is 166 MHz. The minimum CPM frequency is 133 MHz.

For modes with a CPU multiplication factor

≥ 3.5, the minimum CPU frequency is 250 MHz. The minimum CPM frequency is as shown in the table.

“High” values are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s device.

2

As Table 14 shows, PCI_MODCK determines the PCI clock frequency range. Refer to Table 17 for lower configurations.

3

MODCK_H = hard reset configuration word [28–31]. MODCK[1-3] = three hardware configuration pins.

4

60x and local bus frequency. Identical to CLKIN.

5

CPM multiplication factor = CPM clock/bus clock

6

CPU multiplication factor = Core PLL multiplication factor

Mode

3

MODCK_H-

MODCK[1-3]

Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=1)

1,2

Bus Clock

4

(MHz) low high

CPM

Multiplication

Factor

5

CPM Clock

(MHz) low high

CPU

Multiplication

Factor

6

CPU Clock

(MHz) low high

PCI

Division

Factor

0000_000

0000_001

0000_010

0000_011

0000_100

66.7

100.0

66.7

100.0

60.0

120.0

71.4

120.0

62.5

120.0

2

2

2.5

Default Modes (MODCK_H=0000)

133.3 200.0

2.5

166.7 250.0

133.3 200.0

150.0 300.0

3

3

200.0 300.0

180.0 360.0

2.5

2.5

178.6 300.0

156.3 300.0

3.5

4

250.0 420.0

250.0 480.0

4

4

6

6

6

PCI Clock

(MHz) low high

33.3 50.0

33.3 50.0

25.0 50.0

29.8 50.0

26.0 50.0

30

MPC8280 PowerQUICC II™ Family Hardware Specifications

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Clock Configuration Modes

Mode

3

Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=1)

1,2

(Continued)

MODCK_H-

MODCK[1-3]

Bus Clock

4

(MHz) low high

CPM

Multiplication

Factor

5

CPM Clock

(MHz) low high

CPU

Multiplication

Factor

6

CPU Clock

(MHz) low high

PCI

Division

Factor

PCI Clock

(MHz) low high

0000_101

0000_110

0000_111

0001_000

0001_001

0001_010

0001_011

55.5

100.0

71.4

100.0

62.5

100.0

50.0

100.0

50.0

100.0

50.0

100.0

50.0

100.0

3

3

3

3

3

3

3

166.7 300.0

214.3 300.0

3

3.5

187.5 300.0

4

Full Configuration Modes

150.0 300.0

150.0 300.0

150.0 300.0

150.0 300.0

5

6

7

8

166.7 300.0

250.0 350.0

250.0 400.0

250.0 500.0

300.0 600.0

350.0 700.0

400.0 800.0

6

6

6

6

6

6

6

27.8 50.0

35.7 50.0

31.3 50.0

25.0 50.0

25.0 50.0

25.0 50.0

25.0 50.0

0010_000

0010_001

0010_010

0010_011

50.0

100.0

50.0

100.0

50.0

100.0

50.0

100.0

0010_100

0010_101

0010_110

50.0

75.0

45.5

75.0

41.7

75.0

0011_000

0011_001

0011_010

0011_011

50.0

50.0

41.7

50.0

35.7

50.0

31.3

50.0

0100_000

0100_001

0100_010

0100_011

41.7

50.0

35.7

50.0

31.3

50.0

0101_000

0101_001

0101_010

0101_011

0101_100

66.7

100.0

66.7

100.0

71.4

100.0

66.7

100.0

66.7

100.0

2

2

2

2

2

6

6

6

4

4

4

4

4

4

4

5

5

5

5

200.0 400.0

200.0 400.0

200.0 400.0

200.0 400.0

200.0 300.0

181.8 300.0

166.7 300.0

5

5.5

6

5

6

7

8

250.0 500.0

300.0 600.0

350.0 700.0

400.0 800.0

250.0 375.0

250.0 412.5

250.0 450.0

250.0 250.0

208.3 250.0

178.6 250.0

156.3 250.0

7

8

5

6

250.0 250.0

250.0 300.0

250.0 350.0

250.0 400.0

250.0 300.0

214.3 300.0

187.5 300.0

Reserved

6

7

8

250.0 300.0

250.0 350.0

250.0 400.0

133.3 200.0

133.3 200.0

142.9 200.0

133.3 200.0

133.3 200.0

2.5

3

3.5

4

4.5

166.7 250.0

200.0 300.0

250.0 350.0

266.7 400.0

300.0 450.0

4

4

4

4

4

6

6

6

6

6

6

8

8

8

8

5

5

5

5

41.7 50.0

35.7 50.0

31.3 50.0

33.3 50.0

33.3 50.0

35.7 50.0

33.3 50.0

33.3 50.0

25.0 50.0

25.0 50.0

25.0 50.0

25.0 50.0

33.3 50.0

30.3 50.0

27.8 50.0

50.0 50.0

41.7 50.0

35.7 50.0

31.3 50.0

31 MOTOROLA

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Clock Configuration Modes

Mode

3

Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=1)

1,2

(Continued)

MODCK_H-

MODCK[1-3]

Bus Clock

4

(MHz) low high

CPM

Multiplication

Factor

5

CPM Clock

(MHz) low high

CPU

Multiplication

Factor

6

CPU Clock

(MHz) low high

PCI

Division

Factor

PCI Clock

(MHz) low high

0110_000

0110_001

0110_010

0110_011

0110_100

0110_101

0110_110

66.7

120.0

60.0

120.0

71.4

120.0

62.5

120.0

60.0

120.0

60.0

120.0

60.0

120.0

0111_000

0111_001

0111_010

0111_011

0111_100

55.5

100.0

71.4

100.0

62.5

100.0

55.6

100.0

1000_000

1000_001

1000_010

1000_011

1000_100

1000_101

1000_110

66.7

133.3

71.4

133.3

66.7

133.3

66.7

133.3

66.7

133.3

66.7

133.3

1001_000

1001_001

1001_010

1001_011

1001_100

71.4

114.3

62.5

114.3

57.1

114.3

1001_101

1001_110

1001_111

50.0

85.7

45.5

85.7

42.9

85.7

3.5

3.5

3.5

3.5

3.5

3.5

3

3

3

3

3

3

3

3

3

3

2.5

2.5

2.5

2.5

2.5

2.5

2.5

166.7 300.0

150.0 300.0

178.6 300.0

156.3 300.0

150.0 300.0

150.0 300.0

150.0 300.0

2.5

3

3.5

4

4.5

5

6

166.7 300.0

180.0 360.0

250.0 420.0

250.0 480.0

270.0 540.0

300.0 600.0

360.0 720.0

166.7 300.0

214.3 300.0

187.5 300.0

166.7 300.0

Reserved

3

3.5

4

4.5

166.7 300.0

250.0 350.0

250.0 400.0

250.0 450.0

200.0 400.0

214.3 400.0

200.0 400.0

200.0 400.0

200.0 400.0

200.0 400.0

Reserved

3

3.5

4

4.5

6

6.5

200.0 400.0

250.0 466.7

266.7 533.3

300.0 600.0

400.0 800.0

433.3 866.7

250.0 400.0

218.8 400.0

200.0 400.0

Reserved

Reserved

3.5

4

4.5

250.0 400.0

250.0 457.1

257.1 514.3

175.0 300.0

159.1 300.0

150.0 300.0

5

5.5

6

250.0 428.6

250.0 471.4

257.1 514.3

6

6

6

8

8

8

8

8

8

8

8

8

6

6

6

6

6

6

6

6

6

6

6

27.8 50.0

25.0 50.0

29.8 50.0

26.0 50.0

25.0 50.0

25.0 50.0

25.0 50.0

27.8 50.0

35.7 50.0

31.3 50.0

27.8 50.0

25.0 50.0

26.8 50.0

25.0 50.0

25.0 50.0

25.0 50.0

25.0 50.0

31.3 50.0

27.3 50.0

25.0 50.0

29.2 50.0

26.5 50.0

25.0 50.0

32

MPC8280 PowerQUICC II™ Family Hardware Specifications

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Clock Configuration Modes

Mode

3

Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=1)

1,2

(Continued)

MODCK_H-

MODCK[1-3]

Bus Clock

4

(MHz) low high

CPM

Multiplication

Factor

5

CPM Clock

(MHz) low high

CPU

Multiplication

Factor

6

CPU Clock

(MHz) low high

PCI

Division

Factor

PCI Clock

(MHz) low high

1010_000

1010_001

1010_010

1010_011

1010_100

75.0

150.0

75.0

150.0

75.0

150.0

75.0

150.0

75.0

150.0

2

2

2

2

2

150.0 300.0

150.0 300.0

150.0 300.0

150.0 300.0

150.0 300.0

2

2.5

3

3.5

4

150.0 300.0

187.5 375.0

225.0 450.0

262.5 525.0

300.0 600.0

6

6

6

6

6

25.0 50.0

25.0 50.0

25.0 50.0

25.0 50.0

25.0 50.0

1011_000

1011_001

1011_010

1011_011

1011_100

1011_101

80.0

160.0

80.0

160.0

80.0

160.0

80.0

160.0

80.0

160.0

1101_000

1101_001

1101_010

1101_011

1101_100

55.5

100.0

71.4

100.0

62.5

100.0

55.6

100.0

50.0

100.0

1101_101

1101_110

66.7

125.0

66.7

125.0

1110_000

1110_001

1110_010

1110_011

1110_100

71.4

100.0

62.5

100.0

55.6

100.0

50.0

100.0

50.0

100.0

1100_000

1100_001

1100_010

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

3

3

3

3

3

2

2

200.0 400.0

200.0 400.0

200.0 400.0

200.0 400.0

200.0 400.0

Reserved

2.5

3

3.5

4

4.5

200.0 400.0

240.0 480.0

280.0 560.0

320.0 640.0

360.0 720.0

138.5 250.0

178.6 250.0

156.3 250.0

138.9 250.0

125.0 250.0

3

3.5

4

4.5

5

166.7 300.0

250.0 350.0

250.0 400.0

250.0 450.0

250.0 500.0

133.3 250.0

133.3 250.0

214.3 300.0

187.5 300.0

166.7 300.0

150.0 300.0

150.0 300.0

3

4

3.5

4

4.5

5

5.5

Reserved

Reserved

Reserved

200.0 375.0

266.7 500.0

250.0 350.0

250.0 400.0

250.0 450.0

250.0 500.0

275.0 550.0

5

5

5

5

5

8

8

8

8

8

6

6

6

6

6

5

5

25.0 50.0

25.0 50.0

25.0 50.0

25.0 50.0

25.0 50.0

27.8 50.0

35.7 50.0

31.3 50.0

27.8 50.0

25.0 50.0

26.6 50.0

26.6 50.0

35.7 50.0

31.3 50.0

27.8 50.0

25.0 50.0

25.0 50.0

33 MOTOROLA

MPC8280 PowerQUICC II™ Family Hardware Specifications

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Freescale Semiconductor, Inc.

Clock Configuration Modes

1

“Low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency guarantees the required minimum CPU operating frequency. Minimum CPU frequency is determined by the clock mode.

For modes with a CPU multiplication factor

≤ 3, the minimum CPU frequency is 166 MHz. The minimum CPM frequency is 133 MHz.

For modes with a CPU multiplication factor

≥ 3.5, the minimum CPU frequency is 250 MHz. The minimum CPM frequency is as shown in the table.

“High” values are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s device.

2

As Table 14 shows, PCI_MODCK determines the PCI clock frequency range. Refer to Table 16 for higher configurations.

3

MODCK_H = hard reset configuration word [28–31]. MODCK[1-3] = three hardware configuration pins.

4

60x and local bus frequency. Identical to CLKIN.

5

CPM multiplication factor = CPM clock/bus clock

6

CPU multiplication factor = Core PLL multiplication factor

7.3

PCI Agent Mode

Table 18 and Table 19 show configurations for PCI agent mode. The frequencies listed are for the purpose

of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s device. In addition, note the following:

NOTE: PCI_MODCK

In PCI mode only, PCI_MODCK comes from the LGPL5 pin and

MODCK_H[0–3] comes from {LGPL0, LGPL1, LGPL2, LGPL3}.

NOTE: Tval (Output Hold)

The minimum Tval = 2 when PCI_MODCK = 1, and the minimum

Tval = 1 when PCI_MODCK = 0. Therefore, designers should use clock configurations that fit this condition to achieve PCI-compliant AC timing.

Table 18. Clock Configurations for PCI Agent Mode (PCI_MODCK=0)

1,2

Bus Clock

(MHz)

Mode

3

MODCK_H-

MODCK[1-3]

PCI Clock

(MHz) low high

CPM

Multiplication

Factor

4

CPM Clock

(MHz) low high

CPU

Multiplication

Factor

5

CPU Clock

(MHz) low high

0000_000

0000_001

0000_010

0000_011

0000_100

0000_101

0000_110

0000_111

0001_001

66.7

66.7

55.5

62.5

50.0

59.5

53.6

50.0

66.7

66.7

66.7

66.7

66.7

66.7

66.7

66.7

2

2

3

3

3

3

4

4

Default Modes (MODCK_H=0000

133.3 133.3

133.3 133.3

166.7 200.0

187.5 200.0

150.0 200.0

178.6 200.0

214.3 266.6

200.0 266.6

2.5

3

3

4

3

3.5

3.5

3

166.7 166.7

200.0 200.0

166.7 200.0

250.0 266.6

180.0 240.0

250.0 280.0

250.0 311.1

240.0 320.0

Full Configuration Modes

Reserved

Bus

Division

Factor

2.5

2.5

3

2.5

3

3

2

2

low high

66.7

66.7

66.7

66.7

55.5

66.7

62.5

66.7

60.0

80.0

71.4

80.0

71.4

88.9

80.0

106.7

34

MPC8280 PowerQUICC II™ Family Hardware Specifications

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MOTOROLA

Freescale Semiconductor, Inc.

Clock Configuration Modes

Table 18. Clock Configurations for PCI Agent Mode (PCI_MODCK=0)

1,2

(Continued)

Mode

3

PCI Clock

(MHz) low high

CPM

Multiplication

Factor

4

CPM Clock

(MHz) low high

CPU

Multiplication

Factor

5

CPU Clock

(MHz) low high

MODCK_H-

MODCK[1-3]

0001_010

0001_011

0001_100 66.7

66.7

2 133.3 133.3

Reserved

Reserved

8 266.6 266.6

Bus

Division

Factor

4

Bus Clock

(MHz) low high

33.3

33.3

3

3

3

3

2.5

2.5

2.5

2.5

60.0

80.0

71.4

80.0

62.5

80.0

60.0

80.0

0010_001

0010_010

0010_011

0010_100

50.0

66.7

59.5

66.7

52.1

66.7

50.0

66.7

0011_000

0011_001

0011_010

0011_011

0011_100

0100_000

0100_001

0100_010

0100_011

0100_100

50.0

66.7

62.5

66.7

55.6

66.7

0101_000

0101_001

0101_010

0101_011

0101_100

0101_101

0101_110

50.0

66.7

50.0

66.7

50.0

66.7

50.0

66.7

50.0

66.7

50.0

66.7

50.0

66.7

0110_000

0110_001

0110_010

0110_011

50.0

66.7

53.6

66.7

50.0

66.7

3

3

3

5

5

5

5

5

5

5

4

4

4

150.0 200.0

178.6 200.0

156.3 200.0

150.0 200.0

3

3.5

4

4.5

Reserved

Reserved

Reserved

Reserved

Reserved

180.0 240.0

250.0 280.0

250.0 320.0

270.0 360.0

166.7 200.0

187.5 200.0

166.7 200.0

Reserved

3

Reserved

4

4.5

166.7 200.0

250.0 266.6

250.0 300.0

250.0 333.3

250.0 333.3

250.0 333.3

250.0 333.3

250.0 333.3

250.0 333.3

250.0 333.3

2.5

3

3.5

4

4.5

5

5.5

250.0 333.3

300.0 400.0

350.0 466.6

400.0 533.3

450.0 599.9

500.0 666.6

550.0 733.3

200.0 266.6

214.3 266.6

200.0 266.6

Reserved

3

3.5

4

200.0 266.6

250.0 311.1

266.7 355.5

3

3

3

2.5

2.5

2.5

2.5

2.5

2.5

2.5

3

3

3

66.7

88.9

71.4

88.9

66.7

88.9

66.7

66.7

62.5

66.7

55.6

66.7

100.0 133.3

100.0 133.3

100.0 133.3

100.0 133.3

100.0 133.3

100.0 133.3

100.0 133.3

35 MOTOROLA

MPC8280 PowerQUICC II™ Family Hardware Specifications

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Freescale Semiconductor, Inc.

Clock Configuration Modes

Table 18. Clock Configurations for PCI Agent Mode (PCI_MODCK=0)

1,2

(Continued)

Mode

3

MODCK_H-

MODCK[1-3]

0110_100

PCI Clock

(MHz) low high

50.0

66.7

CPM

Multiplication

Factor

4

4

CPM Clock

(MHz) low high

200.0 266.6

CPU

Multiplication

Factor

5

4.5

CPU Clock

(MHz) low high

300.0 400.0

Bus

Division

Factor

3

Bus Clock

(MHz) low high

66.7

88.9

3

3

3

3

2

2

2

2

83.3

100.0

75.0

100.0

75.0

100.0

75.0

100.0

0111_000

0111_001

0111_010

0111_011

55.5

66.7

50.0

66.7

50.0

66.7

50.0

66.7

1000_000

1000_001

1000_010

1000_011

1000_100

1000_101

66.7

66.7

50.0

66.7

59.5

66.7

52.1

66.7

50.0

66.7

1001_000

1001_001

1001_010

1001_011

1001_100

62.5

66.7

55.6

66.7

1010_000

1010_001

1010_010

1010_011

1010_100

50.0

66.7

53.6

66.7

50.0

66.7

50.0

66.7

1011_000

1011_001

1011_010

1011_011

1011_100

50.0

66.7

50.0

66.7

50.0

66.7

50.0

66.7

1100_101 50.0

66.7

4

4

4

4

6

4

4

4

4

3

3

3

3

3

4

4

166.7 200.0

150.0 200.0

150.0 200.0

150.0 200.0

2

2.5

3

3.5

166.7 200.0

187.5 250.0

225.0 300.0

262.5 350.0

200.0 200.0

150.0 200.0

178.6 200.0

156.3 200.0

150.0 200.0

Reserved

2.5

3

3.5

4

4.5

166.7 166.7

180.0 240.0

250.0 280.0

250.0 320.0

270.0 360.0

250.0 266.6

222.2 266.6

Reserved

Reserved

Reserved

4

4.5

250.0 266.6

250.0 300.0

200.0 266.6

214.3 266.6

200.0 266.6

200.0 266.6

Reserved

3

3.5

4

4.5

200.0 266.6

250.0 311.1

266.7 355.5

300.0 400.0

200.0 266.6

200.0 266.6

200.0 266.6

200.0 266.6

Reserved

2.5

3

3.5

4

200.0 266.6

240.0 320.0

280.0 373.3

320.0 426.6

300.0 400.0

4 400.0 533.3

4

4

2.5

2.5

2.5

2.5

3

3

3

3

3

2.5

2.5

2.5

2.5

2.5

80.0

80.0

60.0

80.0

71.4

80.0

62.5

80.0

60.0

80.0

62.5

66.7

55.6

66.7

66.7

88.9

71.4

88.9

66.7

88.9

66.7

88.9

80.0

106.7

80.0

106.7

80.0

106.7

80.0

106.7

100.0 133.3

36

MPC8280 PowerQUICC II™ Family Hardware Specifications

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Clock Configuration Modes

Table 18. Clock Configurations for PCI Agent Mode (PCI_MODCK=0)

1,2

(Continued)

Mode

3

PCI Clock

(MHz) low high

CPM

Multiplication

Factor

4

CPM Clock

(MHz) low high

CPU

Multiplication

Factor

5

CPU Clock

(MHz) low high

MODCK_H-

MODCK[1-3]

1100_110

1100_111

1101_000

50.0

66.7

50.0

66.7

50.0

66.7

6

6

6

300.0 400.0

300.0 400.0

300.0 400.0

4.5

5

5.5

450.0 599.9

500.0 666.6

550.0 733.3

Bus

Division

Factor

3

3

3

Bus Clock

(MHz) low high

100.0 133.3

100.0 133.3

100.0 133.3

1101_001

1101_010

1101_011

1101_100

1110_000

1110_001

1110_010

1110_011

50.0

50.0

50.0

50.0

50.0

66.7

66.7

66.7

66.7

66.7

50.0

66.7

50.0

66.7

50.0

66.7

5

5

5

5

6

6

6

6

300.0 400.0

300.0 400.0

300.0 400.0

300.0 400.0

250.0 333.3

250.0 333.3

250.0 333.3

250.0 333.3

2.5

3

3.5

4

3.5

4

4.5

5

420.0 559.9

480.0 639.9

540.0 719.9

600.0 799.9

312.5 416.6

375.0 500.0

437.5 583.3

500.0 666.6

2

2

2

2

2.5

2.5

2.5

2.5

120.0 160.0

120.0 160.0

120.0 160.0

120.0 160.0

125.0 166.7

125.0 166.7

125.0 166.7

125.0 166.7

1110_100

1110_101

1110_110

1110_111

50.0

50.0

50.0

50.0

66.7

66.7

66.7

66.7

5

5

5

5

250.0 333.3

250.0 333.3

250.0 333.3

250.0 333.3

4

4.5

5

5.5

333.3 444.4

375.0 500.0

416.7 555.5

458.3 611.1

3

3

3

3

83.3

111.1

83.3

111.1

83.3

111.1

83.3

111.1

1100_000 Reserved

1100_001 Reserved

1100_010 Reserved

1

“Low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency guarantees the required minimum CPU operating frequency. Minimum CPU frequency is determined by the clock mode.

For modes with a CPU multiplication factor

≤ 3, the minimum CPU frequency is 166 MHz. The minimum CPM frequency is 133 MHz.

For modes with a CPU multiplication factor

≥ 3.5, the minimum CPU frequency is 250 MHz. The minimum CPM frequency is as shown in the table.

“High” values are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s device.

2

As shown in Table 14, PCI_MODCK determines the PCI clock frequency range. Refer to Table 19 for lower

configurations.

3

MODCK_H = hard reset configuration word [28–31]. MODCK[1-3] = three hardware configuration pins.

4

CPM multiplication factor = CPM clock/PCI clock

5

CPU multiplication factor = Core PLL multiplication factor

37 MOTOROLA

MPC8280 PowerQUICC II™ Family Hardware Specifications

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Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Configuration Modes

Mode

3

MODCK_H-

MODCK[1-3]

Table 19. Clock Configurations for PCI Agent Mode (PCI_MODCK=1)

1,2

PCI Clock

(MHz) low high

CPM

Multiplication

Factor

4

CPM Clock

(MHz) low high

CPU

Multiplication

Factor

5

CPU Clock

(MHz) low high

Bus

Division

Factor

0000_000

0000_001

0000_010

0000_011

0000_100

0000_101

0000_110

0000_111

0001_001

0001_010

0001_011

0001_100

33.3

50.0

33.3

50.0

27.8

50.0

31.3

50.0

25.0

50.0

29.8

50.0

26.8

50.0

25.0

50.0

50.0

50.0

41.7

50.0

35.7

50.0

33.3

50.0

4

4

4

4

6

8

6

6

8

4

4

6

Default Modes (MODCK_H=0000)

133.3 200.0

133.3 200.0

166.7 300.0

187.5 300.0

150.0 300.0

178.6 300.0

214.3 400.0

200.0 400.0

3

Full Configuration Modes

200.0 200.0

166.7 200.0

5

6

142.9 200.0

133.3 200.0

7

8

2.5

3

3

4

3

3.5

3.5

166.7 250.0

200.0 300.0

166.7 300.0

250.0 400.0

180.0 360.0

250.0 420.0

250.0 466.7

240.0 480.0

250.0 250.0

250.0 300.0

250.0 350.0

266.7 400.0

4

4

4

4

3

2.5

2.5

3

2.5

2

2

3

Bus Clock

(MHz) low high

66.7

100.0

66.7

100.0

55.5

100.0

62.5

100.0

60.0

120.0

71.4

120.0

71.4

133.3

80.0

160.0

50.0

50.0

41.7

50.0

35.7

50.0

33.3

50.0

6

6

6

6

60.0

120.0

71.4

120.0

62.5

120.0

60.0

120.0

0010_001

0010_010

0010_011

0010_100

25.0

50.0

29.8

50.0

26.0

50.0

25.0

50.0

0011_000

0011_001

0011_010

0011_011

0011_100

50.0

50.0

46.9

50.0

41.7

50.0

0100_000

0100_001

0100_010

0100_011

0100_100

27.8

50.0

35.7

50.0

31.3

50.0

27.8

50.0

0101_000 27.8

50.0

6

6

6

6

5

4

4

4

150.0 300.0

178.6 300.0

156.3 300.0

150.0 300.0

3

3.5

4

4.5

180.0 360.0

250.0 420.0

250.0 480.0

270.0 540.0

200.0 200.0

187.5 200.0

166.7 200.0

Reserved

2.5

Reserved

4

4.5

166.7 166.7

250.0 266.7

250.0 300.0

2.5

2.5

2.5

2.5

3

3

3

166.7 300.0

214.3 300.0

187.5 300.0

166.7 300.0

Reserved

3

3.5

4

4.5

166.7 300.0

250.0 350.0

250.0 400.0

250.0 450.0

166.7 250.0

2.5

166.7 250.0

2.5

3

3

3

3

66.7

66.7

62.5

66.7

55.6

66.7

55.5

100.0

71.4

100.0

62.5

100.0

55.6

100.0

55.5

100.0

38

MPC8280 PowerQUICC II™ Family Hardware Specifications

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Go to: www.freescale.com

MOTOROLA

Freescale Semiconductor, Inc.

Clock Configuration Modes

Table 19. Clock Configurations for PCI Agent Mode (PCI_MODCK=1)

1,2

(Continued)

Mode

3

PCI Clock

(MHz) low high

CPM

Multiplication

Factor

4

CPM Clock

(MHz) low high

CPU

Multiplication

Factor

5

CPU Clock

(MHz) low high

MODCK_H-

MODCK[1-3]

0101_001

0101_010

0101_011

0101_100

0101_101

0101_110

27.8

50.0

35.7

50.0

31.3

50.0

27.8

50.0

27.8

50.0

27.8

50.0

5

5

5

5

5

5

139.0 250.0

178.6 250.0

156.3 250.0

138.9 250.0

133.3 250.0

133.3 250.0

3

3.5

4

4.5

5

5.5

167.7 300.0

250.0 350.0

250.0 400.0

250.0 450.0

266.7 500.0

305.3 550.0

Bus

Division

Factor

2.5

2.5

2.5

2.5

2.5

2.5

Bus Clock

(MHz) low high

55.5

100.0

71.4

100.0

62.5

100.0

55.6

100.0

55.5

100.0

55.5

100.0

0110_000

0110_001

0110_010

0110_011

0110_100

25.0

50.0

26.8

50.0

25.0

50.0

25.0

50.0

0111_000

0111_001

0111_010

0111_011

41.6

50.0

25.0

50.0

25.0

50.0

25.0

50.0

1000_000

1000_001

1000_010

1000_011

1000_100

1000_101

27.8

50.0

25.0

50.0

29.8

50.0

26.0

50.0

25.0

50.0

1001_000

1001_001

1001_010

1001_011

1001_100

31.3

50.0

27.8

50.0

1010_000

1010_001 25.0

50.0

6

6

6

6

8

8

8

8

6

6

6

6

6

8

8

8

200.0 400.0

214.3 400.0

200.0 400.0

200.0 400.0

166.7 300.0

150.0 300.0

150.0 300.0

150.0 300.0

Reserved

3

3.5

4

4.5

2

2.5

3

3.5

200.0 400.0

250.0 466.7

266.7 533.3

300.0 600.0

166.7 300.0

187.5 375.0

225.0 450.0

262.5 525.0

166.7 300.0

150.0 300.0

178.6 300.0

156.3 300.0

150.0 300.0

Reserved

2.5

3

3.5

4

4.5

166.7 300.0

180.0 360.0

250.0 420.0

250.0 480.0

270.0 540.0

2.5

2.5

2.5

2.5

2.5

2

2

2

2

3

3

3

3

250.0 400.0

222.2 400.0

Reserved

Reserved

Reserved

4

4.5

250.0 400.0

250.0 450.0

200.0 400.0

Reserved

3 200.0 400.0

4

4

3

66.7

133.3

71.4

133.3

66.7

133.3

66.7

133.3

83.2

150.0

75.0

150.0

75.0

150.0

75.0

150.0

66.7

120.0

60.0

120.0

71.4

120.0

62.5

120.0

60.0

120.0

62.5

100.0

55.6

100.0

66.7

133.3

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1011_000

1011_001

1011_010

1011_011

1011_100

25.0

50.0

25.0

50.0

25.0

50.0

25.0

50.0

1100_101

1100_110

1100_111

1101_000

31.3

50.0

27.8

50.0

25.0

50.0

25.0

50.0

1101_001

1101_010

1101_011

1101_100

29.8

50.0

26.0

50.0

25.0

50.0

25.0

50.0

1110_000

1110_001

1110_010

1110_011

33.3

50.0

25.0

50.0

28.6

50.0

25.0

50.0

1110_100

1110_101

1110_110

1110_111

37.5

50.0

33.3

50.0

30.0

50.0

27.3

50.0

1100_000

1100_001

1100_010

Freescale Semiconductor, Inc.

Clock Configuration Modes

Table 19. Clock Configurations for PCI Agent Mode (PCI_MODCK=1)

1,2

(Continued)

Mode

3

PCI Clock

(MHz) low high

CPM

Multiplication

Factor

4

CPM Clock

(MHz) low high

CPU

Multiplication

Factor

5

CPU Clock

(MHz) low high

MODCK_H-

MODCK[1-3]

1010_010

1010_011

1010_100

26.8

50.0

25.0

50.0

25.0

50.0

8

8

8

214.3 400.0

200.0 400.0

200.0 400.0

3.5

4

4.5

250.0 466.7

266.7 533.3

300.0 600.0

Bus

Division

Factor

3

3

3

Bus Clock

(MHz) low high

71.4

133.3

66.7

133.3

66.7

133.3

5

5

5

5

6

6

6

6

5

5

5

5

6

6

6

6

8

8

8

8

200.0 400.0

200.0 400.0

200.0 400.0

200.0 400.0

Reserved

2.5

3

3.5

4

200.0 400.0

240.0 480.0

280.0 560.0

320.0 640.0

2.5

2.5

2.5

2.5

187.5 300.0

166.7 300.0

150.0 300.0

150.0 300.0

178.6 300.0

156.3 300.0

150.0 300.0

150.0 300.0

4

4.5

5

5.5

3.5

4

4.5

5

250.0 400.0

250.0 450.0

250.0 500.0

275.0 550.0

250.0 420.0

250.0 480.0

270.0 540.0

300.0 600.0

3

3

3

3

2.5

2.5

2.5

2.5

133.3 250.0

125.0 250.0

142.9 250.0

125.0 250.0

187.5 250.0

166.7 250.0

150.0 250.0

136.4 250.0

2.5

3

3.5

4

4

4.5

5

5.5

Reserved

Reserved

Reserved

166.7 312.5

187.5 375.0

250.0 437.5

250.0 500.0

250.0 333.3

250.0 375.0

250.0 416.7

250.0 458.3

3

3

3

3

2

2

2

2

80.0

160.0

80.0

160.0

80.0

160.0

80.0

160.0

62.5

100.0

55.6

100.0

50.0

100.0

50.0

100.0

71.4

120.0

62.5

120.0

60.0

120.0

60.0

120.0

66.7

125.0

62.5

125.0

71.4

125.0

62.5

125.0

62.5

83.3

55.6

83.3

50.0

83.3

45.5

83.3

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MPC8280 PowerQUICC II™ Family Hardware Specifications

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Pinout

1

“Low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency guarantees the required minimum CPU operating frequency. Minimum CPU frequency is determined by the clock mode.

For modes with a CPU multiplication factor

≤ 3, the minimum CPU frequency is 166 MHz. The minimum CPM frequency is 133 MHz.

For modes with a CPU multiplication factor

≥ 3.5, the minimum CPU frequency is 250 MHz. The minimum CPM frequency is as shown in the table.

“High” values are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s device.

2

As shown in Table 14, PCI_MODCK determines the PCI clock range. Refer to Table 18 for higher range configurations.

3

MODCK_H = hard reset configuration word [28–31]. MODCK[1-3] = three hardware configuration pins.

4

CPM multiplication factor = CPM clock/PCI clock

5

CPU multiplication factor = Core PLL multiplication factor

8 Pinout

This section provides the pin assignments and pinout lists for both HiP7 PowerQUICC II packages.

8.1

ZU Package—MPC8280 and MPC8270

The following figures and table represent the standard 480 TBGA package. For information on the alternate

package, refer to Section 8.2, “VR and ZQ Packages—MPC8275 and MPC8270” on page 56.

Figure 13 shows the pinout of the ZU package as viewed from the top surface.

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Pinout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

V

W

Y

AA

T

U

P

R

AB

AC

AD

AE

AF

AG

AH

AJ

L

M

N

J

K

G

H

A

B

C

D

E

F

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Not to Scale

V

W

Y

AA

T

U

P

R

AB

AC

AD

AE

AF

AG

AH

AJ

L

M

N

J

K

G

H

A

B

C

D

E

F

Figure 13. Pinout of the 480 TBGA Package (View from Top)

Figure 14 shows the side profile of the TBGA package to indicate the direction of the top surface view.

View

Polymide Tape

Copper Heat Spreader

(Oxidized for Insulation)

Die

Attach

Etched

Cavity

Pressure Sensitive

Adhesive

Soldermask

1.27 mm Pitch

Die

Glob-Top Filled Area

Glob-Top Dam

Copper Traces

Wire Bonds

Figure 14. Side View of the TBGA Package

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Pinout

Table 20 shows the pinout list of the MPC8280 and MPC8270. Table 21 defines conventions and acronyms

used in Table 20.

Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List

Pin Name

Ball

A24

A25

A26

A27

A20

A21

A22

A23

A16

A17

A18

A19

A12

A13

A14

A15

A8

A9

A10

A11

A4

A5

A6

A7

A0

A1

A2

A3

BR

BG

ABB/IRQ2

TS

MPC8280/MPC8270 MPC8280 only

P4

P3

P2

P1

N4

N3

N2

N1

L2

L1

M5

N5

K1

L5

L4

L3

J1

K4

K3

K2

J5

J4

J3

J2

G1

H5

H2

H1

W5

F4

E2

E3

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Pinout

Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List (Continued)

Pin Name

Ball

MPC8280/MPC8270

D10

D11

D12

D13

D6

D7

D8

D9

D14

D15

D2

D3

D4

D5

DBG

DBB/IRQ3

D0

D1

TT4

TBST

TSIZ0

TSIZ1

TSIZ2

TSIZ3

AACK

ARTRY

TT0

TT1

TT2

TT3

A28

A29

A30

A31

MPC8280 only

B15

B13

A11

E9

A6

B5

A20

E17

B7

B4

A16

A13

E12

D9

V1

V2

B20

A18

D2

F5

F3

E1

F2

D3

C1

E4

F1

G4

G3

G2

R1

R3

R5

R4

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D44

D45

D46

D47

D40

D41

D42

D43

D48

D49

D36

D37

D38

D39

D32

D33

D34

D35

D28

D29

D30

D31

D24

D25

D26

D27

D20

D21

D22

D23

D16

D17

D18

D19

Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List (Continued)

Pin Name

Ball

MPC8280/MPC8270 MPC8280 only

A10

D8

B6

C4

D18

A17

A14

B12

C18

E16

D11

C8

E7

A3

E18

B17

A15

A12

C11

B8

A4

E6

C19

C17

C15

D13

B11

A8

A5

C5

D19

D17

D15

C13

Pinout

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Pinout

Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List (Continued)

Pin Name

MPC8280/MPC8270

D54

D55

D56

D57

D50

D51

D52

D53

D58

D59

D60

D61

D62

D63

DP0/RSRV/EXT_BR2

IRQ1/DP1/EXT_BG2

IRQ2/DP2/TLBISYNC/EXT_DBG2

IRQ3/DP3/CKSTP_OUT/EXT_BR3

IRQ4/DP4/CORE_SRESET/EXT_BG3

IRQ5/CINT/DP5/TBEN/EXT_DBG3

IRQ6/DP6/CSE0

IRQ7/DP7/CSE1

PSDVAL

TA

TEA

GBL/IRQ1

CI/BADDR29/IRQ2

WT/BADDR30/IRQ3

L2_HIT/IRQ4

CPU_BG/BADDR31/IRQ5/CINT

CPU_DBG

CPU_BR

CS0

CS1

MPC8280 only

Ball

Y4

U4

R2

Y3

V5

W1

U2

U3

F25

C29

A21

E20

V3

C22

E21

D21

C21

B21

D6

C2

B22

A22

E14

D12

C10

E8

C6

D5

B18

B16

B14

C12

B10

A7

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Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List (Continued)

Pin Name

Ball

MPC8280/MPC8270

CS6

CS7

CS8

CS9

CS2

CS3

CS4

CS5

CS10/BCTL1

CS11/AP0

BADDR27

BADDR28

ALE

BCTL0

PWE0/PSDDQM0/PBS0

PWE1/PSDDQM1/PBS1

PWE2/PSDDQM2/PBS2

PWE3/PSDDQM3/PBS3

PWE4/PSDDQM4/PBS4

PWE5/PSDDQM5/PBS5

PWE6/PSDDQM6/PBS6

PWE7/PSDDQM7/PBS7

PSDA10/PGPL0

PSDWE/PGPL1

POE/PSDRAS/PGPL2

PSDCAS/PGPL3

PGTA/PUPMWAIT/PGPL4/PPBS

PSDAMUX/PGPL5

LWE0/LSDDQM0/LBS0/PCI_CFG0

LWE1/LSDDQM1/LBS1/PCI_CFG1

LWE2/LSDDQM2/LBS2/PCI_CFG2

LWE3/LSDDQM3/LBS3/PCI_CFG3

LSDA10/LGPL0/PCI_MODCKH0

LSDWE/LGPL1/PCI_MODCKH1

MPC8280 only

H28

H27

H26

G29

A24

B23

A23

D22

D27

C28

B25

A25

E23

B24

D24

C24

B26

A26

T2

A27

C25

E24

F29

G28

T5

U1

F28

G25

D29

E29

E27

E28

F26

F27

Pinout

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Freescale Semiconductor, Inc.

Pinout

Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List (Continued)

Pin Name

MPC8280/MPC8270

LOE/LSDRAS/LGPL2/PCI_MODCKH2

LSDCAS/LGPL3/PCI_MODCKH3

LGTA/LUPMWAIT/LGPL4/LPBS

LGPL5/LSDAMUX/PCI_MODCK

LWR

L_A14/PAR

L_A15/FRAME/SMI

L_A16/TRDY

L_A17/IRDY/CKSTP_OUT

L_A18/STOP

L_A19/DEVSEL

L_A20/IDSEL

L_A21/PERR

L_A22/SERR

L_A23/REQ0

L_A24/REQ1/HSEJSW

L_A25/GNT0

L_A26/GNT1/HSLED

L_A27/GNT2/HSENUM

L_A28/RST/CORE_SRESET

L_A29/INTA

L_A30/REQ2

L_A31/DLLOUT

LCL_D0/AD0

LCL_D1/AD1

LCL_D2/AD2

LCL_D3/AD3

LCL_D4/AD4

LCL_D5/AD5

LCL_D6/AD6

LCL_D7/AD7

LCL_D8/AD8

LCL_D9/AD9

LCL_D10/AD10

MPC8280 only

Ball

J25

K25

L29

L27

J29

J28

J27

J26

L26

L25

AA26

N25

AA25

AB29

AB28

P25

AB27

H29

R26

R29

R28

W29

P28

N26

AA27

P29

D28

N27

T29

R27

E26

D25

C26

B27

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Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List (Continued)

Pin Name

Ball

MPC8280/MPC8270

LCL_D11/AD11

LCL_D12/AD12

LCL_D13/AD13

LCL_D14/AD14

LCL_D15/AD15

LCL_D16/AD16

LCL_D17/AD17

LCL_D18/AD18

LCL_D19/AD19

LCL_D20/AD20

LCL_D21/AD21

LCL_D22/AD22

LCL_D23/AD23

LCL_D24/AD24

LCL_D25/AD25

LCL_D26/AD26

LCL_D27/AD27

LCL_D28/AD28

LCL_D29/AD29

LCL_D30/AD30

LCL_D31/AD31

LCL_DP0/C0/BE0

LCL_DP1/C1/BE1

LCL_DP2/C2/BE2

LCL_DP3/C3/BE3

IRQ0/NMI_OUT

IRQ7/INT_OUT/APE

TRST

1

TCK

TMS

TDI

TDO

TRIS

PORESET

1

MPC8280 only

W28

T1

D1

AH3

AG5

AJ3

AE6

AF5

AB4

AG6

Y29

Y28

Y25

AA29

AA28

L28

N28

T28

V26

W27

W26

W25

U25

V29

V28

V27

N29

T25

U27

U26

M29

M28

M27

M26

Pinout

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Pinout

MPC8280/MPC8270

HRESET

SRESET

QREQ

RSTCONF

MODCK1/AP1/TC0/BNKSEL0

MODCK2/AP2/TC1/BNKSEL1

MODCK3/AP3/TC2/BNKSEL2

CLKIN1

PA0/RESTART1/DREQ3

PA1/REJECT1/DONE3

PA2/CLK20/DACK3

PA3/CLK19/DACK4/L1RXD1A2

PA4/REJECT2/DONE4

PA5/RESTART2/DREQ4

PA6/FCC2_RXADDR3

PA7/SMSYN2/FCC2_TXADDR3

PA8/SMRXD2/FCC2_TXADDR4

PA9/SMTXD2

PA10/MSNUM5

PA11/MSNUM4

PA12/MSNUM3

PA13/MSNUM2

Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List (Continued)

Pin Name

Ball

PA14/FCC1_MII_HDLC_RXD3

PA15/FCC1_MII_HDLC_RXD2

PA16/FCC1_MII_HDLC_RXD1/

FCCI_RMII_RXD1

PA17/FCC1_MII_HDLC_RXD0/

FCC1_MII_TRAN_RXD/

FCCI_RMII_RXD0

PA18/FCC1_MII_HDLC_TXD0/

FCC1_MII_TRAN_TXD/

FCC1_RMII_TXD0

MPC8280 only

FCC2_UTM_TXADDR2

FCC2_UTM_TXADDR1

FCC2_UTM_TXADDR0

FCC2_UTM_RXADDR0

FCC2_UTM_RXADDR1

FCC2_UTM_RXADDR2/FCC1_UT_RX

PRTY

L1RSYNCA1

L1TSYNCA1/L1GNTA1

L1RXD0A1/L1RXDA1

L1TXD0A1

FCC1_UT8_RXD0/FCC1_UT16_RXD8

FCC1_UT8_RXD1/FCC1_UT16_RXD9

FCC1_UT8_RXD2/

FCC1_UT16_RXD10

FCC1_UT8_RXD3/

FCC1_UT16_RXD11

FCC1_UT8_RXD4/

FCC1_UT16_RXD12

FCC1_UT8_RXD5/

FCC1_UT16_RXD13

FCC1_UT8_RXD6/

FCC1_UT16_RXD14

FCC1_UT8_RXD7/

FCC1_UT16_RXD15

FCC1_UT8_TXD7/FCC1_UT16_TXD15

AE24

2

AH25

2

AF23

2

AH23

2

AE22

2

AH22

2

AJ21

2

AH5

AF6

AA3

AJ4

W2

W3

W4

AH4

AC29

2

AC25

2

AE28

2

AG29

2

AG28

2

AG26

2

AH20

2

AG19

2

AF18

2

AF17

2

AE16

2

AJ16

2

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Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List (Continued)

Pin Name

MPC8280/MPC8270 MPC8280 only

PA19/FCC1_MII_HDLC_TXD1/

FCC1_RMII_TXD1

PA20/FCC1_MII_HDLC_TXD2

PA21/FCC1_MII_HDLC_TXD3

PA22

PA23

PA24/MSNUM1

PA25/MSNUM0

PA26/FCC1_RMII_RX_ER

FCC1_UT8_TXD6/FCC1_UT16_TXD14

FCC1_UT8_TXD5/FCC1_UT16_TXD13

FCC1_UT8_TXD4/FCC1_UT16_TXD12

FCC1_UT8_TXD3/FCC1_UT16_TXD11

FCC1_UT8_TXD2/FCC1_UT16_TXD10

FCC1_UT8_TXD1/FCC1_UT16_TXD9

FCC1_UT8_TXD0/FCC1_UT16_TXD8

FCC1_UTM_RXCLAV/

FCC1_UTS_RXCLAV

FCC1_UT_RXSOC PA27/FCC1_MII_RX_DV/

FCC1_RMII_CRS_DV

PA28/FCC1_MII_TX_EN/

FCC1_RMII_TX_EN

PA29/FCC1_MII_TX_ER

PA30/FCC1_MII_CRS/FCC1_RTS

PA31/FCC1_MII_COL

FCC1_UTM_RXENB/

FCC1_UTS_RXENB

FCC1_UT_TXSOC

FCC1_UTM_TXCLAV/

FCC1_UTS_TXCLAV

FCC1_UTM_TXENB/

FCC1_UTS_TXENB

FCC2_UT8_RXD0 PB4/FCC3_MII_HDLC_TXD3/

L1RSYNCA2/FCC3_RTS

PB5/FCC3_MII_HDLC_TXD2/

L1TSYNCA2/L1GNTA2

PB6/FCC3_MII_HDLC_TXD1/

FCC3_RMII_TXD1/

L1RXDA2/L1RXD0A2

PB7/FCC3_MII_HDLC_TXD0/

FCC3_RMII_TXD0/

FCC3_TXD/L1TXDA2/L1TXD0A2

PB8/FCC3_MII_HDLC_RXD0/

FCC3_RMII_RXD0/

FCC3_RXD/TXD3

FCC2_UT8_RXD1

FCC2_UT8_RXD2

FCC2_UT8_RXD3

FCC2_UT8_TXD3/L1RSYNCD1

PB9/FCC3_MII_HDLC_RXD1/

FCC3_RMII_RXD1/L1TXD2A2

PB10/FCC3_MII_HDLC_RXD2

PB11/FCC3_MII_HDLC_RXD3

FCC2_UT8_TXD2/L1TSYNCD1/

L1GNTD1

FCC2_UT8_TXD1/L1RXDD1

FCC2_UT8_TXD0/L1TXDD1

PB12/FCC3_MII_CRS/TXD2

PB13/FCC3_MII_COL/L1TXD1A2

L1CLKOB1/L1RSYNCC1

L1RQB1/L1TSYNCC1/L1GNTC1

PB14/FCC3_MII_RMII_TX_EN//RXD3 L1RXDC1

PB15/FCC3_MII_TX_ER/RXD2 L1TXDC1

Ball

AG15

2

AF7

2

AD5

2

AF1

2

AD3

2

AB5

2

AD28

2

AD26

2

AD25

2

AE26

2

AH27

2

AG24

2

AJ13

2

AE13

2

AF12

2

AG11

2

AH9

2

AJ8

2

AH7

2

AH24

2

AJ24

2

AG22

2

AH21

2

AG20

2

AF19

2

Pinout

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Pinout

Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List (Continued)

Pin Name

MPC8280/MPC8270 MPC8280 only

PB16/FCC3_MII_RMII_RX_ER/CLK18 L1CLKOA1

PB17/FCC3_MII_RX_DV/CLK17/

FCC3_RMII_CRS_DV

L1RQA1

FCC2_UT8_RXD4 PB18/FCC2_MII_HDLC_RXD3/

L1CLKOD2/L1RXD2A2

PB19FCC2_MII_HDLC_RXD2/

L1RQD2/L1RXD3A2

FCC2_UT8_RXD5

PB20/FCC2_MII_HDLC_RMII_RXD1/

L1RSYNCD2

PB21//FCC2_MII_HDLC_RMII_RXD0/

FCC2_TRAN_RXD/L1TSYNCD2/

L1GNTD2

FCC2_UT8_RXD6/L1TXD1A1

FCC2_UT8_RXD7/L1TXD2A1

PB22/FCC2_MII_HDLC_TXD0/

FCC2_TXD/FCC2_RMII_TXD0/

L1RXDD2

PB23/FCC2_MII_HDLC_TXD1/

L1RXD2A1/L1TXDD2/

FCC2_RMII_TXD1

FCC2_UT8_TXD7/L1RXD1A1

FCC2_UT8_TXD6/L1RXD2A1

PB24/FCC2_MII_HDLC_TXD2/

L1RSYNCC2

PB25/FCC2_MII_HDLC_TXD3/

L1TSYNCC2/L1GNTC2

FCC2_UT8_TXD5/L1RXD3A1

FCC2_UT8_TXD4/L1TXD3A1

PB26/FCC2_MII_CRS/L1RXDC2

PB27/FCC2_MII_COL/L1TXDC2

FCC2_UT8_TXD1

FCC2_UT8_TXD0

PB28/FCC2_MII_RX_ER/

FCC2_RMII_RX_ER/FCC2_RTS/

L1TSYNCB2/L1GNTB2/TXD1

PB29/L1RSYNCB2/FCC2_MII_TX_EN/

FCC2_RMII_TX_EN

FCC2_UTM_RXCLAV/

FCC2_UTS_RXCLAV

FCC2_UT_TXSOC PB30/FCC2_MII_RX_DV/

FCC2_RMII_CRS_DV/L1RXDB2

PB31/FCC2_MII_TX_ER/L1TXDB2 FCC2_UT_RXSOC

PC0/DREQ1/BRGO7/SMSYN2/

L1CLKOA2

PC1/DREQ2/BRGO6/L1RQA2/ SPISEL

PC2/FCC3_CD/DONE2 FCC2_UT8_TXD3

FCC2_UT8_TXD2 PC3/FCC3_CTS/DACK2/CTS4/

USB_RP

PC4/SI2_L1ST4/FCC2_CD FCC2_UTM_RXENB/

FCC2_UTS_RXENB

Ball

AJ18

2

AJ17

2

AE14

2

AF13

2

AG12

2

AH11

2

AH16

2

AE15

2

AJ9

2

AE9

2

AJ7

2

AH6

2

AE3

2

AE2

2

AC5

2

AC4

2

AB26

2

AD29

2

AE29

2

AE27

2

AF27

2

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Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List (Continued)

Pin Name

MPC8280/MPC8270 MPC8280 only

PC5/SI2_L1ST3/FCC2_CTS

PC6/FCC1_CD

PC7/FCC1_CTS

FCC2_UTM_TXCLAV/

FCC2_UTS_TXCLAV

L1CLKOC1/FCC1_UTM_RXADDR2/

FCC1_UTS_RXADDR2/

FCC1_UTM_RXCLAV1

L1RQC1/FCC1_UTM_TXADDR2/

FCC1_UTS_TXADDR2/

FCC1_UTM_TXCLAV1

FCC1_UT16_TXD0 PC8/CD4/RENA4/SI2_L1ST2/CTS3/

USBRN

PC9/CTS4/CLSN4/SI2_L1ST1/

L1TSYNCA2/L1GNTA2/USB_RP

PC10/CD3/RENA3

FCC1_UT16_TXD1

PC11/CTS3/CLSN3/L1TXD3A2

PC12/CD2/RENA2

PC13/CTS2/CLSN2

PC14/CD1/RENA1

PC15/CTS1/CLSN1/SMTXD2

PC16/CLK16/TIN4

PC17/CLK15/TIN3/BRGO8

PC18/CLK14/TGATE2

PC19/CLK13/BRGO7/SPICLK

PC20/CLK12/TGATE1/USB_OE

PC21/CLK11/BRGO6

PC22/CLK10/DONE1/FCC1_UT_TXPRTY

FCC1_UT16_TXD2/SI1_L1ST4/

FCC2_UT8_RXD3

L1CLKOD1/FCC2_UT8_RXD2

SI1_L1ST3/FCC1_UTM_RXADDR1/

FCC1_UTS_RXADDR1

L1RQD1/FCC1_UTM_TXADDR1/

FCC1_UTS_TXADDR1

FCC1_UTM_RXADDR0/

FCC1_UTS_RXADDR0

FCC1_UTM_TXADDR0/

FCC1_UTS_TXADDR0

PC23/CLK9/BRGO5/DACK1

PC24/CLK8/TOUT4

PC25/CLK7/BRGO4

PC26/CLK6/TOUT3/TMCLK

PC27/FCC3_TXD/FCC3_MII_TXD0/

FCC3_RMII_TXD0/CLK5/BRGO3

PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2/

FCC2_RXADDR4

PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1

FCC2_UT8_TXD3

FCC2_UT8_TXD2

Ball

AF24

2

AJ26

2

AJ25

2

AF22

2

AE21

2

AF20

2

AE19

2

AE18

2

AH18

2

AH17

2

AG16

2

AF3

2

AF2

2

AF15

2

AJ15

2

AH14

2

AG13

2

AH12

2

AJ11

2

AG10

2

AE10

2

AF9

2

AE8

2

AJ6

2

AG2

2

Pinout

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Pinout

Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List (Continued)

MPC8280/MPC8270

PC30/CLK2/TOUT1

PC31/CLK1/BRGO1

PD4/BRGO8/FCC3_RTS/SMRXD2

PD5/DONE1

PD6/DACK1

PD7/SMSYN1/FCC1_TXCLAV2

PD8/SMRXD1/BRGO5

PD9/SMTXD1/BRGO3

PD10/L1CLKOB2/BRGO4

PD11/L1RQB2

PD12

PD13

PD14/L1CLKOC2/I2CSCL

PD15/L1RQC2/I2CSDA

PD16/SPIMISO

PD17/BRGO2/SPIMOSI

PD18/SPICLK

PD19/SPISEL/BRGO1

Pin Name

MPC8280 only

FCC2_UT8_TXD3

L1TSYNCD1/L1GNTD1

FCC1_UT16_TXD3

FCC1_UT16_TXD4

FCC1_UTM_TXADDR3/

FCC1_UTS_TXADDR3/

FCC2_UTM_TXADDR4

FCC2_UTS_TXADDR1

FCC2_UT_TXPRTY

FCC2_UT_RXPRTY

FCC2_UT8_RXD1/L1RSYNCB1

FCC2_UT8_RXD0/L1TSYNCB1/

L1GNTB1

SI1_L1ST2/L1RXDB1

SI1_L1ST1/L1TXDB1

FCC1_UT16_RXD0

FCC1_UT16_RXD1

FCC1_UT_TXPRTY/L1TSYNCC1/

L1GNTC1

FCC1_UT_RXPRTY

FCC1_UTM_RXADDR4/

FCC1_UTS_RXADDR4/

FCC1_UTM_RXCLAV3/

FCC2_UTM_RXADDR3/

FCC2_UTS_RXADDR0

FCC1_UTM_TXADDR4/

FCC1_UTS_TXADDR4/

FCC1_UTM_TXCLAV3/

FCC2_UTM_TXADDR3/

FCC2_UTS_TXADDR0

FCC1_UT16_RXD2 PD20/RTS4/TENA4/L1RSYNCA2/

USB_TP

PD21/TXD4/L1RXD0A2/L1RXDA2/

USB_TN

PD22/RXD4L1TXD0A2/L1TXDA2/

USB_RXD

PD23/RTS3/TENA3

PD24/TXD3

PD25/RXD3

FCC1_UT16_RXD3

FCC1_UT16_TXD5

FCC1_UT16_RXD4/L1RSYNCD1

FCC1_UT16_RXD5/L1RXDD1

FCC1_UT16_TXD6/L1TXDD1

Ball

AG25

2

AH26

2

AJ27

2

AJ23

2

AG23

2

AJ22

2

AE20

2

AJ20

2

AG18

2

AG17

2

AF16

2

AH15

2

AJ14

2

AH13

2

AJ12

2

AE12

2

AF10

2

AG9

2

AE1

2

AD1

2

AC28

2

AD27

2

AF29

2

AF28

2

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Pinout

Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List (Continued)

Pin Name

Ball

MPC8280/MPC8270 MPC8280 only

PD26/RTS2/TENA2

PD27/TXD2

PD28/RXD2

PD29/RTS1/TENA1

PD30/TXD1

FCC1_UT16_RXD6/L1RSYNCC1

FCC1_UT16_RXD7/L1RXDC1

FCC1_UT16_TXD7/L1TXDC1

FCC1_UTM_RXADDR3/

FCC1_UTS_RXADDR3/

FCC1_UTM_RXCLAV2/

FCC2_UTM_RXADDR4/

FCC2_UTS_RXADDR1

FCC2_UTM_TXENB/

FCC2_UTS_TXENB

AH8

AG7

AE4

AG1

AD4

2

2

2

2

2

PD31/RXD1

VCCSYN

VCCSYN1

CLKIN2

SPARE4

3

PCI_MODE

4

SPARE6

3

No connect

5

AD2

AB3

B9

2

AE11

U5

AF25

V4

AA1, AG4

I/O power AG21, AG14, AG8, AJ1, AJ2,

AH1, AH2, AG3, AF4, AE5, AC27,

Y27, T27, P27, K26, G27, AE25,

AF26, AG27, AH28, AH29, AJ28,

AJ29, C7, C14, C16, C20, C23,

E10, A28, A29, B28, B29, C27,

D26, E25, H3, M4, T3, AA4, A1,

A2, B1, B2, C3, D4, E5

Core power

Ground

U28, U29, K28, K29, A9, A19,

B19, M1, M2, Y1, Y2, AC1, AC2,

AH19, AJ19, AH10, AJ10, AJ5

AA5, AB1

6

, AB2

7

, AF21, AF14,

AF8, AE7, AF11, AE17, AE23,

AC26, AB25, Y26, V25, T26, R25,

P26, M25, K27, H25, G26, D7,

D10, D14, D16, D20, D23, C9,

E11, E13, E15, E19, E22, B3, G5,

H4, K5, M3, P5, T4, Y5, AA2, AC3

1

Should be tied to VDDH via a 2K

Ω external pull-up resistor.

2

The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive

DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs.

3

Must be pulled down or left floating.

4

If PCI is not desired, must be pulled up or left floating.

5

Sphere is not connected to die.

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6

GNDSYN (AB1): This pin exists as a separate ground signal in MPC826x(A) devices; it does not exist as a separate

ground signal on the MPC8280. New designs must connect AB1 to GND and follow the suggestions in Section 4.3,

“Layout Practices.” Old designs in which the MPC8280 is used as a drop-in replacement can leave the pin connected

to GND with the noise filtering capacitors.

7

XFC (AB2) pin: This pin is used in MPC826x(A) devices; it is not used in MPC8280 because there is no need for external capacitor to operate the PLL. New designs should connect AB2 (XFC) pin to GND. Old designs in which the

MPC8280 is used as a drop-in replacement can leave the pin connected to the current capacitor.

Symbols used in Table 20 are described in Table 21.

Table 21. Symbol Legend

Symbol

OVERBAR

UTM

UTS

UT8

UT16

MII

RMII

Meaning

Signals with overbars, such as TA, are active low.

Indicates that a signal is part of the UTOPIA master interface.

Indicates that a signal is part of the UTOPIA slave interface.

Indicates that a signal is part of the 8-bit UTOPIA interface.

Indicates that a signal is part of the 16-bit UTOPIA interface.

Indicates that a signal is part of the media independent interface.

Indicates that a signal is part of the reduced media independent interface.

8.2

VR and ZQ Packages—MPC8275 and MPC8270

The following figures and table represent the alternate 516 PBGA package. For information on the standard

package for the MPC8280 and the MPC8270, refer to Section 8.1, “ZU Package—MPC8280 and

MPC8270” on page 41.

Figure 15 shows the pinout of the VR and ZQ packages as viewed from the top surface.

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Pinout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

V

W

Y

AA

T

U

P

R

AB

AC

AD

AE

AF

L

M

N

J

K

G

H

A

B

C

D

E

F

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

V

W

Y

AA

T

U

P

R

AB

AC

AD

AE

AF

L

M

N

J

K

G

H

A

B

C

D

E

F

Not to Scale

Figure 15. Pinout of the 516 PBGA Package (View from Top)

Figure 16 shows the side profile of the PBGA package to indicate the direction of the top surface view.

Transfer molding compound

Die attach

Wire bonds

Ball bond

Plated substrate via

DIE

Screen-printed solder mask

Cu substrate traces

1 mm pitch

Figure 16. Side View of the PBGA Package Remove

BT resin glass epoxy

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Pinout

NOTE: Temperature Reflow for the VR Package

In the VR package, sphere composition is lead-free (refer to Table 2). This

requires higher temperature reflow than what is required for other

PowerQUICC II packages. Users should consult “Motorola PowerQUICC II™

Pb-Free Packaging Information” (MPC8250PBFREEPKG) available at www.motorola.com/semiconductors.

Table 22 shows the pinout list of the MPC8275 and MPC8270. Table 21 defines conventions and acronyms

used in Table 22.

Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List

Pin Name

Ball

A8

A9

A10

A11

A4

A5

A6

A7

A0

A1

A2

A3

BR

BG

ABB/IRQ2

TS

A16

A17

A18

A19

A12

A13

A14

A15

A20

A21

MPC8275/MPC8270 MPC8275 only

B5

B6

C7

C8

A4

D7

D8

C6

D5

E8

C4

B4

C16

D2

C1

D1

B8

C9

A7

B9

A6

D9

F11

B7

E11

A8

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Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (Continued)

Pin Name

Ball

MPC8275/MPC8270

D4

D5

D6

D7

D0

D1

D2

D3

D8

D9

TSIZ0

TSIZ1

TSIZ2

TSIZ3

AACK

ARTRY

DBG

DBB/IRQ3

A30

A31

TT0

TT1

TT2

TT3

TT4

TBST

A26

A27

A28

A29

A22

A23

A24

A25

MPC8275 only

N3

K5

J4

G1

W4

Y1

V1

P4

AB1

U4

D3

C2

A14

C15

E3

E2

E1

E4

F8

A3

C3

F5

B12

B13

E7

B3

B11

C12

D12

A10

D11

B10

C11

A9

Pinout

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D38

D39

D40

D41

D34

D35

D36

D37

D42

D43

D30

D31

D32

D33

D26

D27

D28

D29

D22

D23

D24

D25

D18

D19

D20

D21

D14

D15

D16

D17

D10

D11

D12

D13

Pinout

Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (Continued)

Pin Name

Ball

MPC8275/MPC8270 MPC8275 only

H3

F2

Y2

U3

U1

P2

M4

K4

T2

N2

H2

G5

AA1

V2

P5

P3

M3

K3

J1

G4

U5

T5

T3

T1

M2

K2

J5

G3

AA2

W1

U2

N6

N1

L1

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Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (Continued)

Pin Name

MPC8275/MPC8270

D56

D57

D58

D59

D52

D53

D54

D55

D48

D49

D50

D51

D44

D45

D46

D47

D60

D61

D62

D63

DP0/RSRV/EXT_BR2

IRQ1/DP1/EXT_BG2

IRQ2/DP2/TLBISYNC/EXT_DBG2

IRQ3/DP3/CKSTP_OUT/EXT_BR3

IRQ4/DP4/CORE_SRESET/EXT_BG3

IRQ5/CINT/DP5/TBEN/EXT_DBG3

IRQ6/DP6/CSE0

IRQ7/DP7/CSE1

PSDVAL

TA

TEA

GBL/IRQ1

CI/BADDR29/IRQ2

WT/BADDR30/IRQ3

MPC8275 only

Ball

D15

Y4

D16

E15

AD1

AC1

AB2

Y3

D14

E14

AB3

W5

AC2

AA3

L2

J3

H1

F4

V3

R5

R2

N5

M1

J2

H5

F3

W2

T4

R3

N4

M5

K1

H4

F1

Pinout

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Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (Continued)

Pin Name

Ball

MPC8275/MPC8270

CS0

CS1

CS2

CS3

L2_HIT/IRQ4

CPU_BG/BADDR31/IRQ5/CINT

CPU_DBG

CPU_BR

CS4

CS5

CS6

CS7

CS8

CS9

CS10/BCTL1

CS11/AP0

BADDR27

BADDR28

ALE

BCTL0

PWE0/PSDDQM0/PBS0

PWE1/PSDDQM1/PBS1

PWE2/PSDDQM2/PBS2

PWE3/PSDDQM3/PBS3

PWE4/PSDDQM4/PBS4

PWE5/PSDDQM5/PBS5

PWE6/PSDDQM6/PBS6

PWE7/PSDDQM7/PBS7

PSDA10/PGPL0

PSDWE/PGPL1

POE/PSDRAS/PGPL2

PSDCAS/PGPL3

PGTA/PUPMWAIT/PGPL4/PPBS

PSDAMUX/PGPL5

MPC8275 only

AE2

AD2

AE1

AC3

AB4

AE3

AF2

AD3

W6

AA4

AA5

AE4

AD4

AF3

C13

A12

D13

AF4

AE8

AD8

AC8

AB8

AF7

AC7

AD7

AF8

AC6

AD6

AE6

AB7

A17

B14

F13

B17

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Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (Continued)

Pin Name

MPC8275/MPC8270

LWE0/LSDDQM0/LBS0/PCI_CFG0

LWE1/LSDDQM1/LBS1/PCI_CFG1

LWE2/LSDDQM2/LBS2/PCI_CFG2

LWE3/LSDDQM3/LBS3/PCI_CFG3

LSDA10/LGPL0/PCI_MODCKH0

LSDWE/LGPL1/PCI_MODCKH1

LOE/LSDRAS/LGPL2/PCI_MODCKH2

LSDCAS/LGPL3/PCI_MODCKH3

LGTA/LUPMWAIT/LGPL4/LPBS

LGPL5/LSDAMUX/PCI_MODCK

LWR

L_A14/PAR

L_A15/FRAME/SMI

L_A16/TRDY

L_A17/IRDY/CKSTP_OUT

L_A18/STOP

L_A19/DEVSEL

L_A20/IDSEL

L_A21/PERR

L_A22/SERR

L_A23/REQ0

L_A24/REQ1/HSEJSW

L_A25/GNT0

L_A26/GNT1/HSLED

L_A27/GNT2/HSENUM

L_A28/RST/CORE_SRESET

L_A29/INTA

L_A30/REQ2

L_A31/DLLOUT

LCL_D0/AD0

LCL_D1/AD1

LCL_D2/AD2

LCL_D3/AD3

LCL_D4/AD4

MPC8275 only

Ball

AF21

AF22

AE21

AB14

AD20

AB9

AB10

AC10

AD10

AE10

AE14

AC17

AD14

AF13

AE20

AC14

AC19

AD13

AC5

AB5

AF6

AE13

AD15

AF16

AF15

AE15

AB6

AF5

AE5

AD5

AC9

AD9

AE9

AF9

Pinout

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Pinout

Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (Continued)

Pin Name

Ball

MPC8275/MPC8270

LCL_D5/AD5

LCL_D6/AD6

LCL_D7/AD7

LCL_D8/AD8

LCL_D9/AD9

LCL_D10/AD10

LCL_D11/AD11

LCL_D12/AD12

LCL_D13/AD13

LCL_D14/AD14

LCL_D15/AD15

LCL_D16/AD16

LCL_D17/AD17

LCL_D18/AD18

LCL_D19/AD19

LCL_D20/AD20

LCL_D21/AD21

LCL_D22/AD22

LCL_D23/AD23

LCL_D24/AD24

LCL_D25/AD25

LCL_D26/AD26

LCL_D27/AD27

LCL_D28/AD28

LCL_D29/AD29

LCL_D30/AD30

LCL_D31/AD31

LCL_DP0/C0/BE0

LCL_DP1/C1/BE1

LCL_DP2/C2/BE2

LCL_DP3/C3/BE3

IRQ0/NMI_OUT

IRQ7/INT_OUT/APE

TRST

1

MPC8275 only

AF20

AD19

AB18

AE12

AA13

AC15

AF19

A11

E5

F22

AF18

AE17

AD17

AB17

AE18

AD18

AC18

AE19

AB13

AD12

AF14

AF17

AE16

AD16

AC16

AB16

AF10

AF11

AB12

AB11

AF12

AE11

AC13

AC12

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Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (Continued)

Pin Name

Ball

MPC8275/MPC8270

TCK

TMS

TDI

TDO

TRIS

PORESET

1

HRESET

SRESET

QREQ

RSTCONF

MODCK1/AP1/TC0/BNKSEL0

MODCK2/AP2/TC1/BNKSEL1

MODCK3/AP3/TC2/BNKSEL2

CLKIN1

PA0/RESTART1/DREQ3

PA1/REJECT1/DONE3

PA2/CLK20/DACK3

PA3/CLK19/DACK4/L1RXD1A2

PA4/REJECT2/DONE4

PA5/RESTART2/DREQ4

PA6

PA7/SMSYN2

PA8/SMRXD2

PA9/SMTXD2

PA10/MSNUM5

PA11/MSNUM4

PA12/MSNUM3

MPC8275 only

FCC2_UTM_TXADDR2

FCC2_UTM_TXADDR1

FCC2_UTM_TXADDR0

FCC2_UTM_RXADDR0

FCC2_UTM_RXADDR1

FCC2_UTM_RXADDR2

FCC2_UT_RXADDR3

FCC2_UT_TXADDR3

FCC2_UT_TXADDR4

PA13/MSNUM2

PA14/FCC1_MII_HDLC_RXD3

PA15/FCC1_MII_HDLC_RXD2

PA16/FCC1_MII_HDLC_RXD1/

FCC1_RMII_RXD1

FCC1_UT8_RXD0/FCC1_UT16_RXD8

FCC1_UT8_RXD1/FCC1_UT16_RXD9

FCC1_UT8_RXD2/

FCC1_UT16_RXD10

FCC1_UT8_RXD3/

FCC1_UT16_RXD11

FCC1_UT8_RXD4/

FCC1_UT16_RXD12

/FCC1_UT8_RXD5/

FCC1_UT16_RXD13

FCC1_UT8_RXD6/

FCC1_UT16_RXD14

D18

E24

B16

F16

A15

AA22

2

AA23

2

Y26

2

W22

2

W23

2

V26

2

G22

AC20

2

AC21

2

AF25

2

AE24

2

AA21

2

AD25

2

AC24

2

C19

B25

D24

E23

A24

C24

A25

B24

V25

2

T22

2

T25

2

R24

2

Pinout

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Pinout

Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (Continued)

MPC8275/MPC8270

PA17/FCC_MII_HDLC_RXD0/

FCC1_MII_TRAN_RXD/

FCCI_RMII_RXD0

PA18/FCC1_MII_HDLC_TXD0/

FCC1_MIITRAN_TXD/

FCC1_RMII_TXD0

PA19/FCC1_MII_HDLC_TXD1/

FCC1_RMII_TXD1

PA20/FCC1_MII_HDLC_TXD2

PA21/FCC1_MII_HDLC_TXD3

PA22

PA23

PA24/MSNUM1

PA25/MSNUM0

PA26/FCC1_MII_RMII_RX_ER/

Pin Name

MPC8275 only

FCC1_UT8_RXD7/

FCC1_UT16_RXD15

FCC1_UT8_TXD7/FCC1_UT16_TXD15

FCC1_UT8_TXD6/FCC1_UT16_TXD14

FCC1_UT8_TXD5/FCC1_UT16_TXD13

FCC1_UT8_TXD4/FCC1_UT16_TXD12

FCC1_UT8_TXD3/FCC1_UT16_TXD11

FCC1_UT8_TXD2/FCC1_UT16_TXD10

FCC1_UT8_TXD1/FCC1_UT16_TXD9

FCC1_UT8_TXD0/FCC1_UT16_TXD8

FCC1_UTM_RXCLAV/

FCC1_UTS_RXCLAV

FCC1_UT_RXSOC

Ball

P22

2

N26

2

N23

2

K26

2

L23

2

K23

2

H26

2

F25

2

D26

2

D25

2

C25

2

PA27/FCC1_MII_RX_DV/

FCC1_RMII_CRS_DV

PA28/FCC1_MII_TX_EN/

FCC1_RMII_TX_EN

PA29/FCC1_MII_TX_ER

PA30/FCC1_MII_CRS/FCC1_RTS

PA31/FCC1_MII_COL

FCC1_UTM_RXENB/

FCC1_UTS_RXENB

FCC1_UT_TXSOC

FCC1_UTM_TXCLAV/

FCC1_UTS_TXCLAV

FCC1_UTM_TXENB/

FCC1_UTS_TXENB

FCC2_UT8_RXD0

C22

2

B21

2

A20

2

A19

2

AD21

2

PB4/FCC3_MII_HDLC_TXD3/

L1RSYNCA2/FCC3_RTS

PB5/FCC3_MII_HDLC_TXD2/

L1TSYNCA2/L1GNTA2

PB6/FCC3_MII_HDLC_TXD1/

FCC3_RMII_TXD1/

L1RXDA2/L1RXD0A2

PB7/FCC3_MII_HDLC_TXD0/

FCC3_RMII_TXD0/

FCC3_TXD/L1TXDA2/L1TXD0A2

PB8/FCC3_MII_HDLC_RXD0/

FCC3_RMII_RXD0/

FCC3_RXD/TXD3

PB9/FCC3_MII_HDLC_RXD1/

FCC3_RMII_RXD1/L1TXD2A2

PB10/FCC3_MII_HDLC_RXD2

FCC2_UT8_RXD1

FCC2_UT8_RXD2

FCC2_UT8_RXD3

FCC2_UT8_TXD3

FCC2_UT8_TXD2

FCC2_UT8_TXD1

AD22

2

AC22

2

AE26

2

AB23

2

AC26

2

AB26

2

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Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (Continued)

Pin Name

Ball

MPC8275/MPC8270 MPC8275 only

PB11/FCC3_MII_HDLC_RXD3

PB12/FCC3_MII_CRS/TXD2

PB13/FCC3_MII_COL/L1TXD1A2

PB14/FCC3_MII_RMII_TX_EN/RXD3

PB15/FCC3_MII_TX_ER/RXD2

PB16/FCC3_MII_RMII_RX_ER/CLK18

FCC2_UT8_TXD0

PB17/FCC3_MII_RX_DV/CLK17/

FCC3_RMII_CRS_DV

PB18/FCC2_MII_HDLC_RXD3/

L1CLKOD2/L1RXD2A2

FCC2_UT8_RXD4 M23

2

PB19FCC2_MII_HDLC_RXD2/

L1RQD2/L1RXD3A2

PB20/FCC2_MII_HDLC_RMII_RXD1/

L1RSYNCD2

FCC2_UT8_RXD5

FCC2_UT8_RXD6

L24

K24

2

2

PB21//FCC2_MII_HDLC_RMII_RXD0/

FCC2_TRAN_RXD/L1TSYNCD2/

L1GNTD2

PB22/FCC2_MII_HDLC_RMII_TXD0/

FCC2_TXD/FCC2_RMII_TXD0/

L1RXDD2

PB23/FCC2_MII_HDLC_TXD1/

L1RXD2A1/L1TXDD2/

FCC2_RMII_TXD1

PB24/FCC2_MII_HDLC_TXD2/

L1RSYNCC2

PB25/FCC2_MII_HDLC_TXD3/

L1TSYNCC2/L1GNTC2

PB26/FCC2_MII_CRS/L1RXDC2

FCC2_UT8_RXD7 L21

FCC2_UT8_TXD7 P25

FCC2_UT8_TXD6

FCC2_UT8_TXD5 E26

FCC2_UT8_TXD4 H23

FCC2_UT8_TXD1

PB27/FCC2_MII_COL/L1TXDC2 FCC2_UT8_TXD0

PB28/FCC2_MII_RX_ER/FCC2_RMII_RX_ER/

FCC2_RTS/L1TSYNCB2/L1GNTB2/TXD1

PB29/L1RSYNCB2/

FCC2_MII_TX_EN/FCC2_RMII_TX_EN

FCC2_UTM_RXCLAV/

FCC2_UTS_RXCLAV

FCC2_UT_TXSOC PB30/FCC2_MII_RX_DV/L1RXDB2/

FCC2_RMII_CRS_DV

PB31/FCC2_MII_TX_ER/L1TXDB2 FCC2_UT_RXSOC

N25

C26

B26

A22

A21

E20

C20

2

2

2

2

2

2

2

2

2

2

2

AE22

2

PC0/DREQ1/BRGO7/SMSYN2/

L1CLKOA2

PC1/DREQ2/SPISEL/BRGO6/L1RQA2

PC2/FCC3_CD/DONE2 FCC2_UT8_TXD3

AA19

AF24

2

2

AA25

2

W26

2

W25

2

V24

2

U24

2

R22

2

R23

2

Pinout

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Pinout

Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (Continued)

MPC8275/MPC8270

PC3/FCC3_CTS/DACK2/CTS4/

USB_RP

PC4/SI2_L1ST4/FCC2_CD

Pin Name

MPC8275 only

FCC2_UT8_TXD2

Ball

AE25

2

AB22

2

PC5/SI2_L1ST3/FCC2_CTS

PC6/FCC1_CD

PC7/FCC1_CTS

FCC2_UTM_RXENB/

FCC2_UTS_RXENB

FCC2_UTM_TXCLAV/

FCC2_UTS_TXCLAV

FCC1_UTM_RXADDR2/

FCC1_UTS_RXADDR2/

FCC1_UTM_RXCLAV1

FCC1_UTM_TXADDR2/

FCC1_UTS_TXADDR2/

FCC1_UTM_TXCLAV1

FCC1_UT16_TXD0

AC25

2

AB25

2

AA24

2

Y24

2

PC8/CD4/RENA4/SI2_L1ST2/CTS3/

USB_RN

PC9/CTS4/CLSN4/SI2_L1ST1/

L1TSYNCA2/L1GNTA2/USB_RP

PC10/CD3/RENA3

PC11/CTS3/CLSN3/L1TXD3A2

PC12/CD2/RENA2

PC13/CTS2/CLSN2

PC14/CD1/RENA1

PC15/CTS1/CLSN1/SMTXD2

FCC1_UT16_TXD1

FCC1_UT16_TXD2/FCC2_UT8_RXD3

FCC2_UT8_RXD2

FCC1_UTM_RXADDR1/

FCC1_UTS_RXADDR1

FCC1_UTM_TXADDR1/

FCC1_UTS_TXADDR1

FCC1_UTM_RXADDR0/

FCC1_UTS_RXADDR0

FCC1_UTM_TXADDR0/

FCC1_UTS_TXADDR0

U22

2

V23

2

U23

2

T26

2

R26

2

P26

2

P24

2

PC16/CLK16/TIN4

PC17/CLK15/TIN3/BRGO8

PC18/CLK14/TGATE2

PC19/CLK13/BRGO7/SPICLK

PC20/CLK12/TGATE1/USB_OE

PC21/CLK11/BRGO6

PC22/CLK10/DONE1

PC23/CLK9/BRGO5/DACK1

PC24/CLK8/TOUT4

PC25/CLK7/BRGO4

PC26/CLK6/TOUT3/TMCLK

PC27/FCC3_TXD/FCC3_MII_TXD0/

FCC3_RMII_TXD0/CLK5/BRGO3

FCC1_UT_TXPRTY

FCC2_UT8_TXD3

FCC2_UT8_TXD2

M26

2

L26

2

M24

2

L22

2

K25

2

J25

2

G26

2

F26

2

G24

2

E25

2

G23

2

B23

2

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Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (Continued)

Pin Name

Ball

MPC8275/MPC8270 MPC8275 only

PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2 FCC2_UT_RXADDR4

PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1

PC30/CLK2/TOUT1

PC31/CLK1/BRGO1

PD4/BRGO8/FCC3_RTS/SMRXD2

PD5/DONE1

PD6/DACK1

PD7/SMSYN1/FCC1_TXCLAV2

PD8/SMRXD1/BRGO5

PD9/SMTXD1/BRGO3

PD10/L1CLKOB2/BRGO4

PD11/L1RQB2

FCC2_UT8_TXD3

E22

2

E21

2

D21

2

B20

2

FCC1_UT16_TXD3

FCC1_UT16_TXD4

AF23

2

AE23

2

AB21

2

AD23

2

FCC1_UTM_TXADDR3/

FCC1_UTS_TXADDR3/

FCC2_UTM_TXADDR4

FCC2_UTS_TXADDR1

FCC2_UT_TXPRTY

FCC2_UT_RXPRTY

AD26

2

Y22

2

FCC2_UT8_RXD1 AB24

2

FCC2_UT8_RXD0

L1GNTB1

Y23

2

PD12

PD13

PD14/L1CLKOC2/I2CSCL

PD15/L1RQC2/I2CSDA

PD16/SPIMISO

PD17/BRGO2/SPIMOSI

PD18/SPICLK

PD19/SPISEL/BRGO1

AA26

2

W24

2

FCC1_UT16_RXD0

FCC1_UT16_RXD1

V22

2

U26

2

FCC1_UT_TXPRTY T23

2

FCC1_UT_RXPRTY R25

2

P23

2

FCC1_UTM_RXADDR4/

FCC1_UTS_RXADDR4/

FCC1_UTM_RXCLAV3/

FCC2_UTM_RXADDR3/

FCC2_UTS_RXADDR0

N22

2

FCC1_UTM_TXADDR4/

FCC1_UTS_TXADDR4/

FCC1_UTM_TXCLAV3/

FCC2_UTM_TXADDR3/

FCC2_UTS_TXADDR0

PD20/RTS4/TENA4/L1RSYNCA2/

USB_TP

FCC1_UT16_RXD2 M25

2

PD21/TXD4/L1RXD0A2/L1RXDA2/

USB_TN

FCC1_UT16_RXD3

L25

2

PD22/RXD4L1TXD0A2/L1TXDA2/

USB_RXD

FCC1_UT16_TXD5

J26

2

PD23/RTS3/TENA3

PD24/TXD3

FCC1_UT16_RXD4 K22

2

FCC1_UT16_RXD5 G25

2

Pinout

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Pinout

MPC8275/MPC8270

PD25/RXD3

PD26/RTS2/TENA2

PD27/TXD2

PD28/RXD2

PD29/RTS1/TENA1

PD31/RXD1

VCCSYN

VCCSYN1

CLKIN2

SPARE4

3

PCI_MODE

4

SPARE6

3

No connect

5

I/O power

Ground

Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (Continued)

PD30/TXD1

Core Power

Pin Name

Ball

MPC8275 only

FCC1_UT16_TXD6 H24

2

FCC1_UT16_RXD6 F24

2

FCC1_UT16_RXD7 H22

2

FCC1_UT16_TXD7 B22

2

D22

2

FCC1_UTM_RXADDR3/

FCC1_UTS_RXADDR3/

FCC1_UTM_RXCLAV2/

FCC2_UTM_RXADDR4/

FCC2_UTS_RXADDR1

FCC2_UTM_TXENB/

FCC2_UTS_TXENB

C21

2

E19

2

D19

K6

K21

C14

AD24

B15

E17, C23

E6, F6, H6, L5, L6, P6, T6, U6, V5,

Y5, AA6, AA8, AA10, AA11,

AA14, AA16, AA17, AB19, AB20,

W21, U21, T21, P21, N21, M22,

J22, H21, F21, F19, F17, E16,

F14, E13, E12, F10, E10, E9

L3, V4, W3, AC11, AD11, AB15,

U25, T24, J24, H25, F23, B19,

D17, C17, D10, C10

B18

6

, A18

7

, A2, B1, B2, A5, C5,

C18, D4, D6, G2, L4, P1, R1, R4,

AC4, AE7, AC23, Y25, N24, J23,

A23, D23, D20, E18, A13, A16,

K10, K11, K12, K13, K14, K15,

K16, K17, L10, L11, L12, L13,

L14, L15, L16, L17, M10, M11,

M12, M13, M14, M15, M16, M17,

N10, N11, N12, N13, N14, N15,

N16, N17, P10, P11, P12, P13,

P14, P15, P16, P17, R10,

R11,R12, R13, R14, R15, R16,

R17, T10, T11, T12, T13, T14,

T15, T16, T17, U10, U11, U12,

U13, U14, U15, U16, U17

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Package Description

1

Should be tied to VDDH via a 2K

Ω external pull-up resistor.

2

The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive

DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs.

3

Must be pulled down or left floating.

4

If PCI is not desired, must be pulled up or left floating.

5

Sphere is not connected to die.

6

GNDSYN (B18): This pin exists as a separate ground signal in MPC826x(A) devices; it does not exist as a separate ground signal on the MPC8275/MPC8270. New designs must connect B18 to GND and follow the suggestions in

Section 4.3, “Layout Practices.” Old designs in which the MPC8275/MPC8270 is used as a drop-in replacement can

leave the pin connected to GND with the noise filtering capacitors.

7

XFC (A18) pin: This pin is used in MPC826x(A) devices; it is not used in MPC8275/MPC8270 because there is no need for external capacitor to operate the PLL. New designs should connect A18 (XFC) pin to GND. Old designs in which the MPC8275/MPC8270 is used as a drop-in replacement can leave the pin connected to the current capacitor.

9 Package Description

The following sections provide the package parameters and mechanical dimensions.

9.1

Package Parameters

Package parameters are provided in Table 23.

Table 23. Package Parameters

Package

ZU

Devices

Outline

(mm)

37.5 x 37.5

Type

TBGA

Interconnects

480

VR

ZQ

MPC8280

MPC8270

MPC8275VR

MPC8270VR

MPC8275ZQ

MPC8270ZQ

27 x 27

27 x 27

PBGA

PBGA

516

516

Pitch

(mm)

1.27

Nominal Unmounted

Height (mm)

1.55

1

1

2.25

2.25

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71

Freescale Semiconductor, Inc.

Package Description

9.2

Mechanical Dimensions

Figure 17 provides the mechanical dimensions and bottom surface nomenclature of the 480 TBGA (ZU)

package. Refer to Table 2.

Notes:

1. Dimensions and Tolerancing per

ASME Y14.5M-1994.

2. Dimensions in millimeters.

3. Dimension b is measured at the maximum solder ball diameter, parallel to primary data A.

4. Primary data A and the seating plane are defined by the spherical crowns of the solder balls.

Millimeters

Dim

Min Max

b

D

D1 e

A

A1

A2

A3

E

E1

1.45

0.60

0.85

0.25

1.65

0.70

0.95

0.65

0.85

37.50 BSC

35.56 REF

1.27 BSC

37.50 BSC

35.56 REF

Figure 17. Mechanical Dimensions and Bottom Surface Nomenclature—480 TBGA

Figure 18 provides the mechanical dimensions and bottom surface nomenclature of the 516 PBGA (VR/ZQ)

packages.

72

MPC8280 PowerQUICC II™ Family Hardware Specifications

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MOTOROLA

Freescale Semiconductor, Inc.

Package Description

Figure 18. Mechanical Dimensions and Bottom Surface Nomenclature—516 PBGA

MOTOROLA

MPC8280 PowerQUICC II™ Family Hardware Specifications

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73

Freescale Semiconductor, Inc.

Ordering Information

10 Ordering Information

Figure 19 provides an example of the Motorola part numbering nomenclature for the MPC8280. In addition

to the processor frequency, the part numbering scheme also consists of a part modifier that indicates any enhancement(s) in the part from the original production design. Each part number also contains a revision code that refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. For more information, contact your local Motorola sales office.

MPC 82XX C ZU XXX X

Product Code

Device Number

Temperature Range

Blank = 0

TA

C = (-40)

to 105

TA

– 105

Tj

Tj

Die Revision Level

Processor Frequency

(CPU/CPM/Bus)

Package

ZU = 480 TBGA Lead spheres

VR = 516 PBGA Lead-free spheres

ZQ = 516 PBGA Lead spheres

Figure 19. Motorola Part Number Key

11 Document Revision History

Table 24. Document Revision History

Revision Date

0.1

0.2

0.3

— Initial public release

Substantive Changes

11/2002 Table 22, “VR Pinout”: Addition of C18 to the Ground (GND) pin list (page 63)

6/2003 • Removal of notes stating “no local bus” on VR-package devices. The MPC8270VR and the

MPC8275VR have local bus support.

• References to “G2 core” changed to “G2_LE core.” Refer to the G2 Core Reference Manual

(G2CORERM/D).

• Addition of VCCSYN to “Note” below Table 4, and to note 3 of Table 5

• Figure 2: New

• Table 5: Addition of note 1

• Table 6: Addition of

θ

JB and

θ

JC

. Modifications to ZU package values.

• Table 7: Addition of various configurations, Modification of values. Addition of note 3.

• Table 9: Addition of 66 MHZ and 100 MHz values. Addition of sp42a/sp43a.

• Table 10: Addition of 66 MHZ and 100 MHz values

• Table 12: sp30 values. sp33b @100 MHz value. Removal of previous note 2. Modification of

current note 2.

• Figure 5, Figure 6, Figure 7, and Figure 8: Addition of notes

• Section 6.2: Addition of note on PCI timing

• Table 15, Table 16, Table 17, Table 18, Table 19: Addition of note 1 concerning minimum

operating frequencies

• Addition of statement before clock tables about selection of clock configuration and input frequency

• Table 20 and Table 22: Addition of note 1 to CPM pins

74

MPC8280 PowerQUICC II™ Family Hardware Specifications

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MOTOROLA

Freescale Semiconductor, Inc.

Document Revision History

Table 24. Document Revision History

Revision Date

1.0

Substantive Changes

2/2004 • Removal of “Advance Information” and “Preliminary.” The MPC8280 is fully qualified.

• Table 1: New

• Figure 1: Modification to note 2

• Section 1.1: Core frequency range is 166–450 MHz

• Addition of ZQ (516 PBGA with Lead spheres) package references

• Table 4: VDD and VCCSYN modified to 1.45–1.60 V

• Note following Table 4: Modified

• Table 5: Addition of note 2 regarding TRST and PORESET (see VIH row of Table 5)

• Table 5: Changed I

OL

for 60x signals to 6.0 mA

• Table 5: Moved QREQ to V

OL

: I

OL

= 3.2 mA

• Table 5: Addition of critical interrupt (CINT) to IRQ5 for V

OL

• Table 6: Addition of

Ψ

JT and note 4

• Sections 4.1–4.2: New

(I

OL

= 6.0mA)

• Table 7: Modified power values (+ 150mW to each)

• Table 8: Addition of note 2. Changed PCI impedance to 27

Ω.

• Table 9: Changes to sp36b, SP38a, sp38b, sp37a, sp39a, sp40 and sp41

• Table 10: Changes to sp16a, sp18a, sp20 and sp21

• Section 6.2: Addition of Note: CLKIN Jitter and Duty Cycle

• Table 11: Changes to sp13 @ 66 and 83 MHz, sp14 @ 83 MHz

• Table 12: Change to sp30 (data bus signals). Changes to sp33b. Removal of note 2.

• Table 15 through Table 19: Modification of note 1 regarding CPU and CPM Fmin. Modification

to corresponding values in tables.

• Table 20: Addition of note 1 to TRST (AH3) and PORESET (AG6)

• Table 20: Addition of RXD3 to CPM port pin PB14. Previously omitted.

• Table 20: Addition of critical interrupt (CINT) to B21 and U4. Previously omitted.

• Table 20: Addition of note 5 to ‘No connect’ (AA1, AG4)

• Addition of “Note: Temperature Reflow for the VR Package" on page 58

• Table 22: Addition of note 1 to TRST (F22) and PORESET (B25)

• Table 22: Addition of previously omitted signals that are multiplexed with CPM port pins:

PA6—FCC2_UT_RXADDR3

PA7—FCC2_UT_TXADDR3

PA8—FCC2_UT_TXADDR4

PB14—RXD3

PC19—SPICLK

PC22—FCC1_UT_TXPRTY

PC28—FCC2_UT_RXADDR4

• Table 22: Removal of serial interface 1 (SI1) signals from port pins (see note 2 in Figure 1):

PA[6–9], PB[8–17, 20–25], PC[6–7, 10–13], PD[4, 10–13, 16, 23–28]

• Table 22: Addition of critical interrupt (CINT) to AC1 and B14. Previously omitted.

• Table 22: Addition of note 5 to ‘No connect’ (E17, C23)

MOTOROLA

MPC8280 PowerQUICC II™ Family Hardware Specifications

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75

Freescale Semiconductor, Inc.

HOW TO REACH US:

USA/EUROPE/LOCATIONS NOT LISTED:

Motorola Literature Distribution

P.O. Box 5405, Denver, Colorado 80217

1-480-768-2130

(800) 521-6274

JAPAN:

Motorola Japan Ltd.

SPS, Technical Information Center

3-20-1, Minami-Azabu Minato-ku

Tokyo 106-8573 Japan

81-3-3440-3569

ASIA/PACIFIC:

Motorola Semiconductors H.K. Ltd.

Silicon Harbour Centre, 2 Dai King Street

Tai Po Industrial Estate, Tai Po, N.T., Hong Kong

852-26668334

TECHNICAL INFORMATION CENTER:

(800) 521-6274

HOME PAGE:

www.motorola.com/semiconductors

Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.

Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.

Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark

Office. digital dna is a trademark of Motorola, Inc. The described product contains a PowerPC processor core. The PowerPC name is a trademark of IBM Corp. and used under license. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action

Employer.

© Motorola, Inc. 2004

MPC8280EC

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Freescale > PowerPC Processors > MPC82XX PowerQUICC II Processors > MPC8270

MPC8270 : PowerQUICC II Integrated Communications Processor

Introducing the next generation of PowerQUICC II" processors: the MPC8270,

MPC8275 and MPC8280.

Utilizing Freescale's HiPerMOS7 0.13-micron process technology, the next generation

PowerQUICC II family offers a range of performance, feature enhancements and package options with lower power requirements. Ideal for wired and wireless infrastructure communications processing tasks, enhancements to the PowerQUICC II family offer system designers a high degree of integrated features and functionality and a compelling, proven architecture.

The next generation of PowerQUICC II processors is an optimum solution for integrated control and forwarding plane processing in high-end communications and networking equipment -- such as routers, DSLAMs, remote access concentrators, telecom switching equipment and cellular base stations. Combining extensive layer 2 functionality with control plane processing, Freescale's PowerQUICC II processors include a high-performance embedded PowerPC 603e™ core and a powerful RISC-based

Communications Processor Module (CPM). The CPM off-loads peripheral tasks from the embedded PowerPC ISA-based core and provides support for multiple communications protocols, including 10/100Mbps Ethernet, 155Mbps ATM and 256 HDLC channels.

And, of course, the next generation PowerQUICC II devices retain full software compatibility with the PowerQUICC II family.

A range of performance and package options

Taking advantage of the 0.13-micron process, the next generation of PowerQUICC II http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8270&nodeId=018rH3bTdG2977 (1 of 28) [11/10/2004 2:34:48 PM]

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MPC8270 Product Summary Page devices offers significant performance increases and power savings over the current generation PowerQUICC II devices, with speeds of up to 450MHz and 300MHz in the core and CPM respectively at less than 2 watts. The new processors continue to enhance the PowerQUICC architecture's industry-leading ATM support, offering up to 2 UTOPIA ports with support for up to 31 PHYs per interface -- ideal for high-density DSLAM line cards.

The next generation of PowerQUICC II solutions also delivers support for USB, an on-target addition for high performance SOHO and CPE networking equipment. And unlike most other integrated communications processors in the market, the PowerQUICC architecture integrates two processing cores to handle specific tasks: the PowerPC core and the RISC-based CPM -- enabling a balanced approach for systems by handling both high-level tasks and low-level communications all in one integrated device.

Product Picture

MPC8270 Features

MPC8270ZQ/VR Features

603e core with 16K inst and 16K data caches

64-bit 60x bus, 32-bit PCI/local bus

128K ROM, 32K IRAM, 32K DPRAM

Three FCCs for 10/100 Ethernet

128 HDLC channels, 4 TDMs

4 SCCs, 2 SMCs, SPI, I2C

Memory controller built from SDRAM, UPM, GPCM machines

New features -- USB, RMII

Performance

266 MHz CPU, 200 MHz CPM, 66 MHz bus

~ 1W @ full performance, 1.5V

Technology

HIP7AP .13 micron, 3.3V I/O, 1.5V Core

516 PBGA, 27x27mm, 1mm ball pitch

ZQ package has lead-bearing spheres

VR package is lead-free

MPC8270ZU (480 TBGA) Features

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MPC8270 Product Summary Page

603e core with 16K inst and 16K data caches

64-bit 60x bus, 32-bit PCI bus

128K ROM, 32K IRAM, 32K DPRAM

Three FCCs for 10/100 Ethernet

128 HDLC channels, 4 TDMs

4 SCCs, 2 SMCs, SPI, I2C

Memory controller built from SDRAM, UPM, GPCM machines

New features -- USB, RMII

Performance

333 MHz CPU, 250 MHz CPM, 83 MHz bus

450 MHz CPU, 300 MHz CPM, 100 MHz bus

Less than 2W @ full performance, 1.5V

Technology

HIP7AP, 3.3V I/O, 1.5V Core

480 TBGA, 37.5x37.5mm, 1.27mm ball pitch

MPC8280 Family

Performance

-- CPU

-- CPM

--

60x/Memory

Bus

-- Local

Bus

-- I/D

Cache

CPM Interfaces

-- PCI

-- FCCs

MII/RMII

(Fast

Ethernet)

UTOPIA

(ATM)

8270VR 8270 8275VR 8280

266

200

66

66

16/16

YES

3

3

0

333/450

250/300

83/100

83/100

16/16

YES

3

3

0

266

200

66

66

16/16

YES

3

3

2

333/450

250/300

83/100

83/100

16/16

YES

3

3

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MPC8270 Product Summary Page

--

Multichannel

HDLC

-- SCCs

128

-- USB

-- SMCs

4

1

2

-- I2C/SPI

1

IMA/TC Functionality

NO

Package

516

PBGA

128 128

2

1

4

1

NO

480

TBGA

2

1

4

1

NO

516

PBGA

256

2

1

4

1

YES

480

TBGA

PowerQUICC II Masks and Versions

Process

0.29

µm

(HiP3)

Family

MPC8260

Revision Qualification Mask

A.1

B.3

C.2

XC

XC

XC

PVR

IMMR_

[16-31]

1

Rev_Num

2

0K26N 0x00810101 0x0011 0x0001

3K23A 0x00810101 0x0023 0x003B

6K23A,

7K23A

0x00810101 0x0024 0x007B

0.25

µm

(HiP4)

A.0

B.1

C.0

0.0

MPC8280

0.1

A.0

XC

MC

MC

MC

MC

2K25A 0x80811014 0x0060 0x000D

4K25A 0x80811014 0x0062 0x002D

5K25A 0x80811014 0x0064 0x002D

0K49M 0x80822011 0x0A00 0x0070

1K49M 0x80822013 0x0A01 0x0070

2K49M 0x80822014 0x0A10 0x0071

0.13

µm

(HiP7)

MPC8272

0.0

A.0

PC

MC

0K50M 0x80822013

0x0C00

3

0x0D00

4

1K50M 0x80822014

0xC010

3

0xD010

4

0x00E0

0x00E1

Notes:

1. The IMMR[16-31] indicates the mask number.

2. The Rev_Num located at offset 0x8AF0 in DPRAM indicates the CPM microcode revision number.

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MPC8270 Product Summary Page

3 . Encryption Enabled.

4 . Encryption Disabled.

Masks and versions table last updated on 14OCT2004.

Return to Top

CPU

Performance

(Max)

(MIPS)

Operating

Frequency

(Max)

(MHz)

CPM

Operation

Frequency

(Max)

(MHz)

Power

Dissipation

(Typ)

(W)

Power

Dissipation

(Max)

(W)

Core

Operating

Voltage

(Spec)

(V)

I/O

Operating

Voltage

(Max)

(V)

Ambient

Operating

Temperature

(Min)

(oC)

505.4,

632.7,

855,

885

266,

333,

450

200,

250,

300

1.05,

1.3,

2

1.1,

1.9,

2.3

1.5

3.3

-40,

0

Junction

Operating

Temperature

(Max)

(oC)

Integrated

Memory

Controller

105

EDO,

EPROM,

FLASH,

SDRAM,

SRAM

L1 Cache

Instructional

(Max)

(Byte)

L1

Cache

Data

(Max)

(Byte)

Internal

Dual-Port

RAM

(Byte)

16000 16000 64000

DMA

Controller

Channels

30

Bus

Interface

Serial

Interface

60x,

Local,

PCI 2.2

Type

I2C,

MII,

SPI,

TDM,

USB,

UTOPIA

Timers

Channels

4

Other Peripherals

DMA Controller

Network Application Function

Integrated Control/Data Plane

Package Description

FPBGA 516 27*27*1.25P1.0,

FTBGA 480 37*37*1.7P1.27

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MPC8270 Product Summary Page

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MPC8270 Parametrics

MPC8270 Documentation

Documentation

Application Note

ID

AN2059

AN2291

AN2335

AN2347

AN2349

AN2431

AN2491

AN2585

AN2587

AN2654

AN2431SW

Name

AN2059

Differences among PowerQUICC II Devices and Revisions

MPC8260 Dual-Bus Architecture and

Performance Considerations

Using an MPC8260 and an MPC7410 with

Shared Memory

MPC8260 Reset and Configuration Word

PowerQUICC II PCI Example Software

PowerQUICC II PCI Example Software

Vendor ID Format

Size

K

Rev

#

FREESCALE

FREESCALE

FREESCALE pdf pdf

0 n/a

Date Last

Modified

1/01/1

187

1.4 9/30/2003 pdf 61 0

10/15/2002

Order

Availability

FREESCALE

FREESCALE

FREESCALE

FREESCALE pdf pdf 90 0 pdf zip pdf

461

180

726

524

0

0

0

10/01/2002

10/01/2002

12/20/2002

12/20/2002

0 9/30/2003

Simplified Mnemonics for PowerPC

Instructions

MPC82xx PowerQUICC II Reset: Sources,

Effects, and Comments

Software Migration from the NPe495H/L to

PowerQUICC II

FREESCALE

FREESCALE

FREESCALE

Interfacing SDRAM Devices to the MPC8280 at 100 MHz

FREESCALE pdf 84 0.1 2/26/2004 pdf pdf

439

459

0.1 1/28/2004

0 2/10/2004 http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8270&nodeId=018rH3bTdG2977 (6 of 28) [11/10/2004 2:34:48 PM]

MPC8270 Product Summary Page

AN2754

CPM Architecture and Downloading RAM

Microcodes on the PowerQUICC II Family

FREESCALE zip

207

0 9/30/2004 -

Data Sheets

ID

MPC8280EC

Name

MPC8280 Hardware Specifications

Vendor ID Format

FREESCALE pdf

Size

K

1267

Rev

#

Date Last

Modified

1 2/16/2004

Order

Availability

Errata -

Click here for important errata information

ID

MPC8280CE

Name

MPC8280 PowerQUICC II Family Device

Errata

Vendor ID Format

Size

K

Rev

#

FREESCALE pdf

214

0.3

Date Last

Modified

6/28/2004

Order

Availability

-

Fact Sheets

ID Name

MPC8280FACT

MPC8280 POWERQUICC II PROCESSOR

FAMILY

Packaging Information

ID Name

PBGAPRES

TBGAPRESPKG

PBGA Packaging Customer Tutorial

TBGA Packaging Customer Tutorial

Vendor ID Format

Size

K

Rev

#

FREESCALE pdf

150

4

Date Last

Modified

Order

Availability

1/18/2004

Vendor ID Format

FREESCALE pdf

Size

K

1923

Rev

#

Date Last

Modified

1 8/05/2003

Order

Availability

-

FREESCALE pdf

1784

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MPC8270 Product Summary Page

Product Change Notices

ID

PCN10367

PCN9586

Name

MPC8270/8275 516 PBGA REVA

INTRODUCTION

Vendor ID Format

Size

K

Rev

#

FREESCALE

POWERQUICC II MPC8280 FAMILY NEW

ERRATA

FREESCALE htm 18 0 htm 9

Date Last

Modified

10/07/2004

Order

Availability

-

0 2/20/2004 -

Product Numbering Scheme

ID Name

MPC82XXHIP7PNS MPC82xx HiP7 Part Numbering Scheme

Vendor ID Format

Size

K

Rev

#

FREESCALE jpg

156

0

Date Last

Modified

8/01/2003

Order

Availability

-

Reference Manual

ID

G2CORERM

MPC8280RM

MPCFPE32B

MPCFPE32BAD

Name

G2 Core Reference Manual

Vendor ID Format

Size

K

Rev

#

FREESCALE pdf

5948

Date Last

Modified

1 6/27/2003

Order

Availability

MPC60XBUSRM

The Bus Interface for 32-Bit

Microprocessors that Implement the

PowerPC Architecture

MPC8260ESS7UMAD_D

Enhanced SS7 Microcode

Specification

FREESCALE

FREESCALE

MPC8280 PowerQUICC II" Family

Reference Manual

FREESCALE

Programming Environments Manual for 32-Bit Implementations of the

PowerPC Architecture

FREESCALE

Errata to MPCFPE32B,

Programming Environments Manual for 32-Bit Implementations of the

Power PC Architecture, Rev. 2

FREESCALE pdf

2527

0.1 1/14/2004 pdf 325 0.1 pdf pdf pdf

8405

6909

12/05/2002

0 3/30/2004

2

40 0

12/21/2001

10/11/2002

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MPC8270 Product Summary Page

White Paper

ID Name

MPC826XSDRAMWP

Timing Considerations when Interfacing the PowerQUICC II to SDRAM

Vendor ID Format

Size

K

Rev

#

FREESCALE pdf

Date Last

Modified

103

0.1

3/09/2004

Order

Availability

Return to Top

MPC8270 Design Tools

Hardware Tools

Analyzers

Logic

ID Name

TLA715/TLA721

TLA700 Logic Analyzers

The TLA700 Logic Analyzers have the performance to capture and display the fastest signals and gives you instant insight into the digital and analog behavior of your system so you can quickly find those elusive signal integrity problems

Vendor ID Format

Size

K

Rev

#

Order

Availability

TEKTRONIX

- - - http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8270&nodeId=018rH3bTdG2977 (9 of 28) [11/10/2004 2:34:48 PM]

MPC8270 Product Summary Page

Emulators/Probes/Wigglers

ID Name Vendor ID Format

Size

K

Rev

#

Order

Availability

WireTAP Run Control for the PowerPC

Microprocessor

Feature-packed, no nonsense run control tool that

HW-WIRETAPCOP allows developers to save precious development time during target bring-up and debug. Providing visibility and control of on-chip debug (OCD) features of PowerPC microprocessors.

BDI1000/BDI2000

BDI1000/BDI2000

Abatron develops and produces high-quality, high-speed BDM and JTAG Debug Tools (BDI

Family) for software development environments from leading vendors.

10200A

NetICE-R option 2/2M

PROBE

Green Hills Probe & Slingshot

WBDM8XX

WNPJ-COP

WPICE

GUARDIAN-SE

Wiggler for 5xx/8xx BDM

The Wiggler is a low-cost, parallel port interface used for debugging embedded systems. One side of the Wiggler interfaces to the parallel port of a

Windows host PC and the other side connects to the BDM port of the target system.

Wiggler for COP

The Wiggler is a low-cost, parallel port interface used for debugging embedded systems. One side of the Wiggler interfaces to the parallel port of a

Windows host PC and the other side connects to the COP port of the target system.

Guardian-SE

JTAG debug tools for PowerPC development

WIND®POWER ICE

METROWERKS

- - -

ABATRON

CORELIS

- - -

GREENHILLS

- - -

MACRAIGOR

MACRAIGOR

TOOLSMITHS

WINDRIV

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

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MPC8270 Product Summary Page

Evaluation/Development Boards and Systems

ID

MPC8260ADS_ECOM

MPC8260ADS Daughter Card for Telephony

Applications (E1)

MPC8260ADS_TCOM

MPC8260ADS Daughter Card for Telephony

Applications (T1)

PQ2FADS_VR

PQ2FADS_ZU

RATTLER-PCI

Name Vendor ID Format

Size

K

Rev

#

Order

Availability

FREESCALE

FREESCALE

MPC82xx Family Application Development System FREESCALE

MPC82xx Family Application Development System FREESCALE

Rattler-PCI

ANAMIC

-

-

-

-

-

-

-

-

-

-

-

-

-

-

- -

RATTLER1 ANAMIC

- - - -

EP8280M-H-10

SBCPQII

Rattler1

EP82xxM

EP82xxM is a PMC/stand alone single board computer using the 8280/70/66/65/50. PMC PCI, two 10/100 Ethernet, RS232 provided. Direct access to the 82xx IO allows OEMs to create solutions quickly. Linux, VxWorks and INTEGRITY are available.

SBCPowerQUICCII

EMDPLAN

WINDRIV

-

-

-

-

-

- -

-

Models

BSDL

ID Name Vendor ID Format

Size

K

Rev

#

Order

Availability

MPC827075BSDL1

PowerQUICC II (HiP7) PBGA package, BSDL model

(10/22/2003)

FREESCALE

MPC827080BSDL1

PowerQUICC II (HiP7) TBGA package, BSDL model

(10/22/2003)

FREESCALE zip zip

10 0.1

10 0.1 -

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MPC8270 Product Summary Page

Bus Functional Models

ID Name

PQ27LNXBFM

PQ27SOLBFM

PowerQUICC II HiP7 SWIFT Bus Model for

Linux

(01/28/2003)

PowerQUICC II HiP7 SWIFT Bus Model for

Solaris

(10/07/2003)

Vendor ID Format

Size

K

Rev

#

Order

Availability

FREESCALE tar

38160

0 -

FREESCALE tar

45625

2 -

Full Functional Models

ID Name

PQ27LNXFFM

PQ27SOLFFM

EP100

EP201

EP300

EP433

ES100

PowerQUICC II HiP7 SWIFT Full-Function

Model for Linux

(01/28/2003)

PowerQUICC II HiP7 SWIFT Full-Function

Model for Solaris

(01/28/2003)

PowerPC Bus Slave

PowerPC Bus Master

PowerPC Bus Arbiter

PowerPC-PCI Bridge

PowerPC System Controller

Vendor ID Format

Size

K

Rev

#

Order

Availability

FREESCALE tar

40540

0 -

FREESCALE tar

47566

0

EUREKA

EUREKA

EUREKA

EUREKA

EUREKA

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

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MPC8270 Product Summary Page

IBIS

ID Name

PQ27PBGAIBIS

516-pin PBGA IBIS model for local bus and PCI bus (VR and ZQ packages)

For MPC8270VR, MPC8270ZQ, MPC8275VR, and MPC8275ZQ.

(09/07/2004)

PQ27TBGAIBIS

480-pin TBGA IBIS model for local bus and PCI bus

For MPC8270, MPC8280.

(09/07/2004)

Vendor ID Format

Size

K

Rev

#

FREESCALE zip 64 1.6

FREESCALE zip 63 1.6

Order

Availability

-

-

Timing Models

ID

PQIIGPCMTIME

Name

GPCM Timing Generator

(05/29/2003)

Vendor ID Format

Size

K

Rev

#

FREESCALE exe 176 1

Order

Availability

-

Software

Application Software

Calculators

ID Name Vendor ID Format

Size

K

Rev

#

Order

Availability

MPC8260CALC1

Power Consumption Calculator for all

PowerQUICC II Processors

(04/28/2004)

FREESCALE

MPC8260CALC2

CPM Performance Calculator for all

PowerQUICC II and PowerQUICC III Processors

(09/07/2004)

FREESCALE zip zip

491

664

2.1

3.1.3

-

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MPC8270 Product Summary Page

Code Examples

ID Name

MPC8260COD08

Fast Ethernet on the FCC of the PowerQUICC II

(10/13/2003)

MPC8260COD09

Multichannel Communication Controller of the

PowerQUICC II

(09/04/2002)

MPC8260COD11

Example Software for the PowerQUICC II

Family: FEC Frames Using PHYless MII

(08/02/2002)

Vendor ID Format

Size

K

Rev

#

Order

Availability

FREESCALE zip

140

2 -

FREESCALE

FREESCALE zip zip

176

614

0

0 -

-

Microcode

ID Name Vendor ID Format

Size

K

Rev

#

Order

Availability

MPC8260MC05

RAM Microcode Patches for PowerQUICC II

Family Device Errata

(09/28/2004)

DG02010101

MultiRing

MultiRing is a utility that separates frames of different protocols into different buffer descriptor rings (rather than a single ring). The utility supports predefined protocols such as TCP, ICMP.

The user can specify additional protocols.

FREESCALE

DOGAV zip

-

330

-

4.2.3

- -

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MPC8270 Product Summary Page

Board Support Packages

ID Name Vendor ID Format

Size

K

Rev

#

Order

Availability

Arabella MPC82XX Free Reference Design

This free Linux BSP provides a complete Linux distribution and application ready to be used on

ARA-MOT-82XX-FREE the PQ2FADS-ZU/VR and MPC8260/8266ADS

Boards. Source code and Linux tools are provided to immediately get started working with a Linux syste

ARABELLA

- - -

ARC-MOT-MQXBSP

MQX Board Support Packages

BSPs for Freescale ColdFire, PowerPC, and 68K embedded processors including support for emerging USB and CAN technologies as well as drivers for Ethernet, PCI, HDLC, SPI, I2C, and serial devices.

ARC

- - - -

-

EP BSP

EP8280M VDK 10

EP BSP

Embedded Planet Board Support Packages provide complete software drivers for MPC 8xx and 82xx processors for Linux, VxWorks and

INTEGRITY. Embedded Planet can also develop customer specific software for many operating systems.

EP82xxM VxWorks BSP

VxWorks Board Support Packages contain prebuilt RAM and ROM kernel images and documentation that describes installing and running the BSP. See online matrix for supported peripherals.

EMDPLAN

EMDPLAN

-

-

-

-

-

- -

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MPC8270 Product Summary Page

Device Drivers

ID Name Vendor ID Format

Size

K

Rev

#

Order

Availability

ARC-MOT-DEVDEVDRIVER

USB Device Device Driver

USB Device or Host Device Driver

ARC-MOT-USBDEVKITS

USB Host/Device Developer's Kits

Supports on-chip USB host or device controllers. Comprised of USB host or device stack, class driver framework and example device drivers, all integrated with

MQX RTOS & provided royalty-free and in source code.

PCS

PlanetCore

PlanetCore provides a complete set of firmware device drivers for 8xx and 82xx

Motorola processors. These drivers include an application / RTOS boot loader, flash burner and diagnostics. customer specific drivers can also be developed.

ARC

ARC

-

-

-

-

-

-

EMDPLAN

- - - -

-

-

Libraries

ID

PN311-1

Name

KwikPeg GUI

KADAK's KwikPeg Graphical User Interface (GUI) is derived from PEG, a professional, high-quality graphic system created by Swell Software, Inc. to enable you, the embedded system developer, to easily add graphics to your products.

Vendor

ID

Format

Size

K

Rev

#

KADAK

- - -

Order

Availability

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MPC8270 Product Summary Page

Operating Systems

ID Name

ARC-MOT-MFS

ARC-MOT-MQX

MFS

MS-DOS File System is a portable, compatible implementation of the Microsoft MS-DOS file system

MQX Real Time Operating System

A robust, high performance, royalty-free kernel designed for deeply embedded applications requiring a small footprint and fast response.

CMX-RTX

CMX00300

CMX00300A

CMX00300B

CMX00300C

CMX-RTX

CMX TCP/IP

CMX TCP/IP is a full-featured and fast TCP/IP stack that allows designers to offer networking connectivity for their embedded applications. CMX TCP/IP offers a low licensing fee, full source code, no royalties, and free technical support.

TCP/IP DHCP Client

The CMX TCP/IP DHCP Client Add-On Option provides CMX TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the

Dynamic Host Configuration Protocol standard. A source code example is provided for fast design start up.

TCP/IP DHCP Server

The CMX TCP/IP DHCP Server Add-On Option provides CMX TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the

Dynamic Host Configuration Protocol standard. A source code example is provided for fast design start up.

TCP/IP FTP C/S

The CMX TCP/IP FTP Client/Server Add-On Option provides CMX TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the File

Transfer Protocol standard. A source code example is provided for fast design start up.

Vendor ID Format

Size

K

Rev

#

Order

Availability

ARC

ARC

CMX

CMX

CMX

CMX

CMX

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

- -

-

-

-

-

-

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MPC8270 Product Summary Page

CMX00300D

CMX00300E

CMX00300F

CMX00300I

CMX00300G

CMX00300H

TCP/IP IMAP4

The CMX TCP/IP IMAP4 Add-On Option provides

CMX TCP/IP (see CMX00300, CMX00305, or

CMX00310) with functionality for the Internet

Message Access Protocol Version 4 standard. A source code example is provided for fast design start up.

TCP/IP NAT

The CMX TCP/IP NAT Add-On Option provides

CMX TCP/IP (see CMX00300, CMX00305, or

CMX00310) with functionality to add Network

Address Translation function to a network application. Source code example provided for fast design start up.

TCP/IP POP3

The CMX TCP/IP POP3 Client Add-On Option provides CMX TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the Post

Office Protocol Client standard. A source code example is provided for fast design start up.

TCP/IP PPP

The CMX TCP/IP PPP Add-On Option provides

CMX TCP/IP (see CMX00300, CMX00305, or

CMX00310) with functionality to support the Point to

Point Protocol serial or modem connectivity standard.

Source code example provided for fast start up.

TCP/IP PPPoE

The CMX TCP/IP PPPoE Add-On Option provides

CMX TCP/IP (see CMX00300, CMX00305, or

CMX00310) with functionality to support the Point to

Point Protocol over Ethernet standard. A source code example is provided for fast design start up.

TCP/IP SMTP

The CMX TCP/IP SMTP Client Add-On Option provides CMX TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the

Simple Mail Transfer Protocol standard. A source code example is provided for fast design start up.

CMX

CMX

CMX

CMX

CMX

CMX

- - - -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

- -

-

-

-

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MPC8270 Product Summary Page

CMX00300J

CMX00300K

CMX00300L

CMX00300M

CMX00300N

CMX00630

TCP/IP SNMP

The CMX TCP/IP SNMP V1 and V2c Add-On

Option provides CMX TCP/IP (see CMX00300,

CMX00305, or CMX00310) with functionality to support the Simple Network Management Protocol standard. Source code example provided for fast design start up.

TCP/IP Telnet

The CMX TCP/IP Telnet Server Add-On Option provides CMX TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the

Telnet Server standard. A source code example is provided for fast design start up.

TCP/IP TFTP

The CMX TCP/IP TFTP Client/Server Add-On

Option provides CMX TCP/IP (see CMX00300,

CMX00305, or CMX00310) with functionality to support the Trivial File Transfer Protocol

Client/Server standard. Source code example for fast start up.

TCP/IP Web Client

The CMX TCP/IP Web Client/Server Add-On Option provides CMX TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the

Hyper Text Transfer Protocol (HTTP) Web

Client/Server standard. Source code example provided.

TCP/IP Web Server

The CMX TCP/IP Web Server Add-On Option provides CMX TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the

Hyper Text Transfer Protocol (HTTP) Web Server standard. Source code example provided for fast start up.

CMX-FFS

CMX-FFS is a very small, standard Flash File System that allows designers to offer file system functionality for their embedded applications. CMX-FFS offers a low licensing fee, full source code, no royalties, and free technical support.

CMX

CMX

CMX

CMX

CMX

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- - - -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

- -

-

-

-

-

MPC8270 Product Summary Page

CMX00631

CMX00632

CMX-FFS-NAND

CMX-FFS-NAND is an Add-On Option for CMX-

FFS that allows designers to include a NAND driver for their embedded FFS applications.

CMX-FFS-NAND offers a low licensing fee, full source code, no royalties, and free technical support.

CMX-FFS-FAT

CMX-FFS-FAT is a fast file system for embedded developers who wish to add devices to their products that require FAT12/16/32 compliant media.

CMX-FFS-FAT offers a low license fee, full source code, no royalties, and free tech support.

CMX00633

CMX-FFS-THIN

CMX-FFS-THIN is a file system for embedded device developers with limited resource products that require a FAT12/16/32 compliant media.

CMX-FFS-THIN offers a low licensing fee, full source code, no royalties, and free technical support.

DPP.82XXX.KRN

OSE Real-Time Operating System

THREADX

PX382-1

VXWORKS 5.X

CMX

CMX

CMX

-

-

-

-

-

-

-

-

-

VxWorks

VxWorks, the run-time component of TORNADOII for VxWorks, is the most widely adopted real-time operating system (RTOS) in the embedded industry, with a reputation for performance, flexibility, compatibility and scalability.

ENEA

ThreadX

RTOS. Royalty-free real-time operating system

(RTOS) for embedded applications. ThreadX is small, fast, and royalty-free making it ideal for high-volume electronic products.

EXPRESSLOG

- - -

AMX PPC32

AMX is a full featured RTOS for the PowerPC family. AMX has been tested on the EST SBC8260,

Embedded Planet RPX Lite MPC823 and Motorola

Ultra 603, MBX860, MPC860 ADS, MPC860 FADS,

Lite5200EVB and MPC8560 ADS.

KADAK

- - -

WINDRIV

- - -

- - -

-

-

-

-

-

-

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MPC8270 Product Summary Page

Protocol Stacks

ID Name

ARC-MOT-HTTP

ARC-MOT-POP3

ARC-MOT-RTCS

HTTP Web Server

The HTTP (Hyper text Transfer

Protocol) consists of source code and development tools for building an embedded HTTP server. This is a

HTTP 1.0/1.1 compliant Web server with CGI-style user exit support and optional file system support.

ARC-MOT-IPSHIELD

IPShield

Security product support for IPSec,

IKE, SSL and SSH. Also supports hardware accelerated encryption on processors with an Integrated Security

Engine such as MCF5485/5483,

MPC870/875, MPC8272/8248,

MCF5271, and MCF5275/5275L.

Network Protocols

TCP/IP networking stack (ARP,

BootP, CCP, CHAP, DHCP, DNS,

Echo, EDS, FTP, ICMP, IGMP, IP,

ARC-MOT-NETWORKPROTOCOLS

IP-E, IPCP, LCP, PAP, PPP, RIPv2,

RPC, SNMPv1/v2, SNTP, TCP,

TFTP, Telnet, UDP & XDR)& opt'al prototocols, SMTP, SNMPv3, PPPoE,

XML, SSL/H

POP3

Enables client embedded devices to receive e-mail from any POP3 server

RTCS

A real-time, high performance TCP/IP stack designed specifically for embedded networking applications such as IP phones, bridges, routers, pagers, PDAs, cellular phones, and set-top boxes

Vendor ID Format

Size Rev

K #

Order

Availability

ARC

ARC

ARC

ARC

ARC

-

-

-

-

-

-

-

-

-

-

-

-

-

-

- -

-

-

-

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MPC8270 Product Summary Page

ARC-MOT-SMTP

RSTP

TARGETTCP

CMX TCP/IP

IPLITE

PN713-1

SMTP

Royalty free source code SMTP enables embedded devices to send e-mail to any SMTP server. This allows any embedded device to send asynchronous status reports using email.

AvniRSTP

Avnisoft's AvniRSTP is a completely portable ANSI C compliant implementation of the IEEE 802.1w

RSTP Algorithm and Protocol. It includes the AvniPORT platform abstraction layer to simplify integration with target platforms.

TCP/IP Stack

TargetTCP, is a fast, reliable, re-entrant, full-featured TCP/IP protocol stack designed specifically for high-performance embedded networking. The code has a small footprint and is well suited to memory constrained environments.

ARC

AVNISOFT

BLUNK

-

-

-

-

-

-

-

-

-

CMX TCP/IP

IPLITE

IPLITE is a dual-mode IPv4/v6 host stack, optimized for minimum footprint and maximum performance, with a number of PowerQUICC II/III optimizations. Available for leading

RTOSs like INTEGRITY, Linux,

OSE, VxWorks, etc.

KwikNet

The KwikNet TCP/IP Stack enables you to add networking features to your products with a minimum of time and expense. KwikNet is a compact, high performance stack built with

KADAK's characteristic simplicity, flexibility and reliability.

CMX

INTERPEAK

- - -

KADAK

-

-

-

-

-

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-

-

-

-

-

-

MPC8270 Product Summary Page

INFOLINK-STACKNAME

MOC_SSL_CLIENT

PSQ40XXXX

INFOLink Protocol Software Family

Mocana Embedded SSL/TLS Client

MOCANA SSL/TLS CLIENT:

Supports Freescale chipsets out of the box. Small (50KB), fast (2-3x faster than OpenSSL), trusted. Supports all major cryptos. Royalty free, source code license. FREE EVAL: http://www.mocana.com/evaluate.html

RTXC Quadnet Networking Protocols

Full protocol suite: TCP, UDP, SLIP,

ICMP, and ARP with Berkeley

Sockets API. Plus DHCP, BOOTP,

DNS, IGMP v2, RIP v2, NAT, HTTP,

SMTP, POP3, TFTP, FTP, Telnet,

SNMP v1,2,3, PPP and more. New security protocols: SSL, IPsec, IKE.

LINK

MOCANA

-

-

-

-

-

-

QUADROS

- - -

-

-

-

Software Tools

Code Translation

ID

PA68K-PPC

PA86-PPC

Name

PortAsm/68K for PowerPC

PortAsm/86 for PowerPC

Vendor ID

MICROAPL

MICROAPL

Format

-

-

Size

K

Rev #

- -

- -

Order

Availability

-

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MPC8270 Product Summary Page

Compilers

ID Name Vendor ID Format

Size

K

Rev

#

Order

Availability

CWEPPC

CWLINPPC

CodeWarrior Development Studio for

PowerPC" Processors

CodeWarrior Development Studio. Linux

Application Edition for PowerPC

METROWERKS

METROWERKS

-

-

-

-

-

-

CWS-PPC-LLPLT-CX

CodeWarrior Development Studio, PowerPC

ISA - Linux

GNUTOOL

Gnu Tool set

ARC-MOT-COMPILER

MetaWare C/C++ Compiler Tool Suite

Optimized compiler for Motorola processors

COMPILER

C/C++ Compiler

Optimizing C, C++, EC++ compilers for

Freescale PowerPC, ColdFire, StarCore, 68K and ARM-based MAC architectures.

DIAB

Diab C/C++ Compiler

METROWERKS

- - -

ANAMIC

ARC

GREENHILLS

WINDRIV

-

-

-

-

-

-

-

-

-

-

-

- -

-

-

-

-

Debuggers

ID

CWNETROM540A

Name Vendor ID Format

Size

K

Rev

#

Order

Availability

Metrowerks NetROM

A Flexible Platform for Accelerated Embedded

Development: NetROM is a revolutionary product for embedded software developers. It provides a flexible debugging platform that combines high-speed target communication and debugging capabilties

METROWERKS

- - - -

WireTAP Run Control for the PowerPC

Microprocessor

Feature-packed, no nonsense run control tool that

HW-WIRETAPCOP allows developers to save precious development time during target bring-up and debug. Providing visibility and control of on-chip debug (OCD) features of PowerPC microprocessors.

POWERPC

DEBUGGER

MULTI Debugger

METROWERKS

GREENHILLS

-

-

-

-

-

- -

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MPC8270 Product Summary Page

LA-7729

TRACE32-ICD

TRACE32-ICD for PowerQUICC II is a high performance JTAG debugger for C ,C++ and

JAVA. A USB 2.x, LPT or ethernet interface is available for connection to any PC or workstation.

A flash programming utility is included.

LAUBACH

- - - -

Emulation

ID Name Vendor ID Format

Size

K

Rev

#

Order

Availability

MWCTST4SWICCORE

CodeTEST Analysis Tools, Software

In-Circuit

CodeTEST Software In-Circuit (SWIC) is the ideal solution for integrating your application software with your target hardware.

METROWERKS

- - - -

IDE (Integrated Development Environment)

ID

CE-PPCQNX21

Name Vendor ID Format

Size

K

Rev

#

Order

Availability

CodeWarrior for QNX RTOS

Provides a complete toolchain for creating, compiling, linking, and debugging your projects within a single environment. It also offers an application level debugger with multiple process and thread awareness support.

METROWERKS

- - - -

CWPPC1BWPQ3

CodeWarrior for PowerQUICC III

CodeWarrior Development Studio, PowerQUICC III

Edition support the whole development process from board bring-up through application development.

METROWERKS

- - -

MULTI

MULTI

MULTI is a complete integrated development environment for embedded applications using C,

C++, Embedded C++

GREENHILLS

- - -

WIND RIVER

WORKBENCH

Wind River Workbench

Wind River Workbench is an open, standards-based device software development environment for Linux applications providing a deep tools capability in each phase of the development process.

WINDRIV

- - - -

-

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MPC8270 Product Summary Page

WPIDE

WIND®POWER IDE

WINDRIV

- - - -

Initialization/Boot Code Generation

ID Name

MPC82XXCPMMUXIBCG

Parallel Ports Configuration Tool (Pin Mux

Tool)

(03/18/2004)

MPC82XXLBCUPMIBCG

UPM Tool for PowerQUICC II Processors

(12/11/2003)

Vendor ID Format

Size

K

Rev

#

Order

Availability

FREESCALE zip

985 4.0.0

-

FREESCALE zip

137 2.2.1

-

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Orderable Parts Information

Part Number

Package

Description

KMPC8270CVRMIBA

FPBGA 516

27*27*1.25P1.0

No

KMPC8270CZQMIBA

FPBGA 516

27*27*1.25P1.0

No

KMPC8270CZUQLD

KMPC8270CZUUPE

KMPC8270VRMIBA

FTBGA 480

37*37*1.7P1.27

No

FTBGA 480

37*37*1.7P1.27

No

FPBGA 516

27*27*1.25P1.0

No

Tape and

Reel

Pb-Free

Terminations

Yes

No

No

No

Yes

Application/

Qualification

Tier

Status

Budgetary

Price

QTY

1000+

($US)

Info

COMMERCIAL,

INDUSTRIAL

Available

COMMERCIAL,

INDUSTRIAL

Available

COMMERCIAL,

INDUSTRIAL

Available

COMMERCIAL,

INDUSTRIAL

Available

COMMERCIAL,

INDUSTRIAL

Available -

-

-

-

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-

MPC8270 Product Summary Page

KMPC8270ZQMIBA

KMPC8270ZUUPE

MPC8270CVRMIBA

MPC8270CZQMIBA

MPC8270CZUQLD

MPC8270CZUUPE

MPC8270VRMIBA

MPC8270ZQMIBA

MPC8270ZUQLD

MPC8270ZUUPE

FPBGA 516

27*27*1.25P1.0

No

FTBGA 480

37*37*1.7P1.27

No

FPBGA 516

27*27*1.25P1.0

No

FPBGA 516

27*27*1.25P1.0

No

FTBGA 480

37*37*1.7P1.27

No

FTBGA 480

37*37*1.7P1.27

No

FPBGA 516

27*27*1.25P1.0

No

FPBGA 516

27*27*1.25P1.0

No

FTBGA 480

37*37*1.7P1.27

No

FTBGA 480

37*37*1.7P1.27

No

No

No

Yes

No

No

No

Yes

No

No

No

COMMERCIAL,

INDUSTRIAL

Available

COMMERCIAL,

INDUSTRIAL

Available

COMMERCIAL,

INDUSTRIAL

Available

COMMERCIAL,

INDUSTRIAL

Available -

-

-

more more more more

COMMERCIAL,

INDUSTRIAL

Available

COMMERCIAL,

INDUSTRIAL

Available -

more more

COMMERCIAL,

INDUSTRIAL

Available $35.52

more

COMMERCIAL,

INDUSTRIAL

Available $35.52

more

-

-

Available

Available

NOTE:

Cannot find a Sample? Request a sample . Refer to Samples FAQ for more information.

Looking for an obsolete part? Check our distributors' inventory

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MPC8270 Product Summary Page

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MPC8280 Product Summary Page

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Freescale > PowerPC Processors > MPC82XX PowerQUICC II Processors > MPC8280

MPC8280 : PowerQUICC II Integrated Communications Processor

Introducing the next generation of PowerQUICC II" processors: the MPC8270,

MPC8275 and MPC8280.

Utilizing Freescale's HiPerMOS7 0.13-micron process technology, the next generation

PowerQUICC II family offers a range of performance, feature enhancements and package options with lower power requirements. Ideal for wired and wireless infrastructure communications processing tasks, enhancements to the PowerQUICC II family offer system designers a high degree of integrated features and functionality and a compelling, proven architecture.

The next generation of PowerQUICC II processors is an optimum solution for integrated control and forwarding plane processing in high-end communications and networking equipment -- such as routers, DSLAMs, remote access concentrators, telecom switching equipment and cellular base stations. Combining extensive layer 2 functionality with control plane processing, Freescale's PowerQUICC II processors include a high-performance embedded PowerPC 603e™ core and a powerful RISC-based

Communications Processor Module (CPM). The CPM off-loads peripheral tasks from the embedded PowerPC core and provides support for multiple communications protocols, including 10/100Mbps Ethernet, 155Mbps ATM and 256 HDLC channels. And, of course, the next generation PowerQUICC II devices retain full software compatibility with the PowerQUICC II family.

A range of performance and package options

Taking advantage of the 0.13-micron process, the next generation of PowerQUICC II devices offers significant performance increases and power savings over the current generation PowerQUICC II devices, with speeds of up to 450MHz and 300MHz in the

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MPC8280 Product Summary Page core and CPM respectively at less than 2 watts. The new processors continue to enhance the PowerQUICC architecture's industry-leading ATM support, offering up to 2 UTOPIA ports with support for up to 31 PHYs per interface -- ideal for high-density DSLAM line cards.

The next generation of PowerQUICC II solutions also delivers support for USB, an on-target addition for high performance SOHO and CPE networking equipment. And unlike most other integrated communications processors in the market, the PowerQUICC architecture integrates two processing cores to handle specific tasks: the PowerPC core and the RISC-based CPM -- enabling a balanced approach for systems by handling both high-level tasks and low-level communications all in one integrated device.

Product Picture

Block Diagram

MPC8280 Features

MPC8280ZU (480 TBGA) Solution

603e core with 16K inst and 16K data caches

64-bit 60x bus, 32-bit Local / PCI bus

128K ROM, 32K IRAM, 32K DPRAM

Three FCCs supporting ATM, 10/100 Ethernet or HDLC

256 HDLC channels, 8 TDMs

4 SCCs, 2 SMCs, SPI, I2C

Memory controller built from SDRAM, UPM, GPCM machines

New features -- USB, RMII, UTOPIA improvements

Performance

333 MHz CPU, 250 MHz CPM, 83 MHz bus

450 MHz CPU, 300 MHz CPM, 100 MHz bus

Less than 2W @ full performance, 1.5V

Technology

HiP7AP, 3.3V I/O, 1.5V Core

480 TBGA, 37.5x37.5mm, 1.27mm ball pitch

MPC8280 Family

Performance

-- CPU

-- CPM

8270VR 8270 8275VR 8280

266

200

333/450

250/300

266

200

333/450

250/300 http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8280&nodeId=018rH3bTdG2977 (2 of 25) [11/10/2004 3:47:21 PM]

MPC8280 Product Summary Page

--

60x/Memory

Bus

-- Local

Bus

-- I/D

Cache

CPM Interfaces

-- PCI

-- FCCs

MII/RMII

(Fast

Ethernet)

UTOPIA

(ATM)

--

Multichannel

HDLC

-- SCCs

66

66

16/16

YES

3

3

0

128

-- USB

-- SMCs

4

1

2

-- I2C/SPI

1

IMA/TC Functionality

NO

83/100

83/100

16/16

YES

3

3

0

128

4

1

2

1

NO

66

66

16/16

YES

3

3

2

128

4

1

2

1

NO

83/100

83/100

16/16

YES

3

3

2

256

4

1

2

1

YES

Package

516

PBGA

480

TBGA

516

PBGA

480

TBGA

PowerQUICC II Masks and Versions

Process

0.29

µm

(HiP3)

0.25

µm

(HiP4)

Family

MPC8260

Revision Qualification Mask

A.1

B.3

C.2

A.0

B.1

C.0

XC

XC

XC

XC

MC

MC

PVR

IMMR_

[16-31]

1

Rev_Num

2

0K26N 0x00810101 0x0011 0x0001

3K23A 0x00810101 0x0023 0x003B

6K23A,

7K23A

0x00810101 0x0024 0x007B

2K25A 0x80811014 0x0060 0x000D

4K25A 0x80811014 0x0062 0x002D

5K25A 0x80811014 0x0064 0x002D http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8280&nodeId=018rH3bTdG2977 (3 of 25) [11/10/2004 3:47:21 PM]

MPC8280 Product Summary Page

0.13

µm

(HiP7)

MPC8280

MPC8272

0.0

0.1

A.0

0.0

A.0

MC

MC

PC

MC

0K49M 0x80822011 0x0A00 0x0070

1K49M 0x80822013 0x0A01 0x0070

2K49M 0x80822014 0x0A10 0x0071

0K50M 0x80822013

0x0C00

3

0x0D00

4

1K50M 0x80822014

0xC010

3

0xD010

4

0x00E0

0x00E1

Notes:

1. The IMMR[16-31] indicates the mask number.

2. The Rev_Num located at offset 0x8AF0 in DPRAM indicates the CPM microcode revision number.

3 . Encryption Enabled.

4 . Encryption Disabled.

Masks and versions table last updated on 14OCT2004.

Return to Top

Sample

Availability

Y

CPU

Performance

(Max)

(MIPS)

Operating

Frequency

(Max)

(MHz)

CPM

Operation

Frequency

(Max)

(MHz)

Power

Dissipation

(Typ)

(W)

632.7,

855

330,

333,

450

250,

300

1.3,

2

Power

Dissipation

(Max)

(W)

Core

Operating

Voltage

(Spec)

(V)

I/O

Operating

Voltage

(Max)

(V)

1.9,

2.3

1.5

3.3

Ambient

Operating

Temperature

(Min)

(oC)

Junction

Operating

Temperature

(Max)

(oC)

Integrated

Memory

Controller

L1 Cache

Instructional

(Max)

(Byte)

L1

Cache

Data

(Max)

(Byte)

Internal

Dual-Port

RAM

(Byte)

DMA

Controller

Channels

Bus

Interface http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8280&nodeId=018rH3bTdG2977 (4 of 25) [11/10/2004 3:47:21 PM]

MPC8280 Product Summary Page

-40,

0

105

EDO,

EPROM,

FLASH,

SDRAM,

SRAM

16000 16000 64000 30

60x,

Local,

PCI 2.2

Serial Interface Timers

Type Channels

Other Peripherals Network Application Function

I2C,

MII,

SPI,

TDM,

USB,

UTOPIA

4

Package Description

DMA Controller Integrated Control/Data Plane FTBGA 480 37*37*1.7P1.27

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MPC8280 Parametrics

MPC8280 Documentation

Documentation

Application Note

ID

AN2059

AN2070

AN2129

AN2130

AN2131

Name Vendor ID Format

Size

K

Rev

#

AN2059

MPC8260 PowerQUICC II Data Error Protection

Implementation

Instruction and Data Cache Locking on the G2

Processor Core

FREESCALE

FREESCALE

FREESCALE

MPC8260 ADS Revision Changes From ENG Board To

PILOT Revision Board

FREESCALE

MPC8260 ADS - Revising Code Designed for the ENG

Board to Also Run on the PILOT Board

FREESCALE pdf 1/01/1 pdf 24 0 6/15/2000 pdf pdf

0 n/a

141

139

0 4/26/1999

0 pdf 48 1

Date Last

Modified

10/19/1999

12/08/1999

Order

Availability

-

-

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8280&nodeId=018rH3bTdG2977 (5 of 25) [11/10/2004 3:47:21 PM]

MPC8280 Product Summary Page

AN2162

AN2165

AN2176

AN2177

AN2178

AN2179

AN2246

AN2291

AN2335

AN2347

AN2349

AN2431

AN2654

AN2754

AN2431SW

AN2491

AN2547

AN2547SW

AN2585

AN2587

Comparing the MSC8101 and MPC8260

MPC8260 SDRAM Support

MPC8260 GPCM Timing Diagram

MPC8260 IDMA Timing Diagram

MPC8260 SDRAM Timing Diagram

MPC8260 UPM Timing Diagram

MPC8260 60x Bus Timing Diagram

Differences among PowerQUICC II Devices and

Revisions

MPC8260 Dual-Bus Architecture and Performance

Considerations

Using an MPC8260 and an MPC7410 with Shared

Memory

MPC8260 Reset and Configuration Word

PowerQUICC II PCI Example Software

PowerQUICC II PCI Example Software

Simplified Mnemonics for PowerPC Instructions

Detecting a CPM Overload on the PowerQUICC II

Software Detecting CPM Overload (accompanies

AN2547)

MPC82xx PowerQUICC II Reset: Sources, Effects, and

Comments

Software Migration from the NPe495H/L to

PowerQUICC II

Interfacing SDRAM Devices to the MPC8280 at 100

MHz

CPM Architecture and Downloading RAM Microcodes on the PowerQUICC II Family

FREESCALE

FREESCALE

FREESCALE

FREESCALE

FREESCALE

FREESCALE

FREESCALE

FREESCALE

FREESCALE

FREESCALE

FREESCALE

FREESCALE

FREESCALE

FREESCALE

FREESCALE

FREESCALE

FREESCALE

FREESCALE

FREESCALE

FREESCALE pdf pdf pdf pdf pdf

483

207

138

145

0

12/19/2001

127

0.2 9/18/2003

1 8/01/2001

1 8/01/2001

1 8/01/2001 pdf 94 1 8/01/2001 pdf 96 1 8/01/2001 pdf

187

1.4 9/30/2003 pdf 61 0 pdf

461

0

10/15/2002

10/01/2002 pdf 90 0 pdf zip pdf

180

726

524

0

0

10/01/2002

12/20/2002

12/20/2002

0 9/30/2003 pdf 80 0 6/30/2003 zip pdf 84 0.1 2/26/2004 pdf pdf zip

288

439

459

207

0 6/30/2003

0.1 1/28/2004

0 2/10/2004

0 9/30/2004 http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8280&nodeId=018rH3bTdG2977 (6 of 25) [11/10/2004 3:47:21 PM]

-

-

-

-

MPC8280 Product Summary Page

Data Sheets

ID

MPC8280EC

Name

MPC8280 Hardware Specifications

Vendor ID

FREESCALE

Format pdf

Size

K

1267

Rev

#

1

Date Last

Modified

2/16/2004

Order

Availability

Errata -

Click here for important errata information

ID

MPC8280CE

Name

MPC8280 PowerQUICC II Family Device Errata

Vendor ID Format

Size

K

Rev

#

FREESCALE pdf

214

0.3

Date Last

Modified

6/28/2004

Order

Availability

-

Fact Sheets

ID Name Vendor ID Format

Size

K

Rev

#

MPC8280FACT

MPC8280 POWERQUICC II PROCESSOR FAMILY

FREESCALE pdf

150

4

Date Last

Modified

1/18/2004

Order

Availability

Packaging Information

ID

TBGAPRESPKG

Name

TBGA Packaging Customer Tutorial

Vendor ID Format

FREESCALE pdf

Size

K

1784

Rev

#

0

Date Last

Modified

8/05/2003

Order

Availability

-

Product Change Notices

ID

PCN9586

Name Vendor ID Format

Size

K

Rev

#

POWERQUICC II MPC8280 FAMILY NEW ERRATA FREESCALE htm 9 0

Date Last

Modified

Order

Availability

2/20/2004

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8280&nodeId=018rH3bTdG2977 (7 of 25) [11/10/2004 3:47:21 PM]

MPC8280 Product Summary Page

Product Numbering Scheme

ID

MPC82XXHIP7PNS

Name

MPC82xx HiP7 Part Numbering Scheme

Vendor ID Format

Size

K

FREESCALE jpg

156

Rev

#

Date Last

Modified

0 8/01/2003

Order

Availability

-

Reference Manual

ID

G2CORERM

MPC8280RM

MPCFPE32B

MPC60XBUSRM

MPCFPE32BAD

MPC8260ESS7UMAD_D

Name

G2 Core Reference Manual

The Bus Interface for 32-Bit Microprocessors that Implement the PowerPC Architecture

Enhanced SS7 Microcode Specification

Vendor ID Format

Size

K

FREESCALE pdf

5948

Rev

#

Date Last

Modified

1 6/27/2003

Order

Availability

FREESCALE

FREESCALE

MPC8280 PowerQUICC II" Family Reference

Manual

FREESCALE

Programming Environments Manual for

32-Bit Implementations of the PowerPC

Architecture

Errata to MPCFPE32B, Programming

Environments Manual for 32-Bit

Implementations of the Power PC

Architecture, Rev. 2

FREESCALE

FREESCALE pdf

2527

0.1 1/14/2004 pdf 325 0.1

12/05/2002 pdf

8405

0 3/30/2004 pdf pdf

6909

2

40 0

12/21/2001

10/11/2002

-

White Paper

ID Name

MPC826XSDRAMWP

Timing Considerations when Interfacing the

PowerQUICC II to SDRAM

Vendor ID Format

Size

K

FREESCALE pdf

103

Rev

#

0.1

Date Last

Modified

3/09/2004

Order

Availability

Return to Top

MPC8280 Design Tools http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8280&nodeId=018rH3bTdG2977 (8 of 25) [11/10/2004 3:47:21 PM]

MPC8280 Product Summary Page

Hardware Tools

Analyzers

Logic

ID Name Vendor ID Format

Size

K

Rev

#

Order

Availability

TLA700 Logic Analyzers

The TLA700 Logic Analyzers have the performance to

TLA715/TLA721 capture and display the fastest signals and gives you instant insight into the digital and analog behavior of your system so you can quickly find those elusive signal integrity problems

TEKTRONIX

- - - -

Emulators/Probes/Wigglers

ID Name Vendor ID Format

Size

K

Rev

#

Order

Availability

WireTAP Run Control for the PowerPC Microprocessor

Feature-packed, no nonsense run control tool that allows

HW-WIRETAPCOP developers to save precious development time during target bring-up and debug. Providing visibility and control of on-chip debug (OCD) features of PowerPC microprocessors.

BDI1000/BDI2000

BDI1000/BDI2000

Abatron develops and produces high-quality, high-speed

BDM and JTAG Debug Tools (BDI Family) for software development environments from leading vendors.

10200A

NetICE-R option 2/2M

PROBE

Green Hills Probe & Slingshot

WBDM8XX

WNPJ-COP

Wiggler for 5xx/8xx BDM

The Wiggler is a low-cost, parallel port interface used for debugging embedded systems. One side of the Wiggler interfaces to the parallel port of a Windows host PC and the other side connects to the BDM port of the target system.

Wiggler for COP

The Wiggler is a low-cost, parallel port interface used for debugging embedded systems. One side of the Wiggler interfaces to the parallel port of a Windows host PC and the other side connects to the COP port of the target system.

METROWERKS

- - -

ABATRON

CORELIS

- - -

GREENHILLS

- - -

MACRAIGOR

MACRAIGOR

-

-

-

-

-

-

-

-

-

-

-

-

-

-

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8280&nodeId=018rH3bTdG2977 (9 of 25) [11/10/2004 3:47:21 PM]

MPC8280 Product Summary Page

GUARDIAN-SE

WPICE

Guardian-SE

JTAG debug tools for PowerPC development

WIND®POWER ICE

TOOLSMITHS

- - -

WINDRIV

- - -

-

-

Evaluation/Development Boards and Systems

ID Name

MPC8260ADS_ECOM

MPC8260ADS Daughter Card for Telephony

Applications (E1)

MPC8260ADS_TCOM

MPC8260ADS Daughter Card for Telephony

Applications (T1)

PQ2FADS_ZU

MPC82xx Family Application Development System

Vendor ID Format

Size

K

FREESCALE

FREESCALE

-

-

-

-

Rev

#

-

-

FREESCALE - - -

CW8280DSEVAL

CW8280DSEVAL

QUICCStart MPC8280 Evaluation System

MPC8280 Evaluation System enables evaluation and

CWH-PPC-8280N-VX development to begin before hardware is available with a solid platform for engineers to evaluate and prototype designs that closely parallel their final applications.

RATTLER8280

Rattler8280 eCos/linux

Development board with eCos and Linux OS Ports,

Complete tool set supplied with board

EP8280M-H-10

EP82xxM

EP82xxM is a PMC/stand alone single board computer using the 8280/70/66/65/50. PMC PCI, two 10/100

Ethernet, RS232 provided. Direct access to the 82xx IO allows OEMs to create solutions quickly. Linux,

VxWorks and INTEGRITY are available.

SBCPQII

SBCPowerQUICCII

METROWERKS

- - -

METROWERKS

- - -

ANAMIC

EMDPLAN

WINDRIV

-

-

-

-

-

-

-

-

-

Order

Availability

-

-

-

-

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8280&nodeId=018rH3bTdG2977 (10 of 25) [11/10/2004 3:47:21 PM]

MPC8280 Product Summary Page

Models

BSDL

ID Name

MPC827080BSDL1

PowerQUICC II (HiP7) TBGA package, BSDL model

(10/22/2003)

Vendor ID Format

Size

K

Rev

#

Order

Availability

FREESCALE zip 10 0.1 -

Bus Functional Models

ID

PQ27LNXBFM

PQ27SOLBFM

Name

PowerQUICC II HiP7 SWIFT Bus Model for Linux

(01/28/2003)

PowerQUICC II HiP7 SWIFT Bus Model for Solaris

(10/07/2003)

Vendor ID Format

FREESCALE tar

Size

K

38160

FREESCALE tar

45625

Rev

#

Order

Availability

0

2

-

-

Full Functional Models

ID Name

PQ27LNXFFM

PQ27SOLFFM

EP100

EP201

EP300

EP433

ES100

PowerQUICC II HiP7 SWIFT Full-Function Model for

Linux

(01/28/2003)

PowerQUICC II HiP7 SWIFT Full-Function Model for

Solaris

(01/28/2003)

PowerPC Bus Slave

PowerPC Bus Master

PowerPC Bus Arbiter

PowerPC-PCI Bridge

PowerPC System Controller

Vendor ID Format

Size

K

Rev

#

Order

Availability

FREESCALE tar

40540

0 -

FREESCALE tar

47566

0

EUREKA

EUREKA

EUREKA

EUREKA

EUREKA

-

-

-

-

-

- -

- -

- -

- -

- -

-

-

-

-

-

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8280&nodeId=018rH3bTdG2977 (11 of 25) [11/10/2004 3:47:21 PM]

MPC8280 Product Summary Page

IBIS

ID Name

PQ27TBGAIBIS

480-pin TBGA IBIS model for local bus and PCI bus

For MPC8270, MPC8280.

(09/07/2004)

Vendor ID Format

Size

K

Rev

#

Order

Availability

FREESCALE zip 63 1.6 -

Timing Models

ID

PQIIGPCMTIME

Name

GPCM Timing Generator

(05/29/2003)

Vendor ID

FREESCALE

Format

Size

K

Rev # exe 176 1

Order

Availability

-

Software

Application Software

Calculators

ID Name Vendor ID Format

Size

K

Rev

#

Order

Availability

Power Consumption Calculator for all PowerQUICC II

MPC8260CALC1

Processors

(04/28/2004)

CPM Performance Calculator for all PowerQUICC II and

MPC8260CALC2

PowerQUICC III Processors

(09/07/2004)

FREESCALE zip

FREESCALE zip

491

664

2.1

3.1.3

-

-

Code Examples

ID Name

MPC8260COD08

Fast Ethernet on the FCC of the PowerQUICC II

(10/13/2003)

Vendor ID Format

FREESCALE zip

Size

K

140

Rev

#

2

Order

Availability

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MPC8280 Product Summary Page

Microcode

ID Name Vendor ID Format

Size

K

Rev

#

Order

Availability

MPC8260MC05

RAM Microcode Patches for PowerQUICC II Family

Device Errata

(09/28/2004)

FREESCALE

MPC8260MC11

MPC8264MC01

DG02010101

PowerQUICC II AAL2 Microcode (for all revs)

(02/23/2004)

Inverse-Multiplexing for ATM (IMA) Microcode (for all revs)

(02/03/2004)

MultiRing

MultiRing is a utility that separates frames of different protocols into different buffer descriptor rings (rather than a single ring). The utility supports predefined protocols such as TCP, ICMP. The user can specify additional protocols.

FREESCALE

FREESCALE

DOGAV zip zip zip

-

330

386

283

-

4.2.3

3.8

1.2

-

-

-

-

-

Board Support Packages

ID Name Vendor ID Format

Size

K

Rev

#

Order

Availability

Arabella MPC82XX Free Reference Design

This free Linux BSP provides a complete Linux distribution

ARA-MOT-82XX-FREE and application ready to be used on the PQ2FADS-ZU/VR and MPC8260/8266ADS Boards. Source code and Linux tools are provided to immediately get started working with a Linux syste

ARABELLA

- - - -

ARC-MOT-MQXBSP

EP BSP

MQX Board Support Packages

BSPs for Freescale ColdFire, PowerPC, and 68K embedded processors including support for emerging USB and CAN technologies as well as drivers for Ethernet, PCI, HDLC,

SPI, I2C, and serial devices.

EP BSP

Embedded Planet Board Support Packages provide complete software drivers for MPC 8xx and 82xx processors for Linux, VxWorks and INTEGRITY.

Embedded Planet can also develop customer specific software for many operating systems.

ARC

EMDPLAN

-

-

-

-

-

-

-

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MPC8280 Product Summary Page

EP8280M VDK 10

EP82xxM VxWorks BSP

VxWorks Board Support Packages contain prebuilt RAM and ROM kernel images and documentation that describes installing and running the BSP. See online matrix for supported peripherals.

EMDPLAN

- - - -

Device Drivers

ID Name Vendor ID Format

Size

K

Rev

#

Order

Availability

USB Host/Device Developer's Kits

Supports on-chip USB host or device controllers.

ARC-MOT-USBDEVKITS

Comprised of USB host or device stack, class driver framework and example device drivers, all integrated with

MQX RTOS & provided royalty-free and in source code.

PCS

PlanetCore

PlanetCore provides a complete set of firmware device drivers for 8xx and 82xx Motorola processors. These drivers include an application / RTOS boot loader, flash burner and diagnostics. customer specific drivers can also be developed.

ARC

- - -

EMDPLAN

- - -

-

-

Libraries

ID

PN311-1

Name

Vendor

ID

Format

Size

K

Rev

#

Order

Availability

KwikPeg GUI

KADAK's KwikPeg Graphical User Interface (GUI) is derived from

PEG, a professional, high-quality graphic system created by Swell

Software, Inc. to enable you, the embedded system developer, to easily add graphics to your products.

KADAK

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MPC8280 Product Summary Page

Operating Systems

ID Name

ARC-MOT-MFS

CMX-RTX

ARC-MOT-MQX

MFS

MS-DOS File System is a portable, compatible implementation of the Microsoft MS-DOS file system

MQX Real Time Operating System

A robust, high performance, royalty-free kernel designed for deeply embedded applications requiring a small footprint and fast response.

CMX-RTX

CMX00300

CMX00300A

CMX00300B

CMX00300C

CMX00300D

CMX TCP/IP

CMX TCP/IP is a full-featured and fast TCP/IP stack that allows designers to offer networking connectivity for their embedded applications. CMX TCP/IP offers a low licensing fee, full source code, no royalties, and free technical support.

TCP/IP DHCP Client

The CMX TCP/IP DHCP Client Add-On Option provides CMX

TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the Dynamic Host Configuration

Protocol standard. A source code example is provided for fast design start up.

TCP/IP DHCP Server

The CMX TCP/IP DHCP Server Add-On Option provides

CMX TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the Dynamic Host Configuration

Protocol standard. A source code example is provided for fast design start up.

TCP/IP FTP C/S

The CMX TCP/IP FTP Client/Server Add-On Option provides

CMX TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the File Transfer Protocol standard. A source code example is provided for fast design start up.

TCP/IP IMAP4

The CMX TCP/IP IMAP4 Add-On Option provides CMX

TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality for the Internet Message Access Protocol Version

4 standard. A source code example is provided for fast design start up.

Vendor ID Format

Size

K

Rev

#

Order

Availability

ARC

ARC

CMX

CMX

CMX

CMX

CMX

CMX

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

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MPC8280 Product Summary Page

CMX00300E

CMX00300F

CMX00300I

CMX00300J

CMX00300G

CMX00300H

CMX00300K

TCP/IP NAT

The CMX TCP/IP NAT Add-On Option provides CMX TCP/IP

(see CMX00300, CMX00305, or CMX00310) with functionality to add Network Address Translation function to a network application. Source code example provided for fast design start up.

TCP/IP POP3

The CMX TCP/IP POP3 Client Add-On Option provides CMX

TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the Post Office Protocol Client standard. A source code example is provided for fast design start up.

TCP/IP PPP

The CMX TCP/IP PPP Add-On Option provides CMX TCP/IP

(see CMX00300, CMX00305, or CMX00310) with functionality to support the Point to Point Protocol serial or modem connectivity standard. Source code example provided for fast start up.

TCP/IP PPPoE

The CMX TCP/IP PPPoE Add-On Option provides CMX

TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the Point to Point Protocol over

Ethernet standard. A source code example is provided for fast design start up.

TCP/IP SMTP

The CMX TCP/IP SMTP Client Add-On Option provides CMX

TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the Simple Mail Transfer Protocol standard. A source code example is provided for fast design start up.

TCP/IP SNMP

The CMX TCP/IP SNMP V1 and V2c Add-On Option provides

CMX TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the Simple Network Management

Protocol standard. Source code example provided for fast design start up.

TCP/IP Telnet

The CMX TCP/IP Telnet Server Add-On Option provides

CMX TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the Telnet Server standard. A source code example is provided for fast design start up.

CMX

CMX

CMX

CMX

CMX

CMX

CMX

- - - -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

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MPC8280 Product Summary Page

CMX00300L

CMX00300M

CMX00300N

CMX00630

TCP/IP TFTP

The CMX TCP/IP TFTP Client/Server Add-On Option provides

CMX TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the Trivial File Transfer Protocol

Client/Server standard. Source code example for fast start up.

TCP/IP Web Client

The CMX TCP/IP Web Client/Server Add-On Option provides

CMX TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the Hyper Text Transfer Protocol

(HTTP) Web Client/Server standard. Source code example provided.

TCP/IP Web Server

The CMX TCP/IP Web Server Add-On Option provides CMX

TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the Hyper Text Transfer Protocol

(HTTP) Web Server standard. Source code example provided for fast start up.

CMX-FFS

CMX-FFS is a very small, standard Flash File System that allows designers to offer file system functionality for their embedded applications. CMX-FFS offers a low licensing fee, full source code, no royalties, and free technical support.

CMX00631

CMX00632

CMX-FFS-NAND

CMX-FFS-NAND is an Add-On Option for CMX- FFS that allows designers to include a NAND driver for their embedded

FFS applications. CMX-FFS-NAND offers a low licensing fee, full source code, no royalties, and free technical support.

CMX-FFS-FAT

CMX-FFS-FAT is a fast file system for embedded developers who wish to add devices to their products that require

FAT12/16/32 compliant media. CMX-FFS-FAT offers a low license fee, full source code, no royalties, and free tech support.

CMX00633

CMX-FFS-THIN

CMX-FFS-THIN is a file system for embedded device developers with limited resource products that require a

FAT12/16/32 compliant media. CMX-FFS-THIN offers a low licensing fee, full source code, no royalties, and free technical support.

DPP.82XXX.KRN

OSE Real-Time Operating System

CMX

CMX

CMX

CMX

CMX

CMX

CMX

ENEA

- - - -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

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MPC8280 Product Summary Page

THREADX

PX382-1

VXWORKS 5.X

ThreadX

RTOS. Royalty-free real-time operating system (RTOS) for embedded applications. ThreadX is small, fast, and royalty-free making it ideal for high-volume electronic products.

AMX PPC32

AMX is a full featured RTOS for the PowerPC family. AMX has been tested on the EST SBC8260, Embedded Planet RPX

Lite MPC823 and Motorola Ultra 603, MBX860, MPC860

ADS, MPC860 FADS, Lite5200EVB and MPC8560 ADS.

VxWorks

VxWorks, the run-time component of TORNADOII for

VxWorks, is the most widely adopted real-time operating system (RTOS) in the embedded industry, with a reputation for performance, flexibility, compatibility and scalability.

EXPRESSLOG

- - -

KADAK

WINDRIV

-

-

-

-

-

-

-

-

-

Protocol Stacks

ID Name

ARC-MOT-HTTP

ARC-MOT-IPSHIELD

HTTP Web Server

The HTTP (Hyper text Transfer Protocol) consists of source code and development tools for building an embedded HTTP server.

This is a HTTP 1.0/1.1 compliant Web server with CGI-style user exit support and optional file system support.

IPShield

Security product support for IPSec, IKE, SSL and SSH. Also supports hardware accelerated encryption on processors with an Integrated

Security Engine such as MCF5485/5483,

MPC870/875, MPC8272/8248, MCF5271, and MCF5275/5275L.

Network Protocols

TCP/IP networking stack (ARP, BootP, CCP,

CHAP, DHCP, DNS, Echo, EDS, FTP,

ARC-MOT-NETWORKPROTOCOLS

ICMP, IGMP, IP, IP-E, IPCP, LCP, PAP,

PPP, RIPv2, RPC, SNMPv1/v2, SNTP, TCP,

TFTP, Telnet, UDP & XDR)& opt'al prototocols, SMTP, SNMPv3, PPPoE, XML,

SSL/H

Vendor ID Format

Size

K

Rev

#

Order

Availability

ARC

ARC

ARC

-

-

-

-

-

-

-

-

-

-

-

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MPC8280 Product Summary Page

ARC-MOT-POP3

ARC-MOT-RTCS

ARC-MOT-SMTP

RSTP

TARGETTCP

CMX TCP/IP

IPLITE

POP3

Enables client embedded devices to receive e-mail from any POP3 server

RTCS

A real-time, high performance TCP/IP stack designed specifically for embedded networking applications such as IP phones, bridges, routers, pagers, PDAs, cellular phones, and set-top boxes

SMTP

Royalty free source code SMTP enables embedded devices to send e-mail to any

SMTP server. This allows any embedded device to send asynchronous status reports using email.

AvniRSTP

Avnisoft's AvniRSTP is a completely portable ANSI C compliant implementation of the IEEE 802.1w RSTP Algorithm and

Protocol. It includes the AvniPORT platform abstraction layer to simplify integration with target platforms.

TCP/IP Stack

TargetTCP, is a fast, reliable, re-entrant, full-featured TCP/IP protocol stack designed specifically for high-performance embedded networking. The code has a small footprint and is well suited to memory constrained environments.

ARC

ARC

ARC

AVNISOFT

BLUNK

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

CMX TCP/IP

IPLITE

IPLITE is a dual-mode IPv4/v6 host stack, optimized for minimum footprint and maximum performance, with a number of

PowerQUICC II/III optimizations. Available for leading RTOSs like INTEGRITY, Linux,

OSE, VxWorks, etc.

CMX

- - -

INTERPEAK

- - -

-

-

-

-

-

-

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MPC8280 Product Summary Page

IPNET

PN713-1

INFOLINK-STACKNAME

MOC_SSL_CLIENT

PSQ40XXXX

IPNET

IPNET is a full-featured dual-mode IPv4/v6 router stack with built-in IPSec, Virtual

Routing, QoS, VLAN Tagging, as well as

PowerQUICC II/III optimizations. Available for leading RTOSs like INTEGRITY, Linux,

OSE, VxWorks, etc.

KwikNet

The KwikNet TCP/IP Stack enables you to add networking features to your products with a minimum of time and expense.

KwikNet is a compact, high performance stack built with KADAK's characteristic simplicity, flexibility and reliability.

INFOLink Protocol Software Family

INTERPEAK

- - -

KADAK

LINK

-

-

-

-

-

-

Mocana Embedded SSL/TLS Client

MOCANA SSL/TLS CLIENT: Supports

Freescale chipsets out of the box. Small

(50KB), fast (2-3x faster than OpenSSL), trusted. Supports all major cryptos. Royalty free, source code license. FREE EVAL: http://www.mocana.com/evaluate.html

RTXC Quadnet Networking Protocols

Full protocol suite: TCP, UDP, SLIP, ICMP, and ARP with Berkeley Sockets API. Plus

DHCP, BOOTP, DNS, IGMP v2, RIP v2,

NAT, HTTP, SMTP, POP3, TFTP, FTP,

Telnet, SNMP v1,2,3, PPP and more. New security protocols: SSL, IPsec, IKE.

MOCANA

QUADROS

-

-

-

-

-

-

-

-

-

-

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MPC8280 Product Summary Page

Software Tools

Code Translation

ID

PA68K-PPC

PA86-PPC

Name

PortAsm/68K for PowerPC

PortAsm/86 for PowerPC

Vendor ID

MICROAPL

MICROAPL

Format

-

-

Size

K

-

-

Rev #

-

-

Order

Availability

-

-

Compilers

ID Name

CWEPPC

CWLINPPC

CodeWarrior Development Studio for PowerPC"

Processors

CodeWarrior Development Studio. Linux Application

Edition for PowerPC

CWS-PPC-LLPLT-CX

GNUTOOL

CodeWarrior Development Studio, PowerPC ISA -

Linux

Gnu Tool set

ARC-MOT-COMPILER

MetaWare C/C++ Compiler Tool Suite

Optimized compiler for Motorola processors

COMPILER

C/C++ Compiler

Optimizing C, C++, EC++ compilers for Freescale

PowerPC, ColdFire, StarCore, 68K and ARM-based

MAC architectures.

DIAB

Diab C/C++ Compiler

Vendor ID Format

Size

K

Rev

#

Order

Availability

METROWERKS

- - - -

METROWERKS

- - -

METROWERKS

- - -

ANAMIC

ARC

GREENHILLS

WINDRIV

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Debuggers

ID

CWNETROM540A

Name Vendor ID Format

Size

K

Rev

#

Order

Availability

Metrowerks NetROM

A Flexible Platform for Accelerated Embedded

Development: NetROM is a revolutionary product for embedded software developers. It provides a flexible debugging platform that combines high-speed target communication and debugging capabilties

METROWERKS

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MPC8280 Product Summary Page

HW-WIRETAPCOP

WireTAP Run Control for the PowerPC

Microprocessor

Feature-packed, no nonsense run control tool that allows developers to save precious development time during target bring-up and debug. Providing visibility and control of on-chip debug (OCD) features of

PowerPC microprocessors.

ARC-MOT-DEBUGGER

MetaWare SeeCode Debugger

C/C++ Debugger

POWERPC

DEBUGGER

MULTI Debugger

LA-7729

TRACE32-ICD

TRACE32-ICD for PowerQUICC II is a high performance JTAG debugger for C ,C++ and JAVA. A

USB 2.x, LPT or ethernet interface is available for connection to any PC or workstation. A flash programming utility is included.

METROWERKS

- - -

ARC

GREENHILLS

LAUBACH

-

-

-

-

-

-

-

-

-

-

-

-

-

Emulation

ID Name

MWCTST4SWICCORE

CodeTEST Analysis Tools, Software In-Circuit

CodeTEST Software In-Circuit (SWIC) is the ideal solution for integrating your application software with your target hardware.

Vendor ID Format

Size

K

Rev

#

METROWERKS

- - -

Order

Availability

-

IDE (Integrated Development Environment)

ID Name Vendor ID Format

Size

K

Rev

#

Order

Availability

CE-PPCQNX21

CodeWarrior for QNX RTOS

Provides a complete toolchain for creating, compiling, linking, and debugging your projects within a single environment. It also offers an application level debugger with multiple process and thread awareness support.

CodeWarrior for PowerQUICC III

CWPPC1BWPQ3

CodeWarrior Development Studio, PowerQUICC III Edition support the whole development process from board bring-up through application development.

METROWERKS

- - -

METROWERKS

- - -

-

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MPC8280 Product Summary Page

MULTI

WPIDE

WIND RIVER

WORKBENCH

MULTI

MULTI is a complete integrated development environment for embedded applications using C, C++, Embedded C++

Wind River Workbench

Wind River Workbench is an open, standards-based device software development environment for Linux applications providing a deep tools capability in each phase of the development process.

WIND®POWER IDE

GREENHILLS

- - -

WINDRIV

WINDRIV

-

-

-

-

-

-

-

-

-

Initialization/Boot Code Generation

ID Name

MPC82XXCPMMUXIBCG

MPC82XXLBCUPMIBCG

Parallel Ports Configuration Tool (Pin Mux Tool)

(03/18/2004)

UPM Tool for PowerQUICC II Processors

(12/11/2003)

Vendor ID Format

Size

K

FREESCALE zip

985

Rev

#

4.0.0

Order

Availability

-

FREESCALE zip

137 2.2.1

-

Return to Top

Orderable Parts Information

Part Number

Package

Description

CWH-PPC-8280N-VX No

KMPC8280CZUUPE

KMPC8280ZUUPE

FTBGA 480

37*37*1.7P1.27

No

FTBGA 480

37*37*1.7P1.27

No

Tape and

Reel

Pb-Free

Terminations

No

No

No

Application/

Qualification

Tier

Status

Budgetary

Price

QTY

1000+

($US)

Info

Available $895.00

more

COMMERCIAL,

INDUSTRIAL

Available

COMMERCIAL,

INDUSTRIAL

Available

-

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Order

MPC8280 Product Summary Page

MPC8280CZUQLD

MPC8280CZUUPE

MPC8280ZUQLD

MPC8280ZUUPE

FTBGA 480

37*37*1.7P1.27

No

FTBGA 480

37*37*1.7P1.27

No

FTBGA 480

37*37*1.7P1.27

No

FTBGA 480

37*37*1.7P1.27

No

No

No

No

No

COMMERCIAL,

INDUSTRIAL

COMMERCIAL,

INDUSTRIAL

-

-

Available

Available

Available

Available

NOTE:

Cannot find a Sample? Request a sample . Refer to Samples FAQ for more information.

Looking for an obsolete part? Check our distributors' inventory

Return to Top

-

-

-

more more more more

Related Products

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The 33702 is a monolithic IC providing an efficient means of obtaining power for the Freescale Semiconductor PowerQUICC TM

I and II ...

MPC9850 : Clock Generator for PowerPC and PowerQUICC Applications

The MPC9850 is a PLL based clock generator specifically designed for Freescale Microprocessor And Microcontroller applications including the PowerQUICC III. ...

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The MPC9855 is a PLL based clock generator specifically designed for Freescale Microprocessor and Microcontroller applications including the PowerPC and ...

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Related Links

Industrial Control

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MPC8275 Product Summary Page

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About Freescale

Freescale > PowerPC Processors > MPC82XX PowerQUICC II Processors > MPC8275

MPC8275 : PowerQUICC II Integrated Communications Processor

Introducing the next generation of PowerQUICC II" processors: the MPC8270,

MPC8275 and MPC8280.

Utilizing Freescale's HiPerMOS7 0.13-micron process technology, the next generation

PowerQUICC II family offers a range of performance, feature enhancements and package options with lower power requirements. Ideal for wired and wireless infrastructure communications processing tasks, enhancements to the PowerQUICC II family offer system designers a high degree of integrated features and functionality and a compelling, proven architecture.

The next generation of PowerQUICC II processors is an optimum solution for integrated control and forwarding plane processing in high-end communications and networking equipment -- such as routers, DSLAMs, remote access concentrators, telecom switching equipment and cellular base stations. Combining extensive layer 2 functionality with control plane processing, Freescale's PowerQUICC II processors include a high-performance embedded PowerPC 603e" core and a powerful RISC-based

Communications Processor Module (CPM). The CPM off-loads peripheral tasks from the embedded PowerPC core and provides support for multiple communications protocols, including 10/100Mbps Ethernet, 155Mbps ATM and 256 HDLC channels. And, of course, the next generation PowerQUICC II devices retain full software compatibility with the PowerQUICC II family.

A range of performance and package options

Taking advantage of the 0.13-micron process, the next generation of PowerQUICC II http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8275&nodeId=018rH3bTdG2977 (1 of 27) [11/10/2004 3:45:55 PM]

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MPC8275 Product Summary Page devices offers significant performance increases and power savings over the current generation PowerQUICC II devices, with speeds of up to 450MHz and 300MHz in the core and CPM respectively at less than 2 watts. The new processors continue to enhance the PowerQUICC architecture's industry-leading ATM support, offering up to 2 UTOPIA ports with support for up to 31 PHYs per interface -- ideal for high-density DSLAM line cards.

The next generation of PowerQUICC II solutions also delivers support for USB, an on-target addition for high performance SOHO and CPE networking equipment. And unlike most other integrated communications processors in the market, the PowerQUICC architecture integrates two processing cores to handle specific tasks: the PowerPC core and the RISC-based CPM -- enabling a balanced approach for systems by handling both high-level tasks and low-level communications all in one integrated device.

Product Picture

MPC8275 Features

MPC8275ZQ/VR Features

603e core with 16K inst and 16K data caches

64-bit 60x bus, 32-bit PCI/local bus

128K ROM, 32K IRAM, 32K DPRAM

Three FCCs supporting ATM, 10/100 Ethernet or HDLC (no IMA/TC support)

128 HDLC channels, 4 TDMs

4 SCCs, 2 SMCs, SPI, I2C

Memory controller built from SDRAM, UPM, GPCM machines

New features -- USB, RMII, UTOPIA improvements

Performance

266 MHz CPU, 200 MHz CPM, 66 MHz bus

~1W @ full performance, 1.5V

Technology

HIP7AP .13 micron, 3.3V I/O, 1.5V Core

516 PBGA, 27x27mm, 1mm ball pitch

ZQ package has lead-bearing spheres

VR package is lead-free

MPC8280 Family

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MPC8275 Product Summary Page

Performance

-- CPU

-- CPM

--

60x/Memory

Bus

-- Local

Bus

-- I/D

Cache

CPM Interfaces

-- PCI

-- FCCs

MII/RMII

8270VR 8270 8275VR 8280

266

200

66

66

16/16

YES

3

(Fast

Ethernet)

UTOPIA

(ATM)

--

Multichannel

HDLC

-- SCCs

3

0

128

-- USB

-- SMCs

4

1

2

-- I2C/SPI

1

IMA/TC Functionality

NO

333/450

250/300

83/100

83/100

16/16

YES

3

3

0

128

4

1

2

1

NO

266

200

66

66

16/16

YES

3

3

2

128

4

1

2

1

NO

333/450

250/300

83/100

83/100

16/16

YES

3

3

2

256

4

1

2

1

YES

Package

516

PBGA

480

TBGA

516

PBGA

480

TBGA

PowerQUICC II Masks and Versions

Process

0.29

µm

Family Revision Qualification Mask

A.1

B.3

XC

XC

PVR

IMMR_

[16-31]

1

Rev_Num

2

0K26N 0x00810101 0x0011 0x0001

3K23A 0x00810101 0x0023 0x003B http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8275&nodeId=018rH3bTdG2977 (3 of 27) [11/10/2004 3:45:55 PM]

MPC8275 Product Summary Page

(HiP3)

0.13

µm

(HiP7)

MPC8260 C.2

0.25

µm

(HiP4)

A.0

B.1

C.0

0.0

MPC8280

0.1

A.0

MPC8272

0.0

A.0

XC

XC

MC

MC

MC

MC

PC

MC

6K23A,

7K23A

0x00810101 0x0024 0x007B

2K25A 0x80811014 0x0060 0x000D

4K25A 0x80811014 0x0062 0x002D

5K25A 0x80811014 0x0064 0x002D

0K49M 0x80822011 0x0A00 0x0070

1K49M 0x80822013 0x0A01 0x0070

2K49M 0x80822014 0x0A10 0x0071

0K50M 0x80822013

0x0C00

3

0x0D00

4

0x00E0

1K50M 0x80822014

0xC010

3

0xD010

4

0x00E1

Notes:

1. The IMMR[16-31] indicates the mask number.

2. The Rev_Num located at offset 0x8AF0 in DPRAM indicates the CPM microcode revision number.

3 . Encryption Enabled.

4 . Encryption Disabled.

Masks and versions table last updated on 14OCT2004.

Return to Top

CPU

Performance

(Max)

(MIPS)

Operating

Frequency

(Max)

(MHz)

CPM

Operation

Frequency

(Max)

(MHz)

Power

Dissipation

(Typ)

(W)

505.4

266 200 1.05

Power

Dissipation

(Max)

(W)

1.1

Core

Operating

Voltage

(Spec)

(V)

I/O

Operating

Voltage

(Max)

(V)

1.5

3.3

Ambient

Operating

Temperature

(Min)

(oC)

-40,

0 http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8275&nodeId=018rH3bTdG2977 (4 of 27) [11/10/2004 3:45:55 PM]

MPC8275 Product Summary Page

Junction

Operating

Temperature

(Max)

(oC)

Integrated

Memory

Controller

105

EDO,

EPROM,

FLASH,

SDRAM,

SRAM

L1 Cache

Instructional

(Max)

(Byte)

L1

Cache

Data

(Max)

(Byte)

Internal

Dual-Port

RAM

(Byte)

16000 16000 64000

DMA

Controller

Channels

30

Bus

Interface

Serial

Interface

60x,

Local,

PCI 2.2

Type

I2C,

MII,

SPI,

TDM,

USB,

UTOPIA

Other Peripherals

DMA Controller

Network Application Function

Integrated Control/Data Plane

Package Description

FPBGA 516 27*27*1.25P1.0

Return to Top

MPC8275 Parametrics

MPC8275 Documentation

Documentation

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MPC8275 Product Summary Page

Application Note

ID

AN2059

AN2070

AN2129

AN2130

AN2131

AN2162

AN2165

AN2176

AN2177

AN2178

AN2179

AN2246

AN2291

AN2335

AN2347

AN2349

AN2431

Name

AN2059

MPC8260 PowerQUICC II Data Error

Protection Implementation

Instruction and Data Cache Locking on the G2

Processor Core

MPC8260 ADS Revision Changes From ENG

Board To PILOT Revision Board

Vendor ID Format

Size

K

Rev

#

FREESCALE

FREESCALE pdf 0 n/a

Date Last

Modified

1/01/1 pdf 24 0 6/15/2000

Order

Availability

-

FREESCALE

FREESCALE

MPC8260 ADS - Revising Code Designed for the ENG Board to Also Run on the PILOT

Board

FREESCALE

Comparing the MSC8101 and MPC8260

MPC8260 SDRAM Support

FREESCALE

FREESCALE pdf pdf

141

139

0 4/26/1999

0 pdf 48 1 pdf pdf

483

0

10/19/1999

12/08/1999

12/19/2001

127

0.2 9/18/2003

-

-

MPC8260 GPCM Timing Diagram

MPC8260 IDMA Timing Diagram

MPC8260 SDRAM Timing Diagram pdf pdf pdf

207

138

145

1 8/01/2001

1 8/01/2001

1 8/01/2001 -

MPC8260 UPM Timing Diagram

MPC8260 60x Bus Timing Diagram

Differences among PowerQUICC II Devices and Revisions

MPC8260 Dual-Bus Architecture and

Performance Considerations

Using an MPC8260 and an MPC7410 with

Shared Memory

MPC8260 Reset and Configuration Word

PowerQUICC II PCI Example Software

FREESCALE

FREESCALE

FREESCALE

FREESCALE

FREESCALE

FREESCALE

FREESCALE

FREESCALE

FREESCALE

FREESCALE pdf 94 1 8/01/2001 pdf 96 1 8/01/2001 pdf

187

1.4 9/30/2003 pdf 61 0

10/15/2002 pdf pdf 90 0 pdf

461

180

0

0

10/01/2002

10/01/2002

12/20/2002

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MPC8275 Product Summary Page

AN2431SW

AN2491

AN2547

AN2547SW

AN2585

AN2587

AN2654

AN2754

PowerQUICC II PCI Example Software

Simplified Mnemonics for PowerPC

Instructions

Detecting a CPM Overload on the

PowerQUICC II

Software Detecting CPM Overload

(accompanies AN2547)

FREESCALE

FREESCALE

FREESCALE

FREESCALE

MPC82xx PowerQUICC II Reset: Sources,

Effects, and Comments

Software Migration from the NPe495H/L to

PowerQUICC II

Interfacing SDRAM Devices to the MPC8280 at 100 MHz

CPM Architecture and Downloading RAM

Microcodes on the PowerQUICC II Family

FREESCALE

FREESCALE

FREESCALE

FREESCALE zip pdf

726

524

0

12/20/2002

0 9/30/2003 pdf 80 0 6/30/2003 zip

288

0 6/30/2003 pdf 84 0.1 2/26/2004 pdf pdf zip

439

459

207

0.1 1/28/2004

0 2/10/2004

0 9/30/2004 -

-

Data Sheets

ID

MPC8280EC

Name

MPC8280 Hardware Specifications

Vendor ID Format

FREESCALE pdf

Size

K

1267

Rev

#

Date Last

Modified

1 2/16/2004

Order

Availability

Errata -

Click here for important errata information

ID

MPC8280CE

Name

MPC8280 PowerQUICC II Family Device

Errata

Vendor ID Format

Size

K

Rev

#

FREESCALE pdf

214

0.3

Date Last

Modified

6/28/2004

Order

Availability

-

Fact Sheets

ID Name

MPC8280FACT

MPC8280 POWERQUICC II PROCESSOR

FAMILY

Vendor ID Format

Size

K

Rev

#

Date Last

Modified

Order

Availability

FREESCALE pdf

150

4

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MPC8275 Product Summary Page

Packaging Information

ID Name

PBGAPRES

PBGA Packaging Customer Tutorial

TBGAPRESPKG TBGA Packaging Customer Tutorial

Vendor ID Format

FREESCALE

FREESCALE pdf pdf

Size

K

1923

1784

Rev

#

Date Last

Modified

1 8/05/2003

0 8/05/2003

Order

Availability

-

-

Product Change Notices

ID

PCN10367

PCN9586

Name

MPC8270/8275 516 PBGA REVA

INTRODUCTION

Vendor ID Format

Size

K

Rev

#

FREESCALE

POWERQUICC II MPC8280 FAMILY NEW

ERRATA

FREESCALE htm 18 0 htm 9

Date Last

Modified

10/07/2004

Order

Availability

-

0 2/20/2004 -

Product Numbering Scheme

ID Name Vendor ID Format

Size

K

Rev

#

MPC82XXHIP7PNS MPC82xx HiP7 Part Numbering Scheme

FREESCALE jpg

156

0

Date Last

Modified

8/01/2003

Order

Availability

-

Reference Manual

ID

G2CORERM

MPC60XBUSRM

Name

G2 Core Reference Manual

Vendor ID Format

Size

K

Rev

#

FREESCALE

The Bus Interface for 32-Bit

Microprocessors that Implement the

PowerPC Architecture

FREESCALE pdf pdf

5948

2527

Date Last

Modified

1 6/27/2003

0.1 1/14/2004

Order

Availability

MPC8260ESS7UMAD_D

Enhanced SS7 Microcode

Specification

MPC8280RM

MPC8280 PowerQUICC II" Family

Reference Manual

FREESCALE

FREESCALE pdf 325 0.1

12/05/2002 pdf

8405

0 3/30/2004

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MPC8275 Product Summary Page

MPCFPE32B

MPCFPE32BAD

Programming Environments Manual for 32-Bit Implementations of the

PowerPC Architecture

FREESCALE

Errata to MPCFPE32B,

Programming Environments Manual for 32-Bit Implementations of the

Power PC Architecture, Rev. 2

FREESCALE pdf

6909

2

12/21/2001 pdf 40 0

10/11/2002

White Paper

ID Name

MPC826XSDRAMWP

Timing Considerations when Interfacing the PowerQUICC II to SDRAM

Vendor ID Format

Size

K

Rev

#

FREESCALE pdf

Date Last

Modified

103

0.1

3/09/2004

Order

Availability

Return to Top

MPC8275 Reference Designs

ID Name

RDMPC8275IAD MPC8275 Smart Gateway Reference Design

Vendor ID Format

FREESCALE -

Size

K

Rev

#

- -

Order

Availability

-

Return to Top

MPC8275 Design Tools http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8275&nodeId=018rH3bTdG2977 (9 of 27) [11/10/2004 3:45:55 PM]

MPC8275 Product Summary Page

Hardware Tools

Analyzers

Logic

ID Name

TLA715/TLA721

TLA700 Logic Analyzers

The TLA700 Logic Analyzers have the performance to capture and display the fastest signals and gives you instant insight into the digital and analog behavior of your system so you can quickly find those elusive signal integrity problems

Vendor ID Format

Size

K

Rev

#

Order

Availability

TEKTRONIX

- - - -

Emulators/Probes/Wigglers

ID Name Vendor ID Format

Size

K

Rev

#

Order

Availability

WireTAP Run Control for the PowerPC

Microprocessor

Feature-packed, no nonsense run control tool that

HW-WIRETAPCOP allows developers to save precious development time during target bring-up and debug. Providing visibility and control of on-chip debug (OCD) features of PowerPC microprocessors.

BDI1000/BDI2000

BDI1000/BDI2000

Abatron develops and produces high-quality, high-speed BDM and JTAG Debug Tools (BDI

Family) for software development environments from leading vendors.

10200A

NetICE-R option 2/2M

PROBE

Green Hills Probe & Slingshot

METROWERKS

- - -

ABATRON

CORELIS

- - -

- - -

GREENHILLS

- - -

-

-

-

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MPC8275 Product Summary Page

WBDM8XX

WNPJ-COP

GUARDIAN-SE

WPICE

Wiggler for 5xx/8xx BDM

The Wiggler is a low-cost, parallel port interface used for debugging embedded systems. One side of the Wiggler interfaces to the parallel port of a

Windows host PC and the other side connects to the BDM port of the target system.

Wiggler for COP

The Wiggler is a low-cost, parallel port interface used for debugging embedded systems. One side of the Wiggler interfaces to the parallel port of a

Windows host PC and the other side connects to the COP port of the target system.

Guardian-SE

JTAG debug tools for PowerPC development

WIND®POWER ICE

MACRAIGOR

MACRAIGOR

-

-

-

-

-

-

TOOLSMITHS

- - -

WINDRIV

- - -

-

-

-

-

Evaluation/Development Boards and Systems

ID Name Vendor ID Format

Size

K

Rev

#

Order

Availability

MPC8260ADS_ECOM

MPC8260ADS Daughter Card for Telephony

Applications (E1)

MPC8260ADS_TCOM

MPC8260ADS Daughter Card for Telephony

Applications (T1)

PQ2FADS_VR

PQ2FADS_ZU

FREESCALE

FREESCALE

MPC82xx Family Application Development System FREESCALE

MPC82xx Family Application Development System FREESCALE

RATTLER-PCI

Rattler-PCI

ANAMIC

-

-

-

-

-

-

-

-

-

-

-

-

-

-

- -

RATTLER1

SBCPQII

Rattler1

SBCPowerQUICCII

ANAMIC

- - -

WINDRIV

- - - -

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MPC8275 Product Summary Page

Models

BSDL

ID Name Vendor ID Format

Size

K

Rev

#

Order

Availability

MPC827075BSDL1

PowerQUICC II (HiP7) PBGA package, BSDL model

(10/22/2003)

FREESCALE zip 10 0.1 -

Bus Functional Models

ID Name

PQ27LNXBFM

PQ27SOLBFM

PowerQUICC II HiP7 SWIFT Bus Model for

Linux

(01/28/2003)

PowerQUICC II HiP7 SWIFT Bus Model for

Solaris

(10/07/2003)

Vendor ID Format

Size

K

Rev

#

Order

Availability

FREESCALE tar

38160

0 -

FREESCALE tar

45625

2 -

Full Functional Models

ID Name

PQ27LNXFFM

PQ27SOLFFM

EP100

EP201

EP300

EP433

ES100

PowerQUICC II HiP7 SWIFT Full-Function

Model for Linux

(01/28/2003)

PowerQUICC II HiP7 SWIFT Full-Function

Model for Solaris

(01/28/2003)

PowerPC Bus Slave

PowerPC Bus Master

PowerPC Bus Arbiter

PowerPC-PCI Bridge

PowerPC System Controller

Vendor ID Format

Size

K

Rev

#

Order

Availability

FREESCALE tar

40540

0 -

FREESCALE tar

47566

0

EUREKA

EUREKA

EUREKA

EUREKA

EUREKA

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

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MPC8275 Product Summary Page

IBIS

ID Name

PQ27PBGAIBIS

516-pin PBGA IBIS model for local bus and PCI bus (VR and ZQ packages)

For MPC8270VR, MPC8270ZQ, MPC8275VR, and MPC8275ZQ.

(09/07/2004)

Vendor ID Format

Size

K

Rev

#

FREESCALE zip 64 1.6

Order

Availability

-

Timing Models

ID

PQIIGPCMTIME

Name

GPCM Timing Generator

(05/29/2003)

Vendor ID Format

Size

K

Rev

#

FREESCALE exe 176 1

Order

Availability

-

Software

Application Software

Calculators

ID Name Vendor ID Format

Size

K

Rev

#

Order

Availability

MPC8260CALC1

Power Consumption Calculator for all

PowerQUICC II Processors

(04/28/2004)

FREESCALE

MPC8260CALC2

CPM Performance Calculator for all

PowerQUICC II and PowerQUICC III Processors

FREESCALE

(09/07/2004) zip zip

491

664

2.1

3.1.3

-

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MPC8275 Product Summary Page

Code Examples

ID Name

MPC8260COD08

Fast Ethernet on the FCC of the PowerQUICC II

(10/13/2003)

Vendor ID Format

Size

K

Rev

#

Order

Availability

FREESCALE zip

140

2 -

Microcode

ID Name Vendor ID Format

Size

K

Rev

#

Order

Availability

MPC8260MC05

RAM Microcode Patches for PowerQUICC II

Family Device Errata

(09/28/2004)

FREESCALE

MPC8260MC11

PowerQUICC II AAL2 Microcode (for all revs)

(02/23/2004)

DG02010101

MultiRing

MultiRing is a utility that separates frames of different protocols into different buffer descriptor rings (rather than a single ring). The utility supports predefined protocols such as TCP, ICMP.

The user can specify additional protocols.

FREESCALE

DOGAV zip zip

-

330

386

-

4.2.3

3.8

- -

-

-

Board Support Packages

ID

ARC-MOT-MQXBSP

Name

MQX Board Support Packages

BSPs for Freescale ColdFire, PowerPC, and 68K embedded processors including support for emerging USB and CAN technologies as well as drivers for Ethernet, PCI, HDLC, SPI, I2C, and serial devices.

Vendor ID Format

Size

K

Rev

#

Order

Availability

ARA-MOT-82XX-FREE

Arabella MPC82XX Free Reference Design

This free Linux BSP provides a complete Linux distribution and application ready to be used on the PQ2FADS-ZU/VR and MPC8260/8266ADS

Boards. Source code and Linux tools are provided to immediately get started working with a Linux syste

ARABELLA

- - -

ARC

- - - -

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MPC8275 Product Summary Page

EP BSP

EP BSP

Embedded Planet Board Support Packages provide complete software drivers for MPC 8xx and 82xx processors for Linux, VxWorks and

INTEGRITY. Embedded Planet can also develop customer specific software for many operating systems.

EMDPLAN

- - - -

Device Drivers

ID Name Vendor ID Format

Size

K

Rev

#

Order

Availability

ARC-MOT-USBDEVKITS

USB Host/Device Developer's Kits

Supports on-chip USB host or device controllers.

Comprised of USB host or device stack, class driver framework and example device drivers, all integrated with MQX RTOS & provided royalty-free and in source code.

PCS

ARC

- - -

PlanetCore

PlanetCore provides a complete set of firmware device drivers for 8xx and 82xx Motorola processors. These drivers include an application /

EMDPLAN

- - -

RTOS boot loader, flash burner and diagnostics.

customer specific drivers can also be developed.

-

-

Libraries

ID

PN311-1

Name

KwikPeg GUI

KADAK's KwikPeg Graphical User Interface (GUI) is derived from PEG, a professional, high-quality graphic system created by Swell Software, Inc. to enable you, the embedded system developer, to easily add graphics to your products.

Vendor

ID

Format

Size

K

Rev

#

KADAK

- - -

Order

Availability

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MPC8275 Product Summary Page

Operating Systems

ID Name

ARC-MOT-MFS

ARC-MOT-MQX

MFS

MS-DOS File System is a portable, compatible implementation of the Microsoft MS-DOS file system

MQX Real Time Operating System

A robust, high performance, royalty-free kernel designed for deeply embedded applications requiring a small footprint and fast response.

CMX-RTX

CMX00300

CMX00300A

CMX00300B

CMX00300C

CMX-RTX

CMX TCP/IP

CMX TCP/IP is a full-featured and fast TCP/IP stack that allows designers to offer networking connectivity for their embedded applications. CMX TCP/IP offers a low licensing fee, full source code, no royalties, and free technical support.

TCP/IP DHCP Client

The CMX TCP/IP DHCP Client Add-On Option provides CMX TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the

Dynamic Host Configuration Protocol standard. A source code example is provided for fast design start up.

TCP/IP DHCP Server

The CMX TCP/IP DHCP Server Add-On Option provides CMX TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the

Dynamic Host Configuration Protocol standard. A source code example is provided for fast design start up.

TCP/IP FTP C/S

The CMX TCP/IP FTP Client/Server Add-On Option provides CMX TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the File

Transfer Protocol standard. A source code example is provided for fast design start up.

Vendor ID Format

Size

K

Rev

#

Order

Availability

ARC

ARC

CMX

CMX

CMX

CMX

CMX

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

- -

-

-

-

-

-

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MPC8275 Product Summary Page

CMX00300D

CMX00300E

CMX00300F

CMX00300I

CMX00300G

CMX00300H

TCP/IP IMAP4

The CMX TCP/IP IMAP4 Add-On Option provides

CMX TCP/IP (see CMX00300, CMX00305, or

CMX00310) with functionality for the Internet

Message Access Protocol Version 4 standard. A source code example is provided for fast design start up.

TCP/IP NAT

The CMX TCP/IP NAT Add-On Option provides

CMX TCP/IP (see CMX00300, CMX00305, or

CMX00310) with functionality to add Network

Address Translation function to a network application. Source code example provided for fast design start up.

TCP/IP POP3

The CMX TCP/IP POP3 Client Add-On Option provides CMX TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the Post

Office Protocol Client standard. A source code example is provided for fast design start up.

TCP/IP PPP

The CMX TCP/IP PPP Add-On Option provides

CMX TCP/IP (see CMX00300, CMX00305, or

CMX00310) with functionality to support the Point to

Point Protocol serial or modem connectivity standard.

Source code example provided for fast start up.

TCP/IP PPPoE

The CMX TCP/IP PPPoE Add-On Option provides

CMX TCP/IP (see CMX00300, CMX00305, or

CMX00310) with functionality to support the Point to

Point Protocol over Ethernet standard. A source code example is provided for fast design start up.

TCP/IP SMTP

The CMX TCP/IP SMTP Client Add-On Option provides CMX TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the

Simple Mail Transfer Protocol standard. A source code example is provided for fast design start up.

CMX

CMX

CMX

CMX

CMX

CMX

- - - -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

- -

-

-

-

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MPC8275 Product Summary Page

CMX00300J

CMX00300K

CMX00300L

CMX00300M

CMX00300N

CMX00630

TCP/IP SNMP

The CMX TCP/IP SNMP V1 and V2c Add-On

Option provides CMX TCP/IP (see CMX00300,

CMX00305, or CMX00310) with functionality to support the Simple Network Management Protocol standard. Source code example provided for fast design start up.

TCP/IP Telnet

The CMX TCP/IP Telnet Server Add-On Option provides CMX TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the

Telnet Server standard. A source code example is provided for fast design start up.

TCP/IP TFTP

The CMX TCP/IP TFTP Client/Server Add-On

Option provides CMX TCP/IP (see CMX00300,

CMX00305, or CMX00310) with functionality to support the Trivial File Transfer Protocol

Client/Server standard. Source code example for fast start up.

TCP/IP Web Client

The CMX TCP/IP Web Client/Server Add-On Option provides CMX TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the

Hyper Text Transfer Protocol (HTTP) Web

Client/Server standard. Source code example provided.

TCP/IP Web Server

The CMX TCP/IP Web Server Add-On Option provides CMX TCP/IP (see CMX00300, CMX00305, or CMX00310) with functionality to support the

Hyper Text Transfer Protocol (HTTP) Web Server standard. Source code example provided for fast start up.

CMX-FFS

CMX-FFS is a very small, standard Flash File System that allows designers to offer file system functionality for their embedded applications. CMX-FFS offers a low licensing fee, full source code, no royalties, and free technical support.

CMX

CMX

CMX

CMX

CMX

CMX http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8275&nodeId=018rH3bTdG2977 (18 of 27) [11/10/2004 3:45:55 PM]

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-

-

-

-

-

-

-

-

-

-

-

-

-

-

- -

-

-

-

-

MPC8275 Product Summary Page

CMX00631

CMX00632

CMX-FFS-NAND

CMX-FFS-NAND is an Add-On Option for CMX-

FFS that allows designers to include a NAND driver for their embedded FFS applications.

CMX-FFS-NAND offers a low licensing fee, full source code, no royalties, and free technical support.

CMX-FFS-FAT

CMX-FFS-FAT is a fast file system for embedded developers who wish to add devices to their products that require FAT12/16/32 compliant media.

CMX-FFS-FAT offers a low license fee, full source code, no royalties, and free tech support.

CMX00633

CMX-FFS-THIN

CMX-FFS-THIN is a file system for embedded device developers with limited resource products that require a FAT12/16/32 compliant media.

CMX-FFS-THIN offers a low licensing fee, full source code, no royalties, and free technical support.

DPP.82XXX.KRN

OSE Real-Time Operating System

THREADX

PX382-1

CMX

CMX

CMX

-

-

-

-

-

-

-

-

-

ENEA

- - -

ThreadX

RTOS. Royalty-free real-time operating system

(RTOS) for embedded applications. ThreadX is small, fast, and royalty-free making it ideal for high-volume electronic products.

EXPRESSLOG

- - -

AMX PPC32

AMX is a full featured RTOS for the PowerPC family. AMX has been tested on the EST SBC8260,

Embedded Planet RPX Lite MPC823 and Motorola

Ultra 603, MBX860, MPC860 ADS, MPC860 FADS,

Lite5200EVB and MPC8560 ADS.

KADAK

- - -

-

-

-

-

-

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MPC8275 Product Summary Page

Protocol Stacks

ID Name

ARC-MOT-HTTP

ARC-MOT-POP3

ARC-MOT-RTCS

HTTP Web Server

The HTTP (Hyper text Transfer

Protocol) consists of source code and development tools for building an embedded HTTP server. This is a

HTTP 1.0/1.1 compliant Web server with CGI-style user exit support and optional file system support.

ARC-MOT-IPSHIELD

IPShield

Security product support for IPSec,

IKE, SSL and SSH. Also supports hardware accelerated encryption on processors with an Integrated Security

Engine such as MCF5485/5483,

MPC870/875, MPC8272/8248,

MCF5271, and MCF5275/5275L.

Network Protocols

TCP/IP networking stack (ARP,

BootP, CCP, CHAP, DHCP, DNS,

Echo, EDS, FTP, ICMP, IGMP, IP,

ARC-MOT-NETWORKPROTOCOLS

IP-E, IPCP, LCP, PAP, PPP, RIPv2,

RPC, SNMPv1/v2, SNTP, TCP,

TFTP, Telnet, UDP & XDR)& opt'al prototocols, SMTP, SNMPv3, PPPoE,

XML, SSL/H

POP3

Enables client embedded devices to receive e-mail from any POP3 server

RTCS

A real-time, high performance TCP/IP stack designed specifically for embedded networking applications such as IP phones, bridges, routers, pagers, PDAs, cellular phones, and set-top boxes

Vendor ID Format

Size Rev

K #

Order

Availability

ARC

ARC

ARC

ARC

ARC

-

-

-

-

-

-

-

-

-

-

-

-

-

-

- -

-

-

-

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MPC8275 Product Summary Page

ARC-MOT-SMTP

RSTP

TARGETTCP

CMX TCP/IP

IPLITE

IPNET

SMTP

Royalty free source code SMTP enables embedded devices to send e-mail to any SMTP server. This allows any embedded device to send asynchronous status reports using email.

AvniRSTP

Avnisoft's AvniRSTP is a completely portable ANSI C compliant implementation of the IEEE 802.1w

RSTP Algorithm and Protocol. It includes the AvniPORT platform abstraction layer to simplify integration with target platforms.

TCP/IP Stack

TargetTCP, is a fast, reliable, re-entrant, full-featured TCP/IP protocol stack designed specifically for high-performance embedded networking. The code has a small footprint and is well suited to memory constrained environments.

CMX TCP/IP

IPLITE

IPLITE is a dual-mode IPv4/v6 host stack, optimized for minimum footprint and maximum performance, with a number of PowerQUICC II/III optimizations. Available for leading

RTOSs like INTEGRITY, Linux,

OSE, VxWorks, etc.

IPNET

IPNET is a full-featured dual-mode

IPv4/v6 router stack with built-in

IPSec, Virtual Routing, QoS, VLAN

Tagging, as well as PowerQUICC

II/III optimizations. Available for leading RTOSs like INTEGRITY,

Linux, OSE, VxWorks, etc.

ARC

AVNISOFT

BLUNK

CMX

-

-

-

-

-

-

-

-

-

-

-

-

INTERPEAK

- - -

INTERPEAK

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-

-

-

-

-

-

MPC8275 Product Summary Page

PN713-1

INFOLINK-STACKNAME

MOC_SSL_CLIENT

PSQ40XXXX

KwikNet

The KwikNet TCP/IP Stack enables you to add networking features to your products with a minimum of time and expense. KwikNet is a compact, high performance stack built with

KADAK's characteristic simplicity, flexibility and reliability.

INFOLink Protocol Software Family

Mocana Embedded SSL/TLS Client

MOCANA SSL/TLS CLIENT:

Supports Freescale chipsets out of the box. Small (50KB), fast (2-3x faster than OpenSSL), trusted. Supports all major cryptos. Royalty free, source code license. FREE EVAL: http://www.mocana.com/evaluate.html

RTXC Quadnet Networking Protocols

Full protocol suite: TCP, UDP, SLIP,

ICMP, and ARP with Berkeley

Sockets API. Plus DHCP, BOOTP,

DNS, IGMP v2, RIP v2, NAT, HTTP,

SMTP, POP3, TFTP, FTP, Telnet,

SNMP v1,2,3, PPP and more. New security protocols: SSL, IPsec, IKE.

KADAK

LINK

MOCANA

-

-

-

-

-

-

-

-

-

QUADROS

- - -

-

-

-

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MPC8275 Product Summary Page

Software Tools

Code Translation

ID

PA68K-PPC

PA86-PPC

Name

PortAsm/68K for PowerPC

PortAsm/86 for PowerPC

Vendor ID

MICROAPL

MICROAPL

Format

-

-

Size

K

Rev #

- -

- -

Order

Availability

-

-

Compilers

ID Name Vendor ID Format

Size

K

Rev

#

Order

Availability

CWEPPC

CWLINPPC

CodeWarrior Development Studio for

PowerPC" Processors

CodeWarrior Development Studio. Linux

Application Edition for PowerPC

METROWERKS

METROWERKS

-

-

-

-

-

-

CWS-PPC-LLPLT-CX

CodeWarrior Development Studio, PowerPC

ISA - Linux

GNUTOOL

Gnu Tool set

ARC-MOT-COMPILER

MetaWare C/C++ Compiler Tool Suite

Optimized compiler for Motorola processors

COMPILER

C/C++ Compiler

Optimizing C, C++, EC++ compilers for

Freescale PowerPC, ColdFire, StarCore, 68K and ARM-based MAC architectures.

DIAB

Diab C/C++ Compiler

METROWERKS

- - -

ANAMIC

ARC

GREENHILLS

WINDRIV

-

-

-

-

-

-

-

-

-

-

-

- -

-

-

-

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MPC8275 Product Summary Page

Debuggers

ID

CWNETROM540A

Name Vendor ID Format

Size

K

Rev

#

Order

Availability

Metrowerks NetROM

A Flexible Platform for Accelerated Embedded

Development: NetROM is a revolutionary product for embedded software developers. It provides a flexible debugging platform that combines high-speed target communication and debugging capabilties

METROWERKS

- - - -

WireTAP Run Control for the PowerPC

Microprocessor

Feature-packed, no nonsense run control tool that

HW-WIRETAPCOP allows developers to save precious development time during target bring-up and debug. Providing visibility and control of on-chip debug (OCD) features of PowerPC microprocessors.

POWERPC

DEBUGGER

MULTI Debugger

METROWERKS

GREENHILLS

-

-

-

-

-

- -

-

LA-7729

TRACE32-ICD

TRACE32-ICD for PowerQUICC II is a high performance JTAG debugger for C ,C++ and

JAVA. A USB 2.x, LPT or ethernet interface is available for connection to any PC or workstation.

A flash programming utility is included.

LAUBACH

- - - -

Emulation

ID Name Vendor ID Format

Size

K

Rev

#

Order

Availability

MWCTST4SWICCORE

CodeTEST Analysis Tools, Software

In-Circuit

CodeTEST Software In-Circuit (SWIC) is the ideal solution for integrating your application software with your target hardware.

METROWERKS

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MPC8275 Product Summary Page

IDE (Integrated Development Environment)

ID

CE-PPCQNX21

Name Vendor ID Format

Size

K

Rev

#

Order

Availability

CodeWarrior for QNX RTOS

Provides a complete toolchain for creating, compiling, linking, and debugging your projects within a single environment. It also offers an application level debugger with multiple process and thread awareness support.

METROWERKS

- - - -

CWPPC1BWPQ3

CodeWarrior for PowerQUICC III

CodeWarrior Development Studio, PowerQUICC III

Edition support the whole development process from board bring-up through application development.

METROWERKS

- - -

MULTI

WIND RIVER

WORKBENCH

MULTI

MULTI is a complete integrated development environment for embedded applications using C,

C++, Embedded C++

Wind River Workbench

Wind River Workbench is an open, standards-based device software development environment for Linux applications providing a deep tools capability in each phase of the development process.

GREENHILLS

WINDRIV

-

-

-

-

-

-

WPIDE

WIND®POWER IDE

WINDRIV

- - - -

-

-

-

Initialization/Boot Code Generation

ID Name

MPC82XXCPMMUXIBCG

Parallel Ports Configuration Tool (Pin Mux

Tool)

(03/18/2004)

MPC82XXLBCUPMIBCG

UPM Tool for PowerQUICC II Processors

(12/11/2003)

Vendor ID Format

Size

K

Rev

#

Order

Availability

FREESCALE zip

985 4.0.0

-

FREESCALE zip

137 2.2.1

-

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MPC8275 Product Summary Page

Orderable Parts Information

Part Number

Package

Description

KMPC8275CVRMIBA

FPBGA 516

27*27*1.25P1.0

No

KMPC8275CZQMIBA

FPBGA 516

27*27*1.25P1.0

No

KMPC8275VRMIBA

KMPC8275ZQMIBA

MPC8275CVRMIBA

MPC8275CZQMIBA

MPC8275VRMIBA

MPC8275ZQMIBA

FPBGA 516

27*27*1.25P1.0

No

FPBGA 516

27*27*1.25P1.0

No

FPBGA 516

27*27*1.25P1.0

No

FPBGA 516

27*27*1.25P1.0

No

FPBGA 516

27*27*1.25P1.0

No

FPBGA 516

27*27*1.25P1.0

No

Tape and

Reel

Pb-Free

Terminations

Yes

No

Yes

No

Yes

No

Yes

No

Application/

Qualification

Tier

Status

Budgetary

Price

QTY

1000+

($US)

Info

COMMERCIAL,

INDUSTRIAL

Available

COMMERCIAL,

INDUSTRIAL

Available

COMMERCIAL,

INDUSTRIAL

Available

COMMERCIAL,

INDUSTRIAL

Available

COMMERCIAL,

INDUSTRIAL

Available

COMMERCIAL,

INDUSTRIAL

Available

COMMERCIAL,

INDUSTRIAL

Available

COMMERCIAL,

INDUSTRIAL

Available -

-

-

-

-

-

-

more more more more more more more more

NOTE:

Cannot find a Sample? Request a sample . Refer to Samples FAQ for more information.

Looking for an obsolete part? Check our distributors' inventory

Return to Top

Order

-

-

-

-

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MPC8275 Product Summary Page

MC33702 : MICROPROCESSOR POWER SUPPLY (3.0 A)

The 33702 is a monolithic IC providing an efficient means of obtaining power for the Freescale Semiconductor

PowerQUICC TM I and II ...

MPC9850 : Clock Generator for PowerPC and PowerQUICC Applications

The MPC9850 is a PLL based clock generator specifically designed for Freescale Microprocessor And Microcontroller applications including the PowerQUICC III. ...

MPC9855 : Clock Generator for PowerPC and PowerQUICC Applications

The MPC9855 is a PLL based clock generator specifically designed for Freescale Microprocessor and Microcontroller applications including the PowerPC and ...

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Related Links

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