Mitsubishi Electronics Sleep Apnea Machine 00UCPU User manual

Mitsubishi Electronics Sleep Apnea Machine 00UCPU User manual
QCPU User's Manual (Multiple CPU System)
-Q00CPU
-Q01CPU
-Q02(H)CPU
-Q06HCPU
-Q12HCPU
-Q25HCPU
-Q02PHCPU
-Q06PHCPU
-Q12PHCPU
-Q25PHCPU
-Q00UCPU
-Q01UCPU
-Q02UCPU
-Q03UDVCPU
-Q03UD(E)CPU
-Q04UDVCPU
-Q04UD(E)HCPU
-Q06UDVCPU
-Q06UD(E)HCPU
-Q10UD(E)HCPU
-Q13UDVCPU
-Q13UD(E)HCPU
-Q20UD(E)HCPU
-Q26UDVCPU
-Q26UD(E)HCPU
-Q50UDEHCPU
-Q100UDEHCPU
SAFETY PRECAUTIONS
(Read these precautions before using this product.)
Before using this product, please read this manual and the relevant manuals carefully and pay full attention
to safety to handle the product correctly.
In this manual, the safety precautions are classified into two levels: "
WARNING" and "
CAUTION".
WARNING
Indicates that incorrect handling may cause hazardous conditions,
resulting in death or severe injury.
CAUTION
Indicates that incorrect handling may cause hazardous conditions,
resulting in minor or moderate injury or property damage.
Under some circumstances, failure to observe the precautions given under "
CAUTION" may lead to
serious consequences.
Observe the precautions of both levels because they are important for personal and system safety.
Make sure that the end users read this manual and then keep the manual in a safe place for future
reference.
[Design Precautions]
WARNING
● Configure safety circuits external to the programmable controller to ensure that the entire system
operates safely even when a fault occurs in the external power supply or the programmable controller.
Failure to do so may result in an accident due to an incorrect output or malfunction.
(1) Configure external safety circuits, such as an emergency stop circuit, protection circuit, and
protective interlock circuit for forward/reverse operation or upper/lower limit positioning.
(2) The programmable controller stops its operation upon detection of the following status, and the
output status of the system will be as shown below.
Overcurrent or overvoltage protection of
the power supply module is activated.
Q series module
AnS/A series module
All outputs are turned off
All outputs are turned off
All outputs are held or turned off
The CPU module detects an error such as a
watchdog timer error by the self-diagnostic function. according to the parameter setting.
All outputs are turned off
All outputs may turn on when an error occurs in the part, such as I/O control part, where the
programmable controller CPU cannot detect any error. To ensure safety operation in such a case,
provide a safety mechanism or a fail-safe circuit external to the programmable controller. For a
fail-safe circuit example, refer to the QCPU User's Manual (Hardware Design, Maintenance and
Inspection).
(3) Outputs may remain on or off due to a failure of an output module relay or transistor. Configure an
external circuit for monitoring output signals that could cause a serious accident.
1
[Design Precautions]
WARNING
● In an output module, when a load current exceeding the rated current or an overcurrent caused by a
load short-circuit flows for a long time, it may cause smoke and fire. To prevent this, configure an
external safety circuit, such as a fuse.
● Configure a circuit so that the programmable controller is turned on first and then the external power
supply. If the external power supply is turned on first, an accident may occur due to an incorrect output
or malfunction.
● For the operating status of each station after a communication failure, refer to manuals relevant to the
network. Incorrect output or malfunction due to a communication failure may result in an accident.
● When connecting a peripheral with the CPU module or connecting an external device, such as a
personal computer, with an intelligent function module to modify data of a running programmable
controller, configure an interlock circuit in the program to ensure that the entire system will always
operate safely. For other forms of control (such as program modification or operating status change)
of a running programmable controller, read the relevant manuals carefully and ensure that the
operation is safe before proceeding. Especially, when a remote programmable controller is controlled
by an external device, immediate action cannot be taken if a problem occurs in the programmable
controller due to a communication failure. To prevent this, configure an interlock circuit in the
sequence program, and determine corrective actions to be taken between the external device and
CPU module in case of a communication failure.
[Design Precautions]
CAUTION
● Do not install the control lines or communication cables together with the main circuit lines or power
cables. Keep a distance of 100mm (3.94 inches) or more between them. Failure to do so may result in
malfunction due to noise.
● When a device such as a lamp, heater, or solenoid valve is controlled through an output module, a
large current (approximately ten times greater than normal) may flow when the output is turned from
off to on. Take measures such as replacing the module with one having a sufficient current rating.
● After the CPU module is powered on or is reset, the time taken to enter the RUN status varies
depending on the system configuration, parameter settings, and/or program size. Design circuits so
that the entire system will always operate safely, regardless of the time.
2
[Installation Precautions]
CAUTION
● Use the programmable controller in an environment that meets the general specifications in the
QCPU User's Manual (Hardware Design, Maintenance and Inspection). Failure to do so may result in
electric shock, fire, malfunction, or damage to or deterioration of the product.
● To mount the module, while pressing the module mounting lever located in the lower part of the
module, fully insert the module fixing projection(s) into the hole(s) in the base unit and press the
module until it snaps into place. Incorrect mounting may cause malfunction, failure or drop of the
module. When using the programmable controller in an environment of frequent vibrations, fix the
module with a screw. Tighten the screw within the specified torque range. Undertightening can cause
drop of the screw, short circuit, or malfunction. Overtightening can damage the screw and/or module,
resulting in drop, short circuit, or malfunction.
● When using an extension cable, connect it to the extension cable connector of the base unit securely.
Check the connection for looseness. Poor contact may cause incorrect input or output.
● When using a memory card, fully insert it into the memory card slot. Check that it is inserted
completely. Poor contact may cause malfunction.
● When using an SD memory card, fully insert it into the SD memory card slot. Check that it is inserted
completely. Poor contact may cause malfunction.
● Securely insert an extended SRAM cassette into the cassette connector of a CPU module. After
insertion, close the cassette cover to prevent the cassette from coming off. Poor contact may cause
malfunction.
● Shut off the external power supply (all phases) used in the system before mounting or removing the
module. Failure to do so may result in damage to the product. A module can be replaced online (while
power is on) on any MELSECNET/H remote I/O station or in the system where a CPU module
supporting the online module change function is used. Note that there are restrictions on the modules
that can be replaced online, and each module has its predetermined replacement procedure. For
details, refer to the relevant sections in the QCPU User's Manual (Hardware Design, Maintenance
and Inspection) and in the manual for the corresponding module.
● Do not directly touch any conductive parts and electronic components of the module, memory card,
SD memory card, or extended SRAM cassette. Doing so can cause malfunction or failure of the
module.
● When using a Motion CPU module and modules designed for motion control, check that the
combinations of these modules are correct before applying power. The modules may be damaged if
the combination is incorrect. For details, refer to the user's manual for the Motion CPU module.
[Wiring Precautions]
WARNING
● Shut off the external power supply (all phases) used in the system before wiring. Failure to do so may
result in electric shock or damage to the product.
● After installation and wiring, attach the included terminal cover to the module before turning it on for
operation. Failure to do so may result in electric shock.
3
[Wiring Precautions]
CAUTION
● Individually ground the FG and LG terminals of the programmable controller with a ground resistance
of 100 or less. Failure to do so may result in electric shock or malfunction.
● Use applicable solderless terminals and tighten them within the specified torque range. If any spade
solderless terminal is used, it may be disconnected when the terminal screw comes loose, resulting in
failure.
● Check the rated voltage and terminal layout before wiring to the module, and connect the cables
correctly. Connecting a power supply with a different voltage rating or incorrect wiring may cause a fire
or failure.
● Connectors for external devices must be crimped or pressed with the tool specified by the
manufacturer, or must be correctly soldered. Incomplete connections may cause short circuit, fire, or
malfunction.
● Securely connect the connector to the module. Poor contact may cause malfunction.
● Do not install the control lines or communication cables together with the main circuit lines or power
cables. Keep a distance of 100mm (3.94 inches) or more between them. Failure to do so may result in
malfunction due to noise.
● Place the cables in a duct or clamp them. If not, dangling cable may swing or inadvertently be pulled,
resulting in damage to the module or cables or malfunction due to poor connection.
● Check the interface type and correctly connect the cable. Incorrect wiring (connecting the cable to an
incorrect interface) may cause failure of the module and external device.
● Tighten the terminal screws within the specified torque range. Undertightening can cause short circuit,
fire, or malfunction. Overtightening can damage the screw and/or module, resulting in drop, short
circuit, or malfunction.
● Prevent foreign matter such as dust or wire chips from entering the module. Such foreign matter can
cause a fire, failure, or malfunction.
● A protective film is attached to the top of the module to prevent foreign matter, such as wire chips,
from entering the module during wiring. Do not remove the film during wiring. Remove it for heat
dissipation before system operation.
● When disconnecting the cable from the module, do not pull the cable by the cable part. For the cable
with connector, hold the connector part of the cable. For the cable connected to the terminal block,
loosen the terminal screw. Pulling the cable connected to the module may result in malfunction or
damage to the module or cable.
● Mitsubishi programmable controllers must be installed in control panels. Connect the main power
supply to the power supply module in the control panel through a relay terminal block. Wiring and
replacement of a power supply module must be performed by qualified maintenance personnel with
knowledge of protection against electric shock. For wiring methods, refer to the QCPU User's Manual
(Hardware Design, Maintenance and Inspection).
4
[Startup and Maintenance Precautions]
WARNING
● Do not touch any terminal while power is on. Doing so will cause electric shock or malfunction.
● Correctly connect the battery connector. Do not charge, disassemble, heat, short-circuit, solder, or
throw the battery into the fire. Also, do not expose it to liquid or strong shock. Doing so will cause the
battery to produce heat, explode, ignite, or leak, resulting in injury and fire.
● Shut off the external power supply (all phases) used in the system before cleaning the module or
retightening the terminal screws, connector screws, or module fixing screws. Failure to do so may
result in electric shock or cause the module to fail or malfunction.
[Startup and Maintenance Precautions]
CAUTION
● Before performing online operations (especially, program modification, forced output, and operating
status change) for the running CPU module from the peripheral device connected, read relevant
manuals carefully and ensure the safety. Improper operation may damage machines or cause
accidents.
● Do not disassemble or modify the modules. Doing so may cause failure, malfunction, injury, or a fire.
● Use any radio communication device such as a cellular phone or PHS (Personal Handy-phone
System) more than 25cm (9.85 inches) away in all directions from the programmable controller.
Failure to do so may cause malfunction.
● Shut off the external power supply (all phases) used in the system before mounting or removing the
module. Failure to do so may cause the module to fail or malfunction. A module can be replaced
online (while power is on) on any MELSECNET/H remote I/O station or in the system where a CPU
module supporting the online module change function is used. Note that there are restrictions on the
modules that can be replaced online, and each module has its predetermined replacement procedure.
For details, refer to the relevant sections in the QCPU User's Manual (Hardware Design, Maintenance
and Inspection) and in the manual for the corresponding module.
● After the first use of the product, do not mount/remove the module to/from the base unit, and the
terminal block to/from the module, and do not insert/remove the extended SRAM cassette to/from the
CPU module more than 50 times (IEC 61131-2 compliant) respectively. Exceeding the limit of 50 times
may cause malfunction.
● After the first use of the product, do not insert/remove the SD memory card to/from the CPU module
more than 500 times. Exceeding the limit may cause malfunction.
● Do not drop or apply shock to the battery to be installed in the module. Doing so may damage the
battery, causing the battery fluid to leak inside the battery. If the battery is dropped or any shock is
applied to it, dispose of it without using.
● Before handling the module, touch a grounded metal object to discharge the static electricity from the
human body. Failure to do so may cause the module to fail or malfunction.
5
[Disposal Precautions]
CAUTION
● When disposing of this product, treat it as industrial waste. When disposing of batteries, separate
them from other wastes according to the local regulations. (For the Battery Directive in EU member
states, refer to the QCPU User's Manual (Hardware Design, Maintenance and Inspection).)
[Transportation Precautions]
CAUTION
● When transporting lithium batteries, follow the transportation regulations. (For details of the regulated
models, refer to the QCPU User's Manual (Hardware Design, Maintenance and Inspection).)
6
CONDITIONS OF USE FOR THE PRODUCT
(1) Mitsubishi programmable controller ("the PRODUCT") shall be used in conditions;
i) where any problem, fault or failure occurring in the PRODUCT, if any, shall not lead to any major
or serious accident; and
ii) where the backup and fail-safe function are systematically or automatically provided outside of
the PRODUCT for the case of any problem, fault or failure occurring in the PRODUCT.
(2) The PRODUCT has been designed and manufactured for the purpose of being used in general
industries.
MITSUBISHI SHALL HAVE NO RESPONSIBILITY OR LIABILITY (INCLUDING, BUT NOT
LIMITED TO ANY AND ALL RESPONSIBILITY OR LIABILITY BASED ON CONTRACT,
WARRANTY, TORT, PRODUCT LIABILITY) FOR ANY INJURY OR DEATH TO PERSONS OR
LOSS OR DAMAGE TO PROPERTY CAUSED BY the PRODUCT THAT ARE OPERATED OR
USED IN APPLICATION NOT INTENDED OR EXCLUDED BY INSTRUCTIONS, PRECAUTIONS,
OR WARNING CONTAINED IN MITSUBISHI'S USER, INSTRUCTION AND/OR SAFETY
MANUALS, TECHNICAL BULLETINS AND GUIDELINES FOR the PRODUCT.
("Prohibited Application")
Prohibited Applications include, but not limited to, the use of the PRODUCT in;
• Nuclear Power Plants and any other power plants operated by Power companies, and/or any
other cases in which the public could be affected if any problem or fault occurs in the PRODUCT.
• Railway companies or Public service purposes, and/or any other cases in which establishment of
a special quality assurance system is required by the Purchaser or End User.
• Aircraft or Aerospace, Medical applications, Train equipment, transport equipment such as
Elevator and Escalator, Incineration and Fuel devices, Vehicles, Manned transportation,
Equipment for Recreation and Amusement, and Safety devices, handling of Nuclear or
Hazardous Materials or Chemicals, Mining and Drilling, and/or other applications where there is a
significant risk of injury to the public or property.
Notwithstanding the above, restrictions Mitsubishi may in its sole discretion, authorize use of the
PRODUCT in one or more of the Prohibited Applications, provided that the usage of the PRODUCT
is limited only for the specific applications agreed to by Mitsubishi and provided further that no
special quality assurance or fail-safe, redundant or other safety features which exceed the general
specifications of the PRODUCTs are required. For details, please contact the Mitsubishi
representative in your region.
7
INTRODUCTION
This manual describes the system configurations, functions, and communication methods with external devices
required in a multiple CPU system.
Before using this product, please read this manual and the relevant manuals carefully and develop familiarity with the
functions and performance of the Q series programmable controller to handle the product correctly.
When applying the program examples introduced in this manual to the actual system, ensure the applicability and
confirm that it will not cause system control problems.
Relevant CPU modules:
CPU module
Model
Basic model QCPU
Q00CPU, Q01CPU
High Performance model QCPU
Q02(H)CPU, Q06HCPU, Q12HCPU, Q25HCPU
Process CPU
Q02PHCPU, Q06PHCPU, Q12PHCPU, Q25PHCPU
Q00UCPU, Q01UCPU, Q02UCPU, Q03UD(E)CPU, Q03UDVCPU,
Universal model QCPU
Q04UD(E)HCPU, Q04UDVCPU, Q06UD(E)HCPU, Q06UDVCPU,
Q10UD(E)HCPU, Q13UD(E)HCPU, Q13UDVCPU, Q20UD(E)HCPU,
Q26UD(E)HCPU, Q26UDVCPU, Q50UDEHCPU, Q100UDEHCPU
Remark
● This manual does not describe the specifications and precautions of the power supply modules, base units, extension
cables, memory cards, SD memory cards, extended SRAM cassettes, and batteries as well as the peripheral
configurations.
QCPU User's Manual (Hardware Design, Maintenance and Inspection)
● For the functions of CPU modules when used in a system other than a multiple CPU system, refer to the following.
User's Manual (Function Explanation, Program Fundamentals) for the CPU module used
8
Memo
9
CONTENTS
CONTENTS
SAFETY PRECAUTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
CONDITIONS OF USE FOR THE PRODUCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
MANUALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MANUAL PAGE ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
TERMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CHAPTER 1 OVERVIEW
18
CHAPTER 2 CONCEPT OF MULTIPLE CPU SYSTEM
24
2.1
CPU Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2
I/O Number Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2.1
I/O numbers of I/O modules and intelligent function modules . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2.2
I/O numbers of CPU modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
CHAPTER 3 SYSTEM CONFIGURATION
3.1
3.2
3.3
31
System Using Basic Model QCPU as CPU No.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1.1
Available CPU modules, base units, power supply modules, and extension cables . . . . . . . 32
3.1.2
CPU module combinations and mounting positions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.1.3
Available I/O modules and intelligent function modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
System Using High Performance Model QCPU or Process CPU as CPU No.1. . . . . . . . . . . . 41
3.2.1
Available CPU modules, base units, power supply modules, and extension cables . . . . . . . 41
3.2.2
CPU module combinations and mounting positions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.2.3
Available I/O modules and intelligent function modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
System Using Universal Model QCPU as CPU No.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.3.1
Available CPU modules, base units, power supply modules, and extension cables . . . . . . . 53
3.3.2
CPU module combinations and mounting positions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.3.3
Available I/O modules and intelligent function modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.4
Applicable Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.5
Precautions for System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM
75
4.1
Procedure Before Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.2
Operation Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.3
4.2.1
System configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.2.2
Parameter settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Program Examples for Communications by Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.3.1
Program examples for Basic model QCPU, High Performance model QCPU, and Process
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.3.2
4.4
10
Program examples for Universal model QCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Clock Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.4.1
Clock data of CPU modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.4.2
Clock data of intelligent function modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.5
Resetting a Multiple CPU System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.6
System Operation When a Stop Error Occurs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
CHAPTER 5 ACCESS BETWEEN CPU MODULES AND OTHER MODULES
104
5.1
Access to Controlled Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.2
Access to Non-controlled Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.2.1
Loading input (X) data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.2.2
Loading output (Y) data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.2.3
Output to output modules and intelligent function modules . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.2.4
Access to the intelligent function module buffer memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.2.5
Access using the link direct device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.3
Access From a Programming Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.4
Accessible QCPUs when GOT is connected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
6.1
116
Communications Using the CPU Shared Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.1.1
Communications by auto refresh (using the auto refresh area) . . . . . . . . . . . . . . . . . . . . . . 122
6.1.2
Communications by auto refresh (using the multiple CPU high speed transmission area)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6.2
6.3
6.1.3
Communications by programs using the CPU shared memory . . . . . . . . . . . . . . . . . . . . . . 150
6.1.4
Communications among CPU modules when an error is detected . . . . . . . . . . . . . . . . . . . 159
Control Directions from QCPU to Motion CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Communications Among CPU Modules By Dedicated Instructions . . . . . . . . . . . . . . . . . . . . 162
6.3.1
Reading/writing device data from/to Motion CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
6.3.2
Starting interrupt programs from QCPU to C Controller module/PC CPU module. . . . . . . . 164
6.3.3
Reading/writing device data between QCPUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
6.4
Multiple CPU Synchronous Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
6.5
Multiple CPU synchronous startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
APPENDICES
170
Appendix 1 Parameters for a Multiple CPU System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Appendix 1.1
List of parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Appendix 2 Comparison with a Single CPU System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Appendix 3 Precautions for Using AnS/A Series Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Appendix 4 Processing Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
INDEX
Appendix 4.1
Concept of scan time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Appendix 4.2
Factors that increase scan time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Appendix 4.3
Reducing processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
201
REVISIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
WARRANTY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
11
MANUALS
To understand the main specifications, functions, and usage of the CPU module, refer to the basic manuals. Read
other manuals as well when using a different type of CPU module and its functions. Order each manual as needed,
referring to the following lists.
The numbers in the "CPU module" and the respective modules are as follows.
Number
CPU module
Number
CPU module
1)
Basic model QCPU
3)
Process CPU
2)
High Performance model QCPU
4)
Universal model QCPU
●: Basic manual,
: Other CPU module manuals/Use them to utilize functions.
(1) CPU module user's manual
Manual name
Description
<manual number (model code)>
QCPU User's Manual (Hardware Design,
Specifications of the hardware (CPU modules, power
Maintenance and Inspection)
supply modules, base units, extension cables, memory
cards, SD memory cards, and extended SRAM
CPU module
1)
2)
3)
4)
●
●
●
●
cassettes), system maintenance and inspection,
<SH-080483ENG (13JR73)>
troubleshooting, and error codes
QnUCPU User's Manual (Function Explanation,
Program Fundamentals)
●
Functions, methods, and devices for programming
<SH-080807ENG (13JZ27)>
Qn(H)/QnPH/QnPRHCPU User's Manual
(Function Explanation, Program Fundamentals)
Functions, methods, and devices for programming
<SH-080808ENG (13JZ28)>
QnUCPU User's Manual (Communication via
Built-in Ethernet Port)
<SH-080811ENG (13JZ29)>
QnUDVCPU/LCPU User's Manual (Data
Logging Function)
<SH-080893ENG (13JZ39)>
12
Detailed description of communication via the built-in
Ethernet ports of the CPU module
Detailed description of the data logging function of the
CPU module
●
●
●
(2) Programming manual
Manual name
Description
<manual number (model code)>
MELSEC-Q/L Programming Manual (Common
Instruction)
<SH-080809ENG (13JW10)>
Detailed description and usage of instructions used in
programs
MELSEC-Q/L/QnA Programming Manual
System configuration, specifications, functions,
(SFC)
programming, and error codes for SFC (MELSAP3)
<SH-080041 (13JF60)>
System configuration, specifications, functions,
L)
programming, and error codes for SFC (MELSAP-L)
MELSEC-Q/L Programming Manual (Structured
Text)
<SH-080366E (13JF68)>
1)
2)
3)
4)
●
●
●
●
programs
MELSEC-Q/L Programming Manual (MELSAP<SH-080076 (13JF61)>
CPU module
programs
System configuration and programming using structured
text language
MELSEC-Q/L/QnA Programming Manual (PID
Control Instructions)
Dedicated instructions for PID control
<SH-080040 (13JF59)>
MELSEC-Q Programming/Structured
Programming Manual (Process Control
Instructions)
Dedicated instructions for process control
<SH-080316E (13JF67)>
(3) Operating manual
Manual name
<manual number (model code)>
Description
GX Works2 Version 1 Operating Manual
System configuration, parameter settings, and online
(Common)
operations (common to Simple project and Structured
<SH-080779ENG (13JU63)>
GX Developer Version 8 Operating Manual
<SH-080373E (13JU41)>
CPU module
1)
2)
3)
4)
●
●
●
●
project) of GX Works2
Operating methods of GX Developer, such as
programming, printing, monitoring, and debugging
13
MANUAL PAGE ORGANIZATION
In this manual, pages are organized and the symbols are used as shown below.
The following page illustration is for explanation purpose only, and is different from the actual pages.
"" is used for window
names and items.
The chapter of
the current page is shown.
shows operating
procedures.
shows mouse
operations.*1
[ ] is used for items
in the menu bar and
the project window.
The section of
the current page is shown.
Ex. shows setting or
operating examples.
shows reference
manuals.
shows notes that
requires attention.
shows
reference pages.
shows useful
information.
*1
The mouse operation example is provided below. (For GX Works2)
Menu bar
Ex.
[Online]
[Write to PLC...]
Select [Online] on the menu bar,
and then select [Write to PLC...].
A window selected in the view selection area is displayed.
Ex.
[Parameter]
Project window
[PLC Parameter]
Select [Project] from the view selection
area to open the Project window.
In the Project window, expand [Parameter] and
select [PLC Parameter].
View selection area
14
TERMS
Unless otherwise specified, this manual uses the following generic terms and abbreviations.
*
 indicates a part of the model or version.
Ex. Q33B, Q35B, Q38B, Q312BQ3B
Term

Q series
AnS series
A series

Description
Series
The abbreviation for Mitsubishi MELSEC-Q series programmable controller
The abbreviation for compact types of Mitsubishi MELSEC-A series programmable
controller
The abbreviation for large types of Mitsubishi MELSEC-A series programmable controller
CPU module type
A generic term for the Basic model QCPU, High Performance model QCPU, Process
CPU module
CPU, Universal model QCPU, Motion CPU, C Controller module, and PC CPU module.
The term in this manual does not include the Redundant CPU because it cannot be used
in a multiple CPU system.
A generic term for the Basic model QCPU, High Performance model QCPU, Process
QCPU
CPU, and Universal model QCPU.
The term in this manual does not include the Redundant CPU because it cannot be used
in a multiple CPU system.
A generic term for the Q00CPU and Q01CPU.
Basic model QCPU
The term in this manual does not include the Q00JCPU because it cannot be used in a
High Performance model QCPU
A generic term for the Q02CPU, Q02HCPU, Q06HCPU, Q12HCPU, and Q25HCPU
Process CPU
A generic term for the Q02PHCPU, Q06PHCPU, Q12PHCPU, and Q25PHCPU
multiple CPU system.
A generic term for the Q00UCPU, Q01UCPU, Q02UCPU, Q03UDCPU, Q03UDVCPU,
Q03UDECPU, Q04UDHCPU, Q04UDVCPU, Q04UDEHCPU, Q06UDHCPU,
Q06UDVCPU, Q06UDEHCPU, Q10UDHCPU, Q10UDEHCPU, Q13UDHCPU,
Universal model QCPU
Q13UDVCPU, Q13UDEHCPU, Q20UDHCPU, Q20UDEHCPU, Q26UDHCPU,
Q26UDVCPU, Q26UDEHCPU, Q50UDEHCPU, and Q100UDEHCPU.
The term in this manual does not include the Q00UJCPU because it cannot be used in a
multiple CPU system.
A generic term for the Q03UDVCPU, Q03UDECPU, Q04UDVCPU, Q04UDEHCPU,
Built-in Ethernet port QCPU
Q06UDVCPU, Q06UDEHCPU, Q10UDEHCPU, Q13UDVCPU, Q13UDEHCPU,
Q20UDEHCPU, Q26UDVCPU, Q26UDEHCPU, Q50UDEHCPU, and Q100UDEHCPU
High-speed Universal model QCPU
A generic term for the Q03UDVCPU, Q04UDVCPU, Q06UDVCPU, Q13UDVCPU, and
Q26UDVCPU
A generic term for the Mitsubishi motion controllers: Q172CPUN, Q173CPUN,
Motion CPU
Q172HCPU, Q173HCPU, Q172CPUN-T, Q173CPUN-T, Q172HCPU-T, Q173HCPU-T,
Q172DCPU, Q173DCPU, Q172DCPU-S1, Q173DCPU-S1, Q172DSCPU, and
Q173DSCPU
A generic term for the MELSEC-Q series-compatible PC CPU modules manufactured by
PC CPU module
CONTEC Co., Ltd: PPC-CPU686(MS)-64, PPC-CPU686(MS)-128, and PPCCPU852(MS)-512
C Controller module

A generic term for the C Controller modules: Q06CCPU-V, Q06CCPU-V-B, Q12DCCPUV, Q24DHCCPU-V, and Q24DHCCPU-LS
CPU module model
A generic term for the Q00UCPU, Q01UCPU, Q02UCPU, Q03UDCPU, Q04UDHCPU,
QnU(D)(H)CPU
Q06UDHCPU, Q10UDHCPU, Q13UDHCPU, Q20UDHCPU, and Q26UDHCPU.
The term in this manual does not include the Q00UJCPU because it cannot be used in a
multiple CPU system.
15
Term
QnUDVCPU
QnUDE(H)CPU

Description
A generic term for the Q03UDVCPU, Q04UDVCPU, Q06UDVCPU, Q13UDVCPU, and
Q26UDVCPU
A generic term for the Q03UDECPU, Q04UDEHCPU, Q06UDEHCPU, Q10UDEHCPU,
Q13UDEHCPU, Q20UDEHCPU, Q26UDEHCPU, Q50UDEHCPU, and Q100UDEHCPU
Q172CPUN(-T)
A generic term for the Q172CPUN and Q172CPUN-T
Q173CPUN(-T)
A generic term for the Q173CPUN and Q173CPUN-T
Q172HCPU(-T)
A generic term for the Q172HCPU and Q172HCPU-T
Q173HCPU(-T)
A generic term for the Q173HCPU and Q173HCPU-T
Q172DCPU(-S1)
A generic term for the Q172DCPU and Q172DCPU-S1
Q173DCPU(-S1)
A generic term for the Q173DCPU and Q173DCPU-S1
Base unit type
A generic term for the main base unit, extension base unit, slim type main base unit,
redundant power main base unit, redundant power extension base unit, and multiple
Base unit
CPU high speed main base unit.
The term in this manual does not include the redundant type extension base unit
because it cannot be used in a multiple CPU system.
Main base unit
A generic term for the Q3B, Q3SB, Q3RB, and Q3DB
A generic term for the Q5B, Q6B, Q6RB, QA1S5B, QA1S6B,
Extension base unit
QA1S6ADP+A1S5B/A1S6B, QA6B, and QA6ADP+A5B/A6B.
The term in this manual does not include the Q6WRB because it cannot be used in a
multiple CPU system.
Slim type main base unit
Another term for the Q3SB
Redundant power main base unit
Another term for the Q3RB
Redundant power extension base unit
Another term for the Q6RB
Multiple CPU high speed main base unit
Another term for the Q3DB
Redundant power supply base unit

base unit
Base unit model
Q3B
A generic term for the Q33B, Q35B, Q38B, and Q312B main base units
Q3SB
A generic term for the Q32SB, Q33SB, and Q35SB slim type main base units
Q3RB
Another term for the Q38RB redundant power main base unit
Q3DB

A generic term for the redundant power main base unit and redundant power extension
A generic term for the Q35DB, Q38DB, and Q312DB multiple CPU high speed main
base units
Q5B
A generic term for the Q52B and Q55B extension base units
Q6B
A generic term for the Q63B, Q65B, Q68B, and Q612B extension base units
Q6RB
Another term for the Q68RB redundant power extension base unit
QA1S5B
Another term for the QA1S51B extension base unit
QA1S6B
A generic term for the QA1S65B and QA1S68B extension base units
QA6B
A generic term for the QA65B and QA68B extension base units
A5B
A generic term for the A52B, A55B, and A58B extension base units
A6B
A generic term for the A62B, A65B, and A68B extension base units
QA6ADP+A5B/A6B
The abbreviation for A large type extension base unit where the QA6ADP is mounted
QA1S6ADP+A1S5B/A1S6B
The abbreviation for A small type extension base unit where the QA1S6ADP is mounted
Power supply module
A generic term for the Q series power supply module, AnS series power supply module,
Power supply module
A series power supply module, slim type power supply module, and redundant power
supply module
Q series power supply module
AnS series power supply module
16
A generic term for the Q61P-A1, Q61P-A2, Q61P, Q61P-D, Q62P, Q63P, Q64P, and
Q64PN power supply modules
A generic term for the A1S61PN, A1S62PN, and A1S63P power supply modules
Term
A series power supply module


The abbreviation for the Q61SP slim type power supply module
A generic term for the Q63RP and Q64RP redundant power supply modules
Life detection power supply module
The abbreviation for the Q61P-D life detection power supply module
Network module
A generic term for the CC-Link IE Controller Network module and CC-Link IE Field
Network module
MELSECNET/H module
The abbreviation for the MELSECNET/H network module
Ethernet module
The abbreviation for the Ethernet interface module
CC-Link module
The abbreviation for the CC-Link system master/local module
Network
CC-Link IE
A generic term for the CC-Link IE Controller Network and CC-Link IE Field Network
MELSECNET/H
The abbreviation for the MELSECNET/H network system
Memory extension
SRAM card
A generic term for SRAM card, Flash card, and ATA card
A generic term for the Q2MEM-1MBS, Q2MEM-2MBS, Q3MEM-4MBS, and Q3MEM8MBS SRAM cards
Flash card
A generic term for the Q2MEM-2MBF and Q2MEM-4MBF Flash cards
ATA card
A generic term for the Q2MEM-8MBA, Q2MEM-16MBA, and Q2MEM-32MBA ATA cards
SD memory card
Extended SRAM cassette
A generic term for the L1MEM-2GBSD and L1MEM-4GBSD SD Secure Digital memory
cards. An SD card is a non-volatile memory card.
A generic term for the Q4MCA-1MBS, Q4MCA-2MBS, Q4MCA-4MBS, and Q4MCA8MBS extended SRAM cassettes
Software package
Programming tool
GX Works2
GX Developer

supply modules
Redundant power supply module
Memory card

A generic term for the A61P, A61PN, A62P, A63P, A68P, A61PEU, and A62PEU power
Slim type power supply module
CC-Link IE module

Description
A generic term for GX Works2 and GX Developer
The product name for the MELSEC programmable controller software package
Others
A CPU module which controls each I/O module and intelligent function module.
Control CPU
In a multiple CPU system, the CPU module which executes the control can be set for
each module.
Controlled module
Non-controlled module
Extension cable
Battery
QA6ADP
QA1S6ADP
GOT
I/O modules and intelligent function modules which are controlled by a control CPU
I/O modules and intelligent function modules that are controlled by CPU modules other
than a control CPU
A generic term for the QC05B, QC06B, QC12B, QC30B, QC50B, and QC100B
extension cables
A generic term for the Q6BAT, Q7BAT, and Q8BAT CPU module batteries, Q2MEM-BAT
SRAM card battery, and Q3MEM-BAT SRAM card battery
The abbreviation for the QA6ADP QA conversion adapter module
A generic term for the QA1S6ADP and QA1S6ADP-S1 Q-AnS base unit conversion
adapter
A generic term for Mitsubishi Graphic Operation Terminal, GOT-A*** series, GOT-F***
series, and GOT1000 series
17
CHAPTER 1
OVERVIEW
In a multiple CPU system, more than one CPU module is mounted on the main base unit and each CPU module
controls I/O modules and intelligent function modules separately.
QCPUs, Motion CPUs, C Controller modules, and PC CPU modules can be used in multiple CPU systems.
(
Page 31, CHAPTER 3)
Motion CPU
QCPU
PC CPU module
Remark
This manual describes the combinations of CPU modules and communications among CPU modules in a multiple CPU
system. For the uses, functions, and instruction availabilities of each CPU module, refer to the following.
Manual for the CPU module used
For PC CPU modules, contact CONTEC Co., Ltd.
http://www.contec.com/
(1) Distributed control
In a multiple CPU system, control can be distributed by specifying a control CPU module for each I/O module and
intelligent function module. (
Page 24, Section 2.1)
CPU
0
1
2
3
4
5
6
7
1
2
1
1
1
1
2
2
2
Slot number
Control CPU setting
Controlled by CPU No.1.
Controlled by CPU No.2.
Distributed control provides the advantages listed on the following page.
18
CHAPTER 1 OVERVIEW
(a) Distribution of processing
The overall system scan time can be reduced by distributing the high-load processing performed in a single
CPU module over multiple CPU modules.
Data processing (low speed)
Machine control (high speed)
A single QCPU controls an entire system.
(Processing speed:
1ms or less)
CPU module for
machine control
(Processing speed:
1 to several 10ms)
CPU module for
data processing
Machine control speed is further increased with
load distribution according to the control cycle.
(b) Distribution of memory
The memory capacity used for the entire system can be increased by distributing the memory areas over
multiple CPU modules.
Free
space
Used
memory
Free
space
Memory capacity can be expanded by
using more than one CPU module.
Used memory
Used
memory
Free
space
An additional CPU module can
expand the following:
Program memory
Device memory
(c) Distribution of functions
Programs can be developed easily by distributing the functions, for example, having different CPU modules
control production line A and production line B.
19
1
(2) Configuring sequence control and motion control systems on the same base
unit
In a multiple CPU system consisting of a QCPU and Motion CPU, sequence control and motion control can be
implemented together to achieve a high-level motion system.
Control
Sequence
control
Motion control
Operation switch
Operation status lamp
Servo
amplifier
SSCNET
Servo
motor
Servo
amplifier
Servo
motor
Interaction with Motion CPUs for motion control is enhanced in Universal model QCPUs.
(a) High-speed data transfer between CPU modules
In a multiple CPU system, up to 14K-word data are transferred in parallel with programs between CPU
modules. This enables high-speed data transfer independent of scan time, and shortens the takt time of the
entire system. (
Page 150, Section 6.1.3)
CPU No.1
CPU No.2
Program
Multiple CPU high
speed transmission
X0
0
Y20
Data transfer
Program
Multiple CPU high
speed transmission X100
0
Y120
Data transfer
Data transfer
END
END
Data are transferred in parallel with programs.
20
CHAPTER 1 OVERVIEW
(b) Synchronous processing with a motion control
1
An interrupt program which is synchronized with the operation cycle of a Motion CPU (multiple CPU
synchronous interrupt program) can be executed. Command input or output from a Motion CPU can be
synchronized with the operation cycle of the Motion CPU, which enables high-speed data transfer independent
of scan time. (
Page 166, Section 6.4)
Motion
CPU
Operation cycle
of a Motion CPU
Reading an
imposition signal
Motion SFC program
Multiple CPU high
speed transmission
area
Multiple CPU high
speed transmission
Universal
Multiple CPU high
model QCPU
speed transmission
area
END
0
END
0
Program
Multiple CPU
synchronous
interrupt program
I45 IRET
Multiple CPU
high speed
transmission cycle
I45 IRET
I45 IRET
I45 IRET
I45 IRET
I45 IRET
Reading an
imposition signal
Reading an imposition signal when
a multiple CPU synchronous
interrupt program is not used
21
(c) Checking data send/receive timing between CPU modules
With the sampling trace function of Universal model QCPUs, the data communications timing with a Motion
CPU can be checked. Timing can also be checked between Universal model QCPUs.
The sampling trace function facilitates the processing for checking the data send/receive timing between CPU
modules, and reduces the time for debugging the multiple CPU system.
Sampling trace result display using a programming tool
The sampling trace of other CPU modules in the multiple CPU system can be executed, by specifying the following CPU
modules.
• Universal model QCPU (except the Q00UCPU, Q01UCPU, and Q02UCPU)
• Motion CPU (Q172DCPU(-S1), Q173DCPU(-S1), Q172DSCPU, or Q173DSCPU)
22
CHAPTER 1 OVERVIEW
1
(3) Data communications among CPU modules
The following data communications can be performed among CPU modules in a multiple CPU system.
(a) Transferring data among CPU modules
Data can be transferred among CPU modules by setting auto refresh using a programming tool.
(
Page 122, Section 6.1.1 to Page 135, Section 6.1.2)
(b) Reading data from other CPU modules
Each CPU module can read data from other CPU modules whenever required using the following instructions.
(
Page 150, Section 6.1.3)
• Read instruction from the CPU shared memory in another CPU module
• Cyclic transmission area device (U3En\G)
(c) Directing control to the Motion CPU
The QCPU can direct control to the Motion CPU using the following instruction. (
Page 160, Section 6.2)
• Motion dedicated instruction
(d) Reading/writing device data to/from the Motion CPU
The QCPU can read/write device data to/from the Motion CPU using the following instructions.
(
Page 162, Section 6.3.1)
• Multiple CPU transmission dedicated instruction
• Multiple CPU high-speed transmission dedicated instruction
(e) Issuing events to the C Controller module or PC CPU module
The QCPU can issue events to the C Controller module or PC CPU module using the following instruction.
(
Page 164, Section 6.3.2)
• Multiple CPU transmission dedicated instruction
The Universal model QCPU (except the Q00UCPU, Q01UCPU, and Q02UCPU) can execute the motion
dedicated instruction multiple times in one scan. Since the motion dedicated instruction can be executed
consecutively to different axis numbers, delay time of servo startup intervals can be shortened.
(f) Logging communication data among CPU modules
Communication data among CPU modules can be saved to an SD memory card in CSV format by logging the
cyclic transmission area device (U3EnG) using the data logging function of the CPU module.
The high-speed Universal model QCPU supports the data logging function.
(
QnUDVCPU/LCPU User's Manual (Data Logging Function))
23
CHAPTER 2
CONCEPT OF MULTIPLE CPU
SYSTEM
2.1
CPU Numbers
CPU numbers are assigned to identify CPU modules contained in a multiple CPU system.
A CPU module mounted in the CPU slot of a main base unit will be CPU No.1. CPU No.2, No.3, and No.4 will be
assigned sequentially to the right of CPU No.1.
CPU slot: CPU No.1
Slot 0: CPU No.2
Slot 1: CPU No.3
Slot 2: CPU No.4
CPU
0
1
2
1
2
3
4
3
4
Slot number
CPU number
(1) Available CPU numbers
Available CPU numbers differ depending on the QCPU used as CPU No.1 and the main base unit used.
(
Page 31, CHAPTER 3)
Ex. When a Basic model QCPU is used as CPU No.1, the total number of mountable CPU modules is three
(CPU No.1 to No.3). However, when a slim type main base unit (Q3SB) or multiple CPU high-speed
main base unit (Q3DB) is used, the number of mountable CPU modules is limited to one or two (CPU
No.1 and No.2).
24
CHAPTER 2 CONCEPT OF MULTIPLE CPU SYSTEM
(2) Uses of CPU numbers
CPU numbers are used for the following purposes.
2
(a) Setting control CPUs
CPU numbers are used to set a control CPU for each I/O module and intelligent function module.
CPU
0
1
2
3
4
5
6
7
1
2
1
1
1
1
2
2
2
Slot number
Control CPU setting
Controlled by CPU No.1.
Controlled by CPU No.2.
Set control CPUs in PLC parameter ("I/O Assignment").
Project window
[Parameter]
[PLC Parameter]
[I/O Assignment]
Set control CPUs.
2.1 CPU Numbers
25
(b) Specifying a connection target using a programming tool (personal computer)
CPU numbers are used to specify a CPU module to which a programming tool is connected.
CPU
0
1
2
1
2
3
4
Slot number
CPU number
A programming tool
communicates with
CPU No.2.
Specify "PLC No.2".
(3) Checking the host CPU number
The host CPU number of a QCPU is stored in SD395 (Multiple CPU system information). A host CPU number
check program (refer to an example below) should be created. If created, the following status can be checked
easily.
• Incorrect mounting status of the QCPU
• Program writing status to other CPU modules using the programming tool
In the following program, if the QCPU to which the program is written is other than CPU No.1 (if the value in
SD395 is other than "1"), the annunciator (F1) turns on. Accordingly, the USER LED of the QCPU turns on.
The corresponding annunciator number is stored in SD62 (Annunciator number).
<>
K1
SD395
SET
Set the CPU number to be compared.
26
F1
CHAPTER 2 CONCEPT OF MULTIPLE CPU SYSTEM
2.2
I/O Number Assignment
A multiple CPU system uses the following two I/O numbers.
2
• I/O numbers used by CPU modules to communicate with I/O modules and intelligent function modules
(
Page 27, Section 2.2.1)
• I/O numbers used by CPU modules to communicate with other CPU modules (
2.2.1
Page 30, Section 2.2.2)
I/O numbers of I/O modules and intelligent function modules
In the same way as in single CPU systems, I/O number "00H" is assigned to the I/O module or intelligent function
module mounted to the right of the CPU module. The subsequent I/O numbers are assigned sequentially to the right.
In multiple CPU systems, however, CPU modules may be mounted in slots 0 to 2 as well, and accordingly the start slot
of "00H" varies.
Ex. When two CPU modules are mounted
CPU
0
1
2
3
4
5
6
7
Slot number
I/O number: 00H
2.2 I/O Number Assignment
2.2.1 I/O numbers of I/O modules and intelligent function modules
27
● Some CPU modules occupy two or more slots. When this type of CPU module is used, the second slot and after are
treated as empty slots.
In the case of a PC CPU module, for example, the right slot of the occupied two slots is treated as an empty slot having
16 points. (An empty slot occupies 16 points by default.)
For this reason, the start I/O number of the module mounted on the right of the PC CPU module will be "10H".
CPU
0
1
2
Number of
CPU modules: 3
Slot number
Empty slot:
00H to 0FH occupied
Note that the start I/O number can be changed to "00H" by setting "0 Point" to the number of points for the right slot of the
PC CPU module in PLC parameter ("I/O Assignment").
● The I/O numbers of the multiple CPU system can be checked on the System monitor window using a programming tool.
● In the same way as in single CPU systems, the position of I/O number "00H" can be changed to any slot in PLC
parameter ("I/O Assignment"). (
used)
28
User's Manual (Function Explanation, Program Fundamentals) for the CPU module
CHAPTER 2 CONCEPT OF MULTIPLE CPU SYSTEM
Ex. Example of I/O number assignment
Main base unit.........When 32-point modules are mounted in each slot
2
Q series power
supply module
7
8
9
10
11
E0 to FF
6
100 to 11F
5
C0 to DF
4
80 to 9F
3
A0 to BF
2
60 to 7F
1
40 to 5F
0
20 to 3F
CPU
00 to 1F
Q312B (12 slots occupied)
...... Slot number
...... I/O number
CPU No.4
CPU No.3
CPU No.2
CPU No.1
Extension base unit .........When 32-point modules are mounted in each slot
1E0 to 1FF
200 to 21F
220 to 23F
240 to 25F
260 to 27F
280 to 29F
1C0 to 1DF
600 to 61F
620 to 63F
58
59
60
720 to 73F
57
5E0 to 5FF
56
52
700 to 71F
520 to 53F
55
6E0 to 6FF
500 to 51F
5A0 to 5BF
4E0 to 4FF
4th
extension
5C0 to 5DF
44
51
6A0 to 6BF
420 to 43F
43
50
6C0 to 6DF
400 to 41F
42
49
Q68B (8 slots occupied)
53
54
Q65B (5 slots occupied)
61
62
5th
extension
6th
extension
7th
extension
63
Use prohibited
3E0 to 3FF
41
48
580 to 59F
3C0 to 3DF
40
360 to 37F
39
340 to 35F
38
Q68B (8 slots occupied)
3rd
extension
47
2.2 I/O Number Assignment
2.2.1 I/O numbers of I/O modules and intelligent function modules
37
4C0 to 4DF
36
3A0 to 3BF
35
4A0 to 4BF
34
380 to 39F
33
480 to 49F
32
460 to 47F
31
46
680 to 69F
320 to 33F
45
440 to 45F
30
1st
extension
Q68B (8 slots occupied)
2nd
extension
Q68B (8 slots occupied)
29
23
780 to 79F
300 to 31F
22
Use prohibited
2E0 to 2FF
21
560 to 57F
2A0 to 2BF
20
540 to 55F
28
19
660 to 67F
27
18
640 to 65F
26
17
760 to 77F
25
16
740 to 75F
24
2C0 to 2DF
Q55B (5 slots occupied)
15
180 to 19F
14
160 to 17F
13
140 to 15F
120 to 13F
12
1A0 to 1BF
Q612B (12 slots occupied)
If modules are
mounted, an error
occurs.
29
2.2.2
I/O numbers of CPU modules
In multiple CPU systems, I/O numbers are assigned to each CPU module to specify mounted CPU modules. The I/O
number for each CPU module is fixed at the corresponding slot, and cannot be changed in PLC parameter ("I/O
Assignment").
The following is the list of I/O numbers that can be assigned to CPU modules.
CPU module mounting position
Item
Start I/O number
CPU slot
Slot 0
Slot 1
Slot 2
3E00H
3E10H
3E20H
3E30H
Available slots differ depending on the QCPU used as CPU No.1 and the main base unit used. (
Page 31,
CHAPTER 3)
(1) Uses of I/O numbers of CPU modules
The I/O numbers of CPU modules are used for the following purposes.
• Communications among CPU modules (
Page 116, CHAPTER 6)
• Specifying the communication-target CPU module under the MC protocol (
Communication Protocol Reference Manual)
30
MELSEC-Q/L MELSEC
CHAPTER 3 SYSTEM CONFIGURATION
CHAPTER 3
SYSTEM CONFIGURATION
In a multiple CPU system, QCPUs, motion CPUs, C Controller modules, and PC CPU modules can be mounted in the
CPU slot to slot 2 of the main base unit.
I/O modules and intelligent function modules are mounted to the right of CPU modules.
3
This chapter describes the system configurations according to the QCPU used as CPU No.1.
Remark
● For a multiple CPU system using a C Controller module as CPU No.1, refer to the manual for the C Controller module
used.
● For PC CPU modules, contact CONTEC Co., Ltd.
http://www.contec.com/
31
3.1
System Using Basic Model QCPU as CPU No.1
This section describes the system configuration using a Basic model QCPU as CPU No.1.
3.1.1
Available CPU modules, base units, power supply modules,
and extension cables
Available CPU modules and the number of mountable modules differ depending on the main base unit used.
(1) When a main base unit (Q3B) is used
(a) Available modules, the number of extension base units, and the number of
mountable modules
Item
Description
3 CPU modules
Number of CPU
CPU No.1 (Basic model QCPU)
modules
CPU No.2 (Motion CPU)
CPU No.3 (C Controller module or PC CPU module)
Basic model QCPU
Q00CPU, Q01CPU
Function version B or later
Q172CPUN(-T), Q173CPUN(-T),
Motion CPU*2
Q172HCPU(-T), Q173HCPU(-T)
Manual for the Motion CPU
used
Q06CCPU-V, Q06CCPU-V-B,
Applicable CPU
C Controller module
module*1
Q12DCCPU-V, Q24DHCCPU-V,
No function version restriction
Q24DHCCPU-LS
PPC-CPU686(MS)-64,
PC CPU module
PPC-CPU686(MS)-128,
PPC-CPU852(MS)-512
Maximum number of
Manual for the PC CPU
module used
4 extension base units
extension base units
Maximum number of
mountable I/O
25 - (Number of CPU modules)
modules
Applicable main base
Q33B, Q35B, Q38B, Q312B
unit
Type requiring no power supply
Applicable extension
module (Q series)
base unit
Type requiring power supply module
(Q series)
Applicable extension
cable
Applicable power
supply module
*1
*2
32
Q52B, Q55B
Q63B, Q65B, Q68B, Q612B
QC05B, QC06B, QC12B, QC30B, QC50B, QC100B
Q61P-A1, Q61P-A2, Q61P, Q61P-D, Q62P, Q63P, Q64P, Q64PN
For the CPU modules that can be combined and their mounting positions, refer to Page 37, Section 3.1.2.
When using a Motion CPU, install operating system software on the CPU module. For models and versions of the
operating system, refer to the manual for the Motion CPU used.
CHAPTER 3 SYSTEM CONFIGURATION
(b) Precautions
• If I/O modules are mounted exceeding the maximum number, "SP.UNIT LAY ERR" (error code: 2124)
occurs.
• "Number of CPU modules" indicates the number set in "No. of PLC" of PLC parameter ("Multiple CPU
Setting").
• When a C Controller module which occupies three slots is used, the maximum number of mountable I/O
modules will be two smaller than the number defined in the table on Page 32, Section 3.1.1 (1) (a).
• A PC CPU module occupies two slots. When this module is used, the maximum number of mountable I/O
3
modules will be one smaller than the number defined in the table on Page 32, Section 3.1.1 (1) (a).
3.1 System Using Basic Model QCPU as CPU No.1
3.1.1 Available CPU modules, base units, power supply modules, and extension cables
33
(2) When a redundant power main base unit (Q3RB) is used
(a) Available modules, the number of extension base units, and the number of
mountable modules
Item
Description
2 CPU modules
Number of CPU
CPU No.1 (Basic model QCPU)
modules
CPU No.2 (C Controller module)
Basic model QCPU
Applicable CPU
module*1
Q00CPU, Q01CPU
Q24DHCCPU-V,
C Controller module
Q24DHCCPU-LS
Maximum number of
Function version B or later
No function version restriction
4 extension base units
extension base units
Maximum number of
mountable I/O
25 - (Number of CPU modules)
modules
Applicable main base
Q38RB
unit
Applicable extension
base unit
Type requiring no power supply
module (Q series)
Redundant power extension base unit
Applicable extension
cable
Applicable power
Q52B, Q55B
Q68RB
QC05B, QC06B, QC12B, QC30B, QC50B, QC100B
Q63RP, Q64RP
supply module
(The Q63RP and Q64RP can be mounted on the same redundant power supply base unit.)
(b) Precautions
• If I/O modules are mounted exceeding the maximum number, "SP.UNIT LAY ERR" (error code: 2124)
occurs.
• "Number of CPU modules" indicates the number set in "No. of PLC" of PLC parameter ("Multiple CPU
Setting").
• When a C Controller module which occupies three slots is used, the maximum number of mountable I/O
modules will be two smaller than the number defined in the table on Page 34, Section 3.1.1 (2) (a).
34
CHAPTER 3 SYSTEM CONFIGURATION
(3) When a slim type main base unit (Q3SB) is used
(a) Available modules, the number of extension base units, and the number of
mountable modules
Item
Description
Number of CPU
modules
3
2 CPU modules
CPU No.1 (Basic model QCPU)
CPU No.2 (C Controller module)
Applicable CPU
module*1
Basic model QCPU
C Controller module
Q00CPU, Q01CPU
Q06CCPU-V, Q06CCPU-V-B,
Q12DCCPU-V
Maximum number of
Function version B or later
No function version restriction
Extension not allowed
extension base units
Maximum number of
Q32SB
1
mountable I/O
Q33SB
2
modules
Q35SB
4
Applicable main base
unit
Applicable power
supply module
Q32SB, Q33SB, Q35SB
Q61SP
(b) Precautions
Slim type main base units do not have an extension cable connector. Therefore, no extension base unit or GOT
can be bus-connected.
3.1 System Using Basic Model QCPU as CPU No.1
3.1.1 Available CPU modules, base units, power supply modules, and extension cables
35
(4) When a multiple CPU high speed main base unit (Q3DB) is used
(a) Available modules, the number of extension base units, and the number of
mountable modules
Item
Description
2 CPU modules
Number of CPU
CPU No.1 (Basic model QCPU)
modules
CPU No.2 (C Controller module or PC CPU module)
Basic model QCPU
Q00CPU, Q01CPU
Function version B or later
Q06CCPU-V, Q06CCPU-V-B,
C Controller module
Applicable CPU
Q12DCCPU-V, Q24DHCCPU-V,
No function version restriction
Q24DHCCPU-LS
module*1
PPC-CPU686(MS)-64,
PC CPU module
PPC-CPU686(MS)-128,
PPC-CPU852(MS)-512
Maximum number of
Manual for the PC CPU
module used
4 extension base units
extension base units
Maximum number of
mountable I/O
25 - (Number of CPU modules)
modules
Applicable main base
Q35DB, Q38DB, Q312DB
unit
Type requiring no power supply
Applicable extension
module (Q series)
base unit
Type requiring power supply module
(Q series)
Applicable extension
cable
Applicable power
Q63B, Q65B, Q68B, Q612B
QC05B, QC06B, QC12B, QC30B, QC50B, QC100B
Q61P-A1, Q61P-A2, Q61P, Q61P-D, Q62P, Q63P, Q64P, Q64PN
supply module
*1
Q52B, Q55B
For the CPU modules that can be combined and their mounting positions, refer to Page 37, Section 3.1.2.
(b) Precautions
• If I/O modules are mounted exceeding the maximum number, "SP.UNIT LAY ERR" (error code: 2124)
occurs.
• "Number of CPU modules" indicates the number set in "No. of PLC" of PLC parameter ("Multiple CPU
Setting").
• When a C Controller module which occupies three slots is used, the maximum number of mountable I/O
modules will be two smaller than the number defined in the table on Page 36, Section 3.1.1 (4) (a).
• A PC CPU module occupies two slots. When this module is used, the maximum number of mountable I/O
modules will be one smaller than the number defined in the table on Page 36, Section 3.1.1 (4) (a).
36
CHAPTER 3 SYSTEM CONFIGURATION
3.1.2
CPU module combinations and mounting positions
This section describes the combinations and mounting positions of CPU modules when a Basic model QCPU is used
as CPU No.1.
Note that the CPU modules that can be mounted differ depending on the main base unit used. (
Page 32, Section
3.1.1)
3
(1) Combinations
Number of CPU modules that can be mounted as CPU No.2 or others
High
Motion CPU
Performance
CPU No.1
model QCPU,
Process CPU,
Q172CPUN(-T),
Q172DCPU(-S1),
Q06CCPU-V,
Q173CPUN(-T),
Q173DCPU(-S1),
Q06CCPU-V-B,
Q172HCPU(-T),
Q172DSCPU,
Q12DCCPU-V,
model QCPU
Q173HCPU(-T)*2
Q173DSCPU
Q24DHCCPU-V
Cannot be used
together.
0 to 1
Cannot be used
together.
0 to 1
Universal
Basic model
QCPU
C Controller module*1*2
*1
*2
PC CPU module*1
Maximum
number of
mountable
PPC-CPU686(MS)-64,
modules
PPC-CPU686(MS)-128,
(including
PPC-CPU852(MS)-512
CPU No.1)
0 to 1
3
A C Controller module and a PC CPU module cannot be mounted on the same main base unit.
A C Controller module (Q12DCCPU-V, Q24DHCCPU-V, or Q24DHCCPU-LS) and a Motion CPU (Q172CPUN(-T),
Q173CPUN(-T), Q172HCPU(-T), or Q173HCPU(-T)) cannot be mounted on the same main base unit.
(2) Mounting positions
The following shows the possible combinations of mounting positions of CPU modules in a multiple CPU system.
CPU No.2
CPU No.3
B
M
C
B
: Basic model QCPU
P
M
: Motion CPU
C
C
: C Controller module
P
P
: PC CPU module
(a) Basic model QCPU
Only one Basic model QCPU can be mounted in the CPU slot (the slot on the right of the power supply module)
of the main base unit.
(b) Motion CPU
Only one Motion CPU can be mounted in slot 0 on the right of the Basic model QCPU. It cannot be mounted in
a slot other than slot 0.
37
3.1 System Using Basic Model QCPU as CPU No.1
3.1.2 CPU module combinations and mounting positions
CPU No.1
(c) C Controller module or PC CPU module
Either a C Controller module or PC CPU module can be mounted on the extreme right of the other CPU
module(s). No CPU module can be mounted on the right of the C Controller module or PC CPU module.
1
Slot number
2
Motion CPU
0
PC CPU
module
Basic model
QCPU
Power supply
module
CPU
(d) Empty slot setting
Empty slots can be reserved for future addition of CPU modules. Set the number of CPU modules including
empty slots in "No. of PLC" of PLC parameter ("Multiple CPU Setting"). Then, set "PLC (Empty)" to the type of
a target slot in PLC parameter ("I/O Assignment").
2
Slot number
CPU
0
Motion CPU
PLC (Empty)
1
Basic model
QCPU
0
Power supply
module
CPU
Basic model
QCPU
Power supply
module
Ex. Adding a Motion CPU in slot 0 in the future
1
2
Slot number
Added Motion CPU
PLC (Empty)
Slot number
CPU
0
1
2
Slot number
PC CPU
module
Motion CPU
2
Motion CPU
1
Basic model
QCPU
0
Power supply
module
CPU
Basic model
QCPU
Power supply
module
Ex. Adding a PC CPU module in slot 1 in the future
Added PC CPU module
CPU
0
1
2
PC CPU
module
Slot number
Motion CPU
2
Basic model
QCPU
PLC (Empty)
1
Power supply
module
0
PC CPU
module
CPU
Basic model
QCPU
Power supply
module
Ex. Setting "PLC (Empty)" between CPU modules
Added Motion CPU
38
Slot number
CHAPTER 3 SYSTEM CONFIGURATION
● When a Basic model QCPU is used, "PLC (Empty)" can be set between CPU modules. This is useful when adding a
Motion CPU to the system where a Basic model QCPU and a C Controller module or PC CPU module are used. No
program modification is required because the CPU number of the C Controller module or PC CPU module does not need
to be changed even after the new module is added.
● For a CPU module that occupies two slots or more, secure as many empty slots as needed for the module.
3
3.1 System Using Basic Model QCPU as CPU No.1
3.1.2 CPU module combinations and mounting positions
39
3.1.3
Available I/O modules and intelligent function modules
This section describes I/O modules and intelligent function modules that can be used.
(1) I/O modules and interrupt module
I/O modules (QX and QY) and interrupt module (QI60) can be used. Any CPU module can be set as a control
CPU.
(2) Intelligent function modules
Intelligent function modules with function version B or later can be used. Any CPU module can be set as a control
CPU.
Write parameters of each intelligent function module to the CPU module to be controlled.
The following modules can be used even if their function version is not B or later.
Module that can be used
Description
even if its function version is not B or later
High-speed counter module (QD62, QD62D, QD62E)
Modules with function version A can be used.
Any CPU module can be set as a control CPU.
Remark
Intelligent function modules with function version A (except high-speed counter modules (QD62, QD62D, and QD62E)) can
be used in the multiple CPU system only when CPU No.1 is set as a control CPU.
• External devices can access only the control CPU (CPU No.1) via a serial communication module.
• External devices cannot access CPU modules other than the control CPU (CPU No.1) via a MELSECNET/H
module or serial communication module.
• If any of CPU No.2 to No.4 is set as a control CPU, "SP.UNIT VER.ERR" (error code: 2150) will occur and the
multiple CPU system will not start up.
(3) Number of mountable modules
Refer to Page 68, Section 3.5.
(4) Access ranges of controlled and non-controlled modules
Each CPU module can access non-controlled modules by setting "I/O Sharing When Using Multiple CPUs" in
PLC parameter ("Multiple CPU Setting"). (
Page 104, Section 5.2)
If all of the following conditions are met, use a MELSECNET/H module with a serial number (first five digits) of "10042" or
later.
• A multiple CPU system containing a Built-in Ethernet port QCPU is configured.
• A programming tool or GOT is connected to an Ethernet port of the Built-in Ethernet port QCPU.
• A programming tool or GOT accesses another station via a MELSECNET/H module controlled by a CPU module
other than the control CPU.
• The access target on another station is an A/QnA series CPU module.
40
CHAPTER 3 SYSTEM CONFIGURATION
3.2
System Using High Performance Model QCPU or
Process CPU as CPU No.1
This section describes the system configuration using a High Performance model QCPU or Process CPU as CPU
No.1.
3.2.1
Available CPU modules, base units, power supply modules,
and extension cables
3
Available CPU modules and the number of mountable modules differ depending on the main base unit used.
(1) When a main base unit (Q3B) is used
(a) Available modules, the number of extension bases units, and the number of
mountable modules
Item
Description
Number of CPU
modules
High Performance model QCPU
Q02(H)CPU, Q06HCPU, Q12HCPU,
Q25HCPU
Process CPU
Q02PHCPU, Q06PHCPU, Q12PHCPU,
Q25PHCPU
No function version restriction
Universal model QCPU
Q03UD(E)CPU, Q03UDVCPU,
Q04UD(E)HCPU, Q04UDVCPU,
Q06UD(E)HCPU, Q06UDVCPU,
Q10UD(E)HCPU, Q13UD(E)HCPU,
Q13UDVCPU, Q20UD(E)HCPU,
Q26UD(E)HCPU, Q26UDVCPU,
Q50UDEHCPU, Q100UDEHCPU
No function version restriction
Motion CPU*2
Q172CPUN(-T), Q173CPUN(-T),
Q172HCPU(-T), Q173HCPU(-T)
module*1
Q06CCPU-V, Q06CCPU-V-B
C Controller module
Applicable CPU
module*1
Maximum number of
extension base units
• Function version B
• Function version B with a serial number
(first five digits) of "03051" or later when
used as CPU No.1 and with a PC CPU
module
PC CPU module
Manual for the Motion CPU used
• Serial number (first five digits) of "10012"
or later when used with the
Q03UDECPU, Q04UDEHCPU,
Q06UDEHCPU, Q13UD(E)HCPU, or
Q26UD(E)HCPU
• Serial number (first five digits) of "10102"
or later when used with the
Q10UD(E)HCPU, Q20UD(E)HCPU,
Q50UDEHCPU, or Q100UDEHCPU
• Cannot be used with the QnUDVCPU.
Q12DCCPU-V
Serial number (first five digits) of "14122" or
later when used with the QnUDVCPU
Q24DHCCPU-V
Serial number (first five digits) of "14122" or
later when used with the QnUDVCPU
Q24DHCCPU-LS
No function version restriction
PPC-CPU686(MS)-64,
PPC-CPU686(MS)-128,
PPC-CPU852(MS)-512
Manual for the PC CPU module
used
Cannot be used with the QnUDVCPU.
7 extension base units
41
3.2 System Using High Performance Model QCPU or Process CPU as CPU No.1
3.2.1 Available CPU modules, base units, power supply modules, and extension cables
Applicable CPU
4 CPU modules
Item
Description
Maximum number of
mountable I/O modules
65 - (Number of CPU modules)
Applicable main base
unit
Q33B, Q35B, Q38B, Q312B
Type requiring no power supply module
(Q series)
Q52B, Q55B
Type requiring power supply module (Q
series)
Q63B, Q65B, Q68B, Q612B
Type requiring no power supply module
(AnS series)*3*4
Applicable extension
base unit
Type requiring power supply module
QA1S65B, QA1S68B, QA1S6ADP+A1S6B*6
(AnS series)*3*5
Type requiring no power supply module
(A series)*3
Type requiring power supply module (A
series)*3
Applicable extension
cable
QA1S51B, QA1S6ADP+A1S5B*6
QA6ADP+A5B
QA65B, QA68B, QA6ADP+A6B
QC05B, QC06B, QC12B, QC30B, QC50B, QC100B
Power supply module (Q series)
Applicable power supply
module
Power supply module (AnS series)
Power supply module (A series)
Q61P-A1, Q61P-A2, Q61P, Q61P-D, Q62P, Q63P, Q64P, Q64PN
*3
*3
A1S61PN, A1S62PN, A1S63P
A61P, A61PN, A62P, A63P, A61PEU, A62PEU
*1
*2
For the CPU modules that can be combined and their mounting positions, refer to Page 47, Section 3.2.2.
When using a Motion CPU, install operating system software on the CPU module. For models and versions of the
operating system, refer to the manual for the Motion CPU used.
*3
*4
These units cannot be used in a multiple CPU system including a Process CPU. (
Page 188, Appendix 3)
Since the QA1S51B does not have an extension cable connector (OUT), it cannot be used with the QA6B or
QA6ADP+A5B/A6B.
When the QA1S6B is used as an extension base unit, the QA6ADP+A5B/A6B cannot be connected.
When the QA1S6ADP+A1S5B/A1S6B is used, the maximum number of extension base units is 1, and the maximum
number of I/O modules that can be mounted is 20 minus the number of CPU modules. When the QA1S6ADPS1+A1S5B/A1S6B is used, the maximum number of extension base units is 3, and the maximum number of I/O
modules that can be mounted is 36 minus the number of CPU modules.
*5
*6
(b) Precautions
• Extension base units, QA1S5B, QA1S6B, QA1S6ADP+A1S5B/A1S6B, QA6B, and
QA6ADP+A5B/A6B, can be connected when a High Performance model QCPU is set as the control
CPU of AnS/A series modules. (
Page 188, Appendix 3)
• If I/O modules are mounted exceeding the maximum number, "SP.UNIT LAY ERR" (error code: 2124)
occurs.
• "Number of CPU modules" indicates the number set in "No. of PLC" of PLC parameter ("Multiple CPU
Setting").
• When a C Controller module which occupies three slots is used, the maximum number of mountable I/O
modules will be two smaller than the number defined in the table on Page 41, Section 3.2.1 (1) (a).
• A PC CPU module occupies two slots. When this module is used, the maximum number of mountable I/O
modules will be one smaller than the number defined in the table on Page 41, Section 3.2.1 (1) (a).
42
CHAPTER 3 SYSTEM CONFIGURATION
(2) When a redundant power main base unit (Q3RB) is used
(a) Available modules, the number of extension base units, and the number of
mountable modules
Item
Description
Number of CPU
modules
High Performance model QCPU
Q02(H)CPU, Q06HCPU, Q12HCPU,
Q25HCPU
Function version B
Process CPU
Q02PHCPU, Q06PHCPU, Q12PHCPU,
Q25PHCPU
No function version restriction
Universal model QCPU
Q03UD(E)CPU, Q03UDVCPU,
Q04UD(E)HCPU, Q04UDVCPU,
Q06UD(E)HCPU, Q06UDVCPU,
Q10UD(E)HCPU, Q13UD(E)HCPU,
Q13UDVCPU, Q20UD(E)HCPU,
Q26UD(E)HCPU, Q26UDVCPU,
Q50UDEHCPU, Q100UDEHCPU
No function version restriction
Q24DHCCPU-V
Serial number (first five digits) of "14122" or
later when used with the QnUDVCPU
Q24DHCCPU-LS
No function version restriction
Applicable CPU
module*1
C Controller module
Maximum number of
extension base units
7 extension base units
Maximum number of
mountable I/O modules
65 - (Number of CPU modules)
Applicable main base
unit
Q38RB
Type requiring no power supply module
(Q series)
Q52B, Q55B
Redundant power extension base unit
Q68RB
Applicable extension
cable
QC05B, QC06B, QC12B, QC30B, QC50B, QC100B
Applicable power supply
module
Q63RP, Q64RP
(The Q63RP and Q64RP can be mounted on the same redundant power supply base unit.)
For the CPU modules that can be combined and their mounting positions, refer to Page 47, Section 3.2.2.
(b) Precautions
• If I/O modules are mounted exceeding the maximum number, "SP.UNIT LAY ERR" (error code: 2124)
occurs.
• "Number of CPU modules" indicates the number set in "No. of PLC" of PLC parameter ("Multiple CPU
Setting").
• When a C Controller module which occupies three slots is used, the maximum number of mountable I/O
modules will be two smaller than the number defined in the table on Page 43, Section 3.2.1 (2) (a).
43
3.2 System Using High Performance Model QCPU or Process CPU as CPU No.1
3.2.1 Available CPU modules, base units, power supply modules, and extension cables
Applicable extension
base unit
*1
3
4 CPU modules
(3) When a slim type main base unit (Q3SB) is used
(a) Available modules, the number of extension base units, and the number of
mountable modules
Item
Description
Number of CPU
modules
3 CPU modules
High Performance model QCPU
Q02(H)CPU, Q06HCPU, Q12HCPU,
Q25HCPU
Function version B
Universal model QCPU
Q03UD(E)CPU, Q03UDVCPU,
Q04UD(E)HCPU, Q04UDVCPU,
Q06UD(E)HCPU, Q06UDVCPU,
Q10UD(E)HCPU, Q13UD(E)HCPU,
Q13UDVCPU, Q20UD(E)HCPU,
Q26UD(E)HCPU, Q26UDVCPU,
Q50UDEHCPU, Q100UDEHCPU
No function version restriction
Applicable CPU
module
*1
Q06CCPU-V, Q06CCPU-V-B
C Controller module
Serial number (first five digits) of "14122" or
later when used with the QnUDVCPU
Q12DCCPU-V
Maximum number of
extension base units
Extension not allowed
Maximum number of
mountable I/O modules
Q32SB
3 - (Number of CPU modules)
Q33SB
4 - (Number of CPU modules)
Q35SB
6 - (Number of CPU modules)
Applicable main base
unit
Q32SB, Q33SB, Q35SB
Applicable power supply
module
*1
• Serial number (first five digits) of "10012"
or later when used with the
Q03UDECPU, Q04UDEHCPU,
Q06UDEHCPU, Q13UD(E)HCPU, or
Q26UD(E)HCPU
• Serial number (first five digits) of "10102"
or later when used with the
Q10UD(E)HCPU, Q20UD(E)HCPU,
Q50UDEHCPU, or Q100UDEHCPU
• Cannot be used with the QnUDVCPU.
Q61SP
For the CPU modules that can be combined and their mounting positions, refer to Page 47, Section 3.2.2.
(b) Precautions
• Slim type main base units do not have an extension cable connector. Therefore, no extension base unit or
GOT can be bus-connected.
• Four CPU modules cannot be mounted because the power consumption of the CPU modules exceeds the
rated output current of the power supply module (Q61SP).
If a C Controller module is used, three CPU modules cannot be mounted.
• "Number of CPU modules" indicates the number set in "No. of PLC" of PLC parameter ("Multiple CPU
Setting").
44
CHAPTER 3 SYSTEM CONFIGURATION
(4) When a multiple CPU high speed main base unit (Q3DB) is used
(a) Available modules, the number of extension base units, and the number of
mountable modules
Item
Description
Number of CPU
modules
• Function version B
• Function version B with a serial number
(first five digits) of "03051" or later when a
module is used as CPU No.1 and used
with a PC CPU module
High Performance model QCPU
Q02(H)CPU, Q06HCPU, Q12HCPU,
Q25HCPU
Process CPU
Q02PHCPU, Q06PHCPU,
Q12PHCPU, Q25PHCPU
No function version restriction
Universal model QCPU
Q03UD(E)CPU, Q03UDVCPU,
Q04UD(E)HCPU, Q04UDVCPU,
Q06UD(E)HCPU, Q06UDVCPU,
Q10UD(E)HCPU, Q13UD(E)HCPU,
Q13UDVCPU, Q20UD(E)HCPU,
Q26UD(E)HCPU, Q26UDVCPU,
Q50UDEHCPU, Q100UDEHCPU
No function version restriction
Applicable CPU
module*1
Q06CCPU-V, Q06CCPU-V-B
C Controller module
Maximum number of
extension base units
• Serial number (first five digits) of "10012"
or later when used with the Q03UDECPU,
Q04UDEHCPU, Q06UDEHCPU,
Q13UD(E)HCPU, or Q26UD(E)HCPU
• Serial number (first five digits) of "10102"
or later when used with the
Q10UD(E)HCPU, Q20UD(E)HCPU,
Q50UDEHCPU, or Q100UDEHCPU
• Cannot be used with the QnUDVCPU.
Q12DCCPU-V
Serial number (first five digits) of "14122" or
later when used with the QnUDVCPU
Q24DHCCPU-V
Serial number (first five digits) of "14122" or
later when used with the QnUDVCPU
Q24DHCCPU-LS
No function version restriction
PPC-CPU686(MS)-64,
PPC-CPU686(MS)-128,
PPC-CPU852(MS)-512
Manual for the PC CPU module used
Cannot be used with the QnUDVCPU.
7 extension base units
Maximum number of
mountable I/O modules
65 - (Number of CPU modules)
Applicable main base
unit
Q35DB, Q38DB, Q312DB
Applicable extension
base unit
Applicable extension
cable
Type requiring no power supply module (Q
series)
Q52B, Q55B
Type requiring power supply module (Q
series)
Q63B, Q65B, Q68B, Q612B
QC05B, QC06B, QC12B, QC30B, QC50B, QC100B
Applicable power supply
module
Q61P-A1, Q61P-A2, Q61P, Q61P-D, Q62P, Q63P, Q64P, Q64PN
For the CPU modules that can be combined and their mounting positions, refer to Page 47, Section 3.2.2.
45
3.2 System Using High Performance Model QCPU or Process CPU as CPU No.1
3.2.1 Available CPU modules, base units, power supply modules, and extension cables
PC CPU module
*1
3
4 CPU modules
(b) Precautions
• If I/O modules are mounted exceeding the maximum number, "SP.UNIT LAY ERR" (error code: 2124)
occurs.
• "Number of CPU modules" indicates the number set in "No. of PLC" of PLC parameter ("Multiple CPU
Setting").
• A C Controller module (Q24DHCCPU-V) occupies three slots. When this module is used, the maximum
number of mountable I/O modules will be two smaller than the number defined in the table on Page 45,
Section 3.2.1 (4) (a).
• When a C Controller module which occupies three slots is used, the maximum number of mountable I/O
modules will be two smaller than the number defined in the table on Page 45, Section 3.2.1 (4) (a).
46
CHAPTER 3 SYSTEM CONFIGURATION
3.2.2
CPU module combinations and mounting positions
This section describes the combinations and mounting positions of CPU modules when a High Performance model
QCPU or Process CPU is used as CPU No.1.
Note that the CPU modules that can be mounted differ depending on the main base unit used. (
Page 41, Section
3.2.1)
3
(1) Combinations
Number of CPUs that can be mounted as CPU No.2 or others
Motion CPU
High
Performance
model QCPU,
Process CPU,
Universal model
Q172CPUN(-T),
Q173CPUN(-T),
Q172HCPU(-T),
QCPU*1*2*5*6*7
Q173HCPU(-T)*2*4
High
Performance
model QCPU
0 to 3
Process CPU
0 to 3
CPU No.1
*1
*2
*3
*4
*6
*7
PC CPU module*3*5*7
PPCCPU686
(MS)-64,
PPCCPU686
(MS)-128
Maximum
number of
mountable
modules
(including CPU
No.1)
Q172DCPU(-S1),
Q173DCPU(-S1),
Q172DSCPU,
Q173DSCPU
Q06CCPU-V,
Q06CCPU-V-B,
Q12DCCPU-V
Q24DHC
CPU-V,
Q24DHC
CPU-LS
0 to 3
Cannot be used
together.
0 to 3
0 to 1
0 to 1
4
0 to 3
Cannot be used
together.
0 to 3
0 to 1
0 to 1
4
PPCCPU852
(MS)-512
The Q00UCPU, Q01UCPU, and Q02UCPU can be used only as CPU No.1.
A Universal model CPU (except the Q00UCPU, Q01UCPU, and Q02UCPU) and a Motion CPU (Q172CPUN(-T),
Q173CPUN(-T), Q172HCPU(-T), or Q173HCPU(-T)) cannot be mounted on the same main base unit.
A C Controller module and a PC CPU module cannot be mounted on the same main base unit.
A C Controller module (Q12DCCPU-V, Q24DHCCPU-V, or Q24DHCCPU-LS) and a Motion CPU (Q172CPUN(-T),
Q173CPUN(-T), Q172HCPU(-T), or Q173HCPU(-T)) cannot be mounted on the same main base unit.
A Universal model QCPU and a PC CPU module (PPC-CPU686(MS)-64 or PPC-CPU686(MS)-128) cannot be used
together. When a Universal model QCPU is used, use the PPC-CPU852(MS)-512.
A QnUDVCPU and a C Controller module (Q06CCPU-V or Q06CCPU-V-B) cannot be mounted on the same main base
unit.
A QnUDVCPU and a PC CPU module cannot be mounted on the same main base unit.
47
3.2 System Using High Performance Model QCPU or Process CPU as CPU No.1
3.2.2 CPU module combinations and mounting positions
*5
C Controller module*3*4*6
(2) Mounting positions
The following shows the possible combinations of mounting positions of CPU modules in a multiple CPU system.
CPU No.1
CPU No.2
CPU No.3
CPU No.4
Q
Q
Q
Q
M
C
P
M
M
C
P
C
C
P
M
M
M
C
P
C
C
P
C
P
*1
48
C
C
Q
: QCPU*1
M
: Motion CPU
C
: C Controller module
P
: PC CPU module
The QCPU used as CPU No.1 indicates a High Performance model QCPU or Process CPU.
The QCPU used as CPU No.2 or later indicates a High Performance model QCPU, Process CPU, or Universal model
QCPU (except the Q00UCPU, Q01UCPU, and Q02UCPU).
CHAPTER 3 SYSTEM CONFIGURATION
(a) High Performance model QCPU or Process CPU
Up to four High Performance model QCPUs and/or Process CPUs can be mounted in the CPU slot (the slot on
the right of the power supply module) to slot 2 of the main base unit.
(b) Universal model QCPU
Up to three Universal model QCPUs can be mounted in slot 0 to slot 2 of the main base unit.
3
(c) Motion CPU
Up to three Motion CPUs can be mounted in the slot on the right of the High Performance model QCPU or
Process CPU to slot 2 of the main base unit. Only a Motion CPU, C Controller module, or PC CPU module can
be mounted on the right of the Motion CPU.
0
1
2
Motion CPU
Motion CPU
CPU
QCPU
Motion CPU
Slot number
Motion CPU
2
QCPU
1
Power supply
module
0
QCPU
Incorrect mounting positions
CPU
QCPU
Power supply
module
Correct mounting positions
Slot number
(d) C Controller module
Up to three C Controller modules can be mounted in slot 0 to slot 2 of the main base unit. For a C Controller
module which occupies three slots, only one module can be mounted.
Note that only a C Controller module can be mounted on the right of the C Controller module.
(e) PC CPU module
Only one PC CPU module can be mounted on the rightmost slot available for CPU modules. No CPU module
1
2
Slot number
Motion CPU
0
PC CPU
module
QCPU
Power supply
module
CPU
3.2 System Using High Performance Model QCPU or Process CPU as CPU No.1
3.2.2 CPU module combinations and mounting positions
can be mounted on the right of the PC CPU module.
49
(f) Empty slot setting
Empty slots can be reserved for future addition of CPU modules. Set the number of CPU modules including
empty slots in "No. of PLC" of PLC parameter ("Multiple CPU Setting"). Then, set "PLC (Empty)" to the type of
a target slot from the right in PLC parameter ("I/O Assignment").
Ex. Setting the number of CPU modules to "4" in PLC parameter and mounting two High Performance model
QCPUs and one Motion CPU
Mount the High Performance model QCPUs in the CPU slot and slot 0, and the Motion CPU in slot 1, and
set "PLC (Empty)" to slot 2.
PLC (empty)
CPU
0
1
Slot number
2
Motion CPU
Motion CPU
Slot number
PLC (empty)
2
QCPU
1
QCPU
0
Power supply
module
CPU
QCPU
Incorrect mounting positions
QCPU
Power supply
module
Correct mounting positions
When a High Performance model QCPU or Process CPU is used, "PLC (Empty)" cannot be set between CPU modules. To
add a CPU module to the system where a C Controller module or PC CPU module is used, move the C Controller module or
PC CPU module to the right to allow addition of a CPU module.
Set "PLC (Empty)" to slot 2.
Add a CPU module.
Motion CPU
Move to the right.
50
1
2
3
4
Input module
0
PC CPU
module
CPU
Motion CPU
Slot number
Motion CPU
4
High Performance
model QCPU
3
Power supply
module
2
Input module
Motion CPU
1
(Empty)
0
PC CPU
module
CPU
High Performance
model QCPU
Power supply
module
Keep slot 3 empty.
Slot number
CHAPTER 3 SYSTEM CONFIGURATION
3.2.3
Available I/O modules and intelligent function modules
This section describes the I/O modules and intelligent function modules that can be used.
(1) I/O modules, interrupt modules, and intelligent function modules
Refer to the system configuration using a Basic model QCPU as CPU No.1. (
Page 40, Section 3.1.3 (1),
Page 40, Section 3.1.3 (2))
3
(2) Modules replaceable online
(a) I/O modules and intelligent function modules that can be replaced
Modules can be replaced online in a multiple CPU system including a Process CPU.
Modules controlled by the Process CPU are targeted.
The following table lists modules that can be replaced online.
Module can be replaced
Restrictions
Input module
Output module
No function version restriction
I/O combined module
Analog-digital converter module
Digital-analog converter module
Temperature input module
Intelligent function
Temperature control module
module
Pulse input module
Function version C
CT input module
Loop control module
(b) Applicable CPU modules
To replace a module controlled by the Process CPU online, configure a multiple CPU system with the CPU
modules listed below.
CPU module
High Performance
model QCPU
Process CPU
Model
Q02(H)CPU, Q06HCPU, Q12HCPU, Q25HCPU
Restrictions
Serial number (first five digits) of
"04012" or later
Q02PHCPU, Q06PHCPU, Q12PHCPU, Q25PHCPU
Q03UD(E)CPU, Q03UDVCPU, Q04UD(E)HCPU,
Q04UDVCPU, Q06UD(E)HCPU, Q06UDVCPU,
Universal model QCPU
Q10UD(E)HCPU, Q13UD(E)HCPU, Q13UDVCPU,
No function version restriction
Q20UD(E)HCPU, Q26UD(E)HCPU, Q26UDVCPU,
Q50UDEHCPU, Q100UDEHCPU
Motion CPU
C Controller module
PC CPU module
Q172CPUN(-T), Q173CPUN(-T), Q172HCPU(-T),
Q173HCPU(-T)
Version A or later
Q06CCPU-V, Q06CCPU-V-B, Q12DCCPU-V,
Q24DHCCPU-V, Q24DHCCPU-LS
PPC-CPU686(MS)-64, PPC-CPU686(MS)-128,
Manual for the CPU module
used
PPC-CPU852(MS)-512
51
3.2 System Using High Performance Model QCPU or Process CPU as CPU No.1
3.2.3 Available I/O modules and intelligent function modules
Load cell input module
(3) Number of mountable modules
Refer to Page 68, Section 3.5.
(4) Access ranges of controlled and non-controlled modules.
Refer to the system configuration using a Basic model QCPU as CPU No.1. (
52
Page 40, Section 3.1.3 (4))
CHAPTER 3 SYSTEM CONFIGURATION
3.3
System Using Universal Model QCPU as CPU No.1
This section describes the system configuration using a Universal model QCPU as CPU No.1.
3.3.1
Available CPU modules, base units, power supply modules,
and extension cables
3
Available CPU modules and the number of mountable modules differ depending on the main base unit used.
(1) When a multiple CPU high-speed main base unit (Q3DB) is used
(a) Available modules, the number of extension base units, and the number of
mountable modules
Item
Description
Number of CPU
modules
4 CPU modules
Q00UCPU, Q01UCPU, Q02UCPU
Universal model QCPU
Q03UD(E)CPU, Q03UDVCPU,
Q04UD(E)HCPU, Q04UDVCPU,
Q06UD(E)HCPU, Q06UDVCPU,
Q10UD(E)HCPU, Q13UD(E)HCPU,
Q13UDVCPU, Q20UD(E)HCPU,
Q26UD(E)HCPU, Q26UDVCPU,
Q50UDEHCPU, Q100UDEHCPU
The modules can be used as CPU No.1.*2
• No function version restriction
• Serial number (first five digits) of "09072"
or later when used with a PC CPU module
Q02(H)CPU, Q06HCPU, Q12HCPU,
Q25HCPU
Function version B
Process CPU
Q02PHCPU, Q06PHCPU, Q12PHCPU,
Q25PHCPU
No function version restriction
Motion CPU*6
Q172DCPU(-S1), Q173DCPU(-S1),
Q172DSCPU, Q173DSCPU
Applicable CPU
module*1
Q06CCPU-V, Q06CCPU-V-B
C Controller module
Manual for the Motion CPU
• Serial number (first five digits) of "10102"
or later when used with the Q00UCPU,
Q01UCPU, or Q02UCPU
• Serial number (first five digits) of "10012"
or later when used with the Q03UDECPU,
Q04UDEHCPU, Q06UDEHCPU,
Q13UD(E)HCPU, or Q26UD(E)HCPU
• Serial number (first five digits) of "10102"
or later when used with the
Q10UD(E)HCPU, Q20UD(E)HCPU,
Q50UDEHCPU, or Q100UDEHCPU
• Cannot be used with the QnUDVCPU.
Q12DCCPU-V
Serial number (first five digits) of "14122" or
later when used with the QnUDVCPU
Q24DHCCPU-V
Serial number (first five digits) of "14122" or
later when used with the QnUDVCPU
Q24DHCCPU-LS
No function version restriction
53
3.3 System Using Universal Model QCPU as CPU No.1
3.3.1 Available CPU modules, base units, power supply modules, and extension cables
High Performance model QCPU
Item
Description
Applicable CPU
PC CPU module
module*1
PPC-CPU852(MS)-512
• Driver S/W (PPC-DRV-02) version 1.03 or
later when used with the Q00UCPU or
Q01UCPU
• Driver S/W (PPC-DRV-02) version 1.01 or
later when used with the Q02UCPU
• Driver S/W (PPC-DRV-02) version 1.01 or
later when used with the Q03UDCPU,
Q04UDHCPU, or Q06UDHCPU
• Driver S/W (PPC-DRV-02) version 1.02 or
later when used with the Q03UDECPU,
Q04UDEHCPU, Q06UDEHCPU,
Q13UD(E)HCPU, or Q26UD(E)HCPU
• Driver S/W (PPC-DRV-02) version 1.03 or
later when used with the Q10UDEHCPU,
Q20UDEHCPU, Q50UDEHCPU, or
Q100UDEHCPU
• Cannot be used with the QnUDVCPU.
Maximum number
of extension base
units
7 extension base units,
when the Q00UCPU, Q01UCPU, or Q02UCPU is used: 4 extension base units
Maximum number
of mountable I/O
modules
65 - (Number of CPU modules),
when the Q00UCPU or Q01UCPU is used: 25 - (Number of CPU modules),
when the Q02UCPU is used: 37 - (Number of CPU modules)
Applicable main
base unit
Q35DB, Q38DB, Q312DB
Type requiring no power supply module (Q
series)
Q52B, Q55B
Type requiring power supply module (Q series)
Q63B, Q65B, Q68B, Q612B
Type requiring no power supply module (AnS
series)*3*5
Applicable
extension base
unit
Type requiring power supply module (AnS
series)*3*4
Type requiring no power supply module (A
series)*3
Type requiring power supply module (A
series)*3
Applicable
extension cable
QA1S51B, QA1S6ADP+A1S5B*7
QA1S65B, QA1S68B, QA1S6ADP+A1S6B*7
QA6ADP+A5B
QA65B, QA68B, QA6ADP+A6B
QC05B, QC06B, QC12B, QC30B, QC50B, QC100B
Power supply module (Q series)
Applicable power
supply module
Power supply module (AnS series)
Power supply module (A
*1
*2
Q61P-A1, Q61P-A2, Q61P, Q62P, Q63P, Q64P, Q64PN
*3
series)*3
A1S61PN, A1S62PN, A1S63P
A61P, A61PN, A62P, A63P, A61PEU, A62PEU
For the CPU modules that can be combined and their mounting positions, refer to Page 60, Section 3.3.2.
When the Q00UCPU, Q01UCPU, or Q02UCPU is used as CPU No.1, one more CPU module (CPU No.2) can be
mounted. The following CPU modules can be mounted as CPU No.2.
CPU module
Q06CCPU-V, Q06CCPU-V-B, Q12DCCPU-V, Q24DHCCPU-V, Q24DHCCPU-LS
PC CPU module
PPC-CPU852(MS)-512
*3
*4
*5
*6
*7
54
Model
C Controller module
These modules and units can be used when a Universal model QCPU with a serial number (first five digits) of "13102" or
later is set as the control CPU of AnS/A series modules. These modules and units cannot be used in a multiple CPU
system containing a Process CPU (
Page 188, Appendix 3)
When the QA1S6B is used as an extension base unit, the QA6ADP+A5B/A6B cannot be connected.
Since the QA1S51B does not have an extension cable connector (OUT), it cannot be used with the QA6B or
QA6ADP+A5B/A6B.
When using a Motion CPU, install operating system software on the CPU module. For models and versions of the
operating system, refer to the manual for the Motion CPU used.
When the QA1S6ADP+A1S5B/A1S6B is used, the maximum number of extension base units is 1, and the maximum
number of I/O modules that can be mounted is 20 minus the number of CPU modules. When the QA1S6ADPS1+A1S5B/A1S6B is used, the maximum number of extension base units is 3, and the maximum number of I/O
modules that can be mounted is 36 minus the number of CPU modules.
CHAPTER 3 SYSTEM CONFIGURATION
(b) Precautions
• If I/O modules are mounted exceeding the maximum number, "SP.UNIT LAY ERR" (error code: 2124)
occurs.
• "Number of CPU modules" indicates the number set in "No. of PLC" of PLC parameter ("Multiple CPU
Setting").
• When a C Controller module which occupies three slots is used, the maximum number of mountable I/O
modules will be two smaller than the number defined in the table on Page 53, Section 3.3.1 (1) (a).
• A PC CPU module occupies two slots. When this module is used, the maximum number of mountable I/O
3
modules will be one smaller than the number defined in the table on Page 53, Section 3.3.1 (1) (a).
3.3 System Using Universal Model QCPU as CPU No.1
3.3.1 Available CPU modules, base units, power supply modules, and extension cables
55
(2) When a main base unit (Q3B) is used
(a) Available modules, the number of extension base units, and the number of
mountable modules
Item
Description
Number of CPU
modules
4 CPU modules
Q00UCPU, Q01UCPU, Q02UCPU
Q03UD(E)CPU, Q03UDVCPU,
Q04UD(E)HCPU, Q04UDVCPU,
Q06UD(E)HCPU, Q06UDVCPU,
Q10UD(E)HCPU, Q13UD(E)HCPU,
Q13UDVCPU, Q20UD(E)HCPU,
Q26UD(E)HCPU, Q26UDVCPU,
Q50UDEHCPU, Q100UDEHCPU
Universal model QCPU
Q02(H)CPU, Q06HCPU, Q12HCPU,
Q25HCPU
Function version B
Process CPU
Q02PHCPU, Q06PHCPU, Q12PHCPU,
Q25PHCPU
No function version restriction
Motion CPU
Q172CPUN(-T), Q173CPUN(-T),
Q172HCPU(-T), Q173HCPU(-T)
Manual for the Motion CPU
Can be used with the Q00UCPU, Q01UCPU, or
Q02UCPU.
Applicable CPU
C Controller module
PC CPU module
Maximum number
of extension base
units
56
• No function version restriction
• Serial number (first five digits) of "09072" or later
when used with a PC CPU module
High Performance model QCPU
Q06CCPU-V, Q06CCPU-V-B
module*1
The modules can be used as CPU No.1.*2
• Serial number (first five digits) of "10102" or later
when used with the Q00UCPU, Q01UCPU, or
Q02UCPU
• Serial number (first five digits) of "10012" or later
when used with the Q03UDECPU,
Q04UDEHCPU, Q06UDEHCPU,
Q13UD(E)HCPU, or Q26UD(E)HCPU
• Serial number (first five digits) of "10102" or later
when used with the Q10UD(E)HCPU,
Q20UD(E)HCPU, Q50UDEHCPU, or
Q100UDEHCPU
• Cannot be used with the QnUDVCPU.
Q12DCCPU-V
Serial number (first five digits) of "14122" or later
when used with the QnUDVCPU
Q24DHCCPU-V
Serial number (first five digits) of "14122" or later
when used with the QnUDVCPU
Q24DHCCPU-LS
No function version restriction
PPC-CPU852(MS)-512
• Driver S/W (PPC-DRV-02) version 1.03 or later
when used with the Q00UCPU or Q01UCPU
• Driver S/W (PPC-DRV-02) version 1.01 or later
when used with the Q02UCPU
• Driver S/W (PPC-DRV-02) version 1.01 or later
when used with the Q03UDCPU, Q04UDHCPU,
or Q06UDHCPU
• Driver S/W (PPC-DRV-02) version 1.02 or later
when used with the Q03UDECPU,
Q04UDEHCPU, Q06UDEHCPU,
Q13UD(E)HCPU, or Q26UD(E)HCPU
• Driver S/W (PPC-DRV-02) version 1.03 or later
when used with the Q10UDEHCPU,
Q20UDEHCPU, Q50UDEHCPU, or
Q100UDEHCPU
• Cannot be used with the QnUDVCPU.
7 extension base units,
when the Q00UCPU, Q01UCPU, or Q02UCPU is used: 4 extension base units
CHAPTER 3 SYSTEM CONFIGURATION
Item
Description
Maximum number
of mountable I/O
modules
65 - (Number of CPU modules),
when the Q00UCPU or Q01UCPU is used: 25 - (Number of CPU modules),
when the Q02UCPU is used: 37 - (Number of CPU modules)
Applicable main
base unit
Q33B, Q35B, Q38B, Q312B
Type requiring no power supply module
(Q series)
Q52B, Q55B
Type requiring power supply module (Q
series)
Q63B, Q65B, Q68B, Q612B
Type requiring no power supply module
(AnS series)*3*5
Applicable
extension base
unit
Type requiring power supply module
(AnS series)*3*4
Type requiring no power supply module
(A series)*3
Type requiring power supply module (A
series)*3
Applicable
extension cable
3
QA1S51B, QA1S6ADP+A1S5B*6
QA1S65B, QA1S68B, QA1S6ADP+A1S6B*6
QA6ADP+A5B
QA65B, QA68B, QA6ADP+A6B
QC05B, QC06B, QC12B, QC30B, QC50B, QC100B
Power supply module (Q series)
Applicable power
supply module
*1
*2
Q61P-A1, Q61P-A2, Q61P, Q62P, Q63P, Q64P, Q64PN
*3
Power supply module (AnS series)
A1S61PN, A1S62PN, A1S63P
Power supply module (A series)*3
A61P, A61PN, A62P, A63P, A61PEU, A62PEU
For the CPU modules that can be combined and their mounting positions, refer to Page 60, Section 3.3.2.
When the Q00UCPU, Q01UCPU, or Q02UCPU is used as CPU No.1, two more CPU modules (CPU No.2 and No.3) can
be mounted. The following CPU modules can be mounted as CPU No.2 and No.3.
CPU module
Model
Q172CPUN(-T), Q173CPUN(-T), Q172HCPU(-T), Q173HCPU(-T)
C Controller module
Q06CCPU-V, Q06CCPU-V-B, Q12DCCPU-V, Q24DHCCPU-V, Q24DHCCPU-LS
PC CPU module
PPC-CPU852(MS)-512
*3
*4
*5
*6
These modules and units can be used when a Universal model QCPU with a serial number (first five digits) of "13102" or
later is set as the control CPU of AnS/A series modules. These modules and units cannot be used in a multiple CPU
system containing a Process CPU (
Page 188, Appendix 3)
When the QA1S6B is used as an extension base unit, the QA6ADP+A5B/A6B cannot be connected.
Since the QA1S51B does not have an extension cable connector (OUT), it cannot be used with the QA6B or
QA6ADP+A5B/A6B.
When the QA1S6ADP+A1S5B/A1S6B is used, the maximum number of extension base units is 1, and the maximum
number of I/O modules that can be mounted is 20 minus the number of CPU modules. When the QA1S6ADPS1+A1S5B/A1S6B is used, the maximum number of extension base units is 3, and the maximum number of I/O
modules that can be mounted is 36 minus the number of CPU modules.
(b) Precautions
• If I/O modules are mounted exceeding the maximum number, "SP.UNIT LAY ERR" (error code: 2124)
occurs.
• "Number of CPU modules" indicates the number set in "No. of PLC" of PLC parameter ("Multiple CPU
Setting").
• When a C Controller module which occupies three slots is used, the maximum number of mountable I/O
modules will be two smaller than the number defined in the table on Page 56, Section 3.3.1 (2) (a).
• A PC CPU module occupies two slots. When this module is used, the maximum number of mountable I/O
modules will be one smaller than the number defined in the table on Page 56, Section 3.3.1 (2) (a).
57
3.3 System Using Universal Model QCPU as CPU No.1
3.3.1 Available CPU modules, base units, power supply modules, and extension cables
Motion CPU
(3) When a redundant power main base unit (Q3RB) is used
(a) Available modules, the number of extension base units, and the number of
mountable modules
Item
Description
Number of CPU
modules
4 CPU modules
Q00UCPU, Q01UCPU, Q02UCPU
The modules can be used as CPU No.1.*2
Q03UD(E)CPU, Q03UDVCPU,
Q04UD(E)HCPU, Q04UDVCPU,
Q06UD(E)HCPU, Q06UDVCPU,
Q10UD(E)HCPU, Q13UD(E)HCPU,
Q13UDVCPU, Q20UD(E)HCPU,
Q26UD(E)HCPU, Q26UDVCPU,
Q50UDEHCPU, Q100UDEHCPU
No function version restriction
High Performance model QCPU
Q02(H)CPU, Q06HCPU, Q12HCPU,
Q25HCPU
Function version B
Process CPU
Q02PHCPU, Q06PHCPU, Q12PHCPU,
Q25PHCPU
No function version restriction
Q24DHCCPU-V
Serial number (first five digits) of "14122" or later
when used with the QnUDVCPU
Q24DHCCPU-LS
No function version restriction
Universal model QCPU
Applicable CPU
module*1
C Controller module
Maximum number
of extension base
units
7 extension base units (when the Q00UCPU, Q01UCPU, or Q02UCPU is used: 4 extension base units)
Maximum number
of mountable I/O
modules
65 - (Number of CPU modules)
when the Q00UCPU or Q01UCPU is used: 25 - (Number of CPU modules), when the Q02UCPU is used: 37 - (Number of CPU modules)
Applicable main
base unit
Q38RB
Applicable
extension base
unit
Type requiring no power supply module
(Q series)
Q52B, Q55B
Redundant power extension base unit
Q68RB
Applicable
extension cable
QC05B, QC06B, QC12B, QC30B, QC50B, QC100B
Applicable power
supply module
*1
*2
Q63RP, Q64RP
(The Q63RP and Q64RP can be mounted on the same redundant power supply base unit.)
For the CPU modules that can be combined and their mounting positions, refer to Page 60, Section 3.3.2.
When the Q00UCPU, Q01UCPU, or Q02UCPU is used as CPU No.1, one more CPU module (CPU No.2) can be
mounted. The following CPU modules can be mounted as CPU No.2.
CPU module
C Controller module
Model
Q24DHCCPU-V, Q24DHCCPU-LS
(b) Precautions
• If I/O modules are mounted exceeding the maximum number, "SP.UNIT LAY ERR" (error code: 2124)
occurs.
• "Number of CPU modules" indicates the number set in "No. of PLC" of PLC parameter ("Multiple CPU
Setting").
• When a C Controller module which occupies three slots is used, the maximum number of mountable I/O
modules will be two smaller than the number defined in the table on Page 58, Section 3.3.1 (3) (a).
58
CHAPTER 3 SYSTEM CONFIGURATION
(4) When a slim type main base unit (Q3SB) is used
(a) Available modules, the number of extension base units, and the number of
mountable modules
Item
Description
Number of CPU
modules
Universal model QCPU
High Performance model QCPU
Q00UCPU, Q01UCPU, Q02UCPU
The modules can be used as CPU No.1.*2
Q03UD(E)CPU, Q03UDVCPU,
Q04UD(E)HCPU, Q04UDVCPU,
Q06UD(E)HCPU, Q06UDVCPU,
Q10UD(E)HCPU, Q13UD(E)HCPU,
Q13UDVCPU, Q20UD(E)HCPU,
Q26UD(E)HCPU, Q26UDVCPU,
Q50UDEHCPU, Q100UDEHCPU
No function version restriction
Q02(H)CPU, Q06HCPU, Q12HCPU,
Q25HCPU
Function version B
Applicable CPU
module
3
3 CPU modules
*1
Q06CCPU-V, Q06CCPU-V-B
C Controller module
Maximum number
of mountable I/O
modules
Extension not allowed
Q32SB
3 - (Number of CPU modules)
Q33SB
4 - (Number of CPU modules)
Q35SB
6 - (Number of CPU modules)
Applicable
extension cable
Q32SB, Q33SB, Q35SB
Applicable power
supply module
*1
*2
Q61SP
For the CPU modules that can be combined and their mounting positions, refer to Page 60, Section 3.3.2.
When the Q00UCPU, Q01UCPU, or Q02UCPU is used as CPU No.1, one more CPU module (CPU No.2) can be
mounted. The following CPU modules can be mounted as CPU No.2.
CPU module
C Controller module
Model
Q06CCPU-V, Q06CCPU-V-B, Q12DCCPU-V
(b) Precautions
• Slim type main base units do not have an extension cable connector. Therefore, no extension base unit or
GOT can be bus-connected.
• Four CPU modules cannot be mounted because the power consumption of the CPU modules exceeds the
rated output current of the power supply module (Q61SP).
• "Number of CPU modules" indicates the number set in "No. of PLC" of PLC parameter ("Multiple CPU
Setting").
59
3.3 System Using Universal Model QCPU as CPU No.1
3.3.1 Available CPU modules, base units, power supply modules, and extension cables
Serial number (first five digits) of "14122" or later
when used with the QnUDVCPU
Q12DCCPU-V
Maximum number
of extension base
units
• Serial number (first five digits) of "10102" or later
when used with the Q00UCPU, Q01UCPU, or
Q02UCPU
• Serial number (first five digits) of "10012" or later
when used with the Q03UDECPU,
Q04UDEHCPU, Q06UDEHCPU,
Q13UD(E)HCPU, or Q26UD(E)HCPU
• Serial number (first five digits) of "10102" or later
when used with the Q00UCPU, Q01UCPU,
Q02UCPU, Q10UD(E)HCPU, Q20UD(E)HCPU,
Q50UDEHCPU, or Q100UDEHCPU
• Cannot be used with the QnUDVCPU.
3.3.2
CPU module combinations and mounting positions
This section describes the combinations and mounting positions of CPU modules when a Universal model QCPU is
used as CPU No.1.
Note that the CPU modules that can be mounted differ depending on the main base unit used. (
Page 53, Section
3.3.1)
(1) Combinations
Number of CPU modules that can be mounted as CPU No.2 or others
CPU No.1
Q00UCPU,
Q01UCPU,
Q02UCPU
Universal model
QCPU other than
the above
*1
*2
*3
*4
*5
*6
60
Q06CCPU-V,
Q06CCPU-V-B,
Q12DCCPU-V,
Q24DHCCPU-V
Q24DHC
CPU-V,
Q24DHC
CPU-LS
PPC-CPU686
(MS)-64,
PPC-CPU686
(MS)-128
PPCCPU852
(MS)-512
Maximum
number of
mountable
modules
(including
CPU No.1)
Cannot be used
together.
0 to 1
0 to 1
Cannot be
used together.
0 to 1
3
0 to 3
0 to 3
0 to 1
Cannot be
used together.
0 to 1
4
High
Performance
model QCPU,
Process CPU,
Universal model
Q172CPUN(-T),
Q173CPUN(-T),
Q172HCPU(-T),
Q172DCPU(-S1),
Q173DCPU(-S1),
Q172DSCPU,
QCPU*2*5*6
Q173HCPU(-T)*3
Q173DSCPU*4
Cannot be used
together.
0 to 1
0 to 3
Cannot be used
together.
C Controller module*1*5
Motion CPU
PC CPU module*1*6
A C Controller module and a PC CPU module cannot be mounted on the same main base unit.
The Q00UCPU, Q01UCPU, and Q02UCPU can be used only as CPU No.1.
The module and a C Controller module (Q12DCCPU-V, Q24DHCCPU-V, Q24DHCCPU-LS) cannot be mounted on the
same main base unit.
When the Q172DCPU(-S1), Q173DCPU(-S1), Q172DSCPU, or Q173DSCPU is used, only the following CPU modules
can be mounted on the same main base unit.
• Universal model QCPU (except the Q00UCPU, Q01UCPU, and Q02UCPU)
A QnUDVCPU and a C Controller module (Q06CCPU-V or Q06CCPU-V-B) cannot be mounted on the same main base
unit.
A QnUDVCPU and a PC CPU module cannot be mounted on the same main base unit.
CHAPTER 3 SYSTEM CONFIGURATION
(2) Mounting positions
The following shows the possible combinations of mounting positions of CPU modules in a multiple CPU system.
• When the Q00UCPU, Q01UCPU, or Q02UCPU is used as CPU No.1
*1
CPU No.1
CPU No.2
CPU No.3
Q
M
C
Q
: QCPU*1
P
M
: Motion CPU
C
C
: C Controller module
P
P
: PC CPU module
3
The QCPU indicates the Q00UCPU, Q01UCPU, or Q02UCPU.
3.3 System Using Universal Model QCPU as CPU No.1
3.3.2 CPU module combinations and mounting positions
61
• When a CPU module other than the Q00UCPU, Q01UCPU, or Q02UCPU is used as CPU No.1
CPU No.1
CPU No.2
CPU No.3
CPU No.4
Q
Q
Q
*2
Q
M
C
P
*2
Q
M
M
C
P
C
C
P
*2
M
Q
*2
Q
M
C
P
*2
M
Q
M
C
P
C
Q
: QCPU*1
M
: Motion CPU
C
: C Controller module
P
: PC CPU module
C
P
C
P
*1
*2
62
C
C
The QCPU used as CPU No.1 indicates a Universal model QCPU (except the Q00UCPU, Q01UCPU, and Q02UCPU).
The QCPU used as CPU No.2 or later indicates a High Performance model QCPU, Process CPU, or Universal model
QCPU (except the Q00UCPU, Q01UCPU, and Q02UCPU).
The QCPU indicates a Universal model QCPU (except the Q00UCPU, Q01UCPU, and Q02UCPU).
CHAPTER 3 SYSTEM CONFIGURATION
(a) Universal model QCPU
Only one Q00UCPU, Q01UCPU, or Q02UCPU can be mounted in the CPU slot (the slot on the right of the
power supply module).
Up to four Universal model QCPUs other than the Q00UCPU, Q01UCPU, and Q02UCPU can be mounted in
the CPU slot (the slot on the right of the power supply module) to slot 2 of the main base unit.
(b) High Performance model QCPU or Process CPU
When the Q00UCPU, Q01UCPU, or Q02UCPU is used, no High Performance model QCPU or Process CPU
3
can be mounted.
When a Universal model QCPU other than the Q00UCPU, Q01UCPU, and Q02UCPU is used, up to three High
Performance QCPUs and/or Process CPUs can be mounted in slot 0 to slot 2 of the main base unit.
(c) Motion CPU
When the Q00UCPU, Q01UCPU, or Q02UCPU is used, only one Motion CPU can be mounted in slot 0 of the
main base unit.
When a Universal model QCPU other than the Q00UCPU, Q01UCPU, and Q02UCPU is used, up to three
Motion CPUs can be mounted in slot 0 to slot 2.
Only a Universal model QCPU, Motion CPU, C Controller module, or PC CPU module can be mounted on the
right of the Motion CPU.
(d) C Controller module
When the Q00UCPU, Q01UCPU, or Q02UCPU is used, only one C Controller module can be mounted on the
rightmost slot available for CPU modules.
When a Universal model QCPU other than the Q00UCPU, Q01UCPU, and Q02UCPU is used, up to three C
Controller modules can be mounted on the right of the following CPU modules. For a C Controller module
which occupies three slots, only one module can be mounted.
• Process CPU
• Universal model QCPU (except the Q00UCPU, Q01UCPU, and Q02UCPU)
• C Controller module
• Motion CPU (Q172DCPU(-S1), Q173DCPU(-S1), Q172DSCPU, or Q173DSCPU)
(e) PC CPU module
Only one PC CPU module can be mounted on the rightmost slot available for CPU modules. No CPU module
can be mounted on the right of the PC CPU module.
1
2
Slot number
Motion CPU
0
PC CPU
module
QCPU
Power supply
module
CPU
63
3.3 System Using Universal Model QCPU as CPU No.1
3.3.2 CPU module combinations and mounting positions
• High Performance model QCPU
(f) Empty slot setting
Empty slots can be reserved for future addition of CPU modules. Set the number of CPU modules including
empty slots in "No. of PLC" of PLC parameter ("Multiple CPU Setting"). Then, set "PLC (Empty)" to the type of
a target slot in PLC parameter ("I/O Assignment").
PLC (Empty)
Motion CPU
CPU
0
1
Slot number
2
Motion CPU
Universal model
QCPU
Slot number
Universal model
QCPU
2
Universal model
QCPU
1
Universal model
QCPU
0
Power supply
module
CPU
Universal model
QCPU
Power supply
module
Ex. Setting "PLC (Empty)" between CPU modules
Added Universal model QCPU
When a Universal model QCPU is used, "PLC (Empty)" can be set between CPU modules.
This is useful when adding a CPU module to the system in the future. No program modification is required because the CPU
number set as an empty slot can be assigned to the added CPU module.
Note, however, that when the following CPU module is used, "PLC (Empty)" cannot be set to the left of the CPU module.
• High Performance model QCPU
• Process CPU
To add a High Performance mode QCPU to the system where a C Controller module or PC CPU module is used, move the
C Controller module or PC CPU module to the right to allow addition of a CPU module.
Set "PLC (Empty)" to slot 2.
1
High Performance
model QCPU
2
3
4
Slot number
Input module
0
PC CPU
module
CPU
High Performance
model QCPU
Slot number
Universal model
QCPU
4
Move to the right.
High Performance
model QCPU
Add a CPU module.
3
Power supply
module
2
Input module
High Performance
model QCPU
1
(Empty)
0
PC CPU
module
CPU
Universal model
QCPU
Power supply
module
Keep slot 3 empty.
3.3.3
Available I/O modules and intelligent function modules
Refer to the system configuration using a a High Performance model QCPU or Process CPU as CPU No.1.
(
64
Page 51, Section 3.2.3)
CHAPTER 3 SYSTEM CONFIGURATION
3.4
Applicable Software
This section describes software packages applicable in a multiple CPU system.
(1) Applicable GX Works2, GX Developer, and PX Developer
The following table lists the applicable versions of GX Works2, GX Developer, and PX Developer.
QCPU
Basic model QCPU
High Performance model QCPU
Version
GX Works2
1.15R or later
Q02PHCPU,
Process CPU
Q06PHCPU
Q12PHCPU,
3
GX Developer
8.00A or later
6.00A or later
PX Developer
Use prohibited
8.68W or later
1.18U or later*1
7.10L or later
1.00A or later*1*2
8.76E or later
Use prohibited
8.48A or later
Use prohibited
8.76E or later
Use prohibited
8.62Q or later
Use prohibited
Use prohibited
Use prohibited
8.68W or later
Use prohibited
8.76E or later
Use prohibited
Use prohibited
Use prohibited
1.87R or later
Q25PHCPU
Q00UCPU, Q01UCPU
Q02UCPU,
Q03UDCPU,
Q04UDHCPU,
Q06UDHCPU
1.15R or later
Q10UDHCPU,
Q20UDHCPU
Q13UDHCPU,
Q26UDHCPU
Q03UDVCPU,
QCPU
Q04UDVCPU,
Q06UDVCPU,
1.98C or later
3.4 Applicable Software
Universal model
Q13UDVCPU,
Q26UDVCPU
Q03UDECPU,
Q04UDEHCPU,
Q06UDEHCPU,
Q13UDEHCPU,
1.15R or later
Q26UDEHCPU
Q10UDEHCPU,
Q20UDEHCPU
Q50UDEHCPU,
Q100UDEHCPU
*1
*2
1.31H or later
To use GX Works2 in combination with PX Developer, use GX Works2 version 1.98C or later.
To use GX Developer in combination with PX Developer, use GX Developer version 7.12N or later.
65
(2) Applicable GX Configurator
The following tables list the applicable versions of GX Configurator. Applicable GX Configurator versions differ
depending on the intelligent function module used. (
Manual for the intelligent function module used)
(a) When a Basic model QCPU, High Performance model QCPU, or Process CPU is
used
Version
Product
Basic model QCPU
High Performance model
QCPU
GX Configurator-AD
SW0D5C-QADU 20C or later
GX Configurator-DA
SW0D5C-QDAU 20C or later
GX Configurator-SC
SW0D5C-QSCU 20C or later
GX Configurator-CT
1.10L or later
SW0D5C-QCTU 20C or later
GX Configurator-TI
1.00A or later
GX Configurator-TC
SW0D5C-QCTU 00A or later
GX Configurator-FL
SW0D5C-QFLU 00A or later
Process CPU
1.13P or later
GX Configurator-QP
2.10L or later
2.00A or later
2.13P or later
GX Configurator-PT
1.10L or later
1.00A or later
1.13P or later
GX Configurator-MB
1.00A or later
1.00A or later
1.00A or later
GX Configurator-AS
1.13P or later
1.13P or later
1.13P or later
GX Configurator-DN
1.10L or later
1.00A or later
1.13P or later
GX Configurator-DP
7.00A or later
7.00A or later
7.00A or later*1
*1
66
To use GX Configurator with the Q02PH/Q06PHCPU, use the version 7.04E or later.
CHAPTER 3 SYSTEM CONFIGURATION
(b) When a Universal model QCPU is used
Version compatible with the Universal model QCPU
Product
Used with
Q02U/Q03UD/Q04UDH/
Q06UDHCPU
*1
GX Configurator-AD
2.05F or later
GX Configurator-DA
2.06G or later*1
GX Configurator-SC
2.12N or later*1
*1
Used with
Used with
Used with
Q03UDE/Q04UDEH/
Q00U/Q01U/Q10UDH/
Q13UDH/Q26UDHCPU
Q06UDEH/Q13UDEH/
Q20UDH/Q10UDEH/
Q26UDEHCPU
Q20UDEHCPU
*3
2.05F or later
2.05F or later*4
2.06G or later*2
2.06G or later*3
2.06G or later*4
2.12N or later*2
2.17T or later*3
2.17T or later*4
2.05F or later
*2
*2
*3
1.25AB or later*4
GX Configurator-CT
1.25AB or later
1.25AB or later
GX Configurator-TI
1.24AA or later*1
1.24AA or later*2
1.24AA or later*3
1.24AA or later*4
GX Configurator-TC
1.23Z or later*1
1.23Z or later*2
1.23Z or later*3
1.23Z or later*4
GX Configurator-FL
1.23Z or later*1
1.23Z or later*2
1.23Z or later*3
1.23Z or later*4
GX Configurator-QP
2.25B or later
2.29F or later
2.30G or later*5
2.32J or later
GX Configurator-PT
1.23Z or later*1
1.23Z or later*2
1.23Z or later*3
1.23Z or later*4
GX Configurator-MB
1.08J or later
*1
*2
1.08J or later
1.08J or later
*3
1.08J or later*4
GX Configurator-AS
1.21X or later*1
1.21X or later*2
1.21X or later*3
1.21X or later*4
GX Configurator-DN
1.23Z or later*1
1.23Z or later*2
1.24AA or later*3
1.24AA or later*4
GX Configurator-DP*6
7.02C or later*7
7.03D or later
7.03D or later
7.04E or later
The software can be used by installing GX Developer version 8.48A or later.
The software can be used by installing GX Developer version 8.62Q or later.
The software can be used by installing GX Developer version 8.68W or later.
The software can be used by installing GX Developer version 8.76E or later.
GX Configurator-QP version 2.29F can also be used when connected via USB.
To use GX Configurator with the Q50UDEH/Q100UDEHCPU, use the version 7.07H or later.
To use GX Configurator with the Q02UCPU, use the version 7.03D or later.
3.4 Applicable Software
*1
*2
*3
*4
*5
*6
*7
1.25AB or later
3
67
3.5
Precautions for System Configuration
This section describes restrictions and precautions on system configuration.
(1) Number of mountable modules
The number of mountable modules and supported functions are restricted depending on the CPU module used.
For the number of modules that can be connected to each Motion CPU, C Controller module, or PC CPU module,
refer to the manual for the CPU module used.
(a) When a Basic model QCPU is used
Product
Model
CC-Link IE Controller Network
• QJ71GP21-SX
module
• QJ71GP21S-SX
Maximum number of modules/units per system
Up to 4 modules (One
Q00CPU or Q01CPU can
control only one module.)
• QJ71LP21
• QJ71BR11
MELSECNET/H module
Up to 4 modules in total
Up to 4 modules (One
• QJ71LP21-25
Q00CPU or Q01CPU can
• QJ71LP21S-25
control only one module on
• QJ71LP21G
the PLC to PLC network.)
• QJ71LP21GE
• QJ71NT11B
• QJ71E71
Ethernet interface module
• QJ71E71-B2
Only 1 module (Controlled only by the QCPUs)
• QJ71E71-B5
• QJ71E71-100
CC-Link system master/local
• QJ61BT11
module
• QJ61BT11N
Interrupt module
• QI60
Up to 10 modules*1 (One QCPU can control only two
modules.)
• QX40H
Up to 3 modules*2 (One QCPU can control only one
High-speed input module
• QX70H
module.)
(Interrupt module)*4
• QX80H
• QX90H
High speed data logger module
High speed data
communication module
Only 1 module (Controlled by QCPUs or C Controller
• QD81DL96
modules)
Only 1 module (Controlled by QCPUs or C Controller
• QJ71DC96
modules)
*3
• GOT-A900 series (Bus connection only)
GOT
• GOT1000 series (Bus connection only)*3
*1
*2
*3
*4
68
Up to 5 units
Modules of function version B or later can be mounted.
The number indicates interrupt modules with no interrupt pointer setting. With interrupt pointer setting, no restriction
applies.
For the applicable GOT models, refer to the connection manual for the GOT used.
The number of mountable modules is restricted when a high-speed input module is used as an interrupt module by
turning off the function switch (SW2).
CHAPTER 3 SYSTEM CONFIGURATION
(b) When a High Performance model QCPU or Process CPU is used
Product
Model
CC-Link IE Controller Network
• QJ71GP21-SX
module*4
• QJ71GP21S-SX
Maximum number of modules/units per system
Up to 2 modules
• QJ71LP21
• QJ71BR11
Up to 4 modules in total
• QJ71LP21-25
MELSECNET/H module
• QJ71LP21S-25
3
Up to 4 modules
• QJ71LP21G
• QJ71LP21GE
• QJ71NT11B
• QJ71E71
Ethernet interface module
• QJ71E71-B2
Up to 4 modules
• QJ71E71-B5
• QJ71E71-100
CC-Link system master/local
• QJ61BT11
module
• QJ61BT11N
No restriction*1
• A1SJ71PT32-S3
No restriction (Auto refresh setting not allowed)
• A1SJ71T32-S3
• A1SD51S
• A1SD21-S1
AnS series
special function module
*2
• A1SJ71J92-S3
(When using GET/PUT service)
Up to 6 modules in total
• A1SJ71AP23Q
• A1SJ71AR23Q
• A1SJ71AT23BQ
• QI60
• QX40H
High-speed input module
• QX70H
(Interrupt module)*5
• QX80H
Up to 4 modules (Up to 3 modules when A1SI61 is used.
A QCPU can control only 1 module.)
• QX90H
Up to 4 modules (Controlled by QCPUs or C Controller
High speed data logger module
• QD81DL96
modules. A QCPU or C Controller module can control only
1 module.)
Up to 4 modules (Controlled by QCPUs or C Controller
High speed data
communication module
• QJ71DC96
1 module.)
• GOT-A900 Series (Bus connection only)
GOT
modules. A QCPU or C Controller module can control only
*3
• GOT1000 Series (Bus connection only)*3
*1
*2
*3
*4
*5
Up to 5 units
One CPU module can control the following number of modules by setting CC-Link network parameters.
• CPU module with a serial number (first five digits) of "08031" or earlier: Up to 4 modules
• CPU module with a serial number (first five digits) of "08032" or later: Up to 8 modules
There is no restriction on the number of mounted modules when the parameters are set with the CC-Link dedicated
instructions.
The module can be used only when a High Performance model QCPU is set to a control module. However, it cannot be
used if a Process CPU is used in combination. (
Page 188, Appendix 3)
For the applicable GOT models, refer to the connection manual for the GOT used.
The module can be used with the following CPU modules.
• High Performance model QCPU with a serial number (first five digits) of "09012" or later
• Process CPU with a serial number (first five digits) of "10042" or later
The number of mountable modules is restricted when a high-speed input module is used as an interrupt module by
turning off the function switch (SW2).
69
3.5 Precautions for System Configuration
Only 1 module
• A1SI61*2
Interrupt module
Remark
For the restrictions on mounting A-series modules on the QA6B or QA6ADP+A5B/A6B, refer to the following.
QA65B/QA68B Extension Base Unit User's Manual
QA6ADP QA Conversion Adapter Module User's Manual
For the restrictions on mounting AnS-series modules on the QA1S6ADP+A1S5B/A1S6B, refer to the following.
QA1S6ADP Q-AnS Base Unit Conversion Adapter User's Manual
QA1S6ADP-S1 Q-AnS Base Unit Conversion Adapter User's Manual
70
CHAPTER 3 SYSTEM CONFIGURATION
(c) When a Universal model QCPU is used
Product
Model
CC-Link IE Controller Network
• QJ71GP21-SX
module*4
• QJ71GP21S-SX
Maximum number of modules/units per system
Up to 4 modules in total
• QJ71LP21
• QJ71BR11
• QJ71LP21-25
MELSECNET/H module
• QJ71LP21S-25
• QJ71LP21G
• QJ71LP21GE
With the Q00UCPU, Q01UCPU, or Q02UCPU, the
maximum number of connectable modules is as follows:
3
• Q02UCPU: Up to 2 modules in total
• Q00UCPU or Q01UCPU: Only 1 module
• QJ71NT11B
CC-Link IE Field Network
module
No restriction*6
• QJ71GF11-T2
Up to 4 modules
• QJ71E71
Ethernet interface module
• QJ71E71-B2
With the Q00UCPU, Q01UCPU, or Q02UCPU, the
• QJ71E71-B5
maximum number of connectable modules is as follows:
• QJ71E71-100
• Q02UCPU: Up to 2 modules
• Q00UCPU or Q01UCPU: Only 1 module
CC-Link system master/local
• QJ61BT11
module
• QJ61BT11N
• A1SJ71PT32-S3
• A1SJ71T32-S3
No restriction*1*5
No restriction (Auto refresh setting not allowed)
• A1SD51S
• A1SD21-S1
AnS series
special function module*8
• A1SJ71J92-S3
Up to 6 modules in total
• A1SJ71AR23Q
• A1SJ71AT23BQ
• A1SI61*8
Interrupt module
Only 1 module
• QI60
• QX40H
High-speed input module
*7
(Interrupt module)
Up to 4 modules*3
• QX70H
• QX80H
• QX90H
High speed data logger
module*9
High speed data
communication module
GOT
Up to 4 modules (Controlled by QCPUs or C Controller
• QD81DL96
modules. A QCPU or C Controller module can control only
1 module.)
Up to 4 modules (Controlled by QCPUs or C Controller
• QJ71DC96
modules. A QCPU or C Controller module can control only
1 module.)
• GOT1000 Series (for bus connection
only)*2
Up to 5 units
71
3.5 Precautions for System Configuration
(When using GET/PUT service)
• A1SJ71AP23Q
*1
*2
*3
*4
*5
*6
*7
*8
*9
One CPU module can control the following number of modules by setting CC-Link network parameters.
• Q00UCPU or Q01UCPU: Up to 2 modules
• Q02UCPU: Up to 4 modules
• Other CPU modules: Up to 8 modules
There is no restriction on the number of mounted modules when the parameters are set with the CC-Link dedicated
instructions.
For the applicable GOT models, refer to the connection manual for the GOT used.
The number indicates interrupt modules with no interrupt pointer setting. With interrupt pointer setting, no restriction
applies.
When one of the following CPU modules is used in the multiple CPU system, the number of modules can be mounted is
restricted to two.
• High Performance model QCPU
• Process CPU
Modules of function version B or later can be mounted.
One CPU module can control the following number of modules by setting CC-Link IE Field Network parameters using a
programming tool.
• Q00UCPU or Q01UCPU: Up to 2 modules
• Q02UCPU: Up to 4 modules
• Other CPU modules: Up to 8 modules
There is no restriction on the number of mounted modules when the parameters are set with the CC-Link IE Field
Network dedicated instructions.
The number of mountable modules is restricted when a high-speed input module is used as an interrupt module by
turning off the function switch (SW2).
The module can be used when a Universal model QCPU with a serial number (first five digits) of "13102" or later is set to
a control module. However, it cannot be used if a process CPU is used in combination. (
Page 188, Appendix 3)
With a High-speed Universal model QCPU, only high-speed data logger modules with a serial number (first five digits)
"14122" or later can be used.
Remark
For the restrictions on mounting A-series modules on the QA6B or QA6ADP+A5B/A6B, refer to the following.
QA65B/QA68B Extension Base Unit User's Manual
QA6ADP QA Conversion Adapter Module User's Manual
For the restrictions on mounting AnS-series modules on the QA1S6ADP+A1S5B/A1S6B, refer to the following.
QA1S6ADP Q-AnS Base Unit Conversion Adapter User's Manual
QA1S6ADP-S1 Q-AnS Base Unit Conversion Adapter User's Manual
72
CHAPTER 3 SYSTEM CONFIGURATION
(2) Modules that have restrictions when used with an Universal model QCPU
For modules that have restrictions when used with an Universal model QCPU, refer to the following manual.
QnUCPU User's Manual (Function Explanation, Program Fundamentals)
(3) Combinations of power supply modules, base units, and QCPUs
There are some restrictions on combinations of power supply modules, base units, and QCPUs. (
QCPU
User's Manual (Hardware Design, Maintenance and Inspection)
3
Ex. Redundant power supply modules can be mounted only on redundant power main base units or
redundant power extension base units.
(4) Precautions for using a QCPU of function version A
If a QCPU of function version A is used in a multiple CPU system, an error occurs. To configure a multiple CPU
system with QCPUs, use CPU modules of function version B or later.
CPU No.1
Other than CPU No.1
QCPU (function version A)
QCPU (function version A)
QCPU (function version A)
QCPU (function version B)
QCPU (function version B)
QCPU (function version A)
Error in CPU No.1
Error in other than CPU
No.1
"UNIT VERIFY ERROR"
"SP.UNIT LAY ERROR"
(error code: 2000)
(error code: 2125)
"UNIT VERIFY ERROR"
"MULTI EXE.ERROR"
(error code: 2000)
(error code: 7010)
"MULTI EXE.ERROR"
"SP.UNIT LAY ERROR"
(error code: 7010)
(error code: 2125)
A High Performance model QCPU and High-speed Universal model QCPU support the high-speed interrupt
function.
If the parameter with the high-speed interrupt fixed scan interval setting is written, the functions of the CPU
module are partly restricted. The restrictions differ depending on the CPU module used. (
User's Manual
(Function Explanation, Program Fundamentals) for the CPU module used)
Note that the above restrictions do not apply to the High Performance model QCPU with a serial number (first five
digits) of "04011" or earlier because the module ignores the high-speed interrupt fixed scan interval setting.
(6) Precautions for using a Motion CPU (Q172DCPU(-S1), Q173DCPU(-S1),
Q172DSCPU, or Q173DSCPU)
The Q172DCPU(-S1), Q173DCPU(-S1), Q172DSCPU, or Q173DSCPU can only be mounted on a multiple CPU
high-speed main base unit.
Note that do not mount any Motion modules controlled by the Motion CPU in slot 0 to 2 of the multiple CPU highspeed main base unit.
73
3.5 Precautions for System Configuration
(5) Precautions for using the high-speed interrupt function
(7) Precautions for connecting a GOT
The following GOT series can be used.
• GOT-A900 series*1
• GOT-F900 series (The Q-mode compatible operating system and communication driver must be installed.)*1
• GOT1000 series
The GOT800 series, A77GOT, and A64GOT cannot be used.
*1
74
Universal model QCPUs do not support the GOT-A900 and GOT-F900 series.
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM
CHAPTER 4
STARTING UP MULTIPLE CPU
SYSTEM
This chapter describes the procedure for starting up a multiple CPU system.
4.1
Procedure Before Operation
4
Check box
Determine the role of each CPU module.
Determine the role (controls and functions) of each CPU module used in
a multiple CPU system.
Study details of device assignment.
Study details of device assignment. To perform auto refresh of the CPU
shared memory, the refresh range must be set consecutively.
Select modules.
Page 116, CHAPTER 6
4.1 Procedure Before Operation
Page 31, CHAPTER 3
Select modules to be used in a multiple CPU system.
Mount the modules.
Page 31, CHAPTER 3
Mount the selected modules on a main base unit and extension base
unit(s).
Power on the system.
Set the RUN/STOP switch of the CPU No.1 to the STOP position, and
power on the system.
To the next page
75
Connect to a programming tool.
Connect the CPU No.1 and a personal computer where a programming
tool has been installed.*1
Write data to the CPU modules.
Write programs and parameters to the CPU modules. To write data to the
CPU No.2 and later, select the target CPU module in the Transfer Setup
window of the programming tool.
Page 112, Section 5.3
Run all the CPU modules.
Set the RUN/STOP switch of all the CPU modules to the RUN position.
Reset the CPU No.1.
Reset the entire system by resetting the CPU No.1. Set the RUN/STOP
switch of the CPU No.1 to the RUN position again, and check whether no
error occurs in any CPU module in the system.*2
Debug the system.
Debug the program of each CPU module individually.
*1
*2
When a PC CPU module is used, the QCPU can be bus-connected to a programming tool by installing the programming
tool in the PC CPU module. Select "Q Series Bus" for the "PC side I/F" setting in the "Transfer Setup" window using the
programming tool.
If an error has occurred, check the error cause using the programming tool and take corrective action.
An error in the CPU modules can be checked in the "PLC Diagnostics" window.
An error in the I/O modules and intelligent function modules can be checked in the "System Monitor" window.
(
76
QCPU User's Manual (Hardware Design, Maintenance and Inspection))
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM
4.2
Operation Settings
This section describes the settings required to operate a multiple CPU system. A system where three Universal model
QCPUs are mounted shall be used as an example.
(1) Parameters required
(a) Basic model QCPU, High Performance model QCPU, and Process CPU
Settings of parameters in double-lined squares, except some parameters, must be the same in all the CPU
modules used in a multiple CPU system. (
Multiple CPU Setting
Page 172, Appendix 1.1)
4
No. of PLC
Operation Mode
Online Module Change*1
I/O Sharing When Using Multiple CPUs
Change Screens
Refresh Setting
CPU Specific Send Range
PLC Side Device
I/O Assignment
Detailed Setting:
Basic Setting
Slots
Control PLC
4.2 Operation Settings
PLC System
I/O Assignment
Points Occupied by Empty Slot
: Setting required
: Same setting required for all CPU modules
: Individual setting allowed for each CPU module
*1
For Basic model QCPUs, the online module change setting is not available.
High Performance model QCPUs do not support the online change function, but the setting is required to replace
modules controlled by the Process CPU on the same base unit online.
77
(b) Universal model QCPU
Settings of parameters in double-lined squares, except some parameters, must be the same in all the CPU
modules used in a multiple CPU system. (
Multiple CPU Setting
Page 172, Appendix 1.1)
No. of PLC
Host Station
Operation Mode
Multiple CPU Synchronous Startup Setting
Online Module Change*1
I/O Sharing When Using Multiple CPUs
Multiple CPU High Speed Transmission
Area Setting
Use Multiple CPU High Speed
Transmission
CPU Specific Send Range
Auto Refresh
Points
Start
Advanced Setting
Refresh Setting
System Area
CPU Specific Send Range
PLC Side Device
I/O Assignment
PLC System
I/O Assignment
Detailed Setting:
Basic Setting
Slots
Control PLC
Points Occupied by Empty Slot
: Setting required
: Same setting required for all CPU modules
: Individual setting allowed for each CPU module
*1
78
Universal model QCPUs do not support the online change function, but the setting is required to replace modules
controlled by the Process CPU on the same base unit online.
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM
4.2.1
System configuration example
This section describes the procedure for setting parameters required in a multiple CPU system, using the following
system as an example.
4
5
6
7
Input module
Output module
Input module
Output module
Intelligent function module
1
1
2
2
2
2
3
9
10
3
3
3
11
12
13
14
15
4
Slot number
Control CPU setting
Slot number
Control CPU setting
4.2 Operation Settings
4.2.1 System configuration example
8
Intelligent function module
1
Output module
Universal model QCPU
3
Universal model QCPU
2
Universal model QCPU
1
Input module
Power supply module
Power supply module
CPU 0
PLC (Empty)
Personal computer (Programming tool)
79
4.2.2
Parameter settings
This section describes parameters required for the system configuration on Page 79, Section 4.2.1. Use a
programming tool to set parameters.
• Settings of parameters in double-lined squares on Page 77, Section 4.2 (1) must be the same in all the CPU
modules in a multiple CPU system.
• The necessity of parameters differs depending on the QCPU used. (
Page 77, Section 4.2 (1))
(1) Setting parameters (for the first time)
1.
Set "Points Occupied by Empty Slot" in the "PLC System" window of PLC parameter.
Project window
[Parameter]
[PLC Parameter]
[PLC System]
"Points Occupied by
Empty Slot"
Item
Description
Points Occupied by Empty Slot
2.
Set the number of points occupied by one empty slot.
Default
16 points
Set parameters for the multiple CPU system in the "Multiple CPU Setting" window of PLC
parameter.
Project window
80
[Parameter]
[PLC Parameter]
[Multiple CPU Setting]
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM
Item
Description
Default
Set the number of CPU modules mounted on the main base unit in the
multiple CPU system. The number of modules differs depending on the CPU
No. of PLC
module used as CPU No.1 and the main base unit used. (
Page 31,
1
CHAPTER 3)
This parameter must be set.
Set this parameter to check the host CPU number in the multiple CPU system.
If this parameter is set, each CPU module checks its own CPU number with
the one set in this parameter to see if they match.
Host CPU number setting
The CPU module checks
if the CPU numbers match.
4
The CPU module checks
if the CPU numbers match.
CPU
CPU
No.1 CPU No.2 No.3
Host Station
No Specification
CPU numbers are determined by their mounting positions.
• When "No Specification" is selected, the host CPU number is not checked.
• Host CPU numbers do not need to be set to all the CPU modules in the
system.
• To set the same "Multiple CPU Setting" parameters to all the CPU modules
used in the multiple CPU system, select "No Specification". Parameter
4.2 Operation Settings
4.2.2 Parameter settings
settings are shared by all the CPU modules used in the system.
The host CPU number can be checked when one of the following CPU
modules is used.
• Universal model QCPU (except the Q00UCPU, Q01UCPU, and Q02UCPU)
• Motion CPU (Q172DCPU(-S1), Q173DCPU(-S1), Q172DSCPU, or
Q173DSCPU)
• C Controller module (Q12DCCPU-V, Q24DHCCPU-V, or Q24DHCCPU-LS)
Select whether to stop or continue the operation of all the CPU modules when
a stop error occurs in a CPU module. Set this parameter to continue the
operation of other error-free CPU modules if a stop error occurs in a CPU
module other than CPU No.1.
Operation Mode
For example, if the "All station stop by stop error of PLC2" checkbox is
All items selected
unchecked, other CPU modules continue their operation even after a stop
error occurs in CPU No.2.
The operation mode of CPU No.1 cannot be changed. (
Page 102,
Section 4.6)
Set this parameter to enable synchronous startup of the CPU modules in the
multiple CPU system. (
Page 168, Section 6.5)
Only Universal model QCPUs support this parameter.
Multiple CPU Synchronous
Uncheck the checkbox of the corresponding CPU number if any of the
Startup Setting
following CPU modules is used.
All items selected
• High Performance model QCPU
• Process CPU
• C Controller module (Q06CCPU-V or Q06CCPU-V-B)
• PC CPU module
81
Item
Description
(1)
Default
Basic model QCPU
This parameter is not supported.
(2)
Process CPU
Check the checkbox to enable online module change.
Online Module Change
(3)
Not selected
High Performance model QCPU and Universal model QCPU
Check the checkbox if online module change is enabled with a Process
CPU. Modules controlled by a High Performance model QCPU or
Universal model QCPU cannot be replaced online.
Set this parameter to read the input (X) and output (Y) data from the I/O
I/O Sharing When Using
modules and intelligent function modules controlled by other CPU modules.
• Loading input (X) data:
Multiple CPUs
• Loading output (Y) data:
Page 105, Section 5.2.1
Not selected
Page 107, Section 5.2.2
Set this parameter to enable automatic data communications between the
CPU modules in the system using the multiple CPU high speed transmission
area of the CPU shared memory.
Multiple CPU High Speed
Transmission Area Setting
"Use Multiple CPU High
Only Universal model QCPUs support this parameter.
Speed Transmission"
Note that some conditions must be met on the main base units and CPU
checkbox: Selected
modules to be used. (
Page 135, Section 6.1.2)
If the conditions cannot be satisfied, use "Communication Area Setting
(Refresh Setting)".
Communication Area Setting
(Refresh Setting)
Set this parameter to enable automatic data communications between the
CPU modules in the system using the automatic refresh area of the CPU
shared memory. (
-
Page 122, Section 6.1.1)
Match "No. of PLC" with the number of CPU modules actually mounted. If the numbers do not match, an error will occur.
82
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM
3.
Set the types and points for the mounted modules in the "I/O Assignment" window of PLC
parameter.
Project window
[Parameter]
[PLC Parameter]
[I/O Assignment]
4
Item
Description
Default
Select the type of a mounted module.
To reserve an empty slot for the future addition of a CPU module, select
"PLC (Empty)".
The slots where "PLC (Empty)" can be set differ depending on the CPU
module used as CPU No.1.
• When a Basic model QCPU is used as CPU No.1
-
4.2 Operation Settings
4.2.2 Parameter settings
Type
Page 38, Section 3.1.2 (2) (d)
• When a High Performance model QCPU or Process CPU is used as CPU
No.1
Page 50, Section 3.2.2 (2) (f)
• When a Universal model QCPU is used as CPU No.1
Page 64, Section 3.3.2 (2) (f)
Enter the model name of a mounted module.
Model Name
This is a memo in the programming tool and does not affect the operation of
Blank
CPU modules.
Points
Set the number of I/O points for each module.
Blank
83
4.
Click the
button in the "I/O Assignment" window, and set a control CPU for each I/O
module and intelligent function module.
Item
Description
Set the CPU module that controls each I/O module and intelligent function
Control PLC
module mounted.
5.
6.
PLC No.1
Set other parameters required.
Save the project using the programming tool so that the multiple CPU system parameter settings
can be used in other CPU modules.
[Project]
84
Default
[Save As]
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM
(2) Using the multiple CPU system parameters set to another CPU module
1.
Click the
button in the "Multiple CPU Setting" window of PLC parameter.
Select and open the project file from which the settings will be imported.
Project window
[Parameter]
[PLC Parameter]
[Multiple CPU Setting]
4
The settings of a project file created with a different programming tool cannot be used. Reuse such settings as follows.
[Project]
[Open Other Data]
[Open Other Project]
• To import the settings of a project file created with GX Works2 to GX Developer, save the GX Works2 project in
the GX Developer format by using [Export to GX Developer Format File] function.
[Project]
[Export to GX Developer Format File]
2.
The following window appears. Click the
3.
Check the settings in the "Multiple CPU Setting" window of PLC parameter.
button.
To change the auto refresh setting devices, click the
button and set new device ranges.
(Settings of parameters with "(*1)" must be the same in all the CPU modules in the system.)
85
4.2 Operation Settings
4.2.2 Parameter settings
• To import the settings of a project file created with GX Developer to GX Works2, open the GX Developer project in
GX Works2 by using the [Open Other Project] function.
4.
Check the "Points Occupied by Empty Slot" setting in the "PLC System" window of PLC
parameter.
Project window
[Parameter]
[PLC parameter]
[PLC System]
"Points Occupied by
Empty slots"
5.
Check the settings in the "I/O Assignment" window of PLC parameter.
Project window
[PLC parameter]
6.
Click the
7.
Set other parameters required.
8.
Save the project using the programming tool.
[Project]
86
[Parameter]
[I/O Assignment]
button in the "I/O Assignment" window and check the "Control PLC" setting.
[Save As]
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM
4.3
Program Examples for Communications by Auto
Refresh
4.3.1
Program examples for Basic model QCPU, High Performance
model QCPU, and Process CPU
This section provides program examples for communicating data by auto refresh between the CPU modules in the
following system.
4
Personal computer (Programming tool)
3
6
Y50 to Y5F
16
16
16
16
16
16
1
1
1
1
2
2
2
7
Slot number
A/D D/A Input Output
X40 to X4F
Output
5
X/Y30 to X/Y3F
Input
4
X/Y20 to X/Y2F
1
2
Y10 to Y1F
Point assigned
to each slot
1
X0 to XF
High Performance
model QCPU
High Performance
model QCPU
Power supply module
CPU 0
Control CPU setting
(1) Parameter settings
4.3 Program Examples for Communications by Auto Refresh
4.3.1 Program examples for Basic model QCPU, High Performance model QCPU, and Process CPU
(a) I/O assignment
Assign I/O points to the mounted modules. (
Project window
[Parameter]
Page 27, Section 2.2)
[PLC Parameter]
[I/O Assignment]
87
(b) Auto refresh setting
Set auto refresh parameters. (
Project window
Page 123, Section 6.1.1 (2))
[Parameter]
Area Setting (Refresh Setting)"
88
[PLC Parameter]
[Multiple CPU Setting]
"Communication
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM
(2) Program examples
(a) Sending bit data and word data from CPU No.1 to CPU No.2
• Devices used in CPU modules
Device used in CPU No.1
M0
D0 and D1
Send data from CPU No.1 to CPU No.2
Device used in CPU No.2
M0
D0 and D1
D100
-
Send data from CPU No.1 to CPU No.2
Storage device for data received from CPU
No.1
YE0
Data reception flag (for data from CPU No.1)
SM400
Always ON
4
• Program example of CPU No.1
CPU No.1
send data (bit)
Send
command
CPU No.1
send data (word)
• Program example of CPU No.2
SM400
Always ON
CPU No.1
send data
(word)
4.3 Program Examples for Communications by Auto Refresh
4.3.1 Program examples for Basic model QCPU, High Performance model QCPU, and Process CPU
CPU No.2
receive data
(bit)
CPU No.1
send data (bit)
CPU No.2
receive data
(word)
89
(b) Continuously sending data from CPU No.1 to CPU No.2
• Devices used in CPU modules
Device used in CPU No.1
M40
Send data from CPU No.2 to CPU No.1
D10 to
D18
D81 to
D88
SM400
Send data from CPU No.1 to CPU No.2
Storage device of send data to CPU No.2
Device used in CPU No.2
M40
D10 to
D18
Send data from CPU No.2 to CPU No.1
Send data from CPU No.1 to CPU No.2
D121 to
Storage device for data received from CPU
D128
No.1
Always ON
-
For handshake between CPU No.1 and No.2, refer to Page 132, Section 6.1.1 (3).
• Program example of CPU No.1
SM400
Always
ON
Send start data
CPU No.1
send flag
Send end data
Send start
data
CPU No.1
send data
CPU No.1
send flag
CPU No.1
send flag
CPU No.2
receive
complete flag
• Program example of CPU No.2
CPU No.1
send flag
CPU No.1
send data
CPU No.2
receive data
CPU No.2
receive
complete flag
90
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM
(c) Continuously reading/writing data between CPU No.1 and No.2 using the user
setting area
Data can be read/write between CPU modules by programs using the user setting area in the CPU shared
memory.
The same number of points must be set for CPU No.1 and CPU No.2 in the auto refresh setting.
4
Consequently, the user setting area will be a range from 0822H to 0FFFH. (
Page 118, Section 6.1)
CPU shared memory
0000H
to
01FFH
0200H
to
07FFH
0800H
Host CPU operation
information area
System area
Auto refresh area
CPU No.1 memory
0800H
CPU No.2 memory
0800H
D0 to D31
D32 to D63
to
User setting area
0FFFH
081FH
0820H
081FH
0820H
M0 to M31
M32 to M63
0821H
0822H
0821H
0822H
0850H
0850H
0881H
0881H
0FFFH
0FFFH
91
4.3 Program Examples for Communications by Auto Refresh
4.3.1 Program examples for Basic model QCPU, High Performance model QCPU, and Process CPU
The auto refresh area occupies the memory addresses 0800H to 0821H, the area set by setting 1 and setting 2.
• Devices used in CPU modules
Device used in CPU No.1
M31
Send data from CPU No.1 to CPU No.2
M63
D100 to
D149
Device used in CPU No.2
M31
Send data from CPU No.1 to CPU No.2
Send data from CPU No.2 to CPU No.1
M63
Send data from CPU No.2 to CPU No.1
Storage device for data received from CPU
D200 to
No.2
D249
-
Storage device of send data to CPU No.1
M100
Write completion bit of the S.TO instruction
SM400
Always ON
• Program example of CPU No.2
SM400
Write start
data
Always
ON
Write end
data
Write
complete bit
Write start
data
Write complete bit
CPU No.2
write flag
CPU No.1 read
complete flag
CPU No.2
write flag
• Program example of CPU No.1
CPU No.2
write flag
Read
start data
CPU No.1
read
complete flag
92
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM
4.3.2
Program examples for Universal model QCPU
This section provides program examples for communicating data by auto refresh (using the multiple CPU high speed
transmission area) between the CPU modules in the following system.
Personal computer (Programming tool)
3
6
Y50 to Y5F
16
16
16
16
16
16
1
1
1
1
2
2
2
7
Slot number
4
A/D D/A Input Output
X40 to X4F
Output
5
X/Y30 to X/Y3F
Input
4
X/Y20 to X/Y2F
1
2
Y10 to Y1F
Point assigned
to each slot
1
X0 to XF
Universal model QCPU
Universal model QCPU
Power supply module
CPU 0
Control CPU setting
(1) Parameter settings
(a) I/O assignment
Assign I/O points to the mounted modules. (
Project window
[Parameter]
Page 27, Section 2.2)
[PLC Parameter]
[I/O Assignment]
4.3 Program Examples for Communications by Auto Refresh
4.3.2 Program examples for Universal model QCPU
93
(b) Auto refresh setting
Set auto refresh parameters. (
Project window
Page 138, Section 6.1.2 (3))
[Parameter]
[PLC Parameter]
[Multiple CPU Setting]
High Speed Transmission Area Setting"
Setting of CPU No.1
94
Setting of CPU No.2
"Multiple CPU
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM
(2) Program examples
(a) Sending bit data and word data from CPU No.1 to CPU No.2
• Devices used in CPU modules
Device used in CPU No.1
M0
D0 and D1
Send data from CPU No.1 to CPU No.2
Device used in CPU No.2
M0
D0 and D1
D100
-
Send data from CPU No.1 to CPU No.2
Storage device for data received from CPU
No.1
YE0
Data reception flag (for data from CPU No.1)
SM400
Always ON
4
• Program example of CPU No.1
CPU No.1
send data
(bit)
Send
command
CPU No.1
send data
(word)
• Program example of CPU No.2
SM400
CPU No.2
receive data
(bit)
CPU No.1
send data
(bit)
CPU No.1
send data
(word)
4.3 Program Examples for Communications by Auto Refresh
4.3.2 Program examples for Universal model QCPU
Always
ON
CPU No.2
receive data
(word)
95
(b) Continuously sending data from CPU No.1 to CPU No.2
• Devices used in CPU modules
Device used in CPU No.1
M40
Send data from CPU No.2 to CPU No.1
D10 to
D18
D81 to
D88
SM400
Send data from CPU No.1 to CPU No.2
Storage device of send data to CPU No.2
Device used in CPU No.2
M40
D10 to
D18
Send data from CPU No.2 to CPU No.1
Send data from CPU No.1 to CPU No.2
D121 to
Storage device for data received from CPU
D128
No.1
Always ON
-
For handshake between CPU No.1 and No.2, refer to Page 148, Section 6.1.2 (5).
• Program example of CPU No.1
SM400
Always
ON
Send start
data
CPU No.1
send flag
Send end
data
Send start
data
CPU No.1
send data
CPU No.1
send flag
CPU No.1
send flag
CPU No.2
receive
complete flag
• Program example of CPU No.2
CPU No.1
send flag
CPU No.1
send data
CPU No.2
receive data
CPU No.2
receive
complete flag
96
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM
(c) Continuously reading/writing data between CPU No.1 and CPU No.2 using the user
setting area in the multiple CPU high speed transmission area
Data can be read/write between CPU modules using the user setting area in the CPU shared memory.
The same number of points must be set for CPU No.1 and CPU No.2 in the auto refresh setting.
Setting of CPU No.1
Setting of CPU No.2
4
The user setting area will be 3E0\G10000 and later for CPU No.1 and 3E1\G10000 and later for CPU No.2.
CPU shared memory
4.3 Program Examples for Communications by Auto Refresh
4.3.2 Program examples for Universal model QCPU
Host CPU operation
information area
System area
Auto refresh area
Use-prohibited area
CPU No.1 memory
CPU No.2 memory
3E0\G10000
3E0\G10000
Multiple CPU high
speed transmission area
to
User setting area
User setting area
CPU No.1
send area
3E0\G17133
CPU No.1
receive area
3E0\G17133
Auto refresh area
Auto refresh area
3E1\G10000
to
3E1\G10000
User setting area
User setting area
CPU No.2
receive area
3E1\G17133
Auto refresh area
CPU No.2
send area
3E0\G17133
Auto refresh area
97
• Devices used in CPU modules
Device used in CPU No.1
M31
Send data from CPU No.1 to CPU No.2
M63
D100 to
D149
Device used in CPU No.2
M31
Send data from CPU No.1 to CPU No.2
Send data from CPU No.2 to CPU No.1
M63
Send data from CPU No.2 to CPU No.1
Storage device for data received from CPU
D200 to
No.2
D249
-
SM400
Storage device of send data to CPU No.1
Always ON
• Program example of CPU No.2
Always
ON
Write
head data
CPU No.2
write flag
Write
final data
Write
head data
CPU No.2
write flag
CPU No.1 read
completed
CPU No.2
write flag
• Program example of CPU No.1
CPU No.2
write flag
Read
head data
CPU No.1
read
completed
98
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM
4.4
Clock Data
This section describes clock data of CPU modules and intelligent function modules.
4.4.1
Clock data of CPU modules
Set clock data to CPU No.1 in the multiple CPU system using the programming tool.
[Online]
[Set Clock]
4
The clock data settings for CPU No.2 to No.4 differ depending on the CPU module used.
CPU module
Setting of CPU No.2 to No.4
• Universal model QCPU
Clock data do not need to be set. The clock data of CPU No.1 is
• Motion CPU (Q172DCPU(-S1), Q173DCPU(-S1), Q172DSCPU, or
automatically set to CPU No.2 to No.4.
Q173DSCPU)
Even if clock data is set individually to CPU No.2 to No.4, the
• C Controller module (Q12DCCPU-V, Q24DHCCPU-V, or
Q24DHCCPU-LS)
setting is ignored and the clock data of CPU No.1 is
automatically set.
Set clock data individually to CPU No.2 to No.4.
Other than above
The clock data of CPU No.1 is not automatically set to CPU No.2
to No.4.
● To automatically set the clock data of CPU No.1 to a C Controller module, perform the following operation.
• When the Q12DCCPU-V is used
Enable the clock synchronization function using C Controller setting utility. (The function is disabled by default.)
C Controller setting utility [Online Operation]
"C Controller Module Detail Setting"
"Clock"
"Clock
Synchronization Function"
• When the Q24DHCCPU-V or Q24DHCCPU-LS is used
Clock data do not need to be set. The clock data of CPU No.1 is automatically set.
● If there is an error of three seconds or more between the clock data of the C Controller module (Q12DCCPU-V,
Q24DHCCPU-V, or Q24DHCCPU-LS) and the clock data received from CPU No.1, the C Controller module synchronizes
the clock data.
Remark
CPU No.1 sends clock data to other CPU modules at the following timing.
• When the multiple CPU system is powered on
• When the RUN/STOP switch of CPU No.1 is switched from STOP to RUN
• At intervals of one second after the multiple CPU system starts up
The clock data includes year, month, day, day of the week, hour, minute, and second information.
Since CPU No.1 sets the clock data at intervals of one second, an error of one second (maximum) may occur in clock data
of CPU modules other than CPU No.1.
99
4.4 Clock Data
4.4.1 Clock data of CPU modules
● Clock data can also be set by the following methods.
• By a program
• By executing the time setting function (SNTP client) (Only Built-in Ethernet port QCPUs support this function.)
4.4.2
Clock data of intelligent function modules
When an error has occurred, some intelligent function modules store the code and time (clock data read from the
QCPU) corresponding to the error into the buffer memory. Those modules store the clock data of CPU No.1 as the
error time regardless of whether the modules are controlled by CPU No.1 or not.
100
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM
4.5
Resetting a Multiple CPU System
In a multiple CPU system, resetting the QCPU used as CPU No.1 resets all the modules (CPU modules, I/O modules,
and intelligent function modules) in the system.
(1) If a stop error exists any of the CPU modules in the multiple CPU system
Reset CPU No.1 or power off and on the multiple CPU system. The system cannot be restored by resetting any
CPU module other than CPU No.1.
CPU
0
1
2
3
4
5
6
7
1
2
3
4
1
1
2
3
4
3
4
4
Slot number
Control CPU setting
If a CPU module other than CPU No.1
is reset in the multiple CPU system,
"MULTI CPU DOWN" occurs.
CPU No.1 resets the entire multiple CPU system.
101
4.5 Resetting a Multiple CPU System
● Do not individually reset the CPU modules other than CPU No.1 in the multiple CPU system.
If reset, "MULTI CPU DOWN" (error code: 7000) will occur and the entire multiple CPU system stops.
• Depending on the timing in which any of CPU modules other than CPU No.1 is reset, an error other than "MULTI
CPU DOWN" (error code: 7000) may occur, causing the other CPU modules to stop.
• If any of CPU modules other than CPU No.1 is reset, "MULTI CPU DOWN" (error code: 7000) will occur
regardless of the "Operation Mode" setting in PLC parameter ("Multiple CPU Setting").
4.6
System Operation When a Stop Error Occurs
The multiple CPU system operation differs depending on the CPU module where a stop error has occurred.
(1) When a stop error has occurred in CPU No.1
"MULTI CPU DOWN" (error code: 7000) occurs in all the other CPU modules and the operation of the multiple
CPU system stops.
(2) When a stop error has occurred in a CPU module other than CPU No.1
The operating status of the system (whether to stop the entire system or not) depends on the "Operation Mode"
setting in PLC parameter ("Multiple CPU Setting").
Parameters are set by default so that the operations of all the CPU modules stop.
To continue operations, uncheck the "All station stop by stop error of PLC 'n'" checkbox of the corresponding
CPU module.
Operation Mode
All Station stop by stop error of PLC 'n':
Operations of all the other CPU modules
stop when an error occurs in CPU No. n.
All Station stop by stop error of PLC 'n':
Operations of all the other CPU modules
continue even if an error occurs in CPU No. n.
(a) When the "All station stop by stop error of CPU 'n'" checkbox is checked
If a stop error occurs in the CPU module for which "All station stop by stop error of PLC 'n'" has been set,
"MULTI CPU DOWN" (error code: 7000) occurs in all the other CPU modules and the operation of the multiple
CPU system stops.
(b) When the "All station stop by stop error of CPU 'n'" checkbox is not checked
If a stop error occurs in the CPU module for which "All station stop by stop error of PLC 'n'" has not been set,
"MULTI EXE. ERROR" (error code: 7020) occurs in all the other CPU modules, but the operation of the multiple
CPU system continues.
However, if a major error occurs in the CPU module 'n', "MULTI CPU DOWN" (error code: 7000) occurs in all
the other CPU modules and the operation of the multiple CPU system stops regardless of the PLC parameter
setting.
102
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM
If a stop error occurs, "MULTI CPU DOWN" (error code: 7000) will occur in the CPU module where the stop error has been
detected. Depending on the timing of error detection, "MULTI CPU DOWN" may be detected in another CPU module due to
secondary-occurred "MULTI CPU DOWN".
For example, if a stop error occurs in CPU No.2, the operation of CPU No.3 stops. Depending on the timing of error
detection, the operation of CPU No.1 may stop due to the stop error of CPU No.3, not the error of CPU No.2.
1) The CPU module stops due to "OPERATION ERROR".
CPU
0
1
2
3
4
Slot number
4
2
1
3
1
2
3
Control CPU setting
2) The CPU module stops due to a stop error in CPU
No.2. ("MULTI CPU DOWN" occurs.)
3) The CPU module may stop due to a stop error in CPU No.3
depending on the timing of error detection.
("MULTI CPU DOWN" occurs.)
Because of this, CPU No. different from the one of the first error CPU module may be stored in the common error information
field. To restore the system, eliminate the error cause of the CPU module that has been stopped by an error other than
"MULTI CPU DOWN".
In the following example, the error cause (other than "MULTI CPU DOWN") of CPU No.2 shall be eliminated.
4.6 System Operation When a Stop Error Occurs
Eliminate this error cause.
(3) System restoration procedure
The following is the procedure for restoring the system.
1.
Check the error CPU No. and error cause in the "PLC diagnostics" window using the programming
tool.
2.
3.
Eliminate the error cause.
Reset CPU No.1 or power off and on the system.
All the CPU modules in the multiple CPU system are reset and the system is restored.
103
CHAPTER 5
ACCESS BETWEEN CPU MODULES
AND OTHER MODULES
This chapter describes the access between CPU modules and other modules (I/O modules and intelligent function
modules).
5.1
Access to Controlled Modules
In a multiple CPU system, CPU modules access I/O modules and intelligent function modules in the same way as in a
single CPU system. (CPU modules refresh input (X) and output (Y) data, and read/write data from/to the buffer
memory of intelligent function modules.)
5.2
Access to Non-controlled Modules
Access to non-controlled modules is restricted as shown below.
: Accessible ×: Inaccessible
"I/O Sharing When Using Multiple CPUs" in PLC parameter
Access target
Disabled (not checked)
Input (X)
Output (Y)
Enabled (checked)
×
Read
×
Write
×
×
×
×
Buffer memory of an intelligent
Read
function module
Write
● The on/off data of the I/O modules, I/O combined modules, and intelligent function modules controlled by other CPU
modules can be used as an interlock of the host CPU module or to check the status of output to external devices
controlled by other CPU modules.
● The on/off status of input (X) and output (Y) can be read by setting "I/O Sharing When Using Multiple CPUs" in PLC
parameter. (The on/off status cannot be written to the devices.)
● Data in the buffer memory of intelligent function modules can be read regardless of the "I/O Sharing When Using Multiple
CPUs" setting. (The data cannot be written to the buffer memory.)
104
CHAPTER 5 ACCESS BETWEEN CPU MODULES AND OTHER MODULES
5.2.1
Loading input (X) data
Data in the input (X) of input modules and intelligent function modules controlled by other CPU modules can be loaded
in accordance with the "I/O Sharing When Using Multiple CPUs" setting in PLC parameter ("Multiple CPU Setting").
I/O Sharing When Using Multiple CPUs
All CPUs Can Read All Inputs:
Input data can be loaded from the modules
controlled by other CPU modules.
All CPUs Can Read All Inputs:
Input data cannot be loaded from the modules
controlled by other CPU modules.
5
(1) When the "All CPUs Can Read All Inputs" checkbox is checked
The on/off data of input modules and intelligent function modules controlled by other CPU modules can be
loaded. The on/off data are loaded during input refresh processing before the program operation starts.
The on/off data can also be loaded by using the direct access input (DX).
DX20
On/off data
can loaded
by input refresh.
CPU
0
1
2
5.2 Access to Non-controlled Modules
5.2.1 Loading input (X) data
X20
On/off data can
loaded by the
direct access input.
3
4
Slot number
2
Y10 to Y1F
X20 to X2F
Y30 to Y3F
Point assigned
to each slot
X0 to XF
Input Output Input Output
16
16
16
16
2
2
Control CPU setting
On/off data can be loaded from modules controlled
by another control CPU.
105
(a) Modules that can load input (X) data
Data in the input (X) can be loaded from the following modules mounted on the main base unit or extension
base unit.
Module type set
Mounted module
in PLC parameter ("I/O Assignment")
Input module
High-speed input module
Blank
I/O combined module*1
Intelligent function module
Input module
Input
High speed input module
Hi, Input
Output module*2
I/O Mix
I/O combined module*1
Intelligent
*1
Intelligent function module
When input (X) of the QX48Y57 (I/O combined module) is targeted, data in Xn8 to XnF (output part) are loaded as all
points off.
Xn0
Input (X) data (on/off) are loaded
as is.
Xn7
Yn8(Xn8)
Input (X) data (on/off) are loaded
as all points off.
YnE(XnE)
(XnF)
QCPU
QX48Y57
*2
When input (X) of an output module is targeted, data are loaded as all points off.
(b) Modules that cannot load input (X) data
Input data of empty slots and MELSECNET/H or CC-Link network remote stations controlled by other CPU
modules cannot be loaded. To use the input data (on/off data) in a CPU module other than the control CPU,
perform auto refresh using the CPU shared memory. (
Page 118, Section 6.1)
If the input data loaded from other CPU modules are forcibly turned on/off in the host CPU module, the data will be set into
the specified forced on/off status. (
used)
User's Manual (Function Explanation, Program Fundamentals) for the CPU module
(2) When the "All CPUs Can Read All Inputs" checkbox is not checked
The on/off data of input modules and intelligent function modules controlled by other CPU modules cannot be
loaded. Data in the input (X) remain at off.
106
CHAPTER 5 ACCESS BETWEEN CPU MODULES AND OTHER MODULES
5.2.2
Loading output (Y) data
Data in the output (Y) of output modules and intelligent function modules controlled by other CPU modules can be
loaded in accordance with the "I/O Sharing When Using Multiple CPUs" setting in PLC parameter ("Multiple CPU
Setting").
I/O Sharing When Using Multiple CPUs
All CPUs Can Read All Outputs:
Output data can be loaded from the modules
controlled by other CPU modules.
All CPUs Can Read All Outputs:
Output data cannot be loaded from the modules
controlled by other CPU modules.
5
(1) When the "All CPUs Can Read All Outputs" checkbox is checked
The on/off data of output modules and intelligent function modules controlled by other CPU modules can be
loaded to the output (Y) of the host CPU module.
Y30
5.2 Access to Non-controlled Modules
5.2.2 Loading output (Y) data
On/off data can loaded
by output refresh.
CPU
0
1
2
3
4
Slot number
2
Y10 to Y1F
X20 to X2F
Y30 to Y3F
Point assigned
to each slot
X0 to XF
Input Output Input Output
16
16
16
16
2
2
Control CPU setting
On/off data can be loaded from modules controlled
by another control CPU.
107
(a) Modules that can load output (Y) data
Data in the output (Y) can be loaded from the following modules mounted on the main base unit or extension
base unit.
Module type set
Mounted module
in PLC parameter ("I/O Assignment")
Output module
Blank
I/O combined module
Intelligent function module
Input module
Output
Output module
I/O Mix
I/O combined module
Intelligent
Intelligent function module
(b) Modules that cannot load output (Y) data
Output data of empty slots and MELSECNET/H or CC-Link network remote stations controlled by other CPU
modules cannot be loaded. To use the output data in a CPU module other than the control CPU, perform auto
refresh using the CPU shared memory and send the output data of remote stations from the control CPU to
other CPU modules. (
Page 118, Section 6.1)
If the output loaded from other CPU modules is forcibly turned on/off in the host CPU module, the data will be set into the
specified forced on/off status. (
used)
User's Manual (Function Explanation, Program Fundamentals) for the CPU module
(2) When the "All CPUs Can Read All Outputs" checkbox is not checked
The on/off data of output modules and intelligent function modules controlled by other CPU modules cannot be
loaded. Data in the output (Y) remain at off.
108
CHAPTER 5 ACCESS BETWEEN CPU MODULES AND OTHER MODULES
5.2.3
Output to output modules and intelligent function modules
The on/off data cannot be output to non-controlled modules.
If the output status of the output module or intelligent function module controlled by other CPU modules is turned on/off
by the program, the corresponding output status changes only within the CPU module. (The on/off data is not output to
the corresponding output module or intelligent function module.)
X0
Y30
X0
Y10
On/off data
can be output.
CPU
0
1
2
3
4
On/off data cannot
be output.
Slot number
5
2
Y10 to Y1F
X20 to X2F
Y30 to Y3F
Point assigned
to each slot
X0 to XF
Input Output Input Output
16
16
16
16
2
2
Control CPU setting
5.2 Access to Non-controlled Modules
5.2.3 Output to output modules and intelligent function modules
109
5.2.4
Access to the intelligent function module buffer memory
Data in the buffer memory of intelligent function modules controlled by other CPU modules can be read regardless of
the "I/O Sharing When Using Multiple CPUs" setting in PLC parameter ("Multiple CPU Setting").
(1) Reading data from the buffer memory
Data can be read from the buffer memory of intelligent function modules controlled by other CPU modules in the
same way as in a single CPU system.
Intelligent function module
CPU
0
1
2
3
4
5
6
7
Slot number
1
2
1
1
1
1
2
2
2
Control CPU setting
Data can be read from the buffer memory.
(2) Writing data to the buffer memory
Data cannot be written to the buffer memory of intelligent function modules.
If data is written to the buffer memory of an intelligent function module controlled by another CPU module,
"SP.UNIT ERROR" (error code: 2116) occurs.
Intelligent function module
CPU
0
1
2
3
4
5
6
7
Slot number
1
2
1
1
1
1
2
2
2
Control CPU setting
Data cannot be written to
the buffer memory.
Data cannot be written to the buffer memory.
110
CHAPTER 5 ACCESS BETWEEN CPU MODULES AND OTHER MODULES
5.2.5
Access using the link direct device
Only the control CPU can execute instructions using the link direct device to access I/O modules and intelligent
function modules.
The link direct device cannot be used to access modules controlled by other CPU modules. If an instruction using the
link direct device is executed to access a module controlled by another CPU module , "OPERATION ERROR" (error
code: 4102) occurs.
Network module
CPU
0
1
2
3
4
Slot number
5
1
2
1
1
1
2
Control CPU setting
Accessible
Not accessible ("OPERATION ERROR" occurs.)
5.2 Access to Non-controlled Modules
5.2.5 Access using the link direct device
111
5.3
Access From a Programming Tool
This section describes access from a programming tool to modules in a multiple CPU system.
(1) Access to QCPUs
A programming tool can read/write parameters and programs from/to the QCPU connected as well as monitor
and test the entire system. To access another QCPU via the QCPU connected, specify the target CPU No. in
"Multiple CPU Setting" on the "Transfer Setup" window.
(a) When the target CPU module is not specified
CPU
0
1
2
3
4
Slot number
1
2
1
1
2
2
Control CPU setting
A programming tool accesses CPU No.1.
(b) When the target CPU module is specified
CPU
0
1
2
1
2
3
4
Slot number
CPU number
A programming tool
communicates
with CPU No.2.
Specify "PLC No.2".
112
CHAPTER 5 ACCESS BETWEEN CPU MODULES AND OTHER MODULES
(2) Access to controlled and non-controlled modules
A programming tool can access modules both controlled and not controlled by the QCPU connected.
The programming tool connected to one QCPU can access all the modules controlled by any QCPU in the
multiple CPU system.
The programming tool can also access QCPUs on other stations in the same network such as CC-Link IE,
MELSECNET/H, or Ethernet.
CPU
0
1
2
3
4
Slot number
5
1
2
1
1
2
2
Control CPU setting
A programming tool can access all modules in the system.
5.3 Access From a Programming Tool
113
(3) Access from the programming tool connected to another station
The programming tool connected to another station in the same network can access all the QCPUs in the
multiple CPU system.
Ex. Over MELSECNET/H PLC to PLC network
Station No. 2 (normal station)
Station No. 3 (normal station)
Control CPU
setting
MELSECNET/H PLC to PLC network
Station No. 1(control station)
Control CPU
setting
114
CHAPTER 5 ACCESS BETWEEN CPU MODULES AND OTHER MODULES
5.4
Accessible QCPUs when GOT is connected
For the connected GOT, QCPUs that can be accessed differ depending on the connection method. (
Manual for
the GOT used)
5
5.4 Accessible QCPUs when GOT is connected
115
CHAPTER 6
COMMUNICATIONS AMONG CPU
MODULES
This chapter describes data communications among CPU modules in a multiple CPU system.
(1) Communication methods
The following table lists the communication methods available among CPU modules.
Item
Description
Communications using the CPU shared
Data communications is performed among CPU modules using
memory
the internal memory of each CPU module.
Auto refresh
(using the auto refresh area)
Data communications is automatically performed among CPU
Auto refresh
modules in accordance with the settings in the programming
(using the multiple CPU high-speed
tool.
Reference
Page 118, Section 6.1
Page 122, Section 6.1.1
Page 135, Section 6.1.2
transmission area)
By programs
Data communications is performed among CPU modules by
executing programs.
Communications by motion dedicated
Data communications is performed between a QCPU and a
instructions
Motion CPU by executing motion dedicated instructions.
Communications among CPU modules by
Data communications is performed among CPU modules by
dedicated instructions
executing dedicated instructions.
Reading/writing device data between
Device data are read/written between a QCPU and a Motion
QCPU and Motion CPU
CPU.
Starting an interrupt program from
QCPU to C Controller module/PC
CPU module
An interrupt program is started from a QCPU to a C Controller
module/PC CPU module.
Reading/writing device data between
Device data are read/written between Universal model QCPUs
QCPUs
(except the Q00UCPU, Q01UCPU, and Q02UCPU).
116
Page 150, Section 6.1.3
Page 160, Section 6.2
–
Page 162, Section 6.3.1
Page 164, Section 6.3.2
Page 165, Section 6.3.3
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
(2) Communications among CPU modules
Communications availability differs depending on the CPU modules used as the communication source and
target.
: Communications available ×: Communications not available
Communications using the
Communicationsource CPU
CPU shared memory
Communication-target CPU module
module
Auto refresh
Motion CPU
Basic model QCPU
High Performance
model QCPU,
Process CPU
Program
PC CPU module
×
High Performance model QCPU,
Process CPU,
Universal model QCPU
×
Motion CPU
among CPU
modules by
dedicated
instructions
6
×
Q172CPUN(-T),
Q173CPUN(-T),
Q172HCPU(-T),
Q173HCPU(-T)
×
×
Motion CPU
Q172CPUN(-T),
Q173CPUN(-T),
Q172HCPU(-T),
Q173HCPU(-T)
C Controller module
Q06CCPU-V,
Q06CCPU-V-B,
Q12DCCPU-V,
Q24DHCCPU-V,
Q24DHCCPU-LS
×
PC CPU module
×
High Performance model QCPU, Process
CPU
×
Universal model QCPU
×
Motion CPU
Q172DCPU(-S1),
Q173DCPU(-S1),
Q172DSCPU,
Q173DSCPU
C Controller module
Q06CCPU-V,
Q06CCPU-V-B,
Q12DCCPU-V,
Q24DHCCPU-V,
Q24DHCCPU-LS
×
×
×
Page 135,
Section 6.1.2,
Page 150,
Section 6.1.3
*1
instructions*1
×
PC CPU module
Reference
dedicated
C Controller module
PC CPU module
Universal model
QCPU (Except the
Q00UCPU,
Q01UCPU, and
Q02UCPU)
by motion
Communications
Q172CPUN(-T),
Q173CPUN(-T),
Q172HCPU(-T),
Q173HCPU(-T)
C Controller module
Universal model
QCPU
(Q00UCPU,
Q01UCPU,
Q02UCPU)
Communications
Page 159,
Section 6.1.4
Page 160, Section
6.2
There are restrictions on available instructions depending on the version of the Motion CPU used. (
Motion CPU used)
Page 162, Section
6.3
Manual for the
117
6.1
Communications Using the CPU Shared Memory
This section describes data communications among CPU modules in a multiple CPU system using the CPU shared
memory.
(1) CPU shared memory
The CPU shared memory is a data storage area in a CPU module and used to read/write data among CPU
modules in a multiple CPU system.
The CPU shared memory consists of the areas listed below.
Area
Description
Host CPU operation information area
System area
An area used to store error information and LED status of the CPU
Page 119, Section 6.1 (2),
module
Page 121, Section 6.1 (3)
An area used by the operating system of the CPU module
An area used to communicate data by auto refresh.
Auto refresh area
Reference
This area starts from the next address of the last address in the
system area.
–
Page 119, Section 6.1 (2),
Page 122, Section 6.1.1
An area used to communicate data by a program.
User setting area
This area is assigned to the later addresses of those used for the
Page 119, Section 6.1 (2),
auto refresh area. If auto refresh is not performed, the area starts
Page 150, Section 6.1.3
from the next address of the last address in the system area.
Multiple CPU high speed
transmission area
An area to communicate data with other CPU modules in the
multiple CPU system using Universal model QCPUs (except the
Page 119, Section 6.1 (2)
Q00UCPU, Q01UCPU, and Q02UCPU)
An area used to communicate data by a program.
User setting area
This area is assigned to the address 10000H and later of the CPU
Page 150, Section 6.1.3
shared memory.
Auto refresh area
An area used to communicate data by auto refresh
Page 135, Section 6.1.2
Use of the multiple CPU high speed transmission area enables high-speed transmission by reducing the increase in scan
time. Some conditions apply to using the area.
• Data communications by auto refresh:
• Data communications by programs:
118
Page 135, Section 6.1.2
Page 150, Section 6.1.3
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
(2) CPU shared memory configuration and availability of data communications by
programs
The following shows the CPU shared memory configuration and the availability of data communications by
programs using the CPU shared memory.
• Basic model QCPU
Host CPU
CPU shared memory
(0H)
to
(5FH)
(60H)
to
(BFH)
(C0H)
0
to
95
96
to
191
192
to
to
Write
Read
Other CPUs
Write
Read
Host CPU operation
information area
System area
*1
Auto refresh area
6
User setting area
(1FFH) 511
: Communications available,
*1
: Communications not available
The system area is used to communicate data using motion dedicated instructions. For applications and uses of the
system area, refer to the programming manual for the Motion CPU used.
• High Performance model QCPU and Process CPU
Host CPU
CPU shared memory
0
to
511
512
to
to
(7FFH) 2047
(800H) 2048
to
Write
Read
Write
Read
Host CPU operation
information area
*1
System area
Auto refresh area
to
User setting area
(FFFH) 4095
: Communications available,
*1
: Communications not available
The system area is used to communicate data using motion dedicated instructions. For applications and uses of the
system area, refer to the programming manual for the Motion CPU used.
119
6.1 Communications Using the CPU Shared Memory
(0H)
to
(1FFH)
(200H)
Other CPUs
• Universal model QCPU
Host CPU
CPU shared memory
(0H)
to
(1FFH)
(200H)
G0
to
G511
G512
to
(7FFH)
(800H)
to
G2047
G2048
to
to
Write
Other CPU
Read
Write
Read
Host CPU operation
information area
System area
Auto refresh area
User setting area
(FFFH) G4095
(1000H) G4096
to
to
(270FH) G9999
(2710H) G10000
to
to
Max.
(5F0FH) G24335
Use-prohibited area*1
Multiple CPU high speed
transmission area*1
: Communications available,
*1
120
: Communications not available
The Q00UCPU, Q01UCPU, and Q02UCPU do not have the use-prohibited area and the multiple CPU high speed
transmission area.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
(3) Host CPU operation information area
(a) Information stored
The following information about the host CPU module is stored in this area.*1
In a single CPU system, all the values are set to 0.
Shared
memory
Name
Description*2
Meaning
address
Corresponding
special register
This is an area to check whether information is stored in the
0H
Information
Information
existence
existence flag
host CPU operation information area (1H to 1FH).
• 0: Information not stored
–
• 1: Information stored
1H
Diagnostic error
Diagnostic error
The error code of an error detected by the diagnostics is
code
stored in binary.
SD0
The year and month when the error code was stored in the
2H
CPU shared memory (address: 1H) are stored in 2-digit
6
SD1
BCD.
3H
Clock time for
Clock time for
The day and hour when the error code was stored in the
diagnosis error
diagnosis error
CPU shared memory (address: 1H) are stored in 2-digit
occurrence
occurrence
BCD.
SD2
The minute and second when the error code was stored in
4H
the CPU shared memory (address: 1H) are stored in 2-digit
SD3
BCD.
5H
to
10H
11H
to
1BH
Error information
category code
category code
Error common
Error common
The common information corresponding to the error code is
information
information
stored.
Error individual
Error individual
The individual information corresponding to the error code
information
information
is stored.
1CH
Not used
1DH
Switch status
1EH
LED status
1FH
common information or error individual information) is
–
Switch status of a
CPU module
LED status of a
CPU module
CPU operating
Operating status of
status
a CPU module
SD4
stored.
SD5
to
SD15
SD16
to
SD26
Use prohibited
–
The switch status of the CPU module is stored.
SD200
The LED status of the CPU module is stored.
SD201
The operating status of the CPU module is stored.
SD203
*1
Motion CPUs do not use the areas 5H to 1CH.
*2
For details, refer to the description of the corresponding special register areas in the User's Manual (Hardware Design,
Maintenance and Inspection) for the CPU module used.
If data in the areas 5H to 1CH are read from a Motion CPU, the data will be read as "0".
(b) Reading data
Other QCPUs in the multiple CPU system can read data in the host CPU operation information area by
executing the FROM instruction or the instructions using the cyclic transmission area device (U3En\G).
Use the read data for monitoring purposes only because there is a delay in updating data.
121
6.1 Communications Using the CPU Shared Memory
6H
A category code indicating an error information type (error
Error information
6.1.1
Communications by auto refresh (using the auto refresh area)
This section describes data communications by auto refresh using the auto refresh area in the CPU shared memory.
Data communications by auto refresh can also be performed using the auto refresh area in the multiple CPU high speed
transmission area. Use of the multiple CPU high speed transmission area can reduce the increase in scan time. Some
conditions apply to using the area. (
Page 135, Section 6.1.2)
(1) Communications by auto refresh
(a) Overview
Auto refresh communicates data using the auto refresh area in the CPU shared memory. Data are
automatically read/written among all the CPU modules in the multiple CPU system by setting "Communication
Area Setting (Refresh Setting)" in PLC parameter ("Multiple CPU Setting").
Since auto refresh automatically reads device data in other CPU modules, the host CPU module can use those
device data.
Auto refresh increases the scan time in the multiple CPU system. (
Page 192, Appendix 4)
Ex. Operations when CPU No.1 performs auto refresh of data in B0 to B1F (32 points) and CPU No.2
performs auto refresh of data in B20 to B3F (32 points)
CPU No.1
CPU No.2
CPU shared memory
CPU shared memory
Host CPU operation information area
Host CPU operation information area
System area
System area
Auto refresh area
3) Data are read during
END processing of
CPU No.2.
User setting area
User setting area
2) Data are written during
END processing of
CPU No.2.
1) Data are written during END
processing of CPU No.1.
Device
B0 to B1F (for CPU No.1)
B20 to B3F (for CPU No.2)
Auto refresh area
Device
4) Data are read during
END processing of
CPU No.1.
B0 to B1F (for CPU No.1)
B20 to B3F (for CPU No.2)
• Processing performed during END processing of CPU No.1
1) CPU No.1 transfers the device data (B0 to B1F) to the auto refresh area in its own CPU shared memory.
4) CPU No.1 reads the data in the auto refresh area of the CPU No.2’s CPU shared memory and stores
them in B20 to B3F of its own.
• Processing performed during END processing of CPU No.2
2) CPU No.2 transfers the device data (B20 to B3F) to the auto refresh area in its own CPU shared
memory.
3) CPU No.2 reads the data in the auto refresh area of the CPU No.1’s CPU shared memory and stores
them in B0 to B1F of its own.
122
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
(b) Executing auto refresh
Auto refresh is executed when the CPU modules are in RUN, STOP, or PAUSE status. Auto refresh cannot be
executed when a stop error has occurred in any of the CPU modules.
If a stop error occurs in a CPU module, the other modules will hold the data prior to the stop error. In the figure
on Page 122, Section 6.1.1 (1) (a), for example, if the status of B20 is on when a stop error occurs in CPU
No.2, the B20 in CPU No.1 will remain on.
(2) Auto refresh settings
To communicate data by auto refresh, set the ranges (number of points) to be sent by each CPU module ("CPU
Specific Send Range") and the devices for storing data ("PLC Side Device") in PLC parameter ("Multiple CPU
Setting").
Project window
[Parameter]
[PLC Parameter]
[Multiple CPU Setting]
"Communication
Area Setting (Refresh Setting)"
6
Switch the auto refresh range
settings.
Set the send ranges for each
CPU module.
Set the auto refresh device range
setting method.
Set the device ranges of each
CPU module. (Each module uses
the ranges corresponding to the
points set for the module from the
specified start device number.)
Uncheck the
checkbox.
123
6.1 Communications Using the CPU Shared Memory
6.1.1 Communications by auto refresh (using the auto refresh area)
In the following cases, uncheck the "Use Multiple CPU High Speed Transmission" checkbox in the "Multiple High Speed
Transmission Area setting" area set for the Universal model QCPU.
• A High Performance model QCPU or Process CPU is used as CPU No.1.
• The "Use Multiple CPU High Speed Transmission" checkbox is unchecked for the Universal model QCPU used as
CPU No.1.
• A main base unit, slim type main base unit, or redundant power main base unit is used.
(a) "Change Screens"
Up to four auto refresh ranges can be set. Set and switch the ranges in this parameter. With different settings,
on/off data in bit devices and other data in word devices can be auto-refreshed separately.
(b) "CPU Specific Send Range"
Set the number of points in the CPU shared memory in increments of two points (two words). (If a bit device is
specified in "PLC Side Device", two points equal to 32 points.)
If the number of points is set to "0", the data of the corresponding CPU module is not refreshed.
The following number of send points can be set for each CPU module.
QCPU
Number of send points
• Basic model QCPU: 320 words
Basic model QCPU
• Motion CPU, C Controller module, PC CPU module: 2048 words
• All CPU modules in total: 4416 points (4416 words)
High Performance model QCPU,
Process CPU,
Universal model QCPU
• Total of four ranges per CPU module: Up to 2K words
• All CPU modules in total: 8K points (8K words)
Set the same number of send points for all the CPU modules in the multiple CPU system. If not, "PARAMETER ERROR" will
be detected in the consistency check.
124
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
Ex. To refresh data in B0 to B1F (32 points) of CPU No.1 and B20 to B3F (32 points) of CPU No.2, set "2" in
"Points" because the link relay (B) is a bit device.
When the number of points in
the CPU shared memory is
set to "2" and a bit device is
specified for "PLC Side
Device", 32 points of data
can be refreshed.
Since the number of points for CPU No.3 and No.4 is set to "0", data are
not refreshed.
[Auto refresh processing]
CPU No.1
CPU No.2
Device
Device
B0
to
B1F
B20
to
B3F
6
B0
to
B1F
B20
to
B3F
The auto refresh area in the CPU shared memory occupies a total points set for Setting 1 to 4.
When the number of send points is set, the corresponding start and end addresses of the auto refresh area are
Ex. For the CPU module having two auto refresh area settings (Setting 1 and 2), the end address of the auto
refresh area will be the one "start address of the auto refresh area + offset value of Setting 2". In the
following example, CPU No.1 and No.2 use the area from the start address of the auto refresh area to
0011H, and CPU No.4 uses the area from the start address of the auto refresh area to 0021H.
For the CPU module having only one auto refresh area setting (Setting 1), the end address of the auto
refresh area will be the one set in Setting 1. In the following example, CPU No.3 uses only the area set in
Setting 1.
Send range of
CPU No.1
End addresses of
the devices in each
CPU module
End addresses of the CPU shared memory in each CPU module
125
6.1 Communications Using the CPU Shared Memory
6.1.1 Communications by auto refresh (using the auto refresh area)
automatically displayed in hexadecimal offset values.
(c) "PLC Side Device"
Set auto refresh target devices. The following devices can be set.
Device
Restriction
Data register (D),
Link register (W),
–
File register (R, ZR)
Link relay (B),
Internal relay (M),
Specify 0 or multiples of 16 for the start number.
Output (Y)
There are two auto refresh device range setting methods.*1
• Setting device ranges sequentially from the start device number of CPU No.1
• Setting device ranges for each CPU module freely
*1
Auto refresh devices of the following QCPUs can only be set sequentially from the start device of CPU No.1.
• Basic model QCPU
• High Performance model QCPU with a serial number (first five digits) of "07031" or earlier
• Process CPU
In addition, when GX Developer version 8.22Y or earlier is used, auto refresh devices shall only be set sequentially from
the start device of CPU No.1.
Set Starting Devices for each PLC:
Device ranges are set for each CPU
module freely.
Set Starting Devices for each PLC:
Device ranges are set sequentially from
the start device number of CPU No.1.
Each CPU module uses the device ranges corresponding to the points set for the module from the specified
start device number as the auto refresh target ranges. Set device numbers so that the necessary amount of
send points can be secured.
126
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
• Different devices can be set for Setting 1 to 4.
The same device can also be set as long as the device ranges for Setting 1 to 4 are not overlapped.
Setting 1: The link relay (B) is specified.
Different devices can be set for
Setting 1 to 4.
Setting 2: The link register (W) is specified.
The same device can also be set for
Setting 1 to 4. Make sure the device
ranges are not overlapped. In the
setting example here, since the link
relay ranges B0 to B9F (160 points)
are used for Setting 1, set the link
relay ranges BA0 and later for
Setting 3.
Setting 3: The link relay (B) is specified.
6
6.1 Communications Using the CPU Shared Memory
6.1.1 Communications by auto refresh (using the auto refresh area)
The start and end addresses are automatically calculated by the programming tool.
[Auto refresh processing]
CPU No.1
CPU No.2
Device
Device
B0
to
B1F
B20
to
B3F
B0
to
B1F
B20
to
B3F
Used for
Setting 1.
B100
to
B11F
B120
to
B13F
B100
to
B11F
B120
to
B13F
Used for
Setting 3.
127
• Devices of Setting 1 to 4 can be set independently for each CPU module.
For example, while the link relay (B) is set for CPU No.1, the internal relay (M) can be set for CPU No.2.
Refresh setting of CPU No.1
The same device is set for CPU
No.1 and No.2.
The same number of points is set for
all the CPU modules.
Refresh setting of CPU No.2
Different devices are set for CPU
No.1 and No.2.
[Auto refresh processing]
CPU No.1
CPU No.2
Device
B0
to
B1F
B20
to
B3F
128
Device
M0
to
M31
M32
to
M63
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
Ex. Operations when executing auto refresh of four ranges (Setting 1: link relay (B), Setting 2: link register
(W), Setting 3: data register (D), Setting 4: internal relay (M))
CPU No.1
send data
(No.3)
CPU No.4
Maximum
2K words
CPU No.4
send data
(No.1)
CPU No.4
send data
(No.2)
CPU No.4
send data
(No.3)
CPU No.4
send data
(No.4)
g.
sin
es
D
.
Maximum
2K words
CPU No.1
send data
(No.4)
pro
wr
itt
e
n
ce
du
ss
ing
rin
g
CPU No.1
send data
(No.3)
User setting area
EN
ar
e
nd
uri
ng
6
itte
Maximum
8K words
wr
Setting 3
D0
CPU No.1
a
CPU No.2
receive data
(No.2)
CPU No.3
receive data
(No.2)
CPU No.4
receive data
(No.2)
EN
send data
(No.2)
CPU No.1
send data
(No.2)
are
Maximum
2K words
ta
Da
ND
gE
rin
du
n
itte
wr
are
CPU No.1
send data
(No.1)
D
Setting 2
W0
CPU No.1
.
ng
ssi
ce
pro
pr
oc
CPU No.2
receive data
(No.1)
CPU No.3
receive data
(No.1)
CPU No.4
receive data
(No.1)
CPU No.3
CPU No.3
send data
(No.1)
CPU No.3
send data
(No.2)
CPU No.3
send data
(No.3)
CPU No.3
send data
(No.4)
Data are written during END
processing.
send data
(No.1)
ta
Maximum
2K words
CPU No.2
send data
(No.1)
CPU No.2
send data
(No.2)
CPU No.2
send data
(No.3)
CPU No.2
send data
(No.4)
to
Da
CPU No.2
Data are read during
the END processing of
CPU No.1.
CPU shared memory
Da
t
CPU shared memory
of other CPU modules
Device
Setting 1
B0
CPU No.1
CPU No.2
receive data
(No.3)
CPU No.3
receive data
(No.3)
CPU No.4
receive data
(No.3)
Setting 4
M0
6.1 Communications Using the CPU Shared Memory
6.1.1 Communications by auto refresh (using the auto refresh area)
CPU No.1
send data
(No.4)
CPU No.2
receive data
(No.4)
CPU No.3
receive data
(No.4)
CPU No.4
receive data
(No.4)
129
• There are following advantages if device ranges are set for each CPU module freely.
• The order of the send ranges can be changed for each CPU module.
• Since unnecessary refresh can set to be disabled, the system scan time will be reduced.
Ex. Changing the order of send ranges for each CPU module
The following is a setting example of auto refresh between the High Performance model QCPU used as
CPU No.1 and the Motion CPU used as CPU No.2. By setting the device ranges freely, the device in the
High Performance model QCPU can be matched to the that in the Motion CPU.
Setting of CPU No.1
Setting of CPU No.2
CPU No.1
CPU No.2
Device
M2000
to
M2000
Monitor device
to
M3055
M3055
M3072
M3072
to Instruction device
M3839
130
Device
M0
M0
Monitor device
(Fixed)
to Instruction device
M3839
(Fixed)
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
Ex. Disabling unnecessary refresh
Unnecessary refresh can set to be disabled by not setting the device ranges of other CPU modules where
auto refresh is not required. The device ranges of the host CPU module must be set.
The following is a setting example of auto refresh between CPU No.1 and each of other CPU modules
(CPU No.2 to No.4).
Setting of CPU No.1
Setting of CPU No.2
6
Setting of CPU No.3
CPU No.1
Setting of CPU No.4
CPU No.3
CPU No.2
Device
Device
6.1 Communications Using the CPU Shared Memory
6.1.1 Communications by auto refresh (using the auto refresh area)
Device
CPU No.4
Device
D0
to
D9
D10
to
D19
D20
to
D29
D0
to
D9
D0
to
D9
D0
to
D9
D100
to
D109
D100
to
D109
D100
to
D109
D100
to
D109
131
(3) Precautions
(a) Local device setting (except the Basic model QCPU)
Device ranges set for the auto refresh target cannot be set as local devices. If set, the refresh data will not be
updated.
(b) Using the same file name as that of the program in the file register (except the Basic
model QCPU)
Do not set the file register of each program as an auto refresh target device. If set, data are automatically
refreshed to the file register corresponding to the scan execution type program executed last.
(c) Assurance of send data
Old data and new data may coexist (data inconsistency) in each CPU module due to the timing of refreshing
data in the host CPU module and reading data in other CPU modules.
The following are the methods to prevent data inconsistency in data communications by auto refresh.
• Preventing inconsistency of 32-bit data
Data inconsistency will not occur because the data transmission by auto refresh is performed only in units
of 32 bits (parameters are set in increments of 32 bits).
• Preventing inconsistency of data exceeding 32 bits
With auto refresh, data are read in descending order of the setting number in auto refresh setting
parameter. To prevent data inconsistency, use the setting number lower than the setting data as an
interlock device.
132
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
Ex. Auto refresh between a QCPU and a Motion CPU
The following are the program examples for the Basic model QCPU and Motion CPU when PLC
parameters ("Communication Area Setting (Refresh Setting)" of "Multiple CPU Setting") are set as shown
below.
[Parameter setting]
Setting No.
("Change
CPU Specific Send Range
PLC
Screens")
Setting 1
Setting 2
PLC No.1
Points
Start
End
Start
End
2
00C0
00C1
M0
M31
PLC No.2
2
0800
0801
M32
M63
PLC No.1
10
00C2
00CB
D0
D9
PLC No.2
0
–
–
–
–
Program example (sending side)
Write
command
X0
PLC Side Device
Program (sending side): Ladder
Program (receiving side): Motion SFC
1)
Send data processing (D0 to D9)
[
2)
6
Program example (receiving side)
SET MO
]
[
RST MO
]
[
RST XO
]
6) M32
3) [G0]
M0
4) [F0]
Receive data processing
(D0 to D9)
6.1 Communications Using the CPU Shared Memory
6.1.1 Communications by auto refresh (using the auto refresh area)
5) [F1]
SET M32
1) CPU No.1 creates send data.
2) CPU No.1 turns on the data setting complete bit.
(Auto refresh execution)
3) CPU No.2 detects the completion of send data setting.
4) CPU No.2 performs receive data processing.
5) CPU No.2 turns on the receive data processing complete bit.
(Auto refresh execution)
6) CPU No.1 detects the completion of the receive data processing, and turns off the data setting
complete bit.
133
Ex. Auto refresh between QCPUs
The following are the program examples for the High Performance model QCPUs when PLC parameters
("Communication Area Setting (Refresh Setting)" of "Multiple CPU Setting") are set as shown below.
[Parameter setting]
Setting No.
CPU Specific Send Range
("Change
PLC
Points
Screens")
Setting 1
Start
PLC Side Device
End
Start
End
PLC No.1
1024
0000
03FF
D0
D1023
PLC No.2
1024
0000
03FF
D1024
D2047
Use D0.0 as an interlock device of CPU No.1 (data setting complete bit) and D1024.0 as an interlock
device of CPU No.2 (receive data processing complete bit).
Program example (sending side) (CPU No.1)Program example (receiving side) (CPU No.2)
(Sending side
(CPU No.1))
Write
command
MO
D0.0 D1024.0
1)
Setting the send
data to D0 to D1023
2)
SET D0.0
6)
D0.0 D1024.0
3)
D0.0 D1024.0
(Receiving side
(CPU No.2))
4)
Reading the receive
data from D0 to D1023
5)
7)
D0.0 D1024.0
SET D1024.0
RST D1024.0
RST D0.0
RST
MO
1) CPU No.1 creates send data.
2) CPU No.1 turns on the data setting complete bit.
(Auto refresh execution)
3) CPU No.2 detects the completion of send data setting.
4) CPU No.2 performs receive data processing.
5) CPU No.2 turns on the receive data processing complete bit.
(Auto refresh execution)
6) CPU No.1 detects the completion of the receive data processing, and turns off the data setting
complete bit.
(Auto refresh execution)
7) CPU No.2 detects the off status of the data setting complete bit, and turns off the receive data
processing complete bit.
134
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
6.1.2
Communications by auto refresh (using the multiple CPU high
speed transmission area)
This section describes data communications by auto refresh using the multiple CPU high speed transmission area in
the CPU shared memory.
(1) Conditions for data communications
Data communications by auto refresh using the multiple CPU high speed transmission area can be performed
only when the following conditions are all met.
• A multiple CPU high-speed main base unit (Q35DB, Q38DB, or Q312DB) is used.
• A Universal model QCPU (except the Q00UCPU, Q01UCPU, and Q02UCPU) is used as CPU No.1.
• At least two of the following CPU modules are used.
• Universal model QCPU (except the Q00UCPU, Q01UCPU, and Q02UCPU)
• Motion CPU (Q172DCPU(-S1), Q173DCPU(-S1), Q172DSCPU, or Q173DSCPU)
• C Controller module (Q12DCCPU-V, Q24DHCCPU-V, or Q24DHCCPU-LS)
6
If any CPU module other than the above is mounted on the multiple CPU high-speed main base unit, set "0" to
the auto refresh points ("Points") of the relevant CPU module in "Multiple CPU High Speed Transmission Area
Setting" of PLC parameter.
Ex. Setting "0" to the auto refresh points of CPU No.3
If all the conditions cannot be met, use the auto refresh area in the CPU shared memory. (
Page 122, Section 6.1.1)
135
6.1 Communications Using the CPU Shared Memory
6.1.2 Communications by auto refresh (using the multiple CPU high speed transmission area)
Set "0" for the CPU module other
than the Universal model QCPU
(except the Q00UCPU, Q01UCPU,
and Q02UCPU), Motion CPU
(Q172DCPU(-S1), Q173DCPU(-S1),
Q172DSCPU, or Q173DSCPU), and
C Controller module (Q12DCCPU-V,
Q24DHCCPU-V or Q24DHCCPU-LS).
(2) Communications by auto refresh
(a) Overview
Auto refresh communicates data using the auto refresh area of the multiple CPU high speed transmission area
in the CPU shared memory. The data written to the auto refresh area of the multiple CPU high speed
transmission area is sent to that of the other CPU modules at regular intervals (multiple CPU high speed
transmission cycles).
Data are automatically read/written among all the CPU modules in the multiple CPU system by setting "Multiple
CPU High Speed Transmission Area Setting" in PLC parameter ("Multiple CPU Setting").
Since auto refresh automatically reads device data in other CPU modules, the host CPU module can use those
device data.
Auto refresh increases the scan time in the multiple CPU system. (
Page 192, Appendix 4)
Ex. Operations when CPU No.1 performs auto refresh of data in B0 to B1F (32 points) and CPU No.2
performs auto refresh of data in B20 to B3F (32 points)
CPU No.1
CPU No.2
CPU shared memory
CPU shared memory
Multiple CPU high speed transmission
area of CPU No.1
2) Data are sent to
CPU No.2.
Multiple CPU high speed transmission
area of CPU No.1
5) Data are sent to
CPU No.1.
Multiple CPU high speed transmission
area of CPU No.2
Auto refresh area
Multiple CPU high speed transmission
area of CPU No.2
Auto refresh area
Auto refresh area
Auto refresh area
1) Data are written during END
processing.
4) Data are written during END
processing.
6) Data are read during END
processing.
3) Data are read during END
processing.
Device
Device
B0 to B1F (for CPU No.1)
B0 to B1F (for CPU No.1)
B20 to B3F (for CPU No.2)
B20 to B3F (for CPU No.2)
• Procedure for CPU No.2 to read device data of CPU No.1
1) CPU No.1 transfers device data (B0 to B1F) to the auto refresh area in its own CPU shared memory
during END processing.
2) CPU No.1 sends the data in the multiple CPU high speed transmission area of its own to CPU No.2.
3) CPU No.2 transfers the received data to B0 to B1F of its own during END processing.
• Procedure for CPU No.1 to read device data of CPU No.2
4) CPU No.2 transfers device data (B20 to B3F) to the auto refresh area in its own CPU shared memory
during END processing.
5)CPU No.2 sends the data in the multiple CPU high speed transmission area of its own to CPU No.1.
6) CPU No.1 transfers the received data to B20 to B3F of its own during END processing.
136
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
(b) Memory configuration of the multiple CPU high speed transmission area
The following shows the memory configuration of the multiple CPU high speed transmission area.
For the CPU shared memory configuration, refer to Page 118, Section 6.1.
2) CPU No.1 send area
3) User setting area
2) CPU No.2 send area
4) Auto refresh area
1) Multiple CPU high speed
transmission area
2) CPU No.3 send area
2) CPU No.4 send area
No.
Name
Multiple CPU high
1)
speed transmission
area
2)
Size
Description
Setting range
Setting unit
0 to 14K words
1K word
0 to 14K words
1K word
0 to 14K words
2 words
0 to 14K words
2 words
An area used to communicate data among CPU modules in the Multiple
CPU system.
The area up to 14K word is divided and assigned to CPU modules in the
6
system.
CPU No.n send
An area used to store send data of each CPU module.
area
Data sent to other CPU modules are stored in this area.
n (n=1 to 4)
Data received from other CPU modules are stored in the area as well.
3)
User setting area
4)
Auto refresh area
An area used to communicate data with other CPU modules by
executing instructions using the cyclic transmission area device
An area to communicate data with other CPU modules by auto refresh
However, the scan time increases for the time required for the auto refresh. (
(Common Instruction))
MELSEC-Q/L Programming Manual
(c) Executing auto refresh
Auto refresh is executed when the CPU modules are in RUN, STOP, or PAUSE status. The auto refresh
execution status when an error has occurred in any of the CPU modules differs depending on the error.
(
Page 159, Section 6.1.4)
137
6.1 Communications Using the CPU Shared Memory
6.1.2 Communications by auto refresh (using the multiple CPU high speed transmission area)
When the COM instruction is used in the program, auto refresh is performed upon execution of the COM instruction.
(3) Multiple CPU high speed transmission area settings
To perform auto refresh of data in the CPU shared memory, set the ranges (number of points) to be sent by each
CPU module ("CPU Specific Send Range") and the devices for storing data ("Auto Refresh Setting") in PLC
parameter ("Multiple CPU Setting").
Project window
[Parameter]
[PLC Parameter]
High Speed Transmission Area Setting"
138
[Multiple CPU Setting]
"Multiple CPU
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
To check the auto refresh directions, specify the CPU number in "Host Station" of PLC parameter ("Multiple CPU Setting").
• Multiple CPU Setting window
• Auto Refresh Setting window
• Multiple CPU High Speed Transmission Area Assignment Confirmation window
Multiple CPU High Speed Transmission Area
Assignment Confirmation window
Multiple CPU Setting window
Click the
Assignment
Confirmation
button.
6
Click the Refresh button.
Auto Refresh Setting window
The auto refresh directions
can be checked.
Click the
PLC No.1
(Send)
button.
6.1 Communications Using the CPU Shared Memory
6.1.2 Communications by auto refresh (using the multiple CPU high speed transmission area)
139
(a) "CPU Specific Send Range"
Set the number of points for the multiple CPU high speed transmission area used in each CPU module.
Item
Description
CPU Specific
Send Range
Setting/displayed range
Set the number of send data points for each CPU module.*1
Setting range: 0 to 14K points*2
If a CPU module not listed on Page 135, Section 6.1.2 (1) is
Setting unit: 1K points
used, set "0" point to the corresponding CPU module.
The area used to communicate data with other CPU modules by
User Setting Area
programs is displayed. The number of points for this area is the
number obtained by subtracting the points set for “Auto
Displayed range: 0 to 14335 points
Refresh" from the points (K) set for "CPU Specific Send Range".
Set parameters required to communicate data with other CPU
Auto Refresh
modules by auto refresh.
The number of points set in the "Auto Refresh Setting" window
Displayed range: 0 to 14335 points
is displayed. (Page 142, Section 6.1.2 (3) (b))
*1
The following number of points is set by default.
Default of "CPU Specific Send Range"
Number of CPU
*2
140
modules
CPU No.1
CPU No.2
2
7K points
7K points
3
7K points
3K points
3K points
4
3K points
3K points
3K points
CPU No.3
CPU No.4
3K points
Set the number of points so that the total points of all the CPU modules will be the following points or less.
• When two CPU modules are mounted: 14K points
• When three CPU modules are mounted: 13K points
• When four CPU modules are mounted: 12K points
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
The number of points for the system area used by dedicated instructions can be changed to 2K points by checking the
"Advanced Setting" checkbox.
This increases the number of dedicated instructions can be executed simultaneously in one scan.
6
CPU Specific Send
Range
Description
Set the number of send data points for each CPU module.
Setting/displayed range
Setting range: 0 to 14K points*1
Setting unit: 1K points
The area used to communicate data by using motion dedicated
System Area
instructions. (
Manual for the Motion CPU used)
Set the number of points for the system area used in each CPU
Setting range: 1K or 2K points
module.
Total
*1
*2
The total of number of points set for the “CPU Specific Send
Displayed range: 1 to 16K points*2
Range" and "System Area" is displayed.
Displayed unit: 1K points
Set the number of points so that the total points of all the CPU modules will be the following points or less.
• When two CPU modules are mounted: 14K points
• When three CPU modules are mounted: 13K points
• When four CPU modules are mounted: 12K points
Set the number of points so that the total points of all the CPU modules will be 16K points or less (including the points set
for the system area).
141
6.1 Communications Using the CPU Shared Memory
6.1.2 Communications by auto refresh (using the multiple CPU high speed transmission area)
Item
(b) "Auto Refresh Setting"
Set auto refresh target devices to communicate data by auto refresh using the multiple CPU high speed
transmission area. Up to 32 ranges can be set for each CPU module.
Item
Points
Description
Setting range
Set the number of points for data communications
• Setting range: 2 to 14336 points*1
in increment of 2 points (word units).
• Setting unit: 2 points*2
• Device that can send data*3
Specify the auto refresh target device.
Start
For the host CPU module, specify the send target
device. For other CPU modules, specify the
receive target device.
X, Y, M, L, B, D, W, R, ZR, SM, SD, SB, SW
• Device that can receive data:*3
X, Y, M, L, B, D, W, R, ZR
• Leave this field blank if auto refresh is not executed. (The
field can be left blank only when it is used as a receive
target device.)
*1
*2
*3
142
Set the number of points within the points set for the "CPU Specific Send Range" of each CPU module.
Bit devices can be specified in increments of 32 points (2 words).
Set the device numbers for setting No.1 to No.32 so that they will not overlap.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
(4) Auto refresh setting examples and data flow
The data flow among CPU modules will be as follows in a multiple CPU system containing three CPU modules
with two auto refresh range settings.
(a) Auto refresh setting examples
The following are the examples of auto refresh settings to explain the data flow.
(a) Send device setting (CPU No.1)
(b) Receive device setting (CPU No.1)
(c) Receive device setting (CPU No.1)
6
(f) Receive device setting (CPU No.2)
(d) Receive device setting (CPU No.2)
(e) Send device setting (CPU No.2)
(g) Receive device setting (CPU No.3)
(h) Receive device setting (CPU No.3)
(i) Send device setting (CPU No.3)
(1) Auto refresh setting of CPU No.1
(2) Auto refresh setting of CPU No.2
(3) Auto refresh setting of CPU No.3
6.1 Communications Using the CPU Shared Memory
6.1.2 Communications by auto refresh (using the multiple CPU high speed transmission area)
143
(b) Flow of data sent from CPU No.1 to other CPU modules
<Parameter setting>
Refer to those related to the data communications of CPU No.1 ((a) to (c)) among the auto refresh setting
examples on Page 143, Section 6.1.2 (4) (a).
(a) Send device setting (CPU No.1)
(b) Receive device setting (CPU No.1)
(c) Receive device setting (CPU No.1)
(1) Auto refresh setting of CPU No.1
(2) Auto refresh setting of CPU No.2
(3) Auto refresh setting of CPU No.3
<Flow of data sent from CPU No.1 to other CPU modules>
• CPU No.1 writes data (CPU No.1 send data) in the devices set in the auto refresh parameter to its own
auto refresh area during END processing.
• CPU No.1 sends the data stored in its own auto refresh area to CPU No.2 and No.3 in each multiple CPU
high speed transmission cycle.
• CPU No.2 and No.3 transfer the data received from CPU No.1 to the devices set in the auto refresh
parameter (CPU No.1 receive area) during END processing.
CPU No.1
Multiple CPU high speed transmission area
CPU No.1
CPU No.2
CPU No.3
Multiple CPU high speed transmission area
CPU No.1
Multiple CPU high speed transmission area
CPU No.1
User setting area
User setting area
User setting area
2)
1)
2)
Auto refresh area
Auto refresh area
Auto refresh area
CPU No.2
User setting area
CPU No.2
User setting area
CPU No.2
User setting area
Auto refresh area
Auto refresh area
Auto refresh area
CPU No.3
User setting area
CPU No.3
User setting area
CPU No.3
User setting area
Auto refresh area
Auto refresh area
Auto refresh area
Device
B0
to
B1F
B20
to
B3F
B40
to
B5F
W0
to
W1F
W20
to
W3F
W40
to
W5F
CPU No.1 send data
CPU No.2 receive area
CPU No.3 receive area
CPU No.1 send data
CPU No.2 receive area
CPU No.3 receive area
1) Data are written during END processing of CPU No.1.
2) Data are sent from CPU No.1 to CPU No.2 and No.3.
3) Data are read during END processing of CPU No.2.
4) Data are read during END processing of CPU No.3.
144
Device
M0
to
M31
M32
to
M63
M64
to
M95
W0
to
W1F
W20
to
W3F
W40
to
W5F
3)
CPU No.1 receive area
CPU No.2 send data
CPU No.3 receive area
3)
CPU No.1 receive area
CPU No.2 send data
CPU No.3 receive area
Device
B0
to
B1F
B20
to
B3F
B40
to
B5F
D0
to
D31
D32
to
D63
D64
to
D95
4)
CPU No.1 receive area
CPU No.2 receive area
CPU No.3 send data
4)
CPU No.1 receive area
CPU No.2 receive area
CPU No.3 send data
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
(c) Flow of data sent from CPU No.2 to other CPU modules
<Parameter setting>
Refer to those related to the data communications of CPU No.2 ((d) to (f)) among the auto refresh setting
examples on Page 143, Section 6.1.2 (4) (a).
(d) Receive device setting (CPU No.2)
(e) Send device setting (CPU No.2)
(f) Receive device setting (CPU No.2)
(1) Auto refresh setting of CPU No.1
(2) Auto refresh setting of CPU No.2
(3) Auto refresh setting of CPU No.3
<Flow of data sent from CPU No.2 to other CPU modules>
• CPU No.2 writes data (CPU No.2 send data) in the devices set in the auto refresh parameter to its own
auto refresh area during END processing.
• CPU No.2 sends the data stored in its own auto refresh area to CPU No.1 and No.3 in each multiple CPU
6
high speed transmission cycle.
• CPU No.1 and No.3 transfer the data received from CPU No.2 to the devices set in the auto refresh
parameter (CPU No.2 receive area) during END processing.
CPU No.1
CPU No.2
CPU No.3
Multiple CPU high speed transmission area
CPU No.1
Multiple CPU high speed transmission area
CPU No.1
Multiple CPU high speed transmission area
CPU No.1
User setting area
User setting area
Auto refresh area
Auto refresh area
Auto refresh area
CPU No.2
User setting area
CPU No.2
User setting area
CPU No.2
User setting area
2)
2)
Auto refresh area
1)
CPU No.3
User setting area
Auto refresh area
Device
B0
to
B1F
B20
to
B3F
B40
to
B5F
W0
to
W1F
W20
to
W3F
W40
to
W5F
Auto refresh area
Auto refresh area
CPU No.3
User setting area
CPU No.3
User setting area
Auto refresh area
Auto refresh area
Device
CPU No.1 send data
3)
CPU No.2 receive area
CPU No.3 receive area
CPU No.1 send data
3)
CPU No.2 receive area
CPU No.3 receive area
6.1 Communications Using the CPU Shared Memory
6.1.2 Communications by auto refresh (using the multiple CPU high speed transmission area)
User setting area
M0
to
M31
M32
to
M63
M64
to
M95
W0
to
W1F
W20
to
W3F
W40
to
W5F
CPU No.1 receive area
CPU No.2 send data
CPU No.3 receive area
CPU No.1 receive area
CPU No.2 send data
CPU No.3 receive area
Device
B0
to
B1F
B20
to
B3F
B40
to
B5F
D0
to
D31
D32
to
D63
D64
to
D95
CPU No.1 receive area
4)
CPU No.2 receive area
CPU No.3 send data
CPU No.1 receive area
4)
CPU No.2 receive area
CPU No.3 send data
1) Data are written during END processing of CPU No.2.
2) Data are sent from CPU No.2 to CPU No.1 and No.3.
3) Data are read during END processing of CPU No.1.
4) Data are read during END processing of CPU No.3.
145
(d) Flow of data sent from CPU No.3 to other CPU modules
<Parameter setting>
Refer to those related to the data communications of CPU No.3 ((g) to (i)) among the auto refresh setting
examples on Page 143, Section 6.1.2 (4) (a).
(g) Receive device setting (CPU No.3)
(h) Receive device setting (CPU No.3)
(i) Send device setting (CPU No.3)
(1) Auto refresh setting of CPU No.1
(2) Auto refresh setting of CPU No.2
(3) Auto refresh setting of CPU No.3
<Flow of data sent from CPU No.3 to other CPU modules>
• CPU No.3 writes data (CPU No.3 send data) in the devices set in the auto refresh parameter to its own
auto refresh area during END processing.
• CPU No.3 sends the data stored in its own auto refresh area to CPU No.1 and No.2 in each multiple CPU
high speed transmission cycle.
• CPU No.1 and No.2 transfer the data received from CPU No.3 to the devices set in the auto refresh
parameter (CPU No.3 receive area) during END processing.
CPU No.1
CPU No.2
CPU No.3
Multiple CPU high speed transmission area
CPU No.1
Multiple CPU high speed transmission area
CPU No.1
Multiple CPU high speed transmission area
CPU No.1
User setting area
User setting area
User setting area
Auto refresh area
Auto refresh area
Auto refresh area
CPU No.2
User setting area
CPU No.2
User setting area
CPU No.2
User setting area
Auto refresh area
Auto refresh area
Auto refresh area
CPU No.3
User setting area
CPU No.3
User setting area
2)
Auto refresh area
CPU No.3
User setting area
2)
Auto refresh area
Auto refresh area
1)
Device
B0
to
B1F
B20
to
B3F
B40
to
B5F
W0
to
W1F
W20
to
W3F
W40
to
W5F
Device
CPU No.1 send data
CPU No.2 receive area
3)
CPU No.3 receive area
CPU No.1 send data
CPU No.2 receive area
3)
CPU No.3 receive area
1) Data are written during END processing of CPU No.3.
2) Data are sent from CPU No.3 to CPU No.1 and No.2.
3) Data are read during END processing of CPU No.1.
4) Data are read during END processing of CPU No.2.
146
M0
to
M31
M32
to
M63
M64
to
M95
W0
to
W1F
W20
to
W3F
W40
to
W5F
Device
CPU No.1 receive area
CPU No.2 send data
4)
CPU No.3 receive area
CPU No.1 receive area
CPU No.2 send data
4)
CPU No.3 receive area
B0
to
B1F
B20
to
B3F
B40
to
B5F
D0
to
D31
D32
to
D63
D64
to
D95
CPU No.1 receive area
CPU No.2 receive area
CPU No.3 send data
CPU No.1 receive area
CPU No.2 receive area
CPU No.3 send data
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
If "Start" and "End" fields are left blank in "Auto Refresh Setting", auto refresh is not performed. (Only the receive area can
be left blank.)
Ex. When the auto refresh setting of CPU No.2 is left blank in "Flow of data sent from CPU No.3 to other CPU
modules" described on Page 146, Section 6.1.2 (4) (d)
CPU No.2 does not auto-refresh the data received from CPU No.3 to W40 to W5F.
(g) Receive device setting (CPU No.3)
(h) Receive device setting (CPU No.3)
(i) Send device setting (CPU No.3)
(1) Auto refresh setting of CPU No.1
(2) Auto refresh setting of CPU No.2
(3) Auto refresh setting of CPU No.3
For the flow of sending data from CPU No.3, refer to "Flow of sending data from CPU No.3 to other CPUs" on Page 146,
Section 6.1.2 (4) (d).
CPU No.1
CPU No.2
CPU No.3
Multiple CPU high speed transmission area
Multiple CPU high speed transmission area
Multiple CPU high speed transmission area
CPU No.1
CPU No.1
CPU No.1
User setting area
User setting area
User setting area
Auto refresh area
Auto refresh area
Auto refresh area
CPU No.2
User setting area
CPU No.2
User setting area
CPU No.2
User setting area
Auto refresh area
Auto refresh area
Auto refresh area
CPU No.3
User setting area
2)
Auto refresh area
6.1 Communications Using the CPU Shared Memory
6.1.2 Communications by auto refresh (using the multiple CPU high speed transmission area)
CPU No.3
User setting area
CPU No.3
User setting area
2)
Auto refresh area
Auto refresh area
1)
Device
B0
to
B1F
B20
to
B3F
B40
to
B5F
W0
to
W1F
W20
to
W3F
W40
to
W5F
Device
CPU No.1 send data
CPU No.2 receive area
3)
CPU No.3 receive area
CPU No.1 send data
CPU No.2 receive area
3)
CPU No.3 receive area
M0
to
M31
M32
to
M63
M64
to
M95
W0
to
W1F
W20
to
W3F
W40
to
W5F
6
Device
CPU No.1 receive area
CPU No.2 send data
4)
CPU No.3 receive area
B0
to
B1F
B20
to
B3F
B40
to
B5F
D0
to
D31
D32
to
D63
D64
to
D95
CPU No.1 receive area
CPU No.2 send data
CPU No.3 receive area
CPU No.1 receive area
CPU No.2 receive area
CPU No.3 send data
CPU No.1 receive area
CPU No.2 receive area
CPU No.3 send data
1) Data are written during END processing of CPU No.3.
2) Data are sent from CPU No.3 to CPU No.1 and No.2.
3) Data are read during END processing of CPU No.1.
4) Data are read during END processing of CPU No.2.
Data are not refreshed.
147
(5) Precautions
(a) Local device setting
Device ranges set for the auto refresh target cannot be set as local devices. If set, the refresh data will not be
updated.
(b) Using the same file name as that of the program in the file register
Do not set the file register of each program as an auto refresh target device. If set, data are automatically
refreshed to the file register corresponding to the scan execution type program executed last.
(c) Transmission delay time
Data transmission delay time due to auto refresh is from 0.09ms to (1.80 + (sending side scan time + receiving
side scan time × 2))ms.
(d) Assurance of send data
Old data and new data may coexist (data inconsistency) in each CPU module due to the timing of refreshing
data in the host CPU module and reading data in other CPU modules.
The following are the methods to prevent data inconsistency in data communications by auto refresh.
• Preventing inconsistency of 32-bit data
Data inconsistency will not occur because the data transmission by auto refresh is performed only in units
of 32 bits (parameters are set in increments of 32 bits).
• Preventing inconsistency of data exceeding 32 bits
With auto refresh, data are read in descending order of the setting number in auto refresh setting
parameter. To prevent data inconsistency, use the setting number lower than the setting data as an
interlock device.
148
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
Ex. Program example for providing an interlock between CPU No.1 and No.2
[Parameter setting]
CPU No.1 auto refresh setting
PLC
PLC
No.1
PLC
No.2
CPU Specific Send
Setting
No.
Range
Points
Start
End
CPU No.2 auto refresh setting
Auto Refresh
Start
1
2
0
1
M0
M31
10
2
11
D0
D9
2
0
1
M32
PLC
M63

PLC
No.1

PLC
No.2
CPU Specific Send
Setting
Range
No.
End
2
1
Direction
Points
Start
End
Auto Refresh
Start
End
1
2
0
1
M0
M31
2
10
2
11
D0
D9
1
2
0
1
M32
M63
Use M0 as an interlock device of CPU No.1 (data setting complete bit) and M32 as an interlock device of
CPU No.2 (receive data processing complete bit).
Program example (sending side) (CPU No.1)Program example (receiving side) (CPU No.2)]
(Sending side (CPU No.1))
Write
command
1)
M100
M0
M32
(Receiving side (CPU No.2))
3)
M0
M32
5)
2)
SET M0
M0
4)
Operation using the
receive data
(D1 to D9)
Setting the send
data to D0 to D9
6)
M32
6
7)
M0
SET M32
M32
RST M0
RST M32
1) CPU No.1 stores send data to D0 to D9.
2) CPU No.1 turns on the data setting complete bit (M0).
CPU No.1 transfers the data to the auto refresh area in its own CPU No.1 send area during END processing, and
sends the transferred data to CPU No.2. CPU No.2 reads the received data from the auto refresh area in its own CPU
No.1 send area and stores the data to the specified device during END processing.
3) CPU No.2 detects the send data set complete bit.
4) CPU No.2 performs the receive data processing.
5) CPU No.2 turns on the receive data processing complete bit (M32).
CPU No.2 writes the data of to the auto refresh area in its own CPU No.2 send area during END processing, and
sends the written data to CPU No.1. CPU No.1 reads the received data from the auto refresh area in its own CPU No.2
send area and stores the data to the specified device during END processing.
6) CPU No.1 detects the on status of the receive data processing complete bit, and turns off the data set complete bit.
149
6.1 Communications Using the CPU Shared Memory
6.1.2 Communications by auto refresh (using the multiple CPU high speed transmission area)
RST M100
6.1.3
Communications by programs using the CPU shared memory
This section describes data communications by programs using the CPU shared memory.
The QCPU in the multiple CPU system communicates data by executing programs in the following cases.
• To read/write data from/to other CPU module (QCPU, C Controller module, or PC CPU module) in the
system
• To read data in the CPU shared memory of the Motion CPU
(1) Areas used for data communications by programs
The following areas in the CPU shared memory are used.
• User setting area
• User setting area in the multiple CPU high speed transmission area
Host CPU operation
information area
System area
Auto refresh area
User setting area
Available for the QCPU
Use-prohibited area
Multiple CPU high speed
transmission area
User setting area
Available for the Universal
model QCPU only
Auto refresh area
(a) Modules supporting data communications using the multiple CPU high speed
transmission area
Only the following CPU modules can be used as communication-target modules of the Universal model QCPU
using the user setting area in the multiple CPU high speed transmission area.
• Universal model QCPU (except the Q00UCPU, Q01UCPU, and Q02UCPU)
• Motion CPU (Q172DCPU(-S1), Q173DCPU(-S1), Q172DSCPU, or Q173DSCPU)
• C Controller module (Q12DCCPU-V, Q24DHCCPU-V, or Q24DHCCPU-LS)
150
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
(2) Instructions used to read/write data from/to the CPU shared memory
The QCPU in the multiple CPU system communicates data with other CPU modules by executing read/write
instructions. The following read/write instructions can be used.
Item
Description
• Instructions using the cyclic transmission area device (U3En\G)*1
Write
instruction*3*4
• TO/DTO instructions (except for High Performance model QCPUs and Process CPUs)
• S.TO instruction*2
Read instruction*3*4
*1
*2
*3
*4
• Instructions using the cyclic transmission area device (U3En\G)*1
• FROM/DFRO instructions
When accessing the multiple CPU high speed transmission area, the processing times of these instructions are shorter
than those of the TO, DTO, FROM, and DFRO instructions.
With this instruction, data cannot be written to the user setting area in the multiple CPU high speed transmission area.
For details on the TO/DTO/S.TO instructions (for writing) and the FROM/DFRO instructions (for reading), refer to the
following.
MELSEC-Q/L Programming Manual (Common Instruction)
Motion CPUs do not support the use of these instructions.
6
(3) Addresses of the user setting area and multiple CPU high speed transmission
area
(a) Addresses of the user setting area
The addresses of the user setting area differ depending on the CPU module used. (
Page 118, Section
6.1)
(b) Addresses of the multiple CPU high speed transmission area
send areas in each CPU module differ depending on the number of points set in "CPU Specific Send Range" of
PLC parameter ("Multiple CPU Setting").
U3E0\G10000 *1
Multiple CPU high
speed transmission area
CPU No.1 send area
User setting area
CPU No.2 send area
Auto refresh area
U3E1\G10000 *1
U3E2\G10000 *1
CPU No.3 send area
U3E3\G10000 *1
CPU No.4 send area
*1
These addresses are used to specify the user setting area of the target CPU module in the cyclic transmission area
device.
For details on each area in the multiple CPU high speed transmission area, refer to Page 135, Section 6.1.2.
151
6.1 Communications Using the CPU Shared Memory
6.1.3 Communications by programs using the CPU shared memory
The addresses of the multiple CPU high speed transmission area are shown below. The end addresses of the
(4) Overview (when the user setting area is used)
The data written to the CPU shared memory in the host CPU module by a write instruction can be read by other
CPU modules by a read instruction.
Unlike the auto refresh using the CPU shared memory, the up-to-date data at the time of an instruction execution
can be read directly.
The following shows the operations when data written to the CPU shared memory of CPU No.1 by a write
instruction is read by CPU No.2 by a read instruction.
CPU No.1
CPU No.2
CPU shared memory
CPU shared memory
Host CPU operation
information area
Host CPU operation
information area
System area
System area
Auto refresh area
Auto refresh area
User setting area
Data written by the write
instruction
2) Data are read by the read
instruction.
User setting area
1) Data are written by the write
instruction.
Program
Execution of
write instruction
Program
Execution of
read instruction
• Processing in CPU No.1
1) CPU No.1 writes data to the user setting area of its own by the write instruction.
• Processing in CPU No.2
2) CPU No.2 reads the data from the user setting area of CPU No.1 and stores the data in the specified
device by the read instruction.
For the read/write instructions, refer to Page 151, Section 6.1.3 (2).
152
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
(5) Overview (when the user setting area in the multiple CPU high speed
communication area is used)
The data written to the multiple CPU high speed transmission area of the host CPU module by a write instruction
is sent to other CPU modules at regular intervals. Other CPU modules read the receive data by a read
instruction.
Unlike the auto refresh using the CPU shared memory, the up-to-date data at the time of an instruction execution
can be read directly.
The following shows the operation when data written to the CPU shared memory of CPU No.1 by a write
instruction is read by CPU No.2 by a read instruction.
CPU No.1
CPU No.2
CPU shared memory
CPU shared memory
Multiple CPU high speed
transmission area of CPU No.1
2) Data are sent to CPU
No.2.
Multiple CPU high speed
transmission area of CPU No.1
User setting area
Multiple CPU high speed
transmission area of CPU No.2
Multiple CPU high speed transmission
area of CPU No.2
User setting area
1) Data are written by the write
instruction.
6
User setting area
User setting area
3) Data are read by the read
instruction.
Execution of
read instruction
• Procedure for CPU No.2 to read device data of CPU No.1
1) CPU No.1 writes data in the user setting area of the multiple CPU high speed transmission area of its own
by the write instruction.
2) CPU No.1 sends the stored data in the multiple CPU high speed transmission area to that of CPU No.2.
3) CPU No.2 reads the received data and stores the data in the specified device by the read instruction.
For the write/read instructions, refer to Page 151, Section 6.1.3 (2).
The delay time of data communications by programs using the user setting area in the multiple CPU high speed
transmission area is from 0.09ms to 1.80ms.
153
6.1 Communications Using the CPU Shared Memory
6.1.3 Communications by programs using the CPU shared memory
Execution of
write instruction
(6) Parameter settings
To use the user setting area in the multiple CPU high speed transmission area, set the ranges (number of points)
to be sent by each CPU module ("CPU Specific Send Range") in PLC parameter ("Multiple CPU Setting").
For setting details, refer to Page 135, Section 6.1.2.
(7) Assurance of send data
Old data and new data may coexist (data inconsistency) in each CPU module due to the timing of reading data in
the host CPU module and writing/sending data in other CPU modules. The following are the methods to prevent
data inconsistency in data communications by programs using the CPU shared memory.
(a) Preventing inconsistency of 32-bit data
To prevent data inconsistency, access the user setting area in the CPU shared memory by specifying an even
number as the start address.
Ex. Specifying "10002" as the start address
[ DMOV D0 U3E0\G10002 ]
Device memory
D0
CPU shared memory
G10000
G10001
G10002
G10003
G10004
154
Even number
address
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
(b) Preventing inconsistency of data exceeding 32 bits
• When the user setting area is used
The read instruction reads data in order starting from the start address to the end address of the user
setting area. On the other hand, the write instruction writes data in order starting from the end address to
the start address of the user setting area.
To prevent data inconsistency, set an interlock device at the start of data to be communicated.
Ex. Program example for providing an interlock between CPU No.1 and No.2
Program example (CPU No.1, sending side)
M0
Program example (CPU No.2, receiving side)
M2
M0
4)
FROM H3E0 H900 D0 K10
SET M2
M2
FROM H3E1 H900 D10 K1
M2
D0.0
D10.0
5)
D0.0
D10.0
6)
Operation using the receive data
(D1 to D9)
1)
M1
7)
SET D10.0
Set send data in D1 to D9.
M1
2)
6
SET M1
SET D0.0
8)
SET M1
3)
SP.TO H3E0 H900 D0 K10 M3
M3
RST
9)
M2
D0.0
D10.0
M1
M1
SP.TO H3E1 H900 D10 K1 M2
M2
RST M1
12)
D0.0
10)
RST D0.0
SET
SP.TO H3E0 H900 D0 K1 M4
M2
RST
M1
13)
RST D10.0
M3
M4
RST M1
M0: Read command
M1: S.TO instruction in-execution flag
M2, M3: S.TO instruction completion device
1) CPU No.1 sets send data in D1 to D9.
2) CPU No.1 turns on the send data setting complete flag (D0.0).
3) CPU No.1 writes the send data (D1 to D9) to the user setting area of its own.
4) CPU No.2 reads the send data from the user setting area of CPU No.1.
5) CPU No.2 detects the on status of the send data setting complete flag (D0.0).
6) CPU No.2 reads the receive data from D1 to D9.
7) CPU No.2 turns on the receive data processing complete flag (D10.0).
8) CPU No.2 writes the status of the receive data processing complete flag to the user setting area of
CPU No.2.
9) CPU No.1 detects the on status of the receive data processing complete flag (D10.0.
10) CPU No.1 turns off the send data setting complete flag (D0.0).
11) CPU No.1 writes the status of the send data setting complete flag to the user setting area of CPU
No.1.
12) CPU No.2 detects the off status of the send data setting complete flag (D0.0).
13) CPU No.2 turns off the receive data processing complete flag (D10.0).
14) CPU No.2 writes the status of the receive data processing complete flag to the user setting area of
CPU No.2.
155
6.1 Communications Using the CPU Shared Memory
6.1.3 Communications by programs using the CPU shared memory
RST
M1
SET M1
14)
SP.TO H3E1 H900 D10 K1 M3
M1
11)
D10.0
• When the user setting area in the multiple CPU high speed transmission area is used
The read instruction reads data in order of those were written to the user setting area. To prevent data
inconsistency, use the device written after the transfer data as an interlock regardless of the device type
and address.
Ex. Program example for providing an interlock between CPU No.1 and No.2
Program example (CPU No.1, sending side) Program example (CPU No.2, receiving side)
3)
Write
command U3E0\
M0 G10010.0
U3E1\
G10000.0
U3E0\
1)
U3E1\
G10010.0 G10000.0
Set send data in the user
setting area
(U3E0\G10000 to G10009).
2)
6)
U3E0\
U3E1\
G10010.0
G10000.0
4)
Operation using the
receive side data
(U3E0\G10000 to G10009)
U3E0\
5)
U3E1\
SET G10000.0
SET G10010.0
7)
U3E0\
U3E0\
RST G10010.0
RST
U3E1\
G10010.0 G10000.0
U3E1\
RST G10000.0
M0
1) CPU No.1 writes send data to the user setting area.
2) CPU No.1 writes the on status of the send data setting complete bit to the user setting area.
<Sending data in the multiple CPU high speed transmission area of CPU No.1 to CPU No.2>
3) CPU No.2 detects the on status of the send data setting complete bit.
4) CPU No.2 performs receive data processing.
5) CPU No.2 writes the on status of the receive data processing complete bit to the user setting area.
<Sending data in the multiple CPU high speed transmission area of CPU No.2 to CPU No.1>
6) CPU No.1 detects the on status of the receive data processing complete it, and turns off the send data
setting complete bit.
<Sending data in the multiple CPU high speed transmission area of CPU No.1 to CPU No.2>
7) CPU No.2 detects the on status of the send data setting complete bit, and turns off the receive data
processing complete bit.
Remark
With an instruction such as the BMOV instruction, which writes two-word or more data to the user setting area, data are
written in order from the end address to the start address.
When writing the send data and interlock signal together with one instruction, provide an interlock signal at the start of send
data to prevent data inconsistency.
156
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
(8) Precautions
(a) Start I/O numbers of CPU modules
Set the following start I/O numbers to each CPU module for the read/write instructions.
CPU No.
CPU No.1
CPU No.2
CPU No.3
CPU No.4
Start I/O number
3E0H
3E1H
3E2H
3E3H
(b) Writing data to the CPU shared memory
Do not write data to the following areas in the CPU shared memory. (
Page 118, Section 6.1)
• System area
• Auto refresh area
• Use-prohibited area
(c) Reading data from the CPU shared memory
Do not read data from the following areas in the CPU shared memory when a High Performance model QCPU
or Process CPU is used.(
Page 118, Section 6.1)
6
• System area
• Auto refresh area
(d) Accessing a module in RESET status
No error will occur even if the CPU module accessed by a read instruction is in RESET status.
However, the access execution flag (SM390) will remain off even after the instruction execution has been
completed. (This will not apply to Universal model QCPUs.)
(e) Accessing CPU modules simultaneously
instructions. If accessed, old data and new data may coexist (data inconsistency). (
Page 154, Section
6.1.3 (7))
(f) Writing data to the CPU shared memory of other CPU modules
Data cannot be written to the CPU shared memory of other CPU modules by a write instruction.
If data are written by executing the TO, S.TO instructions or those using the cyclic transmission area device
(U3En\G), "SP. UNIT ERROR" (error code: 2115) will occur.
157
6.1 Communications Using the CPU Shared Memory
6.1.3 Communications by programs using the CPU shared memory
Configure an interlock to prevent simultaneous access during data communications by the read/write
(g) Writing data to the CPU shared memory of its own
• Basic model QCPU
Data can be written with any write instruction.
• High Performance model QCPU or Process CPU
Data can be written with the S.TO instruction.
However, data cannot be written with instructions using the cyclic transmission area device (U3En\G). If
used, "SP.UNIT ERROR" (error code: 2114) will occur.
• Universal model QCPU
Data can be written with any write instruction.
(h) Reading data from the CPU shared memory
• Basic model QCPU
Data can be read with any read instruction.
• High Performance model QCPU or Process CPU
Data cannot be read with any read instruction.
If read, "SP.UNIT ERROR" (error code: 2114) will occur.
• Universal model QCPU
Data can be read with any read instruction.
(i) Accessing a CPU module that is not actually mounted
A CPU module that is not actually mounted cannot be accessed with instructions using the cyclic transmission
area device(U3En\G). If accessed, "SP.UNIT ERROR" (error code: 2110) will occur.
158
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
6.1.4
Communications among CPU modules when an error is
detected
This section describes the operations performed when an error is detected during data communications among CPU
modules using the CPU shared memory.
(1) Operation when improper data is received
If a CPU module receives improper data during data communications among CPU modules due to noise or
failure, the module discards the receive data. If the receive data is discarded, the CPU module holds the data
which was received before the discarded data.
When the module receives proper data next, the data will be updated.
(2) Data transmission when an error is detected
The operation status of auto refresh and data communications among CPU modules when the host CPU module
has detected a self-diagnostics error will be as follows.
: Transferred ×: Not transferred
Error definition
Auto refresh*1
6
Data communications
among CPU modules*2
Minor error
Factors other than below
Moderate
Multiple CPU high-speed transmission
error
function parameter error
×*4
×*3*4
×
×*3
(including the consistency check error)
*1
*2
*3
*4
Auto refresh means data transfer between the internal user devices and the multiple CPU high-speed transmission area
in the host CPU module.
Data communications among CPU modules means data communications between the multiple CPU high-speed
transmission area in the host CPU module and the multiple CPU high-speed transmission area in other CPU modules.
If an error occurs during the normal operation, transmission of the normal data before the error is continued.
Even if data are written to the multiple CPU high-speed transmission area after the error, the data will not be sent to
other CPU modules.
If a consistency check error occurs due to PLC parameter change during the normal operation, both auto refresh and
data communications among CPU modules are continued.
(3) Applicable CPU modules
The above operations are performed when any of the following CPU modules is used.
• Universal model QCPU (except the Q00UCPU, Q01UCPU, and Q02UCPU)
• Motion CPU (Q172DCPU(-S1), Q173DCPU(-S1), Q172DSCPU, or Q173DSCPU)
• C Controller module (Q12DCCPU-V, Q24DHCCPU-V, or Q24DHCCPU-LS)
159
6.1 Communications Using the CPU Shared Memory
6.1.4 Communications among CPU modules when an error is detected
Major error
6.2
Control Directions from QCPU to Motion CPU
Control directions can be issued from the QCPU to Motion CPU in a multiple CPU system by using the following
motion dedicated instructions. (Control directions cannot be issued from the Motion CPU to another Motion CPU.)
For details on the motion dedicated instructions and their availabilities, refer to the manual for the motion CPU used.
: Available, ×: Not available
QCPU
Basic model QCPU,
Instruction
Description
High Performance
model QCPU,
Process CPU
Q00UCPU,
Universal model QCPU
Q01UCPU,
(except the Q00UCPU,
Q02UCPU
Q01UCPU, and Q02UCPU)
S.SFCS,
SP.SFCS
Requests startup of the motion
D.SFCS,
SFC program.
DP.SFCS
×
×
×
S.SVST*1,
SP.SVST*1
program.
D.SVST,
×
DP.SVST
S.CHGV*1,
SP.CHGV*1
D.CHGV,
DP.CHGVS*3
S.CHGT*1,
SP.CHGT*1
D.CHGT,
command generation axes during
S.CHGA*1,
SP.CHGA*1
D.CHGA,
×
×
×
×
×
Individually changes the torque
control value during operation and
suspension.
×
Changes the current values of the
halted axes, the synchronized
D.CHGAS*3,
Changes the current values of
DP.CHGAS*3
halted command generation axes.
*3
×
during operation and suspension
encoder, and the cam axes.
*2
×
Changes the torque control value
DP.CHGA
*1
×
positioning and JOG operations.
when in real mode.
DP.CHGT2*2
×
Changes the speed of the
DP.CHGT
D.CHGT2*2,
×
during positioning and JOG
operations.
D.CHGVS*3,
×
Changes the speed of the axes
DP.CHGV
160
×
Requests the start of the servo
×
×
×
×
To execute these instructions, the following restrictions on the version of the Motion CPU apply.
• Q172CPUN(-T), Q173CPUN(-T), Q172HCPU(-T), and Q173HCPU(-T): There is no restriction.
• Q172CPU: Version N or later
• Q173CPU: Version M or later
To execute these instructions, use any of the following Motion CPUs.
• Q172DSCPU
• Q173DSCPU
To execute these instructions, use any of the following Motion CPUs.
• Q172DSCPU (when version 00B or later of operating system software SW8DNC-SV22QL is used)
• Q173DSCPU (when version 00B or later of operating system software SW8DNC-SV22QJ is used)
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
Remark
C Controller modules have functions that direct control to Motion CPUs. (
Manual for the C Controller module used)
Ex. S.SFCS instruction
The motion SFC programs in a Motion CPU can be started up from the QCPU.
Motion CPU
QCPU
Start request
Motion SFC
S.SFCS instruction
6
One QCPU can execute up to total of 32 motion dedicated instructions and multiple CPU transmission dedicated instructions
(except the S(P).GINT instruction) simultaneously.
Note that if a motion dedicated instruction and a multiple CPU transmission dedicated instruction are executed
simultaneously, processing of the instruction received first is performed first. If 33 or more unprocessed instructions are
accumulated, "OPERATION ERROR" (error code: 4107) will occur.
6.2 Control Directions from QCPU to Motion CPU
161
6.3
Communications Among CPU Modules By Dedicated
Instructions
6.3.1
Reading/writing device data from/to Motion CPU
The QCPU can read/write device data from/to the Motion CPU by executing the multiple CPU transmission dedicated
instructions and multiple CPU high-speed transmission dedicated instructions. (The Motion CPU cannot read/write
device data from/to other CPU modules including the Motion CPU.)
For details on these two instructions and their availabilities, refer to the manual for the Motion CPU used.
Ex. S.DDWR instruction
The device data in the QCPU are written to the devices in the Motion CPU.
Motion CPU
QCPU
S.DDWR instruction
Device data are
written.
Device data are read.
Device
Device
(1) Multiple CPU transmission dedicated instructions
The QCPU reads/writes device data from/to the Q172CPUN(-T), Q173CPUN(-T), Q172HCPU(-T), and
Q173HCPU(-T) by executing the multiple CPU transmission dedicated instructions listed below.
: Available, ×: Not available
QCPU
Basic model QCPU,
Instruction
Description
High Performance
model QCPU,
Process CPU
S.DDWR,
Writes device data in the host CPU module
SP.DDWR
to the devices in other CPU modules.
S.DDRD,
Loads device data in other CPU modules to
SP.DDRD
the devices in the host CPU module.
S.GINT,
Requests startup of interrupt programs in
SP.GINT
other CPU modules.
162
Universal model
Q00UCPU,
QCPU (except the
Q01UCPU,
Q00UCPU,
Q02UCPU
Q01UCPU, and
Q02UCPU)
×
×
×
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
(2) Multiple CPU high-speed transmission dedicated instructions
The Universal model QCPU reads/writes device data from/to the Q172DCPU(-S1), Q173DCPU(-S1),
Q172DSCPU, and Q173DSCPU by executing the multiple CPU high-speed transmission dedicated instructions
listed below.
: Available, ×: Not available
QCPU
Basic model QCPU,
Instruction
Description
High Performance
model QCPU,
Process CPU
D.DDWR,
Writes device data in the host CPU module
DP.DDWR
to the devices in other CPU modules.
D.DDRD,
Loads device data in other CPU modules to
DP.DDRD
the devices in the host CPU module.
D.GINT,
Requests startup of interrupt programs in
DP.GINT
other CPU modules.
Q00UCPU,
Q01UCPU,
Q02UCPU
×
×
×
×
×
×
Universal model
QCPU (except the
Q00UCPU, Q01UCPU,
and Q02UCPU)
6
One QCPU can execute up to total of 32 motion dedicated instructions and multiple CPU transmission dedicated instructions
(except the S(P).GINT instruction) simultaneously.
Note that if a motion dedicated instruction and a multiple CPU transmission dedicated instruction are executed
simultaneously, processing of the instruction received first is performed first. If 33 or more unprocessed instructions are
accumulated, "OPERATION ERROR" (error code: 4107) will occur.
Remark
Manual for the C Controller module used)
163
6.3 Communications Among CPU Modules By Dedicated Instructions
6.3.1 Reading/writing device data from/to Motion CPU
C Controller modules have functions that direct control to Motion CPUs. (
6.3.2
Starting interrupt programs from QCPU to C Controller
module/PC CPU module
The QCPU can start interrupt programs to the C controller unit/PC CPU module by executing the multiple CPU
transmission dedicated instructions and multiple CPU high-speed transmission dedicated instructions.
Instruction
Description
S.GINT,
Requests startup of interrupt programs in other CPU modules.
SP.GINT
For the availabilities, refer to the following.
D.GINT,
Manual for the C Controller module used
DP.GINT
Manual for the PC CPU module used
Interrupt programs can be started from a C Controller module to a Motion CPU or another C Controller module.
(
Manual for the C Controller module used)
Interrupt programs cannot be started from a PC CPU module.
Ex. S.GINT instruction
Interrupt programs can be started from the QCPU to the PC CPU module.
PC CPU module
QCPU
Start request
S.GINT instruction
164
Interruption program
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
6.3.3
Reading/writing device data between QCPUs
The Universal model QCPU can read/write device data from/to another Universal model QCPU by executing the
multiple CPU high-speed transmission dedicated instructions listed below.
: Available, ×: Not available
QCPU
Basic model QCPU,
*2
Instruction
Description
High Performance
model QCPU,
Process CPU
D.DDRD,
Loads device data in other CPU modules to
DP.DDRD
the devices in the host CPU module.
D.DDWR,
Writes device data in the host CPU module
DP.DDWR
to the devices in other CPU modules.
*1
*2
Q00UCPU,
Q01UCPU,
Q02UCPU
×
×
×
×
Universal model
QCPU (except the
Q00UCPU, Q01UCPU,
and Q02UCPU)*1
For the Q03UDCPU, Q04UDHCPU, and Q06UDHCPU, the module with a serial number (first five digits) of "10012" or
later must be used.
For details on the multiple CPU high-speed transmission dedicated instructions, refer to the following.
6
MELSEC-Q/L Programming Manual (Common Instruction)
The following is the operation to write device data in CPU No.1 to the device of CPU No.2 by executing the DP.DDWR
instruction.
6.3 Communications Among CPU Modules By Dedicated Instructions
6.3.3 Reading/writing device data between QCPUs
CPU No.1
CPU No.2
Program
DP.DDWR U3EI D0 D100 D200 M0
D0
D0
D100
Writing
D200
165
6.4
Multiple CPU Synchronous Interrupt
This function executes interrupt programs (multiple CPU synchronous interrupt programs) at the start timing of each
multiple CPU high speed transmission cycle. The function enables data communications among CPU modules in
synchronization with the multiple CPU high speed transmission cycles.
Since the multiple CPU high speed transmission cycles are synchronized with the Motion CPU operation cycles, use of
the function enables faster responses to the requests from a Motion CPU and sequence program execution
synchronized with the Motion CPU operation cycles.
(1) Multiple CPU synchronous interrupt programs
Multiple CPU synchronous interrupt program is a program using an interrupt pointer (I45). A sequence of
instructions from an interrupt pointer (I45) to the IRET instruction is a multiple CPU synchronous interrupt
program.
To execute multiple CPU synchronous interrupt programs, enable the execution of interrupt programs using the
EI instruction.*1*2
*1
*2
The setting is not required on the Motion CPU side.
Register the routine corresponding to the multiple CPU synchronous interrupt using the bus interface function of the C
Controller module. (
Manual for the C Controller module used)
(2) Execution timing
Multiple CPU synchronous interrupt programs are executed at the start timing of each multiple CPU high speed
transmission cycle.
Multiple CPU high speed transmission cycle
0.88ms
Multiple CPU high speed
transmission
Interrupt request
END 0
Program
Multiple CPU synchronous
interrupt program
166
I45 IRET
END
I45 IRET
0
I45 IRET
END 0
I45 IRET
I45 IRET
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
(3) Applicable CPU modules
The multiple CPU synchronous interrupt function can be executed when any of the following CPU modules is
used.
• Universal model QCPU (except the Q00UCPU, Q01UCPU, and Q02UCPU)
• Motion CPU (Q172DCPU(-S1), Q173DCPU(-S1), Q172DSCPU, or Q173DSCPU)
• C Controller module (Q12DCCPU-V or Q24DHCCPU-V)
If a multiple CPU synchronous interrupt is requested during the execution of another interrupt program, the CPU
module stops the running program and execute the multiple CPU synchronous interrupt program.
Interrupt request
from I45
Interrupt request
from In
END
0
Program
In
Multiple CPU synchronous
interrupt program
6
IRET
Interrupt program
I45
IRET
(4) Operation when an interrupt factor occurs and restrictions on programming
For the operation when an interrupt factor occurs and the restrictions on programming, refer to the following.
User's Manual (Function Explanation, Program Fundamentals) for the CPU module used
6.4 Multiple CPU Synchronous Interrupt
167
6.5
Multiple CPU synchronous startup
This function synchronizes the startups of CPU No.1 to No.4.
Since the function monitors the startup of each CPU module, an interlock program normally used to check the startup
of another CPU module before accessing is no longer required. This function, however, synchronizes the startups with
the slowest one. As a result, the startup of the system may be slow.
This is the function to access each CPU module in a multiple CPU system without an interlock, not to start operations
simultaneously among CPU modules after startup.
(1) Parameter setting
To use the function, select target CPU modules in "Multiple CPU Synchronous Startup Setting" of PLC parameter
("Multiple CPU Setting") using the programming tool. All the CPU modules are selected by default. (The startups
of all the CPU modules are synchronized.)
Setting of this parameter must be the same for all the CPU modules in the system.
If not, "PARAMETER ERROR" (error code: 3015) will be detected.
(2) Applicable CPU modules
The multiple CPU synchronous startup function can be executed when any of the following CPU modules is
used.
• Universal model QCPU (except the Q00UCPU, Q01UCPU, and Q02UCPU)
• Motion CPU (Q172DCPU(-S1), Q173DCPU(-S1), Q172DSCPU, or Q173DSCPU)
• C Controller module (Q12DCCPU-V, Q24DHCCPU-V, or Q24DHCCPU-LS)
168
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES
(3) Precautions
If a CPU module that does not support this function is used, uncheck the checkbox of the corresponding CPU
number in PLC parameter.
Ex. When High Performance model QCPUs are used as CPU No.2 and No.4
Uncheck the checkboxes of CPU No.2 and No.4.
Remark
If this function is not used (each CPU module starts up asynchronously), create a program to check the startup of
each CPU module using SM220 (CPU No.1 preparation completed) to SM223 (CPU No.4 preparation
6
completed).
A special relay area to check the startup of CPU No.2
SM221
0
MOV
U3E1\
G10000
D0
Access to CPU No.2
6.5 Multiple CPU synchronous startup
169
APPENDICES
Appendix 1
Parameters for a Multiple CPU System
(1) Parameters required
For a multiple CPU system, the following PLC parameters shall be set additionally to those for a single CPU
system.
• "Multiple CPU Setting"
• "Control PLC" setting in "Detailed Setting" of "I/O Assignment"
The same PLC parameters must be set to all the CPU modules used in a multiple CPU system, except some
parameters. (
Page 172, Appendix 1.1)
When a PC CPU module is used, the multiple CPU parameters set in the programming tool can be used as is in
PC CPU setting utility.
(2) When parameters for the multiple CPU system have been changed
Set the same parameters to all the CPU modules in the system, and reset CPU No.1 or power off and on the
system.
The multiple CPU parameters set for a project can be used as is for another project. (
4.2.2 (2))
170
Page 85, Section
APPENDICES
(3) Checking the multiple
In a multiple CPU system, whether the same multiple CPU parameters are set to all the CPU modules is checked
at the following timing.
• When a multiple CPU system is powered on
• When CPU No.1 is reset
• When the operating status of the CPU modules are switched from STOP to RUN
• When any parameter is changed
This check is called a consistency check. (For the parameters to be checked, refer to the items marked
and
in the Consistency column on Page 172, Appendix 1.1. For check details, refer to Page 171, Appendix 1 (3) (b).)
(a) When same parameters are set to all the CPU modules
The multiple CPU system starts up.
(b) When same parameters are not set to all the CPU modules
The multiple CPU system performs either of the operations described in the following table.
Check the multiple CPU parameters, and set the same parameters to all the CPU modules in the system. To
start the system, reset CPU No.1 or power off and on the system. (
Item
CPU No.1
Page 102, Section 4.6)
Other than CPU No.1
A
• The CPU module compares its
The multiple CPU system is powered on.
parameters with those of CPU No.1.
No consistency check of the multiple CPU
parameters is performed.*1
CPU No.1 is reset.
• "PARAMETER ERROR" (error code:
3012/3015) will occur in the CPU module
if the parameters do not match with those
of CPU No.1.
of any CPU module is
in RUN.
• The CPU module compares its parameters with those of a running CPU module with
the lowest No.*2
• "PARAMETER ERROR" (error code: 3012/3015) will occur in the CPU module if the
parameters do not match.
• The CPU module compares its
• The RUN/STOP
switch is switched
There is no CPU
from STOP to RUN.
module whose
• Parameters are
operating status is in
written from a
RUN.
programming tool.
parameters with those of CPU No.2 (in
the STOP status).*2
• "PARAMETER ERROR" (error code:
3012/3015) will occur in the CPU module
if the parameters do not match with those
of CPU No.2.
No.1.
*1
*2
parameters with those of CPU No.1.
• "PARAMETER ERROR" (error code:
3012/3015) will occur in the CPU module
if the parameters do not match with those
of CPU No.1.
Since "MULTI CPU DOWN" (error code:
A stop error has
occurred in CPU
• The CPU module compares its
-
7000) error occurs in the CPU module, the
module will not start running. (No
consistency check is performed.)
Universal model QCPUs perform consistency check. "PARAMETER ERROR" (error code: 3015) will occur in the CPU
module if the parameters do not match.
Universal model QCPUs compare its parameters with those of CPU No.1.
In a multiple CPU system containing a Motion CPU, if multiple CPU parameters not available for Motion CPUs are changed
for a QCPU or PC CPU module, reset the QCPU used as CPU No.1 or power off and on the programmable controller
system.
A High Performance model QCPU, Process CPU, or PC CPU module performs consistency check with the multiple CPU
parameters of the Motion CPU, and detects "PARAMETER ERROR" (error code: 3015).
171
Appendix 1 Parameters for a Multiple CPU System
The operating status
Appendix 1.1
List of parameters
(1) For Basic model QCPU, High Performance model QCPU, and Process CPU
The following table lists PLC parameters need to be set for a Basic model QCPU, High Performance QCPU, or
Process CPU.
Setting*1
PLC parameter
I/O Assignment
Consistency*2
Reference
Type
-
I/O
Model Name
-
Assignment
Points
-
Start XY
-
Base Model Name
-
-
Qn(H)/QnPH/QnPRH
Power Model Name
-
-
User's Manual (Function
Extension Cable
-
-
Explanation, Program
Slots
-
Base Setting
Switch Settings
Error Time Output Mode
-
-
-
-
-
Detailed
PLC Operation Mode at H/W Error
-
-
Settings
I/O Response Time
-
-
Control PLC
Fundamentals)
Page 80, Section 4.2.2
Qn(H)/QnPH/QnPRH
PLC System
Points Occupied by Empty Slot
User's Manual (Function
-
Explanation, Program
Fundamentals)
No. of PLC
Operation Mode
Online Module Change*3
All CPUs Can Read All Inputs
All CPUs Can Read All Outputs
Multiple CPU
Setting
Page 80, Section 4.2.2
CPU Specific
Communication Area Setting
Send Range
(Refresh Setting)
PLC Side Device
*1
-
: Item that must be set in a multiple CPU system (A system does not operate without setting.)
: Item that is set if needed in a multiple CPU system
- : Item that is the same as in a single CPU system
*2
: Item that must have same settings among all the CPU modules in a multiple CPU system
: Item that must have same settings among all the QCPUs and PC CPU module in a multiple CPU system
(item that is not supported in Motion CPUs)
- : Item that can be set individually for each CPU module in a multiple CPU system
*3
172
For a Basic model QCPU, the online module change setting is disabled.
High Performance model QCPUs do not support the online change function. To replace a module controlled by a
Process CPU online, check the "Enable Online Module Change with Another PLC." checkbox.
APPENDICES
(2) For Universal model QCPU
The following table lists PLC parameters need to be set for a Universal model QCPU.
Setting*1
PLC parameter
I/O Assignment
I/O
Base Setting
Assignment
Reference
Type
-
Model Name
-
Points
-
Start XY
-
Base Model Name
-
-
QnUCPU User's
Power Model Name
-
-
Manual (Function
Extension Cable
-
-
Explanation, Program
Slots
-
Switch Settings
Detailed Settings
Consistency*2
-
-
-
Error Time Output Mode
-
-
PLC Operation Mode at H/W Error
-
-
I/O Response Time
-
-
Fundamentals)
Control PLC
Page 80, Section 4.2.2
QnUCPU User's
PLC System
Points Occupied by Empty Slot
A
Manual (Function
-
Explanation, Program
Fundamentals)
No. of PLC
Page 80, Section 4.2.2
Host Station
Page 24, Section 2.1,
-
Page 80, Section 4.2.2
Multiple CPU Synchronous Startup Setting*4
Online Module Change*4
All CPUs Can Read All Inputs
All CPUs Can Read All Outputs
Multiple CPU
Use Multiple CPU High Speed
Setting
Transmission
Multiple CPU high
Transmission Area
Page 80, Section 4.2.2
CPU Specific Send Range
Speed
Auto Refresh
Setting*4
Points
Start
-
Advanced Settings
System Area*3
Communication
Area Setting
(Refresh setting)
CPU Specific Send Range
PLC Side Devices
*5
/
-
173
Appendix 1 Parameters for a Multiple CPU System
Appendix 1.1 List of parameters
Operation Mode
*1
: Item that must be set in a multiple CPU system (A system does not operate without setting.)
: Item that is set if needed in a multiple CPU system
-
*2
: Item that is the same as in a single CPU system
: Item that must have same settings among all the CPU modules in a multiple CPU system
: Item that must have same settings among all the QCPUs and PC CPU module in a multiple CPU system
(item that is not supported in Motion CPUs)
-
: Items that can be set individually for each CPU module in a multiple CPU system
*3
The system area can be set when the "Advanced Setting" checkbox is selected.
*4
For the Q00UCPU, Q01UCPU, and Q02UCPU, "Multiple CPU Synchronous Startup Setting", “Online Module
Change", and "Multiple CPU High Speed Transmission Area Setting" cannot be set.
*5
The consistency level differs depending on the CPU module used.
: For the Q00UCPU, Q01UCPU, and Q02UCPU
: For CPU modules other than the Q00UCPU, Q01UCPU, and Q02UCPU
174
APPENDICES
Appendix 2
Comparison with a Single CPU System
This section describes comparison between a single CPU system and multiple CPU system.
(1) When a Basic model QCPU is used
Item
Single CPU system
Multiple CPU system
Maximum number of
4 levels
extension levels
Maximum number of
25 - (Number of CPU modules)*1*2
24
mountable I/O modules
Main base unit*3
Q3B, Q3SB, Q3RB, Q3DB
System
Extension cable
QC05B, QC06B, QC12B, QC30B, QC50B, QC100B
Within 13.2m
distance
Power supply module*3
Q6P, Q6SP, Q6RP
Function version A or later
I/O module
Available
Section 3.1.1
Q6RB
Overall extension cable
Basic model QCPU
Page 32,
Q5B, Q6B
Extension base unit*3
configuration
No function version restriction
module
Function version B or later
Function version A or later
A
Function version B
Function version A or later
Interrupt module
Intelligent function module
Reference
(Function version A or later for the
Page 32,
Section 3.1.1,
Page 40,
Section 3.1.3
QD62, QD62D, and QD62E)
software
Other than above
package
*1
*2
*3
Version 7 or later
Version 8 or later
The same version can be used in both single CPU systems and multiple
CPU systems.
Page 65,
Section 3.4
"Number of CPU modules" indicates the number set in "No. of PLC" of PLC parameter ("Multiple CPU Setting").
When a module occupying two slots is mounted, the maximum number of mountable I/O modules is the number
obtained by "25 - (Number of CPU modules + 1)".
When a module occupying three slots is mounted, the maximum number of mountable I/O modules is the number
obtained by "25 - (Number of CPU modules + 2)".
If a Motion CPU or PC CPU module is used in a multiple CPU system, the Q3RB, Q6RB, and Q6RP cannot be
used.
175
Appendix 2 Comparison with a Single CPU System
GX Developer
Available
Item
Number of CPU modules
and mounting position
I/O number assignment
Single CPU system
Multiple CPU system
Only 1 module in the CPU slot
3 modules in the CPU slot to slot 1
Slot 0 is 00H.
Concept
Reference
Page 60,
Section 3.3.2
A slot on the right of the rightmost
Page 27,
CPU module is 00H.*1
Section 2.2
The number of mountable
Restrictions on the number
of mountable modules
The number of mountable
modules per system and the
Page 71,
modules differs depending on the
number of controllable modules
Section 3.5
CPU module type.
per CPU module differ depending
(1) (c)
on the CPU module type.
Access from CPU module(s)
to other modules
Relations between CPU modules
All modules can be controlled.
and other modules must be set in
"Control PLC" of PLC parameter.
Page 104,
CHAPTER 5
Manual for
Access from GOTs
Accessible
the GOT
used
Access with instructions
using the link direct device
Accessible
Only control CPU is accessible.
Page 104,
Section 5.2
Manual for
Access range
the CC-Link
Access to CC-Link
Accessible
Only control CPU is accessible.
system
master/local
module used
Accessible through an RS-232
cable or over network.
Access from peripherals
Accessible through an RS-232
For access to the Motion CPU, PC
cable or over network
CPU module, or C Controller
-
module, refer to the relevant
manual.
Clock data used by
Clock function
intelligent function modules
(such as the QD75)
Clock data of the Basic model
Clock data of the Basic model
Page 99,
QCPU is used.
QCPU (CPU No.1) is used.
Section 4.4
The entire system is reset by
Operation when a CPU
The entire system is reset by
module is reset
resetting the Basic model QCPU.
resetting the Basic model QCPU
(CPU No.1).
(Resetting CPU No.2 and No.3
Page 102,
Section 4.6
individually is not allowed.)
If a stop error has occurred in the
Basic model QCPU (CPU No.1),
Operation
the system stops. ("MULTI CPU
Operation when a stop error
has occurred in a CPU
module
DOWN" (error code: 7000) occurs
The system stops.
in CPU No.2 and No.3.)
If a stop error has occurred in CPU
Page 102,
Section 4.6
No.2 or No.3, the operation
depends on the parameter setting
("Operation Mode").
*1
When a CPU module occupying two slots is mounted, the slot on the right of the CPU module will be 10H.
When a CPU module occupying three slots is mounted, the slot on the right of the CPU module will be 20H.
176
APPENDICES
Item
Single CPU system
Multiple CPU system
Reference
Basic model QCPU = 320 points,
Motion CPU = 2048 points,
Communications by auto
refresh using the CPU
Not supported
shared memory
C Controller module = 2048 points,
Page 122,
PC CPU module = 2048 points,
Section 6.1.1
Total of all CPU modules: 4416
points
Data communications is performed
Communications by
Communications
programs using the CPU
among CPU
shared memory
by using the TO, S.TO, FROM
Not supported
instructions, and instructions using
the cyclic transmission area device
Page 150,
Section 6.1.3
(U3En\G).
modules
Communications between
Basic model QCPU and
Not supported
Motion CPU
Communications between
Basic model QCPU and C
Controller module/PC CPU
Data communications is performed
Page 160,
by using five motion dedicated
Section 6.2,
instructions and three multiple CPU
Page 162,
transmission dedicated instructions.
Section 6.3.1
Data communications is performed
Not supported
by using the multiple CPU
transmission dedicated instruction.
module
Page 164,
Section 6.3.2
A
• Writing data during RUN
• Time reserved for communication
Scan time
Factors that increase scan
time
• Writing data during RUN
processing
• Time reserved for
• Refresh processing among CPU
communication processing
modules in the multiple CPU
Page 192,
Appendix 4
system
• Waiting time
• Number of CPU modules
Assignment")
• Out-of-group I/O setting ("Multiple
CPU Setting")
Parameter
Parameters added for a
multiple CPU system
• Operation mode when a stop
Not supported
error has occurred in a CPU
module ("Multiple CPU Setting")
• Communication area setting
Page 80,
Section 4.2.2,
Page 170,
Appendix 1
("Refresh Setting")
• Settings of some parameters
must be the same for all the CPU
modules while others can be set
individually for each CPU module.
Precaution
AnS/A series module
Not supported
Page 188,
Appendix 3
177
Appendix 2 Comparison with a Single CPU System
("Multiple CPU Setting")
• Control PLC setting ("I/O
(2) When a High Performance model QCPU is used
Item
Single CPU system
Multiple CPU system
Maximum number of
7 levels
extension levels
Maximum number of
Main base unit*3
Extension base unit*3*6
configuration
Extension cable
65- (Number of CPU modules)*1*2
64
mountable I/O modules
System
Q3B, Q3SB, Q3RB, Q3DB
QA1S6ADP+A1S5B/A1S6B, QA6B, QA6ADP+A5B/A6B
Within 13.2m
Power supply module*3
Q6P, Q6SP, Q6RP, A1S6P, A6P
Function version A or later
I/O module
Available
Function version B
Page 41,
Function version A or later
Interrupt module
module
Section 3.2.1,
No function version restriction
Page 51,
Function version B or later
Intelligent function module
Section 3.2.1
QC05B, QC06B, QC12B, QC30B, QC50B, QC100B
distance
QCPU
Page 41,
Q5B, Q6B, Q6RB, QA1S5B, QA1S6B,
Overall extension cable
High Performance model
Reference
Function version A or later
Section 3.2.3
(Function version A or later for the
QD62, QD62D, and QD62E.)
GX Developer
Version 4 or later
Version 6 or later
GX Configurator-AD
*4
SW0D5C-QADU 00A or later
SW0D5C-QADU 20C or later*4
Available
GX Configurator-DA
SW0D5C-QDAU 00A or later*4
SW0D5C-QDAU 20C or later*4
software
GX Configurator-SC
SW0D5C-QSCU 00A or later*4
SW0D5C-QSCU 20C or later*4
GX Configurator-CT
later*4
later*4
package
Other than above
Number of CPU modules
and mounting position
I/O number assignment
SW0D5C-QCTU 00A or
SW0D5C-QCTU 20C or
Page 65,
Section 3.4
The same version can be used in both single CPU systems and multiple
CPU systems.
Only 1 module in the CPU slot
Slot 0 is 00H.
Concept
4 modules in the CPU slot to slot 2
Page 47,
Section 3.2.2
A slot on the right of the rightmost
Page 27,
CPU module is 00H.*5
Section 2.2
The number of mountable
Restrictions on number of
mountable modules
The number of mountable
modules per system and the
Page 69,
modules differs depending on the
number of controllable modules
Section 3.5
CPU module type.
per CPU module differ depending
(1) (b)
on the CPU module type.
*1
*2
*3
*4
*5
"Number of CPU modules" indicates the number set in "No. of PLC" of PLC parameter ("Multiple CPU Setting").
When a module occupying two slots is mounted, the maximum number of mountable I/O modules is the number
obtained by "65 - (Number of CPU modules + 1)".
When a module occupying three slots is mounted, the maximum number of mountable I/O modules is the number
obtained by "25 - (Number of CPU modules + 2)".
If a Motion CPU or PC CPU module is used in a multiple CPU system, the Q3RB, Q6RB, and Q6RP cannot be
used.
Available version differs for some intelligent function modules. (
Manual for the intelligent function module used)
When a CPU module occupying two slots is mounted, the slot on the right of the CPU module will be 10H.
When a CPU module occupying three slots is mounted, the slot on the right of the CPU module will be 20H.
*6
178
When the QA1S6ADP+A1S5B/A1S6B is used, the maximum number of extension base units is 1, and the maximum
number of I/O modules that can be mounted is 20 minus the number of CPU modules. When the QA1S6ADPS1+A1S5B/A1S6B is used, the maximum number of extension base units is 3, and the maximum number of I/O
modules that can be mounted is 36 minus the number of CPU modules.
APPENDICES
Item
Access from CPU
module(s) to other modules
Access from GOTs
Access with instructions
using the link direct device
Single CPU system
Multiple CPU system
Relations between CPU modules
All modules can be controlled.
and other modules must be set in
"Control PLC" of PLC parameter.
Accessible
Accessible
Reference
Page 104,
CHAPTER 5
A GOT can access a High
Manual for
Performance model QCPU of the
the GOT
specified CPU No.
used
Only control CPU is accessible.
Page 104,
Section 5.2
Manual for
the CC-Link
Access range
Access to CC-Link
Accessible
Only control CPU is accessible.
system
master/local
module used
Accessible through a USB
cable/RS-232 cable or over
Access from peripherals
Accessible through a USB
network.
cable/RS-232 cable or over
For access to the Motion CPU, PC
network
CPU module, or C Controller
-
module, refer to the relevant
A
manual.
Clock function
Clock data used by
Clock data of the High
intelligent function modules
Performance model QCPU is
(such as the QD75)
used.
Clock data of the High Performance
Page 99,
model QCPU (CPU No.1) is used.
Section 4.4
The entire system is reset by
Operation when a CPU
module is reset.
resetting the High Performance
resetting the High Performance
model QCPU (CPU No.1).
model QCPU.
(Resetting CPU No.2 to No.4
Page 102,
Section 4.6
individually is not allowed.)
If a stop error has occurred in the
High Performance model QCPU
Operation
(CPU No.1), the system stops.
Operation when a stop error
has occurred in a CPU
("MULTI CPU DOWN" (error code:
The system stops.
module
7000) occurs in CPU No.2 to No.4.)
If a stop error has occurred in CPU
Page 102,
Section 4.6
No.2 to No.4, the operation depends
on the parameter setting
("Operation Mode").
Communications by auto
refresh using the CPU
Total of 4 Settings per CPU module:
Not supported
shared memory
up to 2K words,
Total of all CPU modules: 8K words
Page 122,
Section 6.1.1
Data communications is performed
by using the S.TO, FROM
Communications by
programs using the CPU
Communications
Not supported
shared memory
the cyclic transmission area device
Page 150,
Section 6.1.3
(U3En\G).
among CPU
modules
instructions, and instructions using
Communications between
High Performance model
Not supported
QCPU and Motion CPU
Communication between
High Performance model
QCPU and C Controller
module/PC CPU module
Data communications is performed
Page 160,
by using five motion dedicated
Section 6.2,
instructions and three multiple CPU
Page 162,
transmission dedicated instructions.
Section 6.3.1
Data communications is performed
Not supported
by using the multiple CPU
transmission dedicated instruction.
Page 164,
Section 6.3.2
179
Appendix 2 Comparison with a Single CPU System
The entire system is reset by
Item
Single CPU system
Multiple CPU system
Reference
• Writing data during RUN
• Time reserved for communication
Scan time
Factors that increase scan
time
• Writing data during RUN
• Time reserved for
communication processing
processing
• Refresh processing among CPU
modules in the multiple CPU
Page 192,
Appendix 4
system
• Waiting time
• Number of CPU modules
("Multiple CPU Setting")
• Control PLC setting ("I/O
Assignment")
• Out-of-group I/O setting ("Multiple
CPU Setting")
Parameter
Parameters added for a
multiple CPU system
• Operation mode when a stop
Not supported
error has occurred in a CPU
module ("Multiple CPU Setting")
• Communication area setting
Page 80,
Section 4.2.2,
Page 170,
Appendix 1
("Refresh Setting")
• Settings of some parameters
must be the same for all the CPU
modules while others can be set
individually for each CPU module.
Supported only when a High
Precaution
AnS/A series module
Supported
Performance model QCPU is set as
a control CPU.
180
Page 188,
Appendix 3
APPENDICES
(3) When a Process CPU is used.
Item
Single CPU system
Multiple CPU system
Maximum number of
7 levels
extension levels
Maximum number of
Main base unit*3
configuration
Extension base unit
65 - (Number of CPU modules)*1*2
64
mountable I/O modules
System
Q3B, Q3RB, Q3DB
*3
Extension cable
Q5B, Q6B, Q6RB
Section 3.2.1
Within 13.2m
distance
Power supply module*3
Q6P, Q6RP
Process CPU
No function version restriction
I/O module
Function version A or later
Interrupt module
No function version restriction
module
Function version B or later
Intelligent function module
Page 41,
QC05B, QC06B, QC12B, QC30B, QC50B, QC100B
Overall extension cable
Available
Reference
Function version A or later
(Function version A or later for the
Page 41,
Section 3.2.1,
Page 51,
Section 3.2.3
QD62, QD62D, and QD62E.)
Available
GX Works2, GX Developer,
software
PX Developer,
package
GX Configurator
Number of CPU modules
and mounting position
Page 65,
CPU systems.
Section 3.4
Only 1 module in the CPU slot
Slot 0 is 00H.
Concept
4 modules in the CPU slot to slot 2
Page 47,
Section 3.2.2
A slot on the right of the rightmost
Page 27,
CPU module is 00H.*4
Section 2.2
The number of mountable
Restrictions on the number
of mountable modules
The number of mountable
modules per system and the
Page 69,
modules differs depending on the
number of controllable modules
Section 3.5
CPU module type.
per CPU module differ depending
(1) (b)
on the CPU module type.
*1
*2
*3
*4
"Number of CPU modules" indicates the number set in "No. of PLC" of PLC parameter ("Multiple CPU Setting").
When a module occupying two slots is mounted, the maximum number of mountable I/O modules is the number
obtained by "25 - (Number of CPU modules + 1)".
When a module occupying three slots is mounted, the maximum number of mountable I/O modules is the number
obtained by "25 - (Number of CPU modules + 2)".
If a Motion CPU or PC CPU module is used in a multiple CPU system, the Q3RB, Q6RB, and Q6RP cannot be
used.
When a CPU module occupying two slots is mounted, the slot on the right of the CPU module will be 10H.
When a CPU module occupying three slots is mounted, the slot on the right of the CPU module will be 20H.
181
Appendix 2 Comparison with a Single CPU System
I/O number assignment
The same version can be used in both single CPU systems and multiple
A
Item
Access from CPU module(s)
to other modules
Access from GOTs
Access with instructions
using the link direct device
Single CPU system
Multiple CPU system
Relations between CPU modules
All modules can be controlled.
and other modules must be set in
"Control PLC" of PLC parameter.
Accessible
Accessible
A GOT can access a Process CPU
of the specified CPU No.
Only control CPU is accessible.
Reference
Page 104,
CHAPTER 5
Manual for
the GOT
used
Page 104,
Section 5.2
Manual for
Access range
the CC-Link
Access to CC-Link
Accessible
Only control CPU is accessible.
system
master/local
module used
Accessible through a USB
cable/RS-232 cable or over
Access from peripherals
Accessible through a USB
network.
cable/RS-232 cable or over
For access to the Motion CPU, PC
network
CPU module, or C Controller
-
module, refer to the relevant
manual.
Clock data used by
Clock function
intelligent function modules
(such as the QD75)
Clock data of the Process CPU
Clock data of the Process CPU
Page 99,
is used.
(CPU No.1) is used.
Section 4.4
The entire system is reset by
Operation when a CPU
The entire system is reset by
module is reset.
resetting the Process CPU.
resetting the Process CPU (CPU
No.1).
(Resetting CPU No.2 to No.4
Page 102,
Section 4.6
individually is not allowed.)
If a stop error has occurred in the
Process CPU (CPU No.1), the
Operation
system stops. ("MULTI CPU
Operation when a stop error
has occurred in a CPU
DOWN" (error code: 7000) occurs in
The system stops.
module
CPU No.2 to No.4.)
If a stop error has occurred in CPU
Page 102,
Section 4.6
No.2 to No.4, the operation depends
on the parameter setting
("Operation Mode").
Communications by auto
refresh using the CPU
Total of 4 Settings per CPU module:
Not supported
shared memory
up to 2K words,
Total of all CPU modules: 8K words
Page 122,
Section 6.1.1
Data communications is performed
by using the S.TO, FROM
Communications by
programs using the CPU
Communications
Not supported
shared memory
the cyclic transmission area device
Communications between
Process CPU and Motion
Not supported
CPU
Communications between
Process CPU and C
Controller module/PC CPU
module
182
Page 150,
Section 6.1.3
(U3En\G).
among CPU
modules
instructions, and instructions using
Data communications is performed
Page 160,
by using five motion dedicated
Section 6.2,
instructions and three multiple CPU
Page 162,
transmission dedicated instructions.
Section 6.3.1
Data communications is performed
Not supported
by using the multiple CPU
transmission dedicated instruction.
Page 164,
Section 6.3.2
APPENDICES
Item
Single CPU system
Multiple CPU system
Reference
• Writing data during RUN
• Time reserved for communication
Scan time
Factors that increase scan
time
• Writing data during RUN
processing
• Time reserved for
• Refresh processing among CPU
communication processing
modules in a multiple CPU
Page 192,
Appendix 4
system
• Waiting time
• Number of CPU modules
("Multiple CPU Setting")
• Control PLC setting ("I/O
Assignment")
• Out-of-group I/O setting ("Multiple
CPU Setting")
Parameter
Parameters added for
multiple CPU systems
• Operation mode when a stop
Not supported
error has occurred in a CPU
module ("Multiple CPU Setting")
• Communication area setting
Page 80,
Section 4.2.2,
Page 170,
Appendix 1
("Refresh Setting")
• Settings of some parameters
must be the same for all the CPU
modules while others can be set
individually for each CPU module.
Precaution
AnS/A series module
Not supported
Page 188,
A
Appendix 3
Appendix 2 Comparison with a Single CPU System
183
(4) When a Universal model QCPU is used
Item
Single CPU system
Maximum number of
Multiple CPU system
Reference
7 levels (Q00UCPU, Q01UCPU, or Q02UCPU: 4 levels)
extension levels
65 - (Number of CPU modules)*1*2
Maximum number of
mountable I/O modules
64
(Q00UCPU or Q01UCPU:
(Q00UCPU or Q01UCPU: 24,
25 - (Number of CPU modules),
Q02CPU: 36)
Q02UCPU:
37 - (Number of CPU modules))
System
Main base unit*3
configuration
Extension base unit*3*4*5
Extension cable
Q3B, Q3SB, Q3RB, Q3DB
QA1S6ADP+A1S5B/A1S6B, QA6B, QA6ADP+A5B/A6B
QC05B, QC06B, QC12B, QC30B, QC50B, QC100B
Within 13.2m
distance
Power supply module*3
Q6P, Q6SP, Q6RP
Universal model QCPU
No function version restriction
I/O module
Function version A or later
Interrupt module
No function version restriction
module
Function version B or later
Intelligent function module
Section 3.3.1
Q5B, Q6B, Q6RB, QA1S5B, QA1S6B,
Overall extension cable
Available
Page 53,
Function version A or later
(Function version A or later for the
Page 53,
Section 3.3.1,
Page 64,
Section 3.3.3
QD62, QD62D, and QD62E)
Available
GX Works2,
software
GX Developer,
package
GX Configurator
*1
*2
*3
*4
*5
184
The same version can be used in both single CPU systems and multiple
Page 65,
CPU systems.
Section 3.4
"Number of CPU modules" indicates the number set in "No. of PLC" of PLC parameter ("Multiple CPU Setting").
When a module occupying two slots is mounted, the maximum number of mountable I/O modules is the number
obtained by "65 - (Number of CPU modules + 1)".
When a module occupying three slots is mounted, the maximum number of mountable I/O modules is the number
obtained by "65 - (Number of CPU modules + 2)".
If a Motion CPU or PC CPU module is used in a multiple CPU system, the Q3RB, Q6RB, and Q6RP cannot be
used.
AnS/A series-compatible modules can be used with a Universal model QCPU with a serial number (first five digits) of
"13102" or later.
When the QA1S6ADP+A1S5B/A1S6B is used, the maximum number of extension base units is 1, and the maximum
number of I/O modules that can be mounted is 20 minus the number of CPU modules. When the QA1S6ADPS1+A1S5B/A1S6B is used, the maximum number of extension base units is 3, and the maximum number of I/O
modules that can be mounted is 36 minus the number of CPU modules.
APPENDICES
Item
Number of CPU modules
and mounting position
I/O number assignment
Single CPU system
Only 1 module in the CPU slot
Slot 0 is 00H.
Concept
Multiple CPU system
4 modules in the CPU slot to slot 2
Reference
Page 60,
Section 3.3.2
A slot on the right of the rightmost
Page 27,
CPU module is 00H.*1
Section 2.2
The number of mountable modules
Restrictions on the number
of mountable modules
The number of mountable
per system and the number of
Page 71,
modules differs depending on
controllable modules per CPU
Section 3.5
the CPU module type.
module differ depending on the
(1) (c)
CPU module type.
Access from CPU module(s)
to other modules
Access from GOTs
Access with instructions
using the link direct device
Relations between CPU modules
All modules can be controlled.
and other modules must be set in
"Control PLC" of PLC parameter.
Accessible
Accessible
Page 104,
CHAPTER 5
A GOT can access a Universal
Manual for
model QCPU of the specified CPU
the GOT
No.
used
Only control CPU is accessible.
Page 104,
Section 5.2
Manual for
Access range
the CC-Link
Access to CC-Link
Accessible
Only control CPU is accessible.
system
A
master/local
used
Accessible through a USB
cable/RS-232 cable/Ethernet cable
Access from peripherals
or over network.
cable/RS-232 cable/Ethernet
For access to the Motion CPU, PC
cable or over network.
CPU module, or C Controller
-
module, refer to the relevant
manual.
Clock data of the Universal model
Clock data used by CPU
No.2 to No.4
Not supported
Q00UCPU, Q01UCPU, and
Q02UCPU) is used.*2
Clock function
Clock data used by
intelligent function modules
(such as the QD75)
*1
QCPU (CPU No.1) (except the
Clock data of the Universal
Clock data of the Universal model
model QCPU is used.
QCPU (CPU No.1) is used.
Page 99,
Section 4.4
When a CPU module occupying two slots is mounted, the slot on the right of the CPU module will be 10H.
When a CPU module occupying three slots is mounted, the slot on the right of the CPU module will be 20H.
*2
When a Universal model QCPU (except the Q00UCPU, Q01UCPU, and Q02UCPU), Motion CPU (Q172DCPU(-S1),
Q173DCPU(-S1), Q172DSCPU, or Q173DSCPU), or C Controller module (Q12DCCPU-V, Q24DHCCPU-V, or
Q24DHCCPU-LS) is used as any of CPU No.2 to No.4, clock data in CPU No.1 can be used.
185
Appendix 2 Comparison with a Single CPU System
Accessible through a USB
Item
Single CPU system
Multiple CPU system
Reference
The entire system is reset by
Operation when a CPU
module is reset.
The entire system is reset by
resetting the Process CPU (CPU
resetting the Universal model
No.1).
QCPU.
(Resetting CPU No.2 to No.4
Page 102,
Section 4.6
individually is not allowed.)
If a stop error has occurred in the
Process CPU (CPU No.1), the
system stops. ("MULTI CPU
Operation when a stop error
Operation
has occurred in a CPU
DOWN" (error code: 7000) occurs in
The system stops.
module
CPU No.2 to No.4.)
If a stop error has occurred in CPU
Page 102,
Section 4.6
No.2 to No.4, the operation depends
on the parameter setting
("Operation Mode").
Whether to synchronize the startup
Multiple CPU system
synchronized startup
of CPU modules in the multiple CPU
Not supported
system or not can be set.
(The default is set to be
Page 168,
Section 6.5
synchronized.)
Communications by auto
refresh using the CPU
Total of 4 Settings per CPU module:
Not supported
shared memory
Total of all CPU modules: 8K words
CPU high speed
Page 122,
Section 6.1.1
Total memory capacity used by all
Communications by auto
refresh using the multiple
up to 2K words,
CPU modules:
Not supported
2 CPU modules: 14K words,
3 CPU modules: 13K words,
transmission area*1
Page 135,
Section 6.1.2
4 CPU modules: 12K words
Data communications is performed
Communications by
programs using the CPU
Communications
by using the TO, FROM instructions,
Not supported
shared memory
transmission area device
Page 150,
Section 6.1.3
(U3En\G).
between CPU
modules
and instructions using the cyclic
Communications between
Universal model QCPU and
Not supported
Motion CPU
Communications between
Universal model QCPU and
C Controller module/PC
Data communications is performed
Page 160,
by using five motion dedicated
Section 6.2,
instructions and three multiple CPU
Page 162,
transmission dedicated instructions.
Section 6.3.1
Data communications is performed
Not supported
by using the multiple CPU
transmission dedicated instruction.
CPU module
Page 164,
Section 6.3.2
Data communications is performed
Communications between
Universal model QCPUs
Not supported
by using two multiple CPU high-
Page 165,
speed transmission dedicated
Section 6.3.3
instructions.
• Writing data during RUN
• Time reserved for communication
Factors that increase scan
Scan time
time
• Writing data during RUN
• Time reserved for
communication processing
processing
• Refresh processing among CPU
modules in a multiple CPU
Page 192,
Appendix 4
system
• Waiting time
*1
186
When the Q00UCPU, Q01UCPU, or Q02UCPU is used as CPU No.1, this type of communications cannot be performed.
APPENDICES
Item
Single CPU system
Multiple CPU system
Reference
• Number of CPU modules
("Multiple CPU Setting")
• Control PLC setting ("I/O
Assignment")
• Out-of-group I/O setting ("Multiple
CPU Setting")
• Operation mode when a stop
error has occurred in a CPU
module ("Multiple CPU Setting")
Parameters added for
Parameter
multiple CPU systems
Not supported
• Multiple CPU synchronous startup
("Multiple CPU Setting")
• Multiple CPU high speed
transmission area setting
Page 80,
Section
4.2.2,Page
170,
Appendix 1
("Multiple CPU Setting")*1
• Communication area setting
("Refresh Setting")
• Settings of some parameters
must be the same for all the CPU
modules while others can be set
individually for each CPU module.
Supported only when a Universal
AnS/A series module*2
Caution
Supported
model QCPU is set as a control
CPU.
*1
*2
Page 188,
A
Appendix 3
When the Q00UCPU, Q01UCPU, or Q02UCPU is used as CPU No.1, this parameter cannot be set.
AnS/A series-compatible modules can be used with a Universal model QCPU with a serial number (first five digits) of
"13102" or later.
Appendix 2 Comparison with a Single CPU System
187
Appendix 3
Precautions for Using AnS/A Series Modules
(1) Multiple CPU system configuration for using AnS/A series modules
AnS/A series modules can be used in a multiple CPU system configuration where all of the following conditions
are met.
(a) CPU No.1
The following QCPU must be used.
• Universal model QCPU with a serial number (first five digits) of "13102" or later
• High Performance model QCPU
(b) CPU No.2 to No.4
The following CPU module must be used.
• Universal model QCPU with a serial number (first five digits) of "13102" or later
• High Performance model QCPU
• Motion CPU
• C Controller module
• PC CPU module
AnS/A series modules cannot be used in the system using the system configuration other than the above.
(2) Control CPU setting
Set either of the following QCPUs as a control CPU of AnS/A series modules.
• Universal model QCPU with a serial number (first five digits) of "13102" or later
• High Performance model QCPU
Note that only one CPU module can be set as a control CPU.
188
APPENDICES
Ex. When CPU No.2 is set as a control CPU
Set CPU No.2 as the control CPU of all slots where AnS/A series modules are mounted. If a different CPU
No. is set as a control CPU for any of the AnS/A series modules, "PARAMETER ERROR" (error code:
3009) will occur and the multiple CPU system will not start.
A control CPU is set for each slot.
Power
supply
module
CPU
0
1
2
3
4
5
6
7
8
9
10
11
CPU
module
CPU
module
CPU
module
CPU
module
module
module
module
module
module
module
module
module
module
1
2
3
4
1
1
2
2
3
4
4
4
4
Slot number
Control CPU setting
Q312B
Power
supply
module
12
13
14
15
16
17
18
19
AnS
series
module
AnS
series
module
AnS
series
module
AnS
series
module
AnS
series
module
AnS
series
module
AnS
series
module
AnS
series
module
2
2
2
2
2
2
2
2
A
Slot number
Set the same CPU module to all
the AnS/A series modules as
their control CPU.
Control CPU setting
QA1S68B
21
22
23
24
A series
module
A series
module
A series
module
A series
module
A series
module
2
2
2
2
2
25
26
27
Appendix 3 Precautions for Using AnS/A Series Modules
Power
supply
module
20
Slot number
Control CPU setting
QA68B
The control CPU setting shown above indicates the following:
CPU modules 1 to 4:
CPU number
Other than CPU modules:
Control CPU number
189
(3) Access ranges of controlled and non-controlled modules
Access ranges of the controlled and non-controlled modules in a multiple CPU system is shown below.
: Accessible ×: Inaccessible
Controlled
Access target
module
Buffer memory
190
("All CPUs Can Read All Inputs")
Disabled (not checked)
Enabled (checked)
×
×
Read
×
×
Write
×
×
Read
×
×
Write
×
×
Input (X)
Output (Y)
Non-controlled module
APPENDICES
(4) Precautions
(a) Accessible device ranges
When the following AnS/A series modules are used, accessible device ranges are restricted.
• A1SJ71J92-S3, AJ71J92-S3 type JEMANET interface module
• A1SD51S, AD51-S3, AD51H-S3 type intelligent communication module
• A1SJ71AP23Q, A1SJ71AR23Q, A1SJ71AT23BQ type MELSECNET local station data link module
Device
Input (X), Output (Y)
Accessible device range
X/Y0 to X/Y7FF
Internal relay (M), Latch relay (L)
M/L0 to M/L8191
Link relay (B)
B0 to BsFFF
Timer (T)
T0 to T2047
Counter (C)
C0 to C1023
Data register (D)
D0 to D6143
Link register (W)
W0 to WFFF
Annunciator (F)
F0 to F2047
(b) Unavailable modules
A
The following modules cannot be used.
Product
Model name
A1SJ71LP21, A1SJ71BR11, A1SJ71QLP21, A1SJ71QLP21S,
MELSECNET/10 network module
A1SJ71QLP21GE, A1SJ71QBR11, AJ71LP21, AJ71LP21G,
AJ71BR11, AJ71LR21, AJ71QLP21, AJ71QLP21S, AJ71QLP21G,
MELSECNET (II), /B data link module
Ethernet interface module
A1SJ71AP21, A1SJ71AR21, A1SJ71AT21B, AJ71AP21, AJ71AP21S3, AJ71AR21, AJ71AT21B
A1SJ71QE71-B2-S3(-B5-S3), A1SJ71E71-B2-S3(-B5-S3),
AJ71QE71N-B2(-B5T), AJ71E71N-B2(-B5T)
Serial communication module, computer link
A1SJ71QC24(N), A1SJ71UC24-R2(-PRF), AJ71QC24(N),
module
AJ71QC24N-R2(-R4), A1SJ71UC24, AJ71UC24
Computer link/multidrop link module
A1SJ71UC24-R4*1
CC-Link master/local module
A1SJ61QBT11, A1SJ61BT11, AJ61QBT11, AJ61BT11
ME-NET interface module
A1SJ71ME81, AJ71ME81
*1
Only the multidrop link function is supported. The computer link and printer functions are not supported.
(c) Modules that require program modification
Dedicated instructions for the following special function modules cannot be used. Modify the program using the
FROM/TO instructions.
Product
Model name
High-speed counter module
A1SD61, A1SD62, A1SD62D(-S1), A1SD62E, AD61, AD61S1
MELSECNET/MINI-S3
A1SJ71PT32-S3, A1SJ71T32-S3, AJ71PT32-S3, AJ71T32-S3
Positioning module
ID module
A1SD75P1-S3(P2-S3/P3-S3), AD75M1(M2/M3), AD75P1-S3(P2S3/P3-S3)
A1SJ71ID1-R4, A1SJ71ID2-R4, AJ71ID1-R4, AJ71ID2-R4
191
Appendix 3 Precautions for Using AnS/A Series Modules
AJ71QBR11, AJ71QLR21
Appendix 4
Appendix 4.1
Processing Time
Concept of scan time
The concept of scan time in a multiple CPU system is the same as that in a single CPU system.
This section describes how to calculate the processing time when a multiple CPU system is configured.
(1) I/O refresh time
For the calculating formula of I/O refresh time, refer to the following.
User's Manual (Function Explanation, Program Fundamentals) for the CPU module used
The I/O refresh time increases by the time obtained by the following calculation when more than one CPU
module simultaneously accesses I/O modules and intelligent function modules through the bus .
(Extended time) =
(Number of input points + Number of output points)
16
N3
(Number of other CPU modules) (µs)
Use the following value for N3.
N3
QCPU
System with a main base unit
System including extension
only
base unit(s)
8.7µs
21µs
Q00CPU, Q01CPU
Q02(H)CPU, Q06HCPU, Q12HCPU,
Q25HCPU
Q02PHCPU, Q06PHCPU, Q12PHCPU,
Q25PHCPU
Q00UCPU, Q01UCPU, Q02UCPU,
Q03UD(E)CPU, Q04UD(E)HCPU,
Q06UD(E)HCPU, Q10UD(E)HCPU,
Q13UD(E)HCPU, Q20UD(E)HCPU,
Q26UD(E)HCPU, Q50UDEHCPU,
Q100UDEHCPU
Q03UDVCPU, Q04UDVCPU,
Q06UDVCPU, Q13UDVCPU, Q26UDVCPU
(2) Total instruction execution time
For the processing time of the multiple CPU system dedicated instructions and the processing time of instructions
whose processing times differ between in a single CPU system and a multiple CPU system, refer to the following.
MELSEC-Q/L Programming Manual (Common Instruction)
192
APPENDICES
(3) Common processing time
In a multiple CPU system, the common processing time increases as shown below.
QCPU
Q00CPU, Q01CPU
Q02CPU
Common processing time
(0.05 to 0.13) × (Number of other CPU modules) ms
0.02ms
Q02HCPU, Q06HCPU, Q12HCPU,
Q25HCPU
Q02PHCPU, Q06PHCPU, Q12PHCPU,
0.03ms
Q25PHCPU
Q00UCPU, Q01UCPU, Q02UCPU,
Q03UD(E)CPU, Q04UD(E)HCPU,
Q06UD(E)HCPU, Q10UD(E)HCPU,
Q13UD(E)HCPU, Q20UD(E)HCPU,
Q26UD(E)HCPU, Q50UDEHCPU,
0.02ms
Q100UDEHCPU
Q03UDVCPU, Q04UDVCPU,
Q06UDVCPU, Q13UDVCPU, Q26UDVCPU
A
Appendix 4 Processing Time
Appendix 4.1 Concept of scan time
193
Appendix 4.2
Factors that increase scan time
The processing time in a multiple CPU system increases from that in a single CPU system when the following
functions are used.
When any of the following functions is used, add the time values described in this section to the values calculated on
Page 192, Appendix 4.1.
• Auto refresh of the CPU shared memory (including the multiple CPU high speed transmission function)
• Refresh of CC-Link IE and MELSECNET/H
• Auto refresh of CC-Link
(1) Auto refresh of the CPU shared memory (including the multiple CPU high
speed transmission function)
(a) Auto refresh time of the CPU shared memory
This is the time required for executing refresh set in "Communication Area Setting (Refresh Setting)" and
"Multiple CPU High Speed Transmission Area Setting" of PLC parameter ("Multiple CPU Setting"). The value is
the total amount of time required for the CPU module to write data to its own CPU shared memory and read
data from the CPU shared memory of other CPU modules.
The time value needs to be added when refresh is set in "Communication Area Setting (Refresh Setting)" and
"Multiple CPU High Speed Transmission Area Setting" of PLC parameter ("Multiple CPU Setting").
(b) Calculating formula
The time value is obtained by the following calculation.
• For the Basic model QCPU
(Auto refresh time)
= (N1 + (Number of send word points) N2) +
(N3 + (Number of other CPU modules) N4 + (Number of receive word points)
N5) (µs)
The number of receive word points is the sum of the number of word points sent by other CPU modules.
Ex. When the number of CPU modules is 3 and the host CPU is CPU No.1
The number of receive word points will be the sum of the number of word points sent by CPU No.2 and
No.3.
Use the following values for N1 to N5.
Basic model QCPU
194
N1
N2
N3
N4
N5
Q00CPU
63µs
1.13µs
63µs
161µs
0.88µs
Q01CPU
57µs
1.03µs
57µs
146µs
0.80µs
APPENDICES
• For the High Performance model QCPU and Process CPU
(Auto refresh time) = (N1 + (Number of receive word points)
+ (N3 + (Number of send word points)
N2)
(Number of other CPU modules)
N4) (µs)
The number of receive word points is the sum of the number of word points sent by other CPU modules.
Ex. When the number of CPU modules is 4 and the host CPU is CPU No.1
The number of receive word points will be the sum of the number of word points sent by CPU No.2 to
No.4.
Use the following values for N1 to N4.
High Performance model QCPU,
Process CPU
Q02CPU
N1
N2
N3
N4
82µs
0.52µs
106µs
0.17µs
27µs
0.44µs
27µs
0.08µs
Q02HCPU, Q06HCPU, Q12HCPU,
Q25HCPU
Q02PHCPU, Q06PHCPU, Q12PHCPU,
Q25PHCPU
A
Appendix 4 Processing Time
Appendix 4.2 Factors that increase scan time
195
• For the Universal model QCPU
(Auto refresh time)
= (N1 + (Number of send word points) N2) +
(N3 + (Number of other CPU modules) N4 + (Number of receive word points)
N5) (µs)
The number of receive word points is the sum of the number of word points sent by other CPU modules.
Ex. When the number of CPU modules is 4 and the host CPU is CPU No.1
The number of receive word points will be the sum of the number of word points sent by CPU No.2 to
No.4.
For the auto refresh using the multiple CPU high speed transmission area, use the following values for N1 to
N5.
Universal model QCPU
Q00UCPU, Q01UCPU, Q02UCPU
Q03UD(E)CPU
N1
N2
N3
N4
N5
-
-
-
-
-
6µs
0.207µs
2µs
9µs
0.393µs
6µs
0.183µs
2µs
9µs
0.327µs
6µs
0.183µs
1µs
4µs
0.256µs
Q04UD(E)HCPU, Q06UD(E)HCPU,
Q10UD(E)HCPU, Q13UD(E)HCPU,
Q20UD(E)HCPU, Q26UD(E)HCPU,
Q50UDEHCPU, Q100UDEHCPU
Q03UDVCPU, Q04UDVCPU, Q06UDVCPU,
Q13UDVCPU, Q26UDVCPU
For the auto refresh using the CPU shared memory, use the following values for N1 to N5.
N1
N2
N3
N4
N5
Q00UCPU, Q01UCPU, Q02UCPU
Universal model QCPU
34µs
0.155µs
120µs
30µs
0.420µs
Q03UD(E)CPU
9µs
0.162µs
28µs
21µs
0.410µs
8µs
0.132µs
25µs
20µs
0.410µs
4µs
0.105µs
12µs
10µs
0.410µs
Q04UD(E)HCPU, Q06UD(E)HCPU,
Q10UD(E)HCPU, Q13UD(E)HCPU,
Q20UD(E)HCPU, Q26UD(E)HCPU,
Q50UDEHCPU, Q100UDEHCPU
Q03UDVCPU, Q04UDVCPU, Q06UDVCPU,
Q13UDVCPU, Q26UDVCPU
196
APPENDICES
(c) When auto refresh is executed by another CPU module during auto refresh
processing
The auto refresh time increases by the time obtained by the following calculation.
• For the Basic model QCPU
(Extended time) = 4
(Number of receive word points)
N6
(Number of other CPU modules) (µs)
Use the following value for N6.
N6
Basic model QCPU
Q00CPU, Q01CPU
System with a main base unit
System including extension
only
base unit(s)
0.54µs
1.30µs
• For the High Performance model QCPU, Process CPU, and Universal model QCPU
(Extended time) = (Number of send/receive word points) N5
(Number of other CPU modules) (µs)
Use the following value for N5.
A
N5
High Performance model QCPU,
Process CPU,
System with a main base unit
System including extension
Universal model QCPU
only
base unit(s)
0.54µs
1.30µs
Q02(H)CPU, Q06HCPU, Q12HCPU,
Q25HCPU
Q02PHCPU, Q06PHCPU, Q12PHCPU,
Appendix 4 Processing Time
Appendix 4.2 Factors that increase scan time
Q25HCPU
Q00UCPU, Q01UCPU, Q02UCPU,
Q03UD(E)CPU, Q04UD(E)HCPU,
Q06UD(E)HCPU, Q10UD(E)HCPU,
Q13UD(E)HCPU, Q20UD(E)HCPU,
Q26UD(E)HCPU, Q50UDEHCPU,
Q100UDEHCPU
Q03UDVCPU, Q04UDVCPU,
Q06UDVCPU, Q13UDVCPU, Q26UDVCPU
197
(2) Refresh of CC-Link IE and MELSECNET/H
(a) Refresh time of CC-Link IE and MELSECNET/H
This is the time required for executing refresh between a QCPU and a CC-Link IE module or MELSECNET/H
module. For each refresh time, refer to the following.
Reference manual for each network module used
(b) Calculating formula
In a multiple CPU system, if refresh is executed by a network module controlled by another CPU module during
refresh processing, the refresh time increases by the time obtained by the following calculation.
• For the Basic model QCPU
(Extended time) = 4
(Number of send/receive word points)
N6
(Number of other CPU modules) (µs)
The number of send/receive word points is the total points of the following transfer data.
(LB + LX + LY + SB)
+ LW + SW
Link refresh data:
16
Use the following value for N6.
N6
Basic model QCPU
System with a main base unit
System including extension
only
base unit(s)
0.54µs
1.30µs
Q00CPU, Q01CPU
• For the High Performance model QCPU, Process CPU, and Universal model QCPU
(Extended time) = (Number of send/receive word points)
N5
(Number of other CPU modules) (µs)
The number of send/receive word points is the total points of the following transfer data.
Link refresh data:
(LB + LX + LY + SB)
+ LW + SW
16
: card:
Data transferred to a file register in a memory card/SD memory
Interlink data transfer:
LB
+ LW
16
(LB + LX + LY + SB)
16
+ LW + SW
2
Use the following value for N5.
N5
High Performance model QCPU,
Process CPU,
System with a main base unit
System including extension
Universal model QCPU
only
base unit(s)
0.54µs
1.30µs
Q02(H)CPU, Q06HCPU, Q12HCPU,
Q25HCPU
Q02PHCPU, Q06PHCPU, Q12PHCPU,
Q25HCPU
Q00UCPU, Q01UCPU, Q02UCPU,
Q03UD(E)CPU, Q04UD(E)HCPU,
Q06UD(E)HCPU, Q10UD(E)HCPU,
Q13UD(E)HCPU, Q20UD(E)HCPU,
Q26UD(E)HCPU, Q50UDEHCPU,
Q100UDEHCPU
Q03UDVCPU, Q04UDVCPU,
Q06UDVCPU, Q13UDVCPU, Q26UDVCPU
198
APPENDICES
(3) Auto refresh of CC-Link
(a) Auto refresh time of CC-Link
This is the time required for executing refresh between a QCPU and a CC-Link master/local module.
For details, refer to the following.
MELSEC-Q CC-Link System Master/Local Module User's Manual
(b) Calculating formula
In a multiple CPU system, when auto refresh is requested by a CC-Link module controlled by another CPU
module during auto refresh processing, the auto refresh time increases by the time obtained by the following
calculation.
(Extended time) = (Number of send/receive word points)
N5
(Number of other CPU modules) (µs)
The number of send/receive word points is the total points of the following transfer data.
Link refresh data:
(RX + RY + SB)
16
+ SW
Use the following value for N5.
A
N5
QCPU
System with a main base unit
System including extension
only
base unit(s)
0.54µs
1.30µs
Q00CPU, Q01CPU
Q02(H)CPU, Q06HCPU, Q12HCPU,
Q25HCPU
Appendix 4 Processing Time
Appendix 4.2 Factors that increase scan time
Q02PHCPU, Q06PHCPU, Q12PHCPU,
Q25PHCPU
Q00UCPU, Q01UCPU, Q02UCPU,
Q03UD(E)CPU, Q04UD(E)HCPU,
Q06UD(E)HCPU, Q10UD(E)HCPU,
Q13UD(E)HCPU, Q20UD(E)HCPU,
Q26UD(E)HCPU, Q50UDEHCPU,
Q100UDEHCPU
Q03UDVCPU, Q04UDVCPU,
Q06UDVCPU, Q13UDVCPU, Q26UDVCPU
199
Appendix 4.3
Reducing processing time
(1) Multiple CPU system processing
CPU modules access I/O modules and intelligent function modules through a bus (base unit pattern or extension
cable). Note that only one CPU module can use the bus at a time.
If more than one CPU module attempts to use the bus simultaneously, the CPU module attempted access later is
placed in Standby status until the processing of the first CPU module is completed.
In a multiple CPU system, this waiting time will cause delay in input and output, and consequently the scan time
increases.
(2) Maximum waiting time
In a multiple CPU system, the waiting time of the host CPU will reach the maximum when:
• The maximum number of CPU modules allowed in the system is used.
• An extension base unit is used.
• An intelligent function module on an extension base unit has high volume of data.
• All the CPU modules (the maximum number allowed) in the system simultaneously access a module on the
extension base unit.
(3) How to reduce processing time
The following methods can be taken for reducing the processing time in a multiple CPU system.
• Mount modules with a large number of access points (such as CC-Link IE, MELSECNET/H, and CC-Link
modules) together on the main base unit.
• Set one QCPU as a control CPU for all modules with a large number of access points (such as CC-Link IE,
MELSECNET/H, and CC-Link modules) to prevent simultaneous access.
• Reduce the number of refresh points of the CC-Link IE, MELSECNET/H, and CC-Link modules.
• Reduce the number of auto refresh points between CPU modules.
The scan time can be reduced by changing the following PLC parameter settings:(
User's Manual (Function
Explanation, Program Fundamentals) for the CPU module used)
• "A-PLC Compatibility Setting" (except the Basic model QCPU)
• "Floating Point Arithmetic Processing" (High Performance model QCPU only)
200
INDEX
Comparison with a single CPU system . . . . . . . . . 175
Concept of multiple CPU system . . . . . . . . . . . . . . 24
Concept of scan time . . . . . . . . . . . . . . . . . . . . . 192
Control CPU (Control PLC) . . . . . . . . . . . . . . . 17,84
Control directions from QCPU to Motion CPU . . . . 160
Controlled module . . . . . . . . . . . . . . . . . . . . . . . . 17
CPU module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CPU module combinations and mounting positions
A
A series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
A series power supply module . . . . . . . . . . . . . . . . 17
Access from a programming tool. . . . . . . . . . . . . . 112
Access from the programming tool connected to
another station . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Access to controlled module . . . . . . . . . . . . . . . . . 104
Access to non-controlled modules. . . . . . . . . . . . . 104
Access to the intelligent function module buffer
memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Access using the link direct device . . . . . . . . . . . . 111
Addresses of the multiple CPU high speed
transmission area . . . . . . . . . . . . . . . . . . . . . . . . 151
Addresses of the user setting area . . . . . . . . . . . . 151
AnS series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
AnS series power supply module . . . . . . . . . . . . . . 16
Areas used for data communications by programs
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37,47,60
CPU numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
CPU shared memory. . . . . . . . . . . . . . . . . . . . . . 118
D.CHGA . . .
D.CHGAS . .
D.CHGT . . .
D.CHGT2. . .
D.CHGV . . .
D.CHGVS . .
D.DDRD . . .
D.DDWR . . .
D.GINT . . . .
D.SFCS . . . .
D.SVST . . . .
DP.CHGA . .
DP.CHGAS .
DP.CHGT . .
DP.CHGT2 .
DP.CHGV . .
DP.CHGVS .
DP.DDRD . .
DP.DDWR . .
DP.GINT . . .
DP.SFCS . . .
DP.SVST . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
B
. . . . . . . . . . . . . . . . . 16
. . . . . . . . . . . . . . . . . 15
. . . . . . . . . . . . . . . . . 17
. . . . . . . . . . . . . . . . . 15
C
C Controller module . . . . . . . . . . . . . . . . . . . . . . . 15
CC-Link IE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CC-Link IE module . . . . . . . . . . . . . . . . . . . . . . . . 17
CC-Link module . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Clock data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Clock data of CPU modules . . . . . . . . . . . . . . . . . . 99
Clock data of intelligent function modules . . . . . . . 100
Common processing time . . . . . . . . . . . . . . . . . . 193
Communication area setting (refresh setting) . . . . . . 82
Communication methods . . . . . . . . . . . . . . . . . . . 116
Communications among CPU modules . . . . . . . . . 116
Communications among CPU modules by dedicated
instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Communications among CPU modules when an
error is detected . . . . . . . . . . . . . . . . . . . . . . . . . 159
Communications by auto refresh (using the auto
refresh area) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Communications by auto refresh (using the multiple
CPU high speed transmission area) . . . . . . . . . . . 135
Communications by programs using the CPU
shared memory . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Communications using the CPU shared memory . . 118
4
D
Assurance of send data . . . . . . . . . . . . . . . . . . . . 154
ATA card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Auto refresh area . . . . . . . . . . . . . . . . . . . . . . . . 118
Auto refresh time of CC-Link . . . . . . . . . . . . . . . . 199
Auto refresh time of the CPU shared memory . . . . 194
Available CPU modules, base units, power supply
modules, and extension cables . . . . . . . . . . . 32,41,53
Available I/O modules and intelligent function
modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40,51
Base unit . . . . . . . . . . . . . .
Basic model QCPU . . . . . . .
Battery . . . . . . . . . . . . . . . .
Built-in Ethernet port QCPU .
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . 160
. . . . . . . . . . . . . . . . . . . . . . . . . . . 160
. . . . . . . . . . . . . . . . . . . . . . . . . . . 160
. . . . . . . . . . . . . . . . . . . . . . . . . . . 160
. . . . . . . . . . . . . . . . . . . . . . . . . . . 160
. . . . . . . . . . . . . . . . . . . . . . . . . . . 160
. . . . . . . . . . . . . . . . . . . . . . . 163,165
. . . . . . . . . . . . . . . . . . . . . . . 163,165
. . . . . . . . . . . . . . . . . . . . . . . 163,164
. . . . . . . . . . . . . . . . . . . . . . . . . . . 160
. . . . . . . . . . . . . . . . . . . . . . . . . . . 160
. . . . . . . . . . . . . . . . . . . . . . . . . . . 160
. . . . . . . . . . . . . . . . . . . . . . . . . . . 160
. . . . . . . . . . . . . . . . . . . . . . . . . . . 160
. . . . . . . . . . . . . . . . . . . . . . . . . . . 160
. . . . . . . . . . . . . . . . . . . . . . . . . . . 160
. . . . . . . . . . . . . . . . . . . . . . . . . . . 160
. . . . . . . . . . . . . . . . . . . . . . . 163,165
. . . . . . . . . . . . . . . . . . . . . . . 163,165
. . . . . . . . . . . . . . . . . . . . . . . 163,164
. . . . . . . . . . . . . . . . . . . . . . . . . . . 160
. . . . . . . . . . . . . . . . . . . . . . . . . . . 160
E
Ethernet module . . . . . . . .
Extended SRAM cassette .
Extension base unit . . . . .
Extension cable . . . . . . . .
. . . . . . . . . . . . . . . . . . 17
. . . . . . . . . . . . . . . . . . 17
. . . . . . . . . . . . . . . . . . 16
. . . . . . . . . . . . . . . . . . 17
F
Factors that increase scan time . . . . . . . . . . . . . . 194
Flash card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
G
GOT . . . . . . . . .
GX Configurator .
GX Developer . .
GX Works2 . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 17
. . . . . . . . . . . . . . . . . . . . . . . . . 66
. . . . . . . . . . . . . . . . . . . . . . . . . 65
. . . . . . . . . . . . . . . . . . . . . . . . . 65
201
7
I
H
N
High Performance model QCPU . . . . . . . . . . . . . . 15
High-speed Universal model QCPU . . . . . . . . . . . . 15
Host CPU operation information area . . . . . . . 118,121
Host station . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
How to check the host CPU number . . . . . . . . . . . . 26
How to check the multiple CPU parameter settings
No. of PLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Non-controlled module . . . . . . . . . . . . . . . . . . . . . 17
Number of mountable modules . . . . . . . . . . . . . . . 68
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Online module change . . . . . . . . . . . . . . . . . . . .
Operation mode. . . . . . . . . . . . . . . . . . . . . . . . .
Operation settings . . . . . . . . . . . . . . . . . . . . . . .
Output to output modules and intelligent function
modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
How to use the multiple CPU system parameters
set to another CPU module . . . . . . . . . . . . . . . . . . 85
I
I/O assignment . . . . . . . . . . . . . . . . . . . . . . . . . . 83
I/O number assignment . . . . . . . . . . . . . . . . . . . . 27
I/O numbers of CPU modules . . . . . . . . . . . . . . . . 30
I/O numbers of I/O modules and intelligent function
modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
I/O refresh time . . . . . . . . . . . . . . . . . . . . . . . . . 192
I/O sharing when using multiple CPUs . . . . . . . . . . 82
L
Life detection power supply module .
List of parameters . . . . . . . . . . . . .
Loading input (X) data . . . . . . . . . .
Loading output (Y) data . . . . . . . . .
. . . . . . . . . . . 17
. . . . . . . . . . 172
. . . . . . . . . . 105
. . . . . . . . . . 107
. 82
. 81
. 77
109
. 18
P
Parameter settings. . . . . . . . . . . . . . . . . . . . . . . . 80
Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Parameters required for a multiple CPU system . . 170
PC CPU module . . . . . . . . . . . . . . . . . . . . . . . . . 15
Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Points occupied by empty slot . . . . . . . . . . . . . . . . 80
Power supply module . . . . . . . . . . . . . . . . . . . . . . 16
Precautions for connecting a GOT . . . . . . . . . . . . . 74
Precautions for system configuration . . . . . . . . . . . 68
Precautions for using a Motion CPU (Q172DCPU(-S1),
Q173DCPU(-S1), Q172DSCPU, or Q173DSCPU)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Precautions for using a QCPU of function version A
M
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Main base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MELSECNET/H . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MELSECNET/H module . . . . . . . . . . . . . . . . . . . . 17
Memory card . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Memory configuration of the multiple CPU high
speed transmission area . . . . . . . . . . . . . . . . . . . 137
Model name . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Modules replaceable online . . . . . . . . . . . . . . . . . . 51
Modules that can load input (X) data . . . . . . . . . . 106
Modules that can load output (Y) data . . . . . . . . . 108
Modules that cannot load input (X) data . . . . . . . . 106
Modules that cannot load output (Y) data . . . . . . . 108
Modules that have restrictions when used with an
Universal model QCPU . . . . . . . . . . . . . . . . . . . . . 73
Motion CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Motion dedicated instructions . . . . . . . . . . . . . . . 160
Multiple CPU high speed main base unit . . . . . . . . . 16
Multiple CPU high speed transmission area . . . . . 118
Multiple CPU high speed transmission area setting
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Multiple CPU high speed transmission area settings
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Multiple CPU high-speed transmission
dedicated instructions . . . . . . . . . . . . . . . . . . . . . 163
Multiple CPU setting . . . . . . . . . . . . . . . . . . . . . . . 80
Multiple CPU synchronous interrupt . . . . . . . . . . . 166
Multiple CPU synchronous startup . . . . . . . . . . . . 168
Multiple CPU synchronous startup setting . . . . . . . . 81
Multiple CPU system configuration for using
AnS/A series modules . . . . . . . . . . . . . . . . . . . . 188
Multiple CPU transmission dedicated instructions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
202
Precautions for using AnS/A series modules
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188,191
Precautions for using the high-speed interrupt
function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Preventing inconsistency of 32-bit data . . . . . . . . 154
Preventing inconsistency of data exceeding 32 bits
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
. . . . . . . . . . . . . . . . . 75
. . . . . . . . . . . . . . . . . 15
. . . . . . . . . . . . . . . . 192
. . . . . . . . . . . . . . . . . 87
. . . . . . . . . . . . . . . . . 17
. . . . . . . . . . . . . . . . . 65
Procedure before operation
Process CPU . . . . . . . . . .
Processing time . . . . . . . . .
Program examples. . . . . . .
Programming tool . . . . . . .
PX Developer . . . . . . . . . .
Q
Q series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Q series power supply module . . . . . . . . . . . . . . .
Q172CPUN(-T) . . . . . . . . . . . . . . . . . . . . . . . . . .
Q172DCPU(-S1) . . . . . . . . . . . . . . . . . . . . . . . . .
Q172HCPU(-T) . . . . . . . . . . . . . . . . . . . . . . . . . .
Q173CPUN(-T) . . . . . . . . . . . . . . . . . . . . . . . . . .
Q173DCPU(-S1) . . . . . . . . . . . . . . . . . . . . . . . . .
Q173HCPU(-T) . . . . . . . . . . . . . . . . . . . . . . . . . .
QA1S6ADP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
QA6ADP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
QCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
QnU(D)(H)CPU . . . . . . . . . . . . . . . . . . . . . . . . . .
QnUDE(H)CPU . . . . . . . . . . . . . . . . . . . . . . . . . .
QnUDVCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
16
16
16
16
16
16
16
17
17
15
15
16
16
R
V
Reading data from the buffer memory . . . . . . . . . . 110
Reading/writing device data from/to Motion CPU . . 162
Reducing processing time . . . . . . . . . . . . . . . . . . 200
Redundant power extension base unit . . . . . . . . . . . 16
Redundant power main base unit . . . . . . . . . . . . . . 16
Redundant power supply base unit . . . . . . . . . . . . . 16
Redundant power supply module . . . . . . . . . . . . . . 17
Refresh time of CC-Link IE and MELSECNET/H
Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
W
When parameters for the multiple CPU system have
been changed . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Writing data to the buffer memory . . . . . . . . . . . . . 110
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Resetting a system . . . . . . . . . . . . . . . . . . . . . . . 101
4
S
S.CHGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
S.CHGT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
S.CHGV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
S.DDRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
S.DDWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
S.GINT . . . . . . . . . . . . . . . . . . . . . . . . . . . 162,164
S.SFCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
S.SVST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
SD memory card . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Slim type main base unit . . . . . . . . . . . . . . . . . . . . 16
Slim type power supply module . . . . . . . . . . . . . . . 17
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
SP.CHGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
SP.CHGT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
SP.CHGV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
SP.DDRD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
SP.DDWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
SP.GINT . . . . . . . . . . . . . . . . . . . . . . . . . . 162,164
SP.SFCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
SP.SVST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
SRAM card. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Starting interrupt programs from QCPU to
C Controller module/PC CPU module . . . . . . . . . . 164
Starting up multiple CPU system. . . . . . . . . . . . . . . 75
System area . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
System configuration . . . . . . . . . . . . . . . . . . . . . . . 31
System operation when a stop error occurs . . . . . . 102
System restoration procedure . . . . . . . . . . . . . . . . 103
System using Basic model QCPU as CPU No.1 . . . . 32
System using High Performance model QCPU or
Process CPU as CPU No.1 . . . . . . . . . . . . . . . . . . 41
System using Universal model QCPU as CPU No.1
7
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
T
Total instruction execution time . . . . . . . . . . . . . . 192
Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
U
Universal model QCPU . . . . . . . . . . . . . . . . . . . . . 15
User setting area . . . . . . . . . . . . . . . . . . . . . . . . 118
Uses of CPU numbers . . . . . . . . . . . . . . . . . . . . . . 25
Uses of I/O numbers of CPU modules . . . . . . . . . . . 30
203
REVISIONS
*The manual number is given on the bottom left of the back cover.
Print date
Manual number
January 2004
SH(NA)-080485ENG-A
May 2005
SH(NA)-080485ENG-B
Revision
First edition
Partial correction
TERMS, Chapter 1, Section 1.1, 2.1, 2.3, 2.4, 3.1, 3.3.1, 3.3.2, 3.4.1, 3.4.2, 3.8, 3.9,
3.10, 4.1.1, 4.1.2, 4.1.3, 6.1, 6.1.1, 7.1, 8.1, 8.2.2, 8.2.3, 8.2.4, 8.3.1, 8.3.4,
Appendix 1.1
August 2005
SH(NA)-080485ENG-C
Partial correction
TERMS, Section 2.1
April 2007
SH(NA)-080485ENG-D
Universal model QCPU model addition, and revision on the new functions of the
Universal model QCPU with a serial number (first five digits) of "09012"
Model addition
Q02UCPU, Q03UDCPU, Q04UDHCPU, Q06UDHCPU, Q61P, QA65B, QA68B
Partial correction
SAFETY PRECAUTIONS, MANUALS, TERMS, Section 1.1, 1.2, 1.3, 2.1.1, 2.1.2, 2.1.3,
2.2, 2.3, 2.4, 3.1.1, 3.1.2, 3.1.3, Chapter 4, Section 4.1, 4.1.1, 4.1.2, 4.1.3, 4.1.4, 4.1.5,
4.3.2, 5.1, 5.2, 6.1, 6.1.3, 6.1.4, 6.1.7, 6.1.8, 7.1, 8.1, 8.2.1, 8.2.2
August 2007
SH(NA)-080485ENG-E
Model addition
QA6ADP
Partial correction
TERMS, Section 1.1, 1.2, 1.3, 2.1.1, 2.1.2, 2.1.3, 2.2, 2.3, 3.1, 3.1.2, 3.1.3, 3.3.1, 3.8,
4.1, 4.1.2, 4.2.1, 4.3.1, 8.2.2, Appendix 1.1
March 2008
SH(NA)-080485ENG-F
Universal model QCPU model addition
Model addition
Q13UDHCPU, Q26UDHCPU
Partial correction
TERMS, Section 1.1.1, 1.2, 1.3, 2.1.1, 2.1.2, 2.1.3, 2.3, 2.4, 3.1, 3.1.1, 3.1.2, 3.1.3,
Chapter 4, Section 4.1.2, 4.1.3, 4.1.4, 4.1.5, 4.2.1, 4.3.1, 4.4, 4.5, 5.1, 5.2, 5.3, 6.1,
6.1.8, 7.1, 8.1, 8.2.1, 8.2.2, 8.3.1, 8.3.2
Addition
Section 4.3.3
May 2008
SH(NA)-080485ENG-G
Addition of Universal model QCPU and Process CPU models
Model addition
Q02PHCPU, Q06PHCPU, Q03UDECPU, Q04UDEHCPU, Q06UDEHCPU,
Q13UDEHCPU, Q26UDEHCPU
Partial correction
A term "MELSECNET/G" has been revised to "CC-Link IE Controller Network" through
this manual.
TERMS, Chapter 1, Section 1.1, 2.1.1, 2.1.2, 2.1.3, 2.2, 2.3, 2.4, 3.1, 3.8, 4.2, 4.3.1,
4.3.3, 5.1, 5.2, 6.1
204
Print date
Manual number
December 2008
SH(NA)-080485ENG-H
Revision
Addition of Universal model QCPU and C Controller module models
Model addition
Q00UCPU, Q01UCPU, Q10UDHCPU, Q20UDHCPU, Q10UDEHCPU, Q20UDEHCPU,
Q61P-D
Partial correction
MANUALS, TERMS, Chapter 1, Section 1.1, 1.3, 2.1.1, 2.1.2, 2.1.3, 2.3, 2.4, 3.1, 3.1.2,
3.1.3, 3.2, 3.3.2, 3.7, 3.9, 4.1.1, 4.1.2, 4.1.3, 4.1.4, 4.1.5, 4.3.1, 4.3.3, 4.5, 5.1, 5.2, 7.1,
8.1, 8.2.2
August 2009
SH(NA)-080485ENG-I
Partial correction
INTRODUCTION, MANUAL PAGE ORGANIZATION, TERMS, Section 1.1, 2.1.1, 2.1.2,
2.1.3, 2.2, 2.3, 2.4, 3.1, 3.1.2, 3.1.3, 6.1, 8.1
April 2010
SH(NA)-080485ENG-J
Universal model QCPU model addition, and revision on the new functions of the
Universal model QCPU with a serial number (first five digits) of "12012" or later
Model addition
Q50UDEHCPU, Q100UDEHCPU
Partial correction
SAFETY PRECAUTIONS, INTRODUCTION, MANUALS, MANUAL PAGE
ORGANIZATION, TERMS, Section 1.1, 1.2, 2.3, 2.4, 3.1, 3.3.2, 3.7, 4.1.3, 4.1.4, 4.2.1,
4.3.1, 5.1, 5.2, 5.3
June 2011
SH(NA)-080485ENG-K
Model addition
Q35DB
Partial correction
SAFETY PRECAUTIONS, INTRODUCTION, Section 2.1.1, 2.1.3, 2.2, 2.3, 2.4,
3.4.2, 3.10, 3.11, 4.1.2, 4.1.3, 6.1, 6.1.1, 8.2.1, 8.3.1
October 2011
SH(NA)-080485ENG-L
Revision on the new functions of the Universal model QCPU with a serial number (first
five digits) of "13102" or later
Model addition
QA1S51B
Partial correction
TERMS, Section 1.3, 2.1.1, 2.1.2, 2.1.3, 2.4, 7.1
May 2012
SH(NA)-080485ENG-M
Motion CPU model addition
Model addition
Q172DCPU-S1, Q173DCPU-S1, Q172DSCPU, Q173DSCPU
Partial correction
INTRODUCTION, TERMS, Section 1.1, 1.2, 1.3, 2.1.2, 2.1.3, 2.3, 2.4, 3.1, 3.1.3, 3.8.1,
3.11, Chapter 4, Section 4.1.3, 4.1.4, 4.1.5, 4.2, 4.2.1, 4.3, 4.3.1, 4.4, 4.5, 5.1, 5.2, 6.1.8
November 2012
SH(NA)-080485ENG-N
C Controller model addition
Model addition
Q24DHCCPU-V
Partial correction
TERMS, Section 1.1, 1.2, 1.3, 2.1.1, 2.1.2, 2.1.3, 2.3, 3.1, 3.1.1, 3.1.2, 3.1.3, 3.8.1, 3.11,
Chapter 4, Section 4.1.3, 4.1.4, 4.1.5, 4.2.1, 4.4, 4.5, 6.1.8
March 2013
SH(NA)-080485ENG-O
Complete revision due to layout change of the manual, and Universal model QCPU
model addition
Model addition
Q03UDVCPU, Q04UDVCPU, Q06UDVCPU, Q13UDVCPU, Q26UDVCPU
205
Print date
Manual number
September 2013
SH(NA)-080485ENG-P
Revision
C Controller model addition
Model addition
Q24DHCCPU-LS
Partial correction
MANUALS, TERMS, Chapter 1, Section 3.1.1, 3.1.2, 3.1.3, 3.2.1, 3.2.2, 3.2.3, 3.3.1,
3.3.2, 3.4, 3.5, 4.2.2, 4.4.1, 4.6, Chapter 6, Section 6.1.1, 6.1.2, 6.1.3, 6.1.4, 6.5,
Appendix 2, 3, 4.2
January 2014
SH(NA)-080485ENG-Q
Partial correction
Section 3.1.3, 3.5, 4.6
July 2014
SH(NA)-080485ENG-R
Model addition
QA1S6ADP
Partial correction
TERMS, Section 3.2.1, 3.3.1, 3.5, Appendix 2
Japanese manual version SH-080475-R
This manual confers no industrial property rights or any rights of any other kind, nor does it confer any patent licenses. Mitsubishi Electric
Corporation cannot be held responsible for any problems involving industrial property rights which may occur as a result of using the
contents noted in this manual.
© 2004 MITSUBISHI ELECTRIC CORPORATION
206
WARRANTY
Please confirm the following product warranty details before using this product.
1. Gratis Warranty Term and Gratis Warranty Range
If any faults or defects (hereinafter "Failure") found to be the responsibility of Mitsubishi occurs during use of the
product within the gratis warranty term, the product shall be repaired at no cost via the sales representative or
Mitsubishi Service Company.
However, if repairs are required onsite at domestic or overseas location, expenses to send an engineer will be
solely at the customer's discretion. Mitsubishi shall not be held responsible for any re-commissioning,
maintenance, or testing on-site that involves replacement of the failed module.
[Gratis Warranty Term]
The gratis warranty term of the product shall be for one year after the date of purchase or delivery to a designated
place.
Note that after manufacture and shipment from Mitsubishi, the maximum distribution period shall be six (6) months,
and the longest gratis warranty term after manufacturing shall be eighteen (18) months. The gratis warranty term of
repair parts shall not exceed the gratis warranty term before repairs.
[Gratis Warranty Range]
(1) The range shall be limited to normal use within the usage state, usage methods and usage environment, etc.,
which follow the conditions and precautions, etc., given in the instruction manual, user's manual and caution
labels on the product.
(2) Even within the gratis warranty term, repairs shall be charged for in the following cases.
1. Failure occurring from inappropriate storage or handling, carelessness or negligence by the user. Failure
caused by the user's hardware or software design.
2. Failure caused by unapproved modifications, etc., to the product by the user.
3. When the Mitsubishi product is assembled into a user's device, Failure that could have been avoided if
functions or structures, judged as necessary in the legal safety measures the user's device is subject to or
as necessary by industry standards, had been provided.
4. Failure that could have been avoided if consumable parts (battery, backlight, fuse, etc.) designated in the
instruction manual had been correctly serviced or replaced.
5. Failure caused by external irresistible forces such as fires or abnormal voltages, and Failure caused by
force majeure such as earthquakes, lightning, wind and water damage.
6. Failure caused by reasons unpredictable by scientific technology standards at time of shipment from
Mitsubishi.
7. Any other failure found not to be the responsibility of Mitsubishi or that admitted not to be so by the user.
2. Onerous repair term after discontinuation of production
(1) Mitsubishi shall accept onerous product repairs for seven (7) years after production of the product is
discontinued.
Discontinuation of production shall be notified with Mitsubishi Technical Bulletins, etc.
(2) Product supply (including repair parts) is not available after production is discontinued.
3. Overseas service
Overseas, repairs shall be accepted by Mitsubishi's local overseas FA Center. Note that the repair conditions at
each FA Center may differ.
4. Exclusion of loss in opportunity and secondary loss from warranty liability
Regardless of the gratis warranty term, Mitsubishi shall not be liable for compensation of damages caused by any
cause found not to be the responsibility of Mitsubishi, loss in opportunity, lost profits incurred to the user by Failures
of Mitsubishi products, special damages and secondary damages whether foreseeable or not, compensation for
accidents, and compensation for damages to products other than Mitsubishi products, replacement by the user,
maintenance of on-site equipment, start-up test run and other tasks.
5. Changes in product specifications
The specifications given in the catalogs, manuals or technical documents are subject to change without prior notice.
207
Microsoft, Windows, Windows Vista, Windows NT, Windows XP, Windows Server, Visio, Excel, PowerPoint, Visual Basic,
Visual C++, and Access are either registered trademarks or trademarks of Microsoft Corporation in the United States,
Japan, and other countries.
Intel, Pentium, and Celeron are either registered trademarks or trademarks of Intel Corporation
in the United States and other countries.
Ethernet is a registered trademark of Xerox Corp.
The SD and SDHC logos are either registered trademarks or trademarks of SD-3C, LLC.
All other company names and product names used in this manual are
either trademarks or registered trademarks of their respective companies.
208
SH(NA)-080485ENG-R
SH(NA)-080485ENG-R(1407)MEE
MODEL:
QCPU-U-MA-E
MODEL CODE: 13JR75
HEAD OFFICE : TOKYO BUILDING, 2-7-3 MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN
NAGOYA WORKS : 1-14 , YADA-MINAMI 5-CHOME , HIGASHI-KU, NAGOYA , JAPAN
When exported from Japan, this manual does not require application to the
Ministry of Economy, Trade and Industry for service transaction permission.
Specifications subject to change without notice.
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