Texas Instruments | OPAx990 40-V Rail-to-Rail Input/Output, Low Offset Voltage, Low Power Op Amp (Rev. E) | Datasheet | Texas Instruments OPAx990 40-V Rail-to-Rail Input/Output, Low Offset Voltage, Low Power Op Amp (Rev. E) Datasheet

Texas Instruments OPAx990 40-V Rail-to-Rail Input/Output, Low Offset Voltage, Low Power Op Amp (Rev. E) Datasheet
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OPA990, OPA2990, OPA4990
SBOS933E – FEBRUARY 2019 – REVISED DECEMBER 2019
OPAx990 40-V Rail-to-Rail Input/Output, Low Offset Voltage, Low Power Op Amp
1 Features
3 Description
•
•
•
•
•
•
•
The OPAx990 family (OPA990, OPA2990, and
OPA4990) is a family of high voltage (40-V) general
purpose operational amplifiers. These devices offer
excellent DC precision and AC performance,
including rail-to-rail input/output, low offset (±300 µV,
typ), and low offset drift (±0.6 µV/°C, typ).
1
•
•
•
•
•
•
Low offset voltage: ±300 µV
Low offset voltage drift: ±0.6 µV/°C
Low noise: 30 nV/√Hz at 1 kHz
High common-mode rejection: 115 dB
Low bias current: ±10 pA
Rail-to-rail input and output
MUX-friendly/comparator inputs
– Amplifier operates with differential inputs up to
supply rail
– Amplifier can be used in open-loop or as
comparator
Wide bandwidth: 1.1-MHz GBW
High slew rate: 4.5 V/µs
Low quiescent current: 120 µA per amplifier
Wide supply: ±1.35 V to ±20 V, 2.7 V to 40 V
Robust EMIRR performance: 78 dB at 1.8 GHz
Differential and common-mode input voltage
range to supply rail
Unique features such as differential and commonmode input voltage range to the supply rail, high
short-circuit current (±80 mA), high slew rate (4.5
V/µs), and shutdown make the OPAx990 an
extremely flexible, robust, and high-performance op
amp for high-voltage industrial applications.
The OPAx990 family of op amps is available in microsize packages (such as X2QFN, WSON, and SOT553), as well as standard packages (such as SOT-23,
SOIC, and TSSOP), and is specified from –40°C to
125°C.
Device Information(1)
PART NUMBER
OPA990
2 Applications
•
•
•
•
•
•
•
•
•
Multiplexed data-acquisition systems
Test and measurement equipment
Motor drive: power stage and control modules
Power delivery: UPS, server, and merchant
network power
ADC driver and reference buffer amplifier
Programmable logic controllers
Analog input and output modules
High-side and low-side current sensing
High precision comparator
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
SOT-23 (6)
2.90 mm × 1.60 mm
SC70 (5)
2.00 mm × 1.25 mm
SOT-553 (5)(2)
1.60 mm × 1.20 mm
SOIC (8)
4.90 mm × 3.90 mm
(2)
OPA2990
OPA4990
SOT-23 (8)
2.90 mm × 1.60 mm
TSSOP (8)
3.00 mm × 4.40 mm
VSSOP (8)(2)
3.00 mm × 3.00 mm
WSON (8)
2.00 mm × 2.00 mm
X2QFN (10)(2)
2.00 mm × 1.50 mm
SOIC (14)
8.65 mm × 3.90 mm
TSSOP (14)
5.00 mm × 4.40 mm
WQFN (16)(2)
3.00 mm × 3.00 mm
X2QFN (14)(2)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) This package is preview only.
OPAx990 in a High-Voltage, Multiplexed, Data-Acquisition System
Analog Inputs
REF3140
Bridge Sensor
OPA990
Gain Network
Gain Network
RC Filter
OPA375
RC Filter
Reference Driver
+
MUX509
Thermocouple
+
Current Sensing
LED
Photo
Detector
Optical Sensor
High-Voltage Multiplexed Input
REF
OPA990
+
Gain Network
Gain Network
OPA990
High-Voltage Level Translation
VINP
Antialiasing
Filter
ADS8860
VINM
VCM
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA990, OPA2990, OPA4990
SBOS933E – FEBRUARY 2019 – REVISED DECEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features .................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions ......................... 4
Specifications....................................................... 10
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7
Absolute Maximum Ratings ....................................
ESD Ratings............................................................
Recommended Operating Conditions.....................
Thermal Information for Single Channel .................
Thermal Information for Dual Channel....................
Thermal Information for Quad Channel ..................
Electrical Characteristics.........................................
Typical Characteristics ............................................
10
10
10
10
11
11
12
15
Detailed Description ............................................ 23
7.1 Overview ................................................................. 23
7.2 Functional Block Diagram ....................................... 23
7.3 Feature Description................................................. 24
7.4 Device Functional Modes........................................ 31
8
Application and Implementation ........................ 32
8.1 Application Information............................................ 32
8.2 Typical Applications ................................................ 32
9 Power Supply Recommendations...................... 34
10 Layout................................................................... 34
10.1 Layout Guidelines ................................................. 34
10.2 Layout Example .................................................... 34
11 Device and Documentation Support ................. 37
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
37
37
37
38
38
38
38
38
12 Mechanical, Packaging, and Orderable
Information ........................................................... 38
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (July 2019) to Revision E
Page
•
Changed the OPA990 and OPA4990 device statuses from Advance Information to Production Data ................................. 1
•
Removed preview notation from OPA990 SOT-23 (5) package from Device Information table ............................................ 1
•
Removed preview notation from OPA990S SOT-23 (6) package from Device Information table.......................................... 1
•
Removed preview notation from OPA990 SC70 (5) package from Device Information table................................................ 1
•
Removed preview notation from OPA4990 SOIC (14) package from Device Information table............................................ 1
•
Removed preview notation from OPA4990 TSSOP (14) package from Device Information table ........................................ 1
•
Removed preview notation from OPA990 DBV package (SOT-23) in the Pin Configuration and Functions section ............ 4
•
Removed preview notation from OPA990 DCK package (SC70) in the Pin Configuration and Functions section ............... 4
•
Removed preview notation from OPA990S DBV package (SOT-23) in the Pin Configuration and Functions section.......... 4
•
Removed preview notation from OPA4990 D (SOIC) and TSSOP (PW) packages in the Pin Configuration and
Functions section.................................................................................................................................................................... 7
Changes from Revision C (May 2019) to Revision D
Page
•
Removed preview notation from OPA2990 WSON (8) package from Device Information table ........................................... 1
•
Removed preview notation from OPA2990 DSG package (WSON) in the Pin Configuration and Functions section ........... 5
•
Added SHUTDOWN to Electrical Characteristics table........................................................................................................ 13
•
Added Shutdown section to the Detailed Description section .............................................................................................. 31
Changes from Revision B (April 2019) to Revision C
Page
•
Removed preview notation from OPA2990 TSSOP (8) package from Device Information table .......................................... 1
•
Removed preview notation from OPA2990 PW package (TSSOP) in the Pin Configuration and Functions section ............ 5
2
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SBOS933E – FEBRUARY 2019 – REVISED DECEMBER 2019
Changes from Revision A (March 2019) to Revision B
Page
•
Removed preview notation from OPA2990 SOIC (8) package from Device Information table.............................................. 1
•
Removed preview notation from OPA2990 D package (SOIC) in the Pin Configuration and Functions section................... 5
Changes from Original (February 2019) to Revision A
•
Page
Changed the OPA2990 device status from Advance Information to Production Data ........................................................... 1
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3
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SBOS933E – FEBRUARY 2019 – REVISED DECEMBER 2019
www.ti.com
5 Pin Configuration and Functions
OPA990 DBV and DRL Package(1)
5-Pin SOT-23 and SOT-553
Top View
OUT
1
V±
5
OPA990 DCK Package
5-Pin SC70
Top View
V+
IN+
1
V±
2
IN±
3
5
V+
4
OUT
2
IN+
3
4
IN±
Not to scale
Not to scale
(1)
DRL package is preview only.
Pin Functions: OPA990
PIN
NAME
I/O
DESCRIPTION
DBV and DRL
DCK
IN+
3
1
I
Noninverting input
IN–
4
3
I
Inverting input
OUT
1
4
O
Output
V+
5
5
—
Positive (highest) power supply
V–
2
2
—
Negative (lowest) power supply
OPA990S DBV and DRL Package(1)
6-Pin SOT-23 and SOT-563
Top View
+IN
1
6
V+
V±
2
5
SHDN
±IN
3
4
OUT
Not to scale
(1)
DRL package is preview only.
Pin Functions: OPA990S
PIN
NAME
DBV and DRL
I/O
DESCRIPTION
IN+
3
I
Noninverting input
IN–
4
I
Inverting input
OUT
1
O
Output
SHDN
5
I
Shutdown: low = amplifier enabled, high = amplifier disabled. See Shutdown
section for more information.
V+
6
—
Positive (highest) power supply
V–
2
—
Negative (lowest) power supply
4
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SBOS933E – FEBRUARY 2019 – REVISED DECEMBER 2019
OPA2990 D, DDF, DGK, and PW Packages(1)
8-Pin SOIC, SOT-23-8, TSSOP, and VSSOP
Top View
OPA2990 DSG Package(1)
8-Pin WSON With Exposed Thermal Pad
Top View
OUT1
1
8
V+
IN1±
2
7
OUT2
OUT1
1
IN1+
3
6
IN2±
IN1±
2
V±
4
5
IN2+
IN1+
3
V±
4
Thermal
Pad
8
V+
7
OUT2
6
IN2±
5
IN2+
Not to scale
(1)
DDF and DGK packages are preview only.
Not to scale
(1)
Connect thermal pad to V–. See Packages
With an Exposed Thermal Pad section for
more information.
Pin Functions: OPA2990
PIN
SOIC, TSSOP,
VSSOP, and
WSON
I/O
IN1+
3
I
Noninverting input, channel 1
IN1–
2
I
Inverting input, channel 1
IN2+
5
I
Noninverting input, channel 2
IN2–
6
I
Inverting input, channel 2
OUT1
1
O
Output, channel 1
OUT2
7
O
Output, channel 2
V+
8
—
Positive (highest) power supply
V–
4
—
Negative (lowest) power supply
NAME
DESCRIPTION
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OPA2990S DGS Package(1)
10-Pin VSSOP
Top View
OPA2990S RUG Package(1)
10-Pin X2QFN
Top View
10
V+
IN1±
2
9
OUT2
IN1+
3
8
IN2±
V±
4
7
IN2+
SHDN1
5
6
SHDN2
IN1+
1
Not to scale
1
9
IN1±
SHDN1
2
8
OUT1
SHDN2
3
7
V+
IN2+
4
6
OUT2
Package is preview only.
5
(1)
V±
10
OUT1
IN2±
Not to scale
(1)
Package is preview only.
Pin Functions: OPA2990S
PIN
NAME
I/O
DESCRIPTION
VSSOP
X2QFN
IN1+
3
10
I
Noninverting input, channel 1
IN1–
2
9
I
Inverting input, channel 1
IN2+
7
4
I
Noninverting input, channel 2
IN2–
8
5
I
Inverting input, channel 2
OUT1
1
8
O
Output, channel 1
OUT2
9
6
O
Output, channel 2
SHDN 1
5
2
I
Shutdown, channel 1: low = amplifier enabled, high = amplifier
disabled. See Shutdown section for more information.
SHDN 2
6
3
I
Shutdown, channel 2: low = amplifier enabled, high = amplifier
disabled. See Shutdown section for more information.
V+
10
7
—
Positive (highest) power supply
V–
4
1
—
Negative (lowest) power supply
6
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Product Folder Links: OPA990 OPA2990 OPA4990
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SBOS933E – FEBRUARY 2019 – REVISED DECEMBER 2019
OPA4990 D and PW Packages
14-Pin SOIC and TSSOP
Top View
13
IN4±
IN1+
3
12
IN4+
V+
4
11
V±
IN2+
5
10
IN3+
IN2±
6
9
IN3±
OUT2
7
8
OUT3
IN1±
1
IN1+
2
V+
12
IN4±
11
IN4+
3
10
V±
IN2+
4
9
IN3+
IN2±
5
8
IN3±
Not to scale
1
V+
2
IN1±
OUT1
OUT4
IN4±
16
15
14
13
OUT2
OPA4990 RTE Package(1)(2)
16-Pin WQFN With Exposed Thermal Pad
Top View
IN1+
(1)
12
IN4+
11
V±
10
IN3+
9
IN3±
OUT4
2
13
IN1±
7
OUT4
OUT3
14
14
1
6
OUT1
OUT1
OPA4990 RUC Packages(1)
14-Pin X2QFN With Exposed Thermal Pad
Top View
Not to scale
Package is preview only.
Thermal
6
7
8
NC
OUT3
4
NC
IN2±
Pad
5
3
OUT2
IN2+
Not to scale
(1)
Connect thermal pad to V–. See Packages
With an Exposed Thermal Pad section for
more information.
(2)
Package is preview only.
Pin Functions: OPA4990
PIN
NAME
SOIC and
TSSOP
WQFN
X2QFN
I/O
DESCRIPTION
IN1+
3
1
2
I
Noninverting input, channel 1
IN1–
2
16
1
I
Inverting input, channel 1
IN2+
5
3
4
I
Noninverting input, channel 2
IN2–
6
4
5
I
Inverting input, channel 2
IN3+
10
10
9
I
Noninverting input, channel 3
IN3–
9
9
8
I
Inverting input, channel 3
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Pin Functions: OPA4990 (continued)
PIN
I/O
DESCRIPTION
SOIC and
TSSOP
WQFN
X2QFN
IN4+
12
12
11
I
Noninverting input, channel 4
IN4–
13
13
12
I
Inverting input, channel 4
NC
—
6, 7
—
—
Do not connect
OUT1
1
15
14
O
Output, channel 1
OUT2
7
5
6
O
Output, channel 2
NAME
OUT3
8
8
7
O
Output, channel 3
OUT4
14
14
13
O
Output, channel 4
V+
4
2
3
—
Positive (highest) power supply
V–
11
11
10
—
Negative (lowest) power supply
8
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SBOS933E – FEBRUARY 2019 – REVISED DECEMBER 2019
IN1+
1
V+
2
IN1±
OUT1
OUT4
IN4±
16
15
14
13
OPA4990S RTE Package(1)
16-Pin WQFN With Exposed Thermal Pad
Top View
12
IN4+
11
V±
10
IN3+
9
IN3±
Thermal
6
7
8
SHDN34
OUT3
4
SHDN12
IN2±
Pad
5
3
OUT2
IN2+
Not to scale
(1)
Connect thermal pad to V–. See Packages With an Exposed Thermal Pad section for more information.
(2)
Package is preview only.
Pin Functions: OPA4990S
PIN
NAME
WQFN
I/O
DESCRIPTION
IN1+
1
I
Noninverting input, channel 1
IN1–
16
I
Inverting input, channel 1
IN2+
3
I
Noninverting input, channel 2
IN2–
4
I
Inverting input, channel 2
IN3+
10
I
Noninverting input, channel 3
IN3–
9
I
Inverting input, channel 3
IN4+
12
I
Noninverting input, channel 4
IN4–
13
I
Inverting input, channel 4
OUT1
15
O
Output, channel 1
OUT2
5
O
Output, channel 2
OUT3
8
O
Output, channel 3
OUT4
14
O
Output, channel 4
SHDN12
6
I
Shutdown, channels 1 and 2: low = amplifiers enabled, high = amplifiers
disabled. See Shutdown section for more information.
SHDN34
7
I
Shutdown, channels 3 and 4: low = amplifiers enabled, high = amplifiers
disabled. See Shutdown section for more information.
VCC+
2
—
Positive (highest) power supply
VCC–
11
—
Negative (lowest) power supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
MIN
MAX
0
42
V
(V–) – 0.5
(V+) + 0.5
V
Supply voltage, VS = (V+) – (V–)
Common-mode voltage (2)
Differential voltage (2)
Signal input pins
VS + 0.2
Current (2)
–10
Output short-circuit (3)
–55
Junction temperature, TJ
Storage temperature, Tstg
(2)
(3)
V
10
mA
150
°C
150
°C
150
°C
Continuous
Operating ambient temperature, TA
(1)
UNIT
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package. Extended short-circuit current, especially with higher supply voltage, can cause
excessive heating and eventual destruction. See the Thermal Protection section for more information.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
MAX
2.7
40
UNIT
V
(V–) – 0.2
(V+) + 0.2
V
(V–) + 1.1
(V–) + 20 V (1)
V
VS
Supply voltage, (V+) – (V–)
VI
Input voltage range
VIH
High level input voltage at shutdown pin (amplifier enabled)
VIL
Low level input voltage at shutdown pin (amplifier disabled)
(V–)
(V–) + 0.2
V
TA
Specified temperature
–40
125
°C
(1)
Cannot exceed V+.
6.4 Thermal Information for Single Channel
OPA990, OPA990S
THERMAL METRIC
DBV
(SOT-23)
(1)
DRL (2)
(SOT-553)
DCK
(SC70)
UNIT
5 PINS
6 PINS
5 PINS
5 PINS
6 PINS
RθJA
Junction-to-ambient thermal resistance
192.1
1174.5
204.6
TBD
TBD
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
113.6
113.4
116.5
TBD
TBD
°C/W
RθJB
Junction-to-board thermal resistance
60.5
55.8
51.8
TBD
TBD
°C/W
ψJT
Junction-to-top characterization parameter
37.2
39.6
24.9
TBD
TBD
°C/W
ψJB
Junction-to-board characterization parameter
60.3
55.6
51.5
TBD
TBD
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
TBD
TBD
°C/W
(1)
(2)
10
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
This package option is preview for OPA990.
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6.5 Thermal Information for Dual Channel
OPA2990, OPA2990S
THERMAL METRIC (1)
D
(SOIC)
DDF (2)
(SOT-23-8)
DGK (2)
(VSSOP)
DGS (2)
(VSSOP)
DSG
(WSON)
PW
(TSSOP)
RUG (2)
(X2QFN)
UNIT
8 PINS
8 PINS
8 PINS
10 PINS
8 PINS
8 PINS
10 PINS
RθJA
Junction-to-ambient
thermal resistance
138.7
TBD
189.3
152.2
81.6
188.4
TBD
°C/W
RθJC(top)
Junction-to-case (top)
thermal resistance
78.7
TBD
75.8
67.3
101.6
77.1
TBD
°C/W
RθJB
Junction-to-board thermal
resistance
82.2
TBD
111.0
95.5
48.3
119.1
TBD
°C/W
ψJT
Junction-to-top
characterization parameter
27.8
TBD
15.4
67.9
6.0
14.2
TBD
°C/W
ψJB
Junction-to-board
characterization parameter
81.4
TBD
109.3
94.3
48.3
117.4
TBD
°C/W
RθJC(bot)
Junction-to-case (bottom)
thermal resistance
N/A
TBD
N/A
N/A
22.8
N/A
TBD
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
This package option is preview for OPA2990.
6.6 Thermal Information for Quad Channel
OPA4990, OPA4990S
THERMAL METRIC (1)
D
(SOIC)
PW
(TSSOP)
RTE (2)
(WQFN)
RUC (2)
(WQFN)
UNIT
14 PINS
14 PINS
16 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
105.2
134.7
53.5
143.0
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
61.2
55.0
58.3
46.4
°C/W
RθJB
Junction-to-board thermal resistance
61.1
79.0
28.6
81.8
°C/W
ψJT
Junction-to-top characterization parameter
21.4
9.2
2.1
1.0
°C/W
ψJB
Junction-to-board characterization parameter
60.7
78.1
28.6
81.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
12.6
N/A
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
This package option is preview for OPA4990.
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6.7 Electrical Characteristics
For VS = (V+) – (V–) = 2.7 V to 40 V (±1.35 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT
= VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
VCM = V–
dVOS/dT
Input offset voltage drift
PSRR
Input offset voltage versus
power supply
VCM = V–, VS = 4 V to 40 V
Channel separation
f = 0 Hz
±0.3
TA = –40°C to 125°C
TA = –40°C to 125°C
VCM = V–, VS = 2.7 V to 40 V (1)
±1.5
mV
±1.75
±0.6
TA = –40°C to 125°C
µV/℃
±0.1
±1.3
±0.75
±6.6
5
µV/V
µV/V
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
±10
pA
±5
pA
NOISE
EN
Input voltage noise
eN
Input voltage noise density
iN
Input current noise
f = 0.1 Hz to 10 Hz
6
µVPP
1
µVRMS
f = 1 kHz
30
f = 10 kHz
28
f = 1 kHz
2
nV/√Hz
fA/√Hz
INPUT VOLTAGE RANGE
Common-mode voltage
range
VCM
CMRR
Common-mode rejection
ratio
(V–) – 0.2
(V+) + 0.2
VS = 40 V, (V–) – 0.1 V < VCM <
(V+) – 2 V (PMOS pair)
100
115
VS = 4 V, (V–) – 0.1 V < VCM <
(V+) – 2 V (PMOS pair)
75
90
70
90
VS = 2.7 V, (V–) – 0.1 V < VCM <
(V+) – 2 V (PMOS pair) (1)
V
dB
TA = –40°C to 125°C
VS = 2.7 – 40 V, (V+) – 1 V < VCM
< (V+) + 0.1 V (NMOS pair)
80
See Offset Voltage (Transition Region)
in the Typical Characteristics section
(V+) – 2 V < VCM < (V+) – 1 V
INPUT CAPACITANCE
ZID
Differential
ZICM
Common-mode
100 || 3
MΩ || pF
6 || 1
TΩ || pF
OPEN-LOOP GAIN
VS = 40 V, VCM = VS / 2,
(V–) + 0.1 V < VO < (V+) – 0.1 V
AOL
Open-loop voltage gain
VS = 4 V, VCM = VS / 2,
(V–) + 0.1 V < VO < (V+) – 0.1 V
VS = 2.7 V, VCM = VS / 2,
(V–) + 0.1 V < VO < (V+) – 0.1
V (1)
(1)
12
120
TA = –40°C to 125°C
142
104
TA = –40°C to 125°C
130
dB
125
101
TA = –40°C to 125°C
145
118
dB
117
dB
Specified by characterization only.
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Electrical Characteristics (continued)
For VS = (V+) – (V–) = 2.7 V to 40 V (±1.35 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT
= VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
tS
VS = 40 V, G = +1, CL = 20 pF
Settling time
MHz
4.5
V/μs
To 0.1%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF
4
To 0.1%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF
2
To 0.01%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF
5
To 0.01%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF
THD+N
1.1
Phase margin
G = +1, RL = 10 kΩ, CL = 20 pF
Overload recovery time
VIN × gain > VS
Total harmonic distortion +
noise
VS = 40 V, VO = 1 VRMS, G = 1, f = 1 kHz
µs
3
60
°
600
ns
0.00162%
OUTPUT
VS = 40 V, RL = no
load
Voltage output swing from
rail
Positive and negative
rail headroom
2
VS = 40 V, RL = 10 kΩ
45
60
VS = 40 V, RL = 2 kΩ
200
300
1
VS = 2.7 V, RL = 10
kΩ
5
20
25
50
VS = 2.7 V, RL = 2 kΩ
ISC
Short-circuit current
CLOAD
Capacitive load drive
ZO
Open-loop output
impedance
mV
VS = 2.7 V, RL = no
load
±80
mA
See Typical Characteristics section
f = 1 MHz, IO = 0 A
Ω
575
POWER SUPPLY
OPA2990, OPA4990, IO = 0 A
Quiescent current per
amplifier
IQ
OPA990, IO = 0 A
120
TA = –40°C to 125°C
150
160
130
TA = –40°C to 125°C
µA
170
175
Turn-on time
At TA = 25°C, VS = 40 V, VS ramp rate > 0.3 V/µs
40
IQSD
Quiescent current per
amplifier
VS = 2.7 V to 40 V, all amplifiers disabled, SHDN = V– + 1
V
20
ZSHDN
Output impedance during
shutdown
VS = 2.7 V to 40 V, amplifier disabled
VIH
Logic high threshold
voltage (amplifier disabled)
VIL
Logic low threshold voltage
(amplifier enabled)
tON
Amplifier enable time
(2)
G = +1, VCM = V–, VO = 0.1 × VS / 2
11
µs
tOFF
Amplifier disable time
(2)
VCM = V–, VO = VS / 2
2.5
µs
VS = 2.7 V to 40 V, (V–) + 20 V ≥ SHDN ≥ (V–) + 0.9 V
500
VS = 2.7 V to 40 V, (V–) ≤ SHDN ≤ (V–) + 0.7 V
150
μs
SHUTDOWN
SHDN pin input bias
current (per pin)
(2)
30
10 || 12
µA
GΩ || pF
(V–) + 1.1
V
V
(V–) + 0.2 V
V
nA
Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin
and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
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Table 1. Table of Graphs
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
Figure 1
Offset Voltage Drift Distribution
Figure 2
Offset Voltage vs Temperature
Figure 3, Figure 4
Offset Voltage vs Common-Mode Voltage
Figure 5, Figure 6, Figure 7, Figure 8
Offset Voltage vs Power Supply
Figure 9
Open-Loop Gain and Phase vs Frequency
Figure 10
Closed-Loop Gain and Phase vs Frequency
Figure 11
Input Bias Current vs Common-Mode Voltage
Figure 12
Input Bias Current vs Temperature
Figure 13
Output Voltage Swing vs Output Current
Figure 14, Figure 15, Figure 16, Figure 17
CMRR and PSRR vs Frequency
Figure 18
CMRR vs Temperature
Figure 19
PSRR vs Temperature
Figure 20
0.1-Hz to 10-Hz Noise
Figure 21
Input Voltage Noise Spectral Density vs Frequency
Figure 22
THD+N Ratio vs Frequency
Figure 23
THD+N vs Output Amplitude
Figure 24
Quiescent Current vs Supply Voltage
Figure 25
Quiescent Current vs Temperature
Figure 26
Open Loop Voltage Gain vs Temperature
Figure 27
Open Loop Output Impedance vs Frequency
Figure 28
Output Swing vs Supply Voltage
Figure 29, Figure 30, Figure 31, Figure 32
Small Signal Overshoot vs Capacitive Load (100-mV Output Step)
Figure 33, Figure 34
Phase Margin vs Capacitive Load
Figure 35
No Phase Reversal
Figure 36
Positive Overload Recovery
Figure 37
14
Negative Overload Recovery
Figure 38
Small-Signal Step Response (100 mV)
Figure 39, Figure 40
Large-Signal Step Response
Figure 41, Figure 42, Figure 43
Short-Circuit Current vs Temperature
Figure 44
Maximum Output Voltage vs Frequency
Figure 45
Channel Separation vs Frequency
Figure 46
EMIRR vs Frequency
Figure 47
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6.8 Typical Characteristics
25%
25%
20%
20%
Population (%)
15%
10%
15%
10%
5%
Offset Voltage (PV)
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0
D001
0.2
1200
900
1050
750
600
450
300
0
150
-150
-300
-450
-600
-750
-900
-1050
-1200
0
5%
0
Population (%)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
Offset Voltage Drift (PV/qC)
Distribution from 15526 amplifiers, TA = 25°C
D002
Distribution from 190 amplifiers
Figure 1. Offset Voltage Production Distribution
Figure 2. Offset Voltage Drift Distribution
1000
800
800
600
Offset Voltage (µV)
Offset Voltage (µV)
600
400
200
0
-200
-400
400
200
0
-200
-400
-600
-600
-800
-1000
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
-800
-40
140
-20
0
D003
VCM = V+
600
600
400
400
200
0
-200
120
140
D004
200
0
-200
-400
-400
-600
-600
-12
100
Figure 4. Offset Voltage vs Temperature
800
Offset Voltage (µV)
Offset Voltage (µV)
Figure 3. Offset Voltage vs Temperature
-16
40
60
80
Temperature (°C)
VCM = V–
800
-800
-20
20
-8
-4
0
4
8
Common Mode Voltage (V)
12
16
20
-800
16
16.5
17
D005
17.5
18
18.5
19
Common Mode Voltage (V)
19.5
20
D005
TA = 25°C
TA = 25°C
Figure 5. Offset Voltage vs Common-Mode Voltage
Figure 6. Offset Voltage vs Common-Mode Voltage
(Transition Region)
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Typical Characteristics (continued)
1000
800
800
600
600
400
Offset Voltage (µV)
400
200
0
-200
-400
200
0
-200
-400
-600
-600
-800
-800
-1000
-1000
-20
-16
-12
-8
-4
0
4
8
Common Mode Voltage (V)
12
16
-1200
-20
20
-16
-12
-8
-4
0
4
8
Common Mode Voltage (V)
D006
TA = 125°C
12
20
D007
TA = –40°C
Figure 7. Offset Voltage vs Common-Mode Voltage
Figure 8. Offset Voltage vs Common-Mode Voltage
750
100
150
Gain
Phase
600
80
450
300
150
Gain (dB)
Offset Voltage (µV)
16
0
-150
-300
-450
125
60
100
40
75
20
50
0
25
Phase (q)
Offset Voltage (µV)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
-600
-750
0
4
8
12
16 20 24 28
Supply Voltage (V)
32
36
40
44
-20
100
0
1k
10k
100k
Frequency (Hz)
D008
1M
C002
CL = 20 pF
Figure 9. Offset Voltage vs Power Supply
Figure 10. Open-Loop Gain and Phase vs Frequency
70
3
Closed-Loop Gain (dB)
50
40
Input Bias and Offset Current (pA)
G=1
G = -1
G = 10
G = 100
G = 1000
60
30
20
10
0
-10
-20
-30
100
1k
10k
100k
Frequency (Hz)
16
2
C001
IB
IB+
IOS
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
-20
1M
Figure 11. Closed-Loop Gain vs Frequency
2.5
-16
-12
-8
-4
0
4
8
Common Mode Voltage (V)
12
16
20
D010
Figure 12. Input Bias Current vs Common-Mode Voltage
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Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
V+
IB
IB+
IOS
280
240
Output Voltage (V)
Input Bias and Offset Current (pA)
320
200
160
120
V+
1V
V+
2V
V+
3V
V+
4V
V+
5V
V+
6V
V+
7V
40
V+
8V
0
V+
9V
80
-40
-40
V+
-20
0
20
40
60
80
Temperature (°C)
100
120
10 V
0
140
10
20
30
D011
40
50
60
70
Output Current (mA)
80
90
100
D012
Figure 14. Output Voltage Swing vs Output Current
(Sourcing)
Figure 13. Input Bias Current vs Temperature
V + 10 V
5
-40°C
25°C
85°C
125°C
V +9V
V +8V
-40qC
4.5
4
V +7V
Output Voltage (V)
Output Voltage (V)
-40°C
25°C
85°C
125°C
V +6V
V +5V
V +4V
V +3V
3.5
2.5
85qC
2
1.5
V +2V
1
V +1V
0.5
V
25qC
125qC
3
0
0
10
20
30
40
50
60
70
Output Current (mA)
80
90
100
0
10
20
D012
30
40
50
60
70
Output Current (mA)
80
90
100
D013
VS = 5 V
Figure 16. Output Voltage Swing vs Output Current
(Sourcing)
5
110
4.5
100
4
90
PSRR and CMRR (dB)
Output Voltage (V)
Figure 15. Output Voltage Swing vs Output Current
(Sinking)
3.5
3
85qC
2.5
125qC
2
1.5
1
25qC
0.5
10
20
30
40
50
60
70
Output Current (mA)
80
70
60
50
40
30
20
-40qC
10
0
0
PSRR+
PSRRCMRR
80
90
100
0
100
1k
D013
10k
100k
Frequency (Hz)
1M
10M
C003
VS = 5 V
Figure 17. Output Voltage Swing vs Output Current
(Sinking)
Figure 18. CMRR and PSRR vs Frequency
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Typical Characteristics (continued)
124
145
120
144
116
Power Supply Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
VS = 40 V
VS = 4 V
112
108
104
100
96
92
88
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
143
142
141
140
139
138
137
136
135
-40
140
-20
0
20
D015
f = 0 Hz
D016
Input Voltage Noise Spectral Density (nV/rHz)
Voltage (1uV/div)
110
100
90
80
70
60
50
40
30
20
10
0
10
Figure 21. 0.1-Hz to 10-Hz Noise
100
1k
Frequency (Hz)
10k
100k
C017
Figure 22. Input Voltage Noise Spectral Density vs
Frequency
-40
-30
RL = 10 k:
RL = 2 k:
RL = 600 :
RL = 128 :
-40
-50
THD+N (dB)
THD+N (dB)
140
120
C015
-70
-80
-60
-70
-90
-80
-100
-90
-110
100
1k
Frequency (Hz)
-100
0.001
10k
BW = 80 kHz, VOUT = 1 VRMS
Figure 23. THD+N Ratio vs Frequency
18
120
Figure 20. PSRR vs Temperature (dB)
Time (1s/Div)
-60
100
f = 0 Hz
Figure 19. CMRR vs Temperature (dB)
-50
40
60
80
Temperature (°C)
RL = 10 k:
RL = 2 k:
RL = 549 :
RL = 128 :
0.01
C012
0.1
Amplitude (VRMS)
1
10 20
C023
BW = 80 kHz, f = 1 kHz
Figure 24. THD+N vs Output Amplitude
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Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
127.5
125
125
120
122.5
Quiescent current (µA)
Quiescent current (µA)
130
115
110
105
100
95
120
117.5
115
112.5
110
107.5
90
105
85
102.5
-40
0
4
8
12
16
20
24
28
Supply Voltage (V)
32
36
40
-20
0
20
D021
40
60
80
Temperature (°C)
100
120
140
D022
VCM = V–
Figure 26. Quiescent Current vs Temperature
780
144
720
Open Loop Output Impedance (:)
Open Loop Voltage Gain (dB)
Figure 25. Quiescent Current vs Supply Voltage
146
142
140
138
136
VS = 40 V
VS = 4 V
134
132
130
128
126
124
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
160
140
120
100
80
60
40
20
0
12
16
20
24
28
Supply Voltage (V)
480
420
360
300
240
180
1k
10k
100k
Frequency (Hz)
32
36
40
1M
10M
C013
Figure 28. Open-Loop Output Impedance vs Frequency
Delta Between Supply and Output Voltage (mV)
Delta Between Supply and Output Voltage (mV)
180
8
540
D023
200
4
600
120
100
140
Figure 27. Open-Loop Voltage Gain vs Temperature (dB)
0
660
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
-220
0
4
8
D026
RL = 2 kΩ
12
16
20
24
28
Supply Voltage (V)
32
36
40
D026
RL = 2 kΩ
Figure 29. Output Swing vs Supply Voltage, Positive Swing
Figure 30. Output Swing vs Supply Voltage, Negative Swing
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Typical Characteristics (continued)
40
36
32
28
24
20
16
12
8
4
0
0
4
8
12
16
20
24
28
Supply Voltage (V)
32
36
40
Delta Between Supply and Output Voltage (mV)
Delta Between Supply and Output Voltage (mV)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
0
4
8
12
D027
RL = 10 kΩ
32
36
40
D027
RL = 10 kΩ
Figure 31. Output Swing vs Supply Voltage, Positive Swing
Figure 32. Output Swing vs Supply Voltage, Negative Swing
33
55
30
50
27
45
24
40
Overshoot (%)
Overshoot (%)
16
20
24
28
Supply Voltage (V)
21
18
15
12
35
30
25
20
RISO = 0 :, Positive Overshoot
RISO = 0 :, Negative Overshoot
RISO = 50 :, Positive Overshoot
RISO = 50 :, Negative Overshoot
9
6
RISO = 0 :, Positive Overshoot
RISO = 0 :, Negative Overshoot
RISO = 50 :, Positive Overshoot
RISO = 50 :, Negative Overshoot
15
10
3
5
0
40
80
120
160 200 240
Cap Load (pF)
280
320
360
0
40
80
C007
G = –1, 10-mV output step
120
160 200 240
Cap Load (pF)
280
320
360
C008
G = 1, 10-mV output step
Figure 33. Small-Signal Overshoot vs Capacitive Load
Figure 34. Small-Signal Overshoot vs Capacitive Load
64
Input
Output
60
56
Amplitude (2V/div)
Phase Margin (q)
52
48
44
40
36
32
28
24
20
0
100
200
300
400 500 600
Cap Load (pF)
700
800
C009
Figure 35. Phase Margin vs Capacitive Load
20
Time (20µs/Div)
900 1000
C016
VIN = ±20 V; VS = VOUT = ±17 V
Figure 36. No Phase Reversal
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Typical Characteristics (continued)
Voltage (5V/div)
Voltage (5V/div)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
Input
Output
Input
Output
Time (500ns/div)
Time (500ns/div)
C018
C018
G = –10
G = –10
Figure 37. Positive Overload Recovery
Figure 38. Negative Overload Recovery
Amplitude (5mV/div)
Amplitude (5mV/div)
Input
Output
Input
Output
Time (1µs/div)
Time (2Ps/div)
C010
C011
CL = 20 pF, G = 1, 20-mV step response
CL = 20 pF, G = –1, 20-mV step response
Figure 39. Small-Signal Step Response
Figure 40. Small-Signal Step Response
Amplitude (2V/div)
Amplitude (2V/div)
Input
Output
Input
Output
Time (1µs/div)
Time (1µs/div)
C005
C005
CL = 20 pF, G = 1
Figure 41. Large-Signal Step Response (Falling)
CL = 20 pF, G = 1
Figure 42. Large-Signal Step Response (Rising)
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Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
Large Signal Step Response (2V/div)
100
Short-Circuit Current (mA)
80
Input
Output
60
40
20
Sourcing
Sinking
0
-20
-40
-60
-80
-100
-40
Time (2µs/div)
-20
0
C021
20
40
60
80
Temperature (°C)
100
120
140
D038
CL = 20 pF, G = –1
Figure 43. Large-Signal Step Response
Figure 44. Short-Circuit Current vs Temperature
20
-60
-70
Channel Seperation (dB)
Maximum Output Swing (V)
VS = 15 V
VS = 2.7 V
15
10
5
-80
-90
-100
-110
-120
0
1k
10k
100k
Frequency (Hz)
1M
10M
-130
100
1k
C020
Figure 45. Maximum Output Voltage vs Frequency
10k
100k
Frequency (Hz)
1M
10M
C014
Figure 46. Channel Separation vs Frequency
100
90
EMIRR (dB)
80
70
60
50
40
30
1M
10M
100M
Frequency (Hz)
1G
C004
Figure 47. EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency
22
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7 Detailed Description
7.1 Overview
The OPAx990 family (OPA990, OPA2990, and OPA4990) is a family of high voltage (40-V) general purpose
operational amplifiers.
These devices offer excellent DC precision and AC performance, including rail-to-rail input/output, low offset
(±300 µV, typ), and low offset drift (±0.6 µV/°C, typ).
Unique features such as differential and common-mode input voltage range to the supply rail, high short-circuit
current (±80 mA), high slew rate (4.5 V/µs), and shutdown make the OPAx990 an extremely flexible, robust, and
high-performance operational amplifier for high-voltage industrial applications.
7.2 Functional Block Diagram
+
NCH Input
Stage
±
IN+
40-V
Differential
MUX-Friendly
Front End
+
Slew
Boost
Output
Stage
Shutdown
Circuitry
OUT
±
IN-
+
PCH Input
Stage
±
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7.3 Feature Description
7.3.1 Input Protection Circuitry
The OPAx990 uses a unique input architecture to eliminate the requirement for input protection diodes but still
provides robust input protection under transient conditions. Figure 48 shows conventional input diode protection
schemes that are activated by fast transient step responses and introduce signal distortion and settling time
delays because of alternate current paths, as shown in Figure 49. For low-gain circuits, these fast-ramping input
signals forward-bias back-to-back diodes, causing an increase in input current and resulting in extended settling
time.
V+
V+
VIN+
VIN+
40 V
VOUT
OPAx990
VOUT
~0.7 V
VIN
VIN
V
OPAx990 Provides Full 40-V
Differential Input Range
V
Conventional Input Protection
Limits Differential Input Range
Figure 48. OPAx990 Input Protection Does Not Limit Differential Input Capability
Vn = 10 V
RFILT
10 V
1
Ron_mux
Sn
1
D
10 V
CFILT
2
~±9.3 V
CS
CD
Vn+1 = ±10 V RFILT
±10 V
Ron_mux
Sn+1
VIN±
2
~0.7 V
CS
CFILT
VOUT
Idiode_transient
±10 V
Input Low-Pass Filter
VIN+
Buffer Amplifier
Simplified Mux Model
Figure 49. Back-to-Back Diodes Create Settling Issues
The OPAx990 family of operational amplifiers provides a true high-impedance differential input capability for highvoltage applications using a patented input protection architecture that does not introduce additional signal
distortion or delayed settling time, making the device an optimal op amp for multichannel, high-switched, input
applications. The OPA990 tolerates a maximum differential swing (voltage between inverting and non-inverting
pins of the op amp) of up to 40 V, making the device suitable for use as a comparator or in applications with fastramping input signals such as data-acquisition systems; see the TI TechNote MUX-Friendly Precision
Operational Amplifiers for more information.
24
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Feature Description (continued)
7.3.2 EMI Rejection
The OPAx990 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the OPAx990 benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz.
Figure 50 shows the results of this testing on the OPAx990. Table 2 shows the EMIRR IN+ values for the
OPAx990 at particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of
Operational Amplifiers application report contains detailed information on the topic of EMIRR performance as it
relates to op amps and is available for download from www.ti.com.
100
90
EMIRR (dB)
80
70
60
50
40
30
1M
10M
100M
Frequency (Hz)
1G
C004
Figure 50. EMIRR Testing
Table 2. OPA990 EMIRR IN+ For Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
59.5 dB
900 MHz
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
68.9 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
77.8 dB
2.4 GHz
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
78.0 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
88.8 dB
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
87.6 dB
5 GHz
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7.3.3 Thermal Protection
VOUT
The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This
phenomenon is called self heating. The absolute maximum junction temperature of the OPAx990 is 150°C.
Exceeding this temperature causes damage to the device. The OPAx990 has a thermal protection feature that
reduces damage from self heating. The protection works by monitoring the temperature of the device and turning
off the op amp output drive for temperatures above 170°C. Figure 51 shows an application example for the
OPA990 that has significant self heating because of its power dissipation (0.81 W). Thermal calculations indicate
that for an ambient temperature of 65°C, the device junction temperature must reach 177°C. The actual device,
however, turns off the output drive to recover towards a safe junction temperature. Figure 51 shows how the
circuit behaves during thermal protection. During normal operation, the device acts as a buffer so the output is 3
V. When self heating causes the device junction temperature to increase above the internal limit, the thermal
protection forces the output to a high-impedance state and the output is pulled to ground through resistor RL. If
the condition that caused excessive power dissipation is not removed, the amplifier will oscillate between a
shutdown and enabled state until the output fault is corrected.
3V
TA = 65°C
PD = 0.81W
0V
JA = 138.7°C/W
TJ = 138.7°C/W × 0.81W + 65°C
TJ = 177.3°C (expected)
30 V
OPA990
+
±
+
RL
3V
100 Ÿ ±
VIN
3V
170ºC
Temperature
IOUT = 30 mA
Figure 51. Thermal Protection
7.3.4 Capacitive Load and Stability
55
33
50
30
45
27
40
24
Overshoot (%)
Overshoot (%)
The OPAx990 features a resistive output stage capable of driving moderate capacitive loads, and by leveraging
an isolation resistor, the device can easily be configured to drive large capacitive loads. Increasing the gain
enhances the ability of the amplifier to drive greater capacitive loads; see Figure 52 and Figure 53. The particular
op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when
establishing whether an amplifier will be stable in operation.
35
30
25
20
18
15
12
RISO = 0 :, Positive Overshoot
RISO = 0 :, Negative Overshoot
RISO = 50 :, Positive Overshoot
RISO = 50 :, Negative Overshoot
15
10
RISO = 0 :, Positive Overshoot
RISO = 0 :, Negative Overshoot
RISO = 50 :, Positive Overshoot
RISO = 50 :, Negative Overshoot
9
6
5
3
0
40
80
120
160 200 240
Cap Load (pF)
280
320
360
0
40
80
C008
Figure 52. Small-Signal Overshoot vs Capacitive Load
(10-mV Output Step, G = 1)
26
21
120
160 200 240
Cap Load (pF)
280
320
360
C007
Figure 53. Small-Signal Overshoot vs Capacitive Load
(10-mV Output Step, G = –1)
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For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small
resistor, RISO, in series with the output, as shown in Figure 54. This resistor significantly reduces ringing and
maintains DC performance for purely capacitive loads. However, if a resistive load is in parallel with the
capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly reducing
the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at low
output levels. A high capacitive load drive makes the OPAx990 well suited for applications such as reference
buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 54 uses an isolation resistor,
RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase
margin.
+Vs
Vout
Riso
+
Vin
+
±
Cload
-Vs
Figure 54. Extending Capacitive Load Drive With the OPA990
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7.3.5 Common-Mode Voltage Range
The OPAx990 is a 40-V, true rail-to-rail input operational amplifier with an input common-mode range that
extends 200 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel
and P-channel differential input pairs, as shown in Figure 55. The N-channel pair is active for input voltages
close to the positive rail, typically (V+) – 1 V to 100 mV above the positive supply. The P-channel pair is active
for inputs from 100 mV below the negative supply to approximately (V+) – 2 V. There is a small transition region,
typically (V+) – 2 V to (V+) – 1 V in which both input pairs are on. This transition region can vary modestly with
process variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD performance
may be degraded compared to operation outside this region.
Figure 5 shows this transition region for a typical device in terms of input voltage offset in more detail.
For more information on common-mode voltage range and PMOS/NMOS pair interaction, see Op Amps With
Complementary-Pair Input Stages application note.
V+
INPMOS
PMOS
NMOS
IN+
NMOS
V-
Figure 55. Rail-to-Rail Input Stage
7.3.6 Phase Reversal Protection
The OPAx990 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond its linear common-mode range. This condition is most often encountered in non-inverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The OPAx990 is a rail-to-rail input op amp; therefore, the common-mode range can
extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into
the appropriate rail. This performance is shown in Figure 56. For more information on phase reversal, see Op
Amps With Complementary-Pair Input Stages application note.
Amplitude (2V/div)
Input
Output
Time (20µs/Div)
C016
Figure 56. No Phase Reversal
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7.3.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the
output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. Figure 57 shows an illustration of the ESD circuits contained in the OPAx990 (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or
the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain
inactive during normal circuit operation.
TVS
+
±
RF
+VS
VDD
R1
RS
IN±
100 Ÿ
IN+
100 Ÿ
OPAx990
±
+
Power-Supply
ESD Cell
ID
VIN
RL
+
±
VSS
+
±
±VS
TVS
Figure 57. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event is very short in duration and very high voltage (for example; 1 kV, 100 ns), whereas an EOS event
is long duration and lower voltage (for example; 50 V, 100 ms). The ESD diodes are designed for out-of-circuit
ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).
During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit (labeled
ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by
turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting
resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.
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7.3.8 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a
linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the
rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
The overload recovery time for the OPAx990 is approximately 600 ns.
7.3.9 Typical Specifications and Distributions
Designers often have questions about a typical specification of an amplifier in order to design a more robust
circuit. Due to natural variation in process technology and manufacturing procedures, every specification of an
amplifier will exhibit some amount of deviation from the ideal value, like an amplifier's input offset voltage. These
deviations often follow Gaussian ("bell curve"), or normal distributions, and circuit designers can leverage this
information to guardband their system, even when there is not a minimum or maximum specification in the
Electrical Characteristics table.
0.00002% 0.00312% 0.13185%
1
-61
1
-51
2.145% 13.59% 34.13% 34.13% 13.59% 2.145%
1
1
-41
-31
1
-21
1
-1
1
1
+1
1
0.13185% 0.00312% 0.00002%
1
1
1
+21 +31 +41 +51 +61
Figure 58. Ideal Gaussian Distribution
Figure 58 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ, or sigma,
is the standard deviation of a system. For a specification that exhibits this kind of distribution, approximately twothirds (68.26%) of all units can be expected to have a value within one standard deviation, or one sigma, of the
mean (from µ–σ to µ+σ).
Depending on the specification, values listed in the typical column of the Electrical Characteristics table are
represented in different ways. As a general rule of thumb, if a specification naturally has a nonzero mean (for
example, like gain bandwidth), then the typical value is equal to the mean (µ). However, if a specification
naturally has a mean near zero (like input offset voltage), then the typical value is equal to the mean plus one
standard deviation (µ + σ) in order to most accurately represent the typical value.
You can use this chart to calculate approximate probability of a specification in a unit; for example, for OPAx990,
the typical input voltage offset is 300 µV, so 68.2% of all OPAx990 devices are expected to have an offset from
–300 µV to +300 µV. At 4 σ (±1200 µV), 99.9937% of the distribution has an offset voltage less than ±1200 µV,
which means 0.0063% of the population is outside of these limits, which corresponds to about 1 in 15,873 units.
30
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Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits
will be removed from production material. For example, the OPAx990 family has a maximum offset voltage of 1.5
mV at 25°C, and even though this corresponds to 5 σ (≈1 in 1.7 million units), which is extremely unlikely, TI
assures that any unit with larger offset than 1.5 mV will be removed from production material.
For specifications with no value in the minimum or maximum column, consider selecting a sigma value of
sufficient guardband for your application, and design worst-case conditions using this value. For example, the 6σ
value corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and could be an option
as a wide guardband to design a system around. In this case, the OPAx990 family does not have a maximum or
minimum for offset voltage drift, but based on Figure 2 and the typical value of 0.6 µV/°C in the Electrical
Characteristics table, it can be calculated that the 6-σ value for offset voltage drift is about 3.6 µV/°C. When
designing for worst-case system conditions, this value can be used to estimate the worst possible offset across
temperature without having an actual minimum or maximum value.
However, process variation and adjustments over time can shift typical means and standard deviations, and
unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a
device. This information should be used only to estimate the performance of a device.
7.3.10 Packages With an Exposed Thermal Pad
The OPAx990 family is available in packages such as the WSON-8 (DSG) and WQFN-16 (RTE) which feature
an exposed thermal pad. Inside the package, the die is attached to this thermal pad using an electrically
conductive compound. For this reason, when using a package with an exposed thermal pad, the thermal pad
must either be connected to V– or left floating. Attaching the thermal pad to a potential other than V– is not
allowed, and performance of the device is not assured when doing so.
7.3.11 Shutdown
The OPAx990S devices feature one or more shutdown pins (SHDN) that disable the op amp, placing it into a
low-power standby mode. In this mode, the op amp typically consumes about 20 µA. The SHDN pins are active
high, meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic high.
The SHDN pins are referenced to the negative supply rail of the op amp. The threshold of the shutdown feature
lies around 800 mV (typical) and does not change with respect to the supply voltage. Hysteresis has been
included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown
behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage
between V– and V– + 0.4 V. A valid logic high is defined as a voltage between V– + 1.2 V and V– + 20 V. The
shutdown pin circuitry includes a pull-down resistor, which will inherently pull the voltage of the pin to the
negative supply rail if not driven. Thus, to enable the amplifier, the SHDN pins should either be left floating or
driven to a valid logic low. To disable the amplifier, the SHDN pins must be driven to a valid logic high. The
maximum voltage allowed at the SHDN pins is V– + 20 V. Exceeding this voltage level will damage the device.
The SHDN pins are high-impedance CMOS inputs. Channels of single and dual op amp packages are
independently controlled, and channels of quad op amp packages are controlled in pairs. For battery-operated
applications, this feature may be used to greatly reduce the average current and extend battery life. The typical
enable time out of shutdown is 30 µs; disable time is 3 µs. When disabled, the output assumes a highimpedance state. This architecture allows the OPAx990S family to operate as a gated amplifier, multiplexer, or
programmable-gain amplifier. Shutdown time (tOFF) depends on loading conditions and increases as load
resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load to
midsupply (VS / 2) is required. If using the OPAx990S without a load, the resulting turnoff time significantly
increases.
7.4 Device Functional Modes
The OPAx990 has a single functional mode and is operational when the power-supply voltage is greater than or
equal to 2.7 V (±1.35 V). The maximum power supply voltage for the OPAx990 is 40 V (±20 V).
The OPAx990S devices feature a shutdown pin, which can be used to place the op amp into a low-power mode.
See Shutdown section for more information.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPAx990 family offers excellent DC precision and AC performance. These devices operate up to 40-V
supply rails and offer true rail-to-rail input/output, low offset voltage and offset voltage drift, as well as 1.1-MHz
bandwidth and high output drive. These features make the OPAx990 a robust, high-performance operational
amplifier for high-voltage industrial applications.
8.2 Typical Applications
8.2.1 High Voltage Buffered Multiplexer
The OPAx990S shutdown devices can be configured to create a high voltage, buffered multiplexer. Outputs can
be connected together on a common bus and the shutdown pins can be used to select the desired channel to
pass through. Since the amplifier circuitry has been designed such that disable transitions occur significantly
faster than enable transitions, the amplifier naturally exhibits a "break before make" switch topology. Amplifier
outputs enter a high impedance state when placed in shutdown, so there is no risk of bus contention when
connecting multiple channel outputs together. Additionally, because outputs are isolated from inputs, there is no
concern about the impedance at the input of each channel interacting undesirably with the impedance at the
output, like an amplifier gain stage or ADC driver circuit. Also, because this topology uses amplifiers instead of
MOSFET switches, other common issues with multiplexers such as charge injection or signal error due to RON
effects are eliminated.
Figure 59 shows an example topology for a basic 2:1 multiplexer. When SEL is low, channel 1 is selected and
active; when SEL is high, channel 2 is selected and active. For more information on how to use the OPAx990S
shutdown function, see the shutdown section in the Electrical Characteristics table.
±
Channel 1
Channel 1
Input
+
SEL
Channel 2
Input
Output
+
Channel 2
±
Figure 59. High Voltage Buffered Multiplexer
8.2.2 Slew Rate Limit for Input Protection
In control systems for valves or motors, abrupt changes in voltages or currents can cause mechanical damages.
By controlling the slew rate of the command voltages into the drive circuits, the load voltages ramps up and down
at a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate), one
additional op amp provides slew-rate control for a given analog gain stage. The unique input protection and high
output current and slew rate of the OPAx990 make the device an optimal amplifier to achieve slew rate control
for both dual- and single-supply systems. Figure 60 shows the OPA990 in a slew-rate limit design.
32
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OPA990, OPA2990, OPA4990
www.ti.com
SBOS933E – FEBRUARY 2019 – REVISED DECEMBER 2019
Typical Applications (continued)
Op Amp Gain Stage
Slew Rate Limiter
C1
470 nF
R1
1.69 kŸ
VEE
VEE
+
R2
1.6 MŸ
VIN
OPAx990
V+
VOUT
OPAx990
V+
VCC
RL
10 kŸ
VCC
Figure 60. Slew Rate Limiter Uses One Op Amp
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33
OPA990, OPA2990, OPA4990
SBOS933E – FEBRUARY 2019 – REVISED DECEMBER 2019
www.ti.com
9 Power Supply Recommendations
The OPAx990 is specified for operation from 2.7 V to 40 V (±1.35 V to ±20 V); many specifications apply from
–40°C to 125°C or with specific supply voltages and test conditions. Parameters that can exhibit significant
variance with regard to operating voltage or temperature are presented in the Typical Characteristics section.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 62, keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
10.2 Layout Example
+
VIN
VOUT
RG
RF
Figure 61. Schematic Representation
34
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OPA990, OPA2990, OPA4990
www.ti.com
SBOS933E – FEBRUARY 2019 – REVISED DECEMBER 2019
Layout Example (continued)
Run the input traces
as far away from
the supply lines
as possible
Place components close
to device and to each
other to reduce parasitic
errors
VS+
RF
NC
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
±IN
V+
VIN
+IN
OUTPUT
V±
NC
GND
VS±
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
GND
V+
INPUT
Figure 62. Operational Amplifier Board Layout for Noninverting Configuration
GND
OUT
V-
GND
Figure 63. Example Layout for SC70 (DCK) Package
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35
OPA990, OPA2990, OPA4990
SBOS933E – FEBRUARY 2019 – REVISED DECEMBER 2019
www.ti.com
OUTPUT A
Layout Example (continued)
GND
GND
GND
V+
INPUT A
INPUT B
OUTPUT B
VGND
GND
GND
GND
V+
GND
OUT A
Figure 64. Example Layout for VSSOP-8 (DGK) Package
GND
OUT B
- +
+ -
+IN A
V-
+IN B
GND
GND
GND
Figure 65. Example Layout for WSON-8 (DSG) Package
36
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Product Folder Links: OPA990 OPA2990 OPA4990
OPA990, OPA2990, OPA4990
www.ti.com
SBOS933E – FEBRUARY 2019 – REVISED DECEMBER 2019
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.2 Documentation Support
11.2.1 Related Documentation
Texas Instruments, Op Amps With Complementary-Pair Input Stages application note
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 3. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA990
Click here
Click here
Click here
Click here
Click here
OPA2990
Click here
Click here
Click here
Click here
Click here
OPA4990
Click here
Click here
Click here
Click here
Click here
Submit Documentation Feedback
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Product Folder Links: OPA990 OPA2990 OPA4990
37
OPA990, OPA2990, OPA4990
SBOS933E – FEBRUARY 2019 – REVISED DECEMBER 2019
www.ti.com
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.6 Trademarks
E2E is a trademark of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
38
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Product Folder Links: OPA990 OPA2990 OPA4990
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA2990IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OP2990
OPA2990IDSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O29G
OPA2990IPWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2990P
OPA2990SIDGSR
PREVIEW
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
OP29
OPA4990IDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4990D
OPA4990IPWR
PREVIEW
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
OPA49PW
OPA990IDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O90V
OPA990IDCKR
PREVIEW
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
1FL
OPA990SIDBVR
PREVIEW
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
O90S
POPA2990SIDGSR
ACTIVE
VSSOP
DGS
10
2500
TBD
Call TI
Call TI
-40 to 125
POPA4990IDR
ACTIVE
SOIC
D
14
2500
TBD
Call TI
Call TI
-40 to 125
POPA4990IPWR
ACTIVE
TSSOP
PW
14
2000
TBD
Call TI
Call TI
-40 to 125
POPA990IDCKR
ACTIVE
SC70
DCK
5
3000
TBD
Call TI
Call TI
-40 to 125
POPA990SIDBVR
ACTIVE
SOT-23
DBV
6
3000
TBD
Call TI
Call TI
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2020
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
OPA2990IDR
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
SOIC
D
8
2500
330.0
OPA2990IDSGR
WSON
DSG
8
3000
OPA2990IPWR
TSSOP
PW
8
2000
OPA4990IDR
SOIC
D
14
OPA990IDBVR
SOT-23
DBV
5
B0
(mm)
K0
(mm)
P1
(mm)
12.4
6.4
5.2
2.1
8.0
180.0
8.4
2.3
2.3
1.15
330.0
12.4
7.0
3.6
1.6
2500
330.0
16.4
6.5
9.0
3000
180.0
8.4
3.2
3.2
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
12.0
Q1
4.0
8.0
Q2
8.0
12.0
Q1
2.1
8.0
16.0
Q1
1.4
4.0
8.0
Q3
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Dec-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2990IDR
SOIC
D
8
2500
367.0
367.0
35.0
OPA2990IDSGR
WSON
DSG
8
3000
210.0
185.0
35.0
OPA2990IPWR
TSSOP
PW
8
2000
367.0
367.0
35.0
OPA4990IDR
SOIC
D
14
2500
367.0
367.0
38.0
OPA990IDBVR
SOT-23
DBV
5
3000
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
6
2X 0.95
1.9
1.45 MAX
3.05
2.75
5
2
4
0.50
6X
0.25
0.2
C A B
3
(1.1)
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214840/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X (0.95)
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214840/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X(0.95)
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
SCALE 3.200
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
10
1
3.1
2.9
NOTE 3
8X 0.5
2X
2
5
6
B
10X
3.1
2.9
NOTE 4
SEE DETAIL A
0.27
0.17
0.1
C A
1.1 MAX
B
0.23
TYP
0.13
0.25
GAGE PLANE
0 -8
0.15
0.05
0.7
0.4
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (0.3)
10X (1.45)
(R0.05)
TYP
SYMM
1
10
SYMM
8X (0.5)
6
5
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
10X (0.3)
SYMM
1
(R0.05) TYP
10
SYMM
8X (0.5)
6
5
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DSG 8
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2 x 2, 0.5 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.32
0.18
0.4
0.2
OPTIONAL TERMINAL
TYPICAL
C
0.8 MAX
SEATING PLANE
0.05
0.00
0.08 C
EXPOSED
THERMAL PAD
(0.2) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
SEE OPTIONAL
TERMINAL
9
8
1
PIN 1 ID
1.6 0.1
8X
0.4
8X
0.2
0.32
0.18
0.1
0.05
C A B
C
4218900/C 04/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
8X (0.5)
( 0.2) VIA
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(R0.05) TYP
(1.9)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218900/C 04/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
SYMM
METAL
1
8
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/C 04/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
SCALE 2.800
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
1
3.1
2.9
NOTE 3
2X
1.95
4
5
B
4.5
4.3
NOTE 4
SEE DETAIL A
8X
0.30
0.19
0.1
C A
1.2 MAX
B
(0.15) TYP
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
1
8
(R0.05)
TYP
SYMM
6X (0.65)
5
4
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
(R0.05) TYP
1
8
SYMM
6X (0.65)
5
4
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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