Texas Instruments | OPA462 High-Voltage (180-V), High-Current (30-mA) Operational Amplifier (Rev. A) | Datasheet | Texas Instruments OPA462 High-Voltage (180-V), High-Current (30-mA) Operational Amplifier (Rev. A) Datasheet

Texas Instruments OPA462 High-Voltage (180-V), High-Current (30-mA) Operational Amplifier (Rev. A) Datasheet
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OPA462
SBOS803A – DECEMBER 2018 – REVISED DECEMBER 2019
OPA462 High-Voltage (180-V), High-Current (30-mA) Operational Amplifier
1 Features
3 Description
•
The OPA462 is a high voltage (180 V) and high
current drive (45 mA) operational amplifier. The
device is unity-gain stable and has a gain-bandwidth
product of 6.5 MHz.
1
•
•
•
•
•
•
•
•
•
Wide power-supply range:
±6 V (12 V) to ±90 V (180 V)
High-output load drive: IO ±45 mA
Current limit protection
Thermal protection
Status flag
Independent output disable
Gain bandwidth: 6.5 MHz
Slew rate: 32 V/µs
Wide temperature range: –40°C to +85°C
8-pin HSOIC (SO PowerPAD™) package
The OPA462 is internally protected against overtemperature conditions and current overloads. The
device is fully specified to perform over a wide powersupply range of ±6 V to ±90 V, or on a single supply
of 12 V to 180 V. The status flag is an open-drain
output that allows the device to be easily referenced
to standard low-voltage logic circuitry. This highvoltage operational amplifier provides excellent
accuracy and wide output swing, and is free from
phase inversion problems that are often found in
similar amplifiers.
2 Applications
•
•
•
•
•
•
The output can be disabled using the enable-disable
(E/D) pin. The E/D pin has a common return pin to
allow for easy interface to low-voltage logic circuitry.
This disable is accomplished without disturbing the
input signal path, not only saving power but also
protecting the load.
Semiconductor test
Optical module
Lab and field instrumentation
Semiconductor manufacturing
Multiparameter patient monitor
Display panel for PC and notebooks
Featured in a small exposed-metal pad package, the
OPA462 dissipates heat over the industrial
temperature range of –40°C to +85°C.
Device Information(1)
PART NUMBER
OPA462
PACKAGE
HSOIC (8)
BODY SIZE (NOM)
4.89 mm × 3.90 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
OPA462 Block Diagram
Maximum Output Voltage vs Frequency
200
Vs=r90 V
Vs=r50 V
Vs=r6 V
175
±IN
Differential
Amplifier
Voltage
Amplifier
High Current
Output Stage
OUT
Output Voltage (VPP)
V+
150
125
100
75
50
25
+IN
0
Biasing
Current Limiting
Enable/Disable
Status
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
V
E/D
E/D Status
COM Flag
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA462
SBOS803A – DECEMBER 2018 – REVISED DECEMBER 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
7
9
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics: Table of Graphs ..................
Typical Characteristics ..............................................
Detailed Description ............................................ 19
7.1 Overview ................................................................. 19
7.2 Functional Block Diagram ....................................... 19
7.3 Feature Description................................................. 19
7.4 Device Functional Modes........................................ 20
8
Application and Implementation ........................ 21
8.1 Application Information............................................ 21
8.2 Typical Applications ................................................ 21
9 Power Supply Recommendations...................... 27
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 30
11 Device and Documentation Support ................. 31
11.1
11.2
11.3
11.4
11.5
11.6
Device Support ....................................................
Documentation Support .......................................
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
32
32
32
32
12 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
Changes from Original (December 2018) to Revision A
•
2
Page
Changed OPA462 from advanced information (preview) to production data (active) ............................................................ 1
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SBOS803A – DECEMBER 2018 – REVISED DECEMBER 2019
5 Pin Configuration and Functions
DDA PACKAGE
8-Pin SO PowerPAD™
Top View
E/D Com
1
±IN
2
8
E/D
7
V+
PowerPAD
+IN
3
6
OUT
V±
4
5
Status Flag
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
E/D
8
I
Enable or disable
E/D Com
1
I
Enable and disable common
–IN
2
I
Inverting input
+IN
3
I
Noninverting input
OUT
6
O
Output
Status Flag
5
O
Status Flag is an open-drain active-low output referenced to E/D Com. This pin
goes active for either an overcurrent or overtemperature condition.
V–
4
—
Negative (lowest) power supply
V+
7
—
Positive (highest) power supply
PowerPAD
—
The PowerPAD is internally connected to V–. The PowerPAD must be soldered
to a printed-circuit board (PCB) connected to V–, even with applications that
have low power dissipation.
PowerPAD
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SBOS803A – DECEMBER 2018 – REVISED DECEMBER 2019
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VS
Supply voltage
+IN, –IN
Signal input pins (2)
(V–) – 0.3
MAX
UNIT
190
V
(V+) + 0.3
V
E/D to E/D Com
7
All input pins (2)
Output short circuit (3)
TA
Operating
TJ
Junction
TSTG
Storage
(1)
(2)
(3)
V
±10
mA
Continuous
Continuous
–55
125
°C
150
°C
125
°C
–55
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input terminals, Status Flag, E/D, and E/D Com, and Output are diode-clamped to the power-supply rails. Input signals that can swing
more than 0.3 V beyond the supply rails must be current-limited to 10 mA or less.
Short-circuit to ground.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
Supply voltage
TA
Specified temperature
MAX
UNIT
±6
NOM
±90
V
–40
85
°C
6.4 Thermal Information
OPA462
THERMAL METRIC (1)
DDA (HSOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
36.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
45.4
°C/W
RθJB
Junction-to-board thermal resistance
11.3
°C/W
ψJT
Junction-to-top characterization parameter
1.8
°C/W
ψJB
Junction-to-board characterization parameter
11.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.1
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS803A – DECEMBER 2018 – REVISED DECEMBER 2019
6.5 Electrical Characteristics
at TA = 25°C, VS = ±90V RL = 10 kΩ to mid-supply, VCM = VOUT = mid-supply (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±0.2
±3.4
mV
±4
±20
µV/°C
OFFSET VOLTAGE
VOS
Input offset voltage
IO = 0 mA
dVOS/dT
Input offset voltage drift
At TA = –40°C to +85°C
PSRR
Power supply rejection ratio
VS = ±6 V to ±90 V
0.03
0.3
µV/V
VS = ±6 V to ±90 V
At TA = –40°C to +85°C
0.3
1.5
µV/V
VS = ±50V
±30
±100
pA
±2.2
nA
±100
pA
±1.1
nA
INPUT BIAS CURRENT
IB
IOS
Input bias current
Input offset current
At TA = –40°C to +85°C
±30
At TA = –40°C to +85°C
NOISE
en
Input voltage noise density
Input voltage noise
in
Current noise density
f = 1 kHz
33
nV/√Hz
f = 10 kHz
23
nV/√Hz
f = 0.1 Hz to 10 Hz
12.5
µVPP
f = 1 kHz
40
fA/√Hz
f = 10 kHz
450
fA/√Hz
INPUT VOLTAGE
VCM
Common-mode voltage
Linear operation
CMRR
Common-mode
Common-mode rejection
rejection
(V–) + 1
(V+) – 3
V
–85 V ≤ VCM ≤ 85 V
120
128
dB
CMRR
Common-mode rejection
–85 V ≤ VCM ≤ 85 V
At TA = –40°C to +85°C
116
120
dB
INPUT IMPEDANCE
Differential
Common-mode
1013 || 6
Ω || pF
1013 || 3.5
Ω || pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
(V–) + 3 V < VO < (V+) – 3 V
126
135
dB
(V–) + 3 V < VO < (V+) – 3 V
At TA = –40°C to +85°C
120
134
dB
(V–) + 5 V < VO < (V+) – 5 V, RL =
5kΩ
126
135
dB
(V–) + 5 V < VO < (V+) – 5 V, RL =
5kΩ
At TA = –40°C to +85°C
120
130
dB
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product
Small-signal
6.5
MHz
Slew rate
G = ±1 V/V, VO = 80-V step,
RL = 3.27 kΩ
32
V/µs
25
kHz
5.2
µs
G = +10 V/V,
f = 1 kHz, VO = 150 VPP
0.0009
%
G = +10 V/V,
f = 1 kHz, VO = 150 VPP, RL = 5 kΩ
0.0012
%
G = +20 V/V,
f = 1 kHz, VO = 150 VPP
0.0015
%
G = +20 V/V,
f = 1 kHz, VO = 150 VPP, RL = 5 kΩ
0.0025
%
Full-power bandwidth
tS
THD+N
Settling time
Total harmonic distortion + noise
To ±0.01%, G = ±5 V/V or ±10
V/V,
VO = 120-V step
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Electrical Characteristics (continued)
at TA = 25°C, VS = ±90V RL = 10 kΩ to mid-supply, VCM = VOUT = mid-supply (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
Overload recovery
VO
Output voltage swing
G = –10 V/V
150
ns
RL = 10 kΩ,
(V–) + 3
(V+) – 1.5
V
RL = 5 kΩ,
(V–) + 5
(V+) – 3
V
VS = ±45 V, At TA = –40°C to
+85°C
ISC
Short-circuit current
CLOAD
Capacitive load drive
ZO
Open-loop output impedance
f = 1 MHz
Output impedance
Output capacitance
±45
mA
200
pF
90
Ω
Output disabled
160
kΩ
Output disabled
36
pF
Enable → Disable, 10 kΩ pull-up
to 5 V
3.5
µs
Disable → Enable, 10 kΩ pull-up
to 5V
11
µs
Overcurrent delay, 10 kΩ pull-up
to 5V
1
µs
Overcurrent recovery delay, 10 kΩ
pull-up to 5 V
9
µs
Alarm (Status Flag high)
150
°C
Return to normal operation
(Status Flag low)
130
°C
See typical
curves
V
STATUS FLAG PIN (Referenced to E/D Com)
Status Flag delay
Device thermal
shutdown
Status Flag output voltage
Normal operation
E/D (ENABLE/DISABLE) PIN
High (output enabled)
Pin open or forced high
Low (output disabled)
Pin forced low
VSD
E/D Com +
0.8
E/D Com +
5.5
V
E/D Com
E/D Com +
0.35
V
Output disable time
4
µs
Output enable time
2.5
µs
E/D COM PIN
Pin voltage
VS ≥ 106 V
(V–)
(V–) +100
V
VS < 106 V
(V–)
(V+) – 6
V
POWER SUPPLY
IQ
6
Quiescent current
IO = 0 mA
3.2
3.7
mA
Quiescent current in Shutdown mode
IO = 0 mA, VE/D = 0.65 V
1.5
2
mA
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6.6 Typical Characteristics: Table of Graphs
Table 1. Table of Graphs
DESCRIPTION
FIGURE
Offset Voltage Production Distribution at 25°C
Figure 1
Offset Voltage Distribution at 85°C
Figure 2
Offset Voltage Distribution at -40°C
Figure 3
Offset Voltage Drift Distribution from -40°C to 85°C
Figure 4
Offset Voltage vs Temperature
Figure 5
Offset Voltage Warmup
Figure 6
Offset Voltage vs Common-Mode Voltage (Low Vcm)
Figure 7
Offset Voltage vs Common-Mode Voltage (High Vcm)
Figure 8
Offset Voltage vs Power Supply (Low Supply)
Figure 9
Offset Voltage vs Power Supply (High Supply)
Figure 10
Offset Voltage vs Output Voltage (Low Output)
Figure 11
Offset Voltage vs Output Voltage (High Output)
Figure 12
CMRR vs Temperature
Figure 13
CMRR vs Frequency
Figure 14
PSRR vs Temperature
Figure 15
PSRR vs Frequency
Figure 16
EMIRR vs Frequency
Figure 17
No Phase Reversal
Figure 18
Input Bias Current Production Distribution at 25℃
Figure 19
IB vs Temperature
Figure 20
IB vs Common-Mode Voltage
Figure 21
Enable Response
Figure 22
Current Limit Response
Figure 23
Open-Loop Gain vs Temperature
Figure 24
Open-Loop Gain vs Output Voltage
Figure 25
Open-Loop Gain and Phase vs Frequency
Figure 26
Open-Loop Output Impedance vs Frequency
Figure 27
Closed-Loop Gain vs Frequency
Figure 28
Maximum Output Voltage vs Frequency
Figure 29
Positive Output Voltage vs Output Current
Figure 30
Negative Output Voltage vs Output Current
Figure 31
Short-Circuit Current vs Temperature
Figure 32
Negative Overload Recovery
Figure 33
Positive Overload Recovery
Figure 34
Settling Time
Figure 35
Phase Margin vs Capacitive Load
Figure 36
Small-Signal Overshoot vs Capacitive Load (G = –1)
Figure 37
Small-Signal Overshoot vs Capacitive Load (G = +1)
Figure 38
Small-Signal Step Response (G = –1)
Figure 39
Small-Signal Step Response (G = +1)
Figure 40
Large-Signal Step Response (G = –1)
Figure 41
Large-Signal Step Response (G = +1)
Figure 42
Slew Rate vs Output Step Size
Figure 43
Slew Rate vs Supply Voltage (Inverting)
Figure 44
Slew Rate vs Supply Voltage (Noninverting)
Figure 45
THD+N Ratio vs Frequency (G = 10)
Figure 46
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Typical Characteristics: Table of Graphs (continued)
Table 1. Table of Graphs (continued)
8
DESCRIPTION
FIGURE
THD+N Ratio vs Frequency (G = 20)
Figure 47
THD+N Ratio vs Output Amplitude (G = 10)
Figure 48
THD+N Ratio vs Output Amplitude (G = 20)
Figure 49
0.1-Hz to 10-Hz Noise
Figure 50
Input Voltage Noise Spectral Density
Figure 51
Current Noise Density
Figure 52
Quiescent Current Production Distribution at 25℃
Figure 53
Quiescent Current vs Supply Voltage
Figure 54
Quiescent Current vs Temperature
Figure 55
Status Flag Voltage vs Temperature
Figure 56
Quiescent Current vs Enable Voltage
Figure 57
Enable Current vs Enable Voltage
Figure 58
Status Flag Current vs Voltage
Figure 59
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6.7 Typical Characteristics
20
20
16
16
Amplifiers (%)
Amplifiers (%)
at TA = 25°C, VS = ±90 V, and RL = 10 kΩ connected to GND, output enabled (unless otherwise noted)
12
8
4
0
-4
12
8
4
-3.2
-2.4
-1.6
-0.8
0
0.8 1.6
Offset Voltage (mV)
2.4
3.2
0
-5
4
Figure 1. Offset Voltage Production Distribution at 25°C
-2
-1
0
1
2
Offset Voltage (mV)
3
4
5
Figure 2. Offset Voltage Distribution at 85°C
25
Amplifiers (%)
16
Amplifiers (%)
-3
30
20
12
8
4
0
-5
-4
20
15
10
5
-4
-3
-2
-1
0
1
2
Offset Voltage (mV)
3
4
0
-20
5
Figure 3. Offset Voltage Distribution at –40°C
-16
-12
-8
-4
0
4
8
Offset Voltage Drift (PV/qC)
12
16
20
Figure 4. Offset Voltage Drift Distribution from –40°C to
+85°C
4
500
3
400
Offset Voltage (PV)
Offset Voltage (mV)
300
2
1
0
-1
-2
100
0
-100
-200
-300
-3
-4
-50
200
-400
-500
-25
0
25
50
Temperature (qC)
75
100
Figure 5. Offset Voltage vs Temperature
100s/div
Figure 6. Offset Voltage Warmup
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Typical Characteristics (continued)
at TA = 25°C, VS = ±90 V, and RL = 10 kΩ connected to GND, output enabled (unless otherwise noted)
4
4
TA = -40
TA = 25
TA = 85
3
2
Offset Voltage (mV)
Offset Voltage (mV)
3
1
0
-1
2
1
0
-1
-2
-2
-3
-3
-4
-90 -89.5 -89 -88.5 -88 -87.5 -87 -86.5 -86 -85.5 -85
Common-mode Voltage (V)
-4
85
4
4
3
3
2
2
1
0
-1
-2
89
90
1
0
-1
-3
-4
3
5
7
9
11
Power Supply Voltage (V)
13
-4
15
Figure 9. Offset Voltage vs Power Supply (Low Supply)
6
5
3
4
2
3
1
0
-1
TA = -40, RL = 5k:
TA = -40, RL = 10k:
TA = 25, RL = 5k:
TA = 25, RL = 10k:
TA = 85, RL = 5k:
TA = 85, RL = 10k:
-2
-3
-4
-5
-90
-88
-86
-84
Output Voltage (V)
-82
-80
Figure 11. Offset Voltage vs Output Voltage (Low Output)
18
30
42
54
66
Power Supply Voltage (V)
78
90
Figure 10. Offset Voltage vs Power Supply (High Supply)
4
Offset Voltage (mV)
Offset Voltage (mV)
87
88
Common-mode Voltage (V)
-2
-3
10
86
Figure 8. Offset Voltage vs Common-Mode Voltage
(High VCM)
Offset Voltage (mV)
Offset Voltage (mV)
Figure 7. Offset Voltage vs Common-Mode Voltage
(Low VCM)
TA = -40
TA = 25
TA = 85
TA = -40, RL = 5k:
TA = -40, RL = 10k:
TA = 25, RL = 5k:
TA = 25, RL = 10k:
TA = 85, RL = 5k:
TA = 85, RL = 10k:
2
1
0
-1
-2
-3
-4
80
82
84
86
Output Voltage (V)
88
90
Figure 12. Offset Voltage vs Output Voltage (High Output)
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Typical Characteristics (continued)
at TA = 25°C, VS = ±90 V, and RL = 10 kΩ connected to GND, output enabled (unless otherwise noted)
0.01
140
0.1
130
120
1
110
100
-50
-25
0
25
50
Temperature (qC)
CMRR
140
Rejection Ratio (dB)
150
160
Common-Mode Rejection Ratio (PV/V)
Common-Mode Rejection Ratio (dB)
160
120
100
80
60
40
20
10
100
75
0
1
10
Figure 13. CMRR vs Temperature
130
1
110
100
-50
-25
0
25
50
Temperature (qC)
PSRR
PSRR
100
80
60
40
0
10m 100m
Figure 15. PSRR vs Temperature
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
Figure 16. PSRR vs Frequency
120
Vin (V)
Vout (V)
110
100
Voltage (25V/div)
EMIRR IN+ (dB)
10M
20
10
100
75
1M
120
Rejection Ratio (dB)
0.1
120
100k
140
Power Supply Rejection Ratio (PV/V)
Power Supply Rejection Ratio (dB)
150
140
1k
10k
Frequency (Hz)
Figure 14. CMRR vs Frequency
0.01
160
100
90
80
70
60
50
10M
100M
1G
Frequency (Hz)
10G
Figure 17. EMIRR vs Frequency
Time (100 Ps/div)
Figure 18. No Phase Reversal
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Typical Characteristics (continued)
at TA = 25°C, VS = ±90 V, and RL = 10 kΩ connected to GND, output enabled (unless otherwise noted)
800
80
IB-, Vs = 6V
IB-, Vs = 90V
IB+, Vs = 6V
IB+, Vs = 90V
IOS, Vs = 6V
IOS, Vs = 90V
700
70
600
Input Bias Current (pA)
Amplifiers (%)
60
50
40
30
20
500
400
300
200
100
0
-100
10
0
-100
-200
-80
-60
-40 -20
0
20
40
Input Bias Current (pA)
60
80
-300
-50
100
-25
Figure 19. Input Bias Current Production Distribution at
25℃
℃
0
25
50
Temperature (qC)
75
100
Figure 20. IB vs Temperature
30
IBIB+
Ios
Voltage (2 V/div)
Input Bias Current (pA)
20
10
0
-10
Enable
Output
Status
-60
-30
0
30
Common-mode Voltage (V)
60
90
Time (2 Ps/div)
Figure 21. IB vs Common-Mode Voltage
4
20
3
0
2
-20
1
-40
0
-60
0.01
150
40
Open-Loop Gain (dB)
VFLAG
IOUT
5
Status Flag (V)
Figure 22. Enable Response
160
60
Output Current (mA)
6
0.1
140
130
1
120
110
10
100
90
Time (200 Ps/div)
Figure 23. Current Limit Response
12
Open-Loop Gain (PV/V)
-20
-90
RL = 10k:
RL = 5k:
80
-50
-25
0
25
50
Temperature (qC)
75
100
100
Figure 24. Open-Loop Gain vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS = ±90 V, and RL = 10 kΩ connected to GND, output enabled (unless otherwise noted)
0.01
120
1
TA
TA
TA
TA
TA
TA
100
=
=
=
=
=
=
80
0
1
2
3
4
5
6
Swing from Rail (V)
-40qC, RL = 10k:
-40qC, RL = 5k:
25qC, RL = 10k: 10
25qC, RL = 5k:
85qC, RL = 10k:
85qC, RL = 5k:
100
7
8
9
10
Gain (dB)
0.1
Open-Loop Gain (PV/V)
140
140
120
200
Gain
Phase 175
100
150
80
125
60
100
40
75
20
50
0
25
-20
10m 100m
Figure 25. Open-Loop Gain vs Output Voltage
1
10
100
1k
10k
Frequency (Hz)
100k
1M
Phase (q)
Open-Loop Gain (dB)
160
0
10M
Figure 26. Open-Loop Gain and Phase vs Frequency
30
10000
G= 1
G= 1
G= 10
20
Zo (:
Gain (dB)
1000
10
0
100
-10
-20
100
10
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
10k
100k
Frequency (Hz)
1M
10M
Figure 28. Closed-Loop Gain vs Frequency
Figure 27. Open-Loop Output Impedance vs Frequency
200
100
Vs=r90 V
Vs=r50 V
Vs=r6 V
175
80
150
Output Voltage (V)
Output Voltage (VPP)
1k
125
100
75
60
40
50
20
TA = -40qC
TA = 25qC
TA = 85qC
25
0
0
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
Figure 29. Maximum Output Voltage vs Frequency
0
10
20
30
Output Current (mA)
40
50
Figure 30. Positive Output Voltage vs Output Current
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Typical Characteristics (continued)
at TA = 25°C, VS = ±90 V, and RL = 10 kΩ connected to GND, output enabled (unless otherwise noted)
60
0
Output Voltage (V)
-20
Short-Circuit Current (mA)
TA = -40qC
TA = 25qC
TA = 85qC
-40
-60
-80
50
40
Sinking
Sourcing
30
-50
-100
0
10
20
30
Output Current (mA)
40
50
Figure 31. Negative Output Voltage vs Output Current
-25
0
25
50
Temperature (qC)
75
100
Figure 32. Short-Circuit Current vs Temperature
Voltage (20 V/div)
Voltage (20 V/div)
VIN
VOUT
VIN
VOUT
Time (500 ns/div)
Time (500 ns/div)
Figure 33. Negative Overload Recovery
Output Delta to Final Value (12 m/div)
Rising
Falling
Phase Margin (q)
50
40
30
20
Time (2 Ps/div)
Figure 35. Settling Time
14
Figure 34. Positive Overload Recovery
60
10
10
100
Cload (pF)
1000
Figure 36. Phase Margin vs Capacitive Load
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Typical Characteristics (continued)
at TA = 25°C, VS = ±90 V, and RL = 10 kΩ connected to GND, output enabled (unless otherwise noted)
80
80
RISO = 0
RISO = 25
RISO = 50
RISO = 0
RISO = 25
RISO = 50
60
Overshoot ( )
Overshoot ( )
60
40
20
0
10
40
20
100
Capactiance (pF)
0
10
1000
G = –1
100
Capactiance (pF)
1000
G = +1
Figure 37. Small-Signal Overshoot vs Capacitive Load
Figure 38. Small-Signal Overshoot vs Capacitive Load
VIN
VOUT
Voltage (5 mV/div)
Voltage (5 mV/div)
VIN
VOUT
Time (1 Ps/div)
Time (1 Ps/div)
G = –1
G = +1
Figure 39. Small-Signal Step Response
Figure 40. Small-Signal Step Response
Vin (V)
Vout (V)
Voltage (20 V/div)
Voltage (20 V/div)
Vin (V)
Vout (V)
Time (2 Ps/div)
Time (2 Ps/div)
G = –1
G = +1
Figure 41. Large-Signal Step Response
Figure 42. Large-Signal Step Response
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Typical Characteristics (continued)
at TA = 25°C, VS = ±90 V, and RL = 10 kΩ connected to GND, output enabled (unless otherwise noted)
33
40
VOUT = 1V
VOUT = 5V
VOUT = 10V
VOUT = 20V
VOUT ! 40V
30
27
30
Slew Rate (V/Ps)
Slew Rate (V/Ps)
24
21
18
15
12
9
20
10
6
G 1
G 1
0
20
40
60
80
100 120
Output Amplitude (VPP)
140
160
0
40
180
Figure 43. Slew Rate vs Output Step Size
100
120
140
Supplpy Voltage (V)
160
-60
10
80
100
120
140
Supplpy Voltage (V)
160
G=
G=
G=
G=
Noise ( )
Total Harmonic Distortion
20
60
180
Figure 44. Slew Rate vs Supply Voltage (Inverting)
VOUT = 1V
VOUT = 5V
VOUT = 10V
VOUT = 20V
VOUT ! 40V
30
Slew Rate (V/Ps)
80
0.1
40
0
40
60
1. 10k: Load
1. 5k: Load
1. 10k: Load
1. 5k: Load
0.01
-80
0.001
-100
0.0001
20
180
Noise (dB)
0
200
Total Harmonic Distortion
3
-120
20k
2k
Frequency (Hz)
G = 10
200
-120
20k
2k
Noise (dB)
-100
0.001
Noise (%)
-80
0.01
1
Total Harmonic Distortion
1. 10k: Load
1. 5k: Load
1. 10k: Load
1. 5k: Load
Total Harmonic Distortion
Total Harmonic Distortion
Noise ( )
G=
G=
G=
G=
0.0001
20
Figure 46. THD+N Ratio vs Frequency
-60
G=
G=
G=
G=
0.1
0.01
-80
0.001
-100
-120
0.0001
100m
1
10
Output Amplitude (VPP)
Frequency (Hz)
G = 20
100
G = 10
Figure 47. THD+N Ratio vs Frequency
16
-40
1, 10k: Load
1, 5k: Load
1, 10k: Load
1, 5k: Load -60
Total Harmonic Distortion + Noise (dB)
Figure 45. Slew Rate vs Supply Voltage (Noninverting)
0.1
Figure 48. THD+N Ratio vs Output Amplitude
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Typical Characteristics (continued)
G=
G=
G=
G=
Total Harmonic Distortion
0.1
-40
1, 10k: Load
1, 5k: Load
1, 10k: Load
1, 5k: Load -60
0.01
-80
0.001
-100
Total Harmonic Distortion + Noise (dB)
Noise (%)
1
Input Referred Voltage Noise (2 PV/div)
at TA = 25°C, VS = ±90 V, and RL = 10 kΩ connected to GND, output enabled (unless otherwise noted)
-120
0.0001
100m
1
10
Output Amplitude (VPP)
Time (1 s/div)
100
G = 20
Figure 49. THD+N Ratio vs Output Amplitude
Figure 50. 0.1-Hz to 10-Hz Noise
10
Current Noise Density (pA/—Hz)
Voltage Noise Spectral Density (nV —Hz)
1000
100
10
1
0.1
0.01
1
10
100
1k
Frequency (Hz)
10k
100k
1
Figure 51. Input Voltage Noise Spectral Density
100
1k
10k
Frequency (Hz)
100k
1M
10M
Figure 52. Current Noise Density
4
Quiescient Current (mA)
60
45
Amplifiers (%)
10
30
15
0
3
2
1
0
2
2.25
2.5
2.75
3
3.25
3.5
Quiescent Current (mA)
3.75
4
Figure 53. Quiescent Current Production Distribution at
25℃
℃
0
20
40
60
Supply Voltage (V)
80
90
Figure 54. Quiescent Current vs Supply Voltage
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Typical Characteristics (continued)
at TA = 25°C, VS = ±90 V, and RL = 10 kΩ connected to GND, output enabled (unless otherwise noted)
1
0.8
3.5
VFLAG to V- (V)
Quiescent Current (mA)
4
3
0.6
0.4
2.5
0.2
E/D Com = -90V
E/D Com = 0V
Vs = 6V
Vs = 90V
2
-50
-25
0
25
50
Temperature (qC)
75
0
-50
100
Figure 55. Quiescent Current vs Temperature
-25
0
75
100
Figure 56. Status Flag Voltage vs Temperature
100
4
E/D Com Current
E/D Current
80
3.5
60
Enable Current (PA)
Quiescent Current (mA)
25
50
Temperature (qC)
3
2.5
2
20
0
-20
-40
-60
TA = -40qC
TA = 25qC
TA = 85qC
1.5
40
-80
1
-100
0
1
2
3
Enable Voltage (V)
4
5
Figure 57. Quiescent Current vs Enable Voltage
0
1
2
3
Enable Voltage (V)
4
5
Figure 58. Enable Current vs Enable Voltage
Status Flag Current (mA)
15
10
5
TA=-40qC
TA=25qC
TA=85qC
0
0
1
2
3
4
Status Flag Voltage - ED COM (V)
5
Figure 59. Status Flag Current vs Voltage
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7 Detailed Description
7.1 Overview
The OPA462 is an operational amplifier (op amp) with high voltage of 180 V, and a high current drive of 30 mA.
This device is unity-gain stable and features a gain-bandwidth product of 6.5 MHz. The high-voltage OPA462
offers excellent accuracy and wide output swing, and has no phase inversion problems that are typically found in
similar op amps. The device can be applied in many common op amp configurations requiring a supply voltage
range from ±6-V to ±90-V.
The OPA462 features an enable-disable function that provides the ability to turn off the output stage and reduce
power consumption when not being used. The device also features a Status Flag pin that indicates an
overtemperature or overcurrent fault conditions.
7.2 Functional Block Diagram
V+
±IN
Differential
Amplifier
+IN
Voltage
Amplifier
High Current
Output Stage
OUT
Biasing
Current Limiting
Enable/Disable
Status
V
E/D
E/D Status
COM Flag
7.3 Feature Description
7.3.1 Status Flag Pin
The Status Flag pin indicates fault conditions and can be used in conjunction with the enable-disable function to
implement fault control loops. This pin is triggered when the device enters an overtemperature or overcurrent
fault condition.
7.3.2 Thermal Protection
The OPA462 features internal thermal protection that is triggered when the junction temperature is greater than
150°C. When the protection circuit is triggered, thermal shutdown occurs to allow the junction to return a safe
operating temperature. Thermal shutdown enables the Status Flag pin, which indicates the device has entered
the thermal shutdown state.
7.3.3 Current Limit
Current limiting is accomplished by internally limiting the drive to the output transistors. The output can supply the
limited current continuously, unless the die temperature rises to 150°C, which initiates thermal shutdown. With
adequate heat dissipation, and use of the lowest possible supply voltage, the OPA462 can remain in current limit
continuously without entering thermal shutdown. The best practice is to provide proper heat dissipation (either by
a physical plate or by airflow) to remain well below the thermal shutdown threshold. For longest operational life of
the device, keep the junction temperature below 125°C.
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Feature Description (continued)
7.3.4 Enable and Disable
If left disconnected, E/D Com is pulled near V– (negative supply) by an internal 10-μA current source. When left
floating, E/D is held approximately 2 V above E/D Com by an internal 1-µA source. Even though active operation
of the OPA462 results when the E/D and E/D Com pins are not connected, a moderately fast, negative-going
signal capacitively coupled to the E/D pin can overpower the 1-µA pullup current and cause device shutdown.
This behavior can appear as an oscillation and is encountered first near extreme cold temperatures. If the enable
function is not used, a conservative approach is to connect E/D through a 30-pF capacitor to a low impedance
source. Another alternative is the connection of an external current source from V+ (positive supply) sufficient to
hold the enable level above the shutdown threshold. Figure 60 shows a circuit that connects E/D and E/D Com.
The E/D Com pin is limited to (V–) + 100 V to enable the use of digital ground in a application where the OPA462
power supply is ±90 V.
When the E/D pin is dropped to a voltage between 0 V and 0.65 V above the E/D Com pin voltage the output of
the OPA462 will become disabled. While in this state the impedance of the output increases to approximately
160 kΩ. Because the inputs are still active, an input signal might be passed to the output of the amplifier. The
voltage at the amplifier output is reduced because of a drop across this output impedance, and may appear
distorted compared to a normal operation output.
After the E/D pin voltage is raised to a voltage between 2.5 V and 5 V greater than the E/D Com, the output
impedance returns to a normal state and the amplifier operates normally.
V+
(Positive Op Amp Supply)
IP
RP
DVDD
(Digital Supply)
V+
5V Logic
E/D
-IN
VOUT
E/D Com
+IN
V-
V(Negative Op Amp Supply)
Figure 60. E/D and E/D Com
7.4 Device Functional Modes
A unique mode of the OPA462 is the output disable capability. This function conserves power during idle periods
(quiescent current drops to approximately 1 mA). This disable is accomplished without disturbing the input signal
path, not only saving power but also protecting the load. This feature makes disable useful for implementing
external fault shutdown loops.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA462 is a high-voltage, high-current operational amplifier capable of operating with supply voltages as
high as ±90 V (180 V), or as low as ±6 V (12 V). The high-voltage process and design of the OPA462 allows the
device to be used in applications where most operational amplifiers cannot be applied, such as high-voltage
power-supply conditions, or when there is a need for very a high-output voltage swing. The output is capable of
delivering up to ±30 mA output current, or swinging within a few volts of the supply rails at moderate current
levels. The OPA462 features input overvoltage protection, output current limiting, thermal protection, a status
flag, and enable-disable capability.
8.2 Typical Applications
8.2.1 High DAC Gain Stage for Semiconductor Test Equipment
R1
10 k
R2
160 k
90 V
100 nF
Status
Flag
Z1
90 V
±
5 VPK
R3
10 k
D1
E/D
+
VI
±
+
3 V to 5 V
E/D Com
D2
Z2
100 nF
RL
10 k
1W
VO
85 VPK
±90 V
±90 V
D1, D2 = 1N5271B zener, PSMA100A TVS, etc.
Z1, Z2 = 1N4935, ES3A, etc. Fast rectifier.
Figure 61. OPA462, High-Voltage Noninverting Amplifier, AV = 17 V/V
8.2.1.1 Design Requirements
The OPA462 high-voltage op amp can be used in commonly applied op amp circuits, but with the added
capability of allowing for the use of much higher supply voltages. A very common application of an op amp is that
of a noninverting amplifier with a gain of 1 V/V or higher. Figure 61 shows the OPA462 in a noninverting
configuration.
The design goals for this circuit are:
• A noninverting gain of 17 V/V (24.6 dB)
• A peak output voltage of 85 V, while driving a 10 kΩ output load
• Correct biasing of E/D and E/D Com
• Protection against back electromagnetic force (EMF)
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Typical Applications (continued)
8.2.1.2 Detailed Design Procedure
Figure 61 shows a noninverting circuit with a moderately high closed-loop gain (AV) of 17 V/V (24.6 dB). In this
example, a 5-VPK ac signal is amplified to 85 VPK across a 10-kΩ load resistor connected to the output. The peak
current for this application is 8.5 mA, and is well within the OPA462 output current capability. Higher output
current, typically up to 30 mA, may be attained at the expense of the output swing to the supply rails. A ±90-VDC
power supply is required for this configuration.
The noninverting amplifier circuit shows the OPA462 enable-disable function. When placed in disabled mode the
op amp becomes nonfunctional, and the current consumption is reduced to approximately one-third to one-half
the enabled level. An enable active state occurs when the E/D pin is left open, or is biased 3 V to 5 V greater
than the E/D Com voltage level. If biased between the E/D com level, to E/D Com + 0.65 V, the OPA462
disables. More information about this function is provided in the Enable and Disable section.
Op amps designed for high-voltage and high-power applications may encounter output loads that can be quite
different than those used in low-voltage, non-power op amp applications. Although every effort is made to make
a high-voltage op amp such as the OPA462 robust and tolerant of different supply and different output load
conditions, some loads can present potentially harmful circumstances.
Purely resistive output loads operating within the current capability range of the OPA462 do not present an
unsafe condition, provided the thermal requirements discussed in the Layout section. Complex loads that have
inductive or capacitive reactive elements might present an unsafe condition, and must be fully considered and
addressed before implementation.
A potentially destructive mechanism is the back EMF transient that can be generated when driving an inductive
load. D1, D2, Z1 and Z2 in Figure 61 have been added to the basic OPA462 amplifier circuit to provide protection
in the event of back EMF. If the voltage at the OPA462 output attempts to momentarily rise above V+, D1
becomes forward-biased and clamps the voltage between the output and V+ pins. This clamp must be sufficient
to protect the OPA462 output transistor. If the event causes the V+ voltage to increase the power supply bypass
capacitor, Z1, or both, a Zener diode or a transient voltage suppressor (TVS) can provide a path for the transient
current to ground. D2 and Z2 provide the same protection in the negative supply circuit.
The OPA462 noninverting amplifier circuit with a closed-loop gain of 17 V/V has a small-signal, –3-dB bandwidth
of nearly 800 kHz. However, the large-signal bandwidth is likely of greater importance in a high-output-voltage
application. For that mode of operation, the slew rate of the op amp and the peak output swing voltage must be
considered in order to determine the maximum large-signal bandwidth. The slew rate (SR) of the OPA462 is
typically 6.5 V/µs, or 6.5 × 106 V/s. Using the 85-VPK output voltage available from the circuit in Figure 61, the
maximum large-signal bandwidth is calculated from the slew rate formula. Equation 1, Equation 2 and Equation 3
show the calculation process.
SR = 23 u fMAX u VPK
(1)
fMAX
(2)
SR / 23 u VPK
6
fMAX
6.5 u 10 V/s / 23 / 85 V
12 kHz
where
•
•
SR = 6.5 × 106 V/s
VPK = 85 V
(3)
The best practice for a typical parameter such as slew rate to allow for variance. In this example, keeping the
large signal fMAX to 10 kHz is sufficient to make sure the output avoids slew rate limiting.
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Typical Applications (continued)
8.2.1.3 Application Curve
Figure 62 shows the OPA462 85-VPK output produced from a 5-VPK, 10-kHz sine input. The results were
obtained from a TINA-TI simulation.
Figure 62. OPA462 Large-Signal Output With a 10-kHz Sine Input From a TINA-TI Simulation
8.2.2 Improved Howland Current Pump for Bioimpedance Measurements in Multiparameter Patient
Monitors
R14
100 k
0V
R15
100 k
90 V
100 nF
R11
100 k
VP
2.5 Vpk
Vo1
R13
125
±
Vout
+
100 nF
±90 V
AM1
RL
500
R12
99.88 k
Figure 63. High-Voltage, 20-mA, Improved Howland Current Pump
8.2.2.1 Design Requirements
The OPA462 can be used to create a high-voltage, improved Howland current pump that provides a constant
output current proportional to a single or differential input voltage applied to the pump inputs. The improved
Howland current pump is described in section 3 of the AN-1515 A Comprehensive Study of the Howland Current
Pump application report. Information about how the current pump resistor values are determined for a specific
combination of input voltage and corresponding output current are detailed in the report. Here, the OPA462 is
used to provide a constant current output over a wide range of output load.
• Input voltage: 2.5 Vpk at 400 Hz
• Output voltage: 20 Vpk
• Output current: ±20 mA in-phase with the output voltage
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Typical Applications (continued)
8.2.2.2 Detailed Design Procedure
The improved Howland current pump circuit is illustrated in Figure 63. The OPA462 sources an output current of
20 mA when a low-voltage single-ended, 2.5-V reference voltage is applied to the circuit input. The source could
be an actual 2.5-V precision reference. If the current-pump output current requires being set to different levels, a
voltage output DAC can be used. If the input voltage polarity is reversed, the output current reverses direction,
and 20 mA is sunk from the load through the OPA462 output.
The circuit shown in Figure 63 provides the resistance values required to obtain a ±20-mA output current with the
2.5-V input voltage applied. The following can be used to select the resistors, thus setting the voltage gain and
output current.
• R13 sets the gain, and is adjusted by the ratio of R14 / R15
• Selecting a low value for R13 enables all other resistors to be high, limiting current through the feedback
network
• The ratio of R11 / (R12 + R13) must equal R14 / R15
• If R14 = R15, then R12 = R11 – R13
Applying these relationships the resistors are selected or derived as follows:
• Let R14 = R15 = 100 kΩ
• R13 = [(VP – VN) (R15 / R14)] / IL = [(2.5 V – 0 V) (105 Ω / 105 Ω)] = 125 Ω
• R12 = (R11 – R13) = (100 kΩ – 125 Ω) = 99.875 kΩ
Verifying R11 / (R12 + R13) must equal R14 / R15 requirement:
• R12 = [R11(R15 / R14)] – R13 = [105 Ω (105 Ω / 105 Ω)] – 125 Ω = 99.875 kΩ
The resistor values for R11 through R15 are seen in Figure 63.
The load is set to be 500 Ω, the sourced output current through the load is 20 mA, and the output voltage is 10
V. The voltage directly at the OPA462 output 2.5 V higher, or 12.5 V, which compensates for the voltage drop
across the 125-Ω R13 resistor. A feedback capacitor can be added to reduce the ac bandwidth of the improved
Howland current pump circuit, if needed. In this example, no capacitor is used.
The improved Howland current pump output is limited to the combined effects of the OPA462 linear output
voltage swing range, the voltage drop developed across R13, and the voltage drop developed across load. For a
particular output current, a maximum output voltage span can be achieved. This span is referred to as the output
voltage compliance range.
The OPA462 current pump sources or sinks a constant current through a load resistance of 0 Ω on the low end,
to just beyond 4.25 kΩ on the high end. This current range is portrayed in the dc transfer plot show in Figure 64.
As shown, the load can be vary from 0 Ω to 4.25 kΩ and the output remains within the span of linear output
compliance range.
Figure 64. Output Voltage Compliance for an Improved Howland Current Pump
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Typical Applications (continued)
The 4.25-kΩ limit is determined by the maximum 85-V drop across the load, and the 2.5-V drop across R13 when
20 mA flows through both. This voltage drop results in an output voltage of 87.5 V at the output of the OPA462,
close to the positive swing limit. Beyond 4.25 kΩ, current-pump operation is forced outside the compliance range,
and the output current is longer maintained at the correct level.
The OPA462 provides this wide output compliance range because of the wide, ±90-V power supply rating. If a
standard ±15-V amplifier supply had been used with the OPA462, or another amplifier rated for ±15-V supplies,
the maximum load resistance is on the order of approximately 500 Ω to 600 Ω, depending on the particular
amplifier linear output range when delivering ±20 mA. The wide supply range of the OPA462 enables the device
to drive a much wider range of loads.
The improved Howland current pump can also be used to generate an accurate ac current with a peak output
that matches a specified dc current level. A ±20-mA dc current source using the OPA462 has already been
discussed; therefore, this current source is applied here to demonstrate how a 400-Hz, 20-mA current is
produced.
The same circuit used in Figure 63 is updated so that the 2.5-V dc voltage source has been replaced by a 400Hz ac source with a peak voltage of 2.5 V, as shown in Figure 65. A sine wave is used in this circuit, but a
triangle wave, square wave, and so on, can be used instead. The output current is dependent on the ac input
voltage at any particular moment.
R14
100 k
R15
100 k
90 V
100 nF
R11
100 k
VP
400 Hz
2.5 Vpk
Vo1
R13
125
±
Vout
+
100 nF
±90 V
AM1
RL
1k
R12
99.88 k
Figure 65. OPA462 Configured as a 400-Hz AC Current Generator
A 2.5-Vpk sine-wave source applied to the input point at R11 results in a 20-mA peak current through the load, as
shown in Figure 66. The load has been set to 1 kΩ, but any resistance that supports the output compliance
range can be used.
Figure 66. Improved Howland Current Pump Applied as a Peak AC-Current Generator
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Typical Applications (continued)
Make sure to consider the power handling ratings of the resistors used with a high-power or high-voltage
amplifier such as the OPA462. In this design, when the OPA462 is providing 20 mA dc to a 4.25-kΩ load
resistance, the dc power for the load and R13 is simply:
• Load Power = I2 ∙ RL = (20 ∙ 10 – 3 A)2 (4.25 ∙ 103 Ω) = 1.7 W
• Power R13 = I2 ∙ R13 = (20 ∙ 10 – 3 A)2 (125 Ω) = 50 mW
Clearly, the power dissipation of the load requires attention. However, in this design, R13 does not require high
power dissipation under these operating conditions. The load must be rated to dissipate the 1.7 W over the
expected operating temperature range for this example. Most often, resistor power dissipation is specified at an
ambient temperature of 25°C, and reduces as temperature increases. The use of a resistor with a power rating
greater than the power that must be dissipated is almost always necessary. For this example, the load may need
to be rated for 3 W, or even 5 W, to make sure that the load does not overheat and maintains reliability. in any
case, determine the power dissipation for the particular operating conditions. Be especially attentive to the power
rating issue regarding surface-mount resistors. The thermal environment in which surface-mount resistors
operate may be much different than a resistor exposed in free air.
The improved Howland current pump amplifier circuit relies on both negative and positive feedback for operation.
More negative feedback than positive feedback is used, but that does not always provide stability when the
output load characteristics are included. When unity-gain stable amplifiers such as the OPA462 are employed,
and they drive a resistive load, the amplifier phase margin should be sufficient so that the circuit is stable.
However, if the output load is complex, containing both resistive and reactive components (R±jX), certain
combinations degrade the phase margin to the point where instability results. Instability is even more evident
when this current pump is used to drive certain inductive loads.
When required, compensation is determined based on the particular circuit to which the OPA462 is being
applied. Amplifier stability and compensation is a vast subject covered in numerous TI documents, and TI training
programs, such as TI Precision Labs – Op Amps.
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9 Power Supply Recommendations
The OPA462 operates from power supplies up to ±90 V, or a total of 180 V, with excellent performance. Most
behavior remains unchanged throughout the full operating voltage range. A power-supply bypass capacitor of at
least 0.1 µF is required for proper operation. Make sure that the capacitor voltage rating is suitable for the high
voltage across the full operating temperature range. Parameters that vary significantly with operating voltage are
shown in the Typical Characteristics section.
Some applications do not require an equal positive and negative output voltage swing. Power-supply voltages do
not have to be equal. The OPA462 operates with as little as 12 V between the supplies, and with up to 180 V
between the supplies.
10 Layout
10.1 Layout Guidelines
10.1.1 Thermally-Enhanced PowerPAD™ Package
The OPA462 comes in an 8-pin SO PowerPAD package that provides an extremely low thermal resistance,
RθJC(bot), path between the die and the exterior of the package. This package features an exposed thermal pad
that has direct thermal contact with the die. Thus, excellent thermal performance is achieved by providing a good
thermal path away from the thermal pad.
The OPA462 SO-8 PowerPAD is a standard-size SO-8 package constructed using a downset leadframe upon
which the die is mounted, as Figure 67 shows. This arrangement results in the leadframe being exposed as a
thermal pad on the underside of the package. The thermal pad on the bottom of the device can then be soldered
directly to the PCB, using the PCB as a heat sink. In addition, plated-through holes (vias) provide a low thermal
resistance heat flow path to the back side of the PCB. This architecture enhances the OPA462 power dissipation
capability significantly, eliminates the use of bulky heat sinks and slugs traditionally used in thermal packages,
and allows the OPA462 to be easily mounted using standard PCB assembly techniques.
NOTE
The SO-8 PowerPAD is pin-compatible with standard SO-8 packages, and as such, the
OPA462 is a drop-in replacement for operational amplifiers in existing sockets. Always
solder the PowerPAD to the PCB V– plane, even with applications that have low power
dissipation. Solder the device to the PCB to provide the necessary thermal, mechanical,
and electrical connections between the leadframe die pad and the PCB.
Leadframe (Copper Alloy)
IC (Silicon)
Mold Compound (Plastic)
Die Attach (Epoxy)
Leadframe Die Pad
Exposed at Base of the Package
(Copper Alloy)
Figure 67. Cross Section View of a PowerPAD™ Package
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Layout Guidelines (continued)
10.1.2 PowerPAD™ Integrated Circuit Package Layout Guidelines
The PowerPAD integrated circuit package allows for both assembly and thermal management in one
manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the
thermal pad must be soldered to a copper area underneath the package. Through the use of thermal paths within
this copper area, heat is conducted away from the package into either a ground plane or other heat-dissipating
device. Always solder the PowerPAD to the PCB, even with applications that have low power dissipation. Follow
these steps to attach the device to the PCB:
1. Connect the PowerPAD to the most negative supply voltage on the device, V–.
2. Prepare the PCB with a top-side etch pattern. There must be etching for the leads, as well as etching for the
thermal pad.
3. Thermal vias improve heat dissipation, but are not required. The thermal pad can connect to the PCB using
an area equal to the pad size with no vias, but externally connected to V–.
4. Place recommended holes in the area of the thermal pad. Recommended thermal land size and thermal via
patterns for the SO-8 DDA package are shown in the thermal land pattern mechanical drawing appended at
the end of this document. These holes must be 13 mils (0.013 in, or 0.3302 mm) in diameter. Keep the holes
small, so that solder wicking through the holes is not a problem during reflow. The minimum recommended
number of holes for the SO-8 PowerPAD package is five.
5. Additional vias can be placed anywhere along the thermal plane outside of the thermal pad area. These vias
help dissipate the heat generated by the OPA462 device. These additional vias may be larger than the 13mil diameter vias directly under the thermal pad because they are not in the thermal pad area to be soldered;
thus, wicking is not a problem.
6. Connect all holes to the internal power plane of the correct voltage potential, V–.
7. When connecting these holes to the plane, do not use the typical web or spoke via connection methodology.
Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during
soldering operations, making the soldering of vias that have plane connections easier. In this application,
however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the
OPA462 PowerPAD package must make the connections to the internal plane with a complete connection
around the entire circumference of the plated-through hole.
8. The top-side solder mask must leave the pins of the package and the thermal pad area exposed. The
bottom-side solder mask must cover the holes of the thermal pad area. This masking prevents solder from
being pulled away from the thermal pad area during the reflow process.
9. Apply solder paste to the exposed thermal pad area and all of the device pins.
10. With these preparatory steps in place, simply place the device in position, and run through the solder reflow
operation as with any standard surface-mount component.
This preparation results in a properly installed device. For detailed information on the PowerPAD package,
including thermal modeling considerations and repair procedures, see the PowerPAD™ Thermally Enhanced
Package application report.
10.1.3 Pin Leakage
When operating the OPA462 with high supply voltages, parasitic leakages may occur between the inputs and the
supplies. This effect is most noticeable at the noninverting input, +IN, when the input common-mode voltage is
high compared to the negative supply voltage, V–. To minimize this leakage, place guard tracing, driven at the
same voltage as the input signal, alongside the input signal traces and pins.
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Layout Guidelines (continued)
10.1.4 Thermal Protection
Figure 68 shows the thermal shutdown behavior of a socketed OPA462 that internally dissipates 1 W.
Unsoldered and in a socket, the RθJA of the DDA package is typically 128°C/W. With the socket at 25°C, the
output stage temperature rises to the shutdown temperature of 150°C, which triggers automatic thermal
shutdown of the device. The device remains in thermal shutdown (output is in a high-impedance state) until it
cools to 130°C where the device is again powered. This thermal protection hysteresis feature typically prevents
the amplifier from leaving the safe operating area, even with a direct short from the output to ground or either
supply. The absolute maximum specification is 180 V, and the OPA462 must not be allowed to exceed 180 V
under any condition. Failure as a result of breakdown, caused by spiking currents into inductive loads
(particularly with elevated supply voltage), is not prevented by the thermal protection architecture.
Figure 68. Thermal Shutdown
10.1.5 Power Dissipation
Power dissipation depends on power supply, signal, and load conditions. For dc signals, power dissipation is
equal to the product of the output current times the voltage across the conducting output transistor, PD = IL (VS –
VO). Power dissipation can be minimized by using the lowest possible power-supply voltage necessary to assure
the required output voltage swing.
For resistive loads, the maximum power dissipation occurs at a dc output voltage of one-half the power-supply
voltage. Dissipation with ac signals is lower because the root-mean square (RMS) value determines heating. The
Instruments, Power Amplifier Stress and Power Handling Limitations application bulletin explains how to
calculate or measure dissipation with unusual loads or signals.
The OPA462 can supply output currents of up to 45 mA. Supplying this level of current is common for op amps
operating from ±15-V supplies. However, with high supply voltages, internal power dissipation of the op amp can
be quite high. Relative to the package size, operation from a single power supply (or unbalanced power supplies)
can produce even greater power dissipation because a large voltage is impressed across the conducting output
transistor. Applications with high power dissipation may require a heat sink or a heat spreader.
10.1.6 Heat Dissipation
Power dissipated in the OPA462 causes the junction temperature to rise. For reliable operation, junction
temperature must be limited to 125°C, maximum. Maintaining a lower junction temperature always results in
higher reliability. Some applications require a heat sink to make sure that the maximum operating junction
temperature is not exceeded. Junction temperature can be determined according to Equation 4:
TJ = TA + PDRθJA
(4)
Package thermal resistance, RθJA , is affected by mounting techniques and environments. Poor air circulation and
use of sockets can significantly increase thermal resistance to the ambient environment. Many op amps placed
closely together also increase the surrounding temperature. Best thermal performance is achieved by soldering
the op amp onto a circuit board with wide printed circuit traces to allow greater conduction through the op amp
leads. Increasing circuit board copper area to approximately 0.5 in2 decreases thermal resistance; however,
minimal improvement occurs beyond 0.5 in2, as shown in Figure 69.
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Layout Guidelines (continued)
For additional information on determining heat sink requirements, consult the Heat Sinking—TO-3 Thermal
Model application bulletin, available for download at www.ti.com.
Thermal Resistance, qJA (°C/W)
60
50
40
30
20
10
0
0
0.5
1.0
1.5
2.0
2.5
3.0
2
Copper Area (inches ), 2 oz
Figure 69. Thermal Resistance vs Circuit Board Copper Area
10.2 Layout Example
E/D COM
Typically V± or GND
E/D
E/D COM
E/D
±IN
V+
±IN
GND
V+
3RZHU3$'Œ
(must connect to
V± or GND)
+IN
+IN
OUT
V±
V±
Status Flag
GND
OUT
Status Flag
Figure 70. OPA462 Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ is
a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a
range of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency
domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 TI Precision Designs
TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the
theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and
measured performance of many useful circuits. TI Precision Designs are available online at
http://www.ti.com/ww/en/analog/precision-designs/.
11.1.1.3 WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to
design, optimize, and simulate complete multistage active filter solutions within minutes.
11.2 Documentation Support
11.2.1 Related Documentation
The following documents are relevant to using the OPA462, and recommended for reference. All are available for
download at www.ti.com unless otherwise noted.
• Texas Instruments, Heat Sinking—TO-3 Thermal Model application bulletin
• Texas Instruments, Power Amplifier Stress and Power Handling Limitations application bulletin
• Texas Instruments, Op Amp Performance Analysis application bulletin
• Texas Instruments, Single-Supply Operation of Operational Amplifiers application bulletin
• Texas Instruments, Tuning in Amplifiers application bulletin
• Texas Instruments, PowerPAD™ Thermally Enhanced Package application report
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11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
PowerPAD, TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA462IDDA
ACTIVE SO PowerPAD
DDA
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
OPA462
OPA462IDDAR
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
OPA462
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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14-Dec-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
OPA462IDDAR
Package Package Pins
Type Drawing
SO
Power
PAD
DDA
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.8
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Dec-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA462IDDAR
SO PowerPAD
DDA
8
2500
366.0
364.0
50.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DDA 8
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
PACKAGE OUTLINE
DDA0008J
PowerPAD TM SOIC - 1.7 mm max height
SCALE 2.400
PLASTIC SMALL OUTLINE
C
6.2
TYP
5.8
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 1.27
8
1
2X
3.81
5.0
4.8
NOTE 3
4
5
B
8X
4.0
3.8
NOTE 4
0.51
0.31
0.1
C A
1.7 MAX
B
0.25
TYP
0.10
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
GAGE PLANE
3.1
2.5
8
1
0 -8
0.15
0.00
1.27
0.40
DETAIL A
2.6
2.0
TYPICAL
4221637/B 03/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012, variation BA.
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EXAMPLE BOARD LAYOUT
DDA0008J
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.6)
SOLDER MASK
OPENING
8X (1.55)
SEE DETAILS
1
8
8X (0.6)
SYMM
(1.3)
TYP
(3.1)
SOLDER MASK
OPENING
(4.9)
NOTE 9
6X (1.27)
5
4
( 0.2) TYP
VIA
METAL COVERED
BY SOLDER MASK
SYMM
(1.3) TYP
(5.4)
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221637/B 03/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
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EXAMPLE STENCIL DESIGN
DDA0008J
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.6)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
1
8
8X (0.6)
(3.1)
BASED ON
0.127 THICK
STENCIL
SYMM
6X (1.27)
5
4
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.150
0.175
2.91 X 3.47
2.6 X 3.1 (SHOWN)
2.37 X 2.83
2.20 X 2.62
4221637/B 03/2016
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
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