Texas Instruments | OPA607 50-MHz, Low-Power, Gain of 6-V/V Stable, Rail-to-Rail Output CMOS Operational Amplifier | Datasheet | Texas Instruments OPA607 50-MHz, Low-Power, Gain of 6-V/V Stable, Rail-to-Rail Output CMOS Operational Amplifier Datasheet

Texas Instruments OPA607 50-MHz, Low-Power, Gain of 6-V/V Stable, Rail-to-Rail Output CMOS Operational Amplifier Datasheet
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OPA607
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1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
The OPA607 is a decompensated (gain = 6 V/V
stable), general-purpose complementary metal oxide
semiconductor (CMOS) operational amplifier (op
amp) that provides low noise of 3.8 nV/√Hz and a
wide gain bandwidth of 50 MHz. The low noise and
wide bandwidth of the OPA607 make the device
attractive for general-purpose applications that
require a good balance between cost and
performance. The high-impedance CMOS inputs
make the OPA607 an ideal amplifier to interface with
sensors with large output impedance (for example,
piezoelectric transducers).
Low IQ: 900 µA (typical)
Gain bandwidth product: 50 MHz
Broadband noise: 3.8 nV/√Hz
Input bias current: 20 pA (maximum)
Offset voltage: 100 µV (typical)
Rail-to-rail output (RRO)
Decompensated, gain ≥ 6 V/V (stable)
Shutdown current: 1 µA (maximum)
Supply range: 2.2 V to 5.5 V
ESD protection: ±3000 V (HBM)
1
The OPA607 features a power-down mode with a
maximum quiescent current of less than 1 µA, making
the device suitable for use in portable batterypowered applications. The rail-to-rail output (RRO) of
the OPA607 can swing up to 10 mV from the supply
rails, enabling maximum dynamic range.
2 Applications
•
•
•
•
•
•
•
•
Current-sensing
Fish finders and sonar
Ultrasonic flow meters
Printers
Light curtains and safety guards
Optical modules
Handheld test equipment
PM2.5 and PM10 particle sensors
This op amp is optimized for low-voltage operation as
low as 2.2 V (±1.1 V) and up to 5.5 V (±2.75 V), and
is specified over the temperature range of –40°C to
+125°C.
Device Information(1)
PART NUMBER
OPA607
PACKAGE
BODY SIZE (NOM)
SC70 (6)
2.00 mm × 1.25 mm
SOT23 (5)(2)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Preview package.
±
+ TLV3201
VS+
±
+
RG
ISH
RSH
±
REXT
ADS7042
OPA607
RG
+
CEXT
1
Output
Input u 20 0.8
Error %
0.6
Short Circuit
Detection
RF
0.4
Voltage (0.5 V/Div)
VTH
LOAD
Settling Performance in a Difference Amplifier
(Gain = 20 V/V, VS = 3.3 V)
0.2
0
-0.2
Error %
OPA607 as a Difference Amplifier for a CurrentSensing Application
RF
-0.4
-0.6
GND
-0.8
VREF
-1
Time (200 nsec/Div)
D100
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
ADVANCE INFORMATION
OPA607 50-MHz, Low-Power, Gain of 6-V/V Stable, Rail-to-Rail Output
CMOS Operational Amplifier
OPA607
SBOS981 – OCTOBER 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
4
4
4
4
5
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
8
8.1 Application Information............................................ 10
8.2 Typical Applications ................................................ 10
9 Power Supply Recommendations...................... 16
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Examples................................................... 16
11 Device and Documentation Support ................. 18
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Detailed Description .............................................. 6
7.1
7.2
7.3
7.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
Application and Implementation ........................ 10
6
6
6
9
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
18
18
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
ADVANCE INFORMATION
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
October 2019
*
Initial release.
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5 Pin Configuration and Functions
DCK Package
6-Pin SC70
Top View
VS±
DBV Package (Preview)
5-Pin SOT-23
Top View
6
VS+
OUT
5
PD
VS±
5
VS+
OUT
Pin Functions
NAME
I/O (1)
DESCRIPTION
DBV
DCK
IN–
4
3
I
Inverting input
IN+
3
1
I
Noninverting input
OUT
1
4
O
Output
PD
—
5
I
Low = amplifier disabled, high = amplifier enabled; see the PowerDown Mode section for more information.
VS–
2
2
P
Negative supply or ground (for single-supply operation)
VS+
5
5
P
Positive supply
(1)
ADVANCE INFORMATION
PIN
I = input, O = output, and P = power.
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
(VS+) – (VS–)
Supply voltage, Vs
VIN+, VIN–
Input voltage (1)
VID
Differential input voltage (1)
±5
V
II
Continuous input current (2)
±10
mA
IO
Continuous output current (3)
±20
mA
(VS–) – 0.5
Continuous power dissipation
6
V
(VS+) + 0.5
V
See Thermal Information
TJ
Maximum junction temperature
150
°C
TA
Operating free-air temperature
–40
125
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
ADVANCE INFORMATION
(3)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should
be current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
Supply voltage (VS+) – (VS–)
TA
Ambient operating temperature
NOM
MAX
2.2
5.5
±1.1
±2.75
–40
25
125
UNIT
V
°C
6.4 Thermal Information
OPA607
THERMAL METRIC (1)
DCK (SC70)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
219.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
182.6
°C/W
RθJB
Junction-to-board thermal resistance
105.7
°C/W
ψJT
Junction-to-top characterization parameter
87
°C/W
ψJB
Junction-to-board characterization parameter
105.4
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
at TA = 25°C, VS = 2.2 V to 5.5 V, G = 6 V/V (1), RF = 5 kΩ, CF = 2.5 pF, VCM = (VS / 2) – 0.5 V, CL = 10 pF, RL = 10 kΩ
connected to (VS / 2) – 0.5 V and PD connected to (VS+) (unless otherwise noted) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
Input offset voltage drift (3)
PSRR
Power-supply rejection ratio
–0.5
TA = –40°C to +125°C
98
0.1
0.5
mV
±0.35
±2.0
µV/°C
120
dB
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
(VS–)
(VS–) < VCM < (VS+) – 1.1 V
94
(VS+) – 1.1
V
100
dB
INPUT BIAS CURRENT
IB
Input bias current (3)
2
20
IOS
Input offset current (3)
2
20
pA
Input voltage noise (peak-to-peak)
f = 0.1 Hz to 10 Hz
1.6
µVPP
eN
Input voltage noise density
f = 10 kHz, 1/f corner at 1 kHz
3.8
nV/√Hz
iN
Input current noise density
f = 1 kHz
47
fA/√Hz
INPUT IMPEDANCE
Differential
CIN
11.5
Common-mode
pF
5.5
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
VOUT = ±1 V
120
Phase margin
140
dB
65
Degrees
AC Characteristics (VS = 5 V)
SSBW
Small-signal bandwidth
VOUT = 20 mVpp
GBW
Gain-bandwidth product
G = 20
SR
Slew rate
3-V output step (10-90%), VOCM = mid-supply
tS
Settling time
9
MHz
50
24
To 0.1%, 3-V step, G = 40, VOCM = mid-supply
0.75
To 0.01%, 3-V step, G = 40, VOCM = mid-supply
1.75
Overdrive recovery time
VIN+ × Gain > VS
HD2
Second-order harmonic distortion
VOUT = 2 VPP f = 20 kHz
-105
HD3
Third-order harmonic distortion
VOUT = 2 VPP f = 20 kHz
-95
V/µs
µs
0.2
µs
dBc
OUTPUT
Output Voltage swing from supply rails
ISC
Short-circuit current
ZO
Open-loop output impedance
8
10
mV
55
mA
f = 1 MHz
500
Ω
IO = 0 mA
900
1000
POWER SUPPLY
IQ
Quiescent current per amplifier
µA
POWER DOWN (Device Enabled When Floating)
IQPD
Power-down quiescent current
PD = VS–
750
1000
IPDB
Power-down pin bias current (4)
PD = VS–
800
900
Enable voltage threshold
Logic-high threshold
Disable voltage threshold
Logic-low threshold
0.7 x VS
0.2 x VS
tON
Turn-on time delay
15
tOFF
Turn-off time delay
0.5
(1)
(2)
(3)
(4)
nA
V
µs
All Gains (G) mentioned are in V/V unless otherwise noted
Parameters with minimum or maximum specification limits are 100% production tested at 25ºC, unless otherwise noted. Over
temperature limits are based on characterization and statistical analysis.
Specified by design and characterization; not production tested.
In Power-Down Mode , IQPD = IPDB + Leakage current drawn by the op amp circuit. Total current in Power-Down mode = IQPD only and
not the sum of IQPD and IPDB
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7 Detailed Description
7.1 Overview
The OPA607 is a low-noise, rail-to-rail output (RRO) operational amplifier (op amp). The device operates from a
supply voltage of 2.2 V to 5.5 V. The input common-mode voltage range also extends down to the negative rail
allowing the OPA607 op amp to be used in most single-supply applications. Rail-to-rail output swing significantly
increases dynamic range, especially in low-supply, voltage-range applications, which results in complete usage
of the full-scale range of the consecutive analog-to-digital converters (ADCs). The decompensated architecture
allows for a favorable tradeoff of low-quiescent current for a very-high gain-bandwidth product (GBW) and lowdistortion performance in high-gain applications.
7.2 Functional Block Diagram
V+
100 k
Reference
SW
PD
PD block
IN+
V
INÛ
NMOS input pair
for phase reversal
protection only
V
BIAS1
Class AB
Control
Circuitry
V
O
V
BIAS2
SW
ADVANCE INFORMATION
V
Current
VÛ
(Ground)
7.3 Feature Description
7.3.1 Operating Voltage
The OPA607 operational amplifier is fully specified and assured for operation from 2.2 V to 5.5 V, applicable from
–40°C to +125°C. The OPA607 is completely operational with asymmetric voltages applied across the supply
pins. The total voltage (that is, (VS+) – (VS–)) must be less than the supply voltage mentioned in the Absolute
Maximum Ratings table.
6
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Feature Description (continued)
7.3.2 Rail-to-Rail Output and Driving Capacitive Loads
Designed as a low-power, low-voltage operational amplifier, the OPA607 delivers a robust output drive capability.
For resistive loads of 10 kΩ, the output swings to within a few millivolts of either supply rail, regardless of the
applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the
rails. The OPA607 drives up to a nominal capacitive load of 10 pF on the output with no special consideration
and without the need of a series isolation resistor RO. When driving capacitive loads greater than 10 pF, TI
recommends using RO as shown in Figure 1 in series with the output as close to the device as possible. Without
RO, the external capacitance (CL) interacts with the output impedance (ZO) of the amplifier, resulting in stability
issues. Inserting RO isolates CL from ZO and restores the phase margin. Figure 1 shows the test circuit.
IOVERLOAD
10mA max
RO
+
VIN
VOUT
OPA607
±
Rf
CL
10 k
Figure 1. Input Current Protection and Driving Capacitive Loads
7.3.3 Input and ESD Protection
When the primary design goal is a linear amplifier with high CMRR, do not exceed the op amp input commonmode voltage range (VCM). This CMRR is used to set the common-mode input range specifications in the
Electrical Characteristics table. The typical specifications for the OPA607 are from the negative rail to 1.1 V
below the positive rail. Assuming the op amp is in linear operation, the voltage difference between the input pins
is small (ideally 0 V) and the input common-mode voltage can be analyzed at either input pin; the other input pin
is assumed to be at the same potential. The voltage at VIN+ is easy to evaluate. In a noninverting configuration
(Figure 1) the input signal, VIN+, must not exceed the VCM rating. However, in an inverting amplifier configuration,
VIN+ must be connected to the voltage within VCM. The input signal applied at VIN- can be any voltage, such that
the output voltage swings with a headroom of 10mV from either of the supply rails.
The input voltage limits have fixed headroom to the power rails and track the power-supply voltages. For single
5-V supply, the linear input voltage range is 0 V to 3.9 V and with a 2.2-V supply this range is 0 V to 1.1 V. The
headroom to each power-supply rail is the same in either case: 0 V and 1.1 V.
The OPA607 also incorporates internal electrostatic discharge (ESD) protection circuits on all pins. For the input
and output pins, this protection primarily consists of current-steering diodes connected between the input and
power-supply pins. These ESD protection diodes also provide input overdrive protection, as long as the current is
limited with a series resistor to 10 mA, as stated in the Absolute Maximum Ratings table. Figure 1 shows a series
input resistor can be added to the driven input to limit the input current. The series input resistor also serves to
cancel input offset voltage resulting from bias current, as detailed in the Device Functional Modes section of the
OPA2834 data sheet.
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Feature Description (continued)
7.3.4 Decompensated Architecture With Wide Gain-Bandwidth Product
Amplifiers such as the OPA607 that are not unity-gain stable are referred to as decompensated amplifiers. The
decompensated architecture typically allows for higher GBW, higher slew rate, and lower noise compared to a
unity-gain stable amplifier with similar quiescent current. The increased available bandwidth reduces the rise time
and the settling time of the op amp, allowing for sampling at faster rates in an ADC-based signal chain.
As shown in Figure 2, the dominant pole fd is moved to the frequency f1 in the case of a decompensated op amp.
The solid AOL plot is the open-loop gain plot of a traditional unity-gain stable op amp. The change in internal
compensation in a decompensated amp such as the OPA607 increases the bandwidth for the same amount of
power. That is, the decompensated op amp has an increased bandwidth to power ratio when compared to a
unity-gain stable op amp of equivalent architecture. Besides the advantages in the above mentioned parameters,
an increased slew rate and a better distortion (HD2 and HD3) value is achieved because of the higher available
loop-gain, compared to its unity-gain counterpart. The most important factor to be considered is to ensure the op
amp is in a noise gain (NG) greater than Gmin. A value of NG lower than Gmin results in instability, as shown in
Figure 2 because the 1/ß curve intersects the AOL curve at 40 dB/decade. This method of analyzing stability is
called the rate of closure method. See the precision lab training videos from TI for a better understanding on
stability and for different techniques of ensuring stability.
ADVANCE INFORMATION
Unity Gain Stable Op Amp
Decompensated Op Amp
AOL
Gmin
´
¶GBP
´
¶d
´
¶1
´
¶u
´
¶2 ´ c
¶u
Figure 2. Gain vs Frequency Characteristics for a Unity-Gain Stable Op Amp
and a Decompensated Op Amp
The OPA607 is stable in a noise gain of 6 V/V (15.56 dB) or higher in conventional gain circuits; see Figure 3.
The device has 9 MHz of small-signal bandwidth (SSBW) in this gain configuration with approximately 65° of
phase margin. The high GBW and low voltage noise of the OPA607 make the device suitable for generalpurpose, high-gain applications.
8
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7.4 Device Functional Modes
The OPA607 has two functional modes: normal operating mode and power-down (PD) mode.
7.4.1 Normal Operating Mode
The OPA607 is operational when the power-supply voltage is between 2.2 V (±1.1 V) and 5.5 V (±2.75 V). Most
newer systems use a single power supply to improve efficiency and simplify the power tree design. The OPA607
can be used with a single-supply power (VS– connected to GND) with no change in performance from split
supply, as long as the input and output pins are biased within the linear operating region of the device. The valid
input and output voltage ranges are given in the Electrical Characteristics table. The outputs nominally swing railto-rail with approximately 10-mV headroom required for linear operation. The inputs can typically swing up to the
negative rail (typically ground) and to within 1.1 V from the positive supply. Figure 3 shows changing from a ±2.5V split supply to a 5-V single-supply.
VSIG
VSIG
Bias
Bias
Signal and bias from
previous stage
OPA607
+
2.5 V
OPA607
+
VOUT
±
VOUT
±
Gain × VSIG
-2.5 V
Gain × Bias
RG
RF
Gain × VSIG
Gain × Bias
Signal and bias to
next stage
RG
RF
Signal and bias to
next stage
Figure 3. Single-Supply and Dual-Supply Operation
7.4.2 Power-Down Mode
The OPA607 features a power-down mode for power critical applications. Under logic control, the amplifier can
be switched from normal operation (consuming ≤ 1 mA) to a power-down current of less than 1 µA. When the PD
pin is connected high, the amplifier is active. Connecting the PD pin to logic low disables the amplifier and places
the output in a high-impedance state. The output of an op amp is high impedance similar to a tri-state highimpedance gate under a power-down condition; however, the feedback network behaves as a parallel load. If the
power-down mode is not used, connect PD to the positive supply pin or leave floating. See the Power Down
(Device Enabled When Floating) section in the Electrical Characteristics table for the enable and disable
threshold voltages. The PD pin can be left floating to keep the op amp always enabled, which is primarily
possible because of the presence of an internal pullup resistor within the op amp that, by default, always keeps
the PD pin weakly tied to VS+.
The PD logic states are transistor-transistor logic (TTL) with reference to the negative supply rail, VS-. When the
op amp is powered from a single supply and ground, driving from logic devices with similar VS+ voltages to the op
amp does not require any special consideration. When the op amp is powered from a split supply, VS- is below
ground and an open-collector type of interface with a pullup resistor is more appropriate.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA607 features a 50-MHz gain bandwidth with 900 µA of supply current, providing good AC performance
at low-power consumption. The low input noise voltage of 3.8 nV/√Hz, the approximate pA of bias current, and a
typical input offset voltage of 0.1 mV make the device very suitable for both AC and DC applications.
8.2 Typical Applications
8.2.1 High-Input Impedance (Hi-Z), Large-Gain Signal Front-End
0.4 nF
ADVANCE INFORMATION
9 NŸ
SW
300 Ÿ
40 NŸ
+2.5V
1.8 NŸ
±
0.1 F
2 NŸ
±
OPA607
+
100 NŸ
To ADC/FDA
OPA836
105 Ÿ
Ultrasonic Sensor
+2.5V
0.4 nF
+
-2.5V
-2.5V
Figure 4. Hi-Z, Large-Gain Front-End Circuit
8.2.1.1 Design Requirements
The objective is to design a high-input impedance, high-dynamic range, signal-conditioning front-end. An
example application for such a front-end circuit is the receive signal chain in an ultrasonic-based end equipment
(EE) such as fish finders, printers, and flow meters. Table 1 lists the design requirements for this application.
Table 1. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Amplifier supply
±2.5 V
Input signal frequency
200 kHz
Minimum voltage
300 µVrms
Minimum SNR at 300 µVrms
40 dB
8.2.1.2 Detailed Design Procedure
The concept used in an ultrasonic transmit (Tx) and receive (Rx) system is to send a large-amplitude tone at a
known frequency and to calculate the time elapsed for the reflections to be received using a highly selective
band-pass filter and to calculate the distance using:
Distance = Time × Speed
(1)
Ultrasound speed is constant for a given medium and the time-of-flight (ToF) is calculated using the method
explained in this section. The transmitter creates these ultrasonic signals by exciting a piezo crystal at its
resonant frequency, which is in turn tuned to be in the ultrasonic frequency spectrum. Fish finders are one the
primary end equipments that use such a Tx and Rx system. Based on the aperture angle and the distance to be
measured in water, a frequency range from 50 kHz to 200 kHz is chosen as a base carrier frequency.
10
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To achieve a SNR of greater than 40 dB for signals from 300 uVrms to 30 mV, a variable-gain front-end stage
based on the OPA607 was chosen. The front-end stage has two gain settings: 6 V/V and 31 V/V. The SW
(switch, relay, or analog mux) can be dynamically toggled to ensure maximum sensitively to the receiving signal.
The OPA607 proves to be an attractive solution for this front-end signal chain because of the high input
impedance of the OPA607. Besides the high input impedance, the OPA607 also has very low quiescent current,
making the device very suitable for a dense, high-channel-count system. The ultrasonic receive sensors (piezo
crystal) have source impedance in the range of a few tens of kilohms. The OPA607 has an input bias current of
20 pA (maximum). This small bias current results in reduced distortion when compared with a bipolar amplifier
with input bias currents in the range of a few hundreds of nano-amperes. The OPA607 large-gain front-end is
followed by a narrowband band-pass filter that is tuned to a 200-kHz center frequency. The narrowband filter is
designed using the OPA836,TI's 5-V bipolar family of op amps with excellent bandwidth to IQ ratio. The driving
stage of the OPA836 is a low-impedance output of the OPA607, hence the higher input bias current of the
OPA836 is not a cause of concern. The OPA836-based band-pass filter was designed using the techniques
mentioned in the Filter Design in Thirty Seconds application report. A 1-µF capacitor is placed in the feedback
network of the OPA607 (as in Figure 4) to reject the DC bias in the received signal since the AC component is of
interest in the received signal. The 1-µF capacitor gives the OPA607 a high-pass response with a low cutoff
frequency that ensures any DC signal picked up by the Rx node is filtered and only the AC signal gets gained.
Figure 6 shows the frequency response of Figure 4. As shown in Figure 6, the frequency response is a high-Q
factor band-pass filter centered around 200 kHz. Designing such a high-Q band-pass filter helps eliminate white
band noise along with other interferences present in the circuitry, resulting in a high SNR signal chain. The
OPA607 front-end and the OPA836-based band-pass filter together help achieve a total gain of 33 dB (44 V/V)
or 50 dB (316 V/V) based on the SW (switch) position. Assuming the maximum full-scale input (FSR) of a dual
supply (±2.5 V) powered ADC to be approximately 2.2 V, the 50-dB gain mode can be used to achieve greater
than a 40-dB SNR for signals from 300 µVrms to 5 mVrms. Because the received signal is a sine wave at 5
mVrms, the Vpeak of the 50-dB amplified signal crosses 2.2 V, resulting in a violation of the maximum input range
of the following ADC, as per the FSR assumptions. Beyond 5 mV, the 33-dB gain mode is used and helps
extend the maximum allowable input voltage from 5 mV to 50 mV. Figure 5 shows the achievable SNR as a
function of the input voltage. Figure 5 shows that operating on the 50-dB gain mode is always favorable until the
input Vrms voltage nears 5 mV to achieve higher SNR.
The SNR value is for the op-amp-based signal chain only. The SNR value of the ADC or fully differential amplifier
(FDA) further effects the reported value in Figure 5 and must be vectorially added to arrive at the total signalchain SNR.
8.2.1.3 Application Curves
100
90
80
60
50 dB Gain
33 dB Gain
50
70
30
Gain (dB)
60
SNR (dB)
Gain setting = 33 dB
Gain setting = 50 dB
40
50
40
20
10
0
-10
-20
30
-30
-40
20
100P
1m
10m
Input RMS voltage (V)
100m
-50
100
D001
Figure 5. Signal-Chain SNR vs Input
1k
10k
100k
Frequency (Hz)
1M
10M
D005
Figure 6. Gain vs Frequency
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The signal chain discussed here, is with a signal frequency at 200 kHz. The signal chain can be tweaked to
support lower frequencies with an appropriate tuning of the band-pass filter. Because the reflected signal
amplitude varies based on the distance of the reflecting object, one of the prime challenges in a design is to have
a wide dynamic range.
OPA607
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8.2.2 Low-Cost, High-Speed Current Sensing
VREF =1.24V
LOAD
TLV431
20 NŸ
ISH
3.3V
3.3V
+
1NŸ
7PŸ
RSH
688 Ÿ
ADS7042
OPA607
±
1NŸ
GND
GND
20 NŸ
GND
240 pF
GND
Figure 7. Hi-Z, High-Speed Front-End Circuit
8.2.2.1 Design Requirements
ADVANCE INFORMATION
The objective of this design is to create a high-speed, high-gain signal chain for bidirectional current-sensing
applications in power systems and motor drive systems. Detailed Design Procedure lists the design requirements
of this application.
Table 2. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Amplifier and ADC supply
3.3 V
Peak current to be measured from load to ground
12 A
Peak current to be measured from ground to load
8A
Accuracy of current measurement
0.1%
Maximum tolerable setting time
1 µs
Current sensing direction
Bidirectional
8.2.2.2 Detailed Design Procedure
The design requirements mentioned in Design Requirements help in designing the complete signal chain. The
aim of the schematic (Figure 7) is to measure bidirectional current with relatively high accuracy in a low-sidesensing-based, high-frequency switching system.
As shown in Figure 7, a single op amp of high bandwidth is capable of accurately sensing current in a highfrequency switching circuit along with driving the consecutive SAR ADC.
Equation 2 gives the output of the OPA607 (VOUT ) in Figure 7.
VOUT = (20 kΩ / 1 kΩ × ISH × RSH) + VREF
where
•
ISH = ISHUNT and RSH = RSHUNT
(2)
As shown Figure 7, the reference voltage applied is 1.24 V. In Equation 2, when the ISH flowing across RSH
equals zero, the output of the difference amplifier is by default biased at a voltage equal to 1.24 V.
When the current (ISH) flows from load to GND, the output of the OPA607 rises above 1.24 V with a value equal
to 20 × VSH where:
VSH = RSH × ISH
(3)
Similarly, when the current flows from GND to load (in the opposite direction) the output of the OPA607 goes
below 1.24 V with a value proportional to 20 × VSH.
The required peak current to be measured is 12 A in the first direction (load to GND).
12
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To calculate the required value of RSH, a rule of thumb can be used. The maximum wattage that can be
dissipated across a surface-mount device (SMD) resistor on a board having a good thermal layout is
approximately 1 W.
Because W = I2 × R, plugging in the values for W and ISH yields a RSH value of approximately 7 mΩ.
The voltage developed across RSH when ISH = 12A is 84 mV.
The maximum allowable voltage at the input of an ADC such as the ADS7042, powered from a 3.3-V VCC, is 3.3
V. This value can be found in the Electrical Characteristics table of the ADS7042 data sheet. However, for this
design, the maximum allowable voltage at the input of the ADC under normal operating condition is assumed to
be 3 V. Thus, the full-scale reading (FSR) for this design can be considered as 3 V. This value enables the
design to have a 300-mV headroom in case the current exceeds the maximum rated value of 12 A. In other
words, for faults and other unexpected conditions, the ADC is capable in measuring currents up to 15 A. The
voltage across RSH must be gained up before being fed to the ADC to increase the dynamic range of the sensing
circuit. Because the considered FSR is 3 V, the output of the OPA607 must swing from the nominal value of 1.24
V to 3 V, whereas an ISH of 12 A is made to flow across RSH.
Equation 4 defines the signal gain required by the op amp, which results in a gain of approximately 20 V/V.
(4)
Currents flowing across RSH in either direction are gained by 20 V/V and swing the output above or below the
nominal 1.24 V proportionally. If the gain value is frozen at 20 V/V, then Equation 5 defines the maximum current
that can be measured in the direction of GND to load. ISH = 8.8 A derived from Equation 5 meets the initial
design requirement of current measuring capability of 8 A from GND to load.
ISH = 1.24 V / (RSH × 20 V/V)
(5)
The next step is to arrive at the right GBW of an op amp that can drive a SAR ADC, while still being able to gain
the signal by 20 V/V. As discussed further in this section, the calculations point towards an op amp with GBW in
the vicinity of 50 MHz.
A 20-kHz switching system such as a motor driver card has a minimum possible duty cycle of approximately 5%.
Thus when the control card is running at its lowest duty cycle, the width of the current pulse (as shown in
Figure 8) shrinks to approximately 2.5 µs. The current pulses are very narrow and require the op amp output to
settle to the final value within this short span of time. Figure 8 is an exaggerated figure showing the typical
current waveform in a low-side current-sensing signal chain of a sinusoidal-driven brushless DC electric motor
(BLDC). An op amp must be able to settle to its 0.1% accuracy within this time period to ensure the current value
flowing across RSH is captured in less than 2.5 µs. In reality, ensuring the op amp settles in less than 1 µs can be
very desirable because the same amplification circuit can be fed to the comparator for short-circuit protection.
This feature brings as additional value of using a high-bandwidth op amp in a current-sensing circuit. Because of
the high bandwidth of the OPA607, as with any op amp, the rise time (which is the prime parameter deciding the
response time of the short circuit protection circuitry) becomes very small.
Equation 6 describes how the rise time and the bandwidth of a op amp are related to each other.
tR (sec) = 0.35 Hz / BW
(6)
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Gain = (3 V – 1.24 V) / 84 mV
OPA607
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Current
SBOS981 – OCTOBER 2019
Current waveform
Time (50 msec/Div)
D004
Figure 8. Low-Side Current-Sensing Waveform in a BLDC Motor Control
ADVANCE INFORMATION
An ADC capturing the data at 500 kSPS puts out a sampled data one time every 2 µs. Because the minimum
current pulse duration while running at a 5% duty cycle is 2.5 µs, a 500-kSPS sampling rate ADC is sufficient for
this BLDC current-sensing application. The ADS7042 is a low-power, 12-bit, 1-MSPS, SAR ADC. The ADS7042
is operated at 500 kSPS via SCLK at a frequency of 12.5 MHz, which is a standard clock frequency available for
SPI communications. For an ADC running at a sampling rate of 500 kSPS on a clock of 12.5 MHz, the bandwidth
of the op amp required to drive such an ADC is approximately 2.7 MHz. See the TI precision lab videos on
driving SAR ADCs to understand the underlying calculation. The OPA607 has a GBW of 50 MHz. With a gain of
20 V/V, the effective bandwidth available with the OPA607 comes out to approximately 2.5 MHz, making the
device the most suitable, cost-optimized amplifier for this application. The RC (240 Ω and 688 pF in Figure 7)
charge bucket designed at the input of the SAR ADC is also derived from the calculations provided in the SAR
ADC precision lab videos. The fundamental concept behind the design of this charge bucket is to ensure that the
acquisition capacitor is charged up to the required final voltage within the acquisition window of the ADC.
The ADS7042 samples at 500 kSPS with a 12.5-MHz clock, which translates to a conversion time of 1 µs out of
the total time period of 2 µs (1 / 500 kHz). These calculations for different sampling rates and clock frequencies
can be found in the ADS7042 data sheet. With the conversion time of 1 µs out of the 2 µs, the OPA607 is left
with 1 µs to settle to the required accuracy of 0.1%. Because the full-scale voltage is assumed to be 3 V, an
accuracy of 0.1% translates to a maximum allowable error voltage of 3 mV. Thus, the OPA607 must settle to ±3
mV of its final intended value within 1 µs.
Figure 9 shows the TINA™ simulation plots for the OPA607 driving the ADS7042. Input voltage (red) is the
signal swing across the shunt resistance and the error signal (blue) is representative of the % error in the output
of the op amp. As shown at the initial region of the graph in Figure 9, at the time instant (to), the input signal
sharply transits from its lowermost point to the uppermost point. This transition can be considered as a shortcircuit event or step increase in current resulting from a sudden metal-oxide-semiconductor field-effect transistor
(MOSFET) switching. The output (black) waveform tries to follow the high slew rate input signal but is limited by
the effective bandwidth of the op amp used. Thus, a higher bandwidth op amp results in the output being able to
more closely track the input. The difference between the output and input is represented by the error waveform
and the goal of the design is to reduce this error to less than 0.1% within the acquisition window of the ADC. The
acquisition window of the ADC is shown in the yellow highlighted regions of Figure 9. Thus the % error signal
(blue) must settle down to less than 0.1% before the end of this 1-µs window (within the yellow marked region).
As illustrated in Figure 9, the error signal comfortably settles to the final value with an error % of –0.025%, which
is well within the required 0.1% accuracy. Thus, the OPA607 settles to 0.1% accuracy within 1 µs with a worstcase, 0-V to 3-V full-scale transient output that is also in a gain configuration of 20 V/V. The OPA607 enables
single-sample settling for the ADS7042 running on a 12.5-MHz clock with 500 kSPS, thus making the device a
very cost-optimized, single amplifier solution.
Figure 10 gives the DC transfer characteristics of the circuit in Figure 7. As per the parameters from Table 2 the
current across RSH is varied in both directions and the voltage at the output of the OPA607 is measured.
Equation 7 describes the relation between the output of the OPA607 and the ISH current:
VO = (20 × ISH × 7 mΩ) + 1.24 V
14
(7)
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The target of the design is to achieve 0.1% measurement accuracy across –8 A to 12 A. As shown in Figure 10,
a DC accuracy of higher than 0.05% is achieved with the OPA607. The simulations are captured with and
without voltage offset calibration. The error at the output of the OPA607 increases drastically below –8 A and
above 12 A because of the RRO limitations of the OPA607. Increasing the supply of the OPA607 to 5-V VCC with
a suitable ADC enables a wider current measurement range to be obtained. Similarly reducing the gain from the
existing 20 V/V or reducing the value of RSH can equivalently help scale the required measurement current.
8.2.2.3 Application Curves
6
3.6
0.5
Measured Output
0.4
Ideal Output
% Error w/o offset correction 0.3
% Error with offset correction
0.2
2.8
0.1
5.2
2
0
1.2
-0.1
0.4
-0.2
-0.4
-0.3
-1.2
-0.4
-2
-20
-16
Figure 9. OPA607 Settling Performance With the ADS7042
-12
-8
-4
0
4
8
Current across RSH (A)
12
16
-0.5
20
D003
Figure 10. DC Current-Sense Transfer Function
8.2.3
Ultrasonic Flow Meters
OPA607
OPA607
Figure 11. High-Gain Ultrasonic Front-End
8.2.3.1 Design Requirements
The OPA607 has a wide operating voltage range of 2.2 V to 5.5 V with a maximum quiescent current of 1 mA.
The availability of the inbuilt shutdown function enables designers to power cycle the front-end signal chain,
reducing the net quiescent current even further. The minimum operating voltage range of 2.2 V proves to be very
suitable for battery-powered applications such as the ultrasonic-based flow meters. The high-gain bandwidth of
the OPA607 enables the gain stages and the ADC drive stages to be designed and combined, thereby reducing
component count. A schematic similar to that of Figure 7 can be used in ultrasonic flow meters for the front-end
signal chain.
The Ultrasonic sensing subsystem reference design for gas flow measurement design guide has a detailed
design procedure for ultrasonic-based sensing for gas flow measurement. The OPA607 is a very suitable op amp
for the discrete front-end design described in this design guide.
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Voltage (V)
4.4
OPA607
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9 Power Supply Recommendations
The OPA607 is specified for operation from 2.2 V to 5.5 V (±1.1 V to ±2.75 V), applicable from –40°C to +125°C.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies.
CAUTION
Supply voltages larger than 6 V can permanently damage the device (see the Absolute
Maximum Ratings table).
For more detailed information on bypass capacitor placement, see the Layout Guidelines section.
10 Layout
10.1 Layout Guidelines
V+
10.2 Layout Examples
INPUT
ADVANCE INFORMATION
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power-supply pins of the circuit as a whole and of
the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing lowimpedance power sources local to the analog circuitry.
– Connect low-equivalent series resistance (ESR), 0.1-µF ceramic bypass capacitors between each
supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+
to ground is applicable for single-supply applications.
• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most
effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to
ground planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI)
noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of
the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than crossing in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the
inverting input minimizes parasitic capacitance; see Figure 12 and Figure 13.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
GND
GND
OUTPUT
V-
GND
Figure 12. Operational Amplifier Board Layout for a Noninverting Configuration
16
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Layout Examples (continued)
VC3
INPUT
OUTPUT
1 +
3
±
U1
OPAx607
2
R3
4
6
5 C4
C2
V+
R1
ADVANCE INFORMATION
C1
R2
Figure 13. Layout Example Schematic
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
Texas Instruments, precision lab videos
11.2 Documentation Support
11.2.1 Related Documentation
ADVANCE INFORMATION
For related documentation see the following:
• Texas Instruments, OPA2834 50-MHz, 170-μA, Negative-Rail In, Rail-to-Rail Out, Voltage-Feedback Amplifier
data sheet
• Texas Instruments, ADS7042 Ultra-Low Power, Ultra-Small Size, 12-Bit, 1-MSPS, SAR ADC data sheet
• Texas Instruments, Ultrasonic Sensing Subsystem Reference Design For Gas Flow Measurement design
guide
• Texas Instruments, OPAx836 Very-Low-Power, Rail-to-Rail Out, Negative Rail In, Voltage-Feedback
Operational Amplifiers data sheet
• Texas Instruments, Filter Design in Thirty Seconds application report
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TINA, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
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PACKAGE OPTION ADDENDUM
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2-Nov-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA607IDCKR
PREVIEW
SC70
DCK
6
3000
TBD
Call TI
Call TI
-40 to 125
OPA607IDCKT
PREVIEW
SC70
DCK
6
250
TBD
Call TI
Call TI
-40 to 125
XOPA607IDCKT
ACTIVE
SC70
DCK
6
250
TBD
Call TI
Call TI
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
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