Texas Instruments | TLV915x 4.5-MHz, Rail-to-Rail Input/Output, Low Offset Voltage, Low Noise Op Amp | Datasheet | Texas Instruments TLV915x 4.5-MHz, Rail-to-Rail Input/Output, Low Offset Voltage, Low Noise Op Amp Datasheet

Texas Instruments TLV915x 4.5-MHz, Rail-to-Rail Input/Output, Low Offset Voltage, Low Noise Op Amp Datasheet
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TLV9152
SBOS986 – OCTOBER 2019
TLV915x 4.5-MHz, Rail-to-Rail Input/Output, Low Offset Voltage, Low Noise Op Amp
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
The TLV915x family (TLV9151, TLV9152, and
TLV9154) is a family of 16-V, general purpose
operational
amplifiers.
These
devices
offer
exceptional DC precision and AC performance,
including rail-to-rail output, low offset (±125 µV, typ),
low offset drift (±0.3 µV/°C, typ), and 4.5-MHz
bandwidth.
•
•
Low offset voltage: ±125 µV
Low offset voltage drift: ±0.3 µV/°C
Low noise: 10.5 nV/√Hz at 1 kHz
High common-mode rejection: 120 dB
Low bias current: ±10 pA
Rail-to-rail input and output
Wide bandwidth: 4.5-MHz GBW
High slew rate: 20 V/µs
Low quiescent current: 560 µA per amplifier
Wide supply: ±1.35 V to ±8 V, 2.7 V to 16 V
Robust EMIRR performance: EMI/RFI filters on
input pins
Differential and common-mode input voltage
range to supply rail
Industry standard packages:
– Single in SOT-23-5, SC70-5, and SOT553
– Dual in SOIC-8, SOT-23-8, TSSOP-8, VSSOP8, WSON-8, and X2QFN-10
– Quad in SOIC-14, TSSOP-14, WQFN-14, and
WQFN-16
Convenient features such as wide differential inputvoltage range, high output current (±75 mA), high
slew rate (20 V/μs), and low noise (10.5 nV/√Hz)
make the TLV915x a robust, low-noise operational
amplifier for industrial applications.
The TLV915x family of op amps is available in
standard packages and is specified from –40°C to
125°C.
Device Information(1)
PART NUMBER
TLV9151
TLV9152
Low-power audio preamplifier
Multiplexed data-acquisition systems
Test and measurement equipment
ADC driver amplifiers
SAR ADC reference buffers
Programmable logic controllers
High-side and low-side current sensing
High precision comparator
SOT-23 (5)
2.90 mm × 1.60 mm
SOT-23 (6)(2)
2.90 mm × 1.60 mm
SC70 (5)(2)
2.00 mm × 1.25 mm
SOT-553 (5)
1.60 mm × 1.20 mm
SOIC (8)(2)
4.90 mm × 3.90 mm
TSSOP (8)(2)
3.00 mm × 4.40 mm
(2)
VSSOP (8)
3.00 mm × 3.00 mm
VSSOP (10)(2)
3.00 mm × 3.00 mm
WSON (8)(2)
2.00 mm × 2.00 mm
X2QFN (10)(2)
1.50 mm × 1.50 mm
(2)
TLV9154
BODY SIZE (NOM)
(2)
(2)
2 Applications
•
•
•
•
•
•
•
•
PACKAGE
SOIC (14)
8.65 mm × 3.90 mm
TSSOP (14)(2)
5.00 mm × 4.40 mm
WQFN (16)(2)
3.00 mm × 3.00 mm
(2)
2.00 mm × 2.00 mm
WQFN (14)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) This package is preview only.
TLV915x in a Single-Pole, Low-Pass Filter
RG
RF
R1
VOUT
VIN
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
1
2pR1C1
(
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
ADVANCE INFORMATION
1
TLV9152
SBOS986 – OCTOBER 2019
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Table of Contents
1
2
3
4
5
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
7.4 Device Functional Modes........................................ 21
Features .................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions ......................... 3
Specifications....................................................... 10
Absolute Maximum Ratings ....................................
ESD Ratings............................................................
Recommended Operating Conditions.....................
Thermal Information for Single Channel .................
Thermal Information for Dual Channel....................
Thermal Information for Quad Channel ..................
Electrical Characteristics.........................................
8
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Applications ................................................ 22
9 Power Supply Recommendations...................... 24
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example .................................................... 25
10
10
10
10
11
11
12
11 Device and Documentation Support ................. 26
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 15
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
26
27
ADVANCE INFORMATION
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
October 2019
*
Initial release.
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5 Pin Configuration and Functions
TLV9151 DBV and DRL Package(1)
5-Pin SOT-23 and SOT-553
Top View
OUT
V±
IN+
1
5
TLV9151 DCK Package(1)
5-Pin SC70
Top View
V+
IN+
1
V±
2
IN±
3
5
V+
4
OUT
2
3
4
IN±
Not to scale
Not to scale
(1)
Package is preview only.
(1)
Package is preview only.
ADVANCE INFORMATION
Pin Functions: TLV9151
PIN
I/O
DESCRIPTION
DBV, DCK,
DRL
DCK
+IN
3
1
I
Noninverting input
–IN
4
3
I
Inverting input
OUT
1
4
O
Output
V+
5
5
—
Positive (highest) power supply
V–
2
2
—
Negative (lowest) power supply
NAME
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TLV9151S DBV and DRL Package(1)
6-Pin SOT-23 and SOT-563
Top View
OUT
1
6
V+
V±
2
5
NC
+IN
3
4
±IN
Not to scale
(1)
Package is preview only.
Pin Functions: TLV9151S
PIN
NAME
DBV, DRL
I/O
DESCRIPTION
ADVANCE INFORMATION
+IN
3
I
Noninverting input
–IN
4
I
Inverting input
OUT
1
O
Output
SHDN
5
I
Shutdown (active low) logic input
V+
6
—
Positive (highest) power supply
V–
2
—
Negative (lowest) power supply
4
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TLV9152
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TLV9152 D, DDF, DGK, and PW Packages(1)
8-Pin SOIC, SOT-23-8, TSSOP, and VSSOP
Top View
TLV9152 DSG Package(1)(2)
8-Pin WSON With Exposed Thermal Pad
Top View
OUT1
1
8
V+
IN1±
2
7
OUT2
OUT1
1
IN1+
3
6
IN2±
IN1±
2
V±
4
5
IN2+
IN1+
3
V±
4
Thermal
Pad
8
V+
7
OUT2
6
IN2±
5
IN2+
Not to scale
(1)
Package is preview only.
(1)
Connect thermal pad to V–.
(2)
Package is preview only. See Packages
With an Exposed Thermal Pad section for
more information.
ADVANCE INFORMATION
Not to scale
Pin Functions: TLV9152
PIN
SOIC, TSSOP,
VSSOP, WSON
I/O
+IN A
3
I
Noninverting input, channel A
+IN B
5
I
Noninverting input, channel B
–IN A
2
I
Inverting input, channel A
–IN B
6
I
Inverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V+
8
—
Positive (highest) power supply
V–
4
—
Negative (lowest) power supply
NAME
DESCRIPTION
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TLV9152S DGS Package(1)
10-Pin VSSOP
Top View
TLV9152S RUG Package(1)
10-Pin X2QFN
Top View
1
10
V+
IN1±
2
9
OUT2
IN1+
3
8
IN2±
V±
4
7
IN2+
SHDN1
5
6
SHDN2
IN1+
OUT1
1
9
IN1±
SHDN1
2
8
OUT1
SHDN2
3
7
V+
IN2+
4
6
OUT2
10
Not to scale
Package is preview only.
5
(1)
V±
IN2±
ADVANCE INFORMATION
Not to scale
(1)
Package is preview only.
Pin Functions: TLV9152S
PIN
NAME
I/O
DESCRIPTION
VSSOP
X2QFN
+IN A
3
10
I
Noninverting input, channel A
+IN B
7
4
I
Noninverting input, channel B
–IN A
2
9
I
Inverting input, channel A
–IN B
8
5
I
Inverting input, channel B
OUT A
1
8
O
Output, channel A
OUT B
9
6
O
Output, channel B
SHDN 1
5
2
I
Shutdown, channel 1: low = amplifier enabled, high = amplifier
disabled. See Shutdown section for more information.
SHDN 2
6
3
I
Shutdown, channel 2: low = amplifier enabled, high = amplifier
disabled. See Shutdown section for more information.
V+
10
7
—
Positive (highest) power supply
V–
4
1
—
Negative (lowest) power supply
6
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TLV9154 D and PW Packages(1)
14-Pin SOIC and TSSOP
Top View
IN4±
IN1+
3
12
IN4+
V+
4
11
V±
IN2+
5
10
IN3+
IN2±
6
9
IN3±
OUT2
7
8
OUT3
IN1±
1
12
IN4±
IN1+
2
11
IN4+
V+
3
10
V±
IN2+
4
9
IN3+
IN2±
5
8
IN3±
Not to scale
(1)
Package is preview only.
IN1+
1
V+
2
OUT2
TLV9154 RTE Package(1)(2)
16-Pin WQFN With Exposed Thermal Pad
Top View
IN1±
OUT1
OUT4
IN4±
16
15
14
13
(1)
12
IN4+
11
V±
10
IN3+
9
IN3±
ADVANCE INFORMATION
13
OUT4
2
13
IN1±
7
OUT4
OUT3
14
14
1
6
OUT1
OUT1
TLV9154 RUC Packages(1)
14-Pin WQFN With Exposed Thermal Pad
Top View
Not to scale
Package is preview only.
Thermal
6
7
8
NC
OUT3
4
NC
IN2±
Pad
5
3
OUT2
IN2+
Not to scale
(1)
Connect thermal pad to V–. See Packages
With an Exposed Thermal Pad section for
more information.
(2)
Package is preview only.
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Pin Functions: TLV9154
PIN
NAME
SOIC, TSSOP
WQFN
I/O
DESCRIPTION
ADVANCE INFORMATION
IN1+
3
1
I
Noninverting input, channel 1
IN1–
2
16
I
Inverting input, channel 1
IN2+
5
3
I
Noninverting input, channel 2
IN2–
6
4
I
Inverting input, channel 2
IN3+
10
10
I
Noninverting input, channel 3
IN3–
9
9
I
Inverting input, channel 3
IN4+
12
12
I
Noninverting input, channel 4
IN4–
13
13
I
Inverting input, channel 4
NC
—
6, 7
—
Do not connect
OUT1
1
15
O
Output, channel 1
OUT2
7
5
O
Output, channel 2
OUT3
8
8
O
Output, channel 3
OUT4
14
14
O
Output, channel 4
V+
4
2
—
Positive (highest) power supply
V–
11
11
—
Negative (lowest) power supply
8
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IN1+
1
V+
2
IN1±
OUT1
OUT4
IN4±
16
15
14
13
TLV9154S RTE Package(1)
16-Pin WQFN With Exposed Thermal Pad
Top View
12
IN4+
11
V±
10
IN3+
9
IN3±
(1)
6
7
8
SHDN34
OUT3
4
SHDN12
IN2±
Pad
5
3
OUT2
IN2+
ADVANCE INFORMATION
Thermal
Not to scale
Package is preview only.
Pin Functions: TLV9154S
PIN
NAME
RTE
I/O
DESCRIPTION
IN1+
1
I
Noninverting input, channel 1
IN1–
16
I
Inverting input, channel 1
IN2+
3
I
Noninverting input, channel 2
IN2–
4
I
Inverting input, channel 2
IN3+
10
I
Noninverting input, channel 3
IN3–
9
I
Inverting input, channel 3
IN4+
12
I
Noninverting input, channel 4
IN4–
13
I
Inverting input, channel 4
OUT1
15
O
Output, channel 1
OUT2
5
O
Output, channel 2
OUT3
8
O
Output, channel 3
OUT4
14
O
Output, channel 4
SHDN12
6
I
Shutdown (active low), channel 1 & 2, logic input
SHDN34
7
I
Shutdown (active low), channel 3 & 4, logic input
VCC+
2
—
Positive (highest) power supply
VCC–
11
—
Negative (lowest) power supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)
(1)
MIN
MAX
0
20
V
(V–) – 0.5
(V+) + 0.5
V
Supply voltage, VS = (V+) – (V–)
Common-mode voltage
Signal input pins
Differential voltage
Current
Output short-circuit
(2)
(2)
VS + 0.2
(2)
–10
(3)
–55
Junction temperature, TJ
Storage temperature, Tstg
(2)
ADVANCE INFORMATION
(3)
V
10
mA
150
°C
150
°C
150
°C
Continuous
Operating ambient temperature, TA
(1)
UNIT
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
UNIT
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101
(2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
VS
Supply voltage, (V+) – (V–)
VI
Input voltage range
TA
Specified temperature
MIN
MAX
2.7
16
UNIT
(V–) – 0.1
(V+) + 0.1
V
–40
125
°C
V
6.4 Thermal Information for Single Channel
TLV9151, TLV9151S
THERMAL METRIC
DBV (2)
(SOT-23)
(1)
DCK (2)
(SC70)
DRL (2)
(SOT-553)
UNIT
5 PINS
6 PINS
5 PINS
5 PINS
6 PINS
RθJA
Junction-to-ambient thermal resistance
TBD
TBD
TBD
TBD
TBD
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
TBD
TBD
TBD
TBD
TBD
°C/W
RθJB
Junction-to-board thermal resistance
TBD
TBD
TBD
TBD
TBD
°C/W
ψJT
Junction-to-top characterization parameter
TBD
TBD
TBD
TBD
TBD
°C/W
ψJB
Junction-to-board characterization parameter
TBD
TBD
TBD
TBD
TBD
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
TBD
TBD
TBD
TBD
TBD
°C/W
(1)
(2)
10
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
This package option is preview for TLV9151.
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6.5 Thermal Information for Dual Channel
TLV9152, TLV9152S
THERMAL METRIC
(1)
D (2)
(SOIC)
DDF (2)
(SOT-23-8)
DGK (2)
(VSSOP)
DGS (2)
(VSSOP)
DSG (2)
(WSON)
PW (2)
(TSSOP)
RUG (2)
(X2QFN)
UNIT
8 PINS
8 PINS
8 PINS
10 PINS
8 PINS
8 PINS
10 PINS
RθJA
Junction-to-ambient
thermal resistance
138.7
TBD
TBD
TBD
TBD
TBD
TBD
°C/W
RθJC(top)
Junction-to-case (top)
thermal resistance
78.7
TBD
TBD
TBD
TBD
TBD
TBD
°C/W
RθJB
Junction-to-board thermal
resistance
82.2
TBD
TBD
TBD
TBD
TBD
TBD
°C/W
ψJT
Junction-to-top
characterization parameter
27.8
TBD
TBD
TBD
TBD
TBD
TBD
°C/W
ψJB
Junction-to-board
characterization parameter
81.4
TBD
TBD
TBD
TBD
TBD
TBD
°C/W
RθJC(bot)
Junction-to-case (bottom)
thermal resistance
N/A
TBD
TBD
TBD
TBD
TBD
TBD
°C/W
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
This package option is preview for TLV9152.
ADVANCE INFORMATION
(1)
6.6 Thermal Information for Quad Channel
TLV9154, TLV9154S
THERMAL METRIC
(1)
D (2)
(SOIC)
PW (2)
(TSSOP)
RTE (2)
(WQFN)
RUC (2)
(WQFN)
UNIT
14 PINS
14 PINS
16 PINS
16 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
TBD
TBD
TBD
TBD
TBD
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
TBD
TBD
TBD
TBD
TBD
°C/W
RθJB
Junction-to-board thermal resistance
TBD
TBD
TBD
TBD
TBD
°C/W
ψJT
Junction-to-top characterization parameter
TBD
TBD
TBD
TBD
TBD
°C/W
ψJB
Junction-to-board characterization
parameter
TBD
TBD
TBD
TBD
TBD
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
TBD
TBD
TBD
TBD
TBD
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
This package option is preview for TLV9154.
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6.7 Electrical Characteristics
For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT
= VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±125
±675
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
VCM = V–
dVOS/dT
Input offset voltage drift
PSRR
Input offset voltage
versus power supply
VCM = V–, VS = 4 V to 16 V
Channel separation
f = 0 Hz
TA = –40°C to 125°C
±720
TA = –40°C to 125°C
VCM = V–, VS = 2.7 V to 16 V (1)
±0.3
TA = –40°C to 125°C
µV
µV/℃
±0.3
±1
±1
±5
5
μV/V
µV/V
INPUT BIAS CURRENT
IB
Input bias current
±10
pA
IOS
Input offset current
±10
pA
NOISE
1.5
μVPP
0.25
µVRMS
ADVANCE INFORMATION
EN
Input voltage noise
f = 0.1 Hz to 10 Hz
eN
Input voltage noise
density
f = 1 kHz
10
f = 10 kHz
9.5
iN
Input current noise
f = 1 kHz
nV/√Hz
2
fA/√Hz
INPUT VOLTAGE RANGE
Common-mode voltage
range
VCM
(V–) – 0.2
VS = 16 V, (V–) – 0.1 V < VCM <
(V+) – 2 V (Main input pair)
CMRR
Common-mode rejection
ratio
VS = 4 V, (V–) – 0.1 V < VCM <
(V+) – 2 V (Main input pair)
VS = 2.7 V, (V–) – 0.1 V < VCM <
(V+) – 2 V (Main input pair) (1)
(V+) + 0.2
109
130
84
100
75
95
TA = –40°C to 125°C
V
dB
VS = 2.7 V to 16 V, (V+) – 1 V <
VCM < (V+) + 0.1 V (Aux input pair)
85
INPUT CAPACITANCE
ZID
Differential
ZICM
Common-mode
100 || 3
MΩ || pF
6 || 1
TΩ || pF
OPEN-LOOP GAIN
VS = 16 V, VCM = V–
(V–) + 0.1 V < VO < (V+) – 0.1 V
AOL
(1)
12
Open-loop voltage gain
120
TA = –40°C to 125°C
142
104
VS = 4 V, VCM = V–
(V–) + 0.1 V < VO < (V+) – 0.1 V
TA = –40°C to 125°C
VS = 2.7 V, VCM = V–
(V–) + 0.1 V < VO < (V+) – 0.1 V (1)
TA = –40°C to 125°C
145
130
125
101
dB
120
118
Specified by characterization only.
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Electrical Characteristics (continued)
For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT
= VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
tS
Settling time
4.5
MHz
VS = 16 V, G = +1, CL = 20 pF
20
V/μs
To 0.01%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF
2.5
To 0.01%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF
1.5
To 0.1%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF
2
To 0.1%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF
THD+N
Phase margin
G = +1, RL = 10 kΩ
Overload recovery time
VIN × gain > VS
Total harmonic distortion
+ noise
VS = 16 V, VO = 3 VRMS, G = 1, f = 1 kHz
μs
1
60
°
600
ns
0.0001%
VS = 16 V, RL = no load (1)
Voltage output swing
from rail
Positive and negative rail headroom
5
10
VS = 16 V, RL = 10 kΩ
50
55
VS = 16 V, RL = 2 kΩ
200
250
1
6
VS = 2.7 V, RL = 10 kΩ
5
12
VS = 2.7 V, RL = 2 kΩ
25
40
VS = 2.7 V, RL = no load (1)
mV
ISC
Short-circuit current
±75
mA
CLOAD
Capacitive load drive
1000
pF
ZO
Open-loop output
impedance
400
Ω
f = 1 MHz, IO = 0 A
ADVANCE INFORMATION
OUTPUT
POWER SUPPLY
IQ
Quiescent current per
amplifier
IO = 0 A
560
TA = –40°C to 125°C
685
735
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7 Detailed Description
7.1 Overview
The TLV915x family (TLV9151, TLV9152, and TLV9154) is a family of 16-V general purpose operational
amplifiers.
These devices offer excellent DC precision and AC performance, including rail-to-rail input/output, low offset
(±125 µV, typ), low offset drift (±0.3 µV/°C, typ), and 4.5-MHz bandwidth.
Wide differential and common-mode input-voltage range, high output current (±80 mA), high slew rate (21 V/µs),
low power operation (560 µA, typ) and shutdown functionality make the TLV915x a robust, high-speed, highperformance operational amplifier for industrial applications.
7.2 Functional Block Diagram
V+
Reference
Current
ADVANCE INFORMATION
V
IN+
V
INÛ
V
BIAS1
Class AB
Control
Circuitry
V
O
V
BIAS2
VÛ
(Ground)
14
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7.3 Feature Description
7.3.1 Input Protection Circuitry
The TLV915x uses a unique input architecture to eliminate the requirement for input protection diodes but still
provides robust input protection under transient conditions. shows conventional input diode protection schemes
that are activated by fast transient step responses and introduce signal distortion and settling time delays
because of alternate current paths, as shown in Figure 1. For low-gain circuits, these fast-ramping input signals
forward-bias back-to-back diodes, causing an increase in input current and resulting in extended settling time.
Vn = 10 V
RFILT
10 V
1
Ron_mux
Sn
1
D
10 V
CFILT
2
~±9.3 V
CS
CD
Vn+1 = ±10 V RFILT
±10 V
Ron_mux
Sn+1
VIN±
2
~0.7 V
CS
VOUT
Idiode_transient
±10 V
Input Low-Pass Filter
VIN+
Buffer Amplifier
Simplified Mux Model
Figure 1. Back-to-Back Diodes Create Settling Issues
The TLV915x family of operational amplifiers provides a true high-impedance differential input capability for highvoltage applications using a patented input protection architecture that does not introduce additional signal
distortion or delayed settling time, making the device an optimal op amp for multichannel, high-switched, input
applications. The TLV9151 tolerates a maximum differential swing (voltage between inverting and non-inverting
pins of the op amp) of up to 40 V, making the device suitable for use as a comparator or in applications with fastramping input signals such as data-acquisition systems; see the TI TechNote MUX-Friendly Precision
Operational Amplifiers for more information.
7.3.2 EMI Rejection
The TLV915x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the TLV915x benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. The EMI
Rejection Ratio of Operational Amplifiers application report contains detailed information on the topic of EMIRR
performance as it relates to op amps and is available for download from www.ti.com.
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Feature Description (continued)
7.3.3 Thermal Protection
The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This
phenomenon is called self heating. The absolute maximum junction temperature of the TLV915x is 150°C.
Exceeding this temperature causes damage to the device. The TLV915x has a thermal protection feature that
reduces damage from self heating. The protection works by monitoring the temperature of the device and turning
off the op amp output drive for temperatures above 170°C. shows an application example for the TLV9151 that
has significant self heating because of its power dissipation (0.81 W). Thermal calculations indicate that for an
ambient temperature of 65°C, the device junction temperature must reach 177°C. The actual device, however,
turns off the output drive to recover towards a safe junction temperature. shows how the circuit behaves during
thermal protection. During normal operation, the device acts as a buffer so the output is 3 V. When self heating
causes the device junction temperature to increase above the internal limit, the thermal protection forces the
output to a high-impedance state and the output is pulled to ground through resistor RL. If the condition that
caused excessive power dissipation is not removed, the amplifier will oscillate between a shutdown and enabled
state until the output fault is corrected.
ADVANCE INFORMATION
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Feature Description (continued)
7.3.4 Common-Mode Voltage Range
The TLV915x is a 16-V, rail-to-rail input operational amplifier with an input common-mode range that extends 200
mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel and Pchannel differential input pairs, as shown in Figure 2. The N-channel pair is active for input voltages close to the
positive rail, typically (V+) – 1 V to 100 mV above the positive supply. The P-channel pair is active for inputs from
100 mV below the negative supply to approximately (V+) – 2 V. There is a small transition region, typically (V+) –
2 V to (V+) – 1 V in which both input pairs are on. This transition region can vary modestly with process variation,
and within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD performance may be degraded
compared to operation outside this region.
For more information on common-mode voltage range and PMOS/NMOS pair interaction, see Op Amps With
Complementary-Pair Input Stages application note.
V+
PMOS
PMOS
IN+
NMOS
NMOS
V-
Figure 2. Rail-to-Rail Input Stage
7.3.5 Phase Reversal Protection
The TLV915x family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond its linear common-mode range. This condition is most often encountered in non-inverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The TLV915x is a rail-to-rail input op amp; therefore, the common-mode range can
extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into
the appropriate rail. For more information on phase reversal, see Op Amps With Complementary-Pair Input
Stages application note.
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Feature Description (continued)
7.3.6 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the
output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. shows an illustration of the ESD circuits contained in the TLV915x (indicated by the dashed line area).
The ESD protection circuitry involves several current-steering diodes connected from the input and output pins
and routed back to the internal power-supply lines, where the diodes meet at an absorption device or the powersupply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain inactive during
normal circuit operation.
ADVANCE INFORMATION
An ESD event is very short in duration and very high voltage (for example; 1 kV, 100 ns), whereas an EOS event
is long duration and lower voltage (for example; 50 V, 100 ms). The ESD diodes are designed for out-of-circuit
ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).
During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit (labeled
ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by
turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting
resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.
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Feature Description (continued)
7.3.7 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a
linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the
rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
The overload recovery time for the TLV915x is approximately 500 ns.
7.3.8 Typical Specifications and Distributions
0.00002% 0.00312% 0.13185%
1
-61
1
-51
1
-41
2.145% 13.59% 34.13% 34.13% 13.59% 2.145%
1
-31
1
-21
1
-1
1
1
+1
1
ADVANCE INFORMATION
Designers often have questions about a typical specification of an amplifier in order to design a more robust
circuit. Due to natural variation in process technology and manufacturing procedures, every specification of an
amplifier will exhibit some amount of deviation from the ideal value, like an amplifier's input offset voltage. These
deviations often follow Gaussian ("bell curve"), or normal distributions, and circuit designers can leverage this
information to guardband their system, even when there is not a minimum or maximum specification in the
Electrical Characteristics table.
0.13185% 0.00312% 0.00002%
1
1
1
+21 +31 +41 +51 +61
Figure 3. Ideal Gaussian Distribution
Figure 3 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ, or sigma, is
the standard deviation of a system. For a specification that exhibits this kind of distribution, approximately twothirds (68.26%) of all units can be expected to have a value within one standard deviation, or one sigma, of the
mean (from µ – σ to µ + σ).
Depending on the specification, values listed in the typical column of the Electrical Characteristics table are
represented in different ways. As a general rule of thumb, if a specification naturally has a nonzero mean (for
example, like gain bandwidth), then the typical value is equal to the mean (µ). However, if a specification
naturally has a mean near zero (like input offset voltage), then the typical value is equal to the mean plus one
standard deviation (µ + σ) in order to most accurately represent the typical value.
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Feature Description (continued)
You can use this chart to calculate approximate probability of a specification in a unit; for example, for TLV915x,
the typical input voltage offset is 125 µV, so 68.2% of all TLV915x devices are expected to have an offset from
–125 µV to 125 µV. At 4 σ (±500 µV), 99.9937% of the distribution has an offset voltage less than ±500 µV,
which means 0.0063% of the population is outside of these limits, which corresponds to about 1 in 15,873 units.
Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits
will be removed from production material. For example, the TLV915x family has a maximum offset voltage of 675
µV at 25°C, and even though this corresponds to about 5 σ (≈1 in 1.7 million units), which is extremely unlikely,
TI assures that any unit with larger offset than 675 µV will be removed from production material.
For specifications with no value in the minimum or maximum column, consider selecting a sigma value of
sufficient guardband for your application, and design worst-case conditions using this value. For example, the 6 σ
value corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and could be an option
as a wide guardband to design a system around. In this case, the TLV915x family does not have a maximum or
minimum for offset voltage drift, but based on the typical value of 0.3 µV/°C in the Electrical Characteristics table,
it can be calculated that the 6 σ value for offset voltage drift is about 1.8 µV/°C. When designing for worst-case
system conditions, this value can be used to estimate the worst possible offset across temperature without
having an actual minimum or maximum value.
ADVANCE INFORMATION
However, process variation and adjustments over time can shift typical means and standard deviations, and
unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a
device. This information should be used only to estimate the performance of a device.
7.3.9 Packages With an Exposed Thermal Pad
The TLV915x family is available in packages such as the WSON-8 (DSG) and WQFN-16 (RTE) which feature an
exposed thermal pad. Inside the package, the die is attached to this thermal pad using an electrically conductive
compound. For this reason, when using a package with an exposed thermal pad, the thermal pad must either be
connected to V– or left floating. Attaching the thermal pad to a potential other than V– is not allowed, and
performance of the device is not assured when doing so.
7.3.10 Shutdown
The TLV915xS devices feature one or more shutdown pins (SHDN) that disable the op amp, placing it into a lowpower standby mode. In this mode, the op amp typically consumes about 20 µA. The SHDN pins are active high,
meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic high.
The SHDN pins are referenced to the negative supply rail of the op amp. The threshold of the shutdown feature
lies around 800 mV (typical) and does not change with respect to the supply voltage. Hysteresis has been
included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown
behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage
between V– and V– + 0.4 V. A valid logic high is defined as a voltage between V– + 1.2 V and V– + 20 V. The
shutdown pin circuitry includes a pull-down resistor, which will inherently pull the voltage of the pin to the
negative supply rail if not driven. Thus, to enable the amplifier, the SHDN pins should either be left floating or
driven to a valid logic low. To disable the amplifier, the SHDN pins must be driven to a valid logic high. The
maximum voltage allowed at the SHDN pins is V– + 20 V. Exceeding this voltage level will damage the device.
The SHDN pins are high-impedance CMOS inputs. Channels of single and dual op amp packages are
independently controlled, and channels of quad op amp packages are controlled in pairs. For battery-operated
applications, this feature may be used to greatly reduce the average current and extend battery life. The typical
enable time out of shutdown is 30 µs; disable time is 3 µs. When disabled, the output assumes a highimpedance state. This architecture allows the TLV915xS family to operate as a gated amplifier, multiplexer, or
programmable-gain amplifier. Shutdown time (tOFF) depends on loading conditions and increases as load
resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load to
midsupply (VS / 2) is required. If using the TLV915xS without a load, the resulting turnoff time significantly
increases.
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7.4 Device Functional Modes
The TLV915x has a single functional mode and is operational when the power-supply voltage is greater than 2.7
V (±1.35 V). The maximum power supply voltage for the TLV915x is 16 V (±8 V).
ADVANCE INFORMATION
The TLV915xS devices feature a shutdown pin, which can be used to place the op amp into a low-power mode.
See Shutdown section for more information.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV915x family offers excellent DC precision and DC performance. These devices operate up to 40-V
supply rails and offer true rail-to-rail input/output, low offset voltage and offset voltage drift, as well as 5-MHz
bandwidth and high output drive. These features make the TLV915x a robust, high-performance operational
amplifier for high-voltage industrial applications.
8.2 Typical Applications
8.2.1 Low-Side Current Measurement
ADVANCE INFORMATION
Figure 4 shows the TLV9151 configured in a low-side current sensing application. For a full analysis of the circuit
shown in Figure 4 including theory, calculations, simulations, and measured data, see TI Precision Design
TIPD129, 0-A to 1-A Single-Supply Low-Side Current-Sensing Solution.
VCC
5V
LOAD
+
OPA991
VOUT
–
RSHUNT
100 m
ILOAD
LM7705
RF
360 k
RG
7.5 k
Figure 4. TLV9151 in a Low-Side, Current-Sensing Application
8.2.1.1 Design Requirements
The design requirements for this design are:
• Load current: 0 A to 1 A
• Output voltage: 4.9 V
• Maximum shunt voltage: 100 mV
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Typical Applications (continued)
8.2.1.2 Detailed Design Procedure
The transfer function of the circuit in Figure 4 is given in Equation 1.
VOUT ILOAD u RSHUNT u Gain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from
0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using Equation 2.
VSHUNT _ MAX 100mV
RSHUNT
100m:
ILOAD _ MAX
1A
(2)
Using Equation 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the TLV9151 to produce an output voltage of 0 V to 4.9 V. The gain needed by the TLV9151 to
produce the necessary output voltage is calculated using Equation 3.
VOUT _ MAX
VIN _ MAX
VOUT _ MIN
VIN _ MIN
(3)
Using Equation 3, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. Equation 4
is used to size the resistors, RF and RG, to set the gain of the TLV9151 to 49 V/V.
RF
Gain 1
RG
(4)
Choosing RF as 360 kΩ, RG is calculated to be 7.5 kΩ. RF and RG were chosen as 360 kΩ and 7.5 kΩ because
they are standard value resistors that create a 49:1 ratio. Other resistors that create a 49:1 ratio can also be
used. Figure 5 shows the measured transfer function of the circuit shown in Figure 4.
8.2.1.3 Application Curves
5
Output (V)
4
3
2
1
0
0
0.1
0.2
0.3
0.4
0.5 0.6
ILOAD (A)
0.7
0.8
0.9
1
Figure 5. Low-Side, Current-Sense, Transfer Function
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9 Power Supply Recommendations
The TLV915x is specified for operation from 2.7 V to 40 V (±1.35 V to ±40 V); many specifications apply from
–40°C to 125°C.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
section.
10 Layout
10.1 Layout Guidelines
ADVANCE INFORMATION
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds paying attention to the flow of the ground current.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much
better as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 7, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is
recommended to remove moisture introduced into the device packaging during the cleaning process. A
low temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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10.2 Layout Example
+
VIN
VOUT
RG
RF
Figure 6. Schematic Representation
Place components close
to device and to each
other to reduce parasitic
errors
VS+
RF
NC
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
±IN
V+
VIN
+IN
OUTPUT
V±
NC
GND
VS±
ADVANCE INFORMATION
Run the input traces
as far away from
the supply lines
as possible
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Figure 7. Operational Amplifier Board Layout for Noninverting Configuration
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
ADVANCE INFORMATION
11.1.1.2 TI Precision Designs
The
TLV915x
is
featured
in
several
TI
Precision
Designs,
available
online
at
http://www.ti.com/ww/en/analog/precision-designs/. TI Precision Designs are analog solutions created by TI’s
precision analog applications experts and offer the theory of operation, component selection, simulation,
complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits.
11.2 Documentation Support
11.2.1 Related Documentation
Texas Instruments, Analog Engineer's Circuit Cookbook: Amplifiers.
Texas Instruments, AN31 amplifier circuit collection.
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
26
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Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TLV9152
TLV9152
www.ti.com
SBOS986 – OCTOBER 2019
11.7 Glossary
ADVANCE INFORMATION
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TLV9152
27
TLV9152
SBOS986 – OCTOBER 2019
www.ti.com
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
ADVANCE INFORMATION
28
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Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TLV9152
PACKAGE OPTION ADDENDUM
www.ti.com
28-Nov-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
PTLV9152IDR
ACTIVE
SOIC
D
8
2500
TBD
Call TI
Call TI
-40 to 125
PTLV9152IPWR
ACTIVE
TSSOP
PW
8
2000
TBD
Call TI
Call TI
-40 to 125
TLV9152IDR
PREVIEW
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T9152D
TLV9152IPWR
PREVIEW
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T9152P
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Nov-2019
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
SCALE 2.800
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
1
3.1
2.9
NOTE 3
2X
1.95
4
5
B
4.5
4.3
NOTE 4
SEE DETAIL A
8X
0.30
0.19
0.1
C A
1.2 MAX
B
(0.15) TYP
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
1
8
(R0.05)
TYP
SYMM
6X (0.65)
5
4
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
(R0.05) TYP
1
8
SYMM
6X (0.65)
5
4
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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