Texas Instruments | TLV9051 / TLV9052 / TLV9054 5-MHz, 15-V/µs High Slew-Rate, RRIO Op Amp (Rev. H) | Datasheet | Texas Instruments TLV9051 / TLV9052 / TLV9054 5-MHz, 15-V/µs High Slew-Rate, RRIO Op Amp (Rev. H) Datasheet

Texas Instruments TLV9051 / TLV9052 / TLV9054 5-MHz, 15-V/µs High Slew-Rate, RRIO Op Amp (Rev. H) Datasheet
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TLV9051, TLV9052, TLV9054
SBOS942H – AUGUST 2018 – REVISED OCTOBER 2019
TLV9051 / TLV9052 / TLV9054 5-MHz, 15-V/µs High Slew-Rate, RRIO Op Amp
1 Features
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•
•
•
•
•
•
•
•
•
1
•
•
High slew rate: 15 V/µs
Low quiescent current: 330 µA
Rail-to-rail input and output
Low input offset voltage: ±0.33 mV
Unity-gain bandwidth: 5 MHz
Low broadband noise: 15 nV/√Hz
Low input bias current: 2 pA
Unity-gain stable
Internal RFI and EMI filter
Scalable family of CMOS op amps for low-cost
applications
Operational at supply voltages as low as 1.8 V
Extended temperature range: –40°C to 125°C
The TLV905xS devices include a shutdown mode
that allow the amplifiers to be switched off into a
standby mode with typical current consumption less
than 1 µA.
The TLV905x family is easy to use due to the devices
being unity-gain stable, including a RFI and EMI filter,
and being free from phase reversal in an overdrive
condition.
Device Information(1)
PART NUMBER
TLV9051
TLV9051S
2 Applications
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•
•
•
•
•
•
HVAC: heating, ventilating, and air conditioning
Photodiode amplifier
Current shunt monitoring for DC motor control
White goods (refrigerators, washing machines,
and so forth)
Sensor signal conditioning
Active filters
Low-side current sensing
TLV9052
TLV9052S
TLV9054
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
1.60 mm × 2.90 mm
SC70 (5)
1.25 mm × 2.00 mm
SOT553 (5)(2)
1.65 mm × 1.20 mm
X2SON (5)
0.80 mm × 0.80 mm
SOT-23 (6)
1.60 mm × 2.90 mm
SOIC (8)
3.91 mm × 4.90 mm
TSSOP (8)
3.00 mm × 4.40 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOT-23 (8)
1.60 mm × 2.90 mm
WSON (8)
2.00 mm × 2.00 mm
VSSOP (10)
3.00 mm × 3.00 mm
X2QFN (10)
1.50 mm × 2.00 mm
SOIC (14)
8.65 mm × 3.91 mm
TSSOP (14)
4.40 mm × 5.00 mm
X2QFN (14)
2.00 mm × 2.00 mm
WQFN (16)
3.00 mm × 3.00 mm
WQFN (16)
3.00 mm × 3.00 mm
3 Description
TLV9054S
The TLV9051, TLV9052, and TLV9054 devices are
single, dual, and quad operational amplifiers,
respectively. The devices are optimized for low
voltage operation from 1.8 V to 5.5 V. The inputs and
outputs can operate from rail to rail at a very high
slew rate. These devices are perfect for costconstrained applications where low-voltage operation,
high slew rate, and low quiescent current is needed.
The capacitive-load drive of the TLV905x family is
150 pF, and the resistive open-loop output
impedance makes stabilization easier with much
higher capacitive loads.
Single-Pole, Low-Pass Filter
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Package is for preview only.
RG
RF
Slew Rate vs Load Capacitance
17
16.5
VOUT
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
(
1
2pR1C1
16
Slew Rate (V/Ps)
R1
VIN
15.5
15
14.5
14
13.5
13
50
100
150
200
250
Capacitive Load (pF)
300
350
D019
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV9051, TLV9052, TLV9054
SBOS942H – AUGUST 2018 – REVISED OCTOBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features .................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Device Comparison Table..................................... 4
Pin Configuration and Functions ......................... 5
Specifications....................................................... 12
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Absolute Maximum Ratings .................................... 12
ESD Ratings............................................................ 12
Recommended Operating Conditions..................... 12
Thermal Information for Single Channel ................. 12
Thermal Information for Dual Channel.................... 13
Thermal Information for Quad Channel .................. 13
Electrical Characteristics: VS (Total Supply Voltage) =
(V+) – (V–) = 1.8 V to 5.5 V ..................................... 14
7.8 Typical Characteristics ............................................ 16
8
Detailed Description ............................................ 23
8.1 Overview ................................................................. 23
8.2 Functional Block Diagram ....................................... 23
8.3 Feature Description................................................. 24
8.4 Device Functional Modes........................................ 27
9
Application and Implementation ........................ 28
9.1 Application Information............................................ 28
9.2 Typical Low-Side Current Sense Application.......... 28
10 Power Supply Recommendations ..................... 30
11 Layout................................................................... 31
11.1 Layout Guidelines ................................................. 31
11.2 Layout Example .................................................... 32
12 Device and Documentation Support ................. 33
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
33
33
33
33
33
33
33
13 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (September 2019) to Revision H
Page
•
Added new human-body model and charged-device model ratings for TLV9051 X2SON package to the ESD Ratings ... 12
•
Added Packages With an Exposed Thermal Pad section to Feature Description section................................................... 25
Changes from Revision F (June 2019) to Revision G
Page
•
Deleted preview tags for all TLV9051 packages .................................................................................................................... 1
•
Deleted preview tags for the TLV9052 SOT-23 (8) - DDF package ...................................................................................... 1
•
Added link to Shutdown Function section in all of the SHDN pin function rows .................................................................... 6
•
Added EMI Rejection section to Feature Description section .............................................................................................. 24
•
Added clarification to the Shutdown Function section.......................................................................................................... 26
Changes from Revision E (May 2019) to Revision F
Page
•
Deleted package preview notation for TLV9052S devices in Device Information.................................................................. 1
•
Deleted package preview notation for TLV9052S devices under Device Comparison Table................................................ 4
•
Deleted preview notation for TLV9052S devices in Device Comparison Table .................................................................... 4
•
Deleted package preview notation for TLV9052S in Pin Configuration and Functions section ............................................. 8
•
Deleted package preview notation for TLV9052S under Thermal Information for Dual Channel ........................................ 13
Changes from Revision D (April 2019) to Revision E
•
2
Page
Added DDF (SOT-23) information to Thermal Information for Dual Channel table ............................................................. 13
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Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TLV9051 TLV9052 TLV9054
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SBOS942H – AUGUST 2018 – REVISED OCTOBER 2019
Changes from Revision C (April 2019) to Revision D
Page
•
Deleted preview notations for TLV9054/S devices in Device Information ............................................................................. 1
•
Deleted preview notations for TLV9054 devices in Device Comparison Table...................................................................... 4
•
Deleted preview notations for TLV9054S device in Device Comparison Table ..................................................................... 4
•
Deleted preview notations for TLV9054 packages in Pin Configurations and Functions section .......................................... 9
•
Deleted preview notation for TLV9054S RTE package in Pin Configurations and Functions section ................................. 11
•
Deleted preview notation for TLV9054/S packages in Thermal Information for Quad Channel .......................................... 13
Changes from Revision B (March 2019) to Revision C
•
Page
Added TLV9051 thermal information for DPW, DBV, and DCK packages .......................................................................... 12
Changes from Revision A (December 2018) to Revision B
Page
•
Added Shutdown device notes in the Description section ..................................................................................................... 1
•
Added SOT-23 (8) package to Device Information ................................................................................................................ 1
•
Added Shutdown devices to Device Information.................................................................................................................... 1
•
Added X2QFN (RUC) package to TLV9054 Device Information............................................................................................ 1
•
Added DDF package information to Device Comparison Table ............................................................................................ 4
•
Added Shutdown devices (TLV9051S/TLV9052S/TLV9054S) and packages (DGS/RUG/RTE) to Device Comparison
Table ...................................................................................................................................................................................... 4
•
Added TLV9051S pinout information to Pin Configurations and Functions section............................................................... 6
•
Added DDF (SOT-23) package .............................................................................................................................................. 7
•
Added TLV9052S pinout information to Pin Configurations and Functions section............................................................... 8
•
Added TLV9054S and TLV9054 X2QFN (RUC) pinout information to Pin Configurations and Functions section................ 9
•
Added TLV9051 and TLV9051S thermal information to Thermal Information for Single Channel ...................................... 12
•
Added TLV9052S thermal info to Thermal Information for Dual Channel ........................................................................... 13
•
Added DDF (SOT-23) package to Thermal Information for Dual Channel........................................................................... 13
•
Added TLV9054 and TLV9054S thermal information to Thermal Information for Quad Channel........................................ 13
•
Added Shutdown Function information in Feature Description section................................................................................ 26
•
Added "S" suffix to Related Links to reflect the addition of Shutdown devices.................................................................... 33
Changes from Original (August 2018) to Revision A
•
Page
Changed the device status from Advance Information to Production Data............................................................................ 1
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TLV9051 TLV9052 TLV9054
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SBOS942H – AUGUST 2018 – REVISED OCTOBER 2019
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5 Device Comparison Table
PACKAGE LEADS
DEVICE
NO. OF
CH.
TLV9051
SC70
DCK
SOT-23
DBV
SOT553(1)
DRL
X2SON
DPW
SOIC
D
WSON
DSG
VSSOP
DGK
TSSOP
PW
SOT-23
DDF
VSSOP
DGS
X2QFN
RUG
X2QFN
RUC
WQFN
RTE
5
5
5
5
—
—
—
—
—
—
—
—
—
TLV9051S
—
6
—
—
—
—
—
—
—
—
—
—
—
TLV9052
—
—
—
—
8
8
8
8
8
—
—
—
—
TLV9052S
—
—
—
—
—
—
—
—
—
10
10
—
—
TLV9054
—
—
—
—
14
—
—
14
—
—
—
14
16
—
—
—
—
—
—
—
—
—
—
—
—
16
1
2
4
TLV9054S
(1) Package is for preview only.
4
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Product Folder Links: TLV9051 TLV9052 TLV9054
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SBOS942H – AUGUST 2018 – REVISED OCTOBER 2019
6 Pin Configuration and Functions
TLV9051 DBV, DRL Packages
5-Pin SOT-23, SOT-553
Top View
OUT
1
V±
2
IN+
3
TLV9051 DPW Package
5-Pin X2SON
Top View
5
V+
4
IN±
OUT
1
5
V+
4
IN+
3
V±
IN±
Not to scale
2
Not to scale
TLV9051 DCK Package
5-Pin SC70
Top View
IN+
1
V±
2
IN±
3
5
V+
4
OUT
Not to scale
Pin Functions: TLV9051
PIN
I/O
DESCRIPTION
SOT-23,
SOT-553
SC-70
X2SON
IN–
4
3
2
I
Inverting input
IN+
3
1
4
I
Noninverting input
OUT
1
4
1
O
Output
V–
2
2
3
—
Negative (low) supply or ground (for single-supply operation)
V+
5
5
5
—
Positive (high) supply
NAME
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Product Folder Links: TLV9051 TLV9052 TLV9054
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TLV9051S DBV Package
6-Pin SOT-23
Top View
OUT
1
6
V+
V±
2
5
SHDN
+IN
3
4
±IN
Not to scale
Pin Functions: TLV9051S
PIN
NAME
NO.
I/O
DESCRIPTION
–IN
4
I
Inverting input
+IN
3
I
Noninverting input
OUT
1
O
Output
SHDN
5
I
Shutdown: low = amp disabled, high = amp enabled. See Shutdown Function section for
more information.
V–
2
—
Negative (lowest) supply or ground (for single-supply operation).
V+
6
—
Positive (highest) supply
6
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SBOS942H – AUGUST 2018 – REVISED OCTOBER 2019
TLV9052 D, DGK, PW, DDF Packages
8-Pin SOIC, VSSOP, TSSOP, SOT-23
Top View
TLV9052 DSG Package
8-Pin WSON With Exposed Thermal Pad
Top View
OUT1
1
8
V+
IN1±
2
7
OUT2
IN1+
3
6
IN2±
V±
4
5
IN2+
OUT1
1
IN1±
2
IN1+
3
V±
4
Thermal
Pad
8
V+
7
OUT2
6
IN2±
5
IN2+
Not to scale
Not to scale
Connect exposed thermal pad to V–. See
Packages With an Exposed Thermal Pad
section for more information.
Pin Functions: TLV9052
PIN
NAME
NO.
I/O
DESCRIPTION
IN1–
2
I
Inverting input, channel 1
IN1+
3
I
Noninverting input, channel 1
IN2–
6
I
Inverting input, channel 2
IN2+
5
I
Noninverting input, channel 2
OUT1
1
O
Output, channel 1
OUT2
7
O
Output, channel 2
V–
4
—
Negative (low) supply or ground (for single-supply operation)
V+
8
—
Positive (high) supply
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TLV9051 TLV9052 TLV9054
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TLV9052S DGS Package
10-Pin VSSOP
Top View
TLV9052S RUG Package
10-Pin X2QFN
Top View
10
V+
IN1±
2
9
OUT2
IN1+
3
8
IN2±
V±
4
7
IN2+
SHDN1
5
6
SHDN2
IN1+
1
V±
1
9
IN1±
SHDN1
2
8
OUT1
SHDN2
3
7
V+
IN2+
4
6
OUT2
10
OUT1
5
Not to scale
IN2±
Not to scale
Pin Functions: TLV9052S
PIN
NAME
I/O
DESCRIPTION
VSSOP
X2QFN
IN1–
2
9
I
Inverting input, channel 1
IN1+
3
10
I
Noninverting input, channel 1
IN2–
8
5
I
Inverting input, channel 2
IN2+
7
4
I
Noninverting input, channel 2
OUT1
1
8
O
Output, channel 1
OUT2
9
6
O
Output, channel 2
SHDN1
5
2
I
Shutdown: low = amp disabled, high = amp enabled, channel 1. See Shutdown
Function section for more information.
SHDN2
6
3
I
Shutdown: low = amp disabled, high = amp enabled, channel 2. See Shutdown
Function section for more information.
V–
4
1
—
Negative (low) supply or ground (for single-supply operation)
V+
10
7
—
Positive (high) supply
8
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SBOS942H – AUGUST 2018 – REVISED OCTOBER 2019
TLV9054 D, PW Packages
14-Pin SOIC, TSSOP
Top View
V±
IN2+
5
10
IN3+
IN2±
6
9
IN3±
OUT2
7
8
OUT3
IN1+
1
V+
2
IN2+
3
IN2±
4
11
IN4+
3
10
V±
IN2+
4
9
IN3+
IN2±
5
8
IN3±
OUT2
11
V±
Pad
10
IN3+
9
IN3±
Not to scale
7
V+
OUT3
2
13
IN4±
14
12
6
IN1+
IN4+
Connect exposed thermal pad to V–. See
Packages With an Exposed Thermal Pad
section for more information.
OUT4
OUT1
TLV9054 RUC Package
14-Pin X2QFN
Top View
1
12
Thermal
Not to scale
IN1±
IN4±
11
13
4
8
V+
OUT3
IN4+
OUT4
12
14
3
7
IN1+
NC
IN4±
OUT1
13
15
2
6
IN1±
NC
OUT4
IN1±
14
5
1
OUT2
OUT1
16
TLV9054 RTE Package
16-Pin WQFN With Exposed Thermal Pad
Top View
Not to scale
Pin Functions: TLV9054
PIN
I/O
DESCRIPTION
SOIC,
TSSOP
WQFN
X2QFN
IN1–
2
16
1
I
Inverting input, channel 1
IN1+
3
1
2
I
Noninverting input, channel 1
IN2–
6
4
5
I
Inverting input, channel 2
IN2+
5
3
4
I
Noninverting input, channel 2
NAME
IN3–
9
9
8
I
Inverting input, channel 3
IN3+
10
10
9
I
Noninverting input, channel 3
IN4–
13
13
12
I
Inverting input, channel 4
IN4+
12
12
11
I
Noninverting input, channel 4
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Pin Functions: TLV9054 (continued)
PIN
I/O
DESCRIPTION
SOIC,
TSSOP
WQFN
NC
—
6, 7
—
—
No internal connection
OUT1
1
15
14
O
Output, channel 1
OUT2
7
5
6
O
Output, channel 2
OUT3
8
8
7
O
Output, channel 3
OUT4
14
14
13
O
Output, channel 4
V–
11
11
10
—
Negative (low) supply or ground (for single-supply operation)
V+
4
2
3
—
Positive (high) supply
NAME
10
Submit Documentation Feedback
X2QFN
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IN1+
1
V+
2
IN1±
OUT1
OUT4
IN4±
16
15
14
13
TLV9054S RTE Package
16-Pin WQFN With Exposed Thermal Pad
Top View
12
IN4+
11
V±
10
IN3+
9
IN3±
Thermal
6
7
8
SHDN34
OUT3
4
SHDN12
IN2±
Pad
5
3
OUT2
IN2+
Not to scale
Connect exposed thermal pad to V–. See Packages With an Exposed Thermal Pad section for more information.
Pin Functions: TLV9054S
PIN
NAME
NO.
I/O
DESCRIPTION
IN1+
1
I
Noninverting input, channel 1
IN1–
16
I
Inverting input, channel 1
IN2+
3
I
Noninverting input, channel 2
IN2–
4
I
Inverting input, channel 2
IN3+
10
I
Noninverting input, channel 3
IN3–
9
I
Inverting input, channel 3
IN4+
12
I
Noninverting input, channel 4
IN4–
13
I
Inverting input, channel 4
SHDN12
6
I
Shutdown: low = amp disabled, high = amp enabled, channel 1 and 2. See Shutdown
Function section for more information.
SHDN34
7
I
Shutdown: low = amp disabled, high = amp enabled, channel 3 and 4. See Shutdown
Function section for more information.
OUT1
15
O
Output, channel 1
OUT2
5
O
Output, channel 2
OUT3
8
O
Output, channel 3
OUT4
14
O
Output, channel 4
V–
11
—
Negative (low) supply or ground (for single-supply operation)
V+
2
—
Positive (high) supply
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7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature (unless otherwise noted) (1)
MIN
Supply voltage, VS = (V+) – (V–)
Signal input pins
Common-mode
Voltage (2)
(V–) – 0.5
Differential
Current (2)
–10
Output short-circuit (3)
–40
Junction temperature, TJ
Storage temperature, Tstg
(2)
(3)
UNIT
6
V
(V+) + 0.5
V
VS + 0.2
V
10
mA
150
°C
150
°C
150
°C
Continuous
Operating ambient temperature, TA
(1)
MAX
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Current limit input signals that can swing more than 0.5 V beyond the supply
rails to 10 mA or less.
Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
VALUE
UNIT
TLV9051 X2SON PACKAGE
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
V
ALL OTHER PACKAGES
V(ESD)
(1)
(2)
Electrostatic discharge
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
VS
Supply voltage, VS = (V+) – (V–)
VIN
Input pin voltage
Specified temperature
MIN
MAX
UNIT
1.8
5.5
V
(V–) – 0.1
(V+) + 0.1
V
–40
125
°C
7.4 Thermal Information for Single Channel
TLV9051, TLV9051S
THERMAL METRIC
(1)
DPW (X2SON)
DBV (SOT-23)
DCK
(SC70)
DRL
(SOT553) (2)
UNIT
5 PINS
5 PINS
6 PINS
5 PINS
5 PINS
RθJA
Junction-to-ambient thermal
resistance
470.0
228.1
210.8
231.2
TBD
°C/W
RθJC(top)
Junction-to-case(top) thermal
resistance
211.9
152.1
152.1
144.4
TBD
°C/W
RθJB
Junction-to-board thermal resistance
334.8
97.7
92.3
78.6
TBD
°C/W
ψJT
Junction-to-top characterization
parameter
29.8
74.1
76.2
51.3
TBD
°C/W
(1)
(2)
12
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
This package option is for preview only.
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Thermal Information for Single Channel (continued)
TLV9051, TLV9051S
THERMAL METRIC
(1)
DPW (X2SON)
DBV (SOT-23)
DCK
(SC70)
DRL
(SOT553) (2)
UNIT
5 PINS
5 PINS
6 PINS
5 PINS
5 PINS
ψJB
Junction-to-board characterization
parameter
333.2
97.3
92.1
78.3
TBD
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal
resistance
N/A
N/A
N/A
N/A
TBD
°C/W
7.5 Thermal Information for Dual Channel
TLV9052, TLV9052S
THERMAL METRIC
(1)
D
(SOIC)
DGK
(VSSOP)
DSG
(WSON)
PW
(TSSOP)
DDF
(SOT-23)
DGS
(VSSOP)
RUG
(X2QFN)
8 PINS
8 PINS
8 PINS
8 PINS
8 PINS
10 PINS
10 PINS
UNIT
RθJA
Junction-to-ambient
thermal resistance
155.4
208.8
102.3
205.1
184.4
170.4
197.2
°C/W
RθJC(top)
Junction-to-case(top)
thermal resistance
95.5
93.3
120.0
93.7
112.8
84.9
93.3
°C/W
RθJB
Junction-to-board thermal
resistance
98.9
130.7
68.2
135.7
99.9
113.5
123.8
°C/W
ψJT
Junction-to-top
characterization
parameter
41.9
26.1
15.1
25.0
18.7
16.4
3.7
°C/W
ψJB
Junction-to-board
characterization
parameter
98.1
128.9
68.2
134.0
99.3
112.3
120.2
°C/W
RθJC(bot)
Junction-to-case(bottom)
thermal resistance
N/A
N/A
43.6
N/A
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Thermal Information for Quad Channel
TLV9054, TLV9054S
THERMAL METRIC (1)
D (SOIC)
PW (TSSOP)
14 PINS
14 PINS
14 PINS
RTE (WQFN)
16 PINS
RUC (X2SQFN)
14 PINS
UNIT
RθJA
Junction-to-ambient thermal
resistance
115.0
147.2
65.5
65.6
209.4
°C/W
RθJC(top)
Junction-to-case(top) thermal
resistance
71.1
67.2
70.6
70.6
68.8
°C/W
RθJB
Junction-to-board thermal resistance
71.0
91.6
40.5
40.5
153.3
°C/W
ψJT
Junction-to-top characterization
parameter
29.7
16.6
5.8
5.8
3.0
°C/W
ψJB
Junction-to-board characterization
parameter
70.6
90.7
40.5
40.5
152.8
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal
resistance
N/A
N/A
24.5
24.5
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2018–2019, Texas Instruments Incorporated
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7.7 Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 1.8 V to 5.5 V
For VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±0.33
±1.6
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
PSRR
VS = 5 V
±2
mV
VS = 5 V
TA = –40°C to 125°C
Drift
VS = 5 V
TA = –40°C to 125°C
Power-supply rejection
ratio
VS = 1.8 V – 5.5 V, VCM = (V–)
±13
Channel separation, DC
At DC
100
dB
±0.5
µV/°C
±80
µV/V
INPUT BIAS CURRENT
IB
Input bias current
±2
pA
IOS
Input offset current
±1
pA
6
µVPP
NOISE
En
Input voltage noise (peakto-peak)
en
Input voltage noise density
in
Input current noise density
VS = 5 V, f = 0.1 Hz to 10 Hz
VS = 5 V, f = 10 kHz
15
VS = 5 V, f = 1 kHz
20
f = 1 kHz
18
nV/√Hz
fA/√Hz
INPUT VOLTAGE RANGE
VCM
Common-mode voltage
range
CMRR
Common-mode rejection
ratio
VS = 1.8 V to 5.5 V
(V–) – 0.1
(V+) + 0.1
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V
TA = –40°C to 125°C
80
96
VS = 5.5 V, VCM = –0.1 V to 5.6 V
TA = –40°C to 125°C
62
79
VS = 1.8 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V
TA = –40°C to 125°C
88
VS = 1.8 V, VCM = –0.1 V to 1.9 V
TA = –40°C to 125°C
72
V
dB
INPUT CAPACITANCE
CID
Differential
2
pF
CIC
Common-mode
4
pF
OPEN-LOOP GAIN
VS = 1.8 V, (V–) + 0.04 V < VO < (V+) – 0.04 V, RL = 10 kΩ
AOL
Open-loop voltage gain
106
VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V, RL = 10 kΩ
104
128
VS = 1.8 V, (V–) + 0.06 V < VO < (V+) – 0.06 V, RL = 2 kΩ
108
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V, RL = 2 kΩ
130
dB
FREQUENCY RESPONSE
GBW
Gain bandwidth product
VS = 5.5 V, G = +1
5
φm
Phase margin
VS = 5.5 V, G = +1
60
°
SR
Slew rate
VS = 5.5 V, G = +1, CL= 130 pF
15
V/µs
tS
Settling time
tOR
Overload recovery time
VS = 5 V, VIN × gain > VS
THD + N
Total harmonic distortion +
noise (1)
VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = +1, f = 1 kHz
(1)
14
To 0.1%, VS = 5.5 V, 2-V step , G = +1, CL = 100 pF
0.75
To 0.01%, VS = 5.5 V, 2-V step, G = +1, CL = 100 pF
1
0.3
MHz
µs
µs
0.0006%
Third-order filter; bandwidth = 80 kHz at –3 dB.
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Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 1.8 V to 5.5 V (continued)
For VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
Positive rail headroom, VS = 5.5 V
Voltage output swing from
rail
VO
Negative rail headroom, VS = 5.5 V
RL = 2 kΩ
40
RL = 10 kΩ
16
RL = 2 kΩ
40
RL = 10 kΩ
mV
16
ISC
Short-circuit current
VS = 5 V
±50
mA
ZO
Open-loop output
impedance
VS = 5 V, f = 5 MHz
250
Ω
POWER SUPPLY
Quiescent current per
amplifier
IQ
VS = 5.5 V, IO = 0 mA
VS = 5.5 V, IO = 0 mA
330
TA = –40°C to 125°C
450
475
µA
SHUTDOWN
IQSD
Quiescent current per
amplifier
VS = 1.8 V to 5.5 V, all amplifiers disabled, SHDN = VS–
ZSHDN
Output impedance during
shutdown
VS = 1.8 V to 5.5 V, amplifier disabled
10 || 8
VIH
High voltage (amplifier
enabled)
VS = 1.8 V to 5.5 V, amplifier enabled
(V–) + 0.9
VIL
Low voltage (amplifier
disabled)
VS = 1.8 V to 5.5 V, amplifier disabled
Amplifier enable time (full
shutdown) (2) (3)
VS = 1.8 V to 5.5 V, full shutdown; G = 1, VOUT = 0.9 × VS / 2
35
Amplifier enable time
(partial shutdown) (2) (3)
VS = 1.8 V to 5.5 V, partial shutdown; G = 1, VOUT = 0.9 × VS / 2
10
Amplifier disable time (2)
VS = 1.8 V to 5.5 V, G = 1, VOUT = 0.1 × VS / 2
6
SHDN pin input bias
current (per pin)
VS = 1.8 V to 5.5 V, V+ ≥ SHDN ≥ (V+) – 0.8 V
40
VS = 1.8 V to 5.5 V, V– ≤ SHDN ≤ (V–) + 0.8 V
160
tON
tOFF
(2)
(3)
0.35
(V–) + 0.2
1
µA
GΩ ||
pF
(V–) + 1.1
(V–) + 0.7
V
V
µs
µs
nA
Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin
and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
Full shutdown refers to the dual TLV9052S having both channels 1 and 2 disabled (SHDN_1 = SHDN_2 = V–) and the quad TLV9054S
having all channels 1 to 4disabled (SHDN_12 = SHDN_34 = V––). For partial shutdown, only one SHDN pin is exercised; in this mode,
the internal biasing circuitry remains operational and the enable time is shorter.
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7.8 Typical Characteristics
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
21
40
18
30
Devices (%)
Devices (%)
15
12
9
6
20
10
3
0
0
-1200
-900
-600
-300
0
300
600
900
Offset Voltage (µV)
VS = 5.5 V
1200
0
DC15
Figure 1. Offset Voltage Production Distribution
Offset Voltage (µV)
Offset Voltage (µV)
2
DC16
350
300
200
100
0
-100
-200
-300
250
150
50
-50
-150
-400
-250
-500
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
-350
-3
110 125
Input Bias Current and Offset Current (pA)
400
300
200
100
0
-100
-200
-300
-400
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
Figure 5. Offset Voltage vs Power Supply
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-1
0
1
Common-Mode Voltage (V)
2
3
DC21
Figure 4. Offset Voltage vs Common-Mode Voltage
Figure 3. Offset Voltage vs Temperature
2
-2
DC08
500
Offset Voltage (µV)
1.6
450
400
16
1.2
Figure 2. Offset Voltage Drift Distribution
500
-500
1.5
0.8
Offset Voltage Drift (µV/C)
VS = 5.5 V, TA = –40°C to 125°C
600
-600
-40
0.4
5.5
120
110
100
IBIB+
IOS
90
80
70
60
50
40
30
20
10
0
-50
-25
0
DC23
25
50
Temperature (°C)
75
100
125
DC02
Figure 6. Input Bias Current vs Temperature
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Typical Characteristics (continued)
18
IBIB+
IOS
16
14
Voltage (1µV/div)
Input Bias Current and Offset Current (pA)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
12
10
8
6
4
2
0
-3
-2
-1
0
1
Input Common-Mode Voltage (V)
2
Time (1s/div)
3
D008
DC03
Figure 8. 0.1-Hz to 10-Hz Input Voltage Noise
140
120
120
100
PSRR and CMRR (dB)
Input Voltage Noise Spectral Density (nV/—Hz)
Figure 7. Input Bias Current and Offset Current vs CommonMode Voltage
100
80
60
40
80
60
40
20
20
0
10
100
1k
Frequency (Hz)
10k
0
100
100k
20
200
19
D018
17
120
100
80
16
15
14
13
60
12
40
11
20
0
-50
1M
18
VS = 5.5 V, VCM = -0.1 V to (V+) - 1.4 V
VS = 5.5 V, VCM = -0.1 V to 5.6 V
VS = 1.8 V, VCM = -0.1 V to (V+) - 1.4 V
VS = 1.8 V, VCM = -0.1 V to 5.6 V
PSRR (µV/V)
CMRR (µV/V)
140
10k
100k
Frequency (Hz)
Figure 10. CMRR and PSRR vs Frequency
(Referred to Input)
220
160
1k
D024
Figure 9. Input Voltage Noise Spectral Density vs Frequency
180
PSRR+
PSRRCMRR
-25
0
25
50
Temperature (°C)
75
100
125
10
-50
-25
0
DC17
25
50
Temperature (°C)
75
100
125
DC18
VS = 1.8 V to 5.5 V
Figure 11. CMRR vs Temperature
Figure 12. PSRR vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
100
60
80
40
60
20
40
0
20
Gain
Phase
-20
100
1k
10k
100k
Frequency (Hz)
130
Open Loop Voltage Gain (dB)
80
135
Phase Margin (q)
120
Open Loop Voltage Gain (dB)
100
125
120
115
110
105
100
0
10M
1M
95
-40
0
180
70
160
60
140
120
100
80
60
40
20
20
40
60
80
Temperature (°C)
100
140
DC01
G=1
G = -1
G = 10
G = 100
G = 1000
50
40
30
20
10
0
-10
-20
0.5
1.5
2.5
3.5
Output Voltage (V)
4.5
-30
1k
5.5
10k
DC26
Figure 15. Open Loop Voltage Gain vs Output Voltage
100k
Frequency (Hz)
1M
10M
D005
Figure 16. Closed Loop Voltage Gain vs Frequency
70
VOUT
VIN
60
50
Voltage (1 V/div)
Phase Margin (q)
120
Figure 14. Open Loop Voltage Gain vs Temperature
Closed Lopp Voltage Gain (dB)
Open Loop Voltage Gain (dB)
-20
D004
Figure 13. Open Loop Voltage Gain and Phase vs Frequency
0
-0.5
VS = 1.8V, RL = 2k:
VS = 5.5V, RL = 2k:
VS = 1.8V, RL = 10k:
VS = 5.5V, RL = 10k:
40
30
20
10
0
0
50
100
150
200
250
Capacitive Load (pF)
300
Figure 17. Phase Margin vs Capacitive Load
18
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Time (100 Ps/div)
350
D013
D017
Figure 18. No Phase Reversal
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Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
60
60
Overshoot(+)
Overshoot(-)
50
Overshoot(+)
Overshoot(-)
50
Overshoot (%)
Overshoot (%)
40
30
20
40
30
20
10
0
10
0
50
100
150 200 250 300
Capacitive Load (pF)
350
400
450
0
50
100
150 200 250 300
Capacitive Load (pF)
D016
G = +1 V/V
VOUT step = 100 mVp-p
350
400
450
D015
G = –1 V/V
VOUT step = 100 mVp-p
Figure 19. Small-Signal Overshoot vs Load Capacitance
Figure 20. Small-Signal Overshoot vs Load Capacitance
17
Slew Rate (V/Ps)
16
15.5
15
14.5
14
Output Voltage (2 V/div)
Input Voltage (0.2 V/div)
16.5
Output
Input
13.5
13
50
100
150
200
250
Capacitive Load (pF)
300
Time (2 us/div)
350
D014
D019
G = –10 V/V
Figure 22. Overload Recovery
Figure 21. Slew Rate vs Capacitive Load
VOUT
VIN
Voltage (2 mV/div)
Voltage (2 mV/div)
VOUT
VIN
Time (1 Ps)
Time (1 Ps/div)
D020
D021
G = +1 V/V
VOUT step = 10
mVp-p
G = –1 V/V
VOUT step = 10
mVp-p
Figure 23. Small-Signal Step Response
Figure 24. Small-Signal Step Response
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Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
VIN
VOUT
VIN
Voltage (1 V/div)
Voltage (1 V/div)
VOUT
Time (1 Ps/div)
Time (1 Ps/div)
D012
D011
G = +1 V/V
VOUT step = 4 Vp-p
G = –1 V/V
VOUT step = 4 Vp-p
Figure 25. Large-Signal Step Response
Figure 26. Large-Signal Step Response
20
Output Delta from Final Value (mV)
Output Delta from Final Value (mV)
20
10
0
0.1% Settling = r 2 mV
-10
-20
-30
0.2
0.4
CL = 100 pF
0.6
0.8
Time (µs)
1
1.2
10
0
0.1% Settling = r 2 mV
-10
-20
-30
0.2
1.4
0.4
0.6
D010
G = +1 V/V
CL = 100 pF
Figure 27. Positive Large-Signal Settling Time
0.8
Time (µs)
1
1.2
1.4
D009
G = +1 V/V
Figure 28. Negative Large-Signal Settling Time
-10
-65
RL = 10 k:
RL = 2 k:
RL = 600 :
-30
G = +1, RL = 10 k:
G = +1, RL = 2 k:
G = +1, RL = 600 :
THD + N (dB)
THD + N (dB)
-75
-85
-50
-70
-95
-90
-105
100
1k
Frequency (Hz)
VOUT = 0.5 VRMS
G = +1
BW = 80 kHz
D023
VCM = 2.5 V
Figure 29. THD + N vs Frequency
20
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-110
1m
10k
10m
100m
Output Voltage Amplitude (V RMS)
f = 1 kHz
G = +1
BW = 80 kHz
1
D022
VCM = 2.5 V
Figure 30. THD + N vs Amplitude
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Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
6
3
2.5
Maximum Output Voltage (V)
2
Output Voltage (V)
1.5
125qC
1
85qC
0.5
25qC
-40qC
0
-0.5
85qC
-1
25qC
-40qC
125qC
-1.5
-2
5
4
3
2
1
VS = 5.5 V
VS = 1.8 V
-2.5
0
-3
0
10
20
30
40
Output Current (mA)
50
1
60
Figure 31. Output Voltage Swing vs Output Current
100
1k
10k
100k
Frequency (Hz)
1M
10M
100M
DC25
Figure 32. Maximum Output Voltage vs Frequency and
Supply Voltage
330
100
Sinking
Sourcing
80
325
60
Quiescent Current (µA)
Short Circuit Current Limit (mA)
10
DC07
40
20
0
-20
-40
320
315
310
305
-60
-80
-40
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
300
1.8
110 125
Figure 33. Short-Circuit Current vs Temperature
Open Loop Output Impedance (:)
Quiescent Current (µA)
325
320
315
310
305
0
20
40
60
Temperature (°C)
80
100
120
Figure 35. Quiescent Current vs Temperature
3.3
3.8
4.3
Supply Voltage (V)
4.8
5.3
DC05
500
400
VS = 1.8V
VS = 5.5V
-20
2.8
Figure 34. Quiescent Current vs Supply Voltage
330
300
-40
2.3
DC06
300
200
100
IOUT = 0 mA
IOUT = 5 mA
IOUT = -5 mA
70
50
40
30
20
10k
DC04
100k
Frequency (Hz)
1M
D025
Figure 36. Open-Loop Output Impedance vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
-70
120
-80
Channel Separation (dB)
140
EMIRR (dB)
100
80
60
40
-100
-110
-120
20
0
10M
-90
100M
Frequency (Hz)
-130
100
1G
1k
D007
PRF = –10 dBm
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1M
D006
PRF = –10 dBm
Figure 37. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR+) vs Frequency
22
10k
100k
Frequency (Hz)
Figure 38. Channel Separation vs Frequency
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8 Detailed Description
8.1 Overview
The TLV905x devices are a 5-MHz family of low-power, rail-to-rail input and output op amps. These devices
operate from 1.8 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose
applications. The input common-mode voltage range includes both rails and allows the TLV905x family to be
used in virtually any single-supply application. The unique combination of a high slew rate and low quiescent
current makes this family a potential choice for battery-powered motor-drive applications. Rail-to-rail input and
output swing significantly increase dynamic range, especially in low-supply applications.
8.2 Functional Block Diagram
V+
Reference
Current
V
V
INÛ
IN+
V
BIAS1
Class AB
Control
Circuitry
V
O
V
BIAS2
VÛ
(Ground)
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8.3 Feature Description
8.3.1 Operating Voltage
The TLV905x family of op amps is specified for operation from 1.8 V to 5.5 V. In addition, many specifications
apply from –40°C to 125°C. Parameters that vary significantly with operating voltages or temperature are
illustrated in the Typical Characteristics section.
8.3.2 Rail-to-Rail Input
The input common-mode voltage range of the TLV905x family extends 100 mV beyond the supply rails for the
full supply voltage range of 1.8 V to 5.5 V. This performance is achieved with a complementary input stage: an
N-channel input differential pair in parallel with a P-channel differential pair, as shown in the Functional Block
Diagram. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to 200 mV
above the positive supply, whereas the P-channel pair is active for inputs from 200 mV below the negative
supply to approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1 V, in
which both pairs are on. This 200-mV transition region can vary up to 200 mV with process variation. Thus, the
transition region (with both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, and up to
(V+) – 1 V to (V+) – 0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift,
and THD can degrade compared to device operation outside this region.
8.3.3 Rail-to-Rail Output
Designed as low-power, low-voltage operational amplifiers, the TLV905x family delivers a robust output drive
capability. A class AB output stage with common-source transistors achieves full rail-to-rail output swing
capability. For resistive loads of 10 kΩ, the output swings to within 16 mV of either supply rail, regardless of the
applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the
rails.
8.3.4 EMI Rejection
The TLV905x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the TLV905x benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz.
Figure 39 shows the results of this testing on the TLV905x. Table 1 shows the EMIRR IN+ values for the
TLV905x at particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of
Operational Amplifiers application report contains detailed information on the topic of EMIRR performance as it
relates to op amps and is available for download from www.ti.com.
140
120
EMIRR (dB)
100
80
60
40
20
0
10M
100M
Frequency (Hz)
1G
D007
Figure 39. EMIRR Testing
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Feature Description (continued)
Table 1. TLV905x EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
59.5 dB
900 MHz
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
68.9 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
77.8 dB
2.4 GHz
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
78.0 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
88.8 dB
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
87.6 dB
5 GHz
8.3.5 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the rated operating voltage, because of the high input voltage or high gain. After the device
enters the saturation region, the output devices require time to return to the linear operating state. After the
output devices return to their linear operating state, the device begins to slew at the specified slew rate.
Therefore, the propagation delay (in case of an overload condition) is the sum of the overload recovery time and
the slew time. The overload recovery time for the TLV905x family is approximately 300 ns.
8.3.6 Packages With an Exposed Thermal Pad
The TLV905x family is available in packages such as the WSON-8 (DSG) and WQFN-16 (RTE) which feature an
exposed thermal pad. Inside the package, the die is attached to this thermal pad using an electrically conductive
compound. For this reason, when using a package with an exposed thermal pad, the thermal pad must either be
connected to V– or left floating. Attaching the thermal pad to a potential other then V– is not allowed, and the
performance of the device is not assured when doing so.
8.3.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. Figure 40 shows the ESD circuits contained in the TLV905x devices. The ESD protection circuitry
involves several current-steering diodes connected from the input and output pins and routed back to the internal
power supply lines, where they meet at an absorption device internal to the operational amplifier. This protection
circuitry is intended to remain inactive during normal circuit operation.
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V+
Power Supply
ESD Cell
+IN
+
±
± IN
OUT
V±
Figure 40. Equivalent Internal ESD Circuitry
8.3.8 Input Protection
The TLV905x family incorporates internal ESD protection circuits on all pins. For input and output pins, this
protection primarily consists of current-steering diodes connected between the input and power-supply pins.
These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to 10
mA, as shown in the Absolute Maximum Ratings. Figure 41 shows how a series input resistor can be added to
the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and
the value must be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA maximum
Device
VOUT
VIN
5 kW
Figure 41. Input Current Protection
8.3.9 Shutdown Function
The TLV905xS devices feature SHDN pins that disable the op amp, placing it into a low-power standby mode. In
this mode, the op amp typically consumes less than 1 µA. The SHDN pins are active low, meaning that
shutdown mode is enabled when the input to the SHDN pin is a valid logic low.
The SHDN pins are referenced to the negative supply voltage of the op amp. The threshold of the shutdown
feature lies around 800 mV (typical) and does not change with respect to the supply voltage. Hysteresis has
been included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown
behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage
between V– and V– + 0.4 V. A valid logic high is defined as a voltage between V– + 1.2 V and V+. The shutdown
pin circuitry includes a pull-up resistor, which will inherently pull the voltage of the pin to the positive supply rail if
not driven. Thus, to enable the amplifier, the SHDN pins should either be left floating or driven to a valid logic
high. To disable the amplifier, the SHDN pins must be driven to a valid logic low .While we highly recommend
that the shutdown pin be connected to a valid high or a low voltage or driven, we have included a pull-up resistor
connected to VCC. The maximum voltage allowed at the SHDN pins is (V+) + 0.5 V. Exceeding this voltage level
will damage the device.
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The SHDN pins are high-impedance CMOS inputs. Dual op amp versions are independently controlled and quad
op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature may be
used to greatly reduce the average current and extend battery life. The enable time is 35 µs for full shutdown of
all channels; disable time is 6 µs. When disabled, the output assumes a high-impedance state. This architecture
allows the TLV905xS to be operated as a gated amplifier (or to have the device output multiplexed onto a
common analog output bus). Shutdown time (tOFF) depends on loading conditions and increases as load
resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load to
midsupply (VS / 2) is required. If using the TLV905xS without a load, the resulting turnoff time is significantly
increased.
8.4 Device Functional Modes
The TLV905x family is operational when the power-supply voltage is between 1.8 V (±0.9 V) and 5.5 V (±2.75 V).
The TLV905xS devices feature a shutdown mode and are shutdown when a valid logic low is applied to the
shutdown pin.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TLV905x family features 5-MHz bandwidth and very high slew rate of 15 V/µs with only 330 µA of supply
current per channel, providing excellent AC performance at very low-power consumption. DC applications are
well served with a very low input noise voltage of 15 nV/√Hz at 10 kHz, low input bias current, and a typical input
offset voltage of 0.33 mV.
9.2 Typical Low-Side Current Sense Application
Figure 42 shows the TLV905x configured in a low-side current sensing application.
VBUS
ILOAD
Z LOAD
5V
+
TLV905x
RSHUNT
0.1 Ÿ
VSHUNT
VOUT
í
+
í
RF
165 NŸ
RG
3.4 NŸ
Figure 42. TLV905x in a Low-Side, Current-Sensing Application
9.2.1 Design Requirements
The design requirements for this design are:
• Load current: 0 A to 1 A
• Output voltage: 4.95 V
• Maximum shunt voltage: 100 mV
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Typical Low-Side Current Sense Application (continued)
9.2.2 Detailed Design Procedure
The transfer function of the circuit in Figure 42 is given in Equation 1.
VOUT ILOAD u RSHUNT u Gain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from
0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using Equation 2.
VSHUNT _ MAX 100mV
RSHUNT
100m:
ILOAD _ MAX
1A
(2)
Using Equation 2, RSHUNT equals 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is amplified by the
TLV905x device to produce an output voltage of approximately 0 V to 4.95 V. Equation 3 calculates the gain
required for the TLV905x device to produce the required output voltage.
Gain
VOUT _ MAX
VIN _ MAX
VOUT _ MIN
VIN _ MIN
(3)
Using Equation 3, the required gain equals 49.5 V/V, which is set with the RF and RG resistors. Equation 4 sizes
the RF and RG, resistors to set the gain of the TLV905x device to 49.5 V/V.
RF
Gain 1
RG
(4)
Selecting RF to equal 165 kΩ and RG to equal 3.4 kΩ provides a combination that equals approximately 49.5
V/V. Figure 43 shows the measured transfer function of the circuit shown in Figure 42.
9.2.3 Application Curve
5
Output (V)
4
3
2
1
0
0
0.2
0.4
0.6
0.8
ILOAD (A)
1
C219
Figure 43. Low-Side, Current-Sense Transfer Function
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10 Power Supply Recommendations
The TLV905x family is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply
from –40°C to 125°C. The Typical Characteristics section presents parameters that can exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 6 V can permanently damage the device; see the Absolute
Maximum Ratings table.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more-detailed information on bypass capacitor placement, see the Layout
Example section.
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11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care
to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more
detailed information, see Circuit Board Layout Techniques.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 45, keeping RF and
RG close to the inverting input minimizes parasitic capacitance on the inverting input.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low-temperature, postcleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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11.2 Layout Example
+
VIN 1
+
VIN 2
VOUT 1
RG
VOUT 2
RG
RF
RF
Figure 44. Schematic Representation for Figure 45
Place components
close to device and to
each other to reduce
parasitic errors .
OUT 1
VS+
OUT1
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
GND
V+
RF
OUT 2
GND
IN1 ±
OUT2
IN1 +
IN2 ±
RF
RG
VIN 1
GND
RG
V±
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
GND
VS±
IN2 +
VIN 2
Keep input traces short
and run the input traces
as far away from
the supply lines
as possible .
Ground (GND) plane on another layer
Figure 45. Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
Texas Instruments, TLVx313 Low-Power, Rail-to-Rail In/Out, 500-µV Typical Offset, 1-MHz Operational Amplifier
for Cost-Sensitive Systems
Texas Instruments, TLVx314 3-MHz, Low-Power, Internal EMI Filter, RRIO, Operational Amplifier
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers
Texas Instruments, QFN/SON PCB Attachment
Texas Instruments, Quad Flatpack No-Lead Logic Packages
Texas Instruments, Circuit Board Layout Techniques
Texas Instruments, Single-Ended Input to Differential Output Conversion Circuit Reference Design
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 2. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLV9051/S
Click here
Click here
Click here
Click here
Click here
TLV9052/S
Click here
Click here
Click here
Click here
Click here
TLV9054/S
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV9051IDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T51D
TLV9051IDCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
T51
TLV9051IDPWR
ACTIVE
X2SON
DPW
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
FH
TLV9051SIDBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T51S
TLV9052IDDFR
ACTIVE
SOT-23-THIN
DDF
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T052
TLV9052IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1PWX
TLV9052IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TL9052
TLV9052IDSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
9052
TLV9052IPWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TL9052
TLV9052SIDGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
T052
TLV9052SIRUGR
ACTIVE
X2QFN
RUG
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
FPF
TLV9054IDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLV9054D
TLV9054IPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
T9054PW
TLV9054IRTER
ACTIVE
WQFN
RTE
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T54RT
TLV9054IRUCR
ACTIVE
QFN
RUC
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1FF
TLV9054SIRTER
ACTIVE
WQFN
RTE
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T9054S
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Dec-2019
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TLV9051IDBVR
Package Package Pins
Type Drawing
SPQ
SOT-23
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
DBV
5
3000
180.0
8.4
3.2
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.2
1.4
4.0
8.0
Q3
TLV9051IDCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TLV9051IDPWR
X2SON
DPW
5
3000
178.0
8.4
0.91
0.91
0.5
2.0
8.0
Q2
TLV9051SIDBVR
SOT-23
DBV
6
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TLV9052IDDFR
SOT23-THIN
DDF
8
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TLV9052IDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
TLV9052IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLV9052IDSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
TLV9052IPWR
TSSOP
PW
8
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
TLV9052SIDGSR
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
TLV9052SIRUGR
X2QFN
RUG
10
3000
178.0
8.4
1.75
2.25
0.56
4.0
8.0
Q1
TLV9054IPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TLV9054IRTER
WQFN
RTE
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TLV9054IRUCR
QFN
RUC
14
3000
180.0
9.5
2.16
2.16
0.5
4.0
8.0
Q2
TLV9054SIRTER
WQFN
RTE
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Dec-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV9051IDBVR
TLV9051IDCKR
SOT-23
DBV
5
3000
210.0
185.0
35.0
SC70
DCK
5
3000
190.0
190.0
30.0
TLV9051IDPWR
X2SON
DPW
5
3000
205.0
200.0
33.0
TLV9051SIDBVR
SOT-23
DBV
6
3000
210.0
185.0
35.0
TLV9052IDDFR
SOT-23-THIN
DDF
8
3000
210.0
185.0
35.0
TLV9052IDGKR
VSSOP
DGK
8
2500
366.0
364.0
50.0
TLV9052IDR
SOIC
D
8
2500
367.0
367.0
35.0
TLV9052IDSGR
WSON
DSG
8
3000
210.0
185.0
35.0
TLV9052IPWR
TSSOP
PW
8
2000
367.0
367.0
35.0
TLV9052SIDGSR
VSSOP
DGS
10
2500
366.0
364.0
50.0
TLV9052SIRUGR
X2QFN
RUG
10
3000
205.0
200.0
33.0
TLV9054IPWR
TSSOP
PW
14
2000
366.0
364.0
50.0
TLV9054IRTER
WQFN
RTE
16
3000
367.0
367.0
35.0
TLV9054IRUCR
QFN
RUC
14
3000
205.0
200.0
30.0
TLV9054SIRTER
WQFN
RTE
16
3000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
SCALE 3.200
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
10
1
3.1
2.9
NOTE 3
8X 0.5
2X
2
5
6
B
10X
3.1
2.9
NOTE 4
SEE DETAIL A
0.27
0.17
0.1
C A
1.1 MAX
B
0.23
TYP
0.13
0.25
GAGE PLANE
0 -8
0.15
0.05
0.7
0.4
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (0.3)
10X (1.45)
(R0.05)
TYP
SYMM
1
10
SYMM
8X (0.5)
6
5
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
10X (0.3)
SYMM
1
(R0.05) TYP
10
SYMM
8X (0.5)
6
5
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DPW0005A
X2SON - 0.4 mm max height
SCALE 12.000
PLASTIC SMALL OUTLINE - NO LEAD
0.85
0.75
B
A
0.85
0.75
PIN 1 INDEX AREA
0.4 MAX
C
SEATING PLANE
NOTE 3
(0.1)
0.05
0.00
(0.25)
4X (0.05)
0.25 0.1
2
4
2X
0.48
3
NOTE 3
2X (0.26)
5
1
4X
0.27
0.17
(0.06)
3X
0.27
0.17
0.1 C A B
0.05 C
0.32
0.23
4223102/B 09/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The size and shape of this feature may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.78)
SYMM
4X (0.42)
( 0.1)
VIA
0.05 MIN
ALL AROUND
TYP
1
5
4X (0.22)
SYMM
4X (0.26)
(0.48)
3
2
4
(R0.05) TYP
( 0.25)
4X (0.06)
(0.21) TYP
EXPOSED METAL
CLEARANCE
SOLDER MASK
OPENING, TYP
METAL UNDER
SOLDER MASK
TYP
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:60X
4223102/B 09/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (0.42)
4X (0.22)
4X (0.06)
5
1
( 0.24)
4X (0.26)
SYMM
(0.21)
TYP
SOLDER MASK
EDGE
3
2
(R0.05) TYP
(0.48)
4
SYMM
(0.78)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
92% PRINTED SOLDER COVERAGE BY AREA
SCALE:100X
4223102/B 09/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DSG 8
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2 x 2, 0.5 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.32
0.18
0.4
0.2
OPTIONAL TERMINAL
TYPICAL
C
0.8 MAX
SEATING PLANE
0.05
0.00
0.08 C
EXPOSED
THERMAL PAD
(0.2) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
SEE OPTIONAL
TERMINAL
9
8
1
PIN 1 ID
1.6 0.1
8X
0.4
8X
0.2
0.32
0.18
0.1
0.05
C A B
C
4218900/C 04/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
8X (0.5)
( 0.2) VIA
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(R0.05) TYP
(1.9)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218900/C 04/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
SYMM
METAL
1
8
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/C 04/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
SCALE 2.800
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
1
3.1
2.9
NOTE 3
2X
1.95
4
5
B
4.5
4.3
NOTE 4
SEE DETAIL A
8X
0.30
0.19
0.1
C A
1.2 MAX
B
(0.15) TYP
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
1
8
(R0.05)
TYP
SYMM
6X (0.65)
5
4
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
(R0.05) TYP
1
8
SYMM
6X (0.65)
5
4
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE
C
2.95
TYP
2.65
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
8
1
6X 0.65
2.95
2.85
NOTE 3
2X
1.95
4
5
B
1.65
1.55
8X
0.4
0.2
0.1
C A
B
1.1 MAX
0.20
TYP
0.08
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.6
0.3
0.1
0.0
DETAIL A
TYPICAL
4222047/B 11/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/B 11/2015
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/B 11/2015
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
6
2X 0.95
1.9
1.45 MAX
3.05
2.75
5
2
4
0.50
6X
0.25
0.2
C A B
3
(1.1)
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214840/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X (0.95)
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214840/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X(0.95)
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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