Texas Instruments | MCP629x 10-MHz, Rail-to-Rail Operational Amplifier (Rev. D) | Datasheet | Texas Instruments MCP629x 10-MHz, Rail-to-Rail Operational Amplifier (Rev. D) Datasheet

Texas Instruments MCP629x 10-MHz, Rail-to-Rail Operational Amplifier (Rev. D) Datasheet
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MCP6291, MCP6292, MCP6294
SBOS879D – JULY 2017 – REVISED OCTOBER 2019
MCP629x 10-MHz, Rail-to-Rail Operational Amplifier
1 Features
3 Description
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The MCP6291 (single), MCP6292 (dual), and
MCP6294 (quad) devices comprise a family of
general-purpose, low-power operational amplifiers.
Features such as rail-to-rail input and output swings,
low quiescent current (600-μA/ch typical) combined
with a wide bandwidth of 10 MHz, and low noise (8.7
nV/√Hz at 10 kHz) make this family attractive for a
variety of applications that require a balance between
cost and performance. The low input bias current
enables the family to be used in applications with
high-source impedances.
1
Gain bandwidth product: 10-MHz typical
Operating supply voltage: 2.4 V to 5.5 V
Rail-to-rail input/output
Low input bias current: 1 pA
Low quiescent current: 0.6 mA
Input voltage noise: 8.7 nV/√Hz at f = 10 kHz
Internal RF and EMI filter
Extended temperature range: –40°C to 125°C
Unity-gain stable
Easier to stabilize with higher capacitive load due
to resistive open-loop output impedance
2 Applications
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Power modules
Smoke detectors
HVAC: heating, ventilating, and air conditioning
Battery-powered applications
Sensor signal conditioning
Photodiode amplifier
Analog filters
Medical instrumentation
Notebooks and PDAs
Barcode scanners
Audio receiver
Automotive infotainment
The robust design of the MCP629x provides ease-ofuse to the circuit designer: a unity-gain stable,
integrated RFI and EMI rejection filter, no phase
reversal in overdrive condition, and high electrostatic
discharge (ESD) protection (4-kV HBM).
The MCP629x family operates over the extended
temperature range of –40°C to 125°C. The family has
a power supply range of 2.4 V to 5.5 V.
Device Information(1)
PART NUMBER
PACKAGE
MCP6291
MCP6292
MCP6294
BODY SIZE (NOM)
SOT-23 (5)
1.60 mm × 2.90 mm
SC70 (5)
1.25 mm × 2.00 mm
SOIC (8)
3.91 mm × 4.90 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOT-23 (8)
1.60 mm × 2.90 mm
SOIC (14)
8.65 mm × 3.91 mm
TSSOP (14)
4.40 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Small-Signal Overshoot vs Load Capacitance
Low-Side Motor Control
60
VBUS
ZLOAD
5V
+
VOUT
MCP629x
VSHUNT
RSHUNT
0.1
RF
165 k
Overshoot (%)
50
ILOAD
40
30
20
10
Overshoot+
Overshoot-
RG
3.4 k
0
0
50
100
150
200
Capacitive Load (pF)
250
300
C025
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MCP6291, MCP6292, MCP6294
SBOS879D – JULY 2017 – REVISED OCTOBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
8
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Absolute Maximum Ratings ...................................... 8
ESD Ratings.............................................................. 8
Recommended Operating Conditions....................... 8
Thermal Information: MCP6291................................ 8
Thermal Information: MCP6292................................ 9
Thermal Information: MCP6294................................ 9
Electrical Characteristics: VS (Total Supply Voltage) =
(V+) – (V–) = 2.4 V to 5.5 V ..................................... 10
7.8 Typical Characteristics ............................................ 12
8
Detailed Description ............................................ 18
8.1 Overview ................................................................. 18
8.2 Functional Block Diagram ....................................... 18
8.3 Feature Description................................................. 19
8.4 Device Functional Modes........................................ 19
9
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application .................................................. 20
10 Power Supply Recommendations ..................... 22
10.1 Input and ESD Protection ..................................... 22
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 23
12 Device and Documentation Support ................. 24
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
24
13 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
Changes from Revision C (January 2019) to Revision D
•
Page
Added SOT-23 (8) (DDF) package to data sheet................................................................................................................... 1
Changes from Revision B (April 2018) to Revision C
Page
•
Deleted SOT-23 package preview notation in Device Information table................................................................................ 1
•
Added SC70 package to Device Information table................................................................................................................. 1
•
Added DCK package information to Device Comparison Table ........................................................................................... 4
•
Deleted DBV package preview notation from Pin Configuration and Functions section........................................................ 5
•
Added DCK package drawing and pin functions to Pin Configuration and Functions section ............................................... 5
•
Added DBV (SOT-23) and DCK (SC70) thermal information................................................................................................. 8
Changes from Revision A (October 2017) to Revision B
•
Page
Added DGK package to Thermal Information table .............................................................................................................. 9
Changes from Original (July 2017) to Revision A
Page
•
Deleted MCP6291 SC70, SOT-553, and SOIC packages from Device Information table..................................................... 1
•
Deleted MCP6292 WSON and VSSOP (10) packages from Device Information table ......................................................... 1
•
Changed MCP6294 14-pin SOIC package from preview to production data in Device Information table ............................ 1
•
Deleted DCK, DRL, DSG, RTE and 8-pin D packages from Device Comparison table ....................................................... 4
•
Deleted DRL (SOT-533) package from MCP6291 pinout image and table in Pin Configuration and Functions section ..... 5
•
Deleted MCP6291 DCK (SC70) and D (SOIC) package pinout drawings and pin information from Pin Configuration
and Functions section............................................................................................................................................................. 5
•
Deleted MCP6292 DSG (WSON) and DGS (VSSOP) package pinout drawings and pin table information in Pin
Configuration and Functions section ..................................................................................................................................... 6
2
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Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: MCP6291 MCP6292 MCP6294
MCP6291, MCP6292, MCP6294
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SBOS879D – JULY 2017 – REVISED OCTOBER 2019
•
Deleted package preview note from MCP6294 pinout drawing in Pin Configuration and Functions section ....................... 7
•
Added MCP6294 Thermal Information table ......................................................................................................................... 9
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: MCP6291 MCP6292 MCP6294
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MCP6291, MCP6292, MCP6294
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5 Device Comparison Table
PACKAGE LEADS
NO. OF
CHANNELS
DBV
DCK
D
DGK
PW
DDF
MCP6291
1
5
5
—
—
—
—
MCP6292
2
—
—
8
8
—
8
MCP6294
4
—
—
14
—
14
—
DEVICE
4
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Product Folder Links: MCP6291 MCP6292 MCP6294
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SBOS879D – JULY 2017 – REVISED OCTOBER 2019
6 Pin Configuration and Functions
MCP6291 DBV Package
5-Pin SOT-23
Top View
OUT
1
V-
2
+IN
3
5
4
MCP6291 DCK Package
5-Pin SC70
Top View
V+
-IN
IN+
1
V±
2
IN±
3
5
V+
4
OUT
Not to scale
Pin Functions: MCP6921
PIN
NAME
NO.
I/O
DESCRIPTION
SOT-23 (DBV)
SC70 (DCK)
–IN
4
3
I
Inverting input
+IN
3
1
I
Noninverting input
OUT
1
4
O
Output
V–
2
8
—
Negative (lowest) supply or ground (for single-supply operation)
V+
5
5
—
Positive (highest) supply
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MCP6292 D, DGK, DDF Packages
8-Pin SOIC, VSSOP
Top View
OUT A
1
8
V+
-IN A
2
7
OUT B
+IN A
3
6
-IN B
V-
4
5
+IN B
Pin Functions: MCP6292
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
Inverting input, channel A
+IN A
3
I
Noninverting input, channel A
–IN B
6
I
Inverting input, channel B
+IN B
5
I
Noninverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V–
4
—
Negative (lowest) supply or ground (for single-supply operation)
V+
8
—
Positive (highest) supply
6
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SBOS879D – JULY 2017 – REVISED OCTOBER 2019
MCP6294 D, PW Packages
14-Pin SOIC, TSSOP
Top View
14
OUT D
13
-IN D
3
12
+IN D
V+
4
11
V-
+IN B
5
10
+IN C
-IN B
6
9
-IN C
OUT B
7
8
OUT C
OUT A
1
-IN A
2
+IN A
A
B
D
C
Pin Functions: MCP6294
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
Inverting input, channel A
+IN A
3
I
Noninverting input, channel A
–IN B
6
I
Inverting input, channel B
+IN B
5
I
Noninverting input, channel B
–IN C
9
I
Inverting input, channel C
+IN C
10
I
Noninverting input, channel C
–IN D
13
I
Inverting input, channel D
+IN D
12
I
Noninverting input, channel D
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
OUT C
8
O
Output, channel C
OUT D
14
O
Output, channel D
V–
11
—
Negative (lowest) supply or ground (for single-supply operation)
V+
4
—
Positive (highest) supply
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted) (1)
MIN
MAX
UNIT
6
V
Supply voltage
Voltage (2)
Signal input pins
Common-mode
Current (2)
Output short-circuit
(V–) – 0.5
(V+) + 0.5
Differential
(V+) – (V–) + 0.2
–10
(3)
10
mA
–40
Junction, TJ
Storage, Tstg
(1)
(2)
(3)
mA
Continuous
Specified, TA
V
–65
125
°C
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Current limit input signals that can swing more than 0.5 V beyond the supply
rails to 10 mA or less.
Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
over operating free-air temperature range (unless otherwise noted)
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
MAX
UNIT
Supply voltage
2.4
5.5
V
Specified temperature
–40
125
°C
7.4 Thermal Information: MCP6291
MCP6291
THERMAL METRIC (1)
DBV (SOT-23)
DCK (SC70)
5 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
221.7
263.3
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
144.7
75.5
°C/W
RθJB
Junction-to-board thermal resistance
49.7
51.0
°C/W
ψJT
Junction-to-top characterization parameter
26.1
1.0
°C/W
ψJB
Junction-to-board characterization parameter
49.0
50.3
°C/W
(1)
8
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Thermal Information: MCP6292
MCP6292
THERMAL METRIC (1)
D (SOIC)
DGK (VSSOP)
DDF (SOT-23)
8 PINS
8 PINS
8 PINS
UNIT
201.2
184.4
°C/W
RθJA
Junction-to-ambient thermal resistance
157.6
RθJC(top)
Junction-to-case (top) thermal resistance
104.6
85.7
112.8
°C/W
RθJB
Junction-to-board thermal resistance
99.7
122.9
99.9
°C/W
ψJT
Junction-to-top characterization parameter
55.6
21.2
18.7
°C/W
ψJB
Junction-to-board characterization parameter
99.2
121.4
99.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Thermal Information: MCP6294
MCP6294
THERMAL METRIC (1)
D (SOIC)
PW (TSSOP)
UNIT
14 PINS
14 PINS
106.9
135.8
°C/W
64
64
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case(top) thermal resistance
RθJB
Junction-to-board thermal resistance
63
79
°C/W
ψJT
Junction-to-top characterization parameter
25.9
15.7
°C/W
ψJB
Junction-to-board characterization parameter
62.7
78.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: MCP6291 MCP6292 MCP6294
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7.7 Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 2.4 V to 5.5 V
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±0.3
±3
UNIT
OFFSET VOLTAGE
VS = 5 V
VOS
Input offset voltage
dVOS/dT
Drift
VS = 5 V, TA = –40°C to 125°C
±1.1
µV/°C
PSRR
Power-supply rejection ratio
VS = 2.4 V – 5.5 V, VCM = (V–)
±7
µV/V
Channel separation, DC
At DC
100
dB
VS = 5 V, TA = –40°C to 125°C
±5
mV
INPUT VOLTAGE RANGE
VCM
CMRR
Common-mode voltage range
Common-mode rejection ratio
VS = 2.4 V to 5.5 V
(V–) – 0.1
(V+) + 0.1
VS = 5.5 V
(V–) – 0.1 V < VCM < (V+) – 1.4 V
TA = –40°C to 125°C
80
103
VS = 5.5 V
VCM = –0.1 V to 5.6 V
TA = –40°C to 125°C
57
87
V
dB
VS = 2.4 V
(V–) – 0.1 V < VCM < (V+) – 1.4 V
TA = –40°C to 125°C
88
VS = 2.4 V
VCM = –0.1 V to 1.9 V
TA = –40°C to 125°C
81
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
±1
pA
±0.05
pA
4.77
µVPP
NOISE
En
Input voltage noise (peak-to-peak)
en
Input voltage noise density
in
Input current noise density
VS = 5 V, f = 0.1 Hz to 10 Hz
VS = 5 V, f = 10 kHz, RL = 10 kΩ
8.7
VS = 5 V, f = 1 kHz, RL = 10 kΩ
16
f = 1 kHz
10
fA/√Hz
nV/√Hz
INPUT CAPACITANCE
CID
Differential
2
pF
CIC
Common-mode
4
pF
OPEN-LOOP GAIN
VS = 2.4 V
(V–) + 0.04 V < VO < (V+) – 0.04 V
RL = 10 kΩ
AOL
Open-loop voltage gain
100
VS = 5.5 V
(V–) + 0.05 V < VO < (V+) – 0.05 V
RL = 10 kΩ
104
130
dB
VS = 2.4 V
(V–) + 0.06 V < VO < (V+) – 0.06 V
RL = 2 kΩ
100
VS = 5.5 V
(V–) + 0.15 V < VO < (V+) – 0.15 V
RL = 2 kΩ
130
FREQUENCY RESPONSE
GBP
Gain bandwidth product
VS = 5 V, G = 1
φm
Phase margin
VS = 5 V, G = 1
55
°
SR
Slew rate
VS = 5 V, G = 1
6.5
V/µs
Settling time
To 0.1%, VS = 5 V, 2-V step , G = 1
CL = 100 pF
0.5
tS
tOR
10
Overload recovery time
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10
MHz
µs
To 0.01%, VS = 5 V, 2-V step , G = 1
CL = 100 pF
1
VS = 5 V
VIN × gain > VS
0.2
µs
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Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 2.4 V to 5.5 V (continued)
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
PARAMETER
THD + N
TEST CONDITIONS
VS = 5 V
VO = 1 VRMS
G = 1, f = 1 kHz
Total harmonic distortion + noise (1)
MIN
TYP
MAX
UNIT
0.0008%
OUTPUT
VS = 5.5 V, RL = 10 kΩ
15
VS = 5.5 V, RL = 2 kΩ
50
VO
Voltage output swing from supply rails
mV
ISC
Short-circuit current
VS = 5 V
±50
mA
ZO
Open-loop output impedance
VS = 5 V, f = 10 MHz
100
Ω
VS = 5.5 V, IO = 0 mA
600
POWER SUPPLY
IQ
(1)
Quiescent current per amplifier
1300
µA
Third-order filter; bandwidth = 80 kHz at –3 dB.
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7.8 Typical Characteristics
500
2500
400
2000
300
1500
Offset Voltage (µV)
Offset Voltage (µV)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
200
100
0
±100
±200
1000
500
0
±500
±1000
±300
±1500
±400
±2000
±500
±2500
±50
0
±25
25
50
75
100
125
Temperature (ƒC)
150
-4
-3
-2
-1
0
1
2
3
4
Input Common Mode Voltage (V)
C003
C005
V+ = 2.75 V, V– = –2.75 V
Figure 2. Offset Voltage vs Common-Mode Voltage
120
Open Loop Voltage Gain (dB)
Offset Voltage (µV)
500
0
±500
±1000
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Supply Voltage (V)
5.5
100
210
Gain
Phase 180
80
150
60
120
40
90
20
60
0
30
-20
100
0
1k
10k
100k
Frequency (Hz)
C004
Input Bias Current and offset current (pA)
Closed Loop Voltage Gain (dB)
30
20
10
0
-10
-20
G = +1
G = +10
G = -1
10k
100k
Frequency (Hz)
1M
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C006
250
IBN
200
IBP
IOS
150
100
50
0
±50
±50
10M
Figure 5. Closed-Loop Gain vs Frequency
12
10M
Figure 4. Open-Loop Gain and Phase vs Frequency
Figure 3. Offset Voltage vs Power Supply
40
-40
1k
1M
CL = 10 pF
VS = 2.4 V to 5.5 V
-30
Phase Margin (q)
Figure 1. Offset Voltage vs Temperature
1000
±25
0
25
50
75
100
Temperature (ƒC)
C007
125
C008
Figure 6. Input Bias Current vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
3
120
PSRRPSRR+
CMRR
100
125ƒC
1
-40ƒC
85ƒC
PSRR and CMRR (dB)
Output Voltage (V)
2
25ƒC
0
25ƒC
85ƒC
±1
-40ƒC
125ƒC
±2
80
60
40
20
±3
10
20
30
40
50
60
Output Current (mA)
C009
0
1k
10k
100k
Frequency (Hz)
V+ = 2.75 V, V– = –2.75 V
1M
10M
C011
Figure 8. CMRR and PSRR vs Frequency
(Referred to Input)
Figure 7. Output Voltage Swing vs Output Current
10
55
9
8
CMRR (µV/V)
CMRR (µV/V)
50
45
40
7
6
5
4
3
35
2
1
30
±50
±25
0
25
50
75
100
Temperature (ƒC)
VS = 5.5 V
TA= –40°C to 125°C
125
±50
±25
0
VCM = (V–) – 0.1 V to (V+) + 0.1 V
RL= 10 kΩ
25
50
75
100
125
Temperature (ƒC)
C012
VS = 5.5 V
RL= 10 kΩ
150
C016
VCM = (V–) – 0.1 V to (V+) – 1.4 V
TA= –40°C to 125°C
Figure 10. CMRR vs Temperature
Figure 9. CMRR vs Temperature
10
Voltage (1µV/div)
PSRR (µV/V)
9
8
7
6
5
±50
±25
0
25
50
75
Temperature (ƒC)
VS = 2.4 V to 5.5 V
Figure 11. PSRR vs Temperature
100
Time (1s/div)
125
C014
C013
VS = 2.4 V to 5.5 V
Figure 12. 0.1-Hz to 10-Hz Input Voltage Noise
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Typical Characteristics (continued)
120
-90
100
-95
80
-100
THD + N (dB)
Input Voltage Noise
Spectral Density (nV/—Hz)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
60
40
-105
-110
-115
20
0
10
100
1k
Frequency (Hz)
10k
100k
-120
100
1k
Frequency (Hz)
C015
VS = 5.5 V
VOUT = 0.5 VRMS
±40
±40
±60
±60
±80
C017
VCM = 2.5 V
G=1
RL = 2 kΩ
BW = 80 kHz
Figure 14. THD + N vs Frequency
THD + N (dB)
THD + N (dB)
Figure 13. Input Voltage Noise Spectral Density vs
Frequency
10k
±80
±100
±100
±120
0.001
0.01
0.1
±120
0.001
1
Output Voltage Amplitude (VRMS)
VS = 5.5 V
G=1
VCM = 2.5 V
BW = 80 kHz
0.01
RL = 2 kΩ
f = 1 kHz
0.1
1
Output Voltage Amplitude (VRMS)
C018
VS = 5.5 V
G = –1
VCM = 2.5 V
BW = 80 kHz
C019
RL = 2 kΩ
f = 1 kHz
Figure 16. THD + N vs Amplitude
Figure 15. THD + N vs Amplitude
800
600
Quiescent Current (µA)
Quiescent current (µA)
700
580
560
540
520
600
500
400
300
200
100
0
500
1.5
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
5.5
Figure 17. Quiescent Current vs Supply Voltage
14
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±50
±25
0
25
50
75
100
Temperature (ƒC)
C020
125
C021
Figure 18. Quiescent Current vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
60
50
160
Overshoot (%)
Open Loop Output Impedance (:)
200
120
80
40
40
30
20
10
Overshoot+
Overshoot-
0
0
10k
100k
1M
Frequency (Hz)
10M
0
50
100
C024
V+ = 2.75 V
RL = 10 kΩ
Figure 19. Open-Loop Output Impedance vs Frequency
150
200
250
Capacitive Load (pF)
300
C025
V– = –2.75 V
VOUT step = 100 mVp-p
G = 1 V/V
Figure 20. Small-Signal Overshoot vs Load Capacitance
60
Voltage (1V/div)
Overshoot (%)
50
40
30
20
10
Input
Overshoot(+)
Output
Overshoot(-)
0
0
50
100
150
200
250
300
Capacitive Load (pF)
V+ = 2.75 V
RL = 10 kΩ
Time (200 µs/div)
C026
V– = –2.75 V
VOUT step = 100 mVp-p
C036
G = –1 V/V
V+ = 2.75 V, V– = –2.75 V
Figure 21. Small-Signal Overshoot vs Load Capacitance
Figure 22. No Phase Reversal
Input
Voltage (2 V/V)
Voltage (20 mV/div)
Output
INPUT
OUTPUT
Time (1 µs/div)
Time (0.1µs/div)
C028
V+ = 2.75 V
V– = –2.75 V
G = –10 V/V
Figure 23. Overload Recovery
C030
V+ = 2.75 V
V– = –2.75 V
G = 1 V/V
Figure 24. Small-Signal Step Response
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Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
Voltage (1 V/div)
Short Circuit Current Limit (mA)
80
Input
Output
60
40
20
Sinking
0
Sourcing
±20
±40
±60
±80
Time (1 µs/div)
±50
0
±25
V+ = 2.75 V
G = 1 V/V
V– = –2.75 V
50
75
100
125
C034
CL = 100 pF
Figure 25. Large-Signal Step Response
Figure 26. Short-Circuit Current vs Temperature
0
120
-20
Channel Seperation (dB)
140
100
EMIRR (dB)
25
Temperature (ƒC)
C031
80
60
40
20
-40
-60
-80
-100
-120
0
10M
100M
1G
Frequency (Hz)
C041
-140
100
1k
10k
100k
Frequency (Hz)
PRF = –10 dBm
1M
10M
C038
V+ = 2.75 V, V– = –2.75 V
Figure 27. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR+) vs Frequency
Figure 28. Channel Separation vs Frequency
200
Open Loop Voltage Gain (dB)
90
Phase Margin (degrees)
75
60
45
30
15
160
120
80
40
0
0
0
10
20
30
40
50
60
70
80
90
Capacitive Load (pF)
100
0
0.5
1
1.5
VS = 5.5 V
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2.5
3
3.5
4
4.5
5
5.5
C023
VS = 5.5 V
Figure 29. Phase Margin vs Capacitive Load
16
2
Output Voltage (V)
C037
Figure 30. Open Loop Voltage Gain vs Output Voltage
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Typical Characteristics (continued)
100
100
75
75
50
50
Output voltage (mV)
Output Voltage (mV)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
25
0
±25
±50
25
0
-25
-50
-75
-100
±75
-125
-150
±100
0
0.3
0.6
0
0.9
Settling time (µs)
Figure 31. Large Signal Settling Time (Positive)
0.3
0.6
0.9
1.2
Settling time (µs)
C032
1.5
C033
Figure 32. Large Signal Settling Time (Negative)
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8 Detailed Description
8.1 Overview
The MCP629x series is a family of low-power, rail-to-rail input and output op amps. These devices operate from
2.4 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose applications. The
input common-mode voltage range includes both rails and allows the MCP629x series to be used in any singlesupply application. Rail-to-rail input and output swing significantly increases dynamic range in low-supply
applications and are designed for driving sampling analog-to-digital converters (ADCs).
8.2 Functional Block Diagram
V+
Reference
Current
V
IN+
V
INÛ
V
Class AB
Control
Circuitry
BIAS1
V
O
V
BIAS2
VÛ
(Ground)
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8.3 Feature Description
8.3.1 Rail-to-Rail Input
The input common-mode voltage range of the MCP629x family extends 100 mV beyond the supply rails for the
full supply voltage range of 2.4 V to 5.5 V. This performance is achieved with a complementary input stage: an
N-channel input differential pair in parallel with a P-channel differential pair, as the Functional Block Diagram
shows. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to 100 mV
above the positive supply, whereas the P-channel pair is active for inputs from 100 mV below the negative
supply to approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1 V, in
which both pairs are on. This 200-mV transition region can vary up to 200 mV with process variation. Thus, the
transition region (with both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, and up to
(V+) – 1 V to (V+) – 0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift,
and THD can degrade compared to device operation outside this region.
8.3.2 Rail-to-Rail Output
Designed as a low-power, low-voltage operational amplifier, the MCP629x series delivers a robust output drive
capability. A class AB output stage with common-source transistors achieves full rail-to-rail output swing
capability. For resistive loads of 10 kΩ, the output swings to within 15 mV of either supply rail, regardless of the
applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the
rails.
8.3.3 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device
enters the saturation region, the charge carriers in the output devices require time to return to the linear state.
After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore,
the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew
time. The overload recovery time for the MCP629x series is approximately 200 ns.
8.4 Device Functional Modes
The MCP629x family has a single functional mode. These devices are powered on as long as the power-supply
voltage is between 2.4 V (±1.2 V) and 5.5 V (±2.75 V).
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The MCP629x series features 10-MHz bandwidth and 6.5-V/µs slew rate with only 600µA of supply current per
channel, providing good AC performance at low power consumption. DC applications are well served with a low
input noise voltage of 8.7 nV / √Hz at 10 kHz, low input bias current, and a typical input offset voltage of 0.3 mV.
9.2 Typical Application
Figure 33 shows the MCP629x configured in a low-side, motor-control application.
VBUS
ILOAD
ZLOAD
5V
+
VOUT
MCP629x
VSHUNT
RSHUNT
0.1
RF
165 k
RG
3.4 k
Figure 33. MCP629x in a Low-Side, Motor-Control Application
9.2.1 Design Requirements
The design requirements for this design are:
• Load current: 0 A to 1 A
• Output voltage: 4.95 V
• Maximum shunt voltage: 100 mV
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Typical Application (continued)
9.2.2 Detailed Design Procedure
The transfer function of the circuit in Figure 33 is shown in Equation 1.
VOUT ILOAD u RSHUNT u Gain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from
0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using Equation 2.
VSHUNT _ MAX 100mV
RSHUNT
100m:
ILOAD _ MAX
1A
(2)
Using Equation 2, RSHUNT is 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is amplified by the
MCP629x to produce an output voltage of roughly 0 V to 4.95 V. The gain needed by the MCP629x to produce
the necessary output voltage is calculated using Equation 3:
Gain
VOUT _ MAX
VIN _ MAX
VOUT _ MIN
VIN _ MIN
(3)
Using Equation 3, the required gain is calculated to be 49.5 V/V, which is set with resistors RF and RG.
Equation 4 is used to size the resistors, RF and RG, to set the gain of the MCP629x to 49.5 V/V.
RF
Gain 1
RG
(4)
Choosing RF as 165 kΩ and RG as 3.4 kΩ provides a combination that equals roughly 49.5 V/V. Figure 34 shows
the measured transfer function of the circuit shown in Figure 33.
9.2.3 Application Curve
5
Output (V)
4
3
2
1
0
0
0.2
0.4
0.6
0.8
ILOAD (A)
1
C219
Figure 34. Low-Side, Current-Sense Transfer Function
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10 Power Supply Recommendations
The MCP629x series is specified for operation from 2.4 V to 5.5 V (±1.2 V to ±2.75 V); many specifications apply
from –40°C to 125°C. The Typical Characteristics section presents parameters that can exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 6 V can permanently damage the device; see the Absolute
Maximum Ratings table.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Example section.
10.1 Input and ESD Protection
The MCP629x series incorporates internal ESD protection circuits on all pins. For input and output pins, this
protection primarily consists of current-steering diodes connected between the input and power-supply pins.
These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to 10mA, as stated in the Absolute Maximum Ratings table. Figure 35 shows how a series input resistor is added to
the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and
the value must be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA maximum
Device
VOUT
VIN
5 kW
Figure 35. Input Current Protection
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11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of op amp
itself. Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the
analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise
pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the
ground current. For more detailed information, see Circuit Board Layout Techniques.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much
better as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Figure 37, keeping RF
and RG close to the inverting input minimizes parasitic capacitance on the inverting input.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is
recommended to remove moisture introduced into the device packaging during the cleaning process. A
low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
11.2 Layout Example
+
VIN A
+
VIN B
VOUT A
RG
VOUT B
RG
RF
RF
Figure 36. Schematic Representation for Figure 37
Place components
close to device and to
each other to reduce
parasitic errors.
OUT A
VS+
OUT A
V+
-IN A
OUT B
+IN A
-IN B
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
GND
RF
OUT B
GND
RF
RG
VIN A
GND
RG
V±
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
GND
VS±
+IN B
Ground (GND) plane on another layer
VIN B
Keep input traces short
and run the input traces
as far away from
the supply lines
as possible.
Figure 37. Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Circuit Board Layout Techniques, SLOA089
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 1. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
MCP6291
Click here
Click here
Click here
Click here
Click here
MCP6292
Click here
Click here
Click here
Click here
Click here
MCP6294
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
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PACKAGE OPTION ADDENDUM
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11-Oct-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MCP6291IDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
1U3F
MCP6291IDCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
1EL
MCP6292IDDFR
ACTIVE
SOT-23-THIN
DDF
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
M292
MCP6292IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
M292
MCP6292IDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
M292
MCP6292IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
MC6292
MCP6294IDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
MCP6294D
MCP6294IPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
MCP6294
MCP6294IPWT
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
MCP6294
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
11-Oct-2019
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
MCP6291IDBVR
SOT-23
DBV
5
3000
180.0
8.4
MCP6291IDCKR
SC70
DCK
5
3000
178.0
MCP6292IDDFR
SOT23-THIN
DDF
8
3000
180.0
MCP6292IDGKR
VSSOP
DGK
8
2500
MCP6292IDGKT
VSSOP
DGK
8
MCP6292IDR
SOIC
D
8
MCP6294IDR
SOIC
D
14
MCP6294IPWR
TSSOP
PW
MCP6294IPWT
TSSOP
PW
3.2
3.2
1.4
4.0
8.0
Q3
9.0
2.4
2.5
1.2
4.0
8.0
Q3
8.4
3.2
3.2
1.4
4.0
8.0
Q3
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
250
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
2500
330.0
15.4
6.4
5.2
2.1
8.0
12.0
Q1
2500
330.0
15.4
6.4
5.2
2.1
8.0
12.0
Q1
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
14
250
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MCP6291IDBVR
SOT-23
DBV
5
3000
210.0
185.0
35.0
MCP6291IDCKR
SC70
DCK
5
3000
190.0
190.0
30.0
MCP6292IDDFR
SOT-23-THIN
DDF
8
3000
210.0
185.0
35.0
MCP6292IDGKR
VSSOP
DGK
8
2500
366.0
364.0
50.0
MCP6292IDGKT
VSSOP
DGK
8
250
366.0
364.0
50.0
MCP6292IDR
SOIC
D
8
2500
333.2
345.9
28.6
MCP6294IDR
SOIC
D
14
2500
336.6
336.6
41.3
MCP6294IPWR
TSSOP
PW
14
2000
366.0
364.0
50.0
MCP6294IPWT
TSSOP
PW
14
250
366.0
364.0
50.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE
C
2.95
TYP
2.65
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
8
1
6X 0.65
2.95
2.85
NOTE 3
2X
1.95
4
5
B
1.65
1.55
8X
0.4
0.2
0.1
C A
B
1.1 MAX
0.20
TYP
0.08
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.6
0.3
0.1
0.0
DETAIL A
TYPICAL
4222047/B 11/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/B 11/2015
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/B 11/2015
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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