Texas Instruments | OPA2834 50-MHz, 170-µA, Negative-Rail In, Rail-to-Rail Out, Voltage-Feedback Amplifier (Rev. A) | Datasheet | Texas Instruments OPA2834 50-MHz, 170-µA, Negative-Rail In, Rail-to-Rail Out, Voltage-Feedback Amplifier (Rev. A) Datasheet

Texas Instruments OPA2834 50-MHz, 170-µA, Negative-Rail In, Rail-to-Rail Out, Voltage-Feedback Amplifier (Rev. A) Datasheet
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OPA2834
SBOS973A – JUNE 2019 – REVISED SEPTEMBER 2019
OPA2834 50-MHz, 170-µA, Negative-Rail In, Rail-to-Rail Out, Voltage-Feedback Amplifier
1 Features
3 Description
•
The OPA2834 is a dual-channel, ultra-low-power, railto-rail output, negative-rail input, voltage-feedback
(VFB) operational amplifier designed to operate over
a power-supply range of 2.7 V to 5.4 V with a single
supply, or ±1.35 V to ±2.7 V with a dual supply.
Consuming only 170 µA per channel and with a unitygain bandwidth of 50 MHz, this amplifier sets an
industry-leading performance-to-power ratio for railto-rail amplifiers.
1
•
•
•
•
•
•
•
•
Ultra-low power:
– Supply voltage: 2.7 V to 5.4 V
– Quiescent current (IQ): 170 µA/ch (typical)
Bandwidth: 50 MHz (G = 1 V/V)
Slew rate: 26 V/µs
Settling time (0.1%): 88 ns (2-VSTEP)
HD2, HD3: –131 dBc, –146 dBc at 10 kHz (2 VPP)
Input voltage noise: 12 nV/√Hz (f = 10 kHz)
Input offset voltage: 350 µV (±1.9 mV max)
Negative rail input, rail-to-rail output (RRO)
– Input voltage range: –0.2 V to 3.9 V
(5-V supply)
Operating temperature range:
–40°C to +125°C
2 Applications
•
•
•
•
•
•
Current sensing in power supplies
Low-power signal conditioning
Battery-powered applications
Portable voice recorders
Low-power SAR and ΔΣ ADC driver
Portable devices
For battery-powered and portable applications where
low power consumption is of key importance, the
OPA2834 offers an excellent bandwidth to IQ ratio.
OPA2834 offers very low distortion making it very
suitable for data acquisition systems and microphone
pre-amplifier.
See the Device Comparison Table for a selection of
low-power, low-noise, 5-V amplifiers from Texas
Instruments with a gain-bandwidth product from
20 MHz to 300 MHz.
Device Information(1)
PART NUMBER
PACKAGE
OPA2834
VSSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
1-kHz FFT Plot
(VOUT = 1 VRMS, RL = 100 kΩ, G = 1)
Low-Side, Current-Shunt Monitoring
LOAD
40
RF¶
VS
20
0
±
VS
RG¶
REXT
±
-20
FFT (dBc)
BODY SIZE (NOM)
-40
RSH
+
RG¶
-60
+
-80
RF¶
-100
-120
VREF
-140
OPA2834-2
CEXT
OPA2834-1
Interrupt
ShortCircuit Fault
Detection
+
VTH
TLV3201
±
-160
0
2k
4k
6k
8k 10k 12k
Frequency (Hz)
14k
16k
18k
20k
µC
VS
FFT_
ADS7056
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA2834
SBOS973A – JUNE 2019 – REVISED SEPTEMBER 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
1
1
1
2
3
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics: 3V to 5V........................... 5
Typical Characteristics: Vs = 5 V .............................. 6
Typical Characteristics: VS = 3.0 V ........................... 9
Typical Characteristics: ±2.5-V to ±1.5-V Split
Supply ...................................................................... 12
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagrams ..................................... 15
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 17
9
Application and Implementation ........................ 20
9.1 Application Information............................................ 21
9.2 Typical Applications ................................................ 21
10 Power Supply Recommendations ..................... 25
11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
11.2 Layout Examples................................................... 26
12 Device and Documentation Support ................. 27
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
13 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June 2019) to Revision A
•
2
Page
Changed document status from APL to production data ...................................................................................................... 1
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5 Device Comparison Table
PART NUMBER
CHANNELS
Av = +1 BANDWIDTH
(MHz)
5-V IQ
(mA, Typ 25°C)
INPUT NOISE
VOLTAGE
(nV/√Hz)
OPA2834
2
50
0.17
12
OPA2835
2
56
0.25
9.4
OPA2836
2
205
1.0
4.6
OPA2837
2
105
0.6
OPA838
1
—
0.96
2-VPP THD
(dBc, 100 kHz)
RAIL-TO-RAIL
INPUT/OUTPUT
Single Channel
VS–, output
—
–104
VS–, output
OPA835
–118
VS–, output
OPA836
4.7
–118
VS–, output
OPA837
1.9
–110
VS–, output
—
6 Pin Configuration and Functions
DGK Package
8-Pin VSSOP
Top View
VOUT1
1
VIN1-
2
8
VS+
7
VOUT2
6
VIN2-
5
VIN2+
A
VIN1+
3
B
VS-
4
Pin Functions
PIN
FUNCTION (1)
DESCRIPTION
NO.
NAME
1
VOUT1
O
Amplifier 1 output pin
2
VIN1–
I
Amplifier 1 inverting input pin
3
VIN1+
I
Amplifier 1 noninverting input pin
4
VS–
P
Negative power-supply pin
5
VIN2+
I
Amplifier 2 noninverting input pin
6
VIN2–
I
Amplifier 2 inverting input pin
7
VOUT2
O
Amplifier 2 output pin
8
VS+
P
Positive power-supply input
(1)
I = input, O = output, and P = power.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VS– to VS+
MAX
Supply voltage (total bipolar supplies) (2)
Supply turnon/off maximum dV/dT
VI
Input voltage
VID
Differential input voltage
5.5
(3)
1
VS– – 0.5
Continuous input current
IO
Continuous output current (5)
Continuous power dissipation
V
V/µs
VS+ + 0.5
V
±1
V
±10
mA
±20
mA
(4)
II
UNIT
See Thermal Information
TJ
Maximum junction temperature
150
°C
TA
Operating free-air temperature
–40
125
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
(4)
(5)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
VS is the total supply voltage given by VS = VS+ – VS–.
Staying below this ± supply turnon edge rate prevents the edge-triggered ESD absorption device across the supply pins from turning on.
Continuous input current limit for both the ESD diodes to supply pins and amplifier differential input clamp diodes. The differential input
clamp diodes limit the voltage across them to 1 V with this continuous input current flowing through them.
Long-term continuous current for electromigration limits.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification
JESD22 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
VS+
Single-supply positive voltage
2.7
5
5.4
UNIT
V
TA
Ambient temperature
–40
25
125
°C
7.4 Thermal Information
OPA2834
THERMAL METRIC (1)
DGK (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
192.6
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
79.3
°C/W
Junction-to-board thermal resistance
114.3
°C/W
ΨJT
Junction-to-top characterization parameter
15.7
°C/W
YJB
Junction-to-board characterization parameter
112.6
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics: 3V to 5V
VS = 3 V to 5 V, RF = 0 Ω, CL = 4 pF, RL = 5 kΩ referenced to mid-supply, G = 1 V/V, input and output VCM = mid-supply, and
TA ≈ 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
SSBW
Small-signal bandwidth
GBWP
Gain-bandwidth product
LSBW
Large-signal bandwidth
Bandwidth for 0.1-dB flatness
VO = 20 mVPP, G = 1, < 1 dB peaking
50
VO = 20 mVPP, G = 2, RF = 3.65 kΩ
20
MHz
20
VO = 2 VPP,VS = 5 V
6
VO = 1 VPP, VS = 3 V
9
VO = 200 mVPP, G = 2, RF = 3.65 kΩ
9
VS= 5V, VO = 2–V step, 20% to 80%
26
VS= 3V, VO = 1–V step, 20% to 80%
17
MHz
MHz
MHz
SR
Slew rate
V/µs
tR, tF
Rise, fall time
VO = 200–mV step, input tR = 1 ns
16
Settling time to 0.1%
VO = 2–V step, input tR = 50 ns
88
Settling time to 0.01%
VO = 2–V step, input tR = 50 ns
110
Over/Under Shoot
VO = 2–V step, input tR = 50 ns
0.6
%
Overdrive recovery time
G = 2, 2x output overdrive
240
ns
ns
ns
HD2
Second-order harmonic distortion f = 10 kHz, VO = 2 VPP
–131
HD3
Third-order harmonic distortion
f = 10 kHz, VO = 2 VPP
–143
eN
Input voltage noise
f > 10 kHz , 1/f corner at 150 Hz
12
nV/√Hz
iN
Input current noise
f > 10 kHz , 1/f corner at 900 Hz
0.2
pA/√Hz
Channel-to-channel crosstalk
f = 100 kHz, VO = 2 VPP
dBc
–130
dBc
124
dB
DC PERFORMANCE
AOL
Open-loop voltage gain
VOS
Input-referred offset voltage
Input offset voltage drift
Input bias current
VO = ±1 V
102
0.35
1.9
TA = –40°C to +125°C (1)
0.5
2.1
TA = –40°C to +125°C (1)
1.2
5
50
90
70
115
5
30
TA = –40°C to +125°C (1)
Input offset current
mV
µV/°C
nA
nA
INPUT
VICR
Common-mode input range
CMRR
Common-mode rejection ratio
TA = –40°C to +125°C (1)
VCM = VS- – 0.2V to VS+ – 1.1 V
VS–– 0.2
VS+–1.1
VS–– 0.1
VS+–1.1
86
Common-mode input impedance
104
dB
1050 || 1.1
Differential input impedance
V
MΩ||pF
1 || 0.2
OUTPUT
VOL
Output voltage, low
VOH
Output voltage, high
ZO
Vs–+0.02
Vs+– 0.1
Vs–+0.05
Vs––0.05
Linear output drive
(sourcing/sinking)
VO = ±1 V, ΔVOS < 1 mV , VS = 5 V
16
28
VO = ±1 V, ΔVOS < 1 mV , VS = 3 V
11
13.5
Closed-loop output impedance
G = 1, IOUT = ±5 mA DC
V
mA
1.1
mΩ
POWER SUPPLY
VS
Specified operating voltage
IQ
Quiescent current per amplifier
PSRR
Power-supply rejection ratio
(1)
2.7
TA = –40°C to +125°C (1)
ΔVS = 0.3 V
86
5.4
170
210
220
290
103
V
µA
dB
Based on electrical characterization of 32 devices. Minimum and maximum values are not specified by final automated test equipment
(ATE) nor by QA sample testing. Typical specifications are ±1 sigma.
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7.6 Typical Characteristics: Vs = 5 V
3
3
0
0
Normalized Gain (dB)
Normalized Gain (dB)
VS+ = 5 V, VS– = 0 V, RF = 0 Ω, RL = 5 kΩ, CL = 4 pF, input and output referenced to mid-supply, and TA ≈ 25°C (unless
otherwise noted)
-3
-6
Gain = 1 V/V
Gain = 2 V/V
Gain = 5 V/V
Gain = 10 V/V
-9
0.1
1
10
-6
Gain = -1 V/V
Gain = -2 V/V
Gain = -5 V/V
Gain = -10 V/V
-9
0.1
100
Frequency (MHz)
-3
1
10
100
Frequency (MHz)
D101
VO = 20 mVPP
D102
VO = 20 mVPP
Figure 1. Noninverting Small-Signal Frequency Response
Figure 2. Inverting Small-Signal Frequency Response
3
9
6
0
Gain (dB)
Gain (dB)
3
0
-3
-3
-6
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
VO = 2 VPP
-6
-9
0.1
1
10
-9
0.1
100
Frequency (MHz)
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
VO = 2 VPP
1
Gain = 2 V/V
Figure 3. Noninverting Large-Signal Frequency Response
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
VO = 2 VPP
Figure 4. Inverting Large-Signal Frequency Response
0.3
0.2
0.1
0
-0.1
-0.2
0.2
0.1
0
-0.1
-0.2
-0.3
-0.3
-0.4
-0.4
1
10
Frequency (MHz)
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
VO = 2 VPP
0.4
Normalized Gain (dB)
0.3
Normalized Gain (dB)
D104
0.5
0.4
100
-0.5
0.1
1
10
Frequency (MHz)
D206
Gain = 2 V/V
100
D205
Gain = –1 V/V
Figure 5. Noninverting Large-Signal Response Flatness
6
100
Gain = –1 V/V
0.5
-0.5
0.1
10
Frequency (MHz)
D103
Figure 6. Inverting Large-Signal Response Flatness
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Typical Characteristics: Vs = 5 V (continued)
VS+ = 5 V, VS– = 0 V, RF = 0 Ω, RL = 5 kΩ, CL = 4 pF, input and output referenced to mid-supply, and TA ≈ 25°C (unless
otherwise noted)
1.2
1
1
0.8
0.8
0.6
0.6
Output Voltage (V)
Output Voltage (V)
1.2
0.4
0.2
0
-0.2
-0.4
-0.6
-1
0.2
0
-0.2
-0.4
-0.6
VO = r 0.125 V
VO = r 0.25 V
VO = r 0.5 V
VO = r 1 V
-0.8
0.4
-0.8
-1
-1.2
VO = r 0.125 V
VO = r 0.25 V
VO = r 0.5 V
VO = r 1 V
-1.2
Time (100 ns/div)
Time (100 ns/div)
D303
D304
Gain = 2 V/V
Gain = –1 V/V
Figure 7. Noninverting Step Response
Figure 8. Inverting Step Response
5
5
VIN u 2 Gain
VOUT (AV = 2)
4
3
Input and Output (V)
3
Input and Output (V)
VIN u -2 Gain
VOUT (Av = -2)
4
2
1
0
-1
-2
2
1
0
-1
-2
-3
-3
-4
-4
-5
-5
Time (500 ns/div)
Time (500 ns/div)
D305
D306
Gain = 2 V/V
Gain = –2 V/V
Figure 9. Noninverting Overdrive Recovery
Figure 10. Inverting Overdrive Recovery
-40
Harmonic Distortion (dBc)
-60
-70
-60
HD2 Gain = 1 V/V
HD3 Gain = 1 V/V
HD2 Gain = -1 V/V
HD3 Gain = -1 V/V
HD2, Gain = 1 V/V
HD3, Gain = 1 V/V
HD2, Gain = -1 V/V
HD3, Gain = -1 V/V
-70
Harmonic Distortion (dBc)
-50
-80
-90
-100
-110
-120
-130
-140
-80
-90
-100
-110
-120
-150
-160
100
1k
10k
Frequency (Hz)
100k
1M
-130
100
D110
VO = 2 VPP
1k
RLOAD (:)
10k
D307
VO = 2 VPP, f = 100 kHz
Figure 11. Harmonic Distortion vs Frequency
Figure 12. Harmonic Distortion vs RLOAD
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Typical Characteristics: Vs = 5 V (continued)
-90
-80
-95
-85
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
VS+ = 5 V, VS– = 0 V, RF = 0 Ω, RL = 5 kΩ, CL = 4 pF, input and output referenced to mid-supply, and TA ≈ 25°C (unless
otherwise noted)
-100
-105
-110
-115
-120
HD2, Gain = 2V/V
HD3, Gain = 2V/V
HD2, Gain = -1V/V
HD3, Gain = -1V/V
-125
-130
0.4
-90
-95
-100
-105
-110
HD2, +Gain
HD3, +Gain
HD2, -Gain
HD3, -Gain
-115
-120
-125
0.8
1.2
1.6
2
2.4
2.8
Output Voltage (Vpp)
3.2
3.6
4
1
D111
f = 100 kHz
3
4
5
6
Gain (V/V)
7
8
9
10
D201
VO = 2 VPP, f = 100 kHz
Figure 13. Harmonic Distortion vs Output Voltage
8
2
Figure 14. Harmonic Distortion vs Gain Magnitude
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7.7 Typical Characteristics: VS = 3.0 V
3
3
0
0
Normalized Gain (dB)
Normalized Gain (dB)
VS+ = 3 V, VS– = 0 V, RF = 0 Ω, RL = 5 kΩ, CL = 4 pF, input and output referenced to mid-supply, and TA ≈ 25°C (unless
otherwise noted)
-3
-6
-3
-6
Gain = 1 V/V
Gain = 2 V/V
Gain = 5 V/V
Gain = 10 V/V
-9
0.1
Gain = -1 V/V
Gain = -2 V/V
Gain = -5 V/V
Gain = -10 V/V
-9
0.1
1
10
Frequency (MHz)
1
10
100
Frequency (MHz)
100
D115
VO = 20 mVPP
D114
VO = 20 mVPP
Figure 16. Inverting Small-Signal Frequency Response
3
3
0
0
Normalized Gain (dB)
Normalized Gain (dB)
Figure 15. Noninverting Small-Signal Frequency Response
-3
-6
-3
-6
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
-9
0.1
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
1
10
Frequency (MHz)
-9
0.1
100
1
Gain = 2 V/V
D117
Figure 18. Inverting Large-Signal Bandwidth
0.5
0.5
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
0.4
0.3
0.2
0.1
0
-0.1
-0.2
0.2
0.1
0
-0.1
-0.2
-0.3
-0.3
-0.4
-0.4
1
10
Frequency (MHz)
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
0.4
Normalized Gain (dB)
0.3
Normalized Gain (dB)
100
Gain = –1 V/V
Figure 17. Noninverting Large-Signal Bandwidth
-0.5
0.1
10
Frequency (MHz)
D116
100
-0.5
0.1
1
10
Frequency (MHz)
D207
Gain = 2 V/V
100
D208
Gain = –1 V/V
Figure 19. Noninverting Large-Signal Frequency Response
Flatness
Figure 20. Inverting Large-Signal Frequency Response
Flatness
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Typical Characteristics: VS = 3.0 V (continued)
VS+ = 3 V, VS– = 0 V, RF = 0 Ω, RL = 5 kΩ, CL = 4 pF, input and output referenced to mid-supply, and TA ≈ 25°C (unless
otherwise noted)
0.8
1.2
1
0.6
0.8
0.4
Output Voltage (V)
Output Voltage (V)
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
0.2
0
-0.2
-0.4
VO = r 0.125 V
VO = r 0.25 V
VO = r 0.5 V
-0.8
-1
-0.6
-1.2
VO = r 0.125 V
VO = r 0.25 V
VO = r 0.5 V
-0.8
Time (100 ns/div)
Time (100 ns/div)
D308
D309
Gain = 2 V/V
Gain = –1 V/V
Figure 21. Noninverting Step Response
Figure 22. Inverting Step Response
3
3
VIN u 2 Gain
VOUT (Av = 2)
2
Input and Output (V)
Input and Output (V)
2
VIN u -1 Gain
VOUT (Av = -1)
1
0
-1
1
0
-1
-2
-2
-3
-3
Time (500 ns/div)
Time (500 ns/div)
D310
D311
Gain = –1 V/V
Gain = 2 V/V
Figure 24. Inverting Overdrive Recovery
Figure 23. Noninverting Overdrive Recovery
-60
-60
-80
HD2 Gain1= 1 V/V
HD3 Gain1= 1 V/V
HD2 Gain1= -1 V/V
HD3 Gain1= -1 V/V
-90
-100
-110
-120
-130
-140
-80
-90
-100
-110
-120
-150
-160
100
1k
10k
Frequency (Hz)
100k
1M
-130
100
D122
VO = 1 VPP
1k
RLOAD(:)
10k
D312
VO = 1 VPP, f = 100 kHz
Figure 25. Harmonic Distortion vs Frequency
10
HD2, Gain = 1 V/V
HD3, Gain = 1 V/V
HD2, Gain = -1 V/V
HD3, Gain = -1 V/V
-70
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-70
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Typical Characteristics: VS = 3.0 V (continued)
VS+ = 3 V, VS– = 0 V, RF = 0 Ω, RL = 5 kΩ, CL = 4 pF, input and output referenced to mid-supply, and TA ≈ 25°C (unless
otherwise noted)
-90
-80
-90
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-95
-100
-105
-110
-115
-120
HD2, Gain = 2V/V
HD3, Gain = 2V/V
HD2, Gain = -1V/V
HD3, Gain = -1V/V
-125
-130
0.4
-100
-110
-120
HD2, +Gain
HD3, +Gain
HD2, -Gain
HD3, -Gain
-130
-140
0.6
0.8
Output Voltage (Vpp)
1
1.2
1
2
D123
3
4
5
6
Gain (V/V)
7
8
9
10
D204
f = 100 kHz, VO = 1 VPP
f = 100 kHz
Figure 27. Harmonic Distortion vs Output Voltage
Figure 28. Harmonic Distortion vs Gain Magnitude
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7.8 Typical Characteristics: ±2.5-V to ±1.5-V Split Supply
1
10
100
1k
10k
100k
Frequency (Hz)
1M
60
Gain (dB) 45
Phase (q) 30
15
0
-15
-30
-45
-60
-75
-90
-105
-120
-135
-150
-165
-180
10M 100M
100
10
Output Impedance (:)
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
-10
-20
Open-Loop Phase (q)
Open-Loop Gain (dB)
with PD = VCC and TA ≈ 25°C , gain mentioned in V/V (unless otherwise noted)
1
0.1
10m
1m
0.1m
100
1k
10k
100k
Frequency (Hz)
D313
Figure 29. Open-Loop Gain and Phase vs Frequency
1M
10M
D314
Figure 30. Closed-Loop Output Impedance vs Frequency
120
100
Voltage Noise
Current Noise
CMRR 5V
CMRR 3V
PSRR 5V
PSRR 3V
110
100
Rejection Ratio (dB)
Input Voltage (nV/—Hz) and
Current (pA/—Hz) noise
Gain = 1V/V
Gain = 2V/V
Gain = 5V/V
10
1
90
80
70
60
50
40
30
20
10
0.1
10
100
1k
10k
Frequency (Hz)
100k
0
10
1M
100
D100
1k
10k
100k
Frequency (Hz)
1M
10M
D315
Measured then fit to ideal 1/f model
Figure 31. Input Noise Density vs Frequency
Figure 32. CMRR and PSRR vs Frequency
14k
5V
3V
12k
200
Input Offset Voltage (PV)
No. of Units in Each Bin
300
10k
8k
6k
4k
0
-100
-200
1600
1400
1200
800
1000
600
400
0
200
-200
-400
-600
-800
-1000
-1200
-1400
-1600
2k
Input Offset Voltage (PV)
-300
-50
D151
-25
0
25
50
75
Ambient Temperature (qC)
100
125
D141
32 units at 5-V and 3-V supply, Input offset voltage calibrated to
0V at 25°C
54000 units at each supply voltage
Figure 33. Input Offset Voltage Distribution
12
100
Figure 34. Input Offset Voltage vs Ambient Temperature
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Typical Characteristics: ±2.5-V to ±1.5-V Split Supply (continued)
with PD = VCC and TA ≈ 25°C , gain mentioned in V/V (unless otherwise noted)
20
0
10
Input Bias Current (nA)
input offset current (nA)
-10
0
-10
-20
-30
-40
-50
-60
-70
-20
-50
-25
0
25
50
75
Ambient Temperature (qC)
100
-80
-50
125
32 units at 5-V and 3-V supply
0
25
50
75
Ambient Temperature (qC)
100
125
D153
32 units at 5-V and 3-V supply
Figure 35. Input Offset Current vs Ambient Temperature
Figure 36. Input Bias Current vs Ambient Temperature
240
40
35
220
30
Supply Current (PA)
No. of Units in Each Bin
-25
D154
25
20
15
200
180
160
10
140
5
120
-50
3
2
2.5
1
1.5
0
0.5
-1
-0.5
-1.5
-2
-2.5
-3
0
Input Offset Voltage Drift PV/qC
D142
0
25
50
75
Ambient Temperature (qC)
100
125
D150
32 units at 5-V and 3-V supply
136 units, –40°C to +125°C
Figure 38. Supply Current vs Ambient Temperature
Figure 37. Input Offset Voltage Drift Distribution
200
9
Gain=1V/V
Gain=2V/V
Gain=5V/V
Gain=10V/V
160
6
3
Normalized Gain (dB)
180
140
RO (:)
-25
120
100
80
60
0
-3
-6
-9
-12
40
-15
20
-18
0
1
10
100
CL (pF)
1000
10000
-21
0.01
D301
See Figure 49,
Recommended value of RO for targeting 30° phase margin
Figure 39. Output Resistor (RO) vs CL
G=1 CL=1nF RO=70:
G=1 CL=0.1nF RO=170:
G=2 CL=1nF RO=55:
G=2 CL=0.1nF RO=110:
G=5 CL=1nF RO=25:
G=5 CL=0.1nF RO=0:
G=10 CL=1nF RO=0:
G=10 CL=0.1nF RO=0:
0.1
1
Frequency (MHz)
10
100
D302
See Figure 49
Figure 40. Small-Signal Frequency Response vs CL
With Recommended RO
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Typical Characteristics: ±2.5-V to ±1.5-V Split Supply (continued)
with PD = VCC and TA ≈ 25°C , gain mentioned in V/V (unless otherwise noted)
3
2.5
1.5
Input Offset Voltage (mV)
Output Voltage Swing (V)
2
1.5
1
0.5
r 2.5 VOH
r 2.5 VOL
r 1.5 VOH
r 1.5 VOL
0
-0.5
-1
-1.5
-2
1
0.5
0
-0.5
-1
-1.5
-2.5
-3
100
1k
RLOAD (:)
-2
-3
10k
D316
-2.4
-1.8 -1.2 -0.6
0
0.6 1.2 1.8
Input Common-mode Voltage (V)
2.4
3
D317
32 units at 5-V and 3-V supplies
Figure 41. Output Voltage Swing vs Load Resistor
Figure 42. Input Offset Voltage vs Input Common-Mode
Voltage
5k
-40
-50
Ch A to Ch B
Ch B to Ch A
4k
No. of units in Each Bin
Crosstalk (dBc)
-60
-70
-80
-90
-100
-110
3k
2k
1k
-120
14
2.6
2.2
1.8
1
1.4
0.6
0.2
-0.2
-1
D300
Input offset mismatch between channels (mV)
D107
Figure 43. Crosstalk vs Frequency
-0.6
100
-1.4
10
Frequency (MHz)
-1.8
1
-2.2
-140
0.1
-2.6
-130
Figure 44. Input Offset Mismatch (Between Channel A and
Channel B) Distribution
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8 Detailed Description
8.1 Overview
The OPA2834 bipolar input operational amplifier offers an unity-gain bandwidth of 50 MHz with ultra-low HD2
and HD3 as shown in the Electrical Characteristics: 3V to 5V. The device can swing to within 100 mV of the
supply rails while driving a 5-kΩ load. The input common-mode voltage of the amplifier can swing to 200 mV
below the negative supply rail. This level of performance is achieved at 170 µA of quiescent current per amplifier
channel.
8.2 Functional Block Diagrams
VSIG
VREF
VS+
VIN
RG
½ OPA2834
VOUT
+
±
VS-
VREF
Gain × VSIG
VREF
RF
Figure 45. Noninverting Amplifier
VREF
VS+
VREF
VIN
Gain × VSIG
VS-
VREF
RF
Figure 46. Inverting Amplifier
8.3 Feature Description
8.3.1 Input Common-Mode Voltage Range
When the primary design goal is a linear amplifier circuit with high CMRR, it is important to not violate the input
common-mode voltage range (VICR) of the op amp. The typical specifications for this device are 0.2 V below the
negative rail and 1.1 V below the positive rail.
Assuming the op amp is in linear operation, the voltage difference between the input pins is small (ideally 0 V);
and the input common-mode voltage is analyzed at either input pin with the other input pin assumed to be at the
same potential. The voltage at VIN+ is simple to evaluate. In a noninverting configuration, as shown in Figure 45,
the input signal, VIN, must not violate the VICR for this operation. In an inverting configuration, as shown in
Figure 46, the reference voltage, VREF, must be within the VICR. Assuming VREF is within VICR, the amplifier is
always in the linear operation range irrespective of the amplitude of the input signal VIN.
The input voltage limits have fixed headroom to the power rails and track the power-supply voltages. For a 5-V
supply, the linear input voltage ranges from –0.2 V to 3.9 V and –0.2 V to 1.6 V for a 2.7-V supply. The delta
headroom from each power-supply rail is the same in either case: –0.2 V and 1.1 V.
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Feature Description (continued)
8.3.2 Output Voltage Range
The OPA2834 is a rail-to-rail output (RRO) op amp. Rail-to-rail output typically means that the output voltage
swings within a couple hundred millivolts of the supply rails. There are different ways to specify this parameter,
one is with the output still in linear operation and another is with the output saturated. Saturated output voltages
are closer to the power-supply rails than linear outputs, but the signal is not a linear representation of the input.
Linear output is a better representation of how well a device performs when used as a linear amplifier. Saturation
and linear operation limits are affected by the output current, where higher currents lead to lower headroom from
either of the output rails.
The Electrical Characteristics: 3V to 5V list the saturated output voltage specifications with a 5-kΩ load. Given a
light load, the output voltage limits have nearly constant headroom to the power rails and track the power-supply
voltages. For example, with a 5-kΩ load and a single 5-V supply, the saturation output voltage ranges from 0.1 V
to 4.95 V and ranges from 0.1 V to 2.65 V for a 2.7-V supply.Figure 41 illustrates the saturated voltage-swing
limits versus output load resistance.
With a device such as the OPA2834, where the input range is lower than the output range, typically the input
limits the available signal swing only in a noninverting gain of 1. Signal swing in noninverting configurations in
gains greater than +1 and inverting configurations in any gain is typically limited by the output voltage limits of
the op amp.
8.3.3 Low-Power Applications and the Effects of Resistor Values on Bandwidth
Choosing the right value of feedback resistor (RF) gives the lowest operating current, maximum bandwidth,
lowest DC error, and the best pulse response. In this section for simplicity, the main focus of the signal chain
design is assumed to be the total operating current. The feedback resistor used to set the gain value invariably
loads the amplifier. For example, in a gain of 2 with RF = RG = 3.6 kΩ (see Figure 48) and VOUT = 4 V (assumed),
555 µA of current flows through the feedback path to ground. However, using a 3.6-kΩ resistor may not be
practical in low-power applications.
In low-power applications, there is a tendency to reduce the current consumed by the amplifier by increasing the
gain-setting resistor values in the feedback path. Using larger value gain resistors has two primary side effects
(other than lower power), because of the interaction of the resistors with parasitic circuit capacitance. These
large-value resistors:
• Lower the bandwidth as a result of the interaction with the parasitic capacitor
• Lower the phase margin by causing
– Peaking in the frequency response
– Overshoot and ringing in the pulse response
Figure 47 shows the small-signal frequency response for a noninverting gain of 2 with RF and RG equal to 2 kΩ,
5 kΩ, 10 kΩ, and 100 kΩ. The test was done with RL = 5 kΩ. Peaking reduces with lower values of RL.
15
12
Closed-Loop Gain (dB)
9
6
3
0
-3
-6
-9
-12
-15
-18
100k
RF = 2 k:
RF = 5 k:
RF = 10 k:
RF = 100 k:
1M
10M
Frequency (Hz)
100M
D401
Figure 47. Frequency Response With Various Gain-Setting Resistor Values
As expected, larger value gain resistors result in gain peaking in the frequency response plots (peaking in the
frequency response is synonymous with the reduced phase margin).
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Feature Description (continued)
However, there is a simple way to get the best of both worlds. An ideal application requires a high value of RF for
a particular gain to reduce the operating current but be limited by the reduced phase margin from the interaction
of RF and CIN. The trick is simple: adding a capacitor in parallel with RF helps compensate the phase margin and
restores the flat frequency response (avoids gain peaking). The value of C chosen must be such that RF × CF =
CIN × RG. CIN for the OPA2834 is 1.1 pF. This value of CIN is listed in the Electrical Characteristics: 3V to 5V
table as common-mode input impedance. For the case discussed here with a Gain = 2, RF = RG = 3.6 kΩ, , CIN =
1.1 pF, using a CF equal to 1 pF is sufficient to reduce the gain peaking. Using a CF equal to 1 pF enables users
to increase the values of RF and RG to much higher values beyond 3.6 kΩ to reduce the operational current
consumed by the amplifier.
CIN
Figure 48 shows the test circuit.
VIN
+
½ OPA2834
RG
VOUT
±
5k
CIN
RF
CF
Figure 48. G = 2 Test Circuit for Various Gain-Setting Resistor Values
8.3.4 Driving Capacitive Loads
The OPA2834 drives up to a nominal capacitive load of 10 pF on the output with no special consideration and
without the need of RO. When driving capacitive loads greater than 10 pF, TI recommends using a small resistor
(RO) in series with the output as close to the device as possible. Without RO, output capacitance interacts with
the output impedance (ZO) of the amplifier causing phase shift in the feedback loop of the amplifier reducing the
phase margin. This reduction in the phase margin causes peaking in the frequency response and overshoot and
ringing in the pulse response. Interaction with other parasitic elements can lead to further instability or ringing.
Inserting RO isolates the phase shift from the loop gain path and restores the phase margin; however RO can
limit the bandwidth slightly. Figure 49 shows a diagram of driving capacitive loads.
Figure 39 shows the test circuit and shows the recommended values of RO versus capacitive loads, CL. See
Figure 40 for the frequency responses with various optimized values of RO with CL.
VIN
+
½ O PA283 4 R
O
VOUT
±
CL
5k
Figure 49. Driving Capacitive Loads With the OPA2834
8.4 Device Functional Modes
8.4.1 Split-Supply Operation (±1.35 V to ±2.7 V)
To facilitate testing with common lab equipment, the OPA2834EVM (see the OPA2837DGK Evaluation Module
user guide) is built to allow split-supply operation. This configuration eases lab testing because the mid-point
between the power rails is ground, and most signal generators, network analyzers, oscilloscopes, spectrum
analyzers, and other lab equipment have inputs and outputs with a ground reference.
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Device Functional Modes (continued)
Figure 50 shows a simple noninverting configuration analogous to Figure 45 with a ±2.5-V supply and the
reference voltage (VREF) equal to ground. The input and output swing symmetrically around ground. For ease of
use, split supplies are preferred in systems where signals swing around ground.
+2.5 V
RG
½ OPA2834
+
VOUT
±
VSIG
-2.5 V
Load
RF
Figure 50. Split-Supply Operation
8.4.2 Single-Supply Operation (2.7 V to 5.4 V)
Often, newer systems use a single power supply to improve efficiency and reduce the cost of the power supply.
The OPA2834 is designed for use with single-supply power operation and can be used with single-supply power
with no change in performance from split supply, as long as the input and output are biased within the linear
operation of the device.
To change the circuit from split-supply to single-supply, level shift all voltages by half the difference between the
power-supply rails. For example, Figure 51 shows changing from a ±2.5-V split supply to a 5-V single supply.
5V
RG
½ OPA2834
+
VOUT
±
VSIG
Load
RF
+
2.5 V
Figure 51. Single-Supply Concept
A practical circuit has an amplifier or some other circuit providing the bias voltage for the input, and the output of
this amplifier stage provides the bias for the next stage.
Figure 52 shows a typical noninverting amplifier circuit. With a 5-V single-supply, a mid-supply reference
generator is needed to bias the negative side through RG. To cancel the voltage offset that is otherwise caused
by the input bias currents, R1 is selected to be equal to RF in parallel with RG. For example, if a gain of 2 is
required and RF = 3.6 kΩ, select RG = 3.6 kΩ to set the gain, and R1 = 1.8 kΩ for bias current cancellation. The
value for C is dependent on the reference, and TI recommends a value of at least 0.1 µF to limit noise.
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Device Functional Modes (continued)
Signal and bias from
previous stage
VSIG
2.5 V
5V
R1
+
½ OPA2834 RO
VOUT
±
5V
RG
2.5 V
REF
Gain × VSIG
2.5 V
C
Signal and bias to
next stage
RF
Figure 52. Noninverting Single-Supply Operation With Reference
Figure 53 illustrates a similar noninverting single-supply scenario with the reference generator replaced by the
Thevenin equivalent using resistors and the positive supply. RG’ and RG” form a resistor divider from the 5-V
supply and are used to bias the negative side with the parallel sum equal to the equivalent RG to set the gain. To
cancel the voltage offset that is otherwise caused by the input bias currents, R1 is selected to be equal to RF in
parallel with RG’ in parallel with RG” (R1= RF || RG’ || RG”). For example, if a gain of 2 is required and RF = 3.6 kΩ,
selecting RG’ = RG” = 7.2 kΩ gives an equivalent parallel sum of 3.6 kΩ, sets the gain to 2, and references the
input to mid supply (2.5 V). R1 is set to 1.8 kΩ for bias current cancellation. The resistor divider costs less than
the 2.5-V reference in Figure 53 but can increase the current from the 5-V supply.
Signal and bias from
previous stage
VSIG
2.5 V
5V
R1
+
½ OPA2834 RO
RG¶
VOUT
±
5V
Gain × VSIG
RG´
2.5 V
RF
Signal and bias to
next stage
Figure 53. Noninverting Single-Supply Operation With Resistors
Figure 54 shows a typical inverting-amplifier circuit. With a 5-V single-supply, a mid-supply reference generator is
needed to bias the positive side through R1. To cancel the voltage offset that is otherwise caused by the input
bias currents, R1 is selected to be equal to RF in parallel with RG. For example, if a gain of –2 is required and RF
= 3.6 kΩ, select RG = 1.8 kΩ to set the gain and R1 = 1.2 kΩ for bias current cancellation. The value for C is
dependent on the reference, but TI recommends a value of at least 0.1 µF to limit noise into the op amp.
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Device Functional Modes (continued)
5V
5V
R1
2.5 V
REF
½ OPA2834 RO
+
C
VOUT
±
Gain × VSIG
2.5 V
RG
RF
VSIG
Signal and bias to
next stage
2.5 V
Signal and bias from
previous stage
Figure 54. Inverting Single-Supply Operation With Reference
Figure 55 illustrates a similar inverting single-supply scenario with the reference generator replaced by the
Thevenin equivalent using resistors and the positive supply. R1 and R2 form a resistor divider from the 5-V supply
and are used to bias the positive side. To cancel the voltage offset that is otherwise caused by the input bias
currents, set the parallel sum of R1 and R2 equal to the parallel sum of RF and RG. C must be added to limit the
coupling of noise into the positive input. For example, if a gain of –2 is required and RF = 3.6 kΩ, select RG =
1.8 kΩ to set the gain. R1 = R2 = 2.4 kΩ for the mid-supply voltage bias and for op-amp input-bias current
cancellation. A good value for C is 0.1 µF. The resistor divider costs less than the 2.5-V reference in Figure 55
but can increase the current from the 5-V supply.
5V
5V
R1
+
½ OPA2834 RO
VOUT
C
R2
±
Gain × VSIG
2.5 V
RG
VSIG
RF
Signal and bias to
next stage
2.5 V
Signal and bias from
previous stage
Figure 55. Inverting Single-Supply Operation With Resistors
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
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9.1 Application Information
9.1.1 Noninverting Amplifier
The OPA2834 can be used as a noninverting amplifier with a signal input to the noninverting input, VIN+.
Figure 45 illustrates a basic block diagram of the circuit.
The amplifier output can be calculated according to Equation 1 if VIN = VREF + VSIG.
æ
RF ö
V
= VSIG ç 1 +
÷ + VREF
OUT
R
G ø
è
(1)
RF
R
G , and VREF provides a reference around which the input and
The signal gain of the circuit is set by
output signals swing. Output signals are in-phase with the input signals.
G= 1 +
The OPA2834 is designed for the nominal value of RF to be 3.6 kΩ in gains other than +1. This value gives
excellent distortion performance, maximum bandwidth, best flatness, and best pulse response. RF = 3.6 kΩ must
be used as a default unless other design goals require changing to other values. All test circuits used to collect
data for this document have RF = 3.6 kΩ for all gains other than +1. A gain of +1 is a special case where RF is
shorted and RG is left open.
9.1.2 Inverting Amplifier
The OPA2834 can be used as an inverting amplifier with a signal input to the inverting input, VIN–, through the
gain-setting resistor RG. Figure 46 illustrates a basic block diagram of the circuit.
The output of the amplifier can be calculated according to Equation 2 if VIN = VREF + VSIG.
æ -R
VOUT = VSIG ç F
è RG
ö
÷ + VREF
ø
(2)
G=
-RF
RG and V
The signal gain of the circuit is given by
REF provides a reference point around which the input
and output signals swing. Output signals are 180˚ out-of-phase with the input signals. The nominal value of RF
must be 3.6 kΩ for inverting gains.
9.2 Typical Applications
9.2.1 Low-Side Current Sensing
Power stages use current feedback for phase current control and regulation. One of the commonly used methods
for this current measurement is low-side current shunt monitoring. Figure 56 shows a representative schematic of
such a system. The use of the OPA2834 is described in this section for a low-side, current-shunt monitoring
application.
VTH
LOAD
±
10 NŸ
3.3V
5V
5V
500 Ÿ
15 APP
10 PŸ 500 Ÿ
ShortCircuit Fault
Detection
+
±
±
OPA2834-2
OPA2834-1
+
ADS7056
90 Ÿ
470 pF
+
10 NŸ
VREF =1.24V
Figure 56. Low-Side Current Sensing
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Typical Applications (continued)
9.2.1.1 Design Requirements
The OPA2834 is used in a gain of 20 V/V followed by an OPA2834 used in a gain of 1 V/V for driving the input of
the ADS7056 which is sampling at 1 MSPS. A comparator is connected to the ADC input for short-circuit fault
detection. This design example is illustrated for the following specifications:
• Switching frequency: 50 kHz
• Shunt resistance: 10 mΩ
• Load current: 15 APP
• Output voltage: 3.0 VPP
• Amplifier supply voltage: 5 V
• Data Acquisition: 1 MSPS with 0.1% accuracy
• Input spikes due to inductive kickbacks from the power plane: 10 V
9.2.1.2 Detailed Design Procedure
One of the channels of the OPA2834 is connected to the shunt resistor in Figure 56 in a 20-V/V difference
amplifier configuration. Equation 3 gives the gain of this circuit. A well-known way to start the design of this signal
chain is to start from fixating the value of RG.
VOUT
§ RF ·
¨
¸ V2 V1
© RG ¹
where
•
RF and RG are the feedback and gain resistors for channel A of the OPA2834
(3)
The values of RF and RG depend on multiple factors. Using small resistors in the feedback network helps reduce
output noise and improves measurement accuracy. Small feedback resistors result in larger power dissipation in
the amplifier output stage. In order to reduce this power dissipation, large-value resistors reduce the phase
margin and cause gain peaking; see Figure 47. Select the values of RF and RG from the recommended range of
values for this device. As given in Equation 4, care must be taken to use a gain-resistor value large enough to
limit the current through the input ESD diodes to within 10 mA for a 10-V input transient (as per the design
targets) with the amplifier powered off a 5-V supply.
VIN VD VS
I D , Max
RG
where
•
•
•
VIN is the input transient voltage
VD is the ESD diode forward voltage drop
ID is the current resulting from this input transient flowing through the ESD diode
(4)
A total gain of 20 V/V is required from the amplifier signal chain. We have chosen RG = 500 Ω in this design, thus
RF = 10 kΩ. A SAR ADC features a sampling capacitor at the input pin. At the end of every conversion cycle, the
circuit driving this SAR ADC needs to replenish this capacitor. Using the analog calculator, the required
bandwidth for the amplifier to drive the ADS7056 ( sampling rate of 1MSPS and a clock frequency of 40 MHz )
comes out to be at least 5 MHz. Because of this requirement, the two amplifier channels are configured in gains
of 20 V/V and 1 V/V, respectively. The effective bandwidth of the amplifier set in a gain on 20 V/V comes out to
be 20MHz/20 = 1MHz. The bandwidth of the second amplifier set in a gain of 1V/V , equals 50MHz. Thus the
rise time and the settling time of the entire signal chain is decided by the first amplifier. Using an amplifier in the
first stage of any lower bandwidth will result in a penalty in the settling time on the ADC. The 1.24-V reference
voltage to the noninverting input of channel 1 sets the output common-mode voltage to 1.24 V. The two channels
of the OPA2834 together provide a signal gain of 20 V/V. The first Amplifier's bandwidth is dedicated to gaining
up the signal with a very low rise time whereas the function of the second amplifier is to utilize its bandwidth to
drive the SAR ADC to achieve the required settling.
22
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Typical Applications (continued)
The ADS7056 samples at 1 MSPS with a 40-MHz clock which translates to an acquisition time of 550 nsec. This
provides the dual amplifier 550 nsec to settle to the required accuracy. In this application, we target an accuracy
of 0.1%. As the ADC is powered from a 3.3 V supply we have assumed the full scale to be 3 V.
0.1
0.5
0.08
0.4
0.06
0.3
0.04
0.2
0.02
0.1
0
0
-0.02
-0.1
-0.04
-0.2
-0.06
-0.3
Input
% error
-0.4
Output/20
-0.5
-0.08
-0.1
% Error
INput and output voltage (V)
An accuracy of 0.1% of 3 V = 3 mV. Thus the second OPA2834 should settle to ±3 mV of its final intended value
within 550 nsec. Figure 57 shows the TINA simulation plots for the OPA2834 driving the ADS7056. Input voltage
(red) is the signal swing across the shunt resistance, the error signal is the % error in the voltage across the
sampling capacitor from its steady-state value (instantaneous value - final value). The input signal sharply
transits from its lowermost point to the uppermost point at 600 nsec instant. This can be considered as a short
circuit event or step increase due to a mosfet switching in real-world circuits. This acquisition window of the ADC
as discussed earlier is 550 nsec. The details on how this time is decided by the ADC can be found from the
ADS7056 datasheet. Thus the % error signal (blue) must settle down to less than 0.1 % before the end of this
550 nsec window. The output signal (black) is divided by 20 V/V so as to be shown beside its corresponding
input signal. As per Figure 57 the error signal comfortably settles to the final value with an error % of -0.05%
which is well within the 0.1% accuracy. Hence the dual OPA2834 settles to 0.1% accuracy within 550 ns with a
worst-case, 0 to 3-V full-scale transient output that too in a gain configuration of 20 V/V as shown in the
Figure 57. OPA2834 enables single sample settling for ADS7056 running at 40 MHz clock with 1 MSPS.
Time ( 600 nsec/div)
sett
Figure 57. OPA2834 Settling Performance With the ADS7056
Another way to look at the signal chain is using the SNR and THD numbers. A 2 kHz tone is input to the first
OPA2834 shown in Figure 56. This signal is gained up by 20 V/V and fed to the ADS7056. The results are
compared to the specifications given in the ADS7056 datasheet.
Table 1. OPA2834 based signal-chain comparison
Parameter
OPA2834 + ADS7056
Ideal Opamp + ADS7056
12.16
ENOB
11.2
SNR (dB)
69.3
75.15
THD (dB)
-87.89
-90.13
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Using a slower clock with the ADC and the same sampling rate causes the ENOB to reduce as the amplifier has
reduced time available to settle. This reduction in ENOB is restored with a lower sampling frequency or use of
wider bandwidth amplifiers from the OPA83x family of products.
9.2.2 Field Transmitter Sensor Interface
XTR117
VREG
5V
Regulator
OPA2834-1
Sensor
µC
OPA2834-2
IRET
Figure 58. Field Transmitter Sensor Interface Block Diagram
9.2.3 Ultrasonic Flow Meters
Figure 59. Ultrasonic Flow Meters Gain Stage
9.2.4 Microphone Pre-Amplifier
5V
Electret
Microphone
3.3V
C1
0.1 F
0.1 F
R3
100
OPA2834
+
Microphone
Cable
Output
R1
5.9 k
R2
100 k
C2
10 nF
±
0.1 F
-1.8 V
C3
1 F
R4 100 k
R5 1.1 k
R6 100
C4 6.8 nF
Figure 60. Low-Power Microphone Pre-Amplifier
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Figure 60 shows an example circuit of the audio pre-amplifier application using OPA2834. The excellent
distortion performance and the ultra-low quiescent current, make OPA2834 a very attractive solution for the
portable and handheld audio instruments. Figure 60 circuit is a bandpass filter with frequency cutoff at 5 Hz and
180 kHz. The OPA2834 is connected to a positive 3.3 V and a negative 1.8 V supply. the primary reason for the
skew in the power supply is to enable the maximum dynamic range possible to the user. The VICR of OPA2834
mentioned in Electrical Characteristics: 3V to 5V is 1.1 V from the positive rail. Thus having a skewed power
supply like in Figure 60 gives a common-mode input range from -2 V up to 2.2 V.
180
Gain
Phase
Gain (dB)
30
120
20
60
10
0
0
-60
-10
-20
100m
Phase (q)
40
-120
1
10
100
1k
10k 100k
Frequency (Hz)
1M
-180
10M 100M
freq
Figure 61. Frequency Response of Microphone Pre-Amplifier
10 Power Supply Recommendations
The OPA2834 is intended to work in a nominal supply range of 3.0 V to 5.0 V. Supply-voltage tolerances are
supported with the specified operating range of 2.7 V (–10% on a 3-V supply) and 5.4 V (8% on a 5-V supply).
Good power-supply bypassing is required. Minimize the distance (< 0.1 inch) from the power-supply pins to highfrequency, 0.1-µF decoupling capacitors. A larger capacitor (2.2 µF is typical) is used along with a highfrequency, 0.1-µF, supply-decoupling capacitor at the device supply pins. For single-supply operation, only the
positive supply has these capacitors. When a split supply is used, use these capacitors for each supply to
ground. If necessary, place the larger capacitors further from the device and share these capacitors among
several devices in the same area of the printed circuit board (PCB). Avoid narrow power and ground traces to
minimize inductance between the pins and the decoupling capacitors. An optional supply decoupling capacitor
across the two power supplies (for bipolar operation) reduces second-order harmonic distortion.
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11 Layout
11.1 Layout Guidelines
The OPA2837EVM can be used as a reference when designing the circuit board. TI recommends following the
EVM layout of the external components near to the amplifier, ground plane construction, and power routing as
closely as possible. Follow these general guidelines:
1. Signal routing must be direct and as short as possible into and out of the op amp.
2. The feedback path must be short and direct avoiding vias if possible, especially with G = 1 V/V.
3. Ground or power planes must be removed from directly under the negative input and output pins of the
amplifier.
4. TI recommends placing a series output resistor as close to the output pin as possible.
5. See Figure 40 for recommended values for the expected capacitive load. These values are derived targeting
a 30° phase margin to the output of the op amp.
6. A 2.2-µF power-supply decoupling capacitor must be placed within two inches of the device and can be
shared with other op amps. For split supply, a capacitor is required for both supplies.
7. A 0.1-µF power-supply decoupling capacitor must be placed as close to the supply pins as possible,
preferably within 0.1 inch. For split supply, a capacitor is required for both supplies.
11.2 Layout Examples
C6 and C8 bypass capacitors
placed close to th e d evi ce
supply pins.
Figure 62. EVM Layout Top Layer
GND a nd p ower planes removed
und er the device pins in ord er to
minimize p arasitic ca pacita nce on
the sen sitive i nput an d o utp ut nod es.
Figure 63. EVM Layout Bottom Layer
26
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, OPA2837DGK Evaluation Module user guide
• Texas Instruments, ADS7046 12-Bit, 3-MSPS, Single-Ended Input, Small-Size, Low-Power SAR ADC data
sheet
• Texas Instruments, Single-Supply Op Amp Design Techniques application report
• Texas Instruments, Noise Analysis for High-Speed Op Amps application report
• Texas Instruments, TIDA-01565 Wired OR MUX and PGA Reference Design design guide
• Texas Instruments, TINA model and simulation tool
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA2834IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
2834
OPA2834IDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
2834
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Dec-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
OPA2834IDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2834IDGKT
VSSOP
DGK
8
250
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2834IDGKR
VSSOP
DGK
8
2500
366.0
364.0
50.0
OPA2834IDGKT
VSSOP
DGK
8
250
366.0
364.0
50.0
Pack Materials-Page 2
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