Texas Instruments | OPA1656 Ultra-Low-Noise, Low-Distortion, FET-Input, Burr-BrownTM Audio Operational Amplifier (Rev. A) | Datasheet | Texas Instruments OPA1656 Ultra-Low-Noise, Low-Distortion, FET-Input, Burr-BrownTM Audio Operational Amplifier (Rev. A) Datasheet

Texas Instruments OPA1656 Ultra-Low-Noise, Low-Distortion, FET-Input, Burr-BrownTM Audio Operational Amplifier (Rev. A) Datasheet
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OPA1656
SBOS901A – MARCH 2019 – REVISED JULY 2019
OPA1656 Ultra-Low-Noise, Low-Distortion, FET-Input, Burr-BrownTM
Audio Operational Amplifier
1 Features
3 Description
•
The OPA1656 is a Burr-Brown™ operational amplifier
(op amp) designed specifically for audio and industrial
applications, where maintaining signal fidelity is
crucial. The FET-input architecture achieves a low
2.9-nV/√Hz voltage noise density and 6-fA/√Hz
current noise density, allowing for very low noise
performance in a wide variety of circuits. The high
bandwidth and high open-loop-gain design of the
OPA1656 delivers a low distortion of 0.000035%
(–129 dB) at 20 kHz, and improves audio signal
fidelity across the full audio bandwidth. This device
also features excellent output current drive capability,
offering rail-to-rail output swing to within 250 mV of
the power supplies with a 2-kΩ load, and can deliver
100 mA of output current.
•
•
•
•
•
•
•
•
•
Ultra-low noise:
– Voltage noise: 2.9 nV/√Hz at 10 kHz
– Current noise: 6 fA/√Hz at 1 kHz
Low distortion:
– 0.000029% (–131 dB) at 1 kHz
– 0.000035% (–129 dB) at 20 kHz
High open-loop gain: 150 dB
High output current: 100 mA
Low input bias current: 10 pA
Slew rate: 24 V/μs
Gain bandwidth product: 53 MHz
Rail-to-rail output
Wide supply range:
±2.25 V to ±18 V or 4.5 V to 36 V
Quiescent current: 3.9 mA per channel
2 Applications
•
•
•
•
•
•
•
•
•
•
Soundbar
Turntable
DJ controllers, mixers, and other DJ equipment
Professional audio mixer or control surface
High-fidelity D/A converter
Guitar effects pedal
Guitar amplifier and other music instrument
amplifier
Professional microphones and wireless systems
Headset and headphones
Vibration analysis
Active Baxandall Tone Control
Pad
Bass
±
Input
+15
+
Output
±
1/2
OPA1656
+
-15
Treble
1/2
OPA1656
The OPA1656 operates over a very wide supply
range of ±2.25 V to ±18 V or (4.5 V to 36 V) on 3.9
mA of supply current to accommodate the power
supply constraints of many types of audio products.
The temperature range is specified from –40°C to
+125°C. The device is offered in an 8-pin SOIC
package.
Device Information(1)
PART NUMBER
OPA1656
PACKAGE
SOIC (8)
BODY SIZE (NOM)
4.90 mm × 3.91 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Ultra-Low Input Voltage Noise
100
Voltage Noise Density (nV/—Hz)
1
10
1
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
C020
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA1656
SBOS901A – MARCH 2019 – REVISED JULY 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 14
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
14
14
14
17
8
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Applications ................................................ 19
9 Power Supply Recommendations...................... 25
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 26
11 Device and Documentation Support ................. 27
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
28
28
28
28
28
28
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
Changes from Original (March 2019) to Revision A
•
2
Page
Changed device status from advanced information (preview) to production data (active) .................................................... 1
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5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
OUT A
1
8
V+
±IN A
2
7
OUT B
+IN A
3
6
±IN B
V±
4
5
+IN B
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
Inverting input, channel A
+IN A
3
I
Noninverting input, channel A
–IN B
6
I
Inverting input, channel B
+IN B
5
I
Noninverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V–
4
—
Negative (lowest) power supply
V+
8
—
Positive (highest) power supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Voltage
Input (all pins except power-supply pins)
Output short-circuit (2)
(V–) – 0.5
(V+) + 0.5
–10
10
mA
125
°C
150
°C
150
°C
–55
Junction, TJ
Storage, Tstg
(2)
V
V
Continuous
Operating, TA
Temperature
UNIT
40
Input
Current
(1)
MAX
Supply voltage, VS = (V+) – (V–)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.Theseare stress ratings
only, which do not imply functional operation of the device at these oranyother conditions beyond those indicated under
RecommendedOperatingConditions. Exposure to absolute-maximum-rated conditions for extended periodsmayaffect device reliability.
Short-circuit to VS / 2 (groundinsymmetrical dual-supply setups), one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allowssafemanufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allowssafemanufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage
Operating temperature, TA
NOM
MAX
UNIT
4.5 (±2.25)
36 (±18)
V
–40
125
°C
6.4 Thermal Information
OPA1656
THERMAL METRIC (1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
119.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
51.8
°C/W
RθJB
Junction-to-board thermal resistance
65.4
°C/W
ψJT
Junction-to-top characterization parameter
10.0
°C/W
ψJB
Junction-to-board characterization parameter
64.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
–
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
at TA = 25°C, VS = ±18 V, RL = 2 kΩ, and VCM = VOUT = VS/2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO PERFORMANCE
0.000029%
G = 1, RL = 600 Ω, VO = 3.5 VRMS, f = 1 kHz,
80-kHz measurement bandwidth
–131
G = 1, RL = 600 Ω, VO = 3.5 VRMS, f = 20 kHz,
80-kHz measurement bandwidth
THD+N
IMD
–120
Total harmonic distortion + noise
Intermodulation distortion
G = 1, RL = 2 kΩ, VO = 3.5 VRMS, f = 1 kHz,
80-kHz measurement bandwidth
0.000029%
G = 1, RL = 2 kΩ, VO = 3.5 VRMS, f = 20 kHz,
80-kHz measurement bandwidth
0.000035%
G=1
VO = 3.5 VRMS
dB
0.0001%
dB
–131
dB
–129
SMPTE/DIN two-tone, 4:1
(60 Hz and 7 kHz)
0.000018%
CCIF twin-tone
(19 kHz and 20 kHz)
0.000020%
dB
–135
dB
–134
dB
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product
G = 100
53
MHz
Unity gain bandwidth
G=1
20
MHz
Slew rate
G = –1, 10-V step
24
V/µs
Full power bandwidth (1)
VO = 1 VP
3.8
MHz
Overload recovery time
G = –10
100
ns
Channel separation
f = 1 kHz
–135
dB
Settling time
0.01%, G = –1, 10-V step
800
ns
f = 20 Hz to 20 kHz
0.53
µVRMS
f = 0.1 Hz to 10 Hz
1.9
µVPP
11.8
nV/√Hz
NOISE
Input voltage noise
f = 100 Hz
en
Input voltage noise density
in
Input current noise density
f = 1 kHz
4.3
f = 10 kHz
2.9
f = 1 kHz
nV/√Hz
6
fA/√Hz
OFFSET VOLTAGE
VOS
Input offset voltage
VS = ±2.25 V to ±18 V
±0.5
±1
mV
dVOS/dT
Input offset voltage drift
VS = ±2.25 V to ±18 V
TA = –40°C to +125°C (2)
0.3
2
µV/°C
PSRR
Power-supply rejection ratio
VS = ±2.25 V to ±18 V
0.3
5
µV/V
INPUT BIAS CURRENT
IB
Input bias current
VCM = 0 V (3)
±10
±20
pA
IOS
Input offset current
VCM = 0 V
±10
±20
pA
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
(V–)
(V–) ≤ VCM ≤ (V+) – 2.25
106
(V+) – 2.25
V
120
dB
INPUT IMPEDANCE
Differential
100 || 9.1
Common-mode
6 || 1.9
MΩ || pF
1012Ω || pF
OPEN-LOOP GAIN
AOL
(1)
(2)
(3)
Open-loop voltage gain
(V–) + 1.3 V ≤ VO ≤ (V+) – 1.3 V
RL = 600 Ω
134
150
dB
(V–) + 0.5 V ≤ VO ≤ (V+) – 0.5 V
RL = 2 kΩ
134
154
dB
Full-power bandwidth = SR / (2π ×VP),where SR = slew rate.
Specified by design and characterization.
Input bias current test conditions can vary from nominal ambient conditions as a result of junction temperature differences.
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Electrical Characteristics (continued)
at TA = 25°C, VS = ±18 V, RL = 2 kΩ, and VCM = VOUT = VS/2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
VO
Voltage output
RL = 2 kΩ
ZO
Open-loop output impedance
f = 1 MHz
(V–) + 0.25
(V+) – 0.25
ISC
Short-circuit current (4)
±100
mA
CL
Capacitive load drive
100
pF
26
V
Ω
POWER SUPPLY
IQ
(4)
6
Quiescent current (per channel)
IO = 0 A, VS = ±2.25 V to ±18 V
IO = 0 A, TA = –40°C to +125°C (2)
3.9
4.6
mA
5.0
mA
One channel at a time.
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6.6 Typical Characteristics
at TA = 25°C, VS = ±15 V, RL = 2 kΩ, and VCM = VS/2 (unless otherwise noted)
Input Referred Voltage Noise (500 nV/div)
Voltage Noise Density (nV/—Hz)
100
10
1
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
Time (1 s/div)
C020
D029
Figure 1. Input Voltage Noise Density vs Frequency
Figure 2. 0.1-Hz to 10-Hz Noise
50
Voltage Noise Contribution
Resistor Noise Contribution
Current Noise Contribution
Total Noise Contribution
200
100
50
20
10
5
2
1
0.5
30
20
10
0.2
0.1
10
100
1k
10k
Source Resistance (:)
100k
0
100
1M
Gain
Phase 150
120
120
90
90
60
60
30
30
0
0
-30
100
1k
10k 100k
Frequency (Hz)
1M
1M
10M
D113
10M
60
G= 1
G= 1
G= 10
G= +100
40
Gain (dB)
150
10
10k
100k
Frequency (Hz)
Figure 4. Maximum Output Voltage vs Frequency
180
Phase (q)
Gain (dB)
Figure 3. Voltage Noise vs Source Resistance
1
1k
D120
180
-30
100m
Vs=r18 V
Vs=r15 V
Vs=r2.25 V
40
Output Voltage (VP)
Noise (nV/—Hz)
1000
500
20
0
-20
100
D104
CL = 10 pF
1k
10k
100k
Frequency (Hz)
1M
10M
D106
CL = 10 pF
Figure 5. Open-Loop Gain and Phase vs Frequency
Figure 6. Closed-Loop Gain vs Frequency
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Typical Characteristics (continued)
-120
20
100
1k
Frequency (Hz)
VOUT = 3 VRMS
0.1
0.01
-100
0.0001
-120
Bandwidth = 80 kHz
f = 1 kHz
-120
-140
2E-6
1E-6
5E-7
-160
2E-7
1E-7
5E-8
-180
2E-8
1E-8
20
100
Noise (%)
1, HD2
1, HD3
1, HD4
1, HD5
1, HD2
1, HD3
1, HD4
1, HD5
1k
Frequency (Hz)
VOUT = 3 VRMS
10k
Amplitude (dB)
Amplitude ( )
2E-5
1E-5
5E-6
-200
20k
Bandwidth = 80 kHz
G = 1, VIN = 1 VPP (0.354 VRMS)
G = 1, VIN = 5 VPP (1.768 VRMS)
G = +1, VIN = 1 VPP (0.354 VRMS)
G = +1, VIN = 5 VPP (1.768 VRMS)
0.003
0.002
0.001
0.0007
0.0005
0.0001
7E-5
5E-5
-120
3E-5
2E-5
r5
r10
f = 1 kHz
Figure 9. Individual Harmonic Amplitude vs Frequency
Figure 10. THD+N vs Supply Voltage
-120
-40
Amplitude (dBc)
Intermodulation Distortion (dB)
-100
0.0001
Bandwidth = 80 kHz
-20
-80
0.001
RL = 2 kΩ
D141
0
-60
0.01
r18
VS (V)
Bandwidth = 80 kHz
CCIF
SMPTE
-100
0.0003
0.0002
D111
0.1
Intermodulation Distortion (%)
D110
Figure 8. THD+N Ratio vs Output Amplitude
Total Harmonic Distortion
G=
G=
G=
G=
G=
G=
G=
G=
10
0.005
-100
0.0002
0.0001
5E-5
-140
1
Output Amplitude (VRMS)
D109
Figure 7. THD+N Ratio vs Frequency
0.001
0.0005
-40
1, 600 : Load
1, 2k : Load
1, 10k : Load
-60
1, 600 : Load
1, 2k : Load
1, 10k : Load
-80
0.001
1E-5
100m
-140
20k
10k
G=
G=
G=
G=
G=
G=
Total Harmonic Distortion + Noise (dB)
0.00001
Noise (%)
0.0001
Total Harmonic Distortion
0.001
1
-80
1, 600 : Load
1, 2k : Load
1, 10k : Load
1, 600 : Load
1, 2k : Load
1, 10k : Load -100
Noise (dB)
G=
G=
G=
G=
G=
G=
Total Harmonic Distortion
Total Harmonic Distortion
Noise (%)
0.01
Total Harmonic Distortion + Noise (dB)
at TA = 25°C, VS = ±15 V, RL = 2 kΩ, and VCM = VS/2 (unless otherwise noted)
-60
-80
-100
-120
-140
-160
-180
1E-5
10m
-140
100m
1
Output Amplitude (VRMS)
10
-200
20
Bandwidth = 80 kHz
G = 1, VOUT = 3 VRMS
Figure 11. Intermodulation Distortion vs Amplitude
8
100
D140
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1k
Frequency (Hz)
RL = 2 kΩ
10k
50k
D142
Bandwidth = 80 kHz
Figure 12. FFT, 1-kHz Sine Wave
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Typical Characteristics (continued)
0
0
-20
-20
-40
-40
-60
-60
Amplitude (dBc)
Amplitude (dBc)
at TA = 25°C, VS = ±15 V, RL = 2 kΩ, and VCM = VS/2 (unless otherwise noted)
-80
-100
-120
-140
-80
-100
-120
-140
-160
-160
-180
-180
-200
1k
-200
10k
Frequency (Hz)
G = 1, VOUT = 3 VRMS
RL = 2 kΩ
0
80k
Bandwidth = 80 kHz
VOUT = 3 VRMS
Figure 13. FFT, 10-kHz Sine Wave
80k
D143
Bandwidth = 80 kHz
PSRR
PSRR
CMRR
140
Rejection Ratio (dB)
-100
-120
-140
-160
120
100
80
60
40
20
0
-180
1k
10k
VOUT = 3 VRMS
100k
Frequency (Hz)
1M
1
10M
10
100
D114
1k
10k
Frequency (Hz)
100k
1M
10M
D107
G=1
Figure 15. Channel Separation vs Frequency
Figure 16. CMRR and PSRR vs Frequency
(Referred to Input)
126
Common-Mode Rejection Ratio (dB)
147
Power Supply Rejection Ratio (dB)
RL = 2 kΩ
60k
160
-80
146
145
144
143
-40
40k
Frequency (Hz)
Figure 14. FFT, CCIF Input (19 kHz + 20 kHz)
-60
Channel Seperation (dB)
20k
D143
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
125
124
123
122
-40
-25
D028
Figure 17. Power Supply Rejection Ratio vs Temperature
(Referred to Input)
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
D027
Figure 18. Common Mode Rejection Ratio vs Temperature
(Referred to Input)
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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 2 kΩ, and VCM = VS/2 (unless otherwise noted)
30
15
Total Amplifiers (%)
Total Amplifiers (%)
25
10
5
20
15
10
5
-1000
-750
-500
-250
0
250
500
Input Offset Voltage (PV)
750
1000
-2
-1.5
D001
Count = 7955
-1
-0.5
0
0.5
1
Offset Voltage Drift (PV/qC)
1.5
2
D004
Count = 32
Figure 19. Input Offset Voltage Distribution
Figure 20. Input Offset Voltage Drift Distribution
1
100
-40qC
75
50
Offset Voltage (PV)
Offset Voltage (mV)
0.5
0
25
0
-25
-0.5
-50
25qC
-75
-1
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
-100
-18 -15 -12
D017
85qC
125qC
-9 -6 -3
0
3
6
9
Input Common-Mode Voltage (V)
12
15
18
D019
5 typical units shown
Figure 21. Input Offset vs Temperature
Figure 22. Input Offset vs Common Mode Voltage
Voltage (5 mV/div)
VIN
VOUT
Voltage (5 mV/div)
VIN
VOUT
Time (1 Ps/div)
Time (1 Ps/div)
D137
G=1
CL = 20 pF
Figure 23. Small-Signal Step Response (100 mV)
10
D135
G = –1
CL = 100 pF
Figure 24. Small-Signal Step Response (100 mV)
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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 2 kΩ, and VCM = VS/2 (unless otherwise noted)
VIN
VOUT
Voltage (5 V/div)
Voltage (5 V/div)
VIN
VOUT
Time (1 Ps/div)
Time (1 Ps/div)
D139
D136
G=1
RL = 2 kΩ
CL = 100 pF
G = –1
Figure 25. Large-Signal Step Response
Figure 26. Large-Signal Step Response
100
50
156
20
10
5
Input Bias Current (nA)
158
AOL (dB)
154
152
150
148
0.2
0.1
0.05
0.02
0.01
0.005
144
-40
0.002
0.001
-40
-10
5
20 35 50 65
Temperature(qC)
80
95
110 125
IB+
IBIOS
2
1
0.5
146
-25
CL = 100 pF
-25
Figure 27. Open-Loop Gain vs Temperature
5
20 35 50 65
Temperature (qC)
80
95
110 125
D024
Figure 28. IB and IOS vs Temperature
30
4
IBIB+
IOS
VS = 4.5 V
VS = 36 V
Quiescent Current (mA)
20
Input Bias Current (pA)
-10
D033
10
0
-10
3.9
3.8
3.7
-20
-30
-18 -15 -12
-9 -6 -3
0
3
6
9
Input Common-Mode Voltage (V)
12
15
18
3.6
-40
-25
D023
Figure 29. IB and IOS vs Common-Mode Voltage
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
D031
Figure 30. Supply Current vs Temperature
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Typical Characteristics (continued)
4.5
18
4
17
25qC
Output Voltage (V)
Quiescent Current (mA)
at TA = 25°C, VS = ±15 V, RL = 2 kΩ, and VCM = VS/2 (unless otherwise noted)
3.5
3
2.5
-40qC
16
15
125qC
14
13
2
85qC
12
1.5
0
4
8
12
16
20
24
Supply Voltage (V)
28
32
0
36
Figure 31. Supply Current vs Supply Voltage
20
30
40 50 60 70 80
Output Current (mA)
90 100 110 120
D025
Figure 32. Output Voltage vs Output Current (Sourcing)
140
-12
Sinking
Sourcing
132
85qC
Short Circuit Current (mA)
-13
Output Voltage (V)
10
D030
-14
125qC
-15
-16
25qC
-17
-40qC
124
116
108
100
92
84
76
68
60
-40
-18
0
10
20
30
40 50 60 70 80
Output Current (mA)
90 100 110 120
-25
Figure 33. Output Voltage vs Output Current (Sinking)
5
20 35 50 65
Temperature (qC)
80
95
110 125
D041
Figure 34. Short-Circuit Current vs Temperature
75
100
RISO = 0 :
RISO = 25 :
RISO = 50 :
90
80
Overshoot ( )
50
Phase Margin (q)
-10
D026
25
0
70
60
50
40
30
20
-25
10
100
Load Capacitance, CL (pF)
500
10
10
D105
G=1
1000
D037
G=1
Figure 35. Phase Margin vs Capacitive Load
12
100
Load Capacitance, C L (pF)
Figure 36. Percent Overshoot vs Capacitive Load
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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 2 kΩ, and VCM = VS/2 (unless otherwise noted)
60
RISO = 0 :
RISO = 25 :
RISO = 50 :
Voltage (5 V/div)
Overshoot ( )
50
40
30
20
10
VIN
VOUT
0
10
100
Load Capacitance, CL (pF)
Time (400 ns/div)
1000
D134
D131
G = –10
G = –1
Figure 38. Negative Overload Recovery
Figure 37. Percent Overshoot vs Capacitive Load
1000
VIN
VOUT
ZO :
Voltage (5 V/div)
100
10
1
0.1
1
Time (400 ns/div)
10
100
1k
10k
Frequency (Hz)
D138
100k
1M
10M
D112
G = –10
Figure 40. Open-Loop Output Impedance vs Frequency
Figure 39. Positive Overload Recovery
Voltage (5 V/div)
VIN
VOUT
Time (400 ns/div)
D138
G=1
Figure 41. No Phase Reversal
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7 Detailed Description
7.1 Overview
The OPA1656 uses a three-gain-stage architecture to achieve very low noise and distortion. The Functional
Block Diagram shows a simplified schematic of the OPA1656 (one channel shown). The device consists of a low
noise input stage and feedforward pathway coupled to a high-current output stage. This topology exhibits
superior distortion performance under a wide range of loading conditions compared to other operational
amplifiers.
7.2 Functional Block Diagram
Feedforward
Path
CM1
CM2
+IN
Input
Stage
Gain
Stage
Output
Stage
OUT
-IN
7.3 Feature Description
7.3.1 Phase Reversal Protection
The OPA1656 has internal phase-reversal protection. Many op amps exhibit phase reversal when the input is
driven beyond the linear common-mode range. This condition is most often encountered in noninverting circuits
when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into
the opposite rail. The input of the OPA1656 prevents phase reversal with excessive common-mode voltage.
Instead, the appropriate rail limits the output voltage. This performance is shown in Figure 42.
20
15
Voltage (V)
10
5
0
-5
-10
-15
-20
VIN
VOUT
Time (125 s/div)
C004
Figure 42. Output Waveform Devoid of Phase Reversal During an Input Overdrive Condition
7.3.2 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
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Feature Description (continued)
A good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is helpful.
Figure 43 illustrates the ESD circuits contained in the OPA1656 (indicated by the dashed line area). The ESD
protection circuitry involves several current-steering diodes connected from the input and output pins and routed
back to the internal power-supply lines, where the diodes meet at an absorption device internal to the operational
amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
TVS
+
±
RF
+VS
R1
IN±
20 Ÿ
RS
IN+
20 Ÿ
+
Power-Supply
ESD Cell
VIN
RL
+
±
+
±
±VS
TVS
Figure 43. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, highcurrent pulse when discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device can activate. The absorption
device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPA1656 but below
the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly activates
and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit, as shown in Figure 43, the ESD protection components
are intended to remain inactive and do not become involved in the application circuit operation. However,
circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. If this
condition occurs, there is a risk that some internal ESD protection circuits can turn on and conduct current. Any
such current flow occurs through steering-diode paths and rarely involves the absorption device.
Figure 43 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the
current, one of the upper input steering diodes conducts and directs current to V+. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
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Feature Description (continued)
If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input when
the power supplies (V+ or V–) are at 0 V. Again, this question depends on the supply characteristic when at 0 V,
or at a level below the input signal amplitude. If the supplies appear as high impedance, then the input source
supplies the operational amplifier current through the current-steering diodes. This state is not a normal bias
condition; most likely, the amplifier does not operate normally. If the supplies are low impedance, then the current
through the steering diodes can become quite high. The current level depends on the ability of the input source
to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the
supply pins; see Figure 43. Select the Zener voltage so that the diode does not turn on during normal operation.
However, the Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise
above the safe-operating, supply-voltage level.
7.3.3 EMI Rejection Ratio (EMIRR)
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many operational amplifiers is a change in the offset voltage as a
result of RF signal rectification. An operational amplifier that is more efficient at rejecting this change in offset as
a result of EMI has a higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in
many ways, but this document provides the EMIRR IN+, which specifically describes the EMIRR performance
when the RF signal is applied to the noninverting input pin of the operational amplifier. In general, only the
noninverting input is tested for EMIRR for the following three reasons:
• Operational amplifier input pins are known to be the most sensitive to EMI, and typically rectify RF signals
better than the supply or output pins.
• The noninverting and inverting operational amplifier inputs have symmetrical physical layouts and exhibit
nearly matching EMIRR performance.
• EMIRR is easier to measure on noninverting pins than on other pins because the noninverting input pin can
be isolated on a printed-circuit-board (PCB). This isolation allows the RF signal to be applied directly to the
noninverting input pin with no complex interactions from other components or connecting PCB traces.
A more formal discussion of the EMIRR IN+ definition and test method is provided in the EMI Rejection Ratio of
Operational Amplifiers application report, available for download at www.ti.com.
The EMIRR IN+ of the OPA1656 is plotted versus frequency in Figure 44. If available, any dual and quad
operational amplifier device versions have nearly identical EMIRR IN+ performance. The OPA1656 unity-gain
bandwidth is 20 MHz. EMIRR performance below this frequency denotes interfering signals that fall within the
operational amplifier bandwidth.
140
EMIRR IN+ (dB)
120
100
80
60
40
20
10M
100M
1G
Frequency (Hz)
10G
D115
Figure 44. OPA1656 EMIRR vs Frequency
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Feature Description (continued)
Table 1 lists the EMIRR IN+ values for the OPA1656 at particular frequencies commonly encountered in realworld applications. Applications listed in Table 1 can be centered on or operated near the particular frequency
shown. This information can be of special interest to designers working with these types of applications, or
working in other fields likely to encounter RF interference from broad sources, such as the industrial, scientific,
and medical (ISM) radio band.
Table 1. OPA1656 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, UHF
36 dB
900 MHz
GSM, radio communication and navigation, GPS (to 1.6 GHz), ISM,
aeronautical mobile, UHF
42 dB
1.8 GHz
GSM, mobile personal comm. broadband, satellite, L-band
52 dB
2.4 GHz
802.11b/g/n, Bluetooth™, mobile personal comm., ISM, amateur radio and satellite, S-band
64 dB
3.6 GHz
Radiolocation, aero comm./nav., satellite, mobile, S-band
67 dB
5 GHz
802.11a/n, aero communication and navigation, mobile communication,
space and satellite operation, C-band
77 dB
7.3.3.1 EMIRR IN+ Test Configuration
Figure 45 shows the circuit configuration for testing the EMIRR IN+. An RF source is connected to the
operational amplifier noninverting input pin using a transmission line. The operational amplifier is configured in a
unity-gain buffer topology with the output connected to a low-pass filter (LPF) and a digital multimeter (DMM). A
large impedance mismatch at the operational amplifier input causes a voltage reflection; however, this effect is
characterized and accounted for when determining the EMIRR IN+. The resulting dc offset voltage is sampled
and measured by the multimeter. The LPF isolates the multimeter from residual RF signals that can interfere with
multimeter accuracy. See the EMI Rejection Ratio of Operational Amplifiers application report for more details.
Ambient temperature: 25Û&
+VS
±
50
Low-Pass Filter
+
RF source
DC Bias: 0 V
Modulation: None (CW)
Frequency Sweep: 201 pt. Log
-VS
Not shown: 0.1 µF and 10 µF
supply decoupling
Sample /
Averaging
Digital Multimeter
Figure 45. EMIRR IN+ Test Configuration Schematic
7.4 Device Functional Modes
7.4.1 Operating Voltage
The OPA1656 operates from ±2.25 V to ±18 V supplies while maintaining excellent performance. The OPA1656
can operate with as little as 4.5 V between the supplies and with up to 36 V between the supplies. However,
some applications do not require equal positive and negative output voltage swing. With the OPA1656, powersupply voltages are not required to be equal. For example, the positive supply can be set to 25 V with the
negative supply at –5 V.
In all cases, the common-mode voltage must be maintained within the specified range. In addition, key
parameters are specified over the temperature range of TA = –40°C to 125°C.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Basic Noise Calculations
Low-noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in
many cases; consider the effect of source resistance on overall op amp noise performance. Total noise of the
circuit is the root-sum-square combination of all noise components.
Figure 46 shows noninverting (A) and inverting (B) op amp circuit configurations with gain. In circuit
configurations with gain, the feedback network resistors contribute noise. In general, the current noise of the op
amp reacts with the feedback resistors to create additional noise components.
The selected feedback resistor values make these noise sources negligible. Low impedance feedback resistors
load the output of the amplifier. The equations for total noise are shown for both configurations.
(A) Noise in Noninverting Gain Configuration
R1
Noise at the output is given as EO, where
R2
GND
±
EO
+
RS
+
±
VS
Source
GND
'1 = l1 +
:2;
A5 = ¥4 „ G$ „ 6(-) „ 45
d
:3;
A41 æ42 = ¨4 „ G$ „ 6(-) „ d
8
41 „ 42
h d
h
41 + 42
¾*V
Thermal noise of R1 || R2
:4;
G$ = 1.38065 „ 10F23
Boltzmann Constant
:5;
,
h
-
6(-) = 237.15 + 6(°%)
(B) Noise in Inverting Gain Configuration
R1
RS
R2
h
>-?
Thermal noise of RS
Temperature in kelvins
:45 + 41 ; „ 42
42
2
p „ ¨:A0 ;2 + kA41 +45 æ42 o + FE0 „ H
IG
45 + 41
45 + 41 + 42
:6;
'1 = l1 +
+
:7;
:45 + 41 ; „ 42
8
I d
A41 +45 æ42 = ¨4 „ G$ „ 6(-) „ H
h
45 + 41 + 42
¾*V Thermal noise of (R1 + RS) || R2
GND
:8;
G$ = 1.38065 „ 10F23
:9;
6(-) = 237.15 + 6(°%)
±
+
±
d
8
¾*V
> 84/5 ?
Noise at the output is given as EO, where
EO
VS
42
41 „ 42 2
2
p „ ¨:A5 ;2 + :A0 ;2 + kA41 æ42 o + :E0 „ 45 ;2 + lE0 „ d
hp
41
41 + 42
:1;
Source
GND
d
,
h
-
2
> 84/5 ?
Boltzmann Constant
>-?
Temperature in kelvins
Copyright © 2017, Texas Instruments Incorporated
(1)
eN is the voltage noise of the amplifier. For the OPA1656, eN = 4.3 nV/√Hz at 1 kHz.
(2)
iN is the current noise of the amplifier. For the OPA1656, iN = 6 fA/√Hz at 1 kHz.
(3)
For additional resources on noise calculations, see TI's Precision Labs Series.
Figure 46. Noise Calculation in Gain Configurations
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8.2 Typical Applications
8.2.1 Preamplifier Circuit for Vinyl Record Playback With Moving-Magnet Phono Cartridges
The noise and distortion performance of the OPA1656 is exceptional in applications with high source
impedances, which makes these devices an excellent choice in preamplifier circuits for moving magnet phono
cartridges. The high source impedance of the cartridge, and high gain required by the RIAA playback curve at
low frequency, requires an amplifier with both low input current noise and low input voltage noise.
15 V
MM Phono Input
R1
47 k
C1
150 pF
V+
V±
R2
118 k
C2
27 nF
R4
127
+
±
-15 V
OPA1656
R5
100
VOUT
R3
10 k
C5
100 uF
Output
R6
100 k
C3
7.5 nF
C4
100 F
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Figure 47. Preamplifier Circuit for Vinyl Record Playback With Moving-Magnet Phono Cartridges
(Single Channel Shown)
8.2.1.1 Design Requirements
•
•
•
Gain: 40 dB (1 kHz)
RIAA Accuracy: ±0.5 dB (100 Hz to 20 kHz)
Power Supplies: ±15 V
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Typical Applications (continued)
8.2.1.2 Detailed Design Procedure
Vinyl records are recorded using an equalization curve specified by the Recording Institute Association of
America (RIAA). The purpose of this equalization curve is to decrease the amount of space occupied by a grove
on the record and therefore maximize the amount of information able to be stored. Proper playback of music
stored on the record requires a preamplifier circuit that applies the inverse transfer function of the recording
equalization curve. The combination of the recording equalization and the playback equalization results in a flat
frequency response over the audio range, as Figure 48 shows.
20
15
Playback Curve
10
Gain (dB)
5
0
Combined Response
-5
-10
Recording Curve
-15
-20
10
100
1000
10000
Frequency (Hz)
C009
Figure 48. RIAA Recording and Playback Curves Normalized at 1 kHz
The basic RIAA playback curve implements three time constants: 75 μs, 380 μs, and 3180 μs. An IEC
amendment is later added to the playback curve and implements a pole in the curve at 20 Hz with the intent of
protecting loudspeakers from excessive low frequency content. Rather than strictly adhering to the IEC
amendment, this design moves this pole to a lower frequency to improve low frequency response and still
providing protection for loudspeakers.
Resistor R1 and capacitor C1 are selected to provide the proper input impedance for the moving magnet
cartridge. Cartridge loading is specified by the manufacturer in the cartridge datasheet and is absolutely crucial
for proper response at high frequency. 47 kΩ is a common value for the input resistor, and the capacitive loading
is usually specified to 200 pF to 300 pF per channel. This capacitive loading specification includes the
capacitance of the cable connecting the turntable to the preamplifier, as well as any additional parasitic
capacitances at the preamplifier input. Therefore, the value of C1 must be less than the loading specification to
account for these additional capacitances.
The output network consisting of R5, R6, and C5 serves to ac couple the preamplifier circuit to any subsequent
electronics in the signal path. The 100-Ω resistor R5 limits in-rush current into coupling capacitor C5 and
prevents parasitic capacitance from cabling from causing instability. R6 prevents charge accumulation on C5.
Capacitor C5 is chosen to be the same value as C4; for simplicity however, the value of C5 must be large
enough to avoid attenuating low frequency information.
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Typical Applications (continued)
The feedback resistor elements must be selected to provide the correct response within the audio bandwidth. In
order to achieve the correct frequency response, the passive components in Figure 47 must satisfy Equation 1,
Equation 2, and Equation 3:
R2 u C2 3180Ps
(1)
R3 u C3
75Ps
R2 || R3 u C2
(2)
C3
318Ps
(3)
R2, R3, and R4 must also be selected to meet the design requirements for gain. The gain at 1 kHz is determined
by subtracting 20 dB from gain of the circuit at very low frequency (near dc), as shown in Equation 4:
A1kHz ALF 20dB
(4)
Therefore, the low frequency gain of the circuit must be 60 dB to meet the goal of 40 dB at 1 kHz and is
determined by resistors R2, R3, and R4 as shown in Equation 5:
R3 R 2
ALF 1
1000(60dB)
R4
(5)
Because there are multiple combinations of passive components that satisfy these equations, a spreadsheet or
other software calculation tool is the easiest method to examine resistor and capacitor combinations.
Capacitor C4 forces the gain of the circuit to unity at dc in order to limit the offset voltage at the output of the
preamplifier circuit. The high-pass corner frequency created by this capacitor is calculated by Equation 6:
1
FHP
2SR 4 C4
(6)
The circuit described in Figure 47 is constructed with 1% tolerance resistors and 5% tolerance NP0, C0G
ceramic capacitors without any additional hand sorting. The large value of C4 typically requires an electrolytic
type to be used. However, electrolytic capacitors have the potential to introduce distortion into the signal path.
This circuit is constructed using a bipolar electrolytic capacitor specifically intended for audio applications.
8.2.1.3 Application Curves
The deviation from the ideal RIAA transfer function curve is shown in Figure 49 and normalized to an ideal gain
of 40 dB at 1 kHz. The measured gain at 1 kHz is 0.05 dB less than the design goal, and the maximum deviation
from 100 Hz to 20 kHz is 0.18 dB. The deviation from the ideal curve can be improved by hand-sorting resistor
and capacitor values to their ideal values. The value of C4 can also be increased to reduce the deviation at low
frequency.
A spectrum of the preamplifier output signal is shown in Figure 50 for a 10 mVRMS, 1-kHz input signal (1-VRMS
output). All distortion harmonics are below the preamplifier noise floor.
1.5
Amplitude (dBV)
Magnitude (dB)
1
0.5
0
-0.5
10
100
1k
Frequency (Hz)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
100
10k
D202
Figure 49. Measured Deviation From Ideal RIAA Response
1k
Frequency (Hz)
10k
D201
Figure 50. Output Spectrum for a 10-mVRMS, 1-kHz Input
Signal
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Typical Applications (continued)
8.2.2 Composite Headphone Amplifier
Figure 51 shows the BUF634A buffer inside the feedback loop of the OPA1656 to increase the available output
current for low-impedance headphones. If the BUF634A is used in wide-bandwidth mode, no additional
components beyond the feedback resistors are required to maintain loop stability.
12V
100 F
0.1 F
0.1 F
+
Input
R1
100
k
OPA1656
Output
BUF634A
0.1 F
±
RBW
0.1 F
100 F
-12V
R3
R2
500
500
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Figure 51. Composite Headphone Amplifier (Single-Channel Shown)
8.2.2.1 Application Curves
0
-85
-30
Amplitude (dBc)
-90
THD + N (dB)
249 : RL
249 : RL
32 : RL
16 : RL
-95
-100
-105
-110
-90
-120
-150
20 Hz
100 Hz
1 kHz
Frequency (Hz)
20 kHz
-180
0
C051
Figure 52. THD + N versus Frequency for a 5 VPP(1.77
VRMS) Input Signal
22
-60
5000
10000
Frequency (Hz)
15000
20000
C052
Figure 53. FFT for 5 VPP(1.77 VRMS), 1-kHz Input Signal
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Typical Applications (continued)
8.2.3 Baxandall Tone Control
Figure 54 gives an example of ultra-low noise and THD tone control. This circuit provides 20 dB of gain at the
first stage, followed by two separate tone controls for bass and treble. The passive circuit is designed to yield a
flat gain response with the potentiometers both set to 50%.
Bass
1.69 NŸ
15.4 NŸ
100 NŸ
11 NŸ
10 µF
11 NŸ
10 nF
10 nF
±
Input
+15
11 NŸ
+
±
1/2
OPA1656
10 µF
4.7 nF
Output
+
1.69 NŸ
-15
3.65 NŸ
1/2
OPA1656
3.65 NŸ
500 NŸ
Treble
Figure 54. Dual Potentiometer Baxandall Tone Control
8.2.3.1 Application Curves
40
10% Bass / 90% Treble
50% Bass / 50% Treble
90% Bass / 10% Treble
36
32
Amplitude (dB)
28
24
20
16
12
8
4
0
100
1k
Frequency (Hz)
10k
D203
Figure 55. Amplitude vs Frequency for Various Tone-Control Settings
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Typical Applications (continued)
8.2.4 Guitar Input to XLR Output
The OPA1656 is an excellent choice for guitar input circuits as a result of the high input impedance and ultra-low
noise performance.Figure 56 gives an example of a basic guitar input circuit to differential XLR schematic. The
logarithmic taper potentiometer shown in this circuit provides 6 dB of gain at 0%, and 40 dB of gain at 100%. The
rail-to-rail output swing of the OPA1656 allows for a high amplitude swing at the outputs of the differentially
configured amplifiers, while maintaining very low distortion performance. A 10-µF dc blocking capacitor is used in
the feedback of the noninverting stage to remove any dc offset as a result of the amplifier offset voltage.
However, this dc blocking capacitor can be eliminated for applications that are not sensitive to low dc offsets.
10 µF
100 NŸ
1 NŸ
1 NŸ
¼ Inch
Jack
10 pF
±
49 Ÿ
+
1/2
OPA1656
1 0Ÿ
XLR
Output
1 NŸ
1 NŸ
10 pF
+5
±
49 Ÿ
+
-5
1/2
OPA1656
Figure 56. Guitar Input to XLR Output Schematic
0.1
0.08
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.1
-0.12
-0.14
-0.16
-0.18
-0.2
0
0.4
0.8
1.2
1.6
2
2.4
3.3
Input Voltage
3
Output Voltage 1 2.7
Output Voltage 2 2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
-0.3
-0.6
-0.9
-1.2
2.8 3.2 3.6
4
Output Voltage (V)
Input Voltage (V)
8.2.4.1 Application Curves
D200
Figure 57. 1-kHz Input Signal Transient Simulation
24
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9 Power Supply Recommendations
The OPA1656 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Physically
separate digital and analog grounds, observing the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to
in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 58, keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, postcleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
10.1.1 Power Dissipation
The OPA1656 op amp is capable of driving 600-Ω loads with a power-supply voltage up to ±18 V and full
operating temperature range. Internal power dissipation increases when operating at high supply voltages.
Copper leadframe construction used in the OPA1656 improves heat dissipation compared to conventional
materials. Circuit board layout can also help minimize junction temperature rise. Wide copper traces help
dissipate the heat by acting as an additional heat sink. Temperature rise can be further minimized by soldering
the devices to the circuit board rather than using a socket.
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10.2 Layout Example
+
VIN A
+
VIN B
VOUT A
RG
VOUT B
RG
RF
RF
(Schematic Representation)
Place components
close to device and to
each other to reduce
parasitic errors.
Output A
VS+
OUTPUT A
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
GND
V+
RF
Output B
GND
-IN A
OUTPUT B
+IN A
-IN B
RF
RG
VIN A
GND
RG
V±
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
GND
VS±
+IN B
Ground (GND) plane on another layer
VIN B
Keep input traces short
and run the input traces
as far away from
the supply lines
as possible.
Figure 58. Operational Amplifier Board Layout for Noninverting Configuration
26
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ is
a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a
range of both passive and active models. TINA-TI provides all the conventional DC, transient, and frequency
domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the WEBENCH® Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 DIP Adapter EVM
The DIP Adapter EVM tool provides an easy, low-cost way to prototype small surface mount devices. The
evaluation tool these TI packages: D or U (SOIC-8), PW (TSSOP-8), DGK (VSSOP-8), DBV (SOT-23-6, SOT-235 and SOT-23-3), DCK (SC70-6 and SC70-5), and DRL (SOT563-6). The DIP Adapter EVM may also be used
with terminal strips or may be wired directly to existing circuits.
11.1.1.3 Universal Operational Amplifier EVM
The Universal Op Amp EVM is a series of general-purpose, blank circuit boards that simplify prototyping circuits
for a variety of device package types. The evaluation module board design allows many different circuits to be
constructed easily and quickly. Five models are offered, with each model intended for a specific package type.
PDIP, SOIC, VSSOP, TSSOP and SOT-23 packages are all supported.
NOTE
These boards are unpopulated, so users must provide their own devices. TI recommends
requesting several op amp device samples when ordering the Universal Op Amp EVM.
11.1.1.4 TI Precision Designs
TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the
theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and
measured performance of many useful circuits. TI Precision Designs are available online at
http://www.ti.com/ww/en/analog/precision-designs/.
11.1.1.5 WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer allows the user to create optimized filter designs using a selection of TI operational amplifiers and
passive components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows the
user to design, optimize, and simulate complete multistage active filter solutions within minutes.
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11.2 Documentation Support
11.2.1 Related Documentation
The following documents are recommended for reference when using the OPA1656, and are available for
download at www.ti.com.
• Texas Instruments, Source Resistance and Noise Considerations in Amplifiers technical brief
• Texas Instruments, Single-Supply Operation of Operational Amplifiers application bulletin
• Texas Instruments, Op Amp Performance Analysis application bulletin
• Texas Instruments, Compensate Transimpedance Amplifiers Intuitively application report
• Texas Instruments, Tuning in Amplifiers application bulletin
• Texas Instruments, Feedback Plots Define Op Amp AC Performance application bulletin
• Texas Instruments, Active Volume Control for Professional Audio design guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
Burr-Brown, TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Jul-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA1656ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OP1656
OPA1656IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OP1656
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Jul-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
OPA1656IDR
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA1656IDR
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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