Texas Instruments | OPAx189 Precision, Lowest-Noise 36-V, Zero-Drift, 14-MHz MUX-Friendly, Rail-to-Rail Output, Operational Amplifiers (Rev. E) | Datasheet | Texas Instruments OPAx189 Precision, Lowest-Noise 36-V, Zero-Drift, 14-MHz MUX-Friendly, Rail-to-Rail Output, Operational Amplifiers (Rev. E) Datasheet

Texas Instruments OPAx189 Precision, Lowest-Noise 36-V, Zero-Drift, 14-MHz MUX-Friendly, Rail-to-Rail Output, Operational Amplifiers (Rev. E) Datasheet
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OPA189, OPA2189
SBOS830E – SEPTEMBER 2017 – REVISED MAY 2019
OPAx189 Precision, Lowest-Noise 36-V, Zero-Drift, 14-MHz
MUX-Friendly, Rail-to-Rail Output, Operational Amplifiers
1 Features
3 Description
•
The OPA189 and OPA2189 (OPAx189) highprecision operational amplifiers are ultra-low noise,
fast-settling, zero-drift devices that provide rail-to-rail
output operation and feature a unique MUX-friendly
architecture and controlled start-up system. These
features and excellent ac performance, combined
with only 0.4 µV of offset voltage and 0.005µV/°C of
drift over temperature for the single-channel version,
make the OPAx189 a great choice for precision
instrumentation, signal measurement, and active
filtering applications. Moreover, the MUX-friendly
input architecture prevents inrush current when
applying large input differential voltages, which
improves settling performance in multichannel
systems, all while providing robust ESD protection
during shipment, handling, and assembly.
Ultra-high precision:
– Zero-drift: 0.005 μV/°C (OPA189)
– Ultra-low offset voltage: 3 μV maximum
(OPA189)
Excellent dc precision:
– CMRR: 168 dB
– Open-loop gain: 170 dB
Low noise:
– en at 1 kHz: 5.2 nV/√Hz
– 0.1-Hz to 10-Hz noise: 0.1 µVPP
Excellent dynamic performance:
– Gain bandwidth: 14 MHz
– Slew rate: 20 V/µs
– Fast settling: 10-V step, 0.01% in 1.1 µs
Robust design:
– MUX-friendly inputs
– RFI/EMI filtered inputs
Wide supply range: 4.5 V to 36 V
Quiescent current: 1.7 mA (maximum)
Rail-to-rail output
Input includes negative rail
1
•
•
•
•
•
•
•
•
Device Information(1)
PART NUMBER
OPA189
OPA2189
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.90 mm
SOT-23 (5)
2.90 mm × 1.60 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (8)
4.90 mm × 3.90 mm
VSSOP (8)
(preview)
3.00 mm × 3.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
2 Applications
•
•
•
•
•
All versions are specified from –40°C to +125°C.
Precision multichannel systems
Bridge amplifier
Strain gauges
Temperature measurement
Resistance temperature detectors
OPAx189 Preserves R-C Settling Performance in a
Switched or Multiplexed Application
OPAx189 MUX-Friendly Input Settles Quickly and
Maintains High Input Impedance When Switched
Analog Inputs
OPAx189 MUX-friendly Inputs
Prevents Loading of Source
OPAx189
Bridge Sensor
Thermocouple
+
Robust MUX-Friendly Inputs
without Anti-Parallel Diodes
Voltage
OPAx189
4:2
HV
MUX
+
OPAx189
Competitor HV Amp
Current Sensing
Classical High-Voltage Op Amp
Anti-Parallel Diodes Loads Source
LED
Photo
Detector
Optical Sensor
High-Voltage Multiplexed Input
High-Voltage Level Translation
Input
Copyright © 2017, Texas Instruments Incorporated
Time
Copyright © 2017, Texas Instruments Incorporated C003
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
OPA189, OPA2189
SBOS830E – SEPTEMBER 2017 – REVISED MAY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
1
1
1
2
4
5
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information: OPA189 .................................. 7
Thermal Information: OPA2189 ................................ 7
Electrical Characteristics........................................... 8
Typical Characteristics ............................................ 10
Detailed Description ............................................ 18
8.1
8.2
8.3
8.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
18
18
19
25
9
Application and Implementation ........................ 26
9.1 Application Information............................................ 26
9.2 Typical Applications ................................................ 26
9.3 System Examples ................................................... 31
10 Power Supply Recommendations ..................... 32
11 Layout................................................................... 33
11.1 Layout Guidelines ................................................. 33
11.2 Layout Example .................................................... 33
12 Device and Documentation Support ................. 34
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
34
34
35
35
35
35
35
35
13 Mechanical, Packaging, and Orderable
Information ........................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (December 2018) to Revision E
Page
•
Changed OPA189 SOT-23 (DBV) package from preview to production data (active)........................................................... 1
•
Changed Figure 3, Input Bias Current Production Distribution, to show updated data........................................................ 11
•
Changed Figure 4, Input Offset Current Production Distribution, to show updated data ..................................................... 11
•
Changed Figure 8, Open-Loop Gain and Phase vs Frequency, for clarity .......................................................................... 12
•
Changed Figure 9, Closed-Loop Gain vs Frequency, for clarity .......................................................................................... 12
•
Added new Figure 39, OPA2189 Long-Term Drift ............................................................................................................... 17
Changes from Revision C (October 2018) to Revision D
Page
•
Changed OPA2189 SOIC (D) package from preview to production data .............................................................................. 1
•
Added input bias current for OPA2189ID ............................................................................................................................... 8
•
Added input offset current for OPA2189ID............................................................................................................................. 8
•
Added crosstalk for OPA2189ID............................................................................................................................................. 9
•
Changed Maximum Output Voltage Amplitude vs Frequency to reflect undistorted operating range ................................. 15
•
Added OPA189 long-term drift and OPA2189 channel separation curves .......................................................................... 16
Changes from Revision B (October 2018) to Revision C
•
Page
First release of production-data sheet for OPA189IDGK ....................................................................................................... 1
Changes from Revision A (November 2017) to Revision B
Page
•
Added input offset for OPA2189ID ......................................................................................................................................... 8
•
Added input offset drift for OPA2189ID .................................................................................................................................. 8
2
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SBOS830E – SEPTEMBER 2017 – REVISED MAY 2019
Changes from Original (September 2017) to Revision A
•
Page
First release of production-data sheet for OPA189ID device ................................................................................................ 1
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3
OPA189, OPA2189
SBOS830E – SEPTEMBER 2017 – REVISED MAY 2019
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5 Device Comparison Table
PRODUCT
4
FEATURES
OPA188
25-µV, 0.085-µV/°C, 8.8-nV/√Hz, Rail-to-Rail Output, 36-V, Zero-Drift CMOS
OPA388
5-µV, 0.05-µV/°C, 7-nV/√Hz, 10-MHz, True Rail-to-Rail Input/Output, 5.5-V, Zero-Drift CMOS
OPA333
10-µV, 0.05-µV/°C, 25-µA, Rail-to-Rail Input/Output, 5.5-V, Zero-Drift CMOS
OPA192
25-µV, 0.8-µV/°C, 1-mA, 10-MHz, Rail-to-Rail Input/Output, 36-V, e-Trim CMOS
OPA140
120-µV, 10-MHz, 5.1-nV/√Hz, 36-V JFET Input Industrial Op Amp
OPA209
2.2-nV/√Hz, 150-µV, 18-MHz, 36-V Bipolar Op Amp in SOT-23 package
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SBOS830E – SEPTEMBER 2017 – REVISED MAY 2019
6 Pin Configuration and Functions
OPA189 D and DGK Packages
8-Pin SOIC, 8-Pin VSSOP
Top View
±IN
2
+IN
3
V±
4
8
NC
±
7
V+
+
6
OUT
5
NC
OUT
1
V±
2
+IN
3
Not to scale
5
V+
4
±IN
±
1
+
NC
OPA189 DBV Package
5-Pin SOT-23
Top View
Not to scale
Pin Functions: OPA189
PIN
I/O
DESCRIPTION
D (SOIC)
DGK (VSSOP)
DBV (SOT-23)
–IN
2
4
I
Inverting input
+IN
3
3
I
Noninverting input
NC
1, 5, 8
—
—
No internal connection (can be left floating)
OUT
6
1
O
Output
V–
4
2
—
Negative (lowest) power supply
V+
7
5
—
Positive (highest) power supply
NAME
OPA2189 D and DGK (preview) Packages
8-Pin SOIC, 8-Pin VSSOP
Top View
OUT A
1
8
V+
±IN A
2
7
OUT B
+IN A
3
6
±IN B
V±
4
5
+IN B
Not to scale
Pin Functions: OPA2189
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
Inverting input channel A
+IN A
3
I
Noninverting input channel A
–IN B
6
I
Inverting input channel B
+IN B
5
I
Noninverting input channel B
OUT A
1
O
Output channel A
OUT B
7
O
Output channel B
V–
4
—
Negative supply
V+
8
—
Positive supply
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage
Signal input pins
VS = (V+) – (V–)
Voltage
MAX
Single-supply
Dual-supply
Common-mode
±20
(V–) – 0.5
Differential
(V+) – (V–) + 0.2
±10
Continuous
Continuous
–55
150
Operating, TA
Junction, TJ
(2)
mA
150
Storage, Tstg
(1)
V
(V+) + 0.5
Current
Output short circuit (2)
Temperature
UNIT
40
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage, VS = (V+) – (V–)
Single-supply
Dual-supply
Specified temperature
6
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NOM
MAX
4.5
36
±2.25
±18
–40
125
UNIT
V
°C
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Product Folder Links: OPA189 OPA2189
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SBOS830E – SEPTEMBER 2017 – REVISED MAY 2019
7.4 Thermal Information: OPA189
OPA189
THERMAL METRIC (1)
D (SOIC)
DGK (VSSOP)
DBV (SOT)
8 PINS
8 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
122.0
166.4
134.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
57.6
54.2
90.5
°C/W
RθJB
Junction-to-board thermal resistance
67.3
87.9
41.9
°C/W
ΨJT
Junction-to-top characterization parameter
12.7
5.5
22.5
°C/W
ΨJB
Junction-to-board characterization parameter
66.2
86.4
41.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Thermal Information: OPA2189
OPA2189
THERMAL METRIC
(1)
D (SOIC)
DGK (VSSOP)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
115.7
150.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
51.1
43.9
°C/W
RθJB
Junction-to-board thermal resistance
60.8
71.4
°C/W
ΨJT
Junction-to-top characterization parameter
9.8
2.9
°C/W
ΨJB
Junction-to-board characterization parameter
59.7
70
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.6 Electrical Characteristics
at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±0.4
±3
UNIT
OFFSET VOLTAGE
Input offset voltage,
OPA189
TA = –40°C to 125°C
Input offset voltage,
OPA2189ID
TA = –40°C to 125°C
Input offset voltage drift,
OPA189
TA = –40°C to 125°C
±0.005
±0.02
µV/°C
TA = –0°C to 85°C
VOS
dVOS/dT
PSRR
Input offset voltage drift,
OPA2189ID
Power-supply rejection
ratio
±4
±1.5
µV
±5
µV
±8
µV
±0.007
±0.03
µV/°C
TA = –40°C to 125°C
±0.01
±0.05
µV/°C
TA = –40°C to 125°C
±0.005
±0.05
µV/V
±70
±300
pA
INPUT BIAS CURRENT
Input bias current, OPA189
IB
TA = 0°C to 85°C
ZIN = 100 kΩ || 500 pF
Input bias current,
OPA2189
±1
TA = –40°C to 125°C
±10
±70
±1.5
TA = –40°C to 125°C
±10
±140
Input offset current,
OPA189
IOS
TA = 0°C to 85°C
ZIN = 100 kΩ || 500 pF
Input offset current,
OPA2189
±300
TA = 0°C to 85°C
±600
±1.6
TA = –40°C to 125°C
±3
±140
TA = 0°C to 85°C
±600
±2.5
TA = –40°C to 125°C
±5
nA
pA
nA
pA
nA
pA
nA
NOISE
En
Input voltage noise
en
Input voltage noise density
in
Input current noise density
f = 0.1 Hz to 10 Hz
17
nVRMS
0.1
µVPP
f = 10 Hz
5.2
f = 100 Hz
5.2
f = 1 kHz
5.2
f = 10 kHz
5.2
f = 1 kHz
165
nV/√Hz
fA/√Hz
INPUT VOLTAGE
VCM
Common-mode voltage
range
CMRR
Common-mode rejection
ratio
(V–) – 0.1
(V–) – 0.1 V ≤ VCM ≤ (V+) – 2.5 V
(V–) – 0.1 V ≤ VCM ≤ (V+) – 2.5 V,
TA = –40°C to 125°C
(V+) – 2.5
VS = ±2.25 V
120
140
VS = ±18 V
146
168
VS = ±18 V
120
VS = ±2.25 V
110
V
dB
INPUT IMPEDANCE
zid
Differential input
impedance
0.1 || 5.5
GΩ || pF
zic
Common-mode input
impedance
60 || 1.7
TΩ || pF
8
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SBOS830E – SEPTEMBER 2017 – REVISED MAY 2019
Electrical Characteristics (continued)
at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
(V–) + 0.3 V < VO <
(V+) – 0.3 V,
RLOAD = 10 kΩ
150
170
(V–) + 0.3 V < VO <
(V+) – 0.3 V,
RLOAD = 10 kΩ,
TA = –40°C to 125°C
140
(V–) + 0.6 V < VO <
(V+) – 0.6 V,
RLOAD = 2 kΩ
150
(V–) + 0.6 V < VO <
(V+) – 0.6 V,
RLOAD = 2 kΩ,
TA = –40°C to 125°C
140
MAX
UNIT
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
VS = ±18 V
dB
170
FREQUENCY RESPONSE
UGB
Unity-gain Bandwith
AV = 1
GBW
Gain-bandwith Product
AV = 1000
14
SR
Slew rate
G = 1, 10-V step
20
THD+N
Total harmonic distortion +
noise
G = 1, f = 1 kHz, VO = 3.5 VRMS
Crosstalk
tS
tOR
8
Overload recovery time
V/µs
0.00006%
OPA2189ID, at dc
150
OPA2189ID, f = 100 kHz
120
To 0.1%
VS = ±18 V, G = 1, 10-V
step
0.8
To 0.01%
VS = ±18 V, G = 1, 10-V
step
1.1
Settling time
MHz
dB
µs
VIN × G = VS
320
ns
OUTPUT
No load
Positive rail
VO
Voltage output swing from
rail
5
15
RLOAD = 10 kΩ
20
110
RLOAD = 2 kΩ
80
500
No load
Negative rail
5
15
RLOAD = 10 kΩ
20
110
RLOAD = 2 kΩ
80
500
20
120
TA = –40°C to 125°C, both rails, RLOAD = 10 kΩ
ISC
Short-circuit current
CLOAD
Capacitive load drive
See Small-Signal Overshoot vs Capacitive Load
ZO
Open-loop output
impedance
f = 1 MHz, IO = 0 A, see Open-Loop Output
Frequency
Impedance vs
mV
±65
mA
380
Ω
POWER SUPPLY
IQ
Quiescent current per
amplifier
VS = ±2.25 V to ±18 V (VS = 4.5 V to
36 V)
TA = 25°C
1.3
TA = –40°C to 125°C
1.7
1.8
mA
TEMPERATURE
TA
Specified range
–40
+125
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7.7 Typical Characteristics
Table 1. Typical Characteristic Graphs
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
Figure 1
Offset Voltage Drift Distribution From –40°C to 125°C
Figure 2
Input Bias Current Production Distribution
Figure 3
Input Offset Current Production Distribution
Figure 4
Offset Voltage vs Temperature
Figure 5
Offset Voltage vs Common-Mode Voltage
Figure 6
Offset Voltage vs Supply Voltage
Figure 7
Open-Loop Gain and Phase vs Frequency
Figure 8
Closed-Loop Gain vs Frequency
Figure 9
Input Bias Current vs Common-Mode Voltage
Figure 10
Input Bias Current and Offset vs Temperature
Figure 11
Output Voltage Swing vs Output Current (Sourcing)
Figure 12
Output Voltage Swing vs Output Current (Sinking)
Figure 13
CMRR and PSRR vs Frequency
Figure 14
CMRR vs Temperature
Figure 15
PSRR vs Temperature
Figure 16
0.1-Hz to 10-Hz Voltage Noise
Figure 17
Input Voltage Noise Spectral Density vs Frequency
Figure 18
THD+N Ratio vs Frequency
Figure 19
THD+N vs Output Amplitude
Figure 20
Quiescent Current vs Supply Voltage
Figure 21
Quiescent Current vs Temperature
Figure 22
Open-Loop Gain vs Temperature (10-kΩ)
Figure 23
Open-Loop Gain vs Temperature (2-kΩ)
Figure 24
Open-Loop Output Impedance vs Frequency
Figure 25
Small-Signal Overshoot vs Capacitive Load (10-mV Step)
Figure 26
No Phase Reversal
Figure 27
Positive Overload Recovery
Figure 28
Negative Overload Recovery
Figure 29
Small-Signal Step Response (10-mV Step)
Figure 30, Figure 31
Large-Signal Step Response (10-V Step)
Figure 32, Figure 33
Settling Time
Figure 34
Short-Circuit Current vs Temperature
Figure 35
Maximum Output Voltage vs Frequency
Figure 36
EMIRR vs Frequency
Figure 37
OPA189 Long-Term Drift
Figure 38
OPA2189 Long-Term Drift
Figure 39
Channel Separation
Figure 40
10
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SBOS830E – SEPTEMBER 2017 – REVISED MAY 2019
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
45
14
40
12
35
Amplifiers (%)
Amplifiers (%)
10
8
6
4
30
25
20
15
10
2
σ = 374.5 nV
VOS (maximum) = ±3 µV
N = 2554
0.02
0.015
0.01
45%
40%
35%
30%
25%
20%
15%
10%
5%
240
0
-600 -480 -360 -240 -120
0
120 240
Input Offset Current (pA)
300
Figure 3. Input Bias Current Production Distribution
360
480
600
Figure 4. Input Offset Current Production Distribution
5
20
4
Input-referred Offset Voltage ( V)
Input-referred Offset Voltage ( V)
0.005
Figure 2. Offset Voltage Drift Distribution
50%
Amplifiers (%)
Amplifiers (%)
C002
µ = 2.83 nV/°C
σ = 2.78 nV/°C
N = 96
dVOS / dT (maximum) = ±0.02 µV/°C
Figure 1. Offset Voltage Production Distribution
35%
32.5%
30%
27.5%
25%
22.5%
20%
17.5%
15%
12.5%
10%
7.5%
5%
2.5%
0
-300 -240 -180 -120 -60
0
60 120 180
Positive Input Bias Current (pA)
0
Input Offset Voltage Drift (µV/ƒC)
C001
µ = 46.67 nV
-0.005
Input Offset Voltage (µV)
-0.01
-0.015
-0.02
0
3
2.5
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
5
-3
0
3
2
1
0
±1
±2
±3
±4
±5
15
10
5
0
±5
±10
VCM = 15.5 V
VCM = ± 18.1 V
±15
±20
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
±20
±15
±10
±5
0
5
10
15
Input Common-mode Voltage (V)
C001
5 Typical Units
20
C003
5 Typical Units
Figure 5. Offset Voltage vs Temperature
Figure 6. Offset Voltage vs Common-Mode Voltage
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160
210
1.5
140
180
1.0
120
150
100
120
0.5
0.0
±0.5
±1.0
VS = 4.5 V
80
90
60
60
40
30
20
±1.5
0
Open Loop Gain
Open Loop Phase
0
±2.0
0
9
18
27
36
Supply Voltage (V)
Phase (q)
2.0
Gain (dB)
Input-referred Offset Voltage ( V)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
-30
-20
-60
1
10
100
1k
10k
Freq
C001
100k
1M
10M
5 Typical Units
Figure 8. Open-Loop Gain and Phase vs Frequency
Figure 7. Offset Voltage vs Supply Voltage
80
500
Gain (dB)
60
=
=
=
=
=
+1
-1
+10
+100
+1000
40
20
400
Input Bias Current (pA)
G
G
G
G
G
300
200
100
0
±100
±200
±300
0
±400
-20
100
±500
1k
10k
100k
Frequency (Hz)
1M
±20
10M
±10
0
±5
5
10
15
Input Common-mode Voltage (V)
Figure 9. Closed-Loop Gain vs Frequency
18
20.0
17
16.0
C001
±40°C
25°C
VO (V)
16
12.0
20
Figure 10. Input Bias Current vs Common-Mode Voltage
24.0
Input Current (nA)
±15
IBP
8.0
IBN
15
125°C
14
4.0
85°C
13
0.0
IOS
±4.0
12
±75
±50
±25
0
25
50
75
Temperature (ƒC)
100
125
150
0
10
20
30
40
50
IO (mA)
C001
60
70
80
90
C001
Sourcing
Figure 11. Input Bias Current and Offset vs Temperature
12
Figure 12. Output Voltage Swing vs Output Current
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
-12
160
-13
140
+PSRR
Rejection Ratio (dB)
125°C
-14
VO (V)
CMRR
85°C
-15
±40°C
-16
25°C
-17
120
±PSRR
100
80
60
40
20
0
-18
0
10
20
30
40
50
60
70
80
1
90
IO (mA)
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
C001
C004
Sinking
Figure 14. CMRR and PSRR vs Frequency
Figure 13. Output Voltage Swing vs Output Current
180
160
0.01
150
140
0.1
130
120
1
±75 ±50 ±25
0
25
50
75
170
160
0.01
150
140
0.1
130
120
100 125 150
Temperature (ƒC)
0.001
1
±75
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
C001
Figure 15. CMRR vs Temperature
C001
Voltage Noise Spectral Density (nV/rtHz)
Input-referred Voltage Noise (50 nV/div)
Figure 16. PSRR vs Temperature
Time (1 s/div)
100
10
1
1
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
C017
Figure 17. 0.1-Hz to 10-Hz Voltage Noise
Power Supply Rejection Ratio (µV/V)
170
Power Supply Rejection Ratio (dB)
0.001
Common-mode Rejection Ratio (µV/V)
Common-Mode Rejection Ratio (dB)
180
C006
Figure 18. Input Voltage Noise Spectral Density
vs Frequency
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Total Harmonic Distortion + Noise (%)
0.1
-60
0.01
-80
0.001
-100
0.0001
-120
-140
20k
0.00001
20
200
2k
Frequency (Hz)
1
0.1
-80
0.001
-100
0.0001
-120
-140
0.00001
0.01
0.1
1
10
Output Amplitude (VRMS)
VRMS, BW = 90 kHz
f = 1 kHz,
Figure 19. THD+N Ratio vs Frequency
C004
BW = 90 kHz
Figure 20. THD+N vs Output Amplitude
2
1.5
1.2
Quiescent Current (mA)
Quiescent Current (mA)
-60
0.01
C004
VOUT = 3.5 V
-40
G = -1, 600- Load
G = -1, 2k- Load
G = -1, 10k- Load
G = +1, 600- Load
G = +1, 2k- Load
G = +1, 10k- Load
Total Harmonic Distortion + Noise (dB)
-40
G = -1, 2k- Load
G = -1, 600- Load
G = -1, 10k- Load
G = +1, 2k- Load
G = +1, 600- Load
G = +1, 10k- Load
Total Harmonic Distortion + Noise (dB)
1
Total Harmonic Distortion + Noise (%)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
0.9
VS = 4.5 V
0.6
0.3
VS = ± 18 V
1.5
1
VS = ± 2.25 V
0.5
0
0
0
9
18
27
36
Supply Voltage (V)
±75
±50
±25
Figure 21. Quiescent Current vs Supply Voltage
180
0
25
50
75
100
125
150
Temperature (ƒC)
C001
C001
Figure 22. Quiescent Current vs Temperature
0.001
180
0.001
VS = ± 18 V
0.01
150
VS = ± 2.25
140
0.1
130
160
0.01
VS = ± 18 V
150
140
0.1
130
Open-loop Gain (µV/V)
160
Open-loop Gain (dB)
170
Open-loop Gain (µV/V)
Open-loop Gain (dB)
170
VS = ± 2.25
120
1
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
1
±50
0
±25
25
50
75
100
125
Temperature (ƒC)
C001
10-kΩ Load
C001
2-kΩ Load
Figure 23. Open-Loop Gain vs Temperature
14
120
Figure 24. Open-Loop Gain vs Temperature
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
1k
ZO (:)
Overshoot (%)
100
10
1
100
1k
10k
100k
1M
Frequency (Hz)
10M
100M
65
60
55
50
45
40
35
30
25
20
15
10
5
0
10
Zotc
100
1000
Capacitive Load (pF)
C004
10-mV Step
Figure 26. Small-Signal Overshoot vs Capacitive Load
Figure 25. Open-Loop Output Impedance vs Frequency
Vout (V)
Output Voltage (5 V/div)
Vin (V)
VIN
5 V/div
VOUT
Time (1 ms/div)
Time (0.2 µs/div)
C017
C017
Figure 27. No Phase Reversal
Figure 28. Positive Overload Recovery
5 V/div
2.5 mV/div
VIN
VOUT
Input
Output
Time (500 ns/div)
Time (0.2 µs/div)
C017
C017
10-mV Step
Figure 29. Negative Overload Recovery
G = +1
Figure 30. Small-Signal Step Response
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2 V/div
2.5 mV/div
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Output
Input
Output
Input
Time (500 ns/div)
Time (500 ns/div)
C017
C017
10-mV Step
G = –1
10-V Step
Figure 31. Small-Signal Step Response
G = –1
Figure 32. Large-Signal Step Response
2 V/div
1 mV/div
.01% Settling = “1 mV
Output
Input
Time (500 ns/div)
Time (500 ns/div)
C017
10-V Step
C017
G = +1
10-V Step
Figure 33. Large-Signal Step Response
Figure 34. Settling Time
40
Vs = ±18V
Vs = ±2.25V
35
90
Sinking
Output Voltage (V pp)
Short Circuit Current (mA)
100
80
70
Sourcing
60
50
30
25
20
15
10
5
40
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C001
Figure 35. Short-Circuit Current vs Temperature
16
150
0
100
1k
10k
Frequency (Hz)
100k
1M
Figure 36. Maximum Output Voltage Amplitude vs
Frequency
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
0.25
120
0.2
Offset Voltage Delta (PV)
EMIRR IN+ (dB)
100
80
60
40
20
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
0
10M
100M
1G
-0.25
10G
Frequency (Hz)
0
250
500
C005
750 1000 1250 1500
Elapsed Time (hours)
1750
2000
PRF = –10 dBm
Figure 38. OPA189 Long-Term Drift
-60
0.2
-80
0.15
Channel Seperation (dB)
Input Referenced Offset Voltage Delta (uV)
Figure 37. EMIRR vs Frequency
0.25
0.1
0.05
0
-0.05
-0.1
-0.15
-100
-120
-140
-160
-0.2
-0.25
0
250
500
750
1000 1250 1500
Elapsed Time (hours)
1750
Figure 39. OPA2189 Long-Term Drift
2000
-180
1k
10k
100k
Frequency (Hz)
1M
10M
Figure 40. OPA2189 Channel Separation
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8 Detailed Description
8.1 Overview
The OPAx189 operational amplifier combines precision offset and drift with excellent overall performance,
making the device well-suited for many precision applications. The precision offset drift of only 0.005 µV/°C
provides stability over the entire temperature range. In addition, this device offers excellent linear performance
with high CMRR, PSRR, and AOL. As with all amplifiers, applications with noisy or high-impedance power
supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate.
See Layout Guidelines for details and layout example.
The OPAx189 is part of a family of zero-drift, MUX-friendly, rail-to-rail output operational amplifiers. These
devices operate from 4.5 V to 36 V, are unity-gain stable, and are suitable for a wide range of general-purpose
and precision applications. The zero-drift architecture provides ultra-low input offset voltage and near-zero input
offset voltage drift over temperature and time. This choice of architecture also offers outstanding ac performance,
such as ultra-low broadband noise, zero flicker noise, and outstanding distortion performance when operating
below the chopper frequency.
8.2 Functional Block Diagram
The Functional Block Diagram shows a representation of the proprietary OPAx189 architecture.
Slew Boost Circuit
CCOMP
CLK
+IN
±IN
CLK
Protection
Switches
OUT
GM1
GM_FF
18
GM2
GM3
Ripple
Reduction FB
Loop
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8.3 Feature Description
The OPAx189 series of op amps can be used with single or dual supplies from an operating range of VS = 4.5 V
(±2.25 V) up to VS = 36 V (±18 V). These devices do not require symmetrical supplies; they only require a
minimum
supply
voltage
of
4.5
V
(±2.25
V).
For
VS
less
than
±2.5
V,
the
common-mode input range does not include midsupply. Supply voltages higher than 40 V can permanently
damage the device; see the Absolute Maximum Ratings table for details. Key parameters are given over the
specified temperature range, TA = –40°C to +125°C, in Electrical Characteristics. Key parameters that vary over
the supply voltage, temperature range, or frequency are shown in Typical Characteristics.
The OPAx189 is unity-gain stable and free from unexpected output phase reversal. This device uses a
proprietary, periodic autocalibration technique to provide low input offset voltage and very low input offset voltage
drift over time and temperature. For lowest offset voltage and precision performance, optimize circuit layout and
mechanical conditions. Avoid temperature gradients that create thermoelectric (Seebeck) effects in the
thermocouple junctions formed from connecting dissimilar conductors. Cancel these thermally-generated
potentials by ensuring they are equal on both input pins. Other layout and design considerations include:
• Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
• Thermally isolate components from power supplies or other heat sources.
• Shield operational amplifier and input circuitry from air currents, such as cooling fans.
Follow these guidelines to reduce the likelihood of junctions being at different temperatures, which may cause
thermoelectric voltages of 0.1 µV/°C or higher, depending on the materials used. See Layout Guidelines for
details and layout example.
8.3.1 Operating Characteristics
The OPAx189 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V). Many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics section.
8.3.2 Phase-Reversal Protection
The OPAx189 has an internal phase-reversal protection. Many op amps exhibit a phase reversal when the input
is driven beyond the linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The OPAx189 input prevents phase reversal with excessive common-mode
voltage. Instead, the output limits into the appropriate rail. This performance is shown in Figure 41.
Vout (V)
Output Voltage (5 V/div)
Vin (V)
Time (1 ms/div)
C017
Figure 41. No Phase Reversal
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Feature Description (continued)
8.3.3 Input Bias Current Clock Feedthrough
Zero-drift amplifiers such as the OPAx189 use switching on the inputs to correct for the intrinsic offset and drift of
the amplifier. Charge injection from the integrated switches on the inputs can introduce short transients in the
input bias current of the amplifier. The extremely short duration of these pulses prevents the pulses from
amplifying, however the pulses may be coupled to the output of the amplifier through the feedback network. The
most effective method to prevent transients in the input bias current from producing additional noise at the
amplifier output is to use a low-pass filter such as an RC network.
8.3.4 EMI Rejection
The OPAx189 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI
interference from sources such as wireless communications and densely-populated boards with a mix of analog
signal chain and digital components. EMI immunity can be improved with circuit design techniques; the OPAx189
benefits from these design improvements. Texas Instruments has developed the ability to accurately measure
and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to
6 GHz. Figure 42 shows the results of this testing on the OPAx189. Table 2 lists the EMIRR +IN values for the
OPAx189 at particular frequencies commonly encountered in real-world applications. Applications listed in
Table 2 may be centered on or operated near the particular frequency shown. Detailed information can also be
found in EMI Rejection Ratio of Operational Amplifiers (SBOA128), available for download from www.ti.com.
120
EMIRR IN+ (dB)
100
80
60
40
20
0
10M
100M
1G
Frequency (Hz)
10G
C005
Figure 42. EMIRR Testing
Table 2. OPAx189 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION AND ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency
(UHF) applications
48.4 dB
900 MHz
Global system for mobile communications (GSM) applications, radio
communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF
applications
52.8 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, L-band
(1 GHz to 2 GHz)
69.1 dB
2.4 GHz
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications,
industrial, scientific and medical (ISM) radio band, amateur radio and satellite, Sband (2 GHz to 4 GHz)
88.9 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
82.5 dB
802.11a, 802.11n, aero communication and navigation, mobile communication,
space and satellite operation, C-band (4 GHz to 8 GHz)
95.5 dB
5 GHz
20
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The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many op amps is a change in the offset voltage as a result of RF
signal rectification. An op amp that is more efficient at rejecting this change in offset as a result of EMI has a
higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in many ways, but this
section provides the EMIRR +IN, which specifically describes the EMIRR performance when the RF signal is
applied to the noninverting input pin of the op amp. In general, only the noninverting input is tested for EMIRR for
the following three reasons:
• Op amp input pins are known to be the most sensitive to EMI, and typically rectify RF signals better than the
supply or output pins.
• The noninverting and inverting op amp inputs have symmetrical physical layouts and exhibit nearly matching
EMIRR performance
• EMIRR is more simple to measure on noninverting pins than on other pins because the noninverting input
terminal can be isolated on a PCB. This isolation allows the RF signal to be applied directly to the
noninverting input terminal with no complex interactions from other components or connecting PCB traces.
High-frequency signals conducted or radiated to any pin of the operational amplifier may result in adverse
effects, as the amplifier would not have sufficient loop gain to correct for signals with spectral content outside the
bandwidth. Conducted or radiated EMI on inputs, power supply, or output may result in unexpected DC offsets,
transient voltages, or other unknown behavior. Take care to properly shield and isolate sensitive analog nodes
from noisy radio signals and digital clocks and interfaces.
The EMIRR +IN of the OPAx189 is plotted versus frequency as shown in Figure 42. If available, any dual and
quad op amp device versions have nearly similar EMIRR +IN performance. The OPAx189 unity-gain bandwidth
is 14 MHz. EMIRR performance below this frequency denotes interfering signals that fall within the op amp
bandwidth.
8.3.5 EMIRR +IN Test Configuration
Figure 43 shows the circuit configuration for testing the EMIRR +IN. An RF source is connected to the op amp
noninverting input terminal using a transmission line. The op amp is configured in a unity-gain buffer topology
with the output connected to a low-pass filter (LPF) and a digital multimeter (DMM). A large impedance mismatch
at the op amp input causes a voltage reflection; however, this effect is characterized and accounted for when
determining the EMIRR IN+. The multimeter samples and measures the resulting DC offset voltage. The LPF
isolates the multimeter from residual RF signals that may interfere with multimeter accuracy.
Ambient temperature: 25Û&
V+
±
Low-Pass
Filter
50
+
RF Source
DC Bias: 0 V
Modulation: None (CW)
Frequency Sweep: 201 pt. Log
V±
Sample /
Averaging
Digital
Multimeter
Not shown: 0.1 µF and 10 µF supply decoupling
Figure 43. EMIRR +IN Test Configuration
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8.3.6 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect from accidental
ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is
helpful. See Figure 44 for an illustration of the ESD circuits contained in the OPAx189 (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device
internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit
operation.
(2)
TVS
RF
V+
RI
ESD CurrentSteering Diodes
IN
(3)
RS
Op Amp
Core
+IN
Edge-Triggered ESD
Absorption Circuit
ID
VIN
OUT
RL
(1)
V±
(2)
TVS
(1)
VIN = V+ + 500 mV
(2)
TVS: 40 V > VTVSBR (min) > V+ ; where VTVSBR
breakdown voltage
(3)
Suggested value is approximately 5 kΩ in overvoltage conditions.
(min)
is the minimum specified value for the transient voltage suppressor
Figure 44. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, highcurrent pulse while discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device may activate. The
absorption device has a trigger or threshold voltage that is above the normal operating voltage of the OPAx189
but below the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly
activates and clamps the voltage across the supply rails to a safe level.
22
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When the operational amplifier connects into a circuit (as shown in Figure 44), the ESD protection components
are intended to remain inactive and do not become involved in the application circuit operation. However,
circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. Should
this condition occur, there is a risk that some internal ESD protection circuits may be biased on, and conduct
current. Any such current flow occurs through steering-diode paths and rarely involves the absorption device.
Figure 44 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the
current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier, and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input while
the power supplies V+ or V– are at 0 V. Again, this question depends on the supply characteristic while at 0 V, or
at a level below the input signal amplitude. If the supplies appear as high impedance, then the operational
amplifier supply current may be supplied by the input source through the current-steering diodes. This state is not
a normal bias condition; the amplifier most likely does not operate normally. If the supplies are low impedance,
then the current through the steering diodes can become quite high. The current level depends on the ability of
the input source to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, external zener diodes must be
added to the supply pins, as shown in Figure 44. The zener voltage must be selected such that the diode does
not turn on during normal operation. However, the zener voltage must be low enough so that the zener diode
conducts if the supply pin begins to rise above the safe operating supply voltage level.
8.3.7 MUX-Friendly Inputs
The OPAx189 features a proprietary input stage design that allows an input differential voltage to be applied
while maintaining high input impedance. Typically, high-voltage CMOS or bipolar-junction input amplifiers feature
anti-parallel diodes that protect input transistors from large VGS voltages that may exceed the semiconductor
process maximum and permanently damage the device. Large VGS voltages can be forced when applying a large
input step, switching between channels, or attempting to use the amplifier as a comparator.
OPAx189 solves these problems with a switched-input technique that prevents large input bias currents when
large differential voltages are applied. This solves many issues seen in switched or multiplexed applications,
where large disruptions to RC filtering networks are caused by fast switching between large potentials. OPAx189
offers outstanding settling performance due to these design innovations and built-in slew rate boost and wide
bandwidth. The OPAx189 can also be used as a comparator. Differential and common-mode Absolute Maximum
Ratings still apply relative to the power supplies.
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8.3.8 Noise Performance
Figure 45 shows the total circuit noise for varying source impedances with the operational amplifier in a unitygain configuration (with no feedback resistor network and therefore no additional noise contributions). The
OPAx189 and OPA211 are shown with total circuit noise calculated. The op amp itself contributes both a voltage
noise component and a current noise component. The voltage noise is commonly modeled as a time-varying
component of the offset voltage. The current noise is modeled as the time-varying component of the input bias
current and reacts with the source resistance to create a voltage component of noise. Therefore, the lowest noise
op amp for a given application depends on the source impedance. For low source impedance, current noise is
negligible, and voltage noise generally dominates. The OPAx189 family has both low voltage noise and low
current noise because of the CMOS input of the op amp. As a result, the current noise contribution of the
OPAx189 series is negligible for any practical source impedance, which makes this device the better choice for
applications with high source impedance.
The equation in Figure 45 shows the calculation of the total circuit noise, with these parameters:
• en = voltage noise
• in = current noise
• RS = source impedance
• k = Boltzmann's constant = 1.38 × 10–23 J/K
• T = temperature in degrees Kelvin (K)
Voltage Noise Spectral Density, EO (V/Hz1/2)
For more details on calculating noise, see Basic Noise Calculations.
10µ
OPA211
1µ
100n
OPAx189
10n
1n
RS = 3.6 kŸ
Resistor Noise
0.1n
1
10
100
1k
10k
100k
1M
10M
Source Resistance, RS (Ÿ)
Copyright © 2017, Texas Instruments Incorporated
C003
RS = 3.6 kΩ is indicated in Figure 45.
This is the source impedance above which OPAx189 is a lower noise option than the OPA211.
Figure 45. Noise Performance of the OPAx189 and OPA211 in Unity-Gain Buffer Configuration
8.3.9 Basic Noise Calculations
Low-noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in
many cases; consider the effect of source resistance on overall op amp noise performance. Total noise of the
circuit is the root-sum-square combination of all noise components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of the
resistance. This function is plotted in Figure 45. The source impedance is usually fixed; consequently, select the
op amp and the feedback resistors to minimize the respective contributions to the total noise.
Figure 46 illustrates both noninverting (A) and inverting (B) op amp circuit configurations with gain. In circuit
configurations with gain, the feedback network resistors also contribute noise. In general, the current noise of the
op amp reacts with the feedback resistors to create additional noise components. However, the extremely low
current noise of the OPAx189 means that the current noise contribution can be neglected.
The feedback resistor values can generally be chosen to make these noise sources negligible. Low impedance
feedback resistors load the output of the amplifier. The equations for total noise are shown for both
configurations.
24
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(A) Noise in Noninverting Gain Configuration
R1
Noise at the output is given as EO, where
R2
GND
±
EO
+
RS
+
±
VS
Source
GND
'1 = l1 +
:2;
A5 = ¥4 „ G$ „ 6(-) „ 45
d
:3;
A41 æ42 = ¨4 „ G$ „ 6(-) „ d
8
41 „ 42
h d
h
41 + 42
¾*V
Thermal noise of R1 || R2
:4;
G$ = 1.38065 „ 10F23
Boltzmann Constant
:5;
,
h
-
6(-) = 237.15 + 6(°%)
(B) Noise in Inverting Gain Configuration
R1
RS
R2
h
>-?
Thermal noise of RS
Temperature in kelvins
:45 + 41 ; „ 42
42
2
p „ ¨:A0 ;2 + kA41 +45 æ42 o + FE0 „ H
IG
45 + 41
45 + 41 + 42
:6;
'1 = l1 +
+
:7;
:45 + 41 ; „ 42
8
I d
A41 +45 æ42 = ¨4 „ G$ „ 6(-) „ H
h
45 + 41 + 42
¾*V Thermal noise of (R1 + RS) || R2
GND
:8;
G$ = 1.38065 „ 10F23
:9;
6(-) = 237.15 + 6(°%)
±
+
±
d
8
¾*V
> 84/5 ?
Noise at the output is given as EO, where
EO
VS
42
41 „ 42 2
2
p „ ¨:A5 ;2 + :A0 ;2 + kA41 æ42 o + :E0 „ 45 ;2 + lE0 „ d
hp
41
41 + 42
:1;
Source
GND
d
,
h
-
2
> 84/5 ?
Boltzmann Constant
>-?
Temperature in kelvins
Copyright © 2017, Texas Instruments Incorporated
(1)
en is the voltage noise spectral density of the amplifier. For the OPAx189 series of operational amplifiers, en = 5.2 nV/
√Hz at 1 kHz.
(2)
in is the current noise spectral density of the amplifier. For the OPAx189 series of operational amplifiers, in = 165 fA/
√Hz at 1 kHz.
(3)
For additional resources on noise calculations visit TI's Precision Labs Series.
Figure 46. Noise Calculation in Gain Configurations
8.4 Device Functional Modes
The OPAx189 has a single functional mode, and is operational when the power-supply voltage is greater than
4.5 V (±2.25 V). The maximum power supply voltage for the OPAx189 is 36 V (±18 V).
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The OPAx189 operational amplifier combines precision offset and drift with excellent overall performance,
making the series ideal for many precision applications. The precision offset drift of only 0.005 µV/°C provides
stability over the entire temperature range. In addition, the device pairs excellent CMRR, PSRR, and AOL dc
performance with outstanding low-noise operation. As with all amplifiers, applications with noisy or highimpedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF
capacitors are adequate.
The following application examples highlight only a few of the circuits where the OPAx189 can be used.
9.2 Typical Applications
9.2.1 25-kHz Low-Pass Filter
R4
2.94 k
C5
1 nF
R1
590
R3
499
Input
C2
39 nF
±
Output
+
OPAx189
Copyright © 2017, Texas Instruments Incorporated
Figure 47. 25-kHz Low-Pass Filter
9.2.1.1 Design Requirements
Low-pass filters are commonly employed in signal processing applications to reduce noise and prevent aliasing.
The OPAx189 devices are ideally suited to construct high-speed, high-precision active filters. Figure 47 shows a
second-order, low-pass filter commonly encountered in signal processing applications.
Use the following parameters for this design example:
• Gain = 5 V/V (inverting gain)
• Low-pass cutoff frequency = 25 kHz
• Second-order Chebyshev filter response with 3-dB gain peaking in the passband
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Typical Applications (continued)
9.2.1.2 Detailed Design Procedure
The infinite-gain multiple-feedback circuit for a low-pass network function is shown in Figure 47. Use Equation 1
to calculate the voltage transfer function.
1 R1R3C2C5
Output
s
2
Input
s
s C2 1 R1 1 R3 1 R4 1 R3R4C2C5
(1)
This circuit produces a signal inversion. For this circuit, the gain at dc and the low-pass cutoff frequency are
calculated by Equation 2:
R4
Gain
R1
fC
1
2S
1 R3R 4 C2C5
(2)
®
Software tools are readily available to simplify filter design. WEBENCH Filter Designer is a simple, powerful,
and easy-to-use active filter design program. The WEBENCH® Filter Designer lets the user create optimized
filter designs using a selection of TI operational amplifiers and passive components from TI's vendor partners.
Available as a web based tool from the WEBENCH Design Center, WEBENCH Filter Designer allows board-level
designers to create, optimize, and simulate complete multistage active filter solutions within minutes.
9.2.1.3 Application Curve
20
Gain (db)
0
-20
-40
-60
100
1k
10k
Frequency (Hz)
100k
1M
Figure 48. OPAx189 Second-Order, 25-kHz, Chebyshev, Low-Pass Filter
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Typical Applications (continued)
9.2.2 Discrete INA + Attenuation for ADC With 3.3-V Supply
NOTE
The TINA-TI files shown in the following sections require that either the TINA software
(from DesignSoft™) or TINA-TI software be installed. Download the free TINA-TI software
from the TINA-TI folder.
Figure 49 shows an example of how the OPAx189 is used as a high-voltage, high-impedance front-end for a
precision, discrete instrumentation amplifier with attenuation. The INA159 provides the attenuation that allows
this circuit to simply interface with 3.3-V or 5-V analog-to-digital converters (ADCs). Click the following link
download the TINA-TI file: Discrete INA.
15 V
VOUTP
OPAx189
5V
VDIFF / 2
- 15 V
RP
10 NŸ
Ref 1
VCM
10V
Ref 2
RG
500 Ÿ
+
VOUT(1)
INA159
Sense
±VDIFF / 2
15 V
OPAx189
RN
10 NŸ
VOUTN
15 V
Copyright © 2017, Texas Instruments Incorporated
(1)
VOUT = VDIFF × (41 / 5) + (Ref 1) / 2.
Figure 49. Discrete INA + Attenuation for ADC With 3.3-V Supply
28
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Typical Applications (continued)
9.2.3 Bridge Amplifier
Figure 50 shows the basic configuration for a bridge amplifier. Click the following link to download the TINA-TI
file: Bridge Amplifier Circuit.
VEX
R1
R
R
R
R
+5V
VOUT
VREF
Copyright © 2017, Texas Instruments Incorporated
Figure 50. Bridge Amplifier
9.2.4 Low-Side Current Monitor
Figure 51 shows the OPAx189 configured in a low-side current-sensing application. The load current (ILOAD)
creates a voltage drop across the shunt resistor (RSHUNT). This voltage is amplified by the OPAx189, with a gain
of 201. In this example the load current is set from 0 A to 500 mA, which corresponds to an output voltage range
from 0 V to 10 V. The output range can be adjusted by changing the shunt resistor or gain of the configuration.
Click the following link to download the TINA-TI file: Current-Sensing Circuit.
VSYSTEM
Load
15 V
+
VOUT = ILOAD * RSHUNT(1 + RF / RIN)
OPAx189
ILOAD
RSHUNT
100 m
VOUT
VOUT / ILOAD= 1 V / 49.75 mA
±
RIN
100
Copyright © 2017, Texas Instruments Incorporated
RF
20 k
CF
150
pF
Figure 51. Low-Side Current Monitor
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Typical Applications (continued)
9.2.5 Programmable Power Supply
Figure 52 shows the OPAx189 configured as a precision programmable power supply using the 16-bit, voltage
output DAC8581 and the OPA548 high-current amplifier. This application amplifies the digital-to-analog converter
(DAC) voltage by a value of five, and handles a large variety of capacitive and current loads. The OPAx189 in
the front-end provides precision and low drift across a wide range of inputs and conditions. Click the following
link to download the TINA-TI file: Programmable Power-Supply Circuit.
C1
500 nF
R1
10 k
R4
40 k
R2
1k
GND
C2
500 nF
+30V
+15V
±
R3
10 k
±
Output = ± 25V
+
DAC8581
VOUT
OPA548
+
OPAx189
±30V
±15V
Input = ± 5V
Copyright © 2017, Texas Instruments Incorporated
Figure 52. Programmable Power Supply
9.2.6 RTD Amplifier With Linearization
See Analog Linearization of Resistance Temperature Detectors (SLYT442) for an in-depth analysis of Figure 53.
Click the following link to download the TINA-TI file: RTD Amplifier with Linearization.
15 V
(5 V)
Out
REF5050
In
1 µF
1 µF
R2
49.1 kŸ
R3
60.4 kŸ
R1
4.99 kŸ
OPAx189
V OUT
0°C = 0 V
200°C = 5 V
R5
(1)
105.8 kŸ
RTD
Pt100
R4
1 kŸ
Copyright © 2017, Texas Instruments Incorporated
(1)
R5 provides positive-varying excitation to linearize output.
Figure 53. RTD Amplifier With Linearization
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9.3 System Examples
9.3.1 24-Bit, Delta-Sigma, Differential Load Cell or Strain Gauge Sensor Signal Conditioning
OPAx189 is used in a 24-bit, differential load cell or strain gauge sensor signal conditioning system alongside the
ADS1225. A pair of OPAx189 amplifiers are configured in a two-amp instrumentation amplifier (IA) configuration
and are band-limited to reduce noise and allow heavy capacitive drive. The load cell is powered by an excitation
voltage (denoted VEX) of 5-V and provides a differential voltage proportional to force applied. The differential
voltage can be quite small and both outputs are biased to VEX / 2.
In this example the OPAx189 is employed here due to the excellent input offset voltage (0.4 µV) and input offset
voltage drift (0.005 µV/°C), the low broadband noise (5.2 nV/√Hz) and zero-flicker noise, and excellent linearity
and high input impedance. The two-amp IA configuration removes the dc bias and amplifies the differential signal
of interest and drives the 24-bit, delta-sigma ADS1225 analog-to-digital converter (ADC) for acquisition and
conversion. The ADS1225 features a 100-SPS data rate, single-cycle settling, and simple conversion control with
the dedicated START pin.
G=1+
C4
0.1 nF
2 ® RF
RG
C5
0.1 µF
C6
0.1 nF
GND
GND
+
GND
GND
OPAx189
VREFN
±
RTRACE
VREFP
C1
10 µF
RF
10 k
+OUT
+SENSE
DVDD
R1
1k
-SENSE
+5V
AINP1
GND
DVDD
SCLK
DRDY / DOUT
RG
50
C2
1 µF
CF
1 µF
+
+3V
START
CF
1 µF
±
+5V
RTRACE
+15V
VEX
AVDD
ADS1225
R2
1k
Load Cell
MSP430xxx
or other host
AINN1
±OUT
MODE
+3V
BUFEN
RF
10 k
GND
TEMPEN
C3
10 µF
+15V
±
GND
GND
GND
OPAx189
+
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 54. 24-Bit, Differential Load Cell or Strain Gauge Sensor Signal Conditioning Schematic
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10 Power Supply Recommendations
The OPAx189 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to +125°C. The Typical Characteristics presents parameters that can exhibit significant variance with
regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 40 V can permanently damage the device (see the
Absolute Maximum Ratings).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or
high-impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.
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11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp
itself. Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the
analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds paying attention to the flow of the ground current. For more detailed
information, seeThe PCB is a component of op amp design.
• To reduce parasitic coupling, run the input traces as far away as possible from the supply or output
traces. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better
as opposed to in parallel with the noisy trace.
• Place the external components as close as possible to the device. As illustrated in Figure 55, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
• For best performance, TI recommends cleaning the PCB following board assembly.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, TI recommends baking the PCB
assembly to remove moisture introduced into the device packaging during the cleaning process. A low
temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
11.2 Layout Example
GND
+V
R3
Use ground pours for
shielding the input
signal pairs
Place bypass
capacitors as close to
device as possible
(avoid use of vias)
C3
C4
C3
R3
IN±
1
NC
NC
C4
8
IN±
IN+
1
NC
NC
8
2
±IN
V+
7
3
+IN
OUT
6
4
V±
NC
5
+V
R1
R1
2
±IN
±
V+
7
3
+IN
+
OUT
6
R2
4
V±
NC
5
OUT
OUT
R2
-V
C1
IN+
R4
GND
R4
C2
Place components
close to device and to
each other to reduce
parasitic errors
C1
-V
Use a lowESR,ceramic bypass
capacitor
C2
Copyright © 2017, Texas Instruments Incorporated
Figure 55. Operational Amplifier Board Layout for Difference Amplifier Configuration
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 TINA-TI™ (Free Software Download)
TINA-TI™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINATI™ is a free, fully-functional version of the TINA™ software, preloaded with a library of macromodels in addition
to a range of both passive and active models. TINA-TI™ provides all the conventional dc, transient, and
frequency domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI™ offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI™
software be installed. Download the free TINA-TI™ software from the TINA-TI™ folder.
12.1.1.2 TI Precision Designs
TI Precision Designs are available online at http://www.ti.com/ww/en/analog/precision-designs/. TI Precision
Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of
operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured
performance of many useful circuits.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Zero-drift Amplifiers: Features and Benefits application brief
• Texas Instruments, The PCB is a component of op amp design technical brief
• Texas Instruments, Operational amplifier gain stability, Part 3: AC gain-error analysis technical brief
• Texas Instruments, Operational amplifier gain stability, Part 2: DC gain-error analysis technical brief
• Texas Instruments, Using infinite-gain, MFB filter topology in fully differential active filters technical brief
• Texas Instruments, Op Amp Performance Analysis application bulletin
• Texas Instruments, Single-Supply Operation of Operational Amplifiers application bulletin
• Texas Instruments, Tuning in Amplifiers application bulletin
• Texas Instruments, Shelf-Life Evaluation of Lead-Free Component Finishes application report
• Texas Instruments, Feedback Plots Define Op Amp AC Performance application bulletin
• Texas Instruments, EMI Rejection Ratio of Operational Amplifiers (With OPA333 and OPA333-Q1 as an
Example) application report
• Texas Instruments, Analog linearization of resistance temperature detectors technical brief
• Texas Instruments, TI Precision Design TIPD102 High-Side Voltage-to-Current (V-I) Converter reference
guide
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12.3 Related Links
Table 3 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA189
Click here
Click here
Click here
Click here
Click here
OPA2189
Click here
Click here
Click here
Click here
Click here
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.6 Trademarks
TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
DesignSoft, TINA are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
12.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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35
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA189ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA189
OPA189IDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1CTV
OPA189IDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1CTV
OPA189IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1CS6
OPA189IDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1CS6
OPA189IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA189
OPA2189ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
OP2189
OPA2189IDGKR
PREVIEW
VSSOP
DGK
8
2500
TBD
Call TI
Call TI
-40 to 125
OPA2189IDGKT
PREVIEW
VSSOP
DGK
8
250
TBD
Call TI
Call TI
-40 to 125
OPA2189IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
POPA2189IDGKR
ACTIVE
VSSOP
DGK
8
2500
TBD
Call TI
Call TI
-40 to 125
OP2189
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
6-Dec-2019
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jun-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
OPA189IDBVR
SOT-23
3000
180.0
DBV
5
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
8.4
3.23
3.17
1.37
4.0
W
Pin1
(mm) Quadrant
8.0
Q3
OPA189IDBVT
SOT-23
DBV
5
250
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
OPA189IDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA189IDGKT
VSSOP
DGK
8
250
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA189IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
OPA2189IDR
SOIC
D
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jun-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA189IDBVR
SOT-23
DBV
5
3000
213.0
191.0
35.0
OPA189IDBVT
SOT-23
DBV
5
250
213.0
191.0
35.0
OPA189IDGKR
VSSOP
DGK
8
2500
366.0
364.0
50.0
OPA189IDGKT
VSSOP
DGK
8
250
366.0
364.0
50.0
OPA189IDR
SOIC
D
8
2500
367.0
367.0
35.0
OPA2189IDR
SOIC
D
8
2500
366.0
364.0
50.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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