Texas Instruments | BUF634A 36-V, 210-MHz, 250-mA Output, High-Speed Buffer (Rev. A) | Datasheet | Texas Instruments BUF634A 36-V, 210-MHz, 250-mA Output, High-Speed Buffer (Rev. A) Datasheet

Texas Instruments BUF634A 36-V, 210-MHz, 250-mA Output, High-Speed Buffer (Rev. A) Datasheet
Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
BUF634A
SBOS948A – FEBRUARY 2019 – REVISED MAY 2019
BUF634A 36-V, 210-MHz, 250-mA Output, High-Speed Buffer
1 Features
3 Description
•
•
•
•
•
•
•
•
•
The BUF634A is a high-performance, high-fidelity,
open-loop buffer capable of driving 250 mA of output
current. The BUF634A is a 36-V device with
bandwidth adjustable from 35 MHz to 210 MHz by
varying the value of an external resistor between the
V– and BW pins. The BUF634A can be used as a
standalone open-loop driver, or inside the feedback
loop of a precision op amp to provide both highprecision as well as large output current drive with
improved capacitive load drive.
1
Pin-selected bandwidth: 35 MHz to 210 MHz
High output current: 250 mA
Slew rate: 3750 V/µs
Low quiescent current: 1.5 mA (35-MHz BW)
Wide supply range: ±2.25 V to ±18 V
Internal output current limit
Thermal shutdown protection
Available in SOIC-8 package
Extended temperature operation:
–40°C to +125°C
For low-power applications, the BUF634A operates
on a 1.5-mA quiescent current with a 250-mA output,
3750-V/µs slew rate, and 35-MHz bandwidth. The
device consumes 8.5-mA quiescent current in widebandwidth mode with a 210-MHz bandwidth. The
BUF634A is fully protected by an internal current limit
in its output stage and by thermal shutdown, making
the device rugged and easy to use.
2 Applications
•
•
•
•
•
•
•
•
•
•
Memory, display testers
Test equipment
Headphone drivers
Op amp current boosters
Capacitive load driver
Valve drivers
Solenoid drivers
Motor drivers
Line drivers
Video drivers
The BUF634A is an upgrade to the BUF634 with 16%
higher bandwidth and a higher slew rate at 43%
reduced supply current. See the Device Comparison
Table for a selection of unity-gain, open-loop buffers
from Texas Instruments. This device is rated to
function over the extended industrial temperature
range of –40°C to +125°C.
Device Information(1)
PART NUMBER
BUF634A
PACKAGE
SOIC (8)
BODY SIZE (NOM)
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Boost the Output Current of Any Operational
Amplifier
THD+N vs Frequency Using the BUF634A With
the OPA2810
(VO = 10 VPP, 90-kHz Measurement Bandwidth)
V+
-80
1 kQ
±
VO
VIN
Vt
Total Harmonic Distortion + Noise (dB)
1 kQ
RL = 16 :
RL = 32 :
RL = 250 :
-90
-100
-110
-120
10
100
1k
Frequency (Hz)
10k
D003
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
BUF634A
SBOS948A – FEBRUARY 2019 – REVISED MAY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
4
5
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: Wide-Bandwidth Mode ....
Electrical Characteristics: Low-Quiescent Current
Mode ..........................................................................
7.7 Typical Characteristics ..............................................
8
6
7
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 15
9
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application .................................................. 18
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 21
12 Device and Documentation Support ................. 22
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support ....................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
23
23
23
13 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (February 2019) to Revision A
•
2
Page
Changed document status from Advance Information to Production Data ........................................................................... 1
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: BUF634A
BUF634A
www.ti.com
SBOS948A – FEBRUARY 2019 – REVISED MAY 2019
5 Device Comparison Table
DEVICE
VS± (V)
IQ / Channel
(mA)
BW (MHz)
SLEW RATE
(V/µs)
VOLTAGE NOISE
(nV/√Hz)
BUF634A
±18
1.5 – 8.5
35 – 210
3750
3.4
Unity-gain, open-loop buffer
BUF634
±18
1.5 – 15
30 – 180
2000
4
Unity-gain, open-loop buffer
LMH6321
±18
11
110
1800
2.8
AMPLIFIER DESCRIPTION
Unity-gain, open-loop buffer with
adjustable current limit
6 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
BW
1
8
NC
NC
2
7
V+
VIN
3
6
VO
V–
4
5
NC
G=1
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
Bandwidth adjust pin. Connect the BW pin to the V– pin for wide-BW mode and leave the
BW pin floating for low-IQ mode. See the Adjustable Bandwidth section.
BW
1
I
NC
2, 5, 8
—
No internal connection
V–
4
I
Negative power supply
V+
7
I
Positive power supply
VIN
3
I
Input
VO
6
O
Output
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: BUF634A
3
BUF634A
SBOS948A – FEBRUARY 2019 – REVISED MAY 2019
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VS = (V+) – (V–)
Supply voltage
VIN
Input voltage
Output short-circuit (to ground)
TA
Operating ambient temperature
TJ
Junction temperature
Tstg
Storage temperature
(1)
MAX
UNIT
40 (±20)
V
Vs ± 0.5
V
Continuous
–40
–65
125
°C
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VS = (V+) – (V–)
Supply voltage
TA
Ambient temperature
(1)
MIN
NOM
MAX
UNIT
±2.25
±15
±18
V
–40
25
125 (1)
°C
Limited by RΘJA and TJ,Max for safe operation. See the Output Current section.
7.4 Thermal Information
BUF634A
THERMAL METRIC (1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
122.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
55.2
°C/W
RθJB
Junction-to-board thermal resistance
68.4
°C/W
ΨJT
Junction-to-top characterization parameter
12.1
°C/W
ΨJB
Junction-to-board characterization parameter
67.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
NA
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: BUF634A
BUF634A
www.ti.com
SBOS948A – FEBRUARY 2019 – REVISED MAY 2019
7.5 Electrical Characteristics: Wide-Bandwidth Mode
at TA = 25°C, VS = ±15 V, BW pin connected to V–, and RL = 100 Ω connected to mid-supply (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
Bandwidth, –3 dB
SR
RL = 1 kΩ
210
RL = 100 Ω
200
MHz
Bandwidth for 0.1-dB flatness
VO = 10 mVPP, RL = 100 Ω, RS = 50 Ω
50
MHz
Slew rate
VO = 20-V step, VIN-SR = 4000 V/µs
Rise and fall time
VO = 200-mV step
3750
1.3
V/µs
ns
Settling time to 0.1%
VO = 20-V step, VIN-SR = 2500 V/µs
90
ns
Settling time to 1%
VO = 20-V step, VIN-SR = 2500 V/µs
20
ns
en
Voltage noise
f = 1 kHz
3.4
nV/√Hz
in
Current noise
f = 100 kHz
0.85
pA/√Hz
HD2
2nd-harmonic distortion
VO = 2 VPP, f = 20 kHz
–77
VO = 10 VPP, f = 20 kHz
–69
HD3
3rd-harmonic distortion
VO = 2 VPP, f = 20 kHz
–77
VO = 10 VPP, f = 20 kHz
–56
dBc
dBc
DC PERFORMANCE
VOS
IB
G
Input offset voltage
TA = 25℃ (see Figure 26)
Input offset voltage drift (1)
TA = –40℃ to 125℃ (see Figure 28)
Input bias current
VIN = 0 V
36
0.25
VO = ±10 V, RL = 1 kΩ
0.95
0.99
VO = ±10 V, RL = 100 Ω
0.93
0.95
VO = ±10 V, RL = 67 Ω
0.91
0.93
Linear input voltage range
RL = 1 kΩ, IB < 10 µA
–13
Input impedance
RL = 100 Ω
Gain
65
175
mV
µV/℃
2
µA
V/V
INPUT
ZIN
13
180 || 5
V
MΩ || pF
OUTPUT
Output headroom to supplies
IO = ±10 mA
1.6
1.8
IO = ±100 mA
2.0
2.2
2.2
2.5
IO = ±150 mA
IO
Current output, continuous
±250
ISC
Short-circuit current
±375
ZO
Output impedance
DC, IO = 10 mA
V
mA
±550
5
mA
Ω
POWER SUPPLY
VS
Operating voltage range
IQ
Quiescent current
IO = 0 mA
±2.25
PSRR
Power-supply rejection ratio
VS = ±2.25 V to ±18 V
8.5
64
±18
V
12
mA
75
dB
180
℃
THERMAL SHUTDOWN
Thermal shutdown
temperature
(1)
Based on electrical characterization over temperature of 35 devices.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: BUF634A
5
BUF634A
SBOS948A – FEBRUARY 2019 – REVISED MAY 2019
www.ti.com
7.6 Electrical Characteristics: Low-Quiescent Current Mode
at TA = 25°C, VS = ±15 V, BW pin left open, and RL = 100 Ω connected to mid-supply (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
RL = 1 kΩ
35
RL = 100 Ω
31
Bandwidth for 0.1-dB flatness
VO = 10 mVPP, RL = 100 Ω, RS = 50 Ω
2.3
MHz
Slew rate
VO = 20-V step, VIN-SR = 4000 V/µs
3750
V/µs
Rise and fall time
VO = 200-mV step
Settling time to 0.1%
VO = 20-V step, VIN-SR = 2500 V/µs
Bandwidth, –3 dB
SR
MHz
4
ns
400
ns
Settling time to 1%
VO = 20-V step, VIN-SR = 2500 V/µs
90
ns
en
Voltage noise
f = 1 kHz
8.1
nV/√Hz
in
Current noise
f = 10 kHz
0.3
pA/√Hz
HD2
2nd-harmonic distortion
VO = 2 VPP, f = 20 kHz
–54
VO = 10 VPP, f = 20 kHz
–65
HD3
3rd-harmonic distortion
VO = 2 VPP, f = 20 kHz
–40
VO = 10 VPP, f = 20 kHz
–44
dBc
dBc
DC PERFORMANCE
VOS
IB
G
Input offset voltage
TA = 25℃ (see Figure 26)
Input offset voltage drift (1)
TA = –40℃ to 125℃ (see Figure 28)
Input bias current
VIN = 0 V
36
0.03
VO = ±10 V, RL = 1 kΩ
0.95
0.99
VO = ±10 V, RL = 100 Ω
0.93
0.95
VO = ±10 V, RL = 67 Ω
0.91
0.93
Linear input voltage range
RL = 1 kΩ, IB < 10 µA
–13
Input impedance
RL = 100 Ω
Gain
65
175
mV
µV/℃
0.25
µA
V/V
INPUT
ZIN
13
1400 || 5
V
MΩ || pF
OUTPUT
Output headroom to supplies
IO = ±10 mA
1.6
1.8
IO = ±100 mA
2.0
2.2
2.2
2.5
IO = ±150 mA
IO
Current output, continuous
±250
ISC
Short-circuit current
±350
ZO
Output impedance
DC, IO = 10 mA
V
mA
±550
7
mA
Ω
POWER SUPPLY
VS
Operating voltage range
IQ
Quiescent current
IO = 0
±2.25
PSRR
Power-supply rejection ratio
VS = ±2.25 V to ±18 V
1.5
64
±18
V
2.3
mA
80
dB
180
℃
THERMAL SHUTDOWN
Thermal shutdown
temperature
(1)
6
Based on electrical characterization over temperature of 35 devices.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: BUF634A
BUF634A
www.ti.com
SBOS948A – FEBRUARY 2019 – REVISED MAY 2019
7.7 Typical Characteristics
10
5
5
0
0
-10
0
-15
-10
-20
8.6 mA
6.6 mA
4.9 mA
2.7 mA
1.5 mA
-30
-40
-50
100k
1M
10M
Frequency (Hz)
100M
-5
Phase (o)
Phase (o)
-5
Normalized Gain (dB)
10
-10
-15
0
-10
-20
-30
-40oC
25oC
125oC
-40
-50
100k
1G
Normalized Gain (dB)
at TA = 25°C, VS = ±15 V, RS = 50 Ω, and RL = 100 Ω (unless otherwise noted)
1M
D001
10M
Frequency (Hz)
100M
1G
D002
Solid lines indicate wide-BW mode,
dashed lines indicate low-IQ mode
10
5
5
0
0
-10
-15
0
-10
-20
-50
100k
1M
10M
Frequency (Hz)
100M
-15
-10
-20
-30
RS = 0 :
RS = 50 :
RS = 100 :
-40
-10
0
-40
RL = 1 k:
RL = 100 :
RL = 50 :
-50
100k
1G
1M
D003
Solid lines indicate wide-BW mode,
dashed lines indicate low-IQ mode
5
0
0
-20
CL = 0 pF
CL = 47 pF
CL = 220 pF
CL = 1 nF
10M
Frequency (Hz)
100M
-5
Phase (o)
Phase (o)
-10
Normalized Gain (dB)
10
5
-15
0
1M
D004
10
-10
-50
100k
1G
Figure 4. Gain and Phase vs Frequency and
Load Resistance
-5
-40
100M
Solid lines indicate wide-BW mode,
dashed lines indicate low-IQ mode
Figure 3. Gain and Phase vs Frequency and
Source Resistance
-30
10M
Frequency (Hz)
-10
0
-20
-30
-40
1G
-15
-10
CL = 0 pF
CL = 47 pF
CL = 220 pF
CL = 1 nF
-50
100k
1M
D005
Low-IQ mode
10M
Frequency (Hz)
100M
Normalized Gain (dB)
-30
-5
Phase (o)
Phase (o)
-5
Normalized Gain (dB)
10
Normalized Gain (dB)
Figure 2. Gain and Phase vs Frequency and Temperature
Figure 1. Gain and Phase vs Frequency and
Quiescent Current
1G
D006
Wide-BW mode
Figure 5. Gain and Phase vs Frequency and
Load Capacitance
Figure 6. Gain and Phase vs Frequency and
Load Capacitance
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: BUF634A
7
BUF634A
SBOS948A – FEBRUARY 2019 – REVISED MAY 2019
www.ti.com
Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RS = 50 Ω, and RL = 100 Ω (unless otherwise noted)
100
5
90
Phase (o)
-5
-10
0
-15
-10
-20
VS = ±2.25 V
VS = ±5 V
VS = ±12 V
VS = ±18 V
-30
-40
-50
100k
1M
10M
Frequency (Hz)
100M
Normalized Gain (dB)
0
Power Supply Rejection Ratio (dB)
10
80
70
60
50
40
30
20
PSRR+
PSRR
10
0
10
1G
100
Solid lines indicate wide-BW mode,
dashed lines indicate low-IQ mode
D008
Low-IQ
Wide-BW
Current Noise (pA/—Hz)
Voltage Noise (nV/—Hz)
10M
100
10
1k
Frequency (Hz)
1M
Figure 8. PSRR vs Frequency
Low-IQ
Wide-BW
100
10k
100k
Frequency (Hz)
Solid lines indicate wide-BW mode,
dashed lines indicate low-IQ mode
Figure 7. Gain and Phase vs Frequency and
Power-Supply Voltage
1
10
1k
D007
10k
10
1
0.1
0.1
100k
1
10
D011
Figure 9. Voltage Noise Density vs Frequency
100
1k
10k
Frequency (Hz)
100k
1M
10M
D017
Figure 10. Current Noise Density vs Frequency
-40
-40
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-50
-60
-70
-80
-90
-100
-110
-120
100
-60
-70
HD2
HD3
HD2
HD3
1k
10k
100k
Frequency (Hz)
1M
10M
-80
100
1k
D012
Wide-BW mode, VIN = 10 VPP, RL = 1 kΩ
Figure 11. Harmonic Distortion vs Frequency
8
-50
10k
100k
Frequency (Hz)
1M
10M
D013
Wide-BW mode, VIN = 10 VPP, RL = 100 Ω
Figure 12. Harmonic Distortion vs Frequency
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: BUF634A
BUF634A
www.ti.com
SBOS948A – FEBRUARY 2019 – REVISED MAY 2019
Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RS = 50 Ω, and RL = 100 Ω (unless otherwise noted)
-30
-30
Harmonic Distortion (dBc)
-50
-60
-70
-80
-90
-40
-50
-60
HD2
HD3
HD2
HD3
-100
100
1k
10k
100k
Frequency (Hz)
1M
-70
100
10M
1k
Low-IQ mode, VIN = 10 VPP, RL = 1 kΩ
Figure 13. Harmonic Distortion vs Frequency
D015
Figure 14. Harmonic Distortion vs Frequency
RL = 1 k:
RL = 100 :
Low-IQ
Wide-BW
400
180
Limit Current (mA)
-3 dB Bandwidth (MHz)
10M
425
210
150
120
90
375
350
325
300
60
30
10
100
1k
10k
Resistance (:)
100k
275
-50
1M
-12
13.5
-12.4
13.2
-12.8
12.9
-13.2
12.6
-13.6
12.3
50
100
150
|Output Current| (mA)
200
-14
250
Output Voltage Swing - Sinking (V)
-11.6
TA = 25oC
TA = -40oC
TA = 125oC
Figure 17. Output Voltage Swing vs Output Current
25
50
75
100
Junction Temperature (oC)
125
150
D016
14.1
-11.6
13.8
-12
13.5
-12.4
13.2
-12.8
12.9
-13.2
12.6
-13.6
TA = -40oC
TA = 25oC
TA = 125oC
12.3
-14
12
0
50
D035
Wide-BW mode (solid lines indicate sourcing current,
dashed lines indicate sinking current)
0
Figure 16. Short-Circuit Current vs Temperature
Output Voltage Swing - Sourcing (V)
14.1
13.8
-25
D001
Figure 15. Small-Signal Bandwidth vs Bandwidth
Adjustment Resistance
Output Voltage Swing - Sourcing (V)
1M
Low-IQ mode, VIN = 10 VPP, RL = 100 Ω
240
0
10k
100k
Frequency (Hz)
D014
100
150
|Output Current| (mA)
200
Output Voltage Swing - Sinking (V)
Harmonic Distortion (dBc)
-40
-14.4
250
D034
Low-IQ mode (solid lines indicate sourcing current,
dashed lines indicate sinking current)
Figure 18. Output Voltage Swing vs Output Current
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: BUF634A
9
BUF634A
SBOS948A – FEBRUARY 2019 – REVISED MAY 2019
www.ti.com
Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RS = 50 Ω, and RL = 100 Ω (unless otherwise noted)
12
0.2
Input and Output Voltage (V)
8
Input and Output Voltage (V)
VIN
VO-Low-IQ
VO-Wide-BW
10
6
4
2
0
-2
-4
-6
-8
VIN
VO-Low-IQ
VO-Wide-BW
0.15
0.1
0.05
0
-0.05
-0.1
-10
-12
-0.15
Time (50 ns/div)
Time (20 ns/div)
D010
D009
Figure 19. Large-Signal Transient Response
Figure 20. Small-Signal Transient Response
10
100
Low-IQ: Sinking
Low-IQ: Sourcing
Wide-BW: Sinking
Wide-BW: Sourcing
Low-IQ
Wide-BW
Output Impedance (:)
Output Impedance (:)
8
10
6
4
2
0
10
1
0
50
100
150
Output Current (mA)
200
250
100
1k
10k
100k
1M
Frequency (Hz)
D030
f = 100 kHz
100M
D036
IO = 100 mA
Figure 21. Output Impedance vs Output Current
Figure 22. Output Impedance vs Frequency
60
6000
50
5000
No. of Units in Each Bin
40
30
20
TA = 40oC
TA = 25oC
TA = 85oC
TA = 125oC
10
4000
3000
2000
1000
48
46
44
42
36
40
32
38
28
36
16
20
24
Supply Voltage (V)
34
12
32
8
30
4
28
0
0
26
Offset Voltage (mV)
10M
Offset Voltage (mV)
D020
D032
14000 devices, µ = 35.7 mV, σ = 2.15 mV
Figure 23. Offset Voltage vs Supply Voltage
10
Figure 24. Offset Voltage Distribution Histogram
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: BUF634A
BUF634A
www.ti.com
SBOS948A – FEBRUARY 2019 – REVISED MAY 2019
Typical Characteristics (continued)
55
14
50
12
No. of Units in Each Bin
45
40
35
30
10
8
6
4
2
25
D021
155
150
145
140
150
135
125
130
25
50
75
100
Ambient Temperature (oC)
125
0
120
-25
110
0
20
-50
115
Offset Voltage (mV)
at TA = 25°C, VS = ±15 V, RS = 50 Ω, and RL = 100 Ω (unless otherwise noted)
D031
Input Offset Drift (PV/oC)
35 devices
TA = –40°C to +125°C, 35 devices, µ = 134 μV/°C, σ = 7.4 μV/°C
Figure 26. Offset Voltage Drift Distribution Histogram
Figure 25. Offset Voltage vs Temperature
0.2
1
0.15
0.8
Input Bias Current (PA)
Input Bias Current (PA)
0.6
0.1
0.05
0
-0.05
-0.1
0.4
0.2
0
-0.2
-0.4
-0.6
-0.15
-0.8
-0.2
-1
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
Supply Voltage (V)
D022
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
Supply Voltage (V)
D023
Low-IQ mode, 35 devices
Wide-BW mode, 35 devices
Figure 27. Input Bias Current vs Supply Voltage
Figure 28. Input Bias Current vs Supply Voltage
9
Quiescent Current (mA)
Quiescent Current (mA)
1.6
1.5
1.4
1.3
1.2
8.5
8
7.5
7
4
8
12
16
20
24
Supply Voltage (V)
28
32
36
4
8
D024
Low-IQ mode, 35 devices
12
16
20
24
Supply Voltage (V)
28
32
36
D025
Wide-BW mode, 35 devices
Figure 29. Quiescent Current vs Supply Voltage
Figure 30. Quiescent Current vs Supply Voltage
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: BUF634A
11
BUF634A
SBOS948A – FEBRUARY 2019 – REVISED MAY 2019
www.ti.com
Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RS = 50 Ω, and RL = 100 Ω (unless otherwise noted)
9.5
Quiescent Current (mA)
Quiescent Current (mA)
1.8
1.7
1.6
1.5
9.1
8.7
8.3
7.9
1.4
-50
-25
0
25
50
75
Ambient Temperature (oC)
100
7.5
-50
125
-25
0
25
50
75
Ambient Temperature (oC)
D028
Low-IQ mode, 35 devices
D029
Figure 32. Quiescent Current vs Temperature
0.97
0.955
0.965
0.95
0.96
Gain (V/V)
Gain (V/V)
Figure 31. Quiescent Current vs Temperature
0.945
0.955
0.94
0.95
0.935
0.945
-25
125
Wide-BW mode, 35 devices
0.96
0.93
-50
100
0
25
50
75
Ambient Temperature (oC)
100
125
0.94
-50
-25
0
25
50
75
Ambient Temperature (oC)
D026
Low-IQ mode, 35 devices
100
125
D027
Wide-BW mode, 35 devices
Figure 33. Buffer Gain vs Temperature
Figure 34. Buffer Gain vs Temperature
Power Dissipation (W)
2
1.5
1
0.5
0
-50
-25
0
25
50
75
100
Ambient Temperature (oC)
125
150
D033
Figure 35. Maximum Power Dissipation vs Temperature
12
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: BUF634A
BUF634A
www.ti.com
SBOS948A – FEBRUARY 2019 – REVISED MAY 2019
8 Detailed Description
8.1 Overview
The BUF634A is a high-speed, unity-gain, open-loop buffer that can be used in a wide range of applications
requiring large output current drive or large slew rates. The BUF634A can operate on power supplies ranging
from 4.5 V to 36 V and includes an internal output current limiting feature as well as thermal shutdown, thereby
making the device rugged and easy to use.
The bandwidth of the BUF634A can be adjusted by connecting a resistor between the V– and BW pins. Its power
scaling with bandwidth makes the device suitable for use in portable battery-powered applications. See the
Adjustable Bandwidth section for a description of the relationship between bandwidth adjustment resistance and
the device –3-dB bandwidth.
The BUF634A can be used in a composite loop (inside the feedback loop of op amps) to increase output current,
eliminate thermal feedback, and improve capacitive load drive. See Figure 44 for this circuit. Decoupling the
high-power output current stage from the precision amplifier gives high precision performance by eliminating
thermal effects on input offset of the composite circuit. With a large slew rate of 3750 V/µs, the BUF634A can
quickly reproduce its input signal at its output without adding considerable delay when used in a composite loop.
When used in a composite loop, the outer amplifier controls the circuit precision and distortion performance and
the buffer augments the circuit output current drive capability.
See the Functional Block Diagram section for a simplified circuit diagram of the open-loop complementary
follower design of the BUF634A.
8.2 Functional Block Diagram
V+
Thermal
Shutdown
I1(1)
50
VO
VIN
1.2 k
8k
BW
V±
NOTE: Stage currents are set by I1.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: BUF634A
13
BUF634A
SBOS948A – FEBRUARY 2019 – REVISED MAY 2019
www.ti.com
8.3 Feature Description
8.3.1 Output Current
The BUF634A can deliver up to ±250-mA continuous output current. Internal circuitry limits the output current to
approximately ±350 mA. Care must be taken to limit the output voltage swing for a given load resistance to avoid
limiting the output current and degrading linearity; see Figure 45. For many applications, however, the continuous
output current is limited by thermal effects. The output voltage swing capability varies with junction temperature
and output current; see Figure 17 and Figure 18. Care must be taken to operate the device below the maximumrecommended junction temperature in applications using this buffer in wide-bandwidth mode with a wide supply
voltage and large output current to avoid permanent damage to the device.
8.3.2 Thermal Shutdown
Power dissipated in the BUF634A causes the junction temperature to rise. A thermal protection circuit in the
BUF634A disables the output when the junction temperature reaches approximately 180°C. When the thermal
protection is activated, the output stage is disabled and the output current is limited, allowing the device to cool.
Quiescent current is approximately 12 mA during thermal shutdown. When the junction temperature cools to
approximately 160°C, the output circuitry is again enabled. This process can cause the protection circuit to cycle
on and off with a period ranging from a fraction of a second to several minutes or more, depending on package
type, signal, load, and thermal environment.
The thermal protection circuit is designed to prevent damage during abnormal conditions. Any tendency to
activate the thermal protection circuit during normal operation is a sign of an inadequate heat sink or excessive
power dissipation for the package type.
8.3.3 ESD Protection
As shown in Figure 36, all device pins are protected with internal ESD protection diodes to the power supplies.
These diodes provide moderate protection to input overdrive voltages above the supplies. The protection diodes
can typically support 10-mA continuous currents. Current limiting series resistors must be added at the inputs if
common-mode voltages higher than the supply voltages are possible. Keep these resistor values as low as
possible because using high values degrades noise performance and frequency response.
V+
Power Supply
ESD Cell
VIN
VO
BW
V±
Figure 36. Internal ESD Protection
14
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: BUF634A
BUF634A
www.ti.com
SBOS948A – FEBRUARY 2019 – REVISED MAY 2019
8.4 Device Functional Modes
8.4.1 Adjustable Bandwidth
The BUF634A –3-dB bandwidth can be adjusted from 35 MHz to 210 MHz for a 1-kΩ load resistance, as shown
in Figure 37, by connecting a resistor between the V– and BW pins. The bandwidth is set to 210 MHz with the
BW pin connected to V– and to 35 MHz with the BW pin left floating. The –3-dB bandwidth also changes with the
value of the load resistance for a given bandwidth adjustment resistance. The device quiescent current varies
from 1.5 mA (typ) to 8.5 mA (typ) with variation in bandwidth from 35 MHz to 210 MHz, respectively.
240
RL = 1 k:
RL = 100 :
-3 dB Bandwidth (MHz)
210
180
150
120
90
60
30
10
100
1k
10k
Resistance (:)
100k
1M
D001
Figure 37. Small-Signal Bandwidth versus Bandwidth Adjustment Resistance
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: BUF634A
15
BUF634A
SBOS948A – FEBRUARY 2019 – REVISED MAY 2019
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Figure 38 shows the BUF634A connected as an open-loop buffer. The source impedance and optional input
resistor, RS, influence the frequency response; see Figure 3. Bypass the power supplies with capacitors
connected close to the device pins. Capacitor values as low as 0.1 µF assure stable operation in most
applications, but high output current and fast output slewing can demand large current transients from the power
supplies, requiring the use of solid tantalum 10-µF capacitors. High-frequency, open-loop applications benefit
from special bypassing and layout considerations. See the High-Frequency Applications section for more
information. If the BUF634A input is left floating, the device output can swing to either of the supplies based on
the input bias current polarity.
Optiona l conn ection
for wide ba ndwidth ±
See Adju stable Ba ndwidth
section
Figure 38. Buffer Connections
9.1.1 High-Frequency Applications
The excellent bandwidth and fast slew rate of the BUF634A are useful in a variety of high-frequency, open-loop
applications. When operated in an open-loop application, printed circuit board (PCB) layout and bypassing
techniques can affect dynamic performance. Figure 39 through Figure 43 illustrate various application circuit
examples for the BUF634A.
For best results, use a ground-plane-type circuit board layout and bypass the power supplies with 0.1-µF ceramic
chip capacitors at the device pins in parallel with solid tantalum 10-µF capacitors. Source resistance affects highfrequency peaking, step-response overshoot, and ringing. Best response is usually achieved with a series input
resistor of 25 Ω to 200 Ω, depending on the signal source. Response with some loads (especially capacitive) can
be improved with a resistor of 10 Ω to 150 Ω in series with the output. When driving multiple device under test
(DUT) inputs in automatic test equipment (ATE) testers (large capacitive load), as illustrated in Figure 40, place
an isolation resistor at the output of the BUF634A for adequate phase margin and stability.
16
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: BUF634A
BUF634A
www.ti.com
SBOS948A – FEBRUARY 2019 – REVISED MAY 2019
Application Information (continued)
G = +2
1 kŸ
1 kŸ
±
1 µF
Drives hea dphon es
or sma ll spea kers.
BUF634A
OPA165 6
+
100 kŸ
Figure 39. High-Performance Headphone Driver
V+
RF
CF
±
RISO
OPA281 0
VIN
VO
BUF634A
+
BW
CL
V-
Figure 40. ATE and Test Pin Driver
+24 V
C(1)
10 k
+
BUF634A
10 F
C(1)
10 k
+
12 V
±
Psuedo
ground
+
12 V
±
NOTE: (1) System bypass capacitors.
Figure 41. Pseudo-Ground Driver
VIN
±2 V
IO = ±200 mA
+
OPA2810
±
BUF634A
Valve
10
Figure 42. Current-Output Valve Driver
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: BUF634A
17
BUF634A
SBOS948A – FEBRUARY 2019 – REVISED MAY 2019
www.ti.com
Application Information (continued)
10 k
1k
9k
± ½
OPA281 0
VIN
±1 V
10 k
BUF634A
Motor
±
½
OPA281 0
BUF634A
+
+
±20 V
At 250mA
Figure 43. Bridge-Connected Motor Driver
9.2 Typical Application
The BUF634A can be connected inside the feedback loop, as shown in Figure 44, of most op amps to increase
output current. When connected inside the feedback loop, the offset voltage of the BUF634A and other errors are
corrected by the open-loop gain and feedback of the op amp.
1 kŸ
1 kŸ
±
+
RL
NOTE: C1 is not required for most common op amps. Use C1 with unity-gain stable, high-speed op amps.
Figure 44. Boosting Op Amp Output Current
9.2.1 Design Requirements
•
•
•
•
•
•
Boost the output current of an OPA2810
Operate from ±12-V power supplies
Operate from –40°C to +125°C
Gain = 2 V/V
Output current = ±250 mA
Bandwidth greater than 100 kHz
9.2.2 Detailed Design Procedure
To assure that the composite amplifier remains stable, the phase shift of the BUF634A must remain small
throughout the loop gain of the circuit. For a G = +1 op-amp circuit, the BUF634A must contribute little additional
phase shift (approximately 20° or less) at the unity-gain frequency of the op amp. Phase shift is affected by
various operating conditions that can affect the stability of the op amp.
For the circuit in Figure 44, most general-purpose or precision op amps remain unity-gain stable with the
BUF634A connected inside the feedback loop. Large capacitive loads may require the BUF634A to be connected
for wide bandwidth for stable operation. High-speed or fast-settling op amps generally require wide-bandwidth
mode to remain stable and to assure good dynamic performance. Check for oscillations or excessive ringing on
signal pulses with the intended load and worst-case conditions that affect phase response of the buffer to
determine stability with an op amp. Connect the circuit as shown in Figure 44. Choose resistors to provide a
voltage gain of 2 V/V. Select the feedback resistor to be 1 kΩ. Choose the input resistor to be 1 kΩ and C1 to be
10 pF. Figure 45 and Figure 46 illustrate the THD+N plots for the BUF634A used with the OPA2810 in a gain of
18
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: BUF634A
BUF634A
www.ti.com
SBOS948A – FEBRUARY 2019 – REVISED MAY 2019
Typical Application (continued)
2-V/V composite loop. The THD+N performance is superior in a composite loop when compared with a
standalone BUF634A because of the negative feedback and open-loop gain of the OPA2810. In Figure 45, the
signal distortion degrades for large output voltages with 16-Ω and 32-Ω loads because of the device internal
short-circuit protection.
9.2.3 Application Curves
-80
RL = 16 :
RL = 32 :
RL = 250 :
-20
Total Harmonic Distortion + Noise (dB)
Total Harmonic Distortion + Noise (dB)
0
-40
-60
-80
-100
-120
1
10
20
Output Voltage (VPP)
RL = 16 :
RL = 32 :
RL = 250 :
-90
-100
-110
-120
10
D002
f = 20 kHz, 90-kHz measurement bandwidth
Figure 45. THD+N vs Output Voltage Using the BUF634A
With the OPA2810
100
1k
Frequency (Hz)
10k
D003
VO = 10 VPP, 90-kHz measurement bandwidth
Figure 46. THD+N vs Frequency Using the BUF634A With
the OPA2810
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: BUF634A
19
BUF634A
SBOS948A – FEBRUARY 2019 – REVISED MAY 2019
www.ti.com
10 Power Supply Recommendations
The BUF634A is intended for operation on supplies ranging from 4.5 V to 36 V (±2.25 V to ±18 V). At low powersupply conditions, such as ±2.25 V, the output swing may be limited. See the output voltage range specifications
in the Electrical Characteristics tables for additional information. The BUF634A can be operated on single-sided
supplies, split, and balanced bipolar supplies or unbalanced bipolar supplies. Operating from a single supply can
have numerous advantages. With the negative supply at ground, the DC errors resulting from the –PSRR term
can be minimized. Minimize the distance (< 0.1") from the power-supply pins to high-frequency, 0.1-µF
decoupling capacitors. A larger capacitor (10 µF typical) is used along with a high-frequency, 0.1-µF supplydecoupling capacitor at the device supply pins. For single-supply operation, only the positive supply has these
capacitors. When a split-supply is used, use these capacitors from each supply to ground. If necessary, place the
larger capacitors further from the device and share these capacitors among several devices in the same area of
the PCB.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit. Bypass capacitors are
used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise
pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the
ground current.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much
better as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible, as illustrated in Figure 47.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is
recommended to remove moisture introduced into the device packaging during the cleaning process. A
low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
The SOIC-8 surface-mount package is excellent for applications requiring high output current with low average
power dissipation. To achieve the best possible thermal performance with the SOIC-8 package, solder the device
directly to a circuit board. Sockets degrade thermal performance because much of the heat is dissipated by
conduction through the package pins. Use wide circuit board traces on all device pins, including pins that are not
connected. For more information on designing the circuit board, see the BUF634AD Evaluation module user's
guide.
11.1.1 Power Dissipation
Power dissipation depends on power-supply voltage, signal, and load conditions. A part of this dissipation is
because of the device quiescent current. There is additional power dissipation in the buffer output stage because
of the output current. With DC signals, power dissipation is equal to the product of output current times the
voltage across the conducting output transistor, VS – VO. Power dissipation can be minimized by using the lowest
possible power-supply voltage necessary to assure the required output voltage swing.
For resistive loads, the maximum power dissipation occurs at a DC output voltage of one-half the power supply
voltage. Dissipation with AC signals is lower. The Power amplifier stress and power handling limitations
application note explains how to calculate or measure power dissipation with unusual signals and loads.
20
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: BUF634A
BUF634A
www.ti.com
SBOS948A – FEBRUARY 2019 – REVISED MAY 2019
Layout Guidelines (continued)
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heat sink. For reliable operation, limit junction temperature to 150°C, maximum. To estimate the margin of safety
in a complete design, increase the ambient temperature until the thermal protection is triggered. The thermal
protection must trigger more than 45°C above the maximum expected ambient condition of your application.
11.2 Layout Example
BUF634A SOIC
Package
±
close to power pins
±
close to power pins
Figure 47. BUF634A Layout Example
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: BUF634A
21
BUF634A
SBOS948A – FEBRUARY 2019 – REVISED MAY 2019
www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macromodels in addition to a range
of both passive and active models. TINA-TI provides all the conventional DC, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
12.1.1.2 TI Precision Designs
The BUF634A is featured in several TI Precision Designs, available online at www.ti.com. TI Precision Designs
are analog solutions created by TI’s precision analog applications experts and offer the theory of operation,
component selection, simulation, complete PCB schematic and layout, bill of materials, and measured
performance of many useful circuits.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, OPA2810 Dual-channel, 27-V, rail-to-rail input/output FET-Input operational amplifier data
sheet
• Texas Instruments, BUF634AD Evaluation module user's guide
• Texas Instruments, Combining an amplifier with the BUF634 application note
• Texas Instruments, Add current limit to the BUF634 application note
• Texas Instruments, Power amplifier stress and power handling limitations application note
• Texas Instruments, Shelf-life evaluation of lead-free component finishes application report
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
22
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: BUF634A
BUF634A
www.ti.com
SBOS948A – FEBRUARY 2019 – REVISED MAY 2019
12.5 Trademarks
TINA-TI, TINA, E2E are trademarks of Texas Instruments.
DesignSoft is a trademark of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: BUF634A
23
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
BUF634AIDR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOIC
D
8
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
BF634A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
11-May-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
BUF634AIDR
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-May-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BUF634AIDR
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising