Texas Instruments | TLV910x 16-V, 1-MHz, Rail-to-Rail Input/Output, Low Power Op Amp (Rev. A) | Datasheet | Texas Instruments TLV910x 16-V, 1-MHz, Rail-to-Rail Input/Output, Low Power Op Amp (Rev. A) Datasheet

Texas Instruments TLV910x 16-V, 1-MHz, Rail-to-Rail Input/Output, Low Power Op Amp (Rev. A) Datasheet
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TLV9101, TLV9102, TLV9104
SBOS943A – FEBRUARY 2019 – REVISED APRIL 2019
TLV910x 16-V, 1-MHz, Rail-to-Rail Input/Output, Low Power Op Amp
1 Features
3 Description
•
•
•
•
•
•
•
•
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The TLV910x family (TLV9101, TLV9102, and
TLV9104) is a family of 16-V general purpose
operational amplifiers.
1
Rail-to-rail input and output
Wide bandwidth: 1.1-MHz GBW
Low quiescent current: 120 µA per amplifier
Low offset voltage: ±300 µV
Low offset voltage drift: ±0.6 µV/°C
Low noise: 28 nV/√Hz at 10 kHz
High common-mode rejection: 110 dB
Low bias current: ±10 pA
High slew rate: 4.5 V/µs
Wide supply: ±1.35 V to ±8 V, 2.7 V to 16 V
Robust EMIRR performance: 77 dB at 1.8 GHz
These devices offer excellent DC precision and AC
performance, including rail-to-rail input/output, low
offset (±300 µV, typ), low offset drift (±0.5 µV/°C, typ),
and 1.1-MHz bandwidth.
Wide differential and common-mode input-voltage
range, high output current (±80 mA), high slew rate
(4.5 V/µs), low power operation (120 µA, typ) and
shutdown functionality make the TLV910x a robust,
low-power, high-performance operational amplifier for
industrial applications.
The TLV910x family of op amps is available in microsize packages, as well as standard packages, and is
specified from –40°C to 125°C.
2 Applications
•
•
•
•
•
•
Central and string solar inverter
Washer, dryer, and refrigerator
Macro remote radio unit (RRU)
Servo drive control module
Resolver and motor encoders
High-side and low-side current sensing
Device Information(1)
PART NUMBER
TLV9101
PACKAGE
2.90 mm × 1.60 mm
SOT-23 (6)(2)
2.90 mm × 1.60 mm
(2)
SC70 (5)
2.00 mm × 1.25 mm
SOT-553 (5)(2)
1.60 mm × 1.20 mm
SOIC (8)
4.90 mm × 3.90 mm
VSSOP (8)(2)
(2)
TLV9102
3.00 mm × 3.00 mm
VSSOP (10)
3.00 mm × 3.00 mm
WSON (8)(2)
2.00 mm × 2.00 mm
X2QFN (10)(2)
1.50 mm × 1.50 mm
(2)
TLV9104
BODY SIZE (NOM)
SOT-23 (5)(2)
SOIC (14)
8.65 mm × 3.90 mm
TSSOP (14)(2)
5.00 mm × 4.40 mm
WQFN (16)(2)
3.00 mm × 3.00 mm
(2)
2.00 mm × 2.00 mm
WQFN (14)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) This package is preview only.
TLV910x in a Single-Pole, Low-Pass Filter
RG
RF
R1
VOUT
VIN
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
1
2pR1C1
(
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TLV9101, TLV9102, TLV9104
SBOS943A – FEBRUARY 2019 – REVISED APRIL 2019
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
1
1
1
2
3
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information for Single Channel ................... 7
Thermal Information for Dual Channel...................... 8
Thermal Information for Quad Channel .................... 8
Electrical Characteristics........................................... 9
Typical Characteristics ............................................ 11
Typical Characteristics ............................................ 12
Detailed Description ............................................ 20
7.1 Overview ................................................................. 20
7.2 Functional Block Diagram ....................................... 20
7.3 Feature Description................................................. 21
7.4 Device Functional Modes........................................ 27
8
Application and Implementation ........................ 28
8.1 Application Information............................................ 28
8.2 Typical Applications ................................................ 28
9 Power Supply Recommendations...................... 30
10 Layout................................................................... 30
10.1 Layout Guidelines ................................................. 30
10.2 Layout Example .................................................... 30
11 Device and Documentation Support ................. 33
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
33
33
33
33
34
34
34
34
12 Mechanical, Packaging, and Orderable
Information ........................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (February 2019) to Revision A
•
2
Page
Changed the TLV9102 device status from Advance Information to Production Data ............................................................ 1
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5 Pin Configuration and Functions
TLV9101 DBV and DRL Package(1)
5-Pin SOT-23 and SOT-553
Top View
OUT
1
V±
2
IN+
3
5
TLV9101 DCK Package(1)
5-Pin SC70
Top View
V+
4
IN±
IN+
1
V±
2
IN±
3
Not to scale
(1)
5
V+
4
OUT
Not to scale
Package is preview only.
(1)
Package is preview only.
Pin Functions: TLV9101
PIN
NAME
DBV and DRL
DCK
+IN
3
1
–IN
4
OUT
1
V+
V–
I/O
DESCRIPTION
I
Noninverting input
3
I
Inverting input
4
O
Output
5
5
—
Positive (highest) power supply
2
2
—
Negative (lowest) power supply
TLV9101S DBV(1)
6-Pin SOT-23
Top View
OUT
1
6
V+
V±
2
5
SHDN
+IN
3
4
±IN
Not to scale
(1)
Package is preview only.
Pin Functions: TLV9101S
PIN
NAME
DBV
+IN
3
–IN
OUT
I/O
DESCRIPTION
I
Noninverting input
4
I
Inverting input
1
O
Output
SHDN
5
I
Shutdown: low = amplifier enabled, high = amplifier disabled
V+
6
—
Positive (highest) power supply
V–
2
—
Negative (lowest) power supply
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TLV9102 D, DGK, and PW Packages(1)
8-Pin SOIC, TSSOP, and VSSOP
Top View
TLV9102 DSG Package(1)(2)
8-Pin WSON With Exposed Thermal Pad
Top View
OUT1
1
8
V+
IN1±
2
7
OUT2
OUT1
1
IN1+
3
6
IN2±
IN1±
2
V±
4
5
IN2+
IN1+
3
V±
4
Thermal
Pad
8
V+
7
OUT2
6
IN2±
5
IN2+
Not to scale
(1)
DGK and PW packages are preview only.
Not to scale
(1)
Connect thermal pad to V–.
(2)
Package is preview only.
Pin Functions: TLV9102
PIN
SOIC, TSSOP,
VSSOP, and
WSON
I/O
+IN A
3
I
Noninverting input, channel A
+IN B
5
I
Noninverting input, channel B
–IN A
2
I
Inverting input, channel A
–IN B
6
I
Inverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V+
8
—
Positive (highest) power supply
V–
4
—
Negative (lowest) power supply
NAME
4
DESCRIPTION
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TLV9102S DGS Package(1)
10-Pin VSSOP
Top View
+IN A
TLV9102S RUG Package(1)
10-Pin X2QFN
Top View
1
10
V+
IN1±
2
9
OUT2
IN1+
3
8
IN2±
V±
4
7
IN2+
SHDN1
5
6
SHDN2
V±
1
9
±IN A
SHDN A
2
8
OUT A
SHDN B
3
7
V+
+IN B
4
6
OUT B
10
OUT1
(1)
5
Not to scale
Package is preview only.
±IN B
Not to scale
(1)
Package is preview only.
Pin Functions: TLV9102S
PIN
NAME
I/O
DESCRIPTION
VSSOP
X2QFN
+IN A
3
10
I
Noninverting input, channel A
+IN B
7
4
I
Noninverting input, channel B
–IN A
2
9
I
Inverting input, channel A
–IN B
8
5
I
Inverting input, channel B
OUT A
1
8
O
Output, channel A
OUT B
9
6
O
Output, channel B
SHDN A
5
2
I
Channel A shutdown: low = amplifier enabled, high = amplifier
disabled
SHDN B
6
3
I
Channel B shutdown: low = amplifier enabled, high = amplifier
disabled
V+
10
7
—
Positive (highest) power supply
V–
4
1
—
Negative (lowest) power supply
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5
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TLV9104 D and PW Packages(1)
14-Pin SOIC and TSSOP
Top View
OUT1
1
14
OUT4
IN1±
2
13
IN4±
IN1+
3
12
IN4+
V+
4
11
V±
IN2+
5
10
IN3+
IN2±
6
9
IN3±
OUT2
7
8
OUT3
Not to scale
(1)
Package is preview only.
Pin Functions: TLV9104
PIN
SOIC and
TSSOP
I/O
+IN A
3
I
Noninverting input, channel A
+IN B
5
I
Noninverting input, channel B
+IN C
10
I
Noninverting input, channel C
+IN D
12
I
Noninverting input, channel D
–IN A
2
I
Inverting input, channel A
–IN B
6
I
Inverting input, channel B
–IN C
9
I
Inverting input, channel C
–IN D
13
I
Inverting input, channel D
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
OUT C
8
O
Output, channel C
OUT D
14
O
Output, channel D
V+
4
—
Positive (highest) power supply
V–
11
—
Negative (lowest) power supply
NAME
6
DESCRIPTION
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
MIN
MAX
0
20
V
(V–) – 0.5
(V+) + 0.5
V
Supply voltage, VS = (V+) – (V–)
Common-mode voltage (2)
Differential voltage (2)
Signal input pins
VS + 0.2
Current (2)
–10
Output short-circuit (3)
–55
Junction temperature, TJ
Storage temperature, Tstg
(2)
(3)
V
10
mA
150
°C
150
°C
150
°C
Continuous
Operating ambient temperature, TA
(1)
UNIT
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
VS
Supply voltage, (V+) – (V–)
VI
Input voltage range
TA
Specified temperature
MIN
MAX
2.7
16
UNIT
(V–) – 0.2
(V+) + 0.2
V
–40
125
°C
V
6.4 Thermal Information for Single Channel
TLV9101, TLV9101S
THERMAL METRIC
DBV (2)
(SOT-23)
(1)
DCK (2)
(SC70)
DRL (2)
(SOT-553)
UNIT
5 PINS
6 PINS
5 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
TBD
TBD
TBD
TBD
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
TBD
TBD
TBD
TBD
°C/W
RθJB
Junction-to-board thermal resistance
TBD
TBD
TBD
TBD
°C/W
ψJT
Junction-to-top characterization parameter
TBD
TBD
TBD
TBD
°C/W
ψJB
Junction-to-board characterization parameter
TBD
TBD
TBD
TBD
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
TBD
TBD
TBD
TBD
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
This package option is preview for TLV9101.
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6.5 Thermal Information for Dual Channel
TLV9102, TLV9102S
THERMAL METRIC (1)
D
(SOIC)
DDF (2)
(SOT-23-8)
DGK (2)
(VSSOP)
DGS (2)
(VSSOP)
DSG (2)
(WSON)
PW (2)
(TSSOP)
RUG (2)
(X2QFN)
UNIT
8 PINS
8 PINS
8 PINS
10 PINS
8 PINS
8 PINS
10 PINS
RθJA
Junction-to-ambient
thermal resistance
138.7
TBD
TBD
TBD
TBD
188.4
TBD
°C/W
RθJC(top)
Junction-to-case (top)
thermal resistance
78.7
TBD
TBD
TBD
TBD
77.1
TBD
°C/W
RθJB
Junction-to-board thermal
resistance
82.2
TBD
TBD
TBD
TBD
119.1
TBD
°C/W
ψJT
Junction-to-top
characterization parameter
27.8
TBD
TBD
TBD
TBD
14.2
TBD
°C/W
ψJB
Junction-to-board
characterization parameter
81.4
TBD
TBD
TBD
TBD
117.4
TBD
°C/W
RθJC(bot)
Junction-to-case (bottom)
thermal resistance
N/A
TBD
TBD
TBD
TBD
N/A
TBD
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
This package option is preview for TLV9102.
6.6 Thermal Information for Quad Channel
TLV9104, TLV9104S
THERMAL METRIC (1)
D (2)
(SOIC)
PW (2)
(TSSOP)
RTE (2)
(WQFN)
RUC (2)
(WQFN)
UNIT
14 PINS
14 PINS
16 PINS
16 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
TBD
TBD
TBD
TBD
TBD
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
TBD
TBD
TBD
TBD
TBD
°C/W
RθJB
Junction-to-board thermal resistance
TBD
TBD
TBD
TBD
TBD
°C/W
ψJT
Junction-to-top characterization parameter
TBD
TBD
TBD
TBD
TBD
°C/W
ψJB
Junction-to-board characterization
parameter
TBD
TBD
TBD
TBD
TBD
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
TBD
TBD
TBD
TBD
TBD
°C/W
(1)
(2)
8
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
This package option is preview for TLV9104.
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6.7 Electrical Characteristics
For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT =
VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
Input offset voltage drift
PSRR
Input offset voltage versus
power supply
VCM = V–
Channel separation
f = 0 Hz
±0.3
VCM = V–
TA = –40°C to 125°C
±1.5
mV
±1.75
TA = –40°C to 125°C
±0.6
TA = –40°C to 125°C
±0.1
µV/℃
±0.7
5
μV/V
µV/V
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
±10
pA
±5
pA
NOISE
EN
Input voltage noise
eN
Input voltage noise density
iN
Input current noise
f = 0.1 Hz to 10 Hz
6
μVPP
1
µVRMS
f = 1 kHz
30
f = 10 kHz
28
f = 1 kHz
2
nV/√Hz
fA/√Hz
INPUT VOLTAGE RANGE
VCM
Common-mode voltage
range
(V–) – 0.2
VS = 16 V, (V–) – 0.1 V <
VCM < (V+) – 2 V (Main
input pair)
CMRR
Common-mode rejection
ratio
VS = 4 V, (V–) – 0.1 V < VCM
< (V+) – 2 V (Main input
pair)
TA = –40°C to 125°C
VS = 2.7 – 16 V, (V+) – 1 V
< VCM < (V+) + 0.1 V (Aux
input pair)
(V+) – 2 V < VCM < (V+) – 1
V
(V+) + 0.2
90
110
75
95
V
dB
80
See Offset Voltage (Transition Region)
INPUT CAPACITANCE
ZID
Differential
ZICM
Common-mode
100 || 3
MΩ || pF
6 || 1
TΩ || pF
115
135
dB
104
125
dB
1.1
MHz
4.5
V/μs
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
VS = 16 V, VCM = V–
(V–) + 0.1 V < VO < (V+) –
0.1 V
VS = 4 V, VCM = V–
(V–) + 0.1 V < VO < (V+) –
0.1 V
TA = –40°C to 125°C
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
tS
Settling time
VS = 16 V, G = +1, CL = 20 pF
To 0.1%, VS = 16 V, VSTEP = 10 V, G = +1, CL = 20 pF
4
To 0.1%, VS = 16 V, VSTEP = 2 V, G = +1, CL = 20 pF
2
To 0.01%, VS = 16 V, VSTEP = 10 V, G = +1, CL = 20 pF
5
To 0.01%, VS = 16 V, VSTEP = 2 V, G = +1, CL = 20 pF
THD+N
Phase margin
G = +1, RL = 10 kΩ, CL = 20 pF
Overload recovery time
VIN × gain > VS
Total harmonic distortion +
noise
VS = 16 V, VO = 1 VRMS, G = -1, f = 1 kHz
3
60
°
600
ns
0.0028%
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Electrical Characteristics (continued)
For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT =
VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
VS = 16 V, RL = no load
Positive rail headroom
Voltage output swing from
rail
ISC
Short-circuit current
CLOAD
Capacitive load drive
ZO
Open-loop output
impedance
45
60
VS = 16 V, RL = 2 kΩ
200
300
VS = 2.7 V, RL = no load
Negative rail headroom
3
VS = 16 V, RL = 10 kΩ
1
VS = 2.7 V, RL = 10 kΩ
5
20
VS = 2.7 V, RL = 2 kΩ
25
50
±80
mV
mA
See Typical Characteristics
f = 1 MHz, IO = 0 A
Ω
600
POWER SUPPLY
IQ
10
Quiescent current per
amplifier
IO = 0 A
120
TA = –40°C to 125°C
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150
160
µA
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6.8 Typical Characteristics
Table 1. Table of Graphs
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
Figure 1
Offset Voltage Drift Distribution
Figure 2
Offset Voltage vs Temperature
Figure 3 , Figure 4
Offset Voltage vs Common-Mode Voltage
Figure 5, Figure 6, Figure 7 , Figure 8
Offset Voltage vs Power Supply
Figure 9
Open-Loop Gain and Phase vs Frequency
Figure 10
Closed-Loop Gain and Phase vs Frequency
Figure 11
Input Bias Current vs Common-Mode Voltage
Figure 12
Input Bias Current vs Temperature
Figure 13
Output Voltage Swing vs Output Current
Figure 14 , Figure 15, Figure 16, Figure 17
CMRR and PSRR vs Frequency
Figure 18
CMRR vs Temperature
Figure 19
PSRR vs Temperature
Figure 20
0.1-Hz to 10-Hz Noise
Figure 21
Input Voltage Noise Spectral Density vs Frequency
Figure 22
THD+N Ratio vs Frequency
Figure 23
THD+N vs Output Amplitude
Figure 24
Quiescent Current vs Supply Voltage
Figure 25
Quiescent Current vs Temperature
Figure 26
Open Loop Voltage Gain vs Temperature
Figure 27
Open Loop Output Impedance vs Frequency
Figure 28
Small Signal Overshoot vs Capacitive Load (100-mV Output Step)
Figure 29, Figure 30
Phase Margin vs Capacitive Load
Figure 31
No Phase Reversal
Figure 32
Positive Overload Recovery
Figure 33
Negative Overload Recovery
Figure 34
Small-Signal Step Response (100 mV)
Figure 35, Figure 36
Large-Signal Step Response
Figure 37, Figure 38, Figure 39
Short-Circuit Current vs Temperature
Figure 40
Maximum Output Voltage vs Frequency
Figure 41
Channel Separation vs Frequency
Figure 42
EMIRR vs Frequency
Figure 43
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6.9 Typical Characteristics
25%
25%
20%
20%
Population (%)
15%
10%
15%
10%
5%
Offset Voltage (PV)
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0
D001
0.2
1200
900
1050
750
600
450
300
0
150
-150
-300
-450
-600
-750
-900
-1050
-1200
0
5%
0
Population (%)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Offset Voltage Drift (PV/qC)
Distribution from 13,481 amplifiers; TA = 25°C
D002
Distribution from 175 amplifiers
Figure 1. Offset Voltage Production Distribution
Figure 2. Offset Voltage Drift Distribution
1000
800
800
600
600
Offset Voltage (µV)
Offset Voltage (µV)
400
400
200
0
-200
-400
200
0
-200
-400
-600
-600
-800
-1000
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
-800
-40
140
-20
0
20
D003
VCM = V+
120
140
D004
Figure 4. Offset Voltage vs Temperature
800
600
600
400
400
Offset Voltage (µV)
Offset Voltage (µV)
Figure 3. Offset Voltage vs Temperature
12
100
VCM = V–
800
200
0
-200
200
0
-200
-400
-400
-600
-600
-800
-8
40
60
80
Temperature (°C)
-800
-6
-4
-2
0
2
4
Common Mode Voltage (V)
6
8
4
D005
4.5
5
5.5
6
6.5
7
Common Mode Voltage (V)
7.5
8
D005
TA = 25°C
TA = 25°C
Figure 5. Offset Voltage vs Common-Mode Voltage
Figure 6. Offset Voltage vs Common-Mode Voltage
(Transition Region)
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Typical Characteristics (continued)
1000
800
800
600
600
400
400
200
Offset Voltage (µV)
200
0
-200
-400
0
-200
-400
-600
-600
-800
-800
-1000
-1000
-8
-6
-4
-2
0
2
4
Common Mode Voltage (V)
6
-1200
-8
8
-6
-4
D006
TA = 125°C
-2
0
2
4
Common Mode Voltage (V)
8
D007
TA = –40°C
Figure 7. Offset Voltage vs Common-Mode Voltage
Figure 8. Offset Voltage vs Common-Mode Voltage
100
750
150
Gain
Phase
600
80
450
300
150
Gain (dB)
Offset Voltage (µV)
6
0
-150
-300
-450
125
60
100
40
75
20
50
0
25
Phase (q)
Offset Voltage (µV)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
-600
-750
2
4
6
8
10
12
Supply Voltage (V)
14
16
18
-20
100
0
1k
10k
100k
Frequency (Hz)
D008
1M
C002
CLOAD = 15 pF
Figure 9. Offset Voltage vs Power Supply
Figure 10. Open-Loop Gain and Phase vs Frequency
3
60
2.5
Input Bias and Offset Current (pA)
70
Closed-Loop Gain (dB)
50
40
30
20
10
0
-10
-20
-30
100
G=1
G = -1
G = 10
G = 100
G = 1000
1k
10k
100k
Frequency (Hz)
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
-8
1M
C001
Figure 11. Closed-Loop Gain and Phase vs Frequency
IB
IB+
IOS
-6
-4
-2
0
2
4
Common Mode Voltage (V)
6
8
D010
Figure 12. Input Bias Current vs Common-Mode Voltage
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Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
IB
IB+
IOS
280
240
Output Voltage (V)
Input Bias and Offset Current (pA)
320
200
160
120
80
40
0
-40
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
20
19.5
19
18.5
18
17.5
17
16.5
16
15.5
15
14.5
14
13.5
13
12.5
12
140
25qC
125qC
85qC
0
10
20
30
D011
Figure 13. Input Bias Current vs Temperature
40
50
60
70
Output Current (mA)
80
90
100
D012
Figure 14. Output Voltage Swing vs Output Current
(Sourcing)
5
-12
-12.5
-13
-13.5
-14
-14.5
-15
-15.5
-16
-16.5
-17
-17.5
-18
-18.5
-19
-19.5
-20
85qC
-40qC
4.5
125qC
4
-40qC
25qC
Output Voltage (V)
Output Voltage (V)
-40qC
3.5
25qC
125qC
3
2.5
85qC
2
1.5
1
0.5
0
0
10
20
30
40
50
60
70
Output Current (mA)
80
90
0
100
10
20
D012
30
40
50
60
70
Output Current (mA)
80
90
100
D013
VS = 5 V
Figure 15. Output Voltage Swing vs Output Current
(Sinking)
Figure 16. Output Voltage Swing vs Output Current
(Sourcing)
5
120
4.5
110
100
PSRR and CMRR (dB)
4
Output Voltage (V)
PSRR+
PSRRCMRR
3.5
3
85qC
2.5
125qC
2
1.5
1
25qC
0.5
-40qC
90
80
70
60
50
40
30
20
10
0
0
10
20
30
40
50
60
70
Output Current (mA)
80
90
100
0
100
D013
1k
10k
100k
Frequency (Hz)
1M
C003
VS = 5 V
Figure 17. Output Voltage Swing vs Output Current
(Sinking)
14
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Figure 18. CMRR and PSRR vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
145
120
VS = 16 V
VS = 4 V
Power Supply Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB)
124
116
112
108
104
100
96
92
88
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
144
143
142
141
140
139
138
137
136
135
-40
140
-20
0
20
D015
Input Voltage Noise Spectral Density (nV/rHz)
Voltage (1uV/div)
Time (1s/Div)
140
D016
120
110
100
90
80
70
60
50
40
30
20
10
0
10
100
C015
Figure 21. 0.1-Hz to 10-Hz Noise
1k
Frequency (Hz)
10k
100k
C017
Figure 22. Input Voltage Noise Spectral Density vs
Frequency
-40
-24
RL = 10 k:
RL = 2 k:
RL = 600 :
RL = 128 :
-32
-40
-48
THD+N (dB)
THD+N (dB)
120
Figure 20. PSRR vs Temperature (dB)
Figure 19. CMRR vs Temperature (dB)
-60
100
f = 0 Hz
f = 0 Hz
-50
40
60
80
Temperature (°C)
-70
-80
-56
-64
-72
-80
-90
-88
-100
-96
-110
100
1k
Frequency (Hz)
-104
0.001
10k
C012
BW = 80 kHz, VOUT = 3.5 VRMS
RL = 10 k:
RL = 2 k:
RL = 549 :
RL = 128 :
0.01 0.02 0.05 0.1 0.2 0.5
Amplitude (VRMS)
1
2 3 4 5 78
OPA2
C023
BW = 80 kHz, f = 1 kHz
Figure 23. THD+N Ratio vs Frequency
Figure 24. THD+N vs Output Amplitude
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Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
127.5
130
125
122.5
120
Quiescent current (µA)
Quiescent current (µA)
125
115
110
105
100
95
120
117.5
115
112.5
110
107.5
90
105
85
102.5
-40
0
2
4
6
8
10
12
Supply Voltage (V)
14
16
18
146
Open Loop Output Impedance (:)
Open Loop Voltage Gain (dB)
20
40
60
80
Temperature (°C)
100
120
140
D022
780
VS = 16 V
VS = 4 V
144
142
140
138
136
134
132
130
128
126
124
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
720
660
600
540
480
420
360
300
240
180
120
100
140
1k
10k
100k
Frequency (Hz)
D023
Figure 27. Open-Loop Voltage Gain vs Temperature (dB)
1M
10M
C013
Figure 28. Open-Loop Output Impedance vs Frequency
60
50
Positive overshoot
Negative overshoot
45
Positive overshoot
Negative overshoot
55
50
40
45
Overshoot (%)
35
30
25
20
40
35
30
25
15
20
10
15
5
10
5
0
0
200
400
600
Cap Load (pF)
800
0
1000
40
C007
80
120
160 200 240
Cap Load (pF)
280
320
360
C008
G = 1, 100-mV output step
G = –1, 100-mV output step
Figure 29. Small-Signal Overshoot vs Capacitive Load
16
0
Figure 26. Quiescent Current vs Temperature
Figure 25. Quiescent Current vs Supply Voltage
Overshoot (%)
-20
D021
Figure 30. Small-Signal Overshoot vs Capacitive Load
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Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
64
Input
Output
60
56
Amplitude (2V/div)
Phase Margin (q)
52
48
44
40
36
32
28
24
20
0
100
200
300
400 500 600
Cap Load (pF)
700
800
Time (20µs/Div)
900 1000
C016
C009
G = –1, 100-mV output step
Figure 32. No Phase Reversal
Voltage (5V/div)
Voltage (5V/div)
Figure 31. Small-Signal Overshoot vs Capacitive Load
Input
Output
Input
Output
Time (500ns/div)
Time (500ns/div)
C018
C018
G = –10
G = –10
Figure 33. Positive Overload Recovery
Figure 34. Negative Overload Recovery
Amplitude (5mV/div)
Amplitude (2mV/div)
Input
Output
Input
Output
Time (1µs/div)
Time (2Ps/div)
C011
C010
CL = 20 pF, G = 1, 20-mV step response
RL = 1 kΩ, CL = 20 pF, G = –1, 10-mV step response
Figure 35. Small-Signal Step Response
Figure 36. Small-Signal Step Response
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Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Amplitude (2V/div)
Amplitude (2V/div)
Input
Output
Input
Output
Time (1µs/div)
Time (1µs/div)
C005
C005
CL = 20 pF, G = 1
CL = 20 pF, G = 1
Figure 37. Large-Signal Step Response (Falling)
Figure 38. Large-Signal Step Response (Rising)
Large Signal Step Response (2V/div)
100
Short-Circuit Current (mA)
80
Input
Output
60
40
20
Sourcing
Sinking
0
-20
-40
-60
-80
-100
-40
Time (2µs/div)
-20
0
C021
20
40
60
80
Temperature (°C)
100
120
140
D038
CL = 10 pF, G = –1
Figure 39. Large-Signal Step Response
Figure 40. Short-Circuit Current vs Temperature
45
-60
VS = 40 V
VS = 30 V
VS = 15 V
VS = 2.7 V
35
-70
Channel Seperation (dB)
Maximum Output Swing (V)
40
30
25
20
15
10
-90
-100
-110
-120
5
0
1k
10k
100k
Frequency (Hz)
1M
10M
-130
100
1k
C020
Figure 41. Maximum Output Voltage vs Frequency
18
-80
10k
100k
Frequency (Hz)
1M
10M
C014
Figure 42. Channel Separation vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
100
90
EMIRR (dB)
80
70
60
50
40
30
1M
10M
100M
Frequency (Hz)
1G
C004
Figure 43. EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency
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7 Detailed Description
7.1 Overview
The TLV910x family (TLV9101, TLV9102, and TLV9104) is a family of 16-V general purpose operational
amplifiers.
These devices offer excellent DC precision and AC performance, including rail-to-rail input/output, low offset
(±300 µV, typ), low offset drift (±0.6 µV/°C, typ), and 1.1-MHz bandwidth.
Wide differential and common-mode input-voltage range, high output current (±80 mA), high slew rate (4.5 V/µs),
low power operation (120 µA, typ) and shutdown functionality make the TLV910x a robust, low-power, highperformance operational amplifier for industrial applications.
7.2 Functional Block Diagram
V+
Reference
Current
V
IN+
V
INÛ
V
BIAS1
Class AB
Control
Circuitry
V
O
V
BIAS2
VÛ
(Ground)
20
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7.3 Feature Description
7.3.1 EMI Rejection
The TLV910x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the TLV910x benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz.
Figure 44 shows the results of this testing on the TLV910x. Table 2 shows the EMIRR IN+ values for the
TLV910x at particular frequencies commonly encountered in real-world applications. Table 2 lists applications
that may be centered on or operated near the particular frequency shown. The EMI Rejection Ratio of
Operational Amplifiers application report contains detailed information on the topic of EMIRR performance as it
relates to op amps and is available for download from www.ti.com.
100
90
EMIRR (dB)
80
70
60
50
40
30
1M
10M
100M
Frequency (Hz)
1G
C004
Figure 44. TLV910x EMIRR Testing
Table 2. TLV910x EMIRR IN+ For Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
59.5 dB
900 MHz
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
68.9 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
77.8 dB
2.4 GHz
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
78.0 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
88.8 dB
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
87.6 dB
5 GHz
7.3.2 Phase Reversal Protection
The TLV910x family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The TLV910x is a rail-to-rail input op amp; therefore, the common-mode range can
extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into
the appropriate rail. This performance is shown in Figure 45.
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Amplitude (2V/div)
Input
Output
Time (20µs/Div)
C016
Figure 45. No Phase Reversal
7.3.3 Thermal Protection
16 V
VOUT
The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This
phenomenon is called self heating. The absolute maximum junction temperature of the TLV910x is 150°C.
Exceeding this temperature causes damage to the device. The TLV910x has a thermal protection feature that
prevents damage from self heating. The protection works by monitoring the temperature of the device and
turning off the op amp output drive for temperatures above 140°C. Figure 46 shows an application example for
the TLV9101 that has significant self heating (154°C) because of its power dissipation (0.39 W). Thermal
calculations indicate that for an ambient temperature of 100°C the device junction temperature must reach
154°C. The actual device, however, turns off the output drive to maintain a safe junction temperature. Figure 46
shows how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so
the output is 3 V. When self heating causes the device junction temperature to increase above 140°C, the
thermal protection forces the output to a high-impedance state and the output is pulled to ground through resistor
RL.
3V
TA = 100°C
PD = 0.39W
0V
JA = 138.7°C/W
TJ = 138.7°C/W × 0.39W + 100°C
TJ = 154.1°C (expected)
Normal
Operation
Output
High-Z
150°C
IOUT = 30 mA
+
±
VIN
3V
+
RL
3V
100 Ÿ ±
Temperature
TLV9101
140ºC
Figure 46. Thermal Protection
22
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7.3.4 Capacitive Load and Stability
The TLV910x features a resistive output stage capable of driving moderate capacitive loads, and by leveraging
an isolation resistor, the device can easily be configured to drive large capacitive loads. Increasing the gain
enhances the ability of the amplifier to drive greater capacitive loads; see Figure 47 and Figure 48. The particular
op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when
establishing whether an amplifier will be stable in operation.
60
50
Positive overshoot
Negative overshoot
55
40
45
35
Overshoot (%)
Overshoot (%)
Positive overshoot
Negative overshoot
45
50
40
35
30
25
30
25
20
20
15
15
10
10
5
5
0
0
40
80
120
160 200 240
Cap Load (pF)
280
320
360
0
200
C008
Figure 47. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step, G = 1)
400
600
Cap Load (pF)
800
1000
C007
Figure 48. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step, G = –1)
For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small (10
Ω to 20 Ω) resistor, RISO, in series with the output, as shown in Figure 49. This resistor significantly reduces
ringing and maintains DC performance for purely capacitive loads. However, if a resistive load is in parallel with
the capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly
reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at
low output levels. A high capacitive load drive makes the TLV910x well suited for applications such as reference
buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 49 uses an isolation resistor,
RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase
margin
+Vs
Vout
Riso
+
Vin
+
±
Cload
-Vs
Figure 49. Extending Capacitive Load Drive With the TLV9101
7.3.5 Common-Mode Voltage Range
The TLV910x is a 16-V, true rail-to-rail input operational amplifier with an input common-mode range that
extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel
and P-channel differential input pairs, as shown in Figure 50. The N-channel pair is active for input voltages
close to the positive rail, typically (V+) – 1 V to 100 mV above the positive supply. The P-channel pair is active
for inputs from 100 mV below the negative supply to approximately (V+) – 2 V. There is a small transition region,
typically (V+) –2 V to (V+) – 1 V in which both input pairs are on. This transition region can vary modestly with
process variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD performance
may be degraded compared to operation outside this region. To achieve best performance with the TLV910x
family, avoid this transition region when possible.
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V+
INPMOS
PMOS
IN+
NMOS
NMOS
V-
Figure 50. Rail-to-Rail Input Stage
24
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7.3.6 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the
output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. Figure 51 shows an illustration of the ESD circuits contained in the TLV910x (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or
the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain
inactive during normal circuit operation.
TVS
+
±
RF
+VS
VDD
R1
RS
IN±
100 Ÿ
IN+
100 Ÿ
TLV960x
±
+
Power-Supply
ESD Cell
ID
VIN
RL
+
±
VSS
+
±
±VS
TVS
Figure 51. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
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An ESD event is very short in duration and very high voltage (for example, 1 kV, 100 ns), whereas an EOS event
is long duration and lower voltage (for example, 50 V, 100 ms). The ESD diodes are designed for out-of-circuit
ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).
During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit (labeled
ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by
turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting
resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.
7.3.7 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a
linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the
rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
The overload recovery time for the TLV910x is approximately 1 µs.
7.3.8 Typical Specifications and Distributions
Designers often have questions about a typical specification of an amplifier in order to design a more robust
circuit. Due to natural variation in process technology and manufacturing procedures, every specification of an
amplifier will exhibit some amount of deviation from the ideal value, like an amplifier's input offset voltage. These
deviations often follow Gaussian ("bell curve"), or normal distributions, and circuit designers can leverage this
information to guardband their system, even when there is not a minimum or maximum specification in the
Electrical Characteristics table.
0.00002% 0.00312% 0.13185%
1
-61
1
-51
2.145% 13.59% 34.13% 34.13% 13.59% 2.145%
1
1
-41
-31
1
-21
1
-1
1
1
+1
1
0.13185% 0.00312% 0.00002%
1
1
1
+21 +31 +41 +51 +61
Figure 52. Ideal Gaussian Distribution
Figure 52 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ, or sigma,
is the standard deviation of a system. For a specification that exhibits this kind of distribution, approximately twothirds (68.26%) of all units can be expected to have a value within one standard deviation, or one sigma, of the
mean (from µ–σ to µ+σ).
26
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Depending on the specification, values listed in the typical column of the Electrical Characteristics table are
represented in different ways. As a general rule of thumb, if a specification naturally has a nonzero mean (for
example, like gain bandwidth), then the typical value is equal to the mean (µ). However, if a specification
naturally has a mean near zero (like input offset voltage), then the typical value is equal to the mean plus one
standard deviation (µ + σ) in order to most accurately represent the typical value.
You can use this chart to calculate approximate probability of a specification in a unit; for example, for TLV910x,
the typical input voltage offset is 300 µV, so 68.2% of all TLV910x devices are expected to have an offset from
–300 µV to +300 µV. At 4 σ (±1200 µV), 99.9937% of the distribution has an offset voltage less than ±1200 µV,
which means 0.0063% of the population is outside of these limits, which corresponds to about 1 in 15,873 units.
Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits
will be removed from production material. For example, the TLV910x family has a maximum offset voltage of 1.5
mV at 25°C, and even though this corresponds to 5 σ (≈1 in 1.7 million units), which is extremely unlikely, TI
assures that any unit with larger offset than 1.5 mV will be removed from production material.
For specifications with no value in the minimum or maximum column, consider selecting a sigma value of
sufficient guardband for your application, and design worst-case conditions using this value. For example, the 6-σ
value corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and could be an option
as a wide guardband to design a system around. In this case, the TLV910x family does not have a maximum or
minimum for offset voltage drift, but based on Figure 2 and the typical value of 0.6 µV/°C in the Electrical
Characteristics table, it can be calculated that the 6-σ value for offset voltage drift is about 3.6 µV/°C. When
designing for worst-case system conditions, this value can be used to estimate the worst possible offset across
temperature without having an actual minimum or maximum value.
However, process variation and adjustments over time can shift typical means and standard deviations, and
unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a
device. This information should be used only to estimate the performance of a device.
7.4 Device Functional Modes
The TLV910x has a single functional mode and is operational when the power-supply voltage is greater than 2.7
V (±1.35 V). The maximum power supply voltage for the TLV910x is 16 V (±8 V).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV910x family offers excellent DC precision and DC performance. These devices operate up to 16-V
supply rails and offer true rail-to-rail input/output, low offset voltage and offset voltage drift, as well as 1.1-MHz
bandwidth and high output drive. These features make the TLV910x a robust, high-performance operational
amplifier for high-voltage industrial applications.
8.2 Typical Applications
8.2.1 High Voltage Precision Comparator
Many different systems require controlled voltages across numerous system nodes to ensure robust operation. A
comparator can be used to monitor and control voltages by comparing a reference threshold voltage with an
input voltage and providing an output when the input crosses this threshold.
The TLV910x family of op amps make excellent high voltage, precision comparators due to their robust input
stage, low typical offset, and high slew rate. Previous generation high-voltage op amps often use back-to-back
diodes across the inputs to prevent damage to the op amp which greatly limits these op amps to be used as
comparators, but the TLV910x's patented input stage allows the device to have a wide differential voltage
between the inputs.
V+
+
VIN
VOUT
VTH
V+
R1
R2
Figure 53. Typical Comparator Application
8.2.1.1 Design Requirements
The primary objective is to design a 15-V precision comparator.
• System supply voltage (V+): 15 V
• Resistor 1 value: 100 kΩ
• Resistor 2 value: 100 kΩ
• Reference threshold voltage (VTH): 7.5 V
• Input voltage range (VIN): 2.5 V – 12.5 V
• Output voltage range (VOUT): 0 V – 15 V
28
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Typical Applications (continued)
8.2.1.2 Detailed Design Procedure
This noninverting comparator circuit applies the input voltage (VIN) to the noninverting terminal of the op amp.
Two resistors (R1 and R2) divide the supply voltage (V+) to create a mid-supply threshold voltage (VTH) as
calculated in Equation 1. The circuit is shown in Figure 53. When VIN is less then VTH, the output voltage
transitions to the negative supply and equals the low-level output voltage. When VIN is greater than VTH, the
output voltage transitions to the positive supply and equals the high-level output voltage.
In this example, resistor 1 and 2 have been selected to be 100 kΩ, which sets the reference threshold at 7.5 V.
However, resistor 1 and 2 can be adjusted to modify the threshold using Equation 1. Resistor 1 and 2's values
have also been selected to reduce power consumption, but these values can be further increased to reduce
power consumption, or reduced to improve noise performance.
VTH
R2
R1 R2
uV
(1)
8.2.1.3 Application Curve
16
Input
Output
14
12
Voltage (V)
10
8
6
4
2
0
-2
0
0.2
0.4
0.6
0.8
1
1.2
Time (ms)
1.4
1.6
1.8
2
comp
Figure 54. Comparator Output Response to Input Voltage
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9 Power Supply Recommendations
The TLV910x is specified for operation from 2.7 V to 16 V (±1.35 V to ±8 V); many specifications apply from
–40°C to 125°C.
CAUTION
Supply voltages larger than 20 V can permanently damage the device; see the
Absolute Maximum Ratings table.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information, see
Circuit Board Layout Techniques.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 56, keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
10.2 Layout Example
+
VIN
VOUT
RG
RF
Figure 55. Schematic Representation
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Layout Example (continued)
Run the input traces
as far away from
the supply lines
as possible
Place components close
to device and to each
other to reduce parasitic
errors
VS+
RF
NC
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
±IN
V+
VIN
+IN
OUTPUT
V±
NC
GND
VS±
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
V+
INPUT
Figure 56. Operational Amplifier Board Layout for Noninverting Configuration
GND
GND
OUT
V-
GND
Figure 57. Example Layout for SC70 (DCK) Package
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OUTPUT A
Layout Example (continued)
GND
GND
GND
V+
INPUT A
INPUT B
OUTPUT B
VGND
GND
GND
GND
V+
GND
OUT A
Figure 58. Example Layout for VSSOP-8 (DGK) Package
GND
OUT B
- +
+ -
+IN A
V-
+IN B
GND
GND
GND
Figure 59. Example Layout for WSON-8 (DSG) Package
32
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.2 Documentation Support
11.2.1 Related Documentation
Texas Instruments, Circuit Board Layout Techniques.
Texas Instruments, Op Amps for Everyone.
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 3. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLV9102
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
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11.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 Trademarks
E2E is a trademark of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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35
PACKAGE OPTION ADDENDUM
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14-Nov-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
PTLV9101IDBVR
ACTIVE
SOT-23
DBV
5
3000
TBD
Call TI
Call TI
-40 to 125
PTLV9104IDR
ACTIVE
SOIC
D
14
2500
TBD
Call TI
Call TI
-40 to 125
TLV9101IDBVR
PREVIEW
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T91V
TLV9102IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T9102D
TLV9102IDSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T912
TLV9102IPWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T9102P
TLV9104IDR
PREVIEW
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLV9104D
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Nov-2019
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Aug-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TLV9102IDR
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
SOIC
D
8
2500
330.0
TLV9102IDSGR
WSON
DSG
8
3000
TLV9102IPWR
TSSOP
PW
8
2000
B0
(mm)
K0
(mm)
P1
(mm)
12.4
6.4
5.2
2.1
8.0
180.0
8.4
2.3
2.3
1.15
330.0
12.4
7.0
3.6
1.6
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
12.0
Q1
4.0
8.0
Q2
8.0
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Aug-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV9102IDR
SOIC
D
8
2500
367.0
367.0
35.0
TLV9102IDSGR
WSON
DSG
8
3000
210.0
185.0
35.0
TLV9102IPWR
TSSOP
PW
8
2000
367.0
367.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DSG 8
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2 x 2, 0.5 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.32
0.18
0.4
0.2
OPTIONAL TERMINAL
TYPICAL
C
0.8 MAX
SEATING PLANE
0.05
0.00
0.08 C
EXPOSED
THERMAL PAD
(0.2) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
SEE OPTIONAL
TERMINAL
9
8
1
PIN 1 ID
1.6 0.1
8X
0.4
8X
0.2
0.32
0.18
0.1
0.05
C A B
C
4218900/C 04/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
8X (0.5)
( 0.2) VIA
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(R0.05) TYP
(1.9)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218900/C 04/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
SYMM
METAL
1
8
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/C 04/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
SCALE 2.800
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
1
3.1
2.9
NOTE 3
2X
1.95
4
5
B
4.5
4.3
NOTE 4
SEE DETAIL A
8X
0.30
0.19
0.1
C A
1.2 MAX
B
(0.15) TYP
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
1
8
(R0.05)
TYP
SYMM
6X (0.65)
5
4
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
(R0.05) TYP
1
8
SYMM
6X (0.65)
5
4
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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