Texas Instruments | INA333-Q1 Automotive, Zerø-Drift, micro-Power, Instrumentation Amplifier | Datasheet | Texas Instruments INA333-Q1 Automotive, Zerø-Drift, micro-Power, Instrumentation Amplifier Datasheet

Texas Instruments INA333-Q1 Automotive, Zerø-Drift, micro-Power, Instrumentation Amplifier Datasheet
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INA333-Q1
SBOS464 – OCTOBER 2019
INA333-Q1 Automotive, Zerø-Drift, micro-Power, Instrumentation Amplifier
1 Features
3 Description
•
The INA333-Q1 is a low-power, precision
instrumentation amplifier offering excellent accuracy.
The versatile three-operational-amplifier design, small
size, and low power make this device an excellent
choice for a wide range of automotive applications
that use resistive bridge sensors.
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 qualified for automotive applications:
– Temperature grade 1: –40°C ≤ TA ≤ +125°C
Low offset voltage: 25 μV (maximum), G ≥ 100
Low drift: 0.1 μV/°C, G ≥ 100
Low noise: 50 nV/√Hz, G ≥ 100
High CMRR: 100 dB (minimum), G ≥ 10
Low input bias current: 200 pA (maximum)
Supply range: 1.8 V to 5.5 V
Input voltage: (V–) + 0.1 V to (V+) – 0.1 V
Output range: (V–) + 0.05 V to (V+) – 0.05 V
Low quiescent current: 50 μA
Operating temperature: –40°C to +125°C
RFI filtered inputs
Package: 8-Pin VSSOP
A single external resistor sets any gain from 1 to
1000. The INA333-Q1 is designed to use an industrystandard gain equation: G = 1 + (100 kΩ / RG).
The INA333-Q1 provides very low offset voltage (25
μV, G ≥ 100), excellent offset voltage drift
(0.1 μV/°C, G ≥ 100), and high common-mode
rejection (100 dB at G ≥ 10). The device operates
with power supplies as low as 1.8 V (±0.9 V) and
quiescent current is only 50 μA, making this device
an excellent choice for battery-operated systems.
Autocalibration
techniques
maintain
excellent
precision over the industrial temperature range. The
INA333-Q1 also offers exceptionally low noise density
(50 nV/√Hz) that extends down to dc.
2 Applications
•
•
•
•
•
•
Powertrain torque sensor
Powertrain pressure sensor
Powertrain temperature sensor
Powertrain knock sensor
Vehicle occupant detection sensor
Driver vital sign monitoring
The INA333-Q1 device is available in an 8-pin
VSSOP package and is specified over the
TA = –40°C to +125°C temperature range.
Device Information(1)
PART NUMBER
PACKAGE
INA333-Q1
VSSOP (8)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Simplified Schematic
V+
7
VIN- 2
RFI Filtered Inputs
150
+
150
A1
RFI Filtered Inputs
1
RG
±
50 k
±
A3
+
50 k
6 VOUT
8
RFI Filtered Inputs
VIN+ 3
RFI Filtered Inputs
±
A2
+
150
150
5 REF
INA333-Q1
4
V-
G
1
§ 100 k: ·
¨
¸
¨ RG ¸
©
¹
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
ADVANCE INFORMATION
1
INA333-Q1
SBOS464 – OCTOBER 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
7.4 Device Functional Modes........................................ 13
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application ................................................. 15
9 Power Supply Recommendations...................... 20
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 20
11 Device and Documentation Support ................. 21
11.1
11.2
11.3
11.4
11.5
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
Device Support......................................................
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
22
22
22
22
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
ADVANCE INFORMATION
4 Revision History
2
DATE
REVISION
NOTES
October 2019
*
Initial release.
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5 Pin Configuration and Functions
DGK Package
8-Pin VSSOP
Top View
RG
1
8
RG
VIN±
2
7
V+
VIN+
3
6
VOUT
V±
4
5
REF
Not to scale
Pin Functions
NO.
I/O
DESCRIPTION
REF
5
I
RG
1, 8
—
Gain setting pins. For gains greater than 1, place a gain resistor between pins 1 and 8.
V+
7
—
Positive supply
V–
4
—
Negative supply
VIN+
3
I
Positive input
VIN–
2
I
Negative input
VOUT
6
O
Output
ADVANCE INFORMATION
PIN
NAME
Reference input. This pin must be driven by low impedance or connected to ground.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
Supply voltage
Analog input voltage
(2)
(V–) – 0.3
Output short-circuit (3)
TA
Operating temperature
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
UNIT
7
V
(V+) + 0.3
V
150
°C
150
°C
150
°C
Continuous
–40
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should be
current limited to 10 mA or less.
Short-circuit to ground.
ADVANCE INFORMATION
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
HBM ESD classification level 3A
UNIT
(1)
±4000
V
Charged-device model (CDM), per AEC Q100-011
CDM ESD classification level C6
±1000
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VS
Supply voltage
1.8
5.5
V
TA
Specified temperature
–40
125
°C
6.4 Thermal Information
INA333-Q1
THERMAL METRIC (1)
DGK (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
169.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
62.7
°C/W
RθJB
Junction-to-board thermal resistance
90.3
°C/W
ψJT
Junction-to-top characterization parameter
7.6
°C/W
ψJB
Junction-to-board characterization parameter
88.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
at VS = 1.8 V to 5.5 V at TA = 25°C, RL = 10 kΩ, VREF = VS / 2, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±10 ±25/G
±25 ±75/G
μV
±1 ±5/G
±5 ±15/G
μV/V
±0.1 ±0.5/G
μV/°C
INPUT (1)
Offset voltage, RTI (2)
VOSI
PSRR
Power-supply rejection ratio
TA = –40°C to +125°C
Long-term stability
Turn on time to specified VOSI
ZIN
Input impedance
VCM
Common-mode voltage
CMRR
Common-mode rejection ratio
See
TA = –40°C to +125°C
(3)
See Typical Characteristics
Differential
100 || 3
Common-mode
100 || 3
VO = 0 V
(V–) + 0.1
DC to 60 Hz,
VCM = (V–) + 0.1 V to (V+) – 0.1 V
GΩ || pF
(V+) – 0.1
G=1
80
90
G = 10
100
110
G = 100
100
115
G = 1000
100
115
V
dB
INPUT BIAS CURRENT
Input bias current
IOS
Input offset current
±70
TA = –40°C to +125°C
See Figure 26
TA = –40°C to +125°C
See Figure 28
±50
±200
pA
ADVANCE INFORMATION
IB
pA/°C
±200
pA
pA/°C
INPUT VOLTAGE NOISE
eNI
Input voltage noise
G = 100, RS = 0 Ω
f = 10 Hz
50
f = 100 Hz
50
f = 1 kHz
50
f = 0.1 Hz to
10 Hz
iN
Input current noise
nV/√Hz
1
f = 10 Hz
μVPP
100
f = 0.1 Hz to 10 Hz
fA/√Hz
2
pAPP
GAIN
Gain equation
G
1 + (100 kΩ/RG)
Gain
Gain error
1
VS = 5.5 V,
(V–) + 100 mV ≤ VO ≤ (V+) – 100 mV
Gain drift error
VS = 5.5 V,
(V–) + 100 mV ≤ VO ≤ (V+) – 100 mV,
TA = –40°C to +125°C
Gain nonlinearity
VS = 5.5 V,
(V–) + 100 mV ≤ VO ≤ (V+) – 100 mV,
RL = 10 kΩ
Output voltage swing from rail
VS = 5.5 V, RL = 10 kΩ
V/V
1000
G=1
±0.01%
±0.1%
G = 10
±0.05%
±0.25%
G = 100
±0.07%
±0.25%
G = 1000
±0.25%
±0.5%
G=1
G > 1 (4)
V/V
±1
±5
ppm/°C
±15
±50
ppm/°C
10
ppm
OUTPUT
See Figure 29
Capacitive load drive
ISC
(1)
(2)
(3)
(4)
Short-circuit current
50
500
Continuous to common
Source
Sink
5
–40
mV
pF
mA
Total VOS, referred-to-input = (VOSI) + (VOSO / G).
RTI = Referred-to-input.
300-hour life test at 150°C demonstrated randomly distributed variation of approximately 1 μV.
Does not include effects of external resistor RG.
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Electrical Characteristics (continued)
at VS = 1.8 V to 5.5 V at TA = 25°C, RL = 10 kΩ, VREF = VS / 2, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
G=1
Bandwidth, –3 dB
SR
Slew rate
Settling time to 0.01%
tS
Settling time to 0.001%
Overload recovery
150
G = 10
35
G = 100
3.5
G = 1000
350
VS = 5 V, VO = 4-V step, G = 1
0.16
VS = 5 V, VO = 4-V step, G = 100
0.05
VSTEP = 4 V, G = 1
kHz
Hz
V/μs
50
VSTEP = 4 V, G = 100
400
VSTEP = 4 V, G = 1
μs
60
VSTEP = 4 V, G = 100
500
50% overdrive
75
μs
REFERENCE INPUT
RIN
Input impedance
300
ADVANCE INFORMATION
Reference input voltage
V–
kΩ
V+
V
POWER SUPPLY
IQ
6
Quiescent current
VIN = VS / 2
50
VIN = VS / 2, TA = –40°C to +125°C
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75
80
μA
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6.6 Typical Characteristics
-0.10
-0.09
-0.08
-0.07
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
-25.0
-22.5
-20.0
-17.5
-15.0
-12.5
-10.0
-7.5
-5.0
-2.5
0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
22.5
25.0
Population
Population
at TA = 25°C, VS = 5 V, RL = 10 kΩ, VREF = midsupply, and G = 1 (unless otherwise noted)
Input Offset Voltage (µV)
Figure 1. Input Offset Voltage
ADVANCE INFORMATION
Input Voltage Offset Drift (µV/°C)
-75.0
-67.5
-60.0
-52.5
-45.0
-37.5
-30.0
-22.5
-15.0
-7.5
0
7.5
15.0
22.5
30.0
37.5
45.0
52.5
60.0
67.5
75.0
-0.50
-0.45
-0.40
-0.35
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Population
Population
Figure 2. Input Voltage Offset Drift (–40°C to 125°C)
Output Offset Voltage (µV)
Output Voltage Offset Drift (µV/°C)
Figure 4. Output Voltage Offset Drift (–40°C to 125°C)
Figure 3. Output Offset Voltage
0
VS = 1.8 V
-5
Noise (1 µV/div)
VOS (µV)
VS = 5 V
-10
-15
-20
-25
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Time (1 s/div)
VCM (V)
Figure 5. Offset Voltage vs Common-Mode Voltage
Figure 6. 0.1-Hz to 10-Hz Noise
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩ, VREF = midsupply, and G = 1 (unless otherwise noted)
Noise (0.5 µV/div)
1000
Output Noise
100
100
Current Noise
Input Noise
10
10
2
(Input Noise) +
Total Input-Referred Noise =
(Output Noise)
2
G
1
1
0.1
Time (1 s/div)
Current Noise Density (fA/ÖHz)
Voltage Noise Density (nV/ÖHz)
1000
1
10
100
1k
10k
Frequency (Hz)
Figure 8. Spectral Noise Density
Figure 7. 0.1-Hz to 10-Hz Noise
G = 1000
G = 100
G = 10
G=1
0.008
Output Voltage (1 V/div)
DC Output Nonlinearity Error (%FSR)
ADVANCE INFORMATION
0.012
0.004
0
-0.004
-0.008
-0.012
0
0.5
1.0
1.5
2.0
2.5
3.0 3.5
4.0
4.5
5.0
5.5
Time (25 µs/div)
VOUT (V)
Figure 10. Large Signal Response
Output Voltage (1 V/div)
Output Voltage (50 mV/div)
Figure 9. Nonlinearity Error
Time (100 µs/div)
Time (10 µs/div)
Figure 11. Large-Signal Step Response
8
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Figure 12. Small-Signal Step Response
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩ, VREF = midsupply, and G = 1 (unless otherwise noted)
Output Voltage (50 mV/div)
10000
Time (ms)
1000
0.001%
100
0.01%
0.1%
10
1
Time (100 µs/div)
1000
100
10
Gain (V/V)
ADVANCE INFORMATION
Figure 14. Settling Time vs Gain
Figure 13. Small-Signal Step Response
80
G = 1000
Supply
60
G = 100
40
Gain (dB)
Supply (1 V/div)
VOUT (50 µV/div)
VOUT
G = 10
20
G=1
0
-20
-40
-60
10
Time (50 µs/div)
100
10k
1k
100k
1M
Frequency (Hz)
Figure 16. Gain vs Frequency
Figure 15. Start-Up Settling Time
10
VS = ±2.75 V
8
G=1
VS = ±0.9 V
Population
CMRR (µV/V)
6
4
G = 10
2
0
-2
-4
G = 100,
G = 1000
-6
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
-8
-10
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
CMRR (µV/V)
Figure 17. Common-Mode Rejection Ratio
Figure 18. Common-Mode Rejection Ratio vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩ, VREF = midsupply, and G = 1 (unless otherwise noted)
160
2.5
2.0
Common-Mode Voltage (V)
140
G = 1000
CMRR (dB)
120
G = 100
100
80
60
G=1
40
G = 10
20
1.0
0
-1.0
-2.0
2.5
0
10
100k
10k
1k
100
-2.5 -2.0
0
-1.0
Frequency (Hz)
2.0
1.0
2.5
Output Voltage (V)
Figure 19. Common-Mode Rejection Ratio vs Frequency
Figure 20. Typical Common-Mode Range vs Output Voltage
0.9
ADVANCE INFORMATION
5
Common-Mode Voltage (V)
Common-Mode Voltage (V)
0.7
4
3
2
1
0.5
0.3
0.1
-0.1
-0.3
-0.5
-0.7
-0.9
0
0
3
2
1
-0.9
5
4
-0.7
-0.3
0.1
-0.1
0.3
0.5
0.7
0.9
Figure 22. Typical Common-Mode Range vs Output Voltage
1.8
160
1.6
140
1.4
120
1.2
+PSRR (dB)
Common-Mode Voltage (V)
Figure 21. Typical Common-Mode Range vs Output Voltage
1.0
0.8
0.6
G = 1000
100
G = 100
80
60
G = 10
40
0.4
G=1
20
0.2
0
0
0
10
-0.5
Output Voltage (V)
Output Voltage (V)
0.2
0.4
0.5
0.8
1.0
1.2
1.4
1.6
1.8
1
10
100
1k
10k
100k
1M
Output Voltage (V)
Frequency (Hz)
Figure 23. Typical Common-Mode Range vs Output Voltage
Figure 24. Positive Power-Supply Rejection Ratio
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩ, VREF = midsupply, and G = 1 (unless otherwise noted)
1200
160
140
G = 1000
-IB
800
100
IB (pA)
-PSRR (dB)
120
80
+IB
1000
G = 100
G = 10
60
600
400
VS = ±0. 9 V
40
VS = ±2.75 V
200
G=1
20
0
0
-200
-20
10
1
100
1k
10k
-50
1M
100k
25
0
-25
50
75
125
100
150
Temperature (°C)
Frequency (Hz)
Figure 25. Negative Power-Supply Rejection Ratio
Figure 26. Input Bias Current vs Temperature
ADVANCE INFORMATION
0.1
250
200
180
200
160
150
120
IOS (pA)
| IB | (pA)
140
100
80
60
100
VS = ±2.75 V
50
0
VS = ±0.9 V
40
-50
20
-100
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
-50
5.0
-25
0
25
50
75
125
100
150
VCM (V)
Temperature (°C)
Figure 27. Input Bias Current vs Common-Mode Voltage
Figure 28. Input Offset Current vs Temperature
80
(V+)
(V+) - 0.25
(V+) - 0.50
(V+) - 0.75
(V+) - 1.00
(V+) - 1.25
(V+) - 1.50
(V+) - 1.75
VS = ±2.75 V
70
VS = ±0.9 V
VS = 5 V
60
50
IQ (µA)
VOUT (V)
0
(V-) + 1.75
(V-) + 1.50
(V-) + 1.25
(V-) + 1.00
(V-) + 0.75
(V-) + 0.50
(V-) + 0.25
(V-)
40
VS = 1.8 V
30
20
125°C
25°C
-40°C
10
0
0
10
20
30
40
50
60
-50
-25
IOUT (mA)
0
25
50
75
100
125
150
Temperature (°C)
Figure 29. Output Voltage Swing vs Output Current
Figure 30. Quiescent Current vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩ, VREF = midsupply, and G = 1 (unless otherwise noted)
80
70
VS = 5 V
60
IQ (µA)
50
40
VS = 1.8 V
30
20
10
0
0
1.0
3.0
2.0
4.0
5.0
VCM (V)
Figure 31. Quiescent Current vs Common-Mode Voltage
ADVANCE INFORMATION
12
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7 Detailed Description
7.1 Overview
The INA333-Q1 is a monolithic instrumentation amplifier (INA) based on the precision zero-drift INA333-Q1
(operational amplifier) core. The INA333-Q1 also integrates laser-trimmed resistors to maintain excellent
common-mode rejection and low gain error. The combination of the zero-drift amplifier core and the precision
resistors allows this device to achieve outstanding dc precision, and makes the INA333-Q1 an excellent choice
for many 3.3-V and 5-V automotive applications.
7.2 Functional Block Diagram
V+
7
VIN- 2
RFI Filtered Inputs
150
+
150
A1
RFI Filtered Inputs
1
±
RG
±
A3
+
50 k
6 VOUT
8
RFI Filtered Inputs
VIN+ 3
RFI Filtered Inputs
±
A2
+
150
150
5 REF
INA333-Q1
4
V-
G
1
§ 100 k: ·
¨
¸
¨ RG ¸
©
¹
7.3 Feature Description
7.3.1 Operating Voltage
The INA333-Q1 operates over a power-supply range of 1.8 V to 5.5 V (±0.9 V to ±2.75 V). Supply voltages
greater than 7 V (absolute maximum) can permanently damage the device. Parameters that vary over supply
voltage or temperature are shown in the Typical Characteristics section of this data sheet.
7.3.2 Internal Offset Correction
The INA333-Q1 internal operational amplifiers use an auto-calibration technique with a time-continuous, 350-kHz
operational amplifier in the signal path. The amplifier is zero-corrected every 8 µs using a proprietary technique.
At power up, the amplifier requires approximately 100 µs to achieve the specified VOS accuracy. This design has
no aliasing or flicker noise.
7.3.3 Input Protection
The input pins of the INA333-Q1 are protected with internal diodes connected to the power-supply rails. These
diodes clamp and prevent the applied signal from damaging the input circuitry. If the input signal voltage exceeds
the power supplies by greater than 0.3 V, limit the input signal current to less than 10 mA to protect the internal
clamp diodes. This current limiting is generally done with a series input resistor. Some signal sources are
inherently current-limited and do not require limiting resistors.
7.4 Device Functional Modes
The INA333-Q1 has a single functional mode and is operational when the power-supply voltage is greater than
1.8 V. The recommended maximum specified power-supply voltage for the INA333-Q1 is 5.5 V.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The INA333-Q1 measures small differential voltage with high common-mode voltage developed between the
noninverting and inverting input. The high input impedance makes the INA333-Q1 a great choice for a wide
range of applications. The ability to set the reference pin to adjust the functionality of the output signal offers
additional flexibility that is practical for multiple configurations.
8.1.1 Input Common-Mode Range
ADVANCE INFORMATION
The linear input voltage range of the input circuitry of the INA333-Q1 is from approximately 0.1 V below the
positive supply voltage to 0.1 V above the negative supply. As a differential input voltage causes the output
voltage to increase, however, the linear input range is limited by the output voltage swing of amplifiers A1 and
A2. Thus, the linear common-mode input range is related to the output voltage of the complete amplifier. This
behavior also depends on supply voltage; see Figure 20 to Figure 23 in the Typical Characteristics section.
Input overload conditions can produce an output voltage that appears normal. For example, if an input overload
condition drives both input amplifiers to the respective positive output swing limit, the difference voltage
measured by the output amplifier is near zero. The output of the INA333-Q1 is near 0 V even though both inputs
are overloaded.
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8.2 Typical Application
Figure 32 shows the basic connections required for operation of the INA333-Q1. Good layout practice mandates
the use of bypass capacitors placed close to the device pins as shown.
The output of the INA333-Q1 is referred to the output reference (REF) pin, which is normally grounded. This
connection must be low-impedance to maintain good common-mode rejection. Although 15 Ω or less of stray
resistance can be tolerated while maintaining specified CMRR, small stray resistances of tens of ohms in series
with the REF pin can cause noticeable degradation in CMRR.
0.1 µF
V+
7
RFI Filtered Inputs
150 k
+
150 k
VO
A1
RFI Filtered Inputs
1
RG
G u V IN
±
G
50 k
±
A3
+
50 k
6
1
V IN
100 k:
RG
+
VOUT
Also drawn in simplified form:
VIN±
Load
8
RFI Filtered Inputs
VIN+ 3
150 k
±
A2
+
RFI Filtered Inputs
150 k
5
REF
±
VO
RG
INA333-Q1
VO
±
VIN+
+
REF
INA333-Q1
4
V±
0.1 µF
Figure 32. Basic Connections
8.2.1 Design Requirements
The device can be configured to monitor the input differential voltage when the gain of the input signal is set by
the external resistor RG. The output signal references to the Ref pin. The most common application is where the
output is referenced to ground when no input signal is present by connecting the Ref pin to ground. When the
input signal increases, the output voltage at the OUT pin increases, too.
8.2.2 Detailed Design Procedure
8.2.2.1 Setting the Gain
Gain of the INA333-Q1 is set by a single external resistor, RG, connected between pins 1 and 8. The value of RG
is selected according to Equation 1:
G = 1 + (100 kΩ / RG)
(1)
Table 1 lists several commonly-used gains and resistor values. The 100 kΩ in Equation 1 comes from the sum of
the two internal feedback resistors of A1 and A2. These on-chip resistors are laser trimmed to accurate absolute
values. The accuracy and temperature coefficient of these resistors are included in the gain accuracy and drift
specifications of the INA333-Q1.
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Typical Application (continued)
The stability and temperature drift of the external gain setting resistor, RG, also affects gain. The contribution of
RG to gain accuracy and drift can be directly inferred from the gain Equation 1. Low resistor values required for
high gain can make wiring resistance important. Sockets add to the wiring resistance and contribute additional
gain error (possibly an unstable gain error) in gains of approximately 100 or greater. To maintain stability, avoid
parasitic capacitance of more than a few picofarads at the RG connections. Careful matching of any parasitics on
both RG pins maintains optimal CMRR over frequency.
Table 1. Commonly-Used Gains and Resistor Values
ADVANCE INFORMATION
(1)
DESIRED GAIN
RG (Ω)
NEAREST 1% RG (Ω)
1
NC (1)
NC
2
100k
100k
5
25k
24.9k
10
11.1k
11k
20
5.26k
5.23k
50
2.04k
2.05
100
1.01k
1k
200
502.5
499
500
200.4
200
1000
100.1
100
NC denotes no connection. When using the SPICE model, the simulation will not converge unless a
resistor is connected to the RG pins; use a very large resistor value.
8.2.2.2 Offset Trimming
Most applications require no external offset adjustment; however, if necessary, adjustments can be made by
applying a voltage to the REF pin. Figure 33 shows an optional circuit for trimming the output offset voltage. The
voltage applied to REF pin is summed at the output. The operational amplifier buffer provides low impedance at
the REF pin to preserve good common-mode rejection.
VIN-
±
V+
RG
VIN+
INA333-Q1
+
VO
100 µA
½ REF200
Ref
100
OPA333
± 10mV
Adjustment Range
10 k
100
100 µA
½ REF200
V-
Figure 33. Optional Trimming of Output Offset Voltage
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8.2.2.3 Noise Performance
The auto-calibration technique used by the INA333-Q1 results in reduced low frequency noise, typically only 50
nV/√Hz (G = 100). The spectral noise density is shown in detail in Figure 8. The low-frequency noise of the
INA333-Q1 is approximately 1 μVPP measured from 0.1 Hz to 10 Hz (G = 100).
8.2.2.4 Input Bias Current Return Path
The input impedance of the INA333-Q1 is extremely high; approximately 100 GΩ. However, a path must be
provided for the input bias current of both inputs. This input bias current is typically ±70 pA. High input
impedance means that this input bias current changes very little with varying input voltage.
Input circuitry must provide a path for this input bias current for proper operation. Figure 34 shows various
provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds
the common-mode range of the INA333-Q1, and the input amplifiers will saturate. If the differential source
resistance is low, the bias current return path can be connected to one input (see the thermocouple example in
Figure 34). With higher source impedance, use two equal resistors to provide a balanced input with the possible
advantages of a lower input offset voltage as a result of bias current, and improved high-frequency commonmode rejection.
Microphone,
Hydrophone,
and more
ADVANCE INFORMATION
±
INA333-Q1
+
±
Thermocouple
INA333-Q1
+
10 NŸ
±
INA333-Q1
+
GND
Figure 34. Providing an Input Common-Mode Current Path
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8.2.2.5 Low Voltage Operation
The INA333-Q1 can be operated on power supplies as low as ±0.9 V. Most parameters vary only slightly
throughout this supply voltage range; see the Typical Characteristics section. Operation at very-low supply
voltage requires careful attention to make sure that the input voltages remain within the linear range. Voltage
swing requirements of internal nodes limit the input common-mode range with low power-supply voltage.
Figure 20 to Figure 23 show the range of linear operation for various supply voltages and gains.
8.2.2.6 Single-Supply Operation
The INA333-Q1 can be used on single power supplies of 1.8 V to 5.5 V. Figure 35 shows a basic single-supply
circuit. The output REF pin is connected to midsupply. Zero differential input voltage demands an output voltage
of midsupply. Actual output voltage swing is limited to approximately 50 mV more than ground, when the load is
referred to ground, as shown. Figure 29 shows how the output voltage swing varies with output current.
With single-supply operation, VIN+ and VIN– must both be 0.1 V greater than ground for linear operation. For
instance, the inverting input cannot be connected to ground to measure a voltage connected to the noninverting
input.
ADVANCE INFORMATION
To show the issues affecting low voltage operation, consider the circuit in Figure 35 that shows the INA333-Q1
operating from a single 3-V supply. A resistor in series with the low side of the bridge makes sure that the bridge
output voltage is within the common-mode range of the amplifier inputs.
+3 V
3V
2 V - DV
RG
300 Ÿ
2 V + DV
±
INA333-Q1
+
VO
REF
1.5 V
150 Ÿ
R1(1)
(1)
R1 creates proper common-mode voltage, only for low-voltage operation; see the Single-Supply Operation section.
Figure 35. Single-Supply Bridge Amplifier
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Output Voltage (1 V/div)
Output Voltage (1 V/div)
8.2.3 Application Curves
Time (25 µs/div)
Time (100 µs/div)
ADVANCE INFORMATION
Figure 37. Large-Signal Step Response
Output Voltage (50 mV/div)
Output Voltage (50 mV/div)
Figure 36. Large Signal Response
Time (10 µs/div)
Time (100 µs/div)
Figure 38. Small-Signal Step Response
Figure 39. Small-Signal Step Response
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9 Power Supply Recommendations
The minimum power supply voltage for INA333-Q1 is 1.8 V, and the maximum power supply voltage is 5.5 V; for
specified performance, 3.3 V to 5 V is recommended. Add a bypass capacitor at the input to compensate for the
layout and power supply source impedance.
10 Layout
10.1 Layout Guidelines
Attention to good layout practices is always recommended.
• Keep traces short.
• When possible, use a printed-circuit-board (PCB) ground plane with surface-mount components placed as
close to the device pins as possible.
• Place a 0.1-μF bypass capacitor closely across the supply pins.
These guidelines should be applied throughout the analog circuit to improve performance, and provide benefits
such as reducing the electromagnetic-interference (EMI) susceptibility.
ADVANCE INFORMATION
Instrumentation amplifiers vary in susceptibility to radio-frequency interference (RFI). RFI can generally be
identified as a variation in offset voltage or dc signal levels with changes in the interfering RF signal. The
INA333-Q1 has been specifically designed to minimize susceptibility to RFI by incorporating passive RC filters
with an 8-MHz corner frequency at the VIN+ and VIN– inputs. As a result, the INA333-Q1 demonstrates remarkably
low sensitivity compared to previous-generation devices. Strong RF fields may continue to cause varying offset
levels, however, and may require additional shielding.
10.2 Layout Example
Gain Resistor
Bypass
Capacitor
RG
RG
VIN-
V-IN
V+
VIN+
V+IN
VO
VOUT
V-
Ref
GND
V+
Bypass
Capacitor
V-
GND
Figure 40. Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI (Free Download Software)
Using TINA-TI SPICE-Based Analog Simulation Program with the INA333-Q1
TINA is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully functional version of the TINA software, preloaded with a library of macromodels in addition to a range
of both passive and active models. It provides all the conventional dc, transient, and frequency domain analysis
of SPICE as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways.
Figure 41 shows example TINA-TI circuits for the INA333-Q1 device that can be used to develop, modify, and
assess the circuit design for specific applications. Links to download these simulation files are given below.
NOTE
These files require that either the TINA software (from DesignSoft) or TINA-TI software be
installed. Download the free TINA-TI software from the TINA-TI folder.
3V
R1
2 NŸ
Rwa
3Ÿ
EMU21 RTD3
±
Pt100 RTD
±
RWb
3Ÿ
VT+
RTD+
VT-
RTD-
U2
OPA333-Q1
+ +
2
VT 25
Mon-
RGAIN
100 NŸ
3V
MonRWc
4Ÿ
+
Temp (°C)
(Volts = °C)
RZERO
100 Ÿ
1
U1 INA333-Q1
±
RG
V-
VOFF
PGA112
MSP430
Out
8
3
6
Ref
RG
V+
5
+
7
V
VREF
3V
VRTD
RWd
3Ÿ
RTD Resistance
(Volts = Ohms)
+
+
A
IREF1
A
IREF2
3V
VREF
U1 REF3212
VREF
EN
+
OUTF
3V
Use BF861A
+
T3 BF256A
Use BF861A
3V
T1 BF256A
+
+
In
OUTS
C7
470 nF
GNDF GNDS
OPA333-Q1
±
VREF
U3
OPA333-Q1
±
3V
+
V4 3
RSET1
2.5 NŸ
RSET2
2.5 NŸ
RWa, RWb, RWc, and RWd simulate wire resistance. These resistors are included to show the four-wire sense technique immunity to line
mismatches. This method assumes the use of a four-wire RTD.
Figure 41. Four-Wire, 3-V Conditioner for a PT100 RTD With Programmable Gain Acquisition System
Download the TINA-TI simulation file for this circuit with the following link: PT100 RTD.
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Virtual instruments offer users the ability to select input waveforms and probe circuit nodes, voltages, and
waveforms, creating a dynamic quick-start tool.
INA333-Q1
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11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, OPA188-Q1 Precision, Low-Noise, Rail-to-Rail Output, 36-V, Zero-Drift, AutomotiveGrade Operational Amplifier data sheet
• Texas Instruments, OPA333-Q1 1.8-V microPower CMOS Operational Amplifier Zero-Drift Series data sheet
• Texas Instruments, Circuit board layout techniques
11.3 Trademarks
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ADVANCE INFORMATION
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
INA333QDGKRQ1
PREVIEW
VSSOP
DGK
8
2500
TBD
Call TI
Call TI
-40 to 125
PINA333QDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
TBD
Call TI
Call TI
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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OTHER QUALIFIED VERSIONS OF INA333-Q1 :
• Catalog: INA333
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
IMPORTANT NOTICE AND DISCLAIMER
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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