Texas Instruments | OPA855 8-GHz Gain Bandwidth Product, Gain of 7-V/V Stable, Bipolar Input Amplifier (Rev. A) | Datasheet | Texas Instruments OPA855 8-GHz Gain Bandwidth Product, Gain of 7-V/V Stable, Bipolar Input Amplifier (Rev. A) Datasheet

Texas Instruments OPA855 8-GHz Gain Bandwidth Product, Gain of 7-V/V Stable, Bipolar Input Amplifier (Rev. A) Datasheet
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OPA855
SBOS622A – JULY 2018 – REVISED OCTOBER 2018
OPA855 8-GHz Gain Bandwidth Product, Gain of 7-V/V Stable, Bipolar Input Amplifier
1 Features
3 Description
•
•
•
•
•
The OPA855 is a wideband, low-noise operational
amplifier with bipolar inputs for wideband
transimpedance and voltage amplifier applications.
When the device is configured as a transimpedance
amplifier (TIA), the 8-GHz gain bandwidth product
(GBWP) enables high closed-loop bandwidths at
transimpedance gains of up to tens of kΩs.
High Gain Bandwidth Product: 8 GHz
Decompensated, Gain ≥ 7 V/V (Stable)
Low Input Voltage Noise: 0.98 nV/√Hz
Slew Rate: 2750 V/µs
Low Input Capacitance:
– Common-Mode: 0.6 pF
– Differential: 0.2 pF
Wide Input Common-Mode Range:
– 0.4 V from Positive Supply
– 1.1 V from Negative Supply
3 VPP Total Output Swing
Supply Voltage Range: 3.3 V to 5.25 V
Quiescent Current: 17.8 mA
Package: 8-Pin WSON
Temperature Range: –40 to +125°C
•
•
•
•
•
•
The graph below shows the bandwidth and noise
performance of the OPA855 as a function of the
photodiode capacitance when the amplifier is
configured as a TIA. The total noise is calculated
along a bandwidth range extending from dc to the
calculated frequency, f, on the left-hand scale. The
OPA855 package has a feedback pin (FB) that
simplifies the feedback network connection between
the input and the output.
2 Applications
•
•
•
•
•
•
•
•
•
High-Speed Transimpedance Amplifier
Laser Distance Measurement
CCD Output Buffer
High-Speed Buffer
Optical Time Domain Reflectometry (OTDR)
High-Speed Active Filter
3D Scanner
Silicon Photomultiplier (SiPM) Buffer Amplifier
Photomultiplier Tube Post Amplifier
High-Speed Time-of-Flight Receiver
The OPA855 is optimized to operate in optical timeof-flight (ToF) systems where the OPA855 is used
with time-to-digital converters, such as the TDC7201.
Use the OPA855 to drive a high-speed analog-todigital converter (ADC) in high-resolution LIDAR
systems with a differential output amplifier, such as
the THS4541 or LMH5401.
Device Information(1)
PART NUMBER
OPA855
TLV3501
±
+
3.8 V
OPA855
+
Stop 2
VREF
±
Start 2
Object
CF
RF
VBIAS
5V
TLV3501
±
TDC7201
(Time-toDigital
Converter)
+
3.8 V
+
OPA855
Stop 1
VREF
±
Start 1
Closed-loop Bandwidth, f-3dB (MHz)
450
5V
2.00 mm × 2.00 mm
Photodiode Capacitance vs Bandwidth and Noise
RF
VBIAS
WSON (8)
BODY SIZE (NOM)
(1) For all available packages, see the package option addendum
at the end of the data sheet.
CF
Rx
Lens
PACKAGE
350
160
f-3dB, RF = 6 k:
f-3dB, RF = 12 k: 140
IRN, RF = 6 k:
IRN, RF = 12 k: 120
300
100
250
80
200
60
150
40
100
20
400
50
0
Tx
Lens
Pulsed Laser
Diode
MSP430
Controller
2
4
6
8
10
12
14
Photodiode capacitance (pF)
16
18
0
20
Integrated Input Referred Noise, IRN (nARMS)
1
D609
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA855
SBOS622A – JULY 2018 – REVISED OCTOBER 2018
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Typical Characteristics ..............................................
8
Parameter Measurement Information ................ 14
9
Detailed Description ............................................ 15
8.1 Parameter Measurement Information ..................... 14
9.1 Overview ................................................................. 15
9.2 Functional Block Diagram ....................................... 15
9.3 Feature Description................................................. 16
9.4 Device Functional Modes........................................ 19
10 Application and Implementation........................ 20
10.1 Application Information.......................................... 20
10.2 Typical Application ............................................... 21
11 Power Supply Recommendations ..................... 23
12 Layout................................................................... 24
12.1 Layout Guidelines ................................................. 24
12.2 Layout Example .................................................... 24
13 Device and Documentation Support ................. 26
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
26
26
14 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
Changes from Original (July 2018) to Revision A
•
2
Page
Changed from Advance Information to Production Data (active) ........................................................................................... 1
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5 Device Comparison Table
DEVICE
INPUT TYPE
MINIMUM STABLE
GAIN
VOLTAGE NOISE
(nV/√Hz)
INPUT
CAPACITANCE (pF)
GAIN BANDWIDTH
(GHz)
OPA855
Bipolar
7 V/V
0.98
0.8
8
OPA858
CMOS
7 V/V
2.5
0.8
5.5
OPA859
CMOS
1 V/V
3.3
0.8
0.9
LMH6629
Bipolar
10 V/V
0.69
5.7
4
6 Pin Configuration and Functions
DSG Package
8-Pin WSON With Exposed Thermal Pad
Top View
FB
1
NC
2
8
PD
7
VS+
Thermal pad
IN±
3
6
OUT
IN+
4
5
VS±
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
FB
1
I
Feedback connection to output of amplifier
IN–
3
I
Inverting input
IN+
4
I
Noninverting input
NC
2
—
Do not connect
OUT
6
O
Amplifier output
PD
8
I
Power down connection. PD = logic low = power off mode; PD = logic high = normal operation.
VS–
5
—
Negative voltage supply
VS+
7
—
Positive voltage supply
—
Connect the thermal pad to VS–
Thermal pad
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SBOS622A – JULY 2018 – REVISED OCTOBER 2018
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VS
Total supply voltage (VS+ – VS–)
VIN+, VIN–
Input voltage
VID
Differential input voltage
VOUT
Output voltage
IIN
Continuous input current
IOUT
Continuous output current (2)
TJ
Junction temperature
TA
Operating free-air temperature
Tstg
Storage temperature
(1)
(2)
MAX
(VS–) – 0.5
(VS–) – 0.5
UNIT
5.5
V
(VS+) + 0.5
V
1
V
(VS+) + 0.5
V
±10
mA
±100
mA
150
°C
–40
125
°C
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Long-term continuous output current for electromigration limits.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
5
5.25
V
125
°C
VS
Total supply voltage (VS+ – VS–)
3.3
TA
Operating free-air temperature
–40
UNIT
7.4 Thermal Information
OPA855
THERMAL METRIC (1)
DSG (WSON)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
80.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
100
°C/W
RθJB
Junction-to-board thermal resistance
45
°C/W
ψJT
Junction-to-top characterization parameter
6.8
°C/W
ψJB
Junction-to-board characterization parameter
45.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
22.7
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
at VS+ = 5 V, VS– = 0 V, G = 7 V/V, RF = 453 Ω, input common-mode biased at midsupply, RL = 200 Ω, output load is
referenced to midsupply, and TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
SSBW
Small-signal bandwidth
VOUT = 100 mVPP
2.5
GHz
LSBW
Large-signal bandwidth
VOUT = 2 VPP
850
MHz
GBWP
Gain-bandwidth product
Bandwdith for 0.1-dB flatness
8
GHz
200
MHz
SR
Slew rate (10%-90%)
VOUT = 2-V step
2750
V/µs
tr
Rise time
VOUT = 100-mV step
0.17
ns
tf
Fall time
VOUT = 100-mV step
0.17
ns
Settling time to 0.1%
VOUT = 2-V step
2.3
ns
Settling time to 0.001%
VOUT = 2-V step
2600
ns
Overshoot or undershoot
VOUT = 2-V step
5%
Overdrive recovery
2x output overdrive
3
f = 10 MHz, VOUT = 2 VPP
90
f = 100 MHz, VOUT = 2 VPP
65
f = 10 MHz, VOUT = 2 VPP
86
f = 100 MHz, VOUT = 2 VPP
74
ns
HD2
Second-order harmonic distortion
dBc
HD3
Third-order harmonic distortion
en
Input-referred voltage noise
f = 1 MHz
0.98
nV/√Hz
ei
Input-referred current noise
f = 1 MHz
2.5
pA/√Hz
zO
Closed-loop output impedance
f = 1 MHz
0.15
Ω
70
76
dB
–1.5
±0.2
dBc
DC PERFORMANCE
AOL
Open-loop voltage gain
VOS
Input offset voltage
TA = 25°C
ΔVOS/ΔT
Input offset voltage drift
TA = –40°C to 125°C
IB
Input bias current
ΔIB/ΔT
Input bias current drift
TA = –40°C to +125°C
IBOS
Input offset current
TA = 25°C
ΔIBOS/ΔT
Input offset current drift
TA = –40°C to +125°C
CMRR
Common-mode rejection ratio
VCM = ±0.5 V referred to midsupply
(1)
TA = 25°C
1.5
0.5
–18.5
–12
–5
–0.08
–1
±0.1
µA
µA/°C
1
1
90
mV
µV/°C
µA
nA/°C
100
dB
Common-mode input resistance
2.3
MΩ
Common-mode input capacitance
0.6
pF
5
kΩ
0.2
pF
INPUT
CCM
Differential input resistance
CDIFF
Differential input capacitance
VIH
Common-mode input range (high)
CMRR > 80 dB, VS+ = 3.3 V
VIL
Common-mode input range (low)
CMRR > 80 dB, VS+ = 3.3 V
VIH
Common-mode input range (high)
CMRR > 80 dB
VIH
Common-mode input range (high)
TA = –40°C to +125 °C, CMRR > 80 dB
4.3
VIL
Common-mode input range (low)
CMRR > 80 dB
1.1
VIL
Common-mode input range (low)
TA = –40°C to +125°C, CMRR > 80 dB
1.3
(1)
2.7
2.9
1.1
4.4
V
1.3
4.6
V
V
V
1.3
V
V
Current flowing into the input pin is considered negative
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Electrical Characteristics (continued)
at VS+ = 5 V, VS– = 0 V, G = 7 V/V, RF = 453 Ω, input common-mode biased at midsupply, RL = 200 Ω, output load is
referenced to midsupply, and TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
TA = 25°C, VS+ = 3.3 V
2.35
2.4
TA = 25°C
3.95
4.1
MAX
UNIT
OUTPUT
Output voltage (high) (2)
VOH
VOH
Output voltage (high) (2)
VOL
Output voltage (low) (2)
VOL
Output voltage (low) (2)
IO_LIN
Linear output drive (sink and source)
ISC
Output short-circuit current
TA = –40°C to +125°C
V
V
4
TA = 25°C, VS+ = 3.3 V
1.05
1.15
TA = 25°C
1.05
1.15
TA = –40°C to +125°C
1.1
RL = 10 Ω, AOL > 60 dB
65
TA = –40°C to +125°C, RL = 10 Ω, AOL > 60 dB
80
105
16
17.8
V
mA
70
85
V
mA
POWER SUPPLY
IQ
Quiescent current
TA = –40°C
16.7
TA = 125°C
19.5
PSRR+
Positive power-supply rejection ratio
80
86
PSRR–
Negative power-supply rejection ratio
70
80
0.65
1
19.5
mA
dB
POWER DOWN
Disable voltage threshold
Amplifier OFF below this voltage
Enable voltage threshold
Amplifier ON below this voltage
1.5
1.8
V
Power-down quiescent current
70
140
μA
PD bias current
70
140
μA
Turnon time delay
Time to VOUT = 90% of final value
Turnoff time delay
(2)
6
V
15
ns
120
ns
Amplifier output saturated
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7.6 Typical Characteristics
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
6
3
3
Normalized Gain (dB)
Normalized Gain (dB)
0
0
-3
-6
Gain = +7 V/V
Gain = 7 V/V
Gain = +10 V/V
Gain = +20 V/V
G = +39.2 V/V
-9
-12
-15
1M
10M
-3
-6
-9
VS = 5 V
V S = 3.3 V
100M
Frequency (Hz)
1G
-12
1M
5G
10M
100M
Frequency (Hz)
D500
VOUT = 100 mVPP; See Parameter Measurement Information for
circuit configuration
1G
5G
D502
VOUT = 100 mVPP
Figure 2. Small-Signal Frequency Response vs Supply
Voltage
Figure 1. Small-Signal Frequency Response vs Gain
3
3
Normalized Gain (dB)
Normalized Gain (dB)
0
-3
-6
-9
-12
1M
R L = 100 :
R L = 200 :
R L = 400 :
10M
100M
Frequency (Hz)
1G
0
-3
TA = 40qC
TA = 0qC
TA = +25qC
TA = +85qC
TA = +125qC
-6
-9
1M
5G
D503
10M
Frequency (Hz)
Gain = 39.2 V/V, RF = 953 Ω
VOUT = 100 mVPP
100M
D504
VOUT = 100 mVPP
Figure 4. Small-Signal Frequency Response vs Ambient
Temperature
Figure 3. Small-Signal Frequency Response vs Output Load
3
4
2
Normalized Gain (dB)
Normalized Gain (dB)
0
0
-2
-4
-6
-8
-10
-12
1M
R S = 16.5 :, C L = 10 pF
R S = 8 :, C L = 47 pF
R S = 5.6 :, C L = 100 pF
R S = 1.6 :, C L = 1 nF
10M
100M
Frequency (Hz)
-3
-6
Gain = +7 V/V
Gain = 7 V/V
Gain = +10 V/V
Gain = +20 V/V
-9
-12
1M
1G
D505
100M
Frequency (Hz)
1G
D506
VOUT = 2 VPP
VOUT = 100 mVPP ; See Figure 45 for circuit configuration
Figure 5. Small-Signal Frequency Response vs Capacitive
Load
10M
Figure 6. Large-Signal Frequency Response vs Gain
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Typical Characteristics (continued)
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
3
0.2
0.1
Normalized Gain (dB)
Normalized Gain (dB)
0
0
-0.1
-0.2
-0.3
-0.4
-3
-6
-9
-0.5
Gain = 7 V/V
-0.6
1M
10M
100M
Frequency (Hz)
VS = 5 V, VOUT = 2 VPP
VS = 5 V, VOUT = 1 VPP
VS = 3.3 V, VOUT = 1 VPP
-12
1M
1G
10M
D507
100M
Frequency (Hz)
1G
5G
D508
VOUT = 2 VPP
Figure 8. Large-Signal Frequency Response vs Voltage
Supply
Closed-Loop Output Impedance (:)
100
90
90
A OL Magnitude (dB)
A OL Phase (q)
Open-Loop Magnitude (dB)
75
10
1
60
0
45
-45
30
-90
15
-135
0
-180
Gain = 7 V/V
Gain = 20 V/V
0.1
1M
10M
Frequency (Hz)
-15
100k
100M
1M
10M
100M
Frequency (Hz)
D509
Small-Signal Response
D510
1.2
10M
1
100M
Input Referred Voltage Noise (nV/—Hz)
10
1
Input Referred Current Noise (pA/ —Hz)
Input Referred Voltage Noise (nV/ —Hz)
Voltage Noise
Current Noise
100k
1M
Frequency (Hz)
-225
10G
Figure 10. Open-Loop Magnitude and Phase vs Frequency
100
10
10k
1G
Small-Signal Response
Figure 9. Closed-Loop Output Impedance vs Frequency
0.1
1k
45
Open-Loop Phase (q)
Figure 7. Large-Signal Response for 0.1-dB Gain Flatness
1.15
1.1
1.05
1
0.95
0.9
0.85
-40
D511
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
140
D512
Frequency = 10 MHz
Figure 11. Voltage and Current Noise Density vs Frequency
8
Figure 12. Voltage Noise Density vs Ambient Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
-40
-60
= 0.5 V PP
= 1 V PP
= 2 V PP
= 2.5 V PP
-70
-80
-90
-100
-110
-120
1M
10M
Frequency (Hz)
-80
-90
-100
10M
Frequency (Hz)
D513
HD2, V OUT = 100 :
HD2, V OUT = 200 :
HD2, V OUT = 400 :
-70
-80
-90
-100
-110
HD3, V OUT = 100 :
HD3, V OUT = 200 :
HD3, V OUT = 400 :
-60
-70
-80
-90
-100
-110
10M
Frequency (Hz)
-120
1M
100M
10M
Frequency (Hz)
D515
VOUT = 2 VPP
Figure 15. Harmonic Distortion (HD2) vs Output Load
Figure 16. Harmonic Distortion (HD3) vs Output Load
HD2, Gain = +7 V/V
HD2, Gain = 7 V/V
HD2, Gain = +10 V/V
HD2, Gain = +20 V/V
HD3, Gain = +7 V/V
HD3, Gain = 7 V/V
HD3, Gain = +10 V/V
HD3, Gain = +20 V/V
-50
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
D516
-40
-70
-80
-90
-100
-110
-120
1M
100M
VOUT = 2 VPP
-40
-60
D514
Figure 14. Harmonic Distortion (HD3) vs Output Swing
-50
-60
-50
100M
-40
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-70
-120
1M
100M
Figure 13. Harmonic Distortion (HD2) vs Output Swing
-120
1M
-60
= 0.5 V PP
= 1 V PP
= 2 V PP
= 2.5 V PP
-110
-40
-50
HD3, V OUT
HD3, V OUT
HD3, V OUT
HD3, V OUT
-50
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-50
-40
HD2, V OUT
HD2, V OUT
HD2, V OUT
HD2, V OUT
-60
-70
-80
-90
-100
-110
10M
Frequency (Hz)
100M
-120
1M
10M
Frequency (Hz)
D517
VOUT = 2 VPP
100M
D518
VOUT = 2 VPP
Figure 17. Harmonic Distortion (HD2) vs Gain
Figure 18. Harmonic Distortion (HD3) vs Gain
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Typical Characteristics (continued)
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
60
1.25
1
0.75
Voltage Swing (V)
Voltage Swing (mV)
40
20
0
-20
0.5
0.25
0
-0.25
-0.5
-0.75
-40
Input
Output
Input
Output
-1
-60
-1.25
Time (5 ns/div)
Time (5 ns/div)
D519
Average Rise and Fall Time (10% - 90%) = 300 ps
Rise and fall time limited by test equipment
Figure 19. Small-Signal Transient Response
Figure 20. Large-Signal Transient Response
4
75
3
50
2
Voltage Swing (V)
Voltage Swing (mV)
D520
Average Rise and Fall Time (10% - 90%) = 569 ps
25
0
-25
-50
RS
RS
RS
RS
= 16.5 :, C L = 10 pF
= 8 :, C L = 47 pF
= 5.6 :, C L = 100 pF
= 1.6 :, C L = 1 nF
1
0
-1
-2
-3
Ideal Output
Measured Output
-4
-75
Time (2 ns/div)
Time (5 ns/div)
D522
D521
2x Output Overdrive
Figure 21. Small-Signal Transient Response vs Capacitive
Load
Figure 22. Output Overload Response
3
3
2
2
Voltage Swing (V)
Voltage Swing (V)
Power Down ( PD)
Output
1
0
-1
-2
1
0
-1
-2
Power Down ( PD)
Output
-3
-3
Time (5 ns/div)
Time (5 ns/div)
D523
Figure 23. Turnon Transient Response
10
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Figure 24. Turnoff Transient Response
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Typical Characteristics (continued)
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
100
120
Power Supply Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB)
CMRR
100
80
60
40
20
0
10k
100k
1M
10M
Frequency (Hz)
100M
PSRR+
PSRR
80
60
40
20
0
10k
1G
100k
1M
10M
Frequency (Hz)
D525
Small-Signal Response
1G
D526
Small-Signal Response
Figure 25. Common-Mode Rejection Ratio vs Frequency
Figure 26. Power Supply Rejection Ratio vs Frequency
19.5
18.25
18
19
17.75
Quiescent Current (mA)
Quiescent Current (mA)
100M
17.5
17.25
17
16.75
16.5
Unit 1
Unit 2
Unit 3
16.25
3.25
3.5
3.75
4
4.25 4.5
Total Supply Voltage (V)
4.75
5
18
17.5
17
16.5
VS = 3.3 V
VS = 5 V
16
-40
16
3
18.5
5.25
-20
0
D560
20
40
60
80
100
Ambient Temperature (qC)
120
140
D561
3 Typical Units
Figure 27. Quiescent Current vs Supply Voltage
Figure 28. Quiescent Current vs Ambient Temperature
0.25
0.75
Unit 1
Unit 2
Unit 3
0.15
0.25
Offset Voltage (mV)
Offset Voltage (mV)
0.5
0
-0.25
-0.5
0.05
-0.05
-0.15
-0.75
-1
3
3.25
3.5
3.75
4
4.25 4.5
Total Supply Voltage (V)
4.75
5
5.25
-0.25
-40
-20
D563
3 Typical Units
µ = 0.4 µV/°C
Figure 29. Offset Voltage vs Supply Voltage
0
20
40
60
80
100
Ambient Temperature (qC)
σ = 0.7 µV/°C
120
140
D564
28 units tested
Figure 30. Offset Voltage vs Ambient Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
1.25
Offset Voltage (mV)
0.75
0.5
Offset Voltage (mV)
1
0.75
Unit 1
Unit 2
Unit 3
0.5
0.25
0
-0.25
-0.5
-0.75
TA = 40qC
TA = +25qC
TA = +125qC
0.25
0
-0.25
-0.5
-1
-1.25
0.5
1
1.5
2
2.5
3
3.5
Common-Mode Voltage (V)
VS+ = 5 V, VS– = 0 V
4
4.5
-0.75
0.5
5
3 Typical Units
1.5
1.5
1
1
Offset Voltage (mV)
Offset Voltage (mV)
2
0
-0.5
2
2.5
3
3.5
Common-Mode Voltage (V)
4
4.5
5
D567
Figure 32. Offset Voltage vs Input Common-Mode Voltage
vs Ambient Temperature
2
0.5
1.5
VS+ = 5 V, VS– = 0 V
Figure 31. Offset Voltage vs Input Common-Mode Voltage
-1
0.5
0
-0.5
-1
Unit 1
Unit 2
Unit 3
-1.5
TA = -40qC
TA = +25qC
TA = +125qC
-1.5
-2
-2
1
1.5
2
2.5
3
3.5
Output Voltage (V)
VS+ = 5 V, VS– = 0 V
4
4.5
1
1.5
D569
3 Typical Units
2
2.5
3
3.5
Output Voltage (V)
4
4.5
D570
VS+ = 5 V, VS– = 0 V
Figure 33. Offset Voltage vs Output Swing
Figure 34. Offset Voltage vs Output Swing vs Ambient
Temperature
0
-7
Unit 1
Unit 2
Unit 3
-8
TA = 40qC
TA = +25qC
TA = +125qC
-5
Input Bias Current (PA)
-9
Input Bias Current (PA)
1
D566
-10
-11
-12
-13
-14
-15
-10
-15
-20
-16
-17
-18
-40
-25
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
140
1
D571
3 Typical Units
2
2.5
3
3.5
Common-Mode Voltage (V)
4
4.5
D572
VS+ = 5 V, VS– = 0 V
Figure 35. Input Bias Current vs Ambient Temperature
12
1.5
Figure 36. Input Bias Current vs Input Common-Mode
Voltage vs Ambient Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
2.2
4.5
TA = 40qC
TA = +25qC
TA = +125qC
4
3.5
Output Voltage (mV)
1.8
1.6
1.4
1.2
3
2.5
2
1.5
1
1
TA = 40qC
TA = +25qC
TA = +125qC
0.5
0.8
-120
0
-100
-80
-60
-40
Output Current (mA)
-20
0
0
20
40
60
80
Output Current (mA)
D573
VS+ = 5 V, VS– = 0 V
Figure 37. Output Swing vs Sinking Current
9000
7000
8000
D574
7000
4000
σ = 0.3 mA
D541
Offset Voltage (mV)
13780 units tested
µ = –0.2 mV
Figure 39. Quiescent Current Distribution
1.5
1.25
1
0.75
0.5
0.25
0
-0.25
-0.5
19.5
17.5
16.5
18.5
D540
Quiescent Current (mA)
µ = 17.6 mA
20
0
19
0
18
1000
17
2000
1000
-0.75
3000
2000
-1
3000
5000
-1.25
4000
6000
-1.5
Amplifiers (Count)
5000
16
σ = 0.15 mV
13780 units tested
Figure 40. Offset Voltage Distribution
8000
9000
Inverting Current
Noninverting Current
7000
8000
7000
Amplifiers (Count)
6000
5000
4000
3000
2000
6000
5000
4000
3000
Input Bias Current (PA)
µ = –11.2 µA
σ = 0.6 µA
D542
13780 units tested
Input Offset Current (PA)
µ = 0.04 µA
Figure 41. Input Bias Current Distribution
σ = 0.1 µA
D543
13780 units tested
Figure 42. Input Offset Current Distribution
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0.8
0.6
0.4
0.2
0
-0.2
-0.8
-6
-7
-8
-9
-10
-11
-12
-13
-14
0
-15
0
-16
1000
-1
2000
1000
-0.6
Amplifiers (Count)
120
Figure 38. Output Swing vs Sourcing Current
8000
6000
Amplifiers (Count)
100
VS+ = 5 V, VS– = 0 V
-0.4
Output Voltage (mV)
2
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8 Parameter Measurement Information
8.1 Parameter Measurement Information
The various test setup configurations for the OPA855 are shown in Figure 43, Figure 44, and Figure 45. When
configuring the OPA855 in a gain of +39.2 V/V, feedback resistor RF was set to 953 Ω.
Figure 1 shows 5-dB of peaking with the amplifier in an inverting configuration of –7 V/V with the amplifier
configured as shown in Figure 44. The 50-Ω matched termination of this circuit configuration results in the
amplifier being configured in a noise gain of 5.3 V/V, which is lower than the recommended +7 V/V.
GND
50
2.5 V
50
50Source
169
+
±
í2.5 V
RG
50
71.5
453
50Measurement
System
GND
GND
GND
RG values depend on gain configuration
Figure 43. Noninverting Configuration
2.5 V
169
+
GND
50Source
50Measurement
System
±
í2.5 V
50
64
50
71.5
GND
453
GND
220
GND
Figure 44. Inverting Configuration (Gain = –7 V/V)
GND
50
50Source
2.5 V
50
+
RS
1k
±
í2.5 V
75
GND
453
CL
GND
50
53.6
50Measurement
System
GND
GND
Figure 45. Capacitive Load Driver Configuration
14
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9 Detailed Description
9.1 Overview
The ultra-wide, 8-GHz gain bandwidth product (GBWP) of the OPA855, combined with the broadband voltage
noise of 0.98 nV/√Hz, produces a viable amplifier for wideband transimpedance applications, high-speed data
acquisition systems, and applications with weak signal inputs that require low-noise and high-gain front ends.
The OPA855 combines multiple features to optimize dynamic performance. In addition to the wide, small-signal
bandwidth, the OPA855 has 850 MHz of large-signal bandwidth (2 VPP), and a slew rate of 2750 V/µs, making
the device a viable option for high-speed pulsed applications.
The OPA855 is offered in a 2-mm × 2-mm, 8-pin WSON package that features a feedback (FB) pin for a simple
feedback network connection between the amplifiers output and inverting input. Excess capacitance on an
amplifiers input pin can reduce phase margin causing instability. This problem is exacerbated in the case of very
wideband amplifiers like the OPA855. To reduce the effects of stray capacitance on the input node, the OPA855
pinout features an isolation pin (NC) between the feedback and inverting input pins that increases the physical
spacing between them thereby reducing parasitic coupling at high frequencies. The OPA855 also features a very
low capacitance input stage with only 0.8-pF of total input capacitance.
9.2 Functional Block Diagram
The OPA855 is a classic, voltage feedback operational amplifier (op amp) with two high-impedance inputs and a
low-impedance output. Standard application circuits are supported, like the two basic options shown in Figure 46
and Figure 47.The resistor on the noninverting pin is used for bias current cancellation to minimize the output
offset voltage. In a noninverting configuration the additional resistors on the noninverting pin add noise to the
system so if SNR is critical, the resistor can be eliminated. In an inverting configuration the noninverting node is
typically connected to a DC voltage, so the high-frequency noise contribution from the bias cancellation resistor
can be bypassed by adding a large 1-µF capacitor in parallel to the resistor to shunt the noise. The DC operating
point for each configuration is level-shifted by the reference voltage (VREF), which is typically set to midsupply in
single-supply operation. VREF is typically connected to ground in split-supply applications.
VSIG
VS+
RF || RG
VREF
VIN
(1+RF/RG)×VSIG
+
VOUT
RG
VREF
±
VS±
VREF
RF
Figure 46. Noninverting Amplifier
VS+
RF || RG
VSIG
VREF
VREF
+
VIN
±
±(RF/RG)×VSIG
VOUT
RG
VREF
VS±
RF
Figure 47. Inverting Amplifier
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9.3 Feature Description
9.3.1 Input and ESD Protection
The OPA855 is fabricated on a low-voltage, high-speed, BiCMOS process. The internal, junction breakdown
voltages are low for these small geometry devices, and as a result, all device pins are protected with internal
ESD protection diodes to the power supplies as Figure 48 shows. There are two antiparallel diodes between the
inputs of the amplifier that clamp the inputs during an overrange or fault condition.
VS+
Power Supply
ESD Cell
VIN+
+
VOUT
±
VINí
FB
VSí
Figure 48. Internal ESD Structure
9.3.2 Feedback Pin
The OPA855 pin layout is optimized to minimize parasitic inductance and capacitance, which is critical in highspeed analog design. The FB pin (pin 1) is internally connected to the output of the amplifier. The FB pin is
separated from the inverting input of the amplifier (pin 3) by a no connect (NC) pin (pin 2). The NC pin must be
left floating. There are two advantages to this pin layout:
1. A feedback resistor (RF) can connect between the FB and IN– pin on the same side of the package (see
Figure 49) rather than going around the package.
2. The isolation created by the NC pin minimizes the capacitive coupling between the FB and IN– pins by
increasing the physical separation between the pins.
RF
FB 1
8
PD
NC 2
7
VS+
6
OUT
5
VS±
±
+
IN± 3
IN+ 4
Figure 49. RF Connection Between FB and IN– Pins
16
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Feature Description (continued)
9.3.3 Wide Gain-Bandwidth Product
Figure 10 shows the open-loop magnitude and phase response of the OPA855. Calculate the gain bandwidth
product of any op amp by determining the frequency at which the AOL is 40 dB and multiplying that frequency by
a factor of 100. The open-loop response shows the OPA855 to have approximately 62° of phase-margin in a
noise gain of 7 V/V. The second pole in the AOL response occurs before the magnitude crosses 0 dB, and the
resultant phase margin is less than 0°. This indicates instability at a gain of 0 dB (1 V/V). Amplifiers that are not
unity-gain stable are known as decompensated amplifiers. Decompensated amplifiers typically have higher gainbandwidth product, higher slew rate, and lower voltage noise, compared to a unity-gain stable amplifier with the
same amount of quiescent power consumption.
Figure 50 shows the open-loop magnitude (AOL) of the OPA855 as a function of temperature. The results show
approximately 5° of phase-margin variation over the entire temperature range in a noise gain of 7 V/V.
Semiconductor process variation is the naturally occurring variation in the attributes of a transistor (Early-voltage,
β, channel-length and width) and other passive elements (resistors and capacitors) when fabricated into an
integrated circuit. The process variation can occur across devices on a single wafer, or, across devices over
multiple wafer lots over time. Typically, the variation across a single wafer is tightly controlled. Figure 51 shows
the AOL magnitude of the OPA855 as a function of process variation over time. The results show the AOL curve
for the nominal process corner and the variation one standard deviation from the nominal. The simulated results
show less than 2° of phase-margin difference within a standard deviation of process variation in a noise gain of 7
V/V.
One of the primary applications for the OPA855 is as a high-speed transimpedance amplifier (TIA). The lowfrequency noise gain of a TIA is 0 dB (1 V/V). At high frequencies the ratio of the total input capacitance and the
feedback capacitance set the noise gain. To maximize the TIA closed-loop bandwidth, the feedback capacitance
is typically smaller than the input capacitance, which implies that the high-frequency noise gain is greater than 0
dB. As a result, op amps configured as TIAs are not required to be unity-gain stable, which makes a
decompensated amplifier a viable option for a TIA. What You Need To Know About Transimpedance Amplifiers –
Part 1 and What You Need To Know About Transimpedance Amplifiers – Part 2 describe transimpedance
amplifier compensation in greater detail.
90
90
AOL at 40qC
AOL at 25qC
AOL at +125qC
60
45
30
15
60
45
30
15
0
0
-15
100k
AOL ( 1 V)
AOL (Typ.)
AOL (+1 V)
75
Open-Loop Gain (dB)
Open-Loop Gain (dB)
75
1M
10M
100M
Frequency (Hz)
1G
10G
-15
100k
D604
Figure 50. Open-Loop Gain vs Temperature
1M
10M
100M
Frequency (Hz)
1G
10G
D605
Figure 51. Open-Loop Gain vs Process Variation
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Feature Description (continued)
9.3.4 Slew Rate and Output Stage
In addition to wide bandwidth, the OPA855 features a high slew rate of 2750 V/µs. The slew rate is a critical
parameter in high-speed pulse applications with narrow sub-10-ns pulses, such as optical time-domain
reflectometry (OTDR) and LIDAR. The high slew rate of the OPA855 implies that the device accurately
reproduces a 2-V, sub-ns pulse edge, as seen in Figure 20. The wide bandwidth and slew rate of the OPA855
make it an excellent amplifier for high-speed signal-chain front ends.
Figure 52 shows the open-loop output impedance of the OPA855 as a function of frequency. To achieve high
slew rates and low output impedance across frequency, the output swing of the OPA855 is limited to
approximately 3 V. The OPA855 is typically used in conjunction with high-speed pipeline ADCs and flash ADCs
that have limited input ranges. Therefore, the OPA855 output swing range coupled with the class-leading voltage
noise specification maximizes the overall dynamic range of the signal chain.
Open-Loop Output Impedance (ohms)
20
18
16
14
12
10
8
6
4
2
0
10k
100k
1M
10M
100M
Frequency (Hz)
1G
10G
D601
Figure 52. Open-Loop Output Impedance (ZOL) vs Frequency
18
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9.4 Device Functional Modes
9.4.1 Split-Supply and Single-Supply Operation
The OPA855 can be configured with single-sided supplies or split-supplies as shown in Figure 58. Split-supply
operation using balanced supplies with the input common-mode set to ground eases lab testing because most
signal generators, network analyzers, spectrum analyzers, and other lab equipment typically reference inputs and
outputs to ground. Split-supply operation is preferred in systems where the signals swing around ground.
However, the system requires two supply rails. In split-supply operation, the thermal pad must be connected to
the negative supply.
Newer systems use a single power supply to improve efficiency and reduce the cost of the extra power supply.
The OPA855 can be used with a single positive supply (negative supply at ground) with no change in
performance if the input common-mode and output swing are biased within the linear operation of the device. In
single-supply operation, level shift the dc input and output reference voltages by half the difference between the
power supply rails. This configuration maintains the input common-mode and output load reference at midsupply.
To eliminate gain errors, the source driving the reference input common-mode voltage must have low output
impedance across the frequency range of interest . In this case, the thermal pad must be connected to ground.
9.4.2 Power-Down Mode
The OPA855 features a power-down mode to reduce the quiescent current to conserve power. Figure 23 and
Figure 24 show the transient response of the OPA855 as the PD pin toggles between the disabled and enabled
states.
The PD disable and enable threshold voltages are with reference to the negative supply. If the amplifier is
configured with the positive supply at 3.3 V and the negative supply at ground, then the disable and enable
threshold voltages are 0.65 V and 1.8 V, respectively. If the amplifier is configured with ±1.65-V supplies, then
the disable and enable threshold voltages are at –1 V and 0.15 V, respectively. If the amplifier is configured with
±2.5-V supplies, then the threshold voltages are at –1.85 V and –0.7 V.
20
20
17.5
17.5
Quiescent Current (mA)
Quiescent Current (mA)
Figure 53 shows the switching behavior of a typical amplifier as the PD pin is swept down from the enabled state
to the disabled state. Similarly, Figure 54 shows the switching behavior of a typical amplifier as the PD pin is
swept up from the disabled state to the enabled state. The small difference in the switching thresholds between
the down sweep and the up sweep is caused by the hysteresis designed into the amplifier to increase immunity
to noise on the PD pin.
15
12.5
10
7.5
5
TA = 40qC
TA = +25qC
TA = +125qC
2.5
0
-2
-1.5
-1
-0.5
0
0.5
Power Down Voltage (V)
1
1.5
15
12.5
10
7.5
5
TA = 40qC
TA = +25qC
TA = +125qC
2.5
2
0
-2
D600
Figure 53. Switching Threshold (PD Pin Swept from High
to Low)
-1.5
-1
-0.5
0
0.5
Power Down Voltage (V)
1
1.5
2
D601
Figure 54. Switching Threshold (PD Pin Swept from Low to
High)
Connecting the PD pin low disables the amplifier and places the output in a high-impedance state. When the
amplifier is configured as a noninverting amplifier, the feedback (RF) and gain (RG) resistor network form a
parallel load to the output of the amplifier. To protect the input stage of the amplifier, the OPA855 uses internal,
back-to-back protection diodes between the inverting and noninverting input pins as Figure 48 shows. In the
power-down state, if the differential voltage between the input pins of the amplifier exceeds a diode voltage drop,
an additional low-impedance path is created between the noninverting input pin and the output pin.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The OPA855 offers very high-bandwidth, high slew-rate, low noise, and better than –60 dBc of distortion
performance at frequencies of up to 100 MHz. These features make this device an excellent low-noise amplifier
in high-speed data acquisition systems.
20
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10.2 Typical Application
Figure 55 shows the OPA855 configured as a transimpedance amplifier (U1) in a wide-bandwidth, optical frontend system. A second amplifier, the OPA859, configured as a unity-gain buffer (U2) sets a dc offset voltage to
the THS4520. The THS4520 is used to convert the single-ended transimpedance output of the OPA855 into a
differential output signal. The THS4520 drives the input of the ADS54J64, 14-bit, 1-GSPS analog-to-digital
converter (ADC) that digitizes the analog signal.
CF
VBIAS
RF
5V
3.8 V
±
U1
+
499
OPA855
VOCM = 1.3 V
5V
3.25 V
±
U2
+
OPA859
499
499
5V
+ ±
± +
Low-pass
filter
ADS54J64
499
Figure 55. OPA855 as a TIA in an Optical Front-End System
10.2.1 Design Requirements
The objective is to design a low noise, wideband optical front-end system using the OPA855 as a
transimpedance amplifier. The design requirements are:
• Amplifier supply voltage: 5 V
• TIA common-mode voltage: 3.8 V
• THS4520 gain: 1 V/V
• ADC input common-mode voltage: 1.3 V
• ADC analog differential input range: 1.1 VPP
10.2.2 Detailed Design Procedure
The closed-loop bandwidth of a transimpedance amplifier is a function of the following:
1. The total input capacitance (CIN). This total includes the photodiode capacitance, the input capacitance of the
amplifier (common-mode and differential capacitance) and any stray capacitance from the PCB.
2. The op amp gain bandwidth product (GBWP).
3. The transimpedance gain (RF).
Figure 55 shows the OPA855 configured as a TIA, with the avalanche photodiode (APD) reverse biased so that
the APD cathode is tied to a large positive bias voltage. In this configuration, the APD sources current into the op
amp feedback loop so that the output swings in a negative direction relative to the input common-mode voltage.
To maximize the output swing in the negative direction, the OPA855 common-mode voltage is set close to the
positive limit; only 1.2 V from the positive supply rail. The feedback resistance (RF) and the input capacitance
(CIN) form a zero in the noise gain that results in instability if left unchecked. To counteract the effect of the zero,
a pole is inserted into the noise gain transfer function by adding the feedback capacitor (CF).
The Transimpedance Considerations for High-Speed Amplifiers Application Report discusses theories and
equations that show how to compensate a transimpedance amplifier for a particular transimpedance gain and
input capacitance. The bandwidth and compensation equations from the application report are available in an
Excel™ calculator. What You Need To Know About Transimpedance Amplifiers – Part 1 provides a link to the
calculator.
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Typical Application (continued)
The equations and calculators in the referenced application report and blog posts are used to model the
bandwidth (f–3dB) and noise (IRN) performance of the OPA855 configured as a TIA. The resultant performance is
shown in Figure 56 and Figure 57. The left-side Y-axis shows the closed-loop bandwidth performance, whereas
the right side of the graph shows the integrated input-referred noise. The noise bandwidth to calculate IRN for a
fixed RF and CPD is set equal to the f–3dB frequency. Figure 56 shows the amplifier performance as a function of
photodiode capacitance (CPD) for RF = 6 kΩ and 12 kΩ. Increasing CPD decreases the closed-loop bandwidth. To
maximize bandwidth, make sure to reduce any stray parasitic capacitance from the PCB. The OPA855 is
designed with 0.8 pF of total input capacitance to minimize the effect of stray capacitance on system
performance. Figure 57 shows the amplifier performance as a function of RF for CPD = 1.5 pF and 2.5 pF.
Increasing RF results in lower bandwidth. To maximize the signal-to-noise ratio (SNR) in an optical front-end
system, maximize the gain in the TIA stage. Increasing RF by a factor of X increases the signal level by X, but
only increases the resistor noise contribution by √X, thereby improving SNR. Since the OPA855 is a bipolar input
amplifier, increasing the feedback resistance increases the voltage offset due to the bias current and also
increases the total output noise due to increased noise contributions from the amplifiers current noise.
The OPA859 configured as a unity-gain buffer drives a dc offset voltage of 3.25 V into the lower half of the
THS4520. To maximize the dynamic range of the ADC, the OPA855 and OPA859 drive a differential commonmode of 3.8 V and 3.25 V respectively into the THS4520. The dc offset voltage of the buffer amplifier can be
derived using Equation 1.
VBUF _ DC
VTIA _ CM
§
¨
¨ 1 u VADC _ DIFF _ IN
¨2
§ RF ·
¨
¨
¸
¨
© RG ¹
©
·
¸
¸
¸
¸
¸
¹
where
•
•
•
VTIA_CM is the common-mode voltage of the TIA (3.8 V)
VADC_DIFF_IN is the differential input voltage range of the ADC (1.1 VPP)
RF and RG are the feedback resistance (499 Ω) and gain resistance (499 Ω) of the THS4520 differential
amplifier
(1)
The low-pass filter between the THS4520 and the ADC54J64 minimizes high-frequency noise and maximizes
SNR. The ADC54J64 has an internal buffer that isolates the output of the THS4520 from the ADC samplingcapacitor input, so a traditional charge bucket filter is not required.
300
100
250
80
200
60
150
40
100
20
400
50
0
2
4
6
8
10
12
14
Photodiode capacitance (pF)
16
18
0
20
120
f-3dB, CF = 1.5 pF
f-3dB, CF = 2.5 pF
IRN, CF = 1.5 pF 100
IRN, RF = 2.5 pF
300
250
80
200
60
150
40
100
4
6
D609
Figure 56. Bandwidth and Noise vs Photodiode
Capacitance
22
350
8
10
12
14
16
Feedback Resistance (k:)
18
20
20
Integrated Input Referred Noise, IRN (nARMS)
350
160
f-3dB, RF = 6 k:
f-3dB, RF = 12 k: 140
IRN, RF = 6 k:
IRN, RF = 12 k: 120
Closed-loop Bandwidth, f-3dB (MHz)
Closed-loop Bandwidth, f-3dB (MHz)
450
Integrated Input Referred Noise, IRN (nARMS)
10.2.3 Application Curves
D610
Figure 57. Bandwidth and Noise vs Feedback Resistance
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11 Power Supply Recommendations
The OPA855 operates on supplies from 3.3 V to 5.25 V. The OPA855 operates on single-sided supplies, split
and balanced bipolar supplies, and unbalanced bipolar supplies. Because the OPA855 does not feature rail-torail inputs or outputs, the input common-mode and output swing ranges are limited at 3.3-V supplies.
a) Single supply configuration
VS+
VS+
2
+
0.1 …F
RG
75
6.8 …F
RF
453
±
50-Ÿ 6RXUFH
+
VI
200
RT
49.9
VS+
2
VS+
2
b) Split supply configuration
VS+
+
0.1 …F
RG
75
6.8 …F
RF
453
±
50-Ÿ 6RXUFH
+
VI
200
+
RT
49.9
0.1 …F
6.8 …F
VS±
Figure 58. Split and Single Supply Circuit Configuration
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12 Layout
12.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier like the OPA855 requires careful attention to
board layout parasitics and external component types. Recommendations that optimize performance include:
• Minimize parasitic capacitance from the signal I/O pins to ac ground. Parasitic capacitance on the output
and inverting input pins can cause instability. To reduce unwanted capacitance, cut out the power and ground
traces under the signal input and output pins. Otherwise, ground and power planes must be unbroken
elsewhere on the board. When configuring the amplifier as a TIA, if the required feedback capacitor is less
than 0.15 pF, consider using two series resistors, each of half the value of a single resistor in the feedback
loop to minimize the parasitic capacitance from the resistor.
• Minimize the distance (less than 0.25") from the power-supply pins to high-frequency bypass
capacitors. Use high-quality, 100-pF to 0.1-µF, C0G and NPO-type decoupling capacitors with voltage
ratings at least three times greater than the amplifiers maximum power supplies. This configuration makes
sure that there is a low-impedance path to the amplifiers power-supply pins across the amplifiers gain
bandwidth specification. At the device pins, do not allow the ground and power plane layout to be in close
proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the
pins and the decoupling capacitors. The power-supply connections must always be decoupled with these
capacitors. Larger (2.2-µF to 6.8-µF) decoupling capacitors that are effective at lower frequency must be used
on the supply pins. Place these decoupling capacitors further from the device. Share the decoupling
capacitors among several devices in the same area of the printed circuit board (PCB).
• Careful selection and placement of external components preserves the high-frequency performance
of the OPA855. Use low-reactance resistors. Surface-mount resistors work best and allow a tighter overall
layout. Never use wirewound resistors in a high-frequency application. Because the output pin and inverting
input pin are the most sensitive to parasitic capacitance, always position the feedback and series output
resistor, if any, as close to the output pin as possible. Place other network components (such as noninverting
input termination resistors) close to the package. Even with a low parasitic capacitance shunting the external
resistors, high resistor values create significant time constants that can degrade performance. When
configuring the OPA855 as a voltage amplifier, keep resistor values as low as possible and consistent with
load driving considerations. Decreasing the resistor values keeps the resistor noise terms low and minimizes
the effect of the parasitic capacitance. However, lower resistor values increase the dynamic power
consumption because RF and RG become part of the output load network of the amplifier.
12.2 Layout Example
Representative schematic
Connect PD to VS+ to enable the
amplifier
VS+
1
CBYP
RS
+
±
CBYP
VSRG
RF
NC (Pin 2) isolates the IN- and FB
pins thereby reducing capacitive
coupling
2
7
Thermal
Pad
RF
Place gain and feedback resistors
close to pins to minimize stray
capacitance
8
3
CBYP
6
RS
RG
4
5
CBYP
Ground and power plane exist on
inner layers.
Connect the thermal pad to the
negative supply pin
Ground and power plane removed
from inner layers. Ground fill on
outer layers also removed
Place bypass capacitor
close to power pins
Figure 59. Layout Recommendation
24
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Layout Example (continued)
When configuring the OPA855 as a transimpedance amplifier additional care must be taken to minimize the
inductance between the avalanche photodiode (APD) and the amplifier. Always place the photodiode on the
same side of the PCB as the amplifier. Placing the amplifier and the APD on opposite sides of the PCB
increases the parasitic effects due to via inductance. APD packaging can be quite large which often requires the
APD to be placed further away from the amplifier than ideal. The added distance between the two device results
in increased inductance between the APD and op amp feedback network as shown in Figure 60. The added
inductance is detrimental to a decompensated amplifiers stability since it isolates the APD capacitance from the
noise gain transfer function. The noise gain is given by Equation 2. The added PCB trace inductance between
the feedback network increases the denominator in Equation 2 thereby reducing the noise gain and the phase
margin. In cases where a leaded APD in a TO can is used inductance should be further minimized by cutting the
leads of the TO can as short as possible.
The layout shown in Figure 60 can be improved by following some of the guidelines shown in Figure 61. The two
key rules to follow are:
• Add an isolation resistor RISO as close as possible to the inverting input of the amplifier. Select the value of
RISO to be between 10 Ω and 20 Ω. The resistor dampens the potential resonance caused by the trace
inductance and the amplifiers internal capacitance.
• Close the loop between the feedback elements (RF and CF) and RISO as close to the APD pins as possible.
This ensures a more balanced layout and reduces the inductive isolation between the APD and the feedback
network.
Noise Gain
§
ZF ·
¨1
¸
ZIN ¹
©
where
•
•
ZF is the total impedance of the feedback network.
ZIN is the total impedance of the input network.
(2)
Vbias
APD
Package
RF
CF
FB 1
8
NC 2
7 VS+
IN± 3
Trace inductance isolates
APD capacitance from the
amplifier noise gain
Thermal
Pad
IN+ 4
PD
6 OUT
5 VS±
Figure 60. Non-Ideal TIA Layout
Vbias
CF
APD
Package
RF
Close the loop close
to APD pins
FB 1
8
NC 2
7 VS+
IN± 3
RISO
Place RISO close to IN±
Thermal
Pad
IN+ 4
PD
6 OUT
5 VS±
Figure 61. Improved TIA Layout
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Development Support
• Wide Bandwidth Optical Front-end Reference Design
• LIDAR-Pulsed Time-of-Flight Reference Design Using High-Speed Data Converters
• LIDAR Pulsed Time of Flight Reference Design
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• OPA855EVM User's Guide
• Transimpedance Considerations for High-Speed Amplifiers Application Report
• What You Need To Know About Transimpedance Amplifiers – Part 1
• What You Need To Know About Transimpedance Amplifiers – Part 2
• Training Video: How to Design Transimpedance Amplifier Circuits
• Training Video: High-Speed Transimpedance Amplifier Design Flow
• Training Video: How to Convert a TINA-TI Model into a Generic SPICE Model
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
Excel is a trademark of Microsoft Corporation.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
26
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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27
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA855IDSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
855
OPA855IDSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
855
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Nov-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
OPA855IDSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
OPA855IDSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Nov-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA855IDSGR
WSON
DSG
8
3000
210.0
185.0
35.0
OPA855IDSGT
WSON
DSG
8
250
210.0
185.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DSG 8
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2 x 2, 0.5 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.32
0.18
0.4
0.2
OPTIONAL TERMINAL
TYPICAL
C
0.8 MAX
SEATING PLANE
0.05
0.00
0.08 C
EXPOSED
THERMAL PAD
(0.2) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
SEE OPTIONAL
TERMINAL
9
8
1
PIN 1 ID
1.6 0.1
8X
0.4
8X
0.2
0.32
0.18
0.1
0.05
C A B
C
4218900/C 04/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
8X (0.5)
( 0.2) VIA
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(R0.05) TYP
(1.9)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218900/C 04/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
SYMM
METAL
1
8
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/C 04/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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