Texas Instruments | LMH6572 Triple 2:1 High Speed Video Multiplexer (Rev. G) | Datasheet | Texas Instruments LMH6572 Triple 2:1 High Speed Video Multiplexer (Rev. G) Datasheet

Texas Instruments LMH6572 Triple 2:1 High Speed Video Multiplexer (Rev. G) Datasheet
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LMH6572
SNCS102G – JUNE 2005 – REVISED AUGUST 2018
LMH6572 Triple 2:1 High Speed Video Multiplexer
1 Features
•
•
•
•
•
•
•
•
1
•
•
350-MHz, 250-mV, −3-dB Bandwidth
290-MHz, 2-VPP, −3-dB Bandwidth
10-ns Channel Switching Time
90-dB Channel to Channel Isolation at 5 MHz
0.02%, 0.02° Diff. Gain, Phase
0.1-dB Gain Flatness to 140 MHz
1400-V/μs Slew Rate
Wide Supply Voltage Range:
6 V (±3 V) to 12 V (±6 V)
−78-dB HD2 at 10 MHz
−75-dB HD3 at 10 MHz
2 Applications
•
•
•
RGB Video Router
Multi Input Video Monitor
Fault Tolerant Data Switch
3 Description
The LMH6572 is a high performance analog
multiplexer optimized for professional grade video
and other high fidelity, high bandwidth analog
applications. The LMH6572 provides a 290-MHz
bandwidth at 2-VPP output signal levels. The 140 MHz
of 0.1-dB bandwidth and a 1500-V/µs slew rate make
this part suitable for high definition television (HDTV)
and high resolution multimedia video applications.
The LMH6572 supports composite video applications
with its 0.02% and 0.02° differential gain and phase
errors for NTSC and PAL video signals while driving
a single, back terminated 75-Ω load. The LM6572
can deliver 80-mA linear output current for driving
multiple video load applications.
The LMH6572 has an internal gain of 2 V/V (+6 dBv)
for driving back terminated transmission lines at a net
gain of 1 V/V (0 dBv).
The LMH6572 is available in the SSOP package.
Device Information(1)
PART NUMBER
LMH6572
PACKAGE
SSOP (16)
BODY SIZE (NOM)
4.90 mm × 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH6572
SNCS102G – JUNE 2005 – REVISED AUGUST 2018
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
±5V Electrical Characteristics ...................................
±3.3V Electrical Characteristics ................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Feature Description................................................. 11
8
Power Supply Recommendations...................... 15
8.1 Power Dissipation ................................................... 15
8.2 ESD Protection........................................................ 15
9
Layout ................................................................... 16
9.1 Layout Guidelines ................................................... 16
10 Device and Documentation Support ................. 17
10.1
10.2
10.3
10.4
10.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
11 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (May 2013) to Revision G
Page
•
Deleted preview watermark .................................................................................................................................................... 1
•
Added Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature Description
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Deleted bolding from Electrical Characteristics specifications, added temperature range to test conditions for clarification 5
•
Changed Overview title from General Information .............................................................................................................. 11
•
Changed Layout Considerations title to Layout Guidelines.................................................................................................. 16
Changes from Revision E (April 2013) to Revision F
•
2
Page
Changed layout of National Semiconductor Data Sheet to TI format .................................................................................. 16
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5 Pin Configuration and Functions
DBQ Package
16-Pin SSOP
Top View
Truth Table
SEL
EN
OUT
0
0
CH 1
1
0
CH 0
X
1
Disable
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6 Specifications
6.1 Absolute Maximum Ratings
see
(1) (2)
MIN
Supply Voltage (V+ − V−)
(3)
IOUT
MAX
UNIT
13.2
V
130
mA
Input Voltage Range
±(VS)
V
Maximum Junction Temperature (4)
+150
°C
+150
°C
Storage temperature, Tstg
(1)
(2)
(3)
(4)
–65
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
The maximum output current (IOUT) is determined by the device power dissipation limitations. See the Power Dissipation section for
more details. A short circuit condition should be limited to 5 seconds or less.
Human Body Model, 1.5 kΩ in series with 100 pF. Machine Model 0 Ω in series with 200 pF.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Machine model (MM)
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
see
(1)
MIN
Operating Temperature
Supply Voltage Range
(1)
NOM
MAX
UNIT
–40
85
°C
6
12
V
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
6.4 Thermal Information
LMH6572
THERMAL METRIC
(1)
DBQ (SSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
125
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
36
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 ±5V Electrical Characteristics
VS = ±5 V and RL = 100 Ω, (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
MAX
UNIT
FREQUENCY DOMAIN PERFORMANCE
SSBW
–3 dB Bandwidth
VOUT = 0.25 VPP
LSBW
–3 dB Bandwidth (2)
VOUT = 2 VPP
.1 dBBW
0.1 dB Bandwidth
VOUT = 0.25 VPP
DG
Differential Gain
RL = 150 Ω, f = 4.43 MHz
0.02%
DP
Differential Phase
RL = 150 Ω, f = 4.43 MHz
0.02
250
350
MHz
290
MHz
140
MHz
deg
TIME DOMAIN RESPONSE
TRS
Channel to Channel Switching Time
Logic Transition to 90% Output
10
ns
Enable and Disable Times
Logic Transition to 90% or 10% Output
11
ns
TRL
Rise and Fall Time
2-V Step
1.5
ns
TSS
Settling Time to 0.05%
2-V Step
17
ns
OS
Overshoot
4-V Step
5%
SR
Slew Rate (2)
4-V Step
1200
1400
V/µs
DISTORTION
HD2
2nd Harmonic Distortion
2 VPP , 10 MHz
−78
dBc
HD3
3rd Harmonic Distortion
2 VPP , 10 MHz
−75
dBc
IMD
3rd Order Intermodulation Products
10 MHz, Two tones 2 VPP at Output
−80
dBc
EQUIVALENT INPUT NOISE
VN
Voltage
>1 MHz, Input Referred
5
nV√Hz
ICN
Current
>1 MHz, Input Referred
5
pA/√Hz
STATIC, DC PERFORMANCE
GAIN
Voltage Gain
Gain Error (3)
Gain Error
VIO
Output Offset Voltage (3)
DVIO
Average Drift
IBN
Input Bias Current (3) (4)
DIBN
Power Supply Rejection Ratio (3)
ICC
Supply Current (3)
Supply Current Disabled (3)
(1)
(2)
(3)
(4)
Logic High Threshold (3)
V/V
±0.3%
±0.5%
No load, with respect to nominal gain of
2.00 V/V, TA = –40°C to +85°C
±0.3%
±0.7%
RL = 50 Ω, with respect to nominal gain
of 2.00 V/V
0.3%
VIN = 0 V
1
±14
VIN = 0 V, TA = –40°C to +85°C
1
±17.5
27
−1.4
±5.0
VIN = 0 V, TA = –40°C to +85°C
−1.4
±5.6
7
µA
nA/°C
DC, Input referred
50
54
DC, Input referred, TA = –40°C to +85°C
48
54
No load
20
23
25
No load, TA = –40°C to +85°C
20
23
28.5
No load
2.0
2.2
No load, TA = –40°C to +85°C
2.0
2.3
Select and Enable Pins
mV
µV/°C
VIN = 0 V
Average Drift
PSRR
VIH
2.0
No load, with respect to nominal gain of
2.00 V/V
dB
2.0
mA
mA
V
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ > TA. See the Power Dissipation section for information on temperature de-rating of this
device. Minimum and maximum ratings are based on product testing, characterization and simulation. Individual parameters are tested
as noted.
Parameters ensured by design.
Parameters ensured by electrical testing at 25° C.
Positive Value is current into device.
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±5V Electrical Characteristics (continued)
VS = ±5 V and RL = 100 Ω, (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
VIL
Logic Low Threshold
(3)
IiL
Logic Pin Input Current Low (4)
IiH
Logic Pin Input Current High (4)
MIN
TYP
MAX
Logic Input = 0 V
−1
±5.0
Logic Input = 0 V, TA = –40°C to +85°C
−1
±15
Select and Enable Pins
0.8
Logic Input = 2.0 V
112
150
200
Logic Input = 2.0 V, TA = –40°C to
+85°C
100
150
210
UNIT
V
µA
µA
MISCELLANEOUS PERFORMANCE
650
800
940
TA = –40°C to +85°C
620
800
1010
Internal Feedback and Gain Set
Resistors in Series to Ground
1.3
1.6
1.88
RF
Internal Feedback and Gain Set
Resistor Values
RODIS
Disabled Output Resistance
RIN+
Input Resistance
100
kΩ
CIN
Input Capacitance
0.9
pF
ROUT
Output Resistance
0.26
Ω
VO
Output Voltage Range
VOL
CMIR
No Load
±3.83
±3.9
No Load, TA = –40°C to +85°C
±3.80
±3.9
RL = 100 Ω
±3.52
±3.53
RL = 100 Ω, TA = –40°C to +85°C
±3.5
±3.53
±2
±2.5
VIN = 0 V
+70
±80
40
±80
Input Voltage Range
Ω
kΩ
V
V
V
IO
Linear Output Current (3) (4)
ISC
Short Circuit Current (5)
VIN = ±2 V, Output Shorted to Ground
±230
mA
XTLK
Channel to Channel Crosstalk
VIN = 2 VPP at 5 MHz
-90
dBc
XTLK
Channel to Channel Crosstalk
VIN = 2 VPP at 100 MHz
-54
dBc
XTLK
All Hostile Crosstalk
In A, C, Out B, VIN = 2 VPP at 5 MHz
-95
dBc
(5)
6
VIN = 0 V, TA = –40°C to +85°C
mA
The maximum output current (IOUT) is determined by the device power dissipation limitations. See the Power Dissipation section for
more details. A short circuit condition should be limited to 5 seconds or less.
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6.6 ±3.3V Electrical Characteristics
VS = ±3.3 V, RL = 100 Ω (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
MAX
UNIT
FREQUENCY DOMAIN PERFORMANCE
SSBW
−3 dB Bandwidth
VOUT = 0.25 VPP
360
MHz
LSBW
−3 dB Bandwidth
VOUT = 2.0 VPP
270
MHz
0.1 dBBW
0.1 dB Bandwidth
VOUT = 0.5 VPP
80
MHz
GFP
Peaking
DC to 200 MHz
0.3
dB
DG
Differential Gain
RL = 150 Ω, f = 4.43 MHz
0.02%
DP
Differential Phase
RL = 150 Ω, f = 4.43 MHz
0.03
deg
TIME DOMAIN RESPONSE
TRL
Rise and Fall Time
2-V Step
2.0
ns
TSS
Settling Time to 0.05%
2-V Step
15
ns
OS
Overshoot
2-V Step
5%
SR
Slew Rate
2-V Step
1000
V/µs
2 VPP, 10 MHz
−70
dBc
DISTORTION
HD2
2nd Harmonic Distortion
rd
HD3
3 Harmonic Distortion
2 VPP, 10 MHz
−74
dBc
IMD
3rd Order Intermodulation Products
10 MHz, Two tones 2 VPP at Output
-79
dBc
2.0
V/V
STATIC, DC PERFORMANCE
GAIN
Voltage Gain
VIO
Output Offset Voltage
DVIO
Average Drift
Input Bias Current (2)
IBN
DIBN
VIN = 0 V
VIN = 0 V
Average Drift
1
mV
36
µV/°C
2
µA
24
nA/°C
PSRR
Power Supply Rejection Ratio
DC, Input Referred
54
dB
ICC
Supply Current
RL = ∞
20
mA
VIH
Logic High Threshold
Select and Enable Pins
VIL
Logic Low Threshold
Select and Enable Pins
1.3
0.4
V
V
MISCELLANEOUS PERFORMANCE
RIN+
Input Resistance
100
kΩ
CIN
Input Capacitance
0.9
pF
ROUT
Output Resistance
0.27
Ω
No Load
±2.5
V
RL = 100 Ω
±2.2
V
VO
VOL
Output Voltage Range
CMIR
Input Voltage Range
IO
Linear Output Current
VIN = 0V
ISC
Short Circuit Current
VIN = ±1V, Output Shorted to Ground
XTLK
Channel to Channel Crosstalk
5 MHz
(1)
(2)
±1.2
V
±60
mA
±150
mA
-90
dBc
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ > TA. See the Power Dissipation section for information on temperature de-rating of this
device. Minimum and maximum ratings are based on product testing, characterization and simulation. Individual parameters are tested
as noted.
Positive Value is current into device.
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6.7 Typical Characteristics
VS = ±5 V and RL = 100 Ω (unless otherwise noted)
Figure 1. Frequency Response vs VOUT
Figure 2. Frequency Response vs VOUT
Load = 1 kΩ || CL
8
Figure 3. Frequency Response vs Capacitive Load
Figure 4. Suggested RS vs Capacitive Load
Figure 5. Harmonic Distortion vs Output Voltage
Figure 6. Harmonic Distortion vs Output Voltage
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Typical Characteristics (continued)
VS = ±5 V and RL = 100 Ω (unless otherwise noted)
Figure 7. Harmonic Distortion vs Frequency
Figure 8. Harmonic Distortion vs Frequency
Figure 9. Harmonic Distortion vs Supply Voltage
Figure 10. Channel Switching Time
Figure 11. Disable Time
Figure 12. Pulse Response
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Typical Characteristics (continued)
VS = ±5 V and RL = 100 Ω (unless otherwise noted)
Figure 13. Crosstalk
Figure 14. PSRR
Figure 15. PSRR
Figure 16. Closed-Loop Output Impedance
Figure 17. Closed-Loop Output Impedance
10
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7 Detailed Description
7.1 Overview
The LMH6572 is a high-speed triple 2:1 analog multiplexer, optimized for very high speed and low distortion.
With a fixed gain of 2 and excellent AC performance, the LMH6572 is ideally suited for switching high resolution,
presentation grade video signals. The LMH6572 has no internal ground reference. Single or split supply
configurations are both possible. The LMH6572 features very high speed channel switching and disable times.
When disabled the LMH6572 output is high impedance, making multiplexer expansion possible by combining
multiple devices.
7.2 Feature Description
7.2.1 Single Supply Operation
The LMH6572 uses mid-supply referenced circuits for the select and disable pins. In order to use the LMH6572
in single supply configuration, it is necessary to use a circuit similar to Figure 19. In this configuration the logical
inputs are compatible with high breakdown open collector TTL, or open drain CMOS logic. In addition, the default
logic state is reversed since there is a pull-up resistor on those pins. Single supply operation also requires the
input to be biased to within the common mode input range of roughly ±2V from the mid-supply point.
7.2.2 Video Performance
The LMH6572 has been designed to provide excellent performance with production quality video signals in a
wide variety of formats such as HDTV and High Resolution VGA. Best performance will be obtained with backterminated loads. The back termination reduces reflections from the transmission line and effectively masks
transmission line and other parasitic capacitances from the amplifier output stage. Figure 18 shows a typical
configuration for driving a 75-Ω cable. The output buffer is configured for a gain of 2, so using back terminated
loads will give a net gain of 1.
Figure 18. Typical Application
Figure 19. Single Supply Application
7.2.3 Gain Accuracy
The gain accuracy of the LMH6572 is accurate to ±0.5% (0.3% typical) and stable over temperature. The internal
gain setting resistors, RF and RG, match very well; however, over process and temperature their absolute value
will change.
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Feature Description (continued)
7.2.4 Expanding the Multiplexer
It is possible to build higher density multiplexers by paralleling several LMH6572s. Figure 20 shows a 4:1 RGB
MUX using two LMH6572s:
Figure 20. RGB MUX Using Two LMH6572's
If it is important in the end application to make sure that no two inputs are presented to the output at the same
time, an optional delay block can be added prior to the ENABLE(EN) pin of each device, as shown. Figure 21
shows one possible approach to this delay circuit. The delay circuit shown will delay ENABLE’s H to L transitions
(R1 and C1 decay) but will not delay its L to H transition.
Figure 21. Delay Circuit Implementation
R2 should be kept small compared to R1 in order to not reduce the ENABLE voltage and to produce little or no
delay to the ENABLE L to H transition.
With the ENABLE pin putting the output stage into a high impedance state, several LMH6572’s can be tied
together to form a larger input MUX. However, there is a slight loading effect on the active output caused by the
off-channel feedback and gain set resistors, as shown in Figure 21. Figure 22 is assuming there are four
LMH6572 devices tied together to form a triple 8:1 MUX. With the internal resistors valued at approximately
800Ω, the gain error is about -0.57 dB, or about −6%.
12
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Feature Description (continued)
Figure 22. Multiplexer Input Expansion by Combining Outputs
An alternate approach would be to tie the outputs directly together and let all devices share a common back
termination resistor in order to alleviate the gain error issue above.
The drawback in this case is the increased capacitive load presented to the output of each LMH6572 due to the
offstate capacitance of the LMH6572.
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Feature Description (continued)
7.2.5 Other Applications
The LMH6572 may be utilized in systems that involve a single RGB channel as well whenever there is a need to
switch between different “flavors” of a single RGB input.
Here are some examples:
1. RGB positive polarity, negative polarity switch
2. RGB full resolution, high-pass filter switch
In each of these applications, the same RGB input occupies one set of inputs to the LMH6572 and the other
“flavor” would be tied to the other input set.
7.2.5.1 Driving Capacitive Loads
Capacitive output loading applications will benefit from the use of a series output resistor. Figure 23 shows the
use of a series output resistor, ROUT, to stabilize the amplifier output under capacitive loading. Capacitive loads of
5 to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation. Figure 24
gives a recommended value for selecting a series output resistor for mitigating capacitive loads. The values
suggested in the charts are selected for .5 dB or less of peaking in the frequency response. This gives a good
compromise between settling time and bandwidth. For applications where maximum frequency response is
needed and some peaking is tolerable, the value of ROUT can be reduced slightly from the recommended values.
Figure 23. Decoupling Capacitive Loads
Figure 24. Recommended ROUT vs Capacitive Load
14
Figure 25. Frequency Response vs Capacitive Load
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8 Power Supply Recommendations
8.1 Power Dissipation
The LMH6572 is optimized for maximum speed and performance in the small form factor of the standard SSOP
package. To achieve its high level of performance, the LMH6572 consumes 23 mA of quiescent current, which
cannot be neglected when considering the total package power dissipation limit. To ensure maximum output
drive and highest performance, thermal shutdown is not provided. Therefore, it is of utmost importance to make
sure that the TJMAX is never exceeded due to the overall power dissipation.
Follow these steps to determine the Maximum power dissipation for the LMH6572:
1. Calculate the quiescent (no-load) power:
PAMP = ICC* (VS)
where
•
VS = V+ - V−
(1)
2. Calculate the RMS power dissipated in the output stage:
PD (rms) = rms [(VS - VOUT) * IOUT]
where
•
•
VOUT and IOUT are the voltage across and the current through the external load
VS is the total supply voltage
(2)
3. Calculate the total RMS power:
PT = PAMP + PD
(3)
The maximum power that the LMH6572 package can dissipate at a given temperature can be derived with the
following equation:
PMAX = (150°C – TAMB)/ θJA
where
•
•
•
TAMB = Ambient temperature (°C)
θJA = Thermal resistance, from junction to ambient, for a given package (°C/W)
For the SSOP package θJA is 125 °C/W
(4)
8.2 ESD Protection
The LMH6572 is protected against electrostatic discharge (ESD) on all pins. The LMH6572 will survive 2000V
Human Body model and 200V Machine model events. Under normal operation the ESD diodes have no effect on
circuit performance. There are occasions, however, when the ESD diodes will be evident. If the LMH6572 is
driven by a large signal while the device is powered down the ESD diodes will conduct. The current that flows
through the ESD diodes will either exit the chip through the supply pins or will flow through the device, hence it is
possible to power up a chip with a large signal applied to the input pins. Shorting the power pins to each other
will prevent the chip from being powered up through the input.
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9 Layout
9.1 Layout Guidelines
Whenever questions about layout arise, use the LMH730151 evaluation board as a guide. To reduce parasitic
capacitances, ground and power planes should be removed near the input and output pins. For long signal paths
controlled impedance lines should be used, along with impedance matching elements at both ends. Bypass
capacitors should be placed as close to the device as possible. Bypass capacitors from each rail to ground are
applied in pairs. The larger electrolytic bypass capacitors can be located farther from the device; however, the
smaller ceramic capacitors should be placed as close to the device as possible. In Figure 18 and Figure 19, the
capacitor between V+ and V− is optional, but is recommended for best second harmonic distortion. Another way
to enhance performance is to use pairs of 0.01 μF and 0.1 μF ceramic capacitors for each supply bypass.
9.1.1 Evaluation Boards
Texas Instruments provides the following evaluation boards as a guide for high frequency layout and as an aid in
device testing and characterization. Many of the datasheet plots were measured with these boards.
DEVICE
PACKAGE
EVALUATION BOARD PART NUMBER
LMH6572
SSOP
LMH730151
An evaluation board can be shipped when a device sample request is placed with Texas Instruments.
16
Submit Documentation Feedback
Copyright © 2005–2018, Texas Instruments Incorporated
Product Folder Links: LMH6572
LMH6572
www.ti.com
SNCS102G – JUNE 2005 – REVISED AUGUST 2018
10 Device and Documentation Support
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
10.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
10.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
10.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2005–2018, Texas Instruments Incorporated
Product Folder Links: LMH6572
17
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMH6572MQ/NOPB
ACTIVE
SSOP
DBQ
16
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LH65
72MQ
LMH6572MQX/NOPB
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LH65
72MQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Aug-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LMH6572MQX/NOPB
Package Package Pins
Type Drawing
SSOP
DBQ
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.5
B0
(mm)
K0
(mm)
P1
(mm)
5.4
2.0
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Aug-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMH6572MQX/NOPB
SSOP
DBQ
16
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
16
1
14X .0250
[0.635]
2X
.175
[4.45]
.189-.197
[4.81-5.00]
NOTE 3
8
9
B
.150-.157
[3.81-3.98]
NOTE 4
16X .008-.012
[0.21-0.30]
.007 [0.17]
C A
B
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[0.11-0.25]
0 -8
.016-.035
[0.41-0.88]
(.041 )
[1.04]
DETAIL A
TYPICAL
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
www.ti.com
EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
.002 MAX
[0.05]
ALL AROUND
METAL
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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