Texas Instruments | OPA145 High-Precision, Low-Noise, Rail-to-Rail Output, 5.5-MHz JFET Operational Amplifier (Rev. C) | Datasheet | Texas Instruments OPA145 High-Precision, Low-Noise, Rail-to-Rail Output, 5.5-MHz JFET Operational Amplifier (Rev. C) Datasheet

Texas Instruments OPA145 High-Precision, Low-Noise, Rail-to-Rail Output, 5.5-MHz JFET Operational Amplifier (Rev. C) Datasheet
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OPA145
SBOS427C – JUNE 2017 – REVISED JULY 2018
OPA145 High-Precision, Low-Noise, Rail-to-Rail Output, 5.5-MHz
JFET Operational Amplifier
1 Features
3 Description
•
The OPA145 operational amplifier (op amp) is a lowpower JFET input amplifier that has excellent drift,
low current noise, and pico-ampere input bias current,
making this device a suitable choice for amplifying
small signals from high-impedance sensors. The railto-rail output swing interfaces to modern, singlesupply, precision analog-to-digital converters (ADCs)
and digital-to-analog converters (DACs). In addition,
the input range that includes V– allows designers to
simplify power management and take advantage of
the single-supply, low-noise JFET architecture.
1
•
•
•
•
•
•
Best Bandwidth and Slew-Rate-to-Power Ratio:
– Gain-Bandwidth Product: 5.5 MHz
– Slew Rate: 20 V/μs
– Low Supply Current: 475 µA (Maximum)
High Precision:
– Very Low Offset: 150 μV (Maximum)
– Very Low Offset Drift: 1 μV/°C (Maximum)
Low Input Bias Current: 2 pA
Excellent Noise Performance:
– Very Low Voltage Noise: 7 nV/√Hz
– Very Low Current Noise: 0.8 fA/√Hz
Input-Voltage Range Includes V– Supply
Single-Supply Operation: 4.5 V to 36 V
Dual-Supply Operation: ±2.25 V to ±18 V
PART NUMBER
OPA145
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOT-23 (5)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
•
•
•
Device Information(1)
Analog I/O Modules
Battery-Powered Instruments
Industrial Controls
Medical Instrumentation
Photodiode Amplifiers
Active Filters
Data Acquisition Systems
Automatic Test Systems
OPA145 Excels in 16-bit, 100-kSPS Fully
Differential Transimpedance Imaging Application
OPA145 Precision JFET Technology Offers
Excellent Linear Input Impedance
3
C1
9 pF
+10V
+10V
R5
22
±
±
OPA145
OPA145
+
+
R3
180
GND
C3
432p
2.5 V to 5 V 2.7 V to 3.6 V
C5
200p
GND
REF
ò ‡ 9REF
AINP
GND
ADS8867
GND
GND
+
Fast Silicon
PIN Photodiode
OPA145
+
±
OPA145
+10V
±
+10V
5 A
3.8 pF
2.5 mW/cm2
Photovoltaic Mode
AVDD
C2
9 pF
C4
432p
R4
180
C6
200p
AINN
GND
R6
22
Normalized Input Bias Current (pA)
R1
50 k
1.5
0
-1.5
-3
±20
±15
±10
±5
0
5
10
Input Common-mode Voltage (V)
15
20
C001
Copyright © 2017, Texas Instruments Incorporated
R2
50 k
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA145
SBOS427C – JUNE 2017 – REVISED JULY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics: VS = 4.5 V to 36 V; ±2.25 V
to ±18 V...................................................................... 5
6.6 Typical Characteristics .............................................. 7
7
Detailed Description ............................................ 15
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
15
15
16
22
8
Application and Implementation ........................ 23
8.1 Application Information............................................ 23
8.2 Typical Application ................................................. 23
8.3 System Examples ................................................... 24
9 Power Supply Recommendations...................... 27
10 Layout................................................................... 28
10.1 Layout Guidelines ................................................. 28
10.2 Layout Example .................................................... 29
11 Device and Documentation Support ................. 30
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
31
31
31
31
12 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (May 2018) to Revision C
Page
•
Deleted "preview" from information re: DBV (SOT-23) package, now released ................................................................... 1
•
Changed status of data sheet to "Production Data" .............................................................................................................. 1
Changes from Revision A (March 2018) to Revision B
•
Deleted "preview" from information re: DGK (VSSOP) package, now released ................................................................... 1
Changes from Original (June 2017) to Revision A
•
2
Page
Page
Added preview of DBV and DGK packages; removed content regarding future device releases ........................................ 1
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SBOS427C – JUNE 2017 – REVISED JULY 2018
5 Pin Configuration and Functions
OPA145: D and DGK Packages
8-Pin SOIC, 8-Pin VSSOP
Top View
±IN
2
+IN
3
V±
4
8
NC
±
7
V+
+
6
OUT
5
NC
OUT
1
V±
2
+IN
3
Not to scale
5
V+
4
±IN
±
1
+
NC
OPA145: DBV Package
5-Pin SOT-23
Top View
Not to scale
Pin Functions: OPA145
PIN
OPA145
NAME
I/O
DESCRIPTION
D (SOIC),
DGK (VSSOP),
DBV (SOT-23)
–IN
2
4
I
Inverting input
+IN
3
3
I
Noninverting input
NC
1, 5, 8
—
—
No internal connection (can be left floating)
OUT
6
1
O
Output
V–
4
2
—
Negative (lowest) power supply
V+
7
5
—
Positive (highest) power supply
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SBOS427C – JUNE 2017 – REVISED JULY 2018
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage, (V+) – (V–)
40
Voltage
(V–) – 0.5
±10
Continuous
–55
150
150
Storage temperature, Tstg
(3)
mA
Continuous
Junction temperature, TJ
(2)
V
(V+) + 0.5
Current
(3)
Operating temperature, TA
(1)
UNIT
±20
Single supply
Signal input pins (2)
Output short-circuit
MAX
Dual supply
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
Short-circuit to VS / 2 (ground in symmetrical dual-supply setups), one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VS
Supply voltage, (V+) – (V–)
TA
Ambient temperature
Dual supply
Single supply
MIN
NOM
MAX
±2.25
±15
±18
4.5
30
36
–40
25
125
UNIT
V
°C
6.4 Thermal Information
OPA145
THERMAL METRIC
(1)
D (SOIC)
DGK (VSSOP)
DBV (SOT)
8 PINS
8 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
136
143
205
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
74
47
200
°C/W
RθJB
Junction-to-board thermal resistance
62
64
113
°C/W
ΨJT
Junction-to-top characterization parameter
19.7
5.3
38.2
°C/W
ΨJB
Junction-to-board characterization parameter
54.8
62.8
104.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS427C – JUNE 2017 – REVISED JULY 2018
6.5 Electrical Characteristics: VS = 4.5 V to 36 V; ±2.25 V to ±18 V
at TA = 25°C, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±40
±150
UNIT
OFFSET VOLTAGE
VS = ±18 V
VOS
dVOS/dT
PSRR
Offset voltage, RTI
Drift
Power-supply rejection ratio
VS = ±18 V, TA = 0°C to +85°C
±280
VS = ±18 V, TA = –40°C to +125°C
±350
VS = ±18 V, TA = 0°C to +85°C
D and DGK Packages
±0.4
±1
VS = ±18 V, TA = 0°C to +85°C
DBV Package
±0.4
±1.2
VS = ±18 V, TA = –40°C to +125°C
D and DGK Packages
±0.5
±1.4
VS = ±18 V, TA = –40°C to +125°C
DBV Package
±0.5
±1.5
VS = ±2.25 V to ±18 V
D Package Only
±0.06
±0.3
VS = ±2.25 V to ±18 V
DGK and DBV Packages
±0.06
±0.5
μV
μV/°C
VS = ±2.25 V to ±18 V,
TA = –40°C to +125°C
μV/V
±2
INPUT BIAS CURRENT
±2
IB
Input bias current
TA = 0°C to +85°C
TA = –40°C to +125°C
Input offset current
pA
±10
±2
IOS
±10
±600
TA = 0°C to +85°C
nA
±10
pA
±600
TA = –40°C to +125°C
±10
nA
NOISE
Input voltage noise
f = 0.1 Hz to 10 Hz
320
nVPP
f = 0.1 Hz to 10 Hz
60
nVRMS
f = 10 Hz
en
In
Input voltage noise density
Input current noise density
9
f = 100 Hz
7.2
f = 1 kHz
7
f = 1 kHz
0.8
nV/√Hz
fA/√Hz
INPUT VOLTAGE RANGE
VCM
CMRR
Common-mode voltage range
Common-mode rejection ratio
TA = –40°C to +125°C
(V–) –0.1
VS = ±18 V, VCM = (V–) –0.1 V to
(V+) – 3.5 V
126
VS = ±18 V, VCM = (V–) –0.1 V to
(V+) – 3.5 V,
TA = –40°C to +125°C
118
(V+)–3.5
V
140
dB
INPUT IMPEDANCE
1013 || 5
Differential
Common-mode
VCM = (V–) –0.1 V to (V+) –3.5 V
1013 || 4.3
Ω || pF
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Electrical Characteristics: VS = 4.5 V to 36 V; ±2.25 V to ±18 V (continued)
at TA = 25°C, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VO = (V–) + 0.35 V to (V+) – 0.35 V,
RL = 10 kΩ
D Package Only
118
123
VO = (V–) + 0.35 V to (V+) – 0.35 V,
RL = 10 kΩ
DGK and DBV Packages
110
123
VO = (V–) + 0.35 V to (V+) – 0.35 V,
RL = 2 kΩ
106
110
VO = (V–) + 0.35 V to (V+) – 0.35 V,
RL = 2 kΩ, TA = –40°C to +125°C
104
MAX
UNIT
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
dB
dB
FREQUENCY RESPONSE
BW
Gain bandwidth product
SR
Slew rate
Settling time
THD+N
5.5
MHz
20
V/μs
12 bits
10-V Step, G = +1
1.6
16 bits
10-V Step, G = +1
6
Total harmonic distortion and noise
1 kHz, G = +1, VO = 3.5 VRMS
μs
0.0001%
Overload recovery time
600
ns
OUTPUT
Linear output voltage swing range
RL = 10 kΩ, AOL ≥ 108 dB, TA =
–40°C to +125°C
See Figure 24 and Figure 25
(V–) + 0.1
(V+) – 0.1
RL = 2 kΩ, AOL ≥ 108 dB, TA =
–40°C to +125°C
See Figure 24 and Figure 25
(V–) + 0.3
(V+) – 0.3
RL = 10 kΩ
75
RL = 10 kΩ, TA = –40°C to +125°C
VO
Voltage output swing from rail
ISC
Short-circuit current
CLOAD
Capacitive load drive
RO
Open-loop output impedance
V
90
RL = 2 kΩ
210
RL = 2 kΩ,TA = –40°C to +125°C
D Package Only
250
RL = 2 kΩ,TA = –40°C to +125°C
DGK and DBV Packages
350
mV
±20
mA
See Figure 27
f = 1 MHz, IO = 0 (See Figure 26)
150
Ω
POWER SUPPLY
VS
Specified voltage range
IQ
Quiescent current (per amplifier)
±2.25
IO = 0 mA
±18
445
V
475
TA = 0°C to +85°C
590
TA = –40°C to +125°C
655
µA
TEMPERATURE RANGE
6
Specified
–40
125
°C
Operating
–55
150
°C
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6.6 Typical Characteristics
Table 1. Table of Graphs
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
Figure 1
Offset Voltage Drift Distribution From –40°C to +125°C
Figure 2
Input Bias Current Production Distribution
Figure 3
Input Offset Current Production Distribution
Figure 4
Offset Voltage vs Temperature
Figure 5
Offset Voltage vs Common-Mode Voltage
Figure 6
Offset Voltage vs Power Supply
Figure 7
Open-Loop Gain and Phase vs Frequency
Figure 8
Closed-Loop Gain vs Frequency
Figure 9
Input Bias Current vs Common-Mode Voltage
Figure 10
Input Bias Current and Offset vs Temperature
Figure 11
Output Voltage Swing vs Output Current (Maximum Supply)
Figure 12
CMRR and PSRR vs Frequency
Figure 13
CMRR vs Temperature
Figure 14
PSRR vs Temperature
Figure 15
0.1-Hz to 10-Hz Voltage Noise
Figure 16
Input Voltage Noise Spectral Density vs Frequency
Figure 17
THD+N Ratio vs Frequency
Figure 18
THD+N vs Output Amplitude
Figure 19
Quiescent Current vs Supply Voltage
Figure 20
Quiescent Current vs Temperature
Figure 21
Open-Loop Gain vs Temperature (10-kΩ)
Figure 22
Open-Loop Gain vs Temperature (2-kΩ)
Figure 23
DC Open-Loop Gain vs Output Voltage Swing Relative to Supply
Figure 24, Figure 25
Open-Loop Output Impedance vs Frequency
Figure 26
Small-Signal Overshoot vs Capacitive Load (10-mV Step)
Figure 27
No Phase Reversal
Figure 28
Positive Overload Recovery
Figure 29
Negative Overload Recovery
Figure 30
Small-Signal Step Response (10-mV Step)
Figure 31, Figure 32
Large-Signal Step Response (10-V Step)
Figure 33, Figure 34
Settling Time
Figure 35
Short-Circuit Current vs Temperature
Figure 36
Maximum Output Voltage vs Frequency
Figure 37
EMIRR vs Frequency
Figure 38
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
20
15
Amplifiers (%)
Amplifiers (%)
15
10
5
10
5
1.4
1.2
1
0.8
0.6
0.4
0
150
120
90
60
30
0
-30
-60
-90
-120
-150
0.2
0
0
Input Offset Voltage Drift (µV/ƒC)
Offset Voltage (µV)
C002
C001
Figure 1. Offset Voltage Production Distribution
Figure 2. Offset Voltage Drift Distribution
From –40°C to +125°C
30
40
35
25
Amplifiers (%)
Amplifiers (%)
30
25
20
15
20
15
10
10
5
5
Input Offset Current (pA)
Input Bias Current (pA)
C013
C013
Figure 3. Input Bias Current Production Distribution
Figure 4. Input Offset Current Production Distribution
150
Input-referred Offset Voltage ( V)
Input-referred Offset Voltage ( V)
400
300
200
100
0
±100
±200
±300
±400
125
100
75
50
25
0
±25
±50
±75
±100
VCM = 14.5 V
VCM = ± 18.1 V
±125
±150
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
±20
±15
±10
±5
0
5
10
Input Common-mode Voltage (V)
C001
5 Typical Units
15
20
C003
5 Typical Units
Figure 5. Offset Voltage vs Temperature
8
5
4
3
2
1
0
-1
-2
-3
-5
5
4
3
2
1
0
-1
-2
-3
-4
-5
-4
0
0
Figure 6. Offset Voltage vs Common-Mode Voltage
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
120
180
Open-loop Gain
100
Gain (dB)
50
0
VS = ± 2.25 V
±50
100
150
80
120
60
90
40
0
9
18
27
20
30
0
0
±20
36
Supply Voltage (V)
60
Phase
±100
±150
Phase (ƒ)
Input-referred Offset Voltage ( V)
150
1
10
100
1k
10k
100k
1M
-30
10M
Frequency (Hz)
C001
C001
5 Typical Units
Figure 7. Offset Voltage vs Supply Voltage
Figure 8. Open-Loop Gain and Phase vs Frequency
3
60
Gain (dB)
40
Normalized Input Bias Current (pA)
G = +1
G= -1
G= +10
20
0
-20
0
-1.5
-3
100
1k
10k
100k
1M
10M
Frequency (Hz)
±20
±15
±10
±5
0
5
10
15
Input Common-mode Voltage (V)
C004
Figure 9. Closed-Loop Gain vs Frequency
20
C001
Figure 10. Input Bias Current vs Common-Mode Voltage
1V
Output Saturation Voltage (V)
10000
Input Bias Current (pA)
1.5
1000
IBN
100
IBP
IOS
10
Sourcing
100mV
-40°C
Sinking
10mV
25°C
85°C
125°C
1
1mV
±75
±50
±25
0
25
50
75
Temperature (ƒC)
100
125
150
1
Figure 11. Input Bias Current and Offset vs Temperature
10
Output Current (mA)
C001
100
C019
Figure 12. Output Voltage Swing vs Output Current
(Maximum Supply)
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Common-Mode Rejection Ratio (dB)
CMRR
140
Rejection Ratio (dB)
+PSRR
120
±PSRR
100
80
60
40
20
0
0.01
150
140
0.1
130
1
120
110
100
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
10
±75 ±50 ±25
0.01
140
0.1
120
1
100
10
0
25
50
75
100
125
Input-referred Voltage Noise (100 nV/div)
160
±25
75
100 125 150
C017
Figure 16. 0.1-Hz to 10-Hz Voltage Noise
10
1
0.1
-60
G = -1, 2k- Load
G = -1, 600- Load
G = -1, 10k- Load
G = +1, 2k- Load
G = +1, 600- Load
G = +1, 10k- Load
0.01
0.001
-80
-100
0.0001
-120
0.00001
1
10
100
1k
10k
100k
Frequency (Hz)
20
200
2k
-140
20k
Frequency (Hz)
C002
VOUT = 3.5
Figure 17. Input Voltage Noise Spectral Density
vs Frequency
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Total Harmonic Distortion + Noise (dB)
Total Harmonic Distortion + Noise (%)
100
0.1
C001
C001
Figure 15. PSRR vs Temperature
Voltage Noise Spectral Density (nv/¥Hz)
50
Time (1 s/div)
150
Temperature (ƒC)
10
25
Figure 14. CMRR vs Temperature
0.001
Power Supply Rejection Ratio (µV/V)
Power Supply Rejection Ratio (dB)
Figure 13. CMRR and PSRR vs Frequency
±50
0
Temperature (ƒC)
C004
180
±75
Common-mode Rejection Ratio (µV/V)
160
160
C004
VRMS, BW = 90 kHz
Figure 18. THD+N Ratio vs Frequency
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-60
0.01
-80
0.001
500
-100
0.0001
0.00001
0.001
G = -1, 600- Load
G = -1, 2k- Load
G = -1, 10k- Load
G = +1, 600- Load
G = +1, 2k- Load
G = +1, 10k- Load
0.01
0.1
-120
-140
1
400
300
VS = ± 2.25 V
200
100
0
0
10
Output Amplitude (VRMS)
f = 1 kHz
Quiescent Current (µA)
0.1
Total Harmonic Distortion + Noise (dB)
Total Harmonic Distortion + Noise (%)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
9
18
27
36
Supply Voltage (V)
C004
C001
BW = 90 kHz
Figure 20. Quiescent Current vs Supply Voltage
Figure 19. THD+N vs Output Amplitude
1000
140
0.1
Open-loop Gain (dB)
800
700
VS = ± 18 V
600
500
400
VS = ± 2.25 V
300
200
VS = ± 18 V
130
120
1
VS = ± 2.25 V
110
Open-loop Gain (µV/V)
Quiescent Current (µA)
900
100
100
0
±75
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
10
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C001
C001
10-kΩ Load
Figure 21. Quiescent Current vs Temperature
Figure 22. Open-Loop Gain vs Temperature
0.1
140
VS = ± 18 V
120
1
110
10
0
25
50
75
100
80
-40°C
60
RL = 2kŸ
40
-5°C
25°C
85°C
125°C
100
±25
RL = 10kŸ
120
20
VS = ± 2.25 V
±50
DC Open-loop Gain (dB)
130
Open-loop Gain (µV/V)
Open-loop Gain (dB)
140
100
125
Temperature (ƒC)
0
0.01
2-kΩ Load
0.1
Output Voltage Swing from Rail (V)
C001
1
C001
VS = ±18 V
Figure 23. Open-Loop Gain vs Temperature)
Figure 24. Open-Loop Gain vs Output Voltage
Swing to Supply
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
1k
DC Open-loop Gain (dB)
120
Open-loop Output Impedance (Ÿ)
140
RL = 10kŸ
100
80
-40°C
60
-5°C
40
25°C
RL = 2kŸ
85°C
20
100
125°C
10
0
0.01
0.1
10
1
Output Voltage Swing from Rail (V)
100
1k
10k
100k
1M
10M
Frequency (Hz)
C001
100M
C021
VS = ±2.25 V
Figure 25. Open-Loop Gain vs Output Voltage
Swing to Supply
Figure 26. Open-Loop Output Impedance vs Frequency
50
VIN
45
G = +1
Output Voltage (5 V/div)
Overshoot (%)
40
35
30
25
20
15
10
VOUT
G = -1
5
0
10
100
Time (45 ms/div)
1000
Capacitive Load (pF)
C004
C017
10-mV Step
Figure 27. Small-Signal Overshoot vs Capacitive Load
Figure 28. No Phase Reversal
VOUT
VIN
5 V/div
5 V/div
VIN
VOUT
Time (100 ns/div)
Time (100 ns/div)
C017
C017
Figure 29. Positive Overload Recovery
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Figure 30. Negative Overload Recovery
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2.5 mV/div
2.5 mV/div
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Output
Input
Output
Input
Time (200 ns/div)
Time (200 ns/div)
C017
C017
G = +1
10-mV Step
Figure 32. Small-Signal Step Response
2 V/div
2 V/div
Figure 31. Small-Signal Step Response (10-mV Step)
G = –1
Output
Output
Input
Input
Time (2 µs/div)
Time (2 µs/div)
C017
10-V Step
C017
G = –1
10-V Step
Figure 33. Large-Signal Step Response
G = +1
Figure 34. Large-Signal Step Response
40
12-bit Settling = “2.44 mV
Short Circuit Current (mA)
t=0
2 mV/div
Rising Edge
Falling Edge
30
Sinking
20
Sourcing
10
0
Time (250 ns/div)
±75
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
C017
C001
12-bit settling on 10-V step = ±2.44 mV
Figure 35. Settling Time (10-V Step)
Figure 36. Short-Circuit Current vs Temperature
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
40
VS = ±18V
140
Maximum output voltage without
slew-rate induced distortion.
120
30
EMIRR IN+ (dB)
Output Voltage (VPP)
35
25
20
15
10
VS = ±2.25V
5
10k
80
60
40
20
0
1k
100
100k
Frequency (Hz)
1M
10M
0
10M
100M
1000M
Frequency (Hz)
C001
C004
PRF = –10 dBm
Figure 37. Maximum Output Voltage Amplitude vs
Frequency
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Figure 38. EMIRR vs Frequency
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7 Detailed Description
7.1 Overview
The OPA145 device is a low-power JFET input amplifier that features superior drift performance and low input
bias current. The rail-to-rail output swing and input range that includes V– allow designers to use the low-noise
characteristics of JFET amplifier while also interfacing to modern, single-supply, precision analog-to-digital
converters (ADCs) and digital-to-analog converters (DACs). The OPA145 device achieves 5.5-MHz gainbandwidth product and 20-V/μs slew rate and consumes only 445 µA (typical) of quiescent current, making it well
suited for low-power applications. This device operates on a single 4.5-V to 36-V supply or dual ±2.25-V to ±18-V
supplies.
The OPA145 device is fully specified from –40°C to +125°C for use in the most challenging environments and is
available in the 5-pin SOT-23, 8-pin VSSOP, and 8-pin SOIC packages
The Functional Block Diagram shows the simplified diagram of the OPA145.
7.2 Functional Block Diagram
V+
Pre-Output Driver
IN–
OUT
IN+
V–
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7.3 Feature Description
7.3.1 Operating Voltage
The OPA145 op amp can be used with single or dual supplies from an operating range of VS = 4.5 V (±2.25 V)
up to VS = 36 V (±18 V). This device does not require symmetrical supplies; it only requires a minimum supply
voltage of 4.5 V (±2.25 V). For VS less than ±3.5 V, the common-mode input range does not include midsupply.
Supply voltages higher than 40 V can permanently damage the device; see the Absolute Maximum Ratings
table. Key parameters are specified over the operating temperature range, TA = –40°C to +125°C. Key
parameters that vary over the supply voltage, temperature range, or frequency are shown in Typical
Characteristics.
7.3.2 Capacitive Load and Stability
The dynamic characteristics of the OPA145 have been optimized for commonly encountered gains, loads, and
operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase
margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be
isolated from the output. The simplest way to achieve this isolation is to add a small resistor (ROUT equal to 50 Ω,
for example) in series with the output.
Figure 27 illustrates the effects on small-signal overshoot for several capacitive loads. Also, see Feedback Plots
Define Op Amp AC Performance, available for download from the TI website, for details of analysis techniques
and application circuits.
7.3.3 Output Current Limit
The output current of the OPA145 device is limited by internal circuitry to +20 mA/–20 mA (sinking/sourcing to
protect the device if the output is accidentally shorted. This short-circuit current depends on temperature, as
shown in Figure 36.
7.3.4 Noise Performance
Figure 39 shows the total circuit noise for varying source impedances with the operational amplifier in a unitygain configuration (with no feedback resistor network and therefore no additional noise contributions). The
OPA145 and OPA211 are shown with total circuit noise calculated. The op amp itself contributes both a voltage
noise component and a current noise component. The voltage noise is commonly modeled as a time-varying
component of the offset voltage. The current noise is modeled as the time-varying component of the input bias
current and reacts with the source resistance to create a voltage component of noise. Therefore, the lowest noise
op amp for a given application depends on the source impedance. For low source impedance, current noise is
negligible, and voltage noise generally dominates. The OPA145 device has both low voltage noise and extremely
low current noise because of the FET input of the op amp. As a result, the current noise contribution of the
OPA145 is negligible for any practical source impedance, which makes it the better choice for applications with
high source impedance.
The equation in Figure 39 shows the calculation of the total circuit noise, with these parameters:
• en = voltage noise
• In = current noise
• RS = source impedance
• k = Boltzmann's constant = 1.38 × 10–23 J/K
• T = temperature in degrees Kelvin (K)
For more details on calculating noise, see Basic Noise Calculations.
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Voltage Noise Spectral Density, EO (V/Hz1/2)
Feature Description (continued)
10µ
OPA211
1µ
100n
OPA145
10n
1n
Resistor Noise
0.1n
1
10
100
1k
RS = 3.8 kŸ
10k
100k
Source Resistance, RS (Ÿ)
1M
10M
C003
RS = 3.8 kΩ is indicated in Figure 39.
This is the source impedance above which OPA145 is a lower noise option than the OPA211.
Figure 39. Noise Performance of the OPA145 and OPA211 in Unity-Gain Buffer Configuration
7.3.5 Basic Noise Calculations
Low-noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in
many cases; consider the effect of source resistance on overall op amp noise performance. Total noise of the
circuit is the root-sum-square combination of all noise components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of the
resistance. This function is plotted in Figure 39. The source impedance is usually fixed; consequently, select the
op amp and the feedback resistors to minimize the respective contributions to the total noise.
Figure 40 illustrates both noninverting (A) and inverting (B) op amp circuit configurations with gain. In circuit
configurations with gain, the feedback network resistors also contribute noise. In general, the current noise of the
op amp reacts with the feedback resistors to create additional noise components. However, the extremely low
current noise of the OPAx145 means that its current noise contribution can be neglected.
The feedback resistor values can generally be chosen to make these noise sources negligible. Low impedance
feedback resistors load the output of the amplifier. The equations for total noise are shown for both
configurations.
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Feature Description (continued)
(A) Noise in Noninverting Gain Configuration
R1
Noise at the output is given as EO, where
R2
GND
±
EO
+
RS
+
±
VS
Source
GND
'1 = l1 +
:2;
A5 = ¥4 „ G$ „ 6(-) „ 45
d
:3;
A41 æ42 = ¨4 „ G$ „ 6(-) „ d
8
41 „ 42
h d
h
41 + 42
¾*V
Thermal noise of R1 || R2
:4;
G$ = 1.38065 „ 10F23
Boltzmann Constant
:5;
,
h
-
6(-) = 237.15 + 6(°%)
(B) Noise in Inverting Gain Configuration
R1
RS
R2
h
Thermal noise of RS
>-?
Temperature in kelvins
:45 + 41 ; „ 42
42
2
p „ ¨:A0 ;2 + kA41 +45 æ42 o + FE0 „ H
IG
45 + 41
45 + 41 + 42
:6;
'1 = l1 +
+
:7;
:45 + 41 ; „ 42
8
I d
A41 +45 æ42 = ¨4 „ G$ „ 6(-) „ H
h
45 + 41 + 42
¾*V Thermal noise of (R1 + RS) || R2
GND
:8;
G$ = 1.38065 „ 10F23
:9;
6(-) = 237.15 + 6(°%)
±
+
±
d
8
¾*V
> 84/5 ?
Noise at the output is given as EO, where
EO
VS
42
41 „ 42 2
2
p „ ¨:A5 ;2 + :A0 ;2 + kA41 æ42 o + :E0 „ 45 ;2 + lE0 „ d
hp
41
41 + 42
:1;
Source
GND
d
,
h
-
2
> 84/5 ?
Boltzmann Constant
>-?
Temperature in kelvins
Copyright © 2017, Texas Instruments Incorporated
(1)
eN is the voltage noise of the amplifier. For the OPA145 operational amplifier, eN = 7 nV/√Hz at 1 kHz.
(2)
iN is the current noise of the amplifier. For the OPA145 operational amplifier, iN = 0.8 fA/√Hz at 1 kHz.
(3)
For additional resources on noise calculations visit TI's Precision Labs Series.
Figure 40. Noise Calculation in Gain Configurations
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Feature Description (continued)
7.3.6 Phase-Reversal Protection
The OPA145 device has internal phase-reversal protection. Many FET- and bipolar-input op amps exhibit a
phase reversal when the input is driven beyond its linear common-mode range. This condition is most often
encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range,
causing the output to reverse into the opposite rail. The input circuitry of the OPA145 device prevents phase
reversal with excessive common-mode voltage; instead, the output limits into the appropriate rail (see Figure 28).
7.3.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
It is helpful to have a good understanding of this basic ESD circuitry and its relevance to an electrical overstress
event. See Figure 41 for an illustration of the ESD circuits contained in the OPA145 device (indicated by the
dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input
and output pins and routed back to the internal power-supply lines, where they meet at an absorption device
internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit
operation.
An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, highcurrent pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent it from being damaged. The energy
absorbed by the protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more of the amplifier device pins, current flows through one or
more of the steering diodes. Depending on the path that the current takes, the absorption device may activate.
The absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the
OPA145 but below the device breakdown voltage level. Once this threshold is exceeded, the absorption device
quickly activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit such as the one Figure 41 shows, the ESD protection
components are intended to remain inactive and not become involved in the application circuit operation.
However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin.
Should this condition occur, there is a risk that some of the internal ESD protection circuits may be biased on,
and conduct current. Any such current flow occurs through steering diode paths and rarely involves the
absorption device.
Figure 41 depicts a specific example where the input voltage, VIN, exceeds the positive supply voltage (+VS) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the
current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier, and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input while
the power supplies +VS or –VS are at 0 V.
Again, it depends on the supply characteristic while at 0 V, or at a level below the input signal amplitude. If the
supplies appear as high impedance, then the operational amplifier supply current may be supplied by the input
source through the current steering diodes. This state is not a normal bias condition; the amplifier most likely will
not operate normally. If the supplies are low impedance, then the current through the steering diodes can
become quite high. The current level depends on the ability of the input source to deliver current, and any
resistance in the input path.
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Feature Description (continued)
If there is an uncertainty about the ability of the supply to absorb this current, external Zener diodes may be
added to the supply pins as shown in Figure 41. The Zener voltage must be selected such that the diode does
not turn on during normal operation.
However, its Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise
above the safe operating supply voltage level.
(2)
TVS
RF
+VS
+V
RI
ESD CurrentSteering Diodes
-In
(3)
RS
+In
Op Amp
Core
Edge-Triggered ESD
Absorption Circuit
ID
VIN
Out
RL
(1)
-V
-VS
(2)
TVS
(1)
VIN = +VS + 500 mV.
(2)
TVS: +VS(max) > VTVSBR (Min) > +VS
(3)
Suggested value approximately 1 kΩ.
Figure 41. Equivalent Internal ESD Circuitry and Its Relation to a Typical Circuit Application
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Feature Description (continued)
7.3.8 EMI Rejection
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many op amps is a change in the offset voltage as a result of RF
signal rectification. An op amp that is more efficient at rejecting this change in offset as a result of EMI has a
higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in many ways, but this
section provides the EMIRR IN+, which specifically describes the EMIRR performance when the RF signal is
applied to the noninverting input pin of the op amp. In general, only the noninverting input is tested for EMIRR for
the following three reasons:
• Op amp input pins are known to be the most sensitive to EMI, and typically rectify RF signals better than the
supply or output pins.
• The noninverting and inverting op amp inputs have symmetrical physical layouts and exhibit nearly matching
EMIRR performance
• EMIRR is easier to measure on noninverting pins than on other pins because the noninverting input terminal
can be isolated on a PCB. This isolation allows the RF signal to be applied directly to the noninverting input
terminal with no complex interactions from other components or connecting PCB traces.
High-frequency signals conducted or radiated to any pin of the operational amplifier result in adverse effects,
as the amplifier would not have sufficient loop gain to correct for signals with spectral content outside its
bandwidth. Conducted or radiated EMI on inputs, power supply, or output may result in unexpected DC
offsets, transient voltages, or other unknown behavior. Be sure to properly shield and isolate sensitive analog
nodes from noisy radio signals and digital clocks and interfaces. Figure 43 shows the effect of conducted
EMI to the power supplies on the input offset voltage of OPA145.
The EMIRR IN+ of the OPA145 is plotted versus frequency as shown in Figure 42. The OPA145 unity-gain
bandwidth is 5.5 MHz. EMIRR performance below this frequency denotes interfering signals that fall within
the op amp bandwidth.
See EMI Rejection Ratio of Operational Amplifiers, available for download from www.ti.com.
50
EMI-Induced Input Offset Voltage (µV)
140
EMIRR IN+ (dB)
120
100
80
60
40
20
V± Supply
0
±50
V+ Supply
±100
±150
±200
0
10M
100M
100
1000M
Frequency (Hz)
Figure 42. OPA145 EMIRR IN+
1k
10k
100k
Frequency (Hz)
C004
1M
C006
Figure 43. OPA145 EMI-Induced Input Offset Voltage
(Power Supplies)
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Table 2 lists the EMIRR IN+ values for the OPA145 at particular frequencies commonly encountered in real-world
applications. Applications listed in Table 2 may be centered on or operated near the particular frequency shown.
This information may be of special interest to designers working with these types of applications, or working in
other fields likely to encounter RF interference from broad sources, such as the industrial, scientific, and medical
(ISM) radio band.
Table 2. OPA145 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
54 dB
900 MHz
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
68 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
86 dB
2.4 GHz
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
107 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
100 dB
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
105 dB
5 GHz
7.3.9 EMIRR +IN Test Configuration
Figure 44 shows the circuit configuration for testing the EMIRR IN+. An RF source is connected to the op amp
noninverting input terminal using a transmission line. The op amp is configured in a unity-gain buffer topology
with the output connected to a low-pass filter (LPF) and a digital multimeter (DMM). A large impedance mismatch
at the op amp input causes a voltage reflection; however, this effect is characterized and accounted for when
determining the EMIRR IN+. The resulting DC offset voltage is sampled and measured by the multimeter. The
LPF isolates the multimeter from residual RF signals that may interfere with multimeter accuracy.
Ambient temperature: 25Û&
+VS
±
50
Low-Pass Filter
+
RF source
DC Bias: 0 V
Modulation: None (CW)
Frequency Sweep: 201 pt. Log
-VS
Sample /
Averaging
Not shown: 0.1 µF and 10 µF
supply decoupling
Digital Multimeter
Figure 44. EMIRR +IN Test Configuration
7.4 Device Functional Modes
The OPA145 has a single functional mode and is operational when the power-supply voltage is greater than 4.5
V (±2.25 V). The maximum power supply voltage for the OPA145 is 36 V (±18 V).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA145 device is a unity-gain stable operational amplifier with low noise, low input-bias current, and low
input offset voltage. Applications with noisy or high-impedance power supplies require decoupling capacitors
placed close to the device pins. In most cases, 0.1-μF capacitors are adequate. Designers can easily use the
rail-to-rail output swing and input range that includes V– to take advantage of the low-noise characteristics of
JFET amplifiers while also interfacing to modern, single-supply, precision data converters.
8.2 Typical Application
R4
2.94 k
C5
1 nF
R1
590
R3
499
Input
C2
39 nF
±
Output
+
OPA145
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Figure 45. 25-kHz Low-Pass Filter
8.2.1 Design Requirements
Low-pass filters are commonly employed in signal processing applications to reduce noise and prevent aliasing.
The OPAx145 device is ideally suited to construct high-speed, high-precision active filters. Figure 45 shows a
second-order, low-pass filter commonly encountered in signal processing applications.
Use the following parameters for this design example:
• Gain = 5 V/V (inverting gain)
• Low-pass cutoff frequency = 25 kHz
• Second-order Chebyshev filter response with 3-dB gain peaking in the passband
8.2.2 Detailed Design Procedure
The infinite-gain multiple-feedback circuit for a low-pass network function is shown in Figure 45. Use Equation 1
to calculate the voltage transfer function.
1 R1R3C2C5
Output
s
2
Input
s
s C2 1 R1 1 R3 1 R4 1 R3R4C2C5
(1)
This circuit produces a signal inversion. For this circuit, the gain at DC and the low-pass cutoff frequency are
calculated by Equation 2:
R4
Gain
R1
fC
1
2S
1 R3R 4 C2C5
(2)
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Typical Application (continued)
For systems which have different filter parameters or require specific system optimization, such as minimizing the
system noise, an alternative device may be desired. A list of recommended alternatives can be found in Table 3.
Table 3. Alternative Devices
FEATURES
PRODUCT
Low-power, 10-MHz FET input industrial op amp
OPA140
2.2-nV/√Hz, low-power, 36-V op amp in SOT-23 package
OPA209
Low-noise, high-precision, 22-MHz, 4-nV/√Hz JFET-input op amp
OPA827
Low-noise, low IQ precision CMOS op amp
OPA376
Low-power, precision, CMOS, rail-to-rail input/output, low-offset, low-bias op amp
OPA191
Software tools are readily available to simplify filter design. WEBENCH® Filter Designer is a simple, powerful,
and easy-to-use active filter design program. The WEBENCH® Filter Designer lets designers create optimized
filter designs using a selection of TI operational amplifiers and passive components from TI's vendor partners.
Available as a web based tool from the WEBENCH Design Center, WEBENCH Filter Designer allows designers
to design, optimize, and simulate complete multistage active filter solutions within minutes.
8.2.3 Application Curve
20
Gain (db)
0
-20
-40
-60
100
1k
10k
Frequency (Hz)
100k
1M
Figure 46. OPA145 Second-Order, 25-kHz, Chebyshev, Low-Pass Filter
8.3 System Examples
8.3.1 16-bit, 100-kSPS, Fully Differential Transimpedance Imaging and Measurement
OPA145 is used in a differential transimpedance (I-V) measurement application capable of driving the ADS8867,
a 16-bit, microPower, truly-differential ADC, at its maximum conversion rate of 100 kSPS with an acquisition time
of 1200 ns and conversion time of 8800 ns. The first stage supports a forward bandwidth of 493.5 kHz with 100
kΩ of transimpedance gain, enabling the photodiode to fully charge and settle to ±38 µV (±1/2 LSB on 5-V ADC
reference voltage) within the conversion time of the ADC. The differential nature of the system provides several
advantages such as double the transimpedance gain compared to a single-ended system, improved signal-tonoise ratio, easy interfacing to high-precision, fully-differential ADCs, and additional protection against
inductively-coupled noise and interference. Additionally, capacitively-coupled common-mode transients can be
minimized using low-impedance termination resistors RTERM1 and RTERM2.
24
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System Examples (continued)
The second stage provides the reverse bandwidth required for settling to 16-bit accuracy after the internal
sampling capacitor of the successive-approximation-register (SAR) ADC is connected to the second stage. The
two OPA145 amplifiers in the second stage are configured as buffers for maximum closed-loop bandwidth, and
their stability is optimized using R3, C3 and R4, C4 by creating a snubber that reduces the open-loop output
impedance (see Figure 26). C5 and C6 are provided as a charge reservoir for the internal sampling capacitor of
the ADC, and R5 and R6 are tuned to optimize the phase margin of the second stage to drive the output
capacitance. This two-stage approach enables compatibility with a wide selection of high output-impedance
sensors while still maintaining 16-bit settling performance. Furthermore, the first stage can be designed with
sufficient phase margin to drive twisted-pair transmission lines in remote measurement systems. Proper design
of the transmission line reduces the interference of other signals over long distances. Figure 48 shows the
settling performance of the system described previously and in Figure 47 — the settling time during the
acquisition cycle is shown for settling successfully to 0 µA from 5 µs to 6.2 µs. At 6.3 µs, the photodiode current
is changed to 5 µA (full-scale) and settles during the conversion cycle of the ADC (6.2 µs to 15 µs), and is then
acquired successfully from 15 µs to 16.2 µs.
R1
50 k
GND
C1
9 pF
RTERM1
1k
+10V
+10V
R5
22
±
±
OPA145
OPA145
+
+
R3
180
GND
2.5 V to 5 V 2.7 V to 3.6 V
C3
432p
C5
200p
GND
AVDD
REF
ò ‡ 9REF
AINP
GND
ADS8867
GND
Twisted Pair
+
Fast Silicon
PIN Photodiode
5 A
3.8 pF
2.5 mW/cm2
Photovoltaic Mode
GND
OPA145
+
±
OPA145
±
+10V
C2
9 pF
RTERM2
1k
+10V
GND
C4
432p
C6
200p
AINN
GND
R4
180
R6
22
Copyright © 2017, Texas Instruments Incorporated
R2
50 k
Figure 47. 16-bit, 100-kSPS, Fully Differential Transimpedance Schematic
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System Examples (continued)
500
Acquisition Stop
Error Signal
400
Error Voltage (µV)
300
+1/2-LSB
200
100
0
-100
-200
-1/2-LSB
-300
-400
Acquisition Start
-500
0
5
10
Time (µs)
15
20
C005
Figure 48. 16-bit, 100-kSPS, Fully Differential Transimpedance Settling Performance
26
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9 Power Supply Recommendations
The OPA145 device is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply
from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds paying attention to the flow of the ground current. For more detailed
information, see App note: 'The PCB is a component of op amp design''.
• To reduce parasitic coupling, run the input traces as far away as possible from the supply or output
traces. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better
as opposed to in parallel with the noisy trace.
• Place the external components as close as possible to the device. As illustrated in Figure 49, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
• For best performance, TI recommends cleaning the PCB following board assembly.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, TI recommends baking the PCB
assembly to remove moisture introduced into the device packaging during the cleaning process. A low
temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
28
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10.2 Layout Example
+V
R3
1
NC
2
±IN
3
+IN
4
V±
C3
NC
8
±
V+
7
+
OUT
6
NC
5
C4
R1
IN±
IN+
OUT
R2
-V
C1
R4
C2
GND
Use ground pours for
shielding the input
signal pairs
Place bypass
capacitors as close to
IC as possible
C3
C4
R3
IN±
1
NC
NC
8
2
±IN
V+
7
3
+IN
OUT
6
4
V±
NC
5
+V
R1
OUT
R2
IN+
GND
R4
Place components
close to device and to
each other to reduce
parasitic errors
C1
-V
Use a lowESR,ceramic bypass
capacitor
C2
Copyright © 2017, Texas Instruments Incorporated
Figure 49. Operational Amplifier Board Layout for Difference Amplifier Configuration
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 WEBENCH Filter Designer Tool
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.
11.1.1.3 TI Precision Designs
TI Precision Designs are available online at http://www.ti.com/ww/en/analog/precision-designs/. TI Precision
Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of
operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured
performance of many useful circuits.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• The PCB is a component of op amp design
• OPA140, OPA2140, OPA4140 EMI Immunity Performance
• Compensate Transimpedance Amplifiers Intuitively
• Operational amplifier gain stability, Part 3: AC gain-error analysis
• Operational amplifier gain stability, Part 2: DC gain-error analysis
• Using infinite-gain, MFB filter topology in fully differential active filters
• Op Amp Performance Analysis
• Single-Supply Operation of Operational Amplifiers
• Tuning in Amplifiers
• Shelf-Life Evaluation of Lead-Free Component Finishes
• Feedback Plots Define Op Amp AC Performance
• EMI Rejection Ratio of Operational Amplifiers
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
30
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11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
WEBENCH is a registered trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA145ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA145
OPA145IDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1IB2
OPA145IDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1IB2
OPA145IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1I4Q
OPA145IDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1I4Q
OPA145IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA145
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Aug-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
OPA145IDBVR
SOT-23
3000
180.0
DBV
5
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
8.4
3.23
3.17
1.37
4.0
W
Pin1
(mm) Quadrant
8.0
Q3
OPA145IDBVT
SOT-23
DBV
5
250
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
OPA145IDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA145IDGKT
VSSOP
DGK
8
250
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA145IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Aug-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA145IDBVR
SOT-23
DBV
5
3000
213.0
191.0
35.0
OPA145IDBVT
SOT-23
DBV
5
250
213.0
191.0
35.0
OPA145IDGKR
VSSOP
DGK
8
2500
366.0
364.0
50.0
OPA145IDGKT
VSSOP
DGK
8
250
366.0
364.0
50.0
OPA145IDR
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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