Texas Instruments | TLV7081 Nano-Power, 4-Bump WCSP, Small-Size Comparator (Rev. A) | Datasheet | Texas Instruments TLV7081 Nano-Power, 4-Bump WCSP, Small-Size Comparator (Rev. A) Datasheet

Texas Instruments TLV7081 Nano-Power, 4-Bump WCSP, Small-Size Comparator (Rev. A) Datasheet
Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
TLV7081
SNOSD69A – MAY 2018 – REVISED JUNE 2018
TLV7081 Nano-Power, 4-Bump WCSP, Small-Size Comparator
1 Features
3 Description
•
•
•
•
•
•
•
•
The TLV7081 is a single-channel, nano-power
comparator that operates down to 1.7 V. The
comparator is available in an ultra-small, WCSP
package measuring 0.7 mm × 0.7 mm, making the
TLV7081 applicable for space-critical designs like
smartphones and other portable or battery-powered
applications.
1
Wide Supply Voltage Range: 1.7 V to 5.5 V
Quiescent Supply Current of 370 nA
Low Propagation Delay of 4 µs
Open-Drain Output
Independent Input Voltage Range up to 5.6 V
Internal Hysteresis: 10 mV
Temperature Range: –40°C to +125°C
Package:
– 0.7 mm × 0.7 mm WCSP (4)
2 Applications
•
•
•
•
•
•
•
•
The TLV7081 features a wide input-voltage range
that is independent of supply voltage. Having an input
range that is independent of supply voltage allows the
TLV7081 to be directly connected to sources that are
active even if the TLV7081 is not powered.
The TLV7081 has an open-drain output stage that
can be pulled beyond V+, making it appropriate for
level translators and bipolar to single-ended
converters.
Smartphones
Notebook PCs and Tablets
Optical Modules
Digital Cameras
Relays and Circuit Breakers
Portable Medical Devices
Door and Window Sensors
Video Game Controllers
Device Information
PART NUMBER
PACKAGE
TLV7081
(1)
BODY SIZE (NOM)
WCSP (4)
0.7 mm × 0.7 mm
Small-Size, Low-Power Comparator Family
FAMILY
IQ PER
CHAN
tPD
Output Type
TLV7081
370 nA
4 µs
Open-Drain
WCSP
TLV7031
335 nA
3 µs
Push-Pull
X2SON
TLV7041
335 nA
3 µs
Open-Drain
X2SON
TLV7011
5 µA
260 ns
Push-Pull
X2SON
TLV7021
5 µA
260 ns
Open-Drain
X2SON
Package
(1) For all available packages, see the package option addendum
at the end of the datasheet.
UnderVoltage Detection
IS vs. Supply Voltage
600
1.8V
Regulator
Output
GPIO ( Logic Levels )
0V & 1.8V
RPU
R1
+
R2
GPIO (input)
IS (nA)
Lithium
Ion
Battery
500
400
300
Temp -40°C
Temp 25°C
Temp 85°C
Temp 125°C
200
TLV7081
PE ASIC
100
1.5
2
2.5
3
3.5
VS (V)
4
4.5
5
5.5
is_v
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV7081
SNOSD69A – MAY 2018 – REVISED JUNE 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Timing Diagrams .......................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 10
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Applications ................................................ 12
9
Layout ................................................................... 14
9.1 Layout Guidelines ................................................... 14
9.2 Layout Example ...................................................... 14
10 Device and Documentation Support ................. 15
10.1
10.2
10.3
10.4
10.5
10.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
15
15
11 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
Changes from Original (December 2017) to Revision A
Page
•
Changed Advance Information to Production Data ............................................................................................................... 1
•
Added note to the Timing Diagrams section .......................................................................................................................... 6
2
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TLV7081
TLV7081
www.ti.com
SNOSD69A – MAY 2018 – REVISED JUNE 2018
5 Pin Configuration and Functions
YKA Package
4-Bump DSBGA
Top View
Top View
A
OUT
IN
B
V+
V-
1
2
Pin Functions
PIN
I/O
DESCRIPTION
NAME
Number
OUT
A1
O
Comparator output: OUT is open-drain.
V+
B1
P
Positive (highest) power supply; functions as an external reference voltage
V–
B2
P
Negative (lowest) power supply
IN
A2
I
Comparator input: IN is the noninverting input
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TLV7081
3
TLV7081
SNOSD69A – MAY 2018 – REVISED JUNE 2018
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage VS = (V+) - (V-)
Input (IN) to (V–)
(2)
MIN
MAX
UNIT
– 0.3
6
V
– 0.3
Current into input (IN)
Output (OUT) to (V–)
Output short-circuit duration
6
V
– 0.3
Storage temperature, Tstg
(2)
(3)
V
mA
(3)
Junction temperature, TJ
(1)
6
±10
– 65
10
s
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input signals that can swing more than 0.3 V below (V–) must be current-limited to 10 mA or less.
Short-circuit to ground, one comparator per package.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±1500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
1.7
5.5
5.5
V
–40
125
°C
Supply voltage VS = (V+) - (V-)
Open-Drain PULL-UP voltage VPULL-UP
Ambient temperature, TA
UNIT
V
6.4 Thermal Information
TLV7081
THERMAL METRIC (1)
YKA (DSBGA)
UNIT
4 PINS
RθJA
Junction-to-ambient thermal resistance
207
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
1.8
°C/W
RθJB
Junction-to-board thermal resistance
73.2
°C/W
ΨJT
Junction-to-top characterization parameter
1
°C/W
ΨJB
Junction-to-board characterization parameter
73.3
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TLV7081
TLV7081
www.ti.com
SNOSD69A – MAY 2018 – REVISED JUNE 2018
6.5 Electrical Characteristics
Over the operating temperature range of TA = –40°C to +125°C, VS = 3.3 V, and VPULL-UP = V+ (unless otherwise
noted). Typical values are at TA = 25°C. Voltage at input pin (IN) is referenced to (V-).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
–10
±1
10
UNIT
VIO
Input Offset Voltage
VS = 1.8 V and 3.3 V, TA = –40°C to
+125°C
dVIO/dT
Input Offset Voltage Drift
TA = –40°C to +125°C
VHYS
Input Hysteresis Voltage
VIN
Input Voltage Range
IBIAS
Input bias current
IN = 5.6 V, positive value means current
entering pin (IN)
3
pA
ILEAK
Input leakage current
IN = 5.6 V, VS = 0 V, positive value means
current entering pin (IN)
4
pA
CI
Input Capacitance
(1)
0
V
1.9
pF
0.1
V
Sinking 2 mA, measured relative to (V-)
0.4
V
IO-SC
Short-circuit sink current
VS = 5 V
IO-LKG
Output Leakage Current
IN = (V+) + 0.1V (output high), VPULL-UP
= (V+)
PSRR
Power Supply Rejection Ratio
VS = 1.8 V to 5 V
(1)
mV
5.6
Sinking 200 µA, measured relative to (V-)
Low-Level Output Voltage
Supply Current
µV/℃
10
VOL
IS
±3
mV
no load, IN = (V+) – 0.1V (output low),
TA = 25°C
45
mA
130
pA
75
dB
370
470
nA
no load, IN = (V+) – 0.1V (output low),
TA = –40°C to +125°C
630
Over Operating Supply Voltage Range (Vs): 1.7 V to 5.5 V
6.6 Switching Characteristics
Typical values are at TA = 25°C, VS = 3.3 V; CL = 15 pF, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPHL
High-to-low propagation
delay (1)
Input overdrive = –100 mV
4
µs
tPLH
Low-to-high propagation
delay (1)
Input overdrive = +100 mV, RPULL-UP =
4.99 kΩ
4
µs
tF
Output fall time
Measured from 20% to 80%
7
ns
1
ms
tON
(1)
(2)
Start-up delay
(2)
High-to-low and low-to-high refers to the transition at the input pin (IN).
During power on, VS must exceed 1.7 V for 1 ms before the output is in a correct state.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TLV7081
5
TLV7081
SNOSD69A – MAY 2018 – REVISED JUNE 2018
www.ti.com
6.7 Timing Diagrams
VPULL-UP
REF
VPULL-UP
(Vt ) + 1.7V
tON
(Vt )
REF
VPULL-UP
OUT
+
OUT
50%
(Vt )
Figure 1. Start-up Delay
VPULL-UP
REF + 100 mV
IN
REF
REF
OUT
+
IN
REF t 100 mV
tpHL
+
±
tpLH
VPULL-UP
80%
80%
OUT
50%
20%
Vt
50%
20%
tF
tR
Figure 2. Timing Diagram
NOTE
The propagation delays tpLH and tpHL include the contribution of input offset and hysteresis.
6
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TLV7081
TLV7081
www.ti.com
SNOSD69A – MAY 2018 – REVISED JUNE 2018
6.8 Typical Characteristics
TA = 25°C, VS = 3.3 V, RPULL-UP = 4.99 kΩ, CL = 15 pF
9
TA = 40qC
TA = 25qC
TA = 125qC
7.5
Propagation Delay H-L (Ps)
Propagation Delay L-H (Ps)
9
6
4.5
3
1.5
10
20
30 40 50 70 100
Input Overdrive (mV)
200
300
7.5
6
4.5
3
1.5
10
500
20
30 40 50 70 100
Input Overdrive (mV)
tPLH
VS = 1.8 V
200
300
500
tPHL
VS = 1.8 V
Figure 3. Propagation Delay (L-H) vs. Input Overdrive
Figure 4. Propagation Delay (H-L) vs. Input Overdrive
9
9
TA = 40qC
TA = 25qC
TA = 125qC
7.5
Propagation Delay H-L (Ps)
Propagation Delay L-H (Ps)
TA = 40qC
TA = 25qC
TA = 125qC
6
4.5
3
1.5
10
20
30 40 50 70 100
Input Overdrive (mV)
200
300
TA = 40qC
TA = 25qC
TA = 125qC
7.5
6
4.5
3
1.5
10
500
20
30 40 50 70 100
Input Overdrive (mV)
tPLH
VS = 3.3 V
200
300
500
tPHL
VS = 3.3 V
Figure 5. Propagation Delay (L-H) vs. Input Overdrive
Figure 6. Propagation Delay (H-L) vs. Input Overdrive
1x105
5000
Output Leakage Current (pA)
Input Bias Current (pA)
1000
100
10
1
0.1
TA = 40qC
TA = 25qC
TA = 85qC
TA = 125qC
1x103
1x102
1x101
VPULL-UP = 1.8 V
VPULL-UP = 3.3 V
VPULL-UP = 5.0 V
1x100
0.01
0.002
0.1
1x104
1
IN (V)
10
2x10-1
-40
ibia
0
40
80
Temperature (°C)
120
160
ilea
VS = 3.3 V
Figure 7. Input Bias Current vs. IN
Figure 8. Output Leakage Current vs. Temperature
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TLV7081
7
TLV7081
SNOSD69A – MAY 2018 – REVISED JUNE 2018
www.ti.com
Typical Characteristics (continued)
TA = 25°C, VS = 3.3 V, RPULL-UP = 4.99 kΩ, CL = 15 pF
5
2
1
OUT (V)
OUT (V)
1
0.1
0.1
TA = -40°C
TA = 25°C
TA = 125°C
0.01
0.1
1
Iout (Sink) (mA)
10
0.005
0.1
20
1
Iout (Sink) (mA)
vout
VS = 1.8 V
10
50
vout
VS = 3.3 V
Figure 9. Output Voltage Low vs. Output Sink Current
Figure 10. Output Voltage Low vs. Output Sink Current
10
0.2
0.16
Input Offset (mV)
1
OUT (V)
TA = -40°C
TA = 25°C
TA = 125°C
0.01
0.1
0.01
1
10
0.12
0.08
0.04
TA = -40°C
TA = 25°C
TA = 125°C
0.005
0.1
0
1.5
100
Iout (Sink) (mA)
Temp -40°C
Temp 25°C
Temp 85°C
Temp 125°C
2
2.5
3
vout
3.5
VS (V)
4
4.5
5
5.5
vio_
VS = 5 V
Figure 12. Input Offset vs. VS
Figure 11. Output Voltage Low vs. Output Sink Current
0.16
11
VS = 1.8v
VS = 3.3v
VS = 5v
0.14
10
0.1
VHYST (mV)
Input Offset (mV)
0.12
Temp -40°C
Temp 25°C
Temp 85°C
Temp 125°C
0.08
0.06
9
8
0.04
7
0.02
0
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
140
6
1.5
vio_
Figure 13. Input Offset vs. Temperature
8
Submit Documentation Feedback
2
2.5
3
3.5
VS (V)
4
4.5
5
5.5
vhys
Figure 14. Hysteresis vs VS
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TLV7081
TLV7081
www.ti.com
SNOSD69A – MAY 2018 – REVISED JUNE 2018
Typical Characteristics (continued)
TA = 25°C, VS = 3.3 V, RPULL-UP = 4.99 kΩ, CL = 15 pF
20
11
10.5
10
15
Frequency (%)
9
8.5
8
5
7.5
VS = 1.8v
VS = 3.3v
VS = 5v
7
vhys
4
3
5
3.
2
5
2.
140
1
120
5
100
1.
40
60
80
Temperature (°C)
0
20
0.
0
5
0
-20
.5
-3
-2
.5
-2
-1
.5
-1
-0
.5
6.5
-40
10
-3
VHYST (mV)
9.5
vos_
Input Offset (mV)
Distribution Taken from 7,990 Comparators
Figure 16. Input Offset Histogram
600
20
500
15
400
IS (nA)
25
8.
8.
8.
8.
9
9.
2
9.
4
9.
6
9.
8
10
10
.2
10
.4
100
1.5
8
0
6
200
4
5
8
300
2
10
7.
4
7.
6
7.
8
Frequency (%)
Figure 15. Hysteresis vs. Temperature
Temp -40°C
Temp 25°C
Temp 85°C
Temp 125°C
2
2.5
3
vhys
Hysteresis (mV)
3.5
VS (V)
4
4.5
5
5.5
is_v
IN = (V+) - 0.1V (output low), No load.
Distribution Taken from 7,990 Comparators
Figure 18. Supply Current vs. VS
Figure 17. Hysteresis Histogram
600
550
IS (nA)
500
450
400
VS = 1.8v
VS = 3.3v
VS = 5v
350
300
-40
-20
0
20
40
60
Temperature (°C)
80
100
120
is_t
IN = (V+) - 0.1V (output low), No load.
Figure 19. Supply Current vs. Temperature
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TLV7081
9
TLV7081
SNOSD69A – MAY 2018 – REVISED JUNE 2018
www.ti.com
7 Detailed Description
7.1 Overview
The TLV7081 is a single-channel, nano-power comparator that does not need a dedicated power supply
connection, and can operate down to 1.7 V. The comparator is available in an ultra-small, WCSP package
measuring 0.7 mm × 0.7 mm, making the TLV7081 applicable for space-critical designs like smartphones and
other portable or battery-powered applications.
The TLV7081 features a wide input-voltage range that is independent of supply voltage. Having an input range
that is independent of supply voltage allows the TLV7081 to be directly connected to sources that are active
even if the TLV7081 is not powered.
The TLV7081 has an open-drain output stage that can be pulled beyond V+, making it appropriate for level
translators and bipolar to single-ended converters.
7.2 Functional Block Diagram
VREF
VPULL-UP
TLV7081
V+
OUT
IN
+
Bias
POR
V7.3 Feature Description
The TLV7081 is a single-channel, nano-power comparator that operates down to 1.7 V. The inverting input is
internally tied to V+ which helps to streamline applications which use supply as the reference. The non-inverting
input IN extends to 5.6 V which is independent of the power supply V+ (1.7 V - 5.5 V) and it's available in an
ultra-small, WCSP package measuring 0.7 mm × 0.7 mm.
7.4 Device Functional Modes
The TLV7081 has a power-on-reset (POR) circuit. While the power supply (VS) is greater than VPOR (typically 1V)
and less than the minimum operating supply voltage, either upon ramp-up or ramp-down, the POR circuitry is
activated.
The POR circuit keeps the output high impedance (logical high) while activated.
When the supply voltage is greater than, or equal to, the minimum supply voltage, the comparator output reflects
the state of the input IN.
10
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TLV7081
TLV7081
www.ti.com
SNOSD69A – MAY 2018 – REVISED JUNE 2018
Device Functional Modes (continued)
7.4.1 Inputs
The TLV7081 input extends from V- to 5.6 V which is independent of supply. The input IN can be any voltage
within these limits and no phase inversion of the comparator output occurs.
The input of TLV7081 is fault tolerant. It maintains the same high input impedance when V+ is unpowered or
ramping up. The input can be safely driven up to the specified maximum voltage (5.6 V) with V+ = 0 V or any
value up to the maximum specified.
The input bias current is typically 3 pA for input IN voltages between 0 and 5.6 V. The comparator inputs are
protected from undervoltage by internal diodes connected to V-. As the input voltage goes under V-, the
protection diodes become forward biased and begin to conduct causing the input bias current to increase
exponentially. Input bias current typically doubles for every 10°C temperature increase.
7.4.2 Internal Hysteresis
The device hysteresis transfer curve is shown in Figure 20. This curve is a function of three components: VTH,
VOS, and VHYST:
• VTH is the actual set voltage or threshold trip voltage.
• VOS is the internal offset voltage between IN and V+. This voltage is added to VTH to form the actual trip point
at which the comparator must respond to change output states.
• VHYST is the internal hysteresis (or trip window) that is designed to reduce comparator sensitivity to noise
(10 mV typical).
VTH + VOS - (VHYST / 2)
VTH + VOS
VTH + VOS + (VHYST / 2)
Figure 20. Hysteresis Transfer Curve
7.4.3 Output
The TLV7081 features an open-drain output stage enabling the output logic levels to be pulled up to an external
source up to 5.5 V independently of the supply voltage.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TLV7081
11
TLV7081
SNOSD69A – MAY 2018 – REVISED JUNE 2018
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV7081 is a 4-pin, nano-power comparator with open-drain output that is well suited for monitoring battery
voltages. The TLV7081's benefits include a small package footprint and a unique input stage that allows the
comparator input to be driven by a voltage source even when the operating voltage for the comparator is turnedoff (zero volts).
8.2 Typical Applications
8.2.1 Nano-Power Battery Monitor
The application of the TLV7081 for an under-voltage detection circuit is shown in Figure 21.
VPULL-UP
REF
1.7 to 5.5 V
TLV7081
VDD
V+
OUT
IN
+
UV
MicroController
Battery
V±
Copyright © 2017, Texas Instruments Incorporated
Figure 21. Under-Voltage Detection
8.2.1.1 Design Requirements
For this design, follow these design requirements:
• The supply voltage connected to pin (V+) serves as the reference voltage for the comparator and can be any
voltage between 1.7 V and 5.5 V.
• The voltage applied to the input pin (IN) can be any voltage in the range of 0 V to 5.6 V. This voltage range is
uniquely independent of the supply voltage applied to pin (V+).
• The comparator output pin (OUT) requires a pull-up resistor that sets the output-high logic level (VOH) for the
comparator. VPULL-UP should be connected to the supply voltage of the microcontroller which is monitoring the
comparator output and serves as the level-shifting block for the logic levels in the application.
12
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TLV7081
TLV7081
www.ti.com
SNOSD69A – MAY 2018 – REVISED JUNE 2018
Typical Applications (continued)
8.2.1.2 Detailed Design Procedure
Instead of being powered directly from the battery, the TLV7081 is powered directly from a voltage reference that
exists in the system. The input to the comparator (IN) is allowed to operate above and below the reference
voltage due to the unique analog front end of the TLV7081. When the battery voltage is above the reference
threshold, the output of the comparator is high and when the battery drops below the threshold of the reference,
the output of the comparator goes low (see Figure 22 for details). For simplicity, the integrated hysteresis of the
comparator is not shown in the timing diagram. Integrated hysteresis is helpful in avoiding glitches at the
comparator output when operating in noisy environments or when the input voltage changes thresholds very
slowly. An open-drain output configuration allows the output logic level of the comparator to be level-shifted to
match the logic level of the receiving device.
8.2.1.3 Application Curve
When the voltage applied to the input pin (IN) falls below the reference threshold (REF), the output pin (OUT) is
pulled low to ground (V-). Moreover, when the input voltage rises above REF, the output of the comparator goes
into a high impedance state and the OUT pin is pulled high by the pull-up resistor and VPULL-UP supply voltage.
IN
REF
VPULL-UP
OUT
(V-)
Figure 22. Under-Voltage Timing Results
8.2.2 Battery Monitoring in Portable Electronics
A recommended circuit diagram for monitoring a battery voltage in a personal electronic device is shown in
Figure 23. In this diagram, the GPIO pin of an application specific integrated circuit (ASIC) serves as the supply
voltage and the voltage reference for the TLV7081. Using a GPIO pin to power the TLV7081 is possible because
of the low quiescent current of the TLV7081. In systems where power consumption needs to be further reduced,
the GPIO pin can be used to power-cycle the TLV7081.
1.8V
Regulator
Lithium
Ion
Battery
Output
GPIO ( Logic Levels )
0V & 1.8V
RPU
R1
+
R2
GPIO (input)
TLV7081
PE ASIC
Figure 23. Battery Monitor
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TLV7081
13
TLV7081
SNOSD69A – MAY 2018 – REVISED JUNE 2018
www.ti.com
9 Layout
9.1 Layout Guidelines
A power supply bypass capacitor of 100 nF is recommended when supply output impedance is high, supply
traces are long, or when excessive noise is expected on the supply lines. Bypass capacitors are also
recommended when the comparator output drives a long trace or is required to drive a capacitive load. Due to
the fast rising and falling edge rates and high-output sink and source capability of the TLV7081 output stages,
higher than normal quiescent current can be drawn from the power supply. Under this circumstance, the system
would benefit from a bypass capacitor across the supply pins.
9.2 Layout Example
Figure 24. Layout Example
14
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TLV7081
TLV7081
www.ti.com
SNOSD69A – MAY 2018 – REVISED JUNE 2018
10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
For related documentation see the following:
• TLV7081
• TLV7031
• TLV7041
• TLV7011
• TLV7021
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
10.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
10.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
10.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TLV7081
15
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
TLV7081YKAR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
DSBGA
YKA
4
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
SAC396 | SNAGCU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TLV7081YKAR
DSBGA
YKA
4
3000
180.0
8.4
TLV7081YKAR
DSBGA
YKA
4
3000
180.0
8.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
0.8
0.8
0.47
4.0
8.0
Q1
0.8
0.8
0.47
4.0
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV7081YKAR
DSBGA
YKA
4
3000
182.0
182.0
20.0
TLV7081YKAR
DSBGA
YKA
4
3000
182.0
182.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
YKA0004
DSBGA - 0.4 mm max height
SCALE 14.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
0.4 MAX
C
SEATING PLANE
0.18
0.13
0.05 C
BALL TYP
0.35 TYP
B
SYMM
0.35
TYP
E: Max = 0.73 mm, Min = 0.67 mm
A
4X
0.015
0.25
0.15
C A B
D: Max = 0.73 mm, Min = 0.67 mm
2
1
SYMM
4221909/B 08/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YKA0004
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
4X ( 0.2)
2
1
A
SYMM
(0.35) TYP
B
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:60X
( 0.2)
METAL
SOLDER MASK
OPENING
0.0325 MAX
EXPOSED
METAL
0.0325 MIN
METAL UNDER
SOLDER MASK
EXPOSED
METAL
NON-SOLDER MASK
DEFINED
( 0.2)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4221909/B 08/2018
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YKA0004
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
4X ( 0.21)
(R0.05) TYP
2
1
A
SYMM
(0.35)
TYP
B
METAL
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm - 0.1 mm THICK STENCIL
SCALE:60X
4221909/B 08/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising