Texas Instruments | TS321 Low-Power Single Operational Amplifier (Rev. D) | Datasheet | Texas Instruments TS321 Low-Power Single Operational Amplifier (Rev. D) Datasheet

Texas Instruments TS321 Low-Power Single Operational Amplifier (Rev. D) Datasheet
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TS321
SLOS489D – DECEMBER 2005 – REVISED MAY 2018
TS321 Low-Power Single Operational Amplifier
1 Features
3 Description
•
The TS321 is a bipolar operational amplifier for costsensitive applications in which space savings are
important.
1
•
•
•
•
Wide Power-Supply Range
– Single Supply from 3 V to 30 V
– Dual Supply from ±1.5 V to ±15 V
Large Output Voltage Swing from
0 V to 3.5 V (Minimum) (VCC = 5 V)
Low Supply Current at 500 μA (Typical)
Low Input Bias Current at 20 nA (Typical)
Stable With High Capacitive Loads
Device Information(1)
PART NUMBER
TS321
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.90 mm
SOT-23 (5)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
Desktop PCs
HVAC: Heating, Ventilating, and Air Conditioning
Portable Media Players
Refrigerators
Washing Machines: High-End and Low-End
NC 1
8 NC
IN– 2
7 VCC+
IN+ 3
6 OUT
VCC– 4
5 NC
OUT 1
5 VCC+
VCC– 2
IN+ 3
4 IN–
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TS321
SLOS489D – DECEMBER 2005 – REVISED MAY 2018
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information: TS321 .....................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 9
8
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application ................................................. 10
9 Power Supply Recommendations...................... 12
10 Layout................................................................... 12
10.1 Layout Guidelines ................................................. 12
10.2 Layout Example .................................................... 12
11 Device and Documentation Support ................. 14
11.1
11.2
11.3
11.4
Documentation Support .......................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
4 Revision History
Changes from Revision C (April 2015) to Revision D
•
Corrected SOIC package pinout quantity from "SOIC (14)" to "SOIC (8)" in Device Information table................................. 1
Changes from Revision B (December 2013) to Revision C
•
2
Page
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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5 Pin Configuration and Functions
D Package
8-Pin SOIC
(Top View)
NC 1
8 NC
IN– 2
7 VCC+
IN+ 3
6 OUT
VCC– 4
5 NC
NC - no internal connection
DBV Package
5-Pin SOT-23
(Top View)
5 VCC+
OUT 1
VCC– 2
IN+ 3
4 IN–
Pin Functions
PIN
NAME
I/O
DESCRIPTION
SOIC
SOT-23
IN–
2
4
I
Negative input
IN+
3
3
I
Positive input
—
—
Do not connect
1
NC
5
8
OUT
6
1
O
Output
VCC–
4
2
—
Negative supply
VCC+
7
5
—
Positive supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage, VCC
MAX
Single supply
32
Dual supplies
±16
Differential input voltage (2),VID
Input voltage range
(3)
, VI
–0.3
Input current, IIK
Duration of output short circuit to ground, tshort
Storage temperature, Tstg
(2)
(3)
V
±32
V
32
V
50
mA
Unlimited
Operating virtual junction temperature, TJ
(1)
UNIT
–65
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Differential voltages are at IN+ with respect to IN–.
Input voltages are at IN with respect to VCC–.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Single supply
VCC
Supply voltage
TA
Operating free-air temperature
Dual supply
MIN
MAX
3
30
±1.5
±15
–40
125
UNIT
V
°C
6.4 Thermal Information: TS321
TS321
THERMAL METRIC (1)
RθJA
(1)
(2)
(3)
4
(2) (3)
Junction-to-ambient thermal resistance
D (SOIC)
DBV (SOT-23)
5 PINS
5 PINS
97
206
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Maximum power dissipation is a function of TJ(max), qJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = [TJ(max) – TA] / qJA. Selecting the maximum of 150°C can effect reliability.
The package thermal impedance is calculated in accordance with JESD 51-7.
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6.5 Electrical Characteristics
VCC+ = 5 V, VCC– = GND, VO = 1.4 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
RS = 0, 5 V < VCC+ < 30 V
0 < VIC < (VCC+ – 1.5 V)
VIO
Input offset voltage
IIO
Input offset current
IIB
Input bias current (1)
AVD
Large-signal differential
voltage amplification
VCC = 15 V, RL = 2 kΩ
VO = 1.4 V to 11.4 V
VICR
Common-mode input
voltage (2)
VCC = 30 V
VOH
High-level output voltage
MIN
TA = 25°C
TYP
MAX
0.5
4
TA = Full range
5
TA = 25°C
2
TA = Full range
30
50
TA = 25°C
20
TA = Full range
150
200
TA = 25°C
50
TA = Full range
25
100
0
VCC+ – 1.5
TA = Full range
0
VCC+ – 2
TA = 25°C
VCC = 30 V
RL = 10 kΩ
TA = 25°C
VCC = 5 V
RL = 2 kΩ
TA = 25°C
TA = Full range
TA = Full range
TA = Full range
26
mV
nA
nA
V/mV
TA = 25°C
VCC = 30 V
RL = 2 kΩ
UNIT
V
27
25.5
27
28
V
26.5
3.5
3
TA = 25°C
5
15
VOL
Low-level output voltage
RL = 10 kΩ
GBP
Gain bandwidth product
VCC = 30 V, VI = 10 mV, RL = 2 kΩ
f = 100 kHz, CL = 100 pF
TA = 25°C
0.8
MHz
SR
Slew rate
VCC = 15 V, VI = 0.5 V to 3 V, RL = 2 kΩ,
CL = 100 pF, unity gain,
TA = 25°C
0.4
V/µs
φm
Phase margin
TA = 25°C
60
°
Common-mode rejection ratio
RS ≤ 10 kΩ
TA = 25°C
65
85
dB
VCC = 15 V, VO = 2 V, VID = 1 V
TA = 25°C
20
40
mA
VCC = 15 V, VID = 1 V
VO = 2 V
TA = 25°C
10
20
mA
VCC = 15 V, VID = 1 V
VO = 0.2 V
TA = 25°C
12
50
µA
65
110
CMRR
ISOURCE Output source current
ISINK
Output sink current
TA = Full range
IO
Short-circuit to GND
VCC = 15 V, TA = 25°C
SVR
Supply-voltage rejection ratio
VCC = 5 V to 30 V, TA = 25°C
ICC
Total supply current
20
40
(1)
(2)
Total harmonic distortion
500
800
VCC = 30 V
TA = 25°C, no load
600
900
VCC = 5 V
TA = full range, no load
600
900
VCC = 30 V, VO = 2 Vpp, AV = 20 dB
RL = 2 k, f = 1 kHz, CL = 100 pF, TA = 25°C
mA
dB
VCC = 5 V
TA = 25°C, no load
µA
VCC = 30 V
TA = full range, no load
THD
60
mV
1000
0.015%
The direction of the input current is out of the device. This current essentially is constant, independent of the state of the output, so no
loading change exists on the input lines.
The input common-mode voltage of either input signal should not be allowed to go negative by more than 0.3 V. The upper end of the
common-mode voltage range is VCC+ – 1.5 V, but either or both inputs can go to 32 V without damage.
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Electrical Characteristics (continued)
VCC+ = 5 V, VCC– = GND, VO = 1.4 V (unless otherwise noted)
PARAMETER
eN
6
Equivalent input noise voltage
TEST CONDITIONS
VCC = 30 V, f = 1 kHz, RS = 100 Ω
TA = 25°C
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MIN
TYP
MAX
UNIT
50
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6.6 Typical Characteristics
45
0.8
40
0.7
0.6
30
ICC (mA)
Input Bias (nA)
35
25
20
15
0.5
0.4
0.3
0.2
10
5
Vcc = 5V
0.1
Vcc = 5V
0
Vcc = 30V
0.0
±50
±25
0
25
50
75
100
125
Temperature (C)
±50
±25
0
25
50
75
100
125
Temperature (C)
C001
Figure 1. Input Current vs Temperature
C001
Figure 2. Supply Current vs Temperature
2.5
2.5
-40C
Voltage from Vcc+ (V)
25C
2.0
VOL (V)
125C
1.5
1.0
0.5
2.0
1.5
1.0
0.5
Iout = 3mA
Iout = 15mA
0.0
0.0
0.01
0.1
1
10
IOL (mA)
±50
±25
0
25
50
75
100
125
Temperature (C)
C001
Figure 3. Output Sinking Characteristics
C001
Figure 4. Output Sourcing Characteristics
25
0
±5
±10
Output (mA)
Output (mA)
20
15
10
±15
±20
±25
±30
±35
5
±40
Vcc = 15V
0
±50
±25
0
25
50
75
100
Temperature (C)
125
±50
±25
(1)
0
25
50
75
100
Temperature (C)
C001
Figure 5. Short-Circuit Current to Supply
(1)
Vcc = 15V
±45
125
C001
Figure 6. Short-Circuit Current to Ground
Short circuits from outputs to VCC can cause excessive heating and eventual destruction.
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7 Detailed Description
7.1 Overview
The TS321 is a single-channel operational amplifier. The device can handle a single supply between 3 V and 30
V or a dual-supply between ±1.5 V and ±15 V. Available in the small SOT-23 package, the TS321 is great for
saving space in any application.
7.2 Functional Block Diagram
VCC
IN–
IN+
OUT
7.3 Feature Description
7.3.1 Operating Voltage
The TS321 can be powered from a single supply between 3 V and 30 V or a dual-supply between ±1.5 V and
±15 V.
7.3.2 Gain Bandwidth Product
Gain bandwidth product is found by multiplying a measured bandwidth of the amplifier by the gain at which that
bandwidth was measured. The TS321 has a gain bandwidth of 0.8 MHz.
7.3.3 Slew Rate
The slew rate is the rate at which an operational amplifier can change the output when there is a change on the
input. The TS321 has a 0.4-V/μs slew rate.
8
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Feature Description (continued)
7.3.4 Input Common-Mode Range
The valid common-mode range is from device ground pin to VCC – 1.5 V (VCC – 2 V across temperature).
Inputs may exceed VCC up to the maximum VCC without device damage. At least one input must be in the valid
input common-mode range for output to be correct phase. If both inputs exceed valid range then output phase is
undefined. If either input is less than –0.3 V then input current must be limited to 1 mA and output phase is
undefined.
7.3.5 Stability With High Capacitive Loads
Operational amplifiers have reduced phase margin when there is a direct capacitance on the output. The stability
is affected most when the amplifier is set to unity gain. Small signal response to a step input of 100 mV reveals
the loop stability with a range of capacitors. See SLVA381 to correlate response waveform to phase margin. The
responses at 1 nF or less indicate acceptable phase margin. The responses at 1 uF and above indicate good
phase margin.
100 nF
100 pF
1 µF
1 nF
10 µF
10 nF
Figure 7. Small-Signal Response
7.4 Device Functional Modes
The TS321 is powered on when the supply is connected. This device can operate as a single-supply operational
amplifier or dual-supply amplifier depending on the application.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TS321 operational amplifier is useful in a wide range of signal conditioning applications. Inputs can be
powered before VCC for flexibility in multiple supply circuits.
8.2 Typical Application
A typical application for an operational amplifier in an inverting amplifier. This amplifier takes a positive voltage
on the input, and makes the voltage a negative voltage of the same magnitude. In the same manner, the
amplifier makes negative voltages positive.
RF
RI
Vsup+
VOUT
+
VIN
Vsup-
Figure 8. Typical Application Schematic
8.2.1 Design Requirements
The supply voltage must be selected such that the supply voltage is larger than the input voltage range and
output range. For instance, this application scales a signal of ±0.5 V to ±1.8 V. Setting the supply at ±12 V is
sufficient to accommodate this application.
8.2.2 Detailed Design Procedure
Determine the gain required by the inverting amplifier:
AV
AV
VOUT
VIN
1.8
0.5
(1)
3.6
(2)
Once the desired gain is determined, select a value for RI or RF. Selecting a value in the kilohm range is
desirable because the amplifier circuit uses currents in the milliamp range. This ensures the part does not draw
too much current. This example selects 10 kΩ for RI which means 36 kΩ is be used for RF. This is determined
by Equation 3.
AV
10
RF
RI
(3)
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Typical Application (continued)
8.2.3 Application Curve
2
VIN
1.5
VOUT
1
Volts
0.5
0
-0.5
-1
-1.5
-2
0
0.5
1
Time (ms)
1.5
2
Figure 9. Input and Output Voltages of the Inverting Amplifier
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9 Power Supply Recommendations
The TS321 is specified to operate between 3 V and 30 V or a dual supply between ±1.5 V and ±15 V.
CAUTION
Supply voltages larger than 32 V for a single supply, or outside the range of ±16 V for
a dual supply can permanently damage the device (see the Absolute Maximum
Ratings ).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, see
SLOA089.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Example.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
VIN
RIN
RG
+
VOUT
RF
Figure 10. Operational Amplifier Schematic for Noninverting Configuration
12
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Layout Example (continued)
Place components close to
device and to each other to
reduce parasitic errors
Run the input traces as far
away from the supply lines
as possible
RF
VS+
NC
NC
IN1í
VCC+
IN1+
OUT
VCCí
NC
Use low-ESR, ceramic
bypass capacitor
RG
GND
VIN
RIN
GND
Only needed for
dual-supply
operation
GND
VS(or GND for single supply)
VOUT
Ground (GND) plane on another layer
Figure 11. Operational Amplifier Board Layout for Noninverting Configuration
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For more information, see the following:
• Simplifying Stability Checks
• Circuit Board Layout Techniques
11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14
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PACKAGE OPTION ADDENDUM
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11-Apr-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TS321ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
SR321I
TS321IDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(9C1G, 9C1S)
TS321IDBVRE4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
9C1G
TS321IDBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
9C1G
TS321IDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(9C1G, 9C1S)
TS321IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
SR321I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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11-Apr-2018
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TS321 :
• Automotive: TS321-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TS321IDBVR
SOT-23
DBV
5
3000
180.0
8.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.23
3.17
1.37
4.0
8.0
Q3
TS321IDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TS321IDBVRG4
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TS321IDBVT
SOT-23
DBV
5
250
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
TS321IDBVT
SOT-23
DBV
5
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TS321IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TS321IDBVR
SOT-23
DBV
5
3000
202.0
201.0
28.0
TS321IDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TS321IDBVRG4
SOT-23
DBV
5
3000
180.0
180.0
18.0
TS321IDBVT
SOT-23
DBV
5
250
202.0
201.0
28.0
TS321IDBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
TS321IDR
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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