Texas Instruments | INA317 Micro-Power (50-µA), Zero-Drift, Rail-to-Rail-Out Instrumentation Amplifier | Datasheet | Texas Instruments INA317 Micro-Power (50-µA), Zero-Drift, Rail-to-Rail-Out Instrumentation Amplifier Datasheet

Texas Instruments INA317 Micro-Power (50-µA), Zero-Drift, Rail-to-Rail-Out Instrumentation Amplifier Datasheet
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INA317
SBOS896 – NOVEMBER 2017
INA317 Micro-Power (50-µA), Zero-Drift, Rail-to-Rail-Out Instrumentation Amplifier
1 Features
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1
3 Description
The INA317 is a low-power, precision instrumentation
amplifier offering excellent accuracy. The versatile 3operational amplifier design, small size and low
power make the INA317 usable in a wide range of
portable applications.
Low Offset Voltage: 75 µV (Maximum), G ≥ 100
Low Drift: 0.3 µV/°C, G ≥ 100
Low Noise: 50 nV/√Hz, G ≥ 100
High CMRR: 100 dB (Minimum), G ≥ 10
Low Input Bias Current: 200 pA (Maximum)
Supply Range: 1.8 V to 5.5 V
Input Voltage: (V–) 0.1 V to (V+) –0.1 V
Output Range: (V–) 0.05 V to (V+) –0.05 V
Low Quiescent Current: 50 µA
Operating Temperature: –40°C to +125°C
RFI Filtered Inputs
8-Pin VSSOP Package
A single external resistor sets any gain from 1 to
1000, as defined by the industry-standard gain
equation: G = 1 + (100 kΩ / RG).
The instrumentation amplifier provides low offset
voltage (75 µV, G ≥ 100), excellent offset voltage drift
(0.3 µV/°C, G ≥ 100) and high common-mode
rejection (100 dB at G ≥ 10). The INA317 operates
with power supplies as low as 1.8 V (±0.9 V) and a
quiescent current of 50 µA, making the device usable
in battery-operated systems. Using autocalibration
techniques to ensure precision over the extended
industrial temperature range, the INA317 device
offers low noise density (50 nV/√Hz) that extends
down to DC.
2 Applications
•
•
•
•
•
•
•
•
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Bridge Amplifiers
ECG Amplifiers
Pressure Sensors
Medical Instrumentation
Portable Instrumentation
Weigh Scales
Thermocouple Amplifiers
RTD Sensor Amplifiers
Data Acquisition
The INA317 is available in an 8-pin VSSOP surfacemount package and is specified over the TA = –40°C
to +125°C temperature range.
Device Information(1)
PART NUMBER
PACKAGE
INA317
VSSOP (8)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
V+
7
V
2
IN-
RFI Filtered Inputs
150 NŸ
A
1
RFI Filtered Inputs
150 NŸ
1
50 NŸ
A
R
G
50 NŸ
6
3
V
OUT
8
RFI Filtered Inputs
V
3
IN+
150 NŸ
A
RFI Filtered Inputs
150 NŸ
5
2
REF
INA317
4
V-
G=1+
100 NŸ
R
G
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA317
SBOS896 – NOVEMBER 2017
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
7.4 Device Functional Modes........................................ 13
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application ................................................. 14
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 21
11 Device and Documentation Support ................. 22
11.1
11.2
11.3
11.4
11.5
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
Device Support......................................................
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
24
24
25
25
12 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
November 2017
*
Initial release.
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5 Pin Configuration and Functions
DGK Package
8-Pin VSSOP
Top View
RG
1
8
RG
VIN-
2
7
V+
VIN+
3
6
VOUT
V-
4
5
REF
Pin Functions
PIN
NAME
REF
NO.
I/O
DESCRIPTION
5
I
RG
1, 8
—
Reference input. This pin must be driven by low impedance or connected to ground.
Gain setting pins. For gains greater than 1, place a gain resistor between pins 1 and 8.
V+
7
—
Positive supply
V–
4
—
Negative supply
VIN+
3
I
Positive input
VIN–
2
I
Negative input
VOUT
6
O
Output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
Supply voltage
MAX
Analog input voltage
(2)
V
(V–) – 0.3
Output short-circuit (3)
(V+) + 0.3
–40
Junction temperature, TJ
Storage temperature, Tstg
(2)
(3)
V
Continuous
Operating temperature, TA
(1)
UNIT
7
–65
150
°C
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails must be
current limited to 10 mA or less.
Short-circuit to ground.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
Machine model (MM)
±200
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
MAX
UNIT
Supply voltage
1.8
5.5
V
Specified temperature
–40
125
°C
6.4 Thermal Information
INA317
THERMAL METRIC (1)
DGK (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
169.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
62.7
°C/W
RθJB
Junction-to-board thermal resistance
90.3
°C/W
ψJT
Junction-to-top characterization parameter
7.6
°C/W
ψJB
Junction-to-board characterization parameter
88.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
for VS = 1.8 V to 5.5 V at TA = 25°C, RL = 10 kΩ, VREF = VS / 2, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT (1)
Offset voltage, RTI (2)
VOSI
±10 ±25 / G
vs temperature, TA = –40°C to 125°C
vs power supply,1.8 V ≤ VS ≤ 5.5 V
PSR
±1 ±5 / G
Long-term stability
Turnon time to specified VOSI
See
TA = –40°C to 125°C
±75 ±75 / G
μV
±0.3 ±0.5 / G
μV/°C
±5 ±15 / G
μV/V
(3)
See Typical Characteristics
Impedance
ZIN
Differential
100 || 3
ZIN
Common-mode
100 || 3
VCM
Common-mode voltage range
VO = 0 V
(V–) + 0.1
GΩ || pF
GΩ || pF
(V+) – 0.1
V
DC to 60 Hz
CMR
Common-mode rejection
VCM = (V–) + 0.1 V
to (V+) – 0.1 V, G = 1
80
90
dB
VCM = (V–) + 0.1 V
to (V+) – 0.1 V, G = 10
100
110
dB
VCM = (V–) + 0.1 V
to (V+) – 0.1 V, G = 100,
100
115
dB
VCM = (V–) + 0.1 V
to (V+) – 0.1 V, G = 1000
100
115
dB
INPUT BIAS CURRENT
Input bias current
IB
vs temperature
±70
TA = –40°C to 125°C
See Figure 26
TA = –40°C to 125°C
See Figure 28
Input offset current
IOS
vs temperature
±200
pA
pA/°C
±50
±200
pA
pA/°C
INPUT VOLTAGE NOISE
eNI
Input voltage noise
G = 100, RS = 0 Ω, f = 10 Hz
50
nV/√Hz
G = 100, RS = 0 Ω, f = 100 Hz
50
nV/√Hz
G = 100, RS = 0 Ω, f = 1 kHz
50
nV/√Hz
G = 100, RS = 0 Ω, f = 0.1 Hz to 10 Hz
iN
Input current noise
1
f = 10 Hz
μVPP
100
f = 0.1 Hz to 10 Hz
fA/√Hz
2
pAPP
GAIN
G
Gain equation
1 + (100 kΩ / RG)
Range of gain
1
V/V
1000
V/V
VS = 5.5 V, (V–) + 100 mV
≤ VO ≤ (V+) – 100 mV
Gain error
G=1
±0.01%
±0.1%
G = 10
±0.05%
±0.25%
G = 100
±0.07%
±0.25%
G = 1000
±0.25%
±0.5%
Gain vs temperature, G = 1
TA = –40°C to 125°C
±1
±5
ppm/°C
Gain vs temperature, G > 1 (4)
TA = –40°C to 125°C
±15
±50
ppm/°C
Gain nonlinearity
VS = 5.5 V, (V–) + 100 mV
≤ VO ≤ (V+) – 100 mV
Gain nonlinearity, G = 1 to 1000
RL = 10 kΩ
10
VS = 5.5 V
RL = 10 kΩ
See Figure 29
ppm
OUTPUT
Output voltage swing from rail
Capacitive load drive
(1)
(2)
(3)
(4)
50
mV
500
pF
Total VOS, referred-to-input = (VOSI) + (VOSO / G)
RTI = Referred-to-input
300-hour life test at 150°C demonstrated randomly distributed variation of approximately 1 μV
Does not include effects of external resistor RG
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Electrical Characteristics (continued)
for VS = 1.8 V to 5.5 V at TA = 25°C, RL = 10 kΩ, VREF = VS / 2, and G = 1 (unless otherwise noted)
PARAMETER
ISC
Short-circuit current
TEST CONDITIONS
MIN
Continuous to common
TYP
MAX
UNIT
–40, 5
mA
G=1
150
kHz
G = 10
35
kHz
G = 100
3.5
kHz
G = 1000
350
Hz
VS = 5 V, VO = 4-V step, G = 1
0.16
V/μs
VS = 5 V, VO = 4-V step, G = 100
0.05
V/μs
FREQUENCY RESPONSE
Bandwidth, –3 dB
SR
Slew rate
tS
Settling time to 0.01%
tS
Settling time to 0.001%
Overload recovery
VSTEP = 4 V, G = 1
VSTEP = 4 V, G = 100
VSTEP = 4 V, G = 1
VSTEP = 4 V, G = 100
50% overdrive
50
μs
400
μs
60
μs
500
μs
75
μs
REFERENCE INPUT
RIN
300
Voltage range
V–
kΩ
V+
V
1.8
5.5
V
±0.9
±2.75
V
75
μA
80
μA
POWER SUPPLY
Voltage range
IQ
Quiescent current vs temperature
Single voltage range
Dual voltage range
VIN = VS / 2
50
TA = –40°C to 125°C
TEMPERATURE RANGE
6
Specified temperature range
–40
125
°C
Operating temperature range
–40
150
°C
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6.6 Typical Characteristics
-0.10
-0.09
-0.08
-0.07
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
-25.0
-22.5
-20.0
-17.5
-15.0
-12.5
-10.0
-7.5
-5.0
-2.5
0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
22.5
25.0
Population
Population
at TA = 25°C, VS = 5 V, RL = 10 kΩ, VREF = midsupply, and G = 1, (unless otherwise noted)
Input Offset Voltage (µV)
Input Voltage Offset Drift (µV/°C)
VS = 5.5 V
VS = 5.5 V
Figure 1. Input Offset Voltage
TA = –40°C to +125°C
-0.50
-0.45
-0.40
-0.35
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
-75.0
-67.5
-60.0
-52.5
-45.0
-37.5
-30.0
-22.5
-15.0
-7.5
0
7.5
15.0
22.5
30.0
37.5
45.0
52.5
60.0
67.5
75.0
Population
Population
Figure 2. Input Voltage Offset Drift
Output Offset Voltage (µV)
Output Voltage Offset Drift (µV/°C)
VS = 5.5 V
VS = 5.5 V
Figure 3. Output Offset Voltage
TA = –40°C to +125°C
Figure 4. Output Voltage Offset Drift
0
VS = 1.8 V
-5
Noise (1 µV/div)
VOS (µV)
VS = 5 V
-10
-15
-20
-25
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Time (1 s/div)
Gain = 1
VCM (V)
Figure 5. Offset Voltage vs Common-Mode Voltage
Figure 6. 0.1-Hz to 10-Hz Noise
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩ, VREF = midsupply, and G = 1, (unless otherwise noted)
Noise (0.5 µV/div)
1000
Output Noise
100
100
Current Noise
Input Noise
10
10
2
(Input Noise) +
Total Input-Referred Noise =
(Output Noise)
2
G
1
1
0.1
Time (1 s/div)
Current Noise Density (fA/ÖHz)
Voltage Noise Density (nV/ÖHz)
1000
Gain = 100
1
10
100
1k
10k
Frequency (Hz)
Figure 8. Spectral Noise Density
Figure 7. 0.1-Hz to 10-Hz Noise
G = 1000
G = 100
G = 10
G=1
0.008
Output Voltage (1 V/div)
DC Output Nonlinearity Error (%FSR)
0.012
0.004
0
-0.004
-0.008
-0.012
0
0.5
1.0
1.5
2.0
2.5
3.0 3.5
4.0
4.5
5.0
Time (25 µs/div)
5.5
Gain = 1
VOUT (V)
VS = ±2.75 V
Figure 10. Large Signal Response
Output Voltage (1 V/div)
Output Voltage (50 mV/div)
Figure 9. Nonlinearity Error
Time (100 µs/div)
Time (10 µs/div)
Gain = 100
Gain = 1
Figure 11. Large-Signal Step Response
8
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Figure 12. Small-Signal Step Response
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩ, VREF = midsupply, and G = 1, (unless otherwise noted)
Output Voltage (50 mV/div)
10000
Time (ms)
1000
0.001%
100
0.01%
0.1%
10
1
Time (100 µs/div)
1000
100
10
Gain = 100
Gain (V/V)
Figure 14. Settling Time vs Gain
Figure 13. Small-Signal Step Response
80
G = 1000
Supply
60
G = 100
40
Gain (dB)
Supply (1 V/div)
VOUT (50 µV/div)
VOUT
G = 10
20
G=1
0
-20
-40
-60
Time (50 µs/div)
10
100
Gain = 1
10k
1k
100k
1M
Frequency (Hz)
Figure 15. Start-Up Settling Time
Figure 16. Gain vs Frequency
10
VS = ±2.75 V
8
G=1
VS = ±0.9 V
Population
CMRR (µV/V)
6
4
G = 10
2
0
-2
-4
G = 100,
G = 1000
-6
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
-8
-10
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
CMRR (µV/V)
VS = 5.5 V
Figure 17. Common-Mode Rejection Ratio
Figure 18. Common-Mode Rejection Ratio vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩ, VREF = midsupply, and G = 1, (unless otherwise noted)
160
2.5
2.0
Common-Mode Voltage (V)
140
G = 1000
CMRR (dB)
120
G = 100
100
80
60
G=1
40
G = 10
20
1.0
0
-1.0
-2.0
2.5
0
10
100k
10k
1k
100
-2.5 -2.0
0
-1.0
Frequency (Hz)
2.5
2.0
1.0
Output Voltage (V)
VS = ±2.5 V
Figure 19. Common-Mode Rejection Ratio vs Frequency
VREF = 0
All gains
Figure 20. Typical Common-Mode Range vs Output Voltage
0.9
5
Common-Mode Voltage (V)
Common-Mode Voltage (V)
0.7
4
3
2
1
0.5
0.3
0.1
-0.1
-0.3
-0.5
-0.7
-0.9
0
0
3
2
1
-0.9
5
4
-0.7
VS = 5 V
VREF = 0
All gains
VS = ±0.9 V
-0.3
0.1
-0.1
0.3
0.5
0.7
0.9
160
1.6
140
1.4
120
1.2
1.0
0.8
0.6
VREF = 0
G = 1000
100
G = 100
80
60
G = 10
40
0.4
All gains
Figure 22. Typical Common-Mode Range vs Output Voltage
1.8
+PSRR (dB)
Common-Mode Voltage (V)
Figure 21. Typical Common-Mode Range vs Output Voltage
G=1
20
0.2
0
0
0
0.2
0.4
0.5
0.8
1.0
1.2
1.4
1.6
1.8
1
VS = 1.8 V
10
100
1k
10k
100k
1M
Frequency (Hz)
Output Voltage (V)
VREF = 0
Figure 23. Typical Common-Mode Range vs Output Voltage
10
-0.5
Output Voltage (V)
Output Voltage (V)
Figure 24. Positive Power-Supply Rejection Ratio
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩ, VREF = midsupply, and G = 1, (unless otherwise noted)
1200
160
140
G = 1000
-IB
800
100
IB (pA)
-PSRR (dB)
120
80
+IB
1000
G = 100
G = 10
60
600
400
VS = ±0. 9 V
40
VS = ±2.75 V
200
G=1
20
0
0
-200
-20
0.1
10
1
100
1k
10k
-50
1M
100k
25
0
-25
50
75
125
100
150
Temperature (°C)
Frequency (Hz)
VS = 5 V
Figure 25. Negative Power-Supply Rejection Ratio
Figure 26. Input Bias Current vs Temperature
250
200
180
200
160
150
120
IOS (pA)
| IB | (pA)
140
100
80
60
100
VS = ±2.75 V
50
0
VS = ±0.9 V
40
-50
20
-100
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
-50
5.0
-25
0
VS = 5 V
50
75
125
100
150
VS = 1.8 V
Figure 28. Input Offset Current vs Temperature
Figure 27. Input Bias Current vs Common-Mode Voltage
80
(V+)
(V+) - 0.25
(V+) - 0.50
(V+) - 0.75
(V+) - 1.00
(V+) - 1.25
(V+) - 1.50
(V+) - 1.75
VS = ±2.75 V
70
VS = ±0.9 V
VS = 5 V
60
50
IQ (µA)
VOUT (V)
25
Temperature (°C)
VCM (V)
(V-) + 1.75
(V-) + 1.50
(V-) + 1.25
(V-) + 1.00
(V-) + 0.75
(V-) + 0.50
(V-) + 0.25
(V-)
40
VS = 1.8 V
30
20
125°C
25°C
-40°C
10
0
0
10
20
30
40
50
60
-50
-25
IOUT (mA)
0
25
50
75
100
125
150
Temperature (°C)
Figure 29. Output Voltage Swing vs Output Current
Figure 30. Quiescent Current vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩ, VREF = midsupply, and G = 1, (unless otherwise noted)
80
70
VS = 5 V
60
IQ (µA)
50
40
VS = 1.8 V
30
20
10
0
0
1.0
3.0
2.0
4.0
5.0
VCM (V)
Figure 31. Quiescent Current vs Common-Mode Voltage
12
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7 Detailed Description
7.1 Overview
The INA317 is a monolithic instrumentation amplifier (INA) based on the precision zero-drift OPA333 (operational
amplifier) core. The INA317 integrates laser-trimmed resistors to ensure excellent common-mode rejection and
low gain error. The combination of the zero-drift amplifier core and the precision resistors allows this device to
achieve outstanding DC precision and is designed for 3.3-V and 5-V industrial applications.
7.2 Functional Block Diagram
V+
7
V
2
IN-
RFI Filtered Inputs
150 NŸ
A
1
RFI Filtered Inputs
150 NŸ
1
50 NŸ
A
R
G
50 NŸ
6
3
V
OUT
8
RFI Filtered Inputs
V
3
IN+
150 NŸ
A
RFI Filtered Inputs
150 NŸ
5
2
REF
INA317
4
V-
G=1+
100 NŸ
R
G
Copyright © 2017, Texas Instruments Incorporated
7.3 Feature Description
The INA317 is a low-power, zero-drift instrumentation amplifier that offers accuracy. The versatile threeoperational-amplifier design and small size makes the amplifier designed for a wide range of applications. Zerodrift chopper circuitry provides DC specifications. A single external resistor sets any gain from 1 to 10,000. The
INA317 is laser trimmed for high common-mode rejection (100 dB at G ≥ 100). Typically, the INA317 operates
with power supplies as low as 1.8 V and quiescent current of 50 µA.
7.4 Device Functional Modes
7.4.1 Internal Offset Correction
INA317 internal operational amplifiers use an autocalibration technique with a time-continuous 350-kHz
operational amplifier in the signal path. The amplifier is zero-corrected every 8 µs using a proprietary technique.
Upon power up, the amplifier requires approximately 100 µs to achieve specified VOS accuracy. This design has
no aliasing or flicker noise.
7.4.2 Input Common-Mode Range
The linear input voltage range of the input circuitry of the INA317 is from approximately 0.1 V below the positive
supply voltage to 0.1 V above the negative supply. However, as a differential input voltage causes the output
voltage to increase, the output voltage swing of amplifiers A1 and A2 limits the linear input range. As a result, the
linear common-mode input range is related to the output voltage of the complete amplifier. This behavior
depends on supply voltage; see Figure 20.
Input overload conditions can produce an output voltage that appears normal. For example, if an input overload
condition drives the input amplifiers to the respective positive output swing limit, the difference voltage measured
by the output amplifier is approximately zero. The output of the INA317 is approximately 0 V even though the
inputs are overloaded.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The INA317 measures small differential voltage with high common-mode voltage that develops between the
noninverting and inverting input. The high input impedance makes the INA317 designed for a wide range of
applications. The ability to set the reference pin to adjust the functionality of the output signal offers additional
flexibility that is practical for multiple configurations.
8.2 Typical Application
Figure 32 shows the basic connections required for operation of the INA317 device. Good layout practice
mandates the use of bypass capacitors placed close to the device pins as shown.
The output of the INA317 device is referred to the output reference (REF) pin, which is normally grounded. This
connection must be low-impedance to ensure good common-mode rejection. Although 15 Ω or less of stray
resistance is tolerated while maintaining specified CMRR, small stray resistances of tens of ohms in series with
the REF pin causes noticeable degradation in CMRR.
V+
0.1 mF
7
VIN-
2
RFI Filter
150 kΩ
150 kΩ
A1
VO = G ´ (VIN+ - VIN-)
RFI Filter
1
50 kΩ
RG
G=1+
6
A3
50 kΩ
+
8
Load VO
RFI Filter
VIN+
100 kΩ
RG
150 kΩ
150 kΩ
A2
3
-
5
Ref
RFI Filter
INA317
4
0.1 mF
V-
Also drawn in simplified form:
VINRG
VIN+
VO
INA317
Ref
Copyright © 2017, Texas Instruments Incorporated
Figure 32. Basic Connections
14
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Typical Application (continued)
8.2.1 Design Requirements
The device is configured to monitor the input differential voltage when the gain of the external resistor RG sets
the input signal. The output signal references to the REF pin. The most common application is where the output
is referenced to ground when no input signal is present by connecting the REF pin to ground. When the input
signal increases, the output voltage at the OUT pin increases.
8.2.2 Detailed Design Procedure
8.2.2.1 Setting the Gain
A single external resistor (RG) that is connected between pins 1 and 8 sets the gain of the INA317. The value of
RG is selected according to Equation 1:
G = 1 + (100 kΩ / RG)
(1)
Table 1 lists several commonly-used gains and resistor values. The 100 kΩ in Equation 1 is a result of the sum
of the two internal feedback resistors (A1 and A2.) These on-chip resistors are laser trimmed to accurate absolute
values. The accuracy and temperature coefficient of these resistors are included in the gain accuracy and drift
specifications of the INA317 device.
The stability and temperature drift of the external gain setting resistor (RG) also affects gain. The contribution of
RG to gain accuracy and drift is inferred from the gain inEquation 1. Low resistor values required for high gain
make wiring resistance important. Sockets add to the wiring resistance and contribute additional gain error
(possibly an unstable gain error) in gains of approximately 100 or greater. To ensure stability, avoid parasitic
capacitance of more than a few picofarads at the RG connections. Careful matching of any parasitics on RG pins
maintains optimal CMRR over frequency.
Table 1. Commonly-Used Gains and Resistor Values
DESIRED GAIN
(1)
RG (Ω)
(1)
NEAREST 1% RG (Ω)
1
NC
2
100 k
100 k
NC
5
25 k
24.9 k
10
11.1 k
11 k
20
5.26 k
5.23 k
50
2.04 k
2.05
100
1.01 k
1k
200
502.5
499
500
200.4
200
1000
100.1
100
NC denotes no connection. When using the SPICE model, the simulation does not converge unless a
resistor is connected to the RG pins; use a large resistor value.
8.2.2.2 Internal Offset Correction
The INA317 device internal operational amplifiers use an autocalibration technique with a time-continuous 350kHz operational amplifier in the signal path. The amplifier is zero-corrected every 8 µs using a proprietary
technique. At power-up, the amplifier requires approximately 100 µs to achieve specified VOS accuracy. This
design has no aliasing or flicker noise.
8.2.2.3 Offset Trimming
Most applications require no external offset adjustment. However, apply a voltage to the REF pin to make
adjustments if necessary. Figure 33 shows an optional circuit for trimming the output offset voltage. The voltage
applied to REF pin is added at the output. The operational amplifier buffer provides low impedance at the REF
pin to preserve good common-mode rejection.
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V
V+
IN-
R
G
V
INA317
V
100 mA
½ REF200
O
Ref
IN+
OPA333
±10 mV
Adjustment Range
100
10 k
100
100 mA
½ REF200
VCopyright © 2017, Texas Instruments Incorporated
Figure 33. Optional Trimming of Output Offset Voltage
8.2.2.4 Noise Performance
The autocalibration technique used by the INA317 device results in reduced low-frequency noise, typically only
50 nV/√Hz (G = 100). The spectral noise density is shown in Figure 8. Low-frequency noise of the INA317 device
is approximately 1 µVPP measured from 0.1 Hz to 10 Hz (G = 100).
8.2.2.5 Input Bias Current Return Path
The input impedance of the INA317 device is extremely high(approximately 100 GΩ.) However, a path must be
provided for the input bias current of the inputs. This input bias current is typically ±70 pA. High-input impedance
means that this input bias current changes very little with varying input voltage.
For proper operation, input circuitry must provide a path for the input bias current. Figure 34 shows various
provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds
the common-mode range of the INA317 device, and the input amplifiers saturate. If the differential source
resistance is low, the bias current return path connects to one input (see the thermocouple example in
Figure 34). With higher source impedance, using two equal resistors provides a balanced input with possible
advantages of lower input offset voltage as a result of bias current and better high-frequency common-mode
rejection.
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Microphone,
Hydrophone,
and more
INA317
47 kΩ
47 kΩ
Thermocouple
INA317
10 kΩ
INA317
Copyright © 2017, Texas Instruments Incorporated
Figure 34. Providing an Input Common-Mode Current Path
8.2.2.6 Input Common-Mode Range
The linear input voltage range of the input circuitry of the INA317 device is from approximately 0.1 V below the
positive supply voltage to 0.1 V above the negative supply. As a differential input voltage causes the output
voltage to increase, however, the linear input range is limited by the output voltage swing of amplifiers A1 and A2.
The linear common-mode input range is related to the output voltage of the complete amplifier. This behavior
depends on supply voltage(see Figure 20 to Figure 23 in the Typical Characteristics section.)
Input overload conditions can produce an output voltage that appears normal. For example, if an input overload
condition drives both input amplifiers to the respective positive output swing limit, the difference voltage
measured by the output amplifier is near zero. The output of the INA317 is near 0 V even though both inputs are
overloaded.
8.2.2.7 Operating Voltage
The INA317 operates over a power-supply range of 1.8 V to 5.5 V (±0.9 V to ±2.75 V). Supply voltages higher
than 7 V (absolute maximum) can permanently damage the device. Parameters that vary over supply voltage or
temperature are shown in the Typical Characteristics section of this data sheet.
8.2.2.8 Low Voltage Operation
The INA317 device operates on power supplies as low as ±0.9 V. Most parameters vary only slightly throughout
this supply voltage range; see the Typical Characteristics section. Operation at very low supply voltage requires
careful attention to ensure that the input voltages remain within the linear range. Voltage swing requirements of
internal nodes limit the input common-mode range with low power supply voltage. Figure 20 to Figure 23 show
the range of linear operation for various supply voltages and gains.
8.2.2.9 Single-Supply Operation
The INA317 device can be used on single power supplies of 1.8 V to 5.5 V. Figure 35 shows a basic singlesupply circuit. The output REF pin is connected to midsupply. Zero differential input voltage demands an output
voltage of midsupply. Actual output voltage swing is limited to approximately 50 mV more than ground when the
load is referred to ground as shown. Figure 29 shows how the output voltage swing varies with output current.
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With single-supply operation, VIN+ and VIN– must be 0.1 V more than ground for linear operation. For instance,
the inverting input cannot connect to ground to measure a voltage that is connected to the noninverting input.
To show the issues affecting low voltage operation, see Figure 35. Figure 35 shows the INA317 device operating
from a single 3-V supply. A resistor in series with the low side of the bridge ensures that the bridge output
voltage is within the common-mode range of the amplifier inputs.
+3 V
3V
2 V - DV
RG
300 Ω
VO
INA317
Ref
2 V + DV
1.5 V
150 Ω
R1
(1)
Copyright © 2017, Texas Instruments Incorporated
(1)
R1 creates proper common-mode voltage only for low-voltage operation; see Single-Supply Operation.
Figure 35. Single-Supply Bridge Amplifier
8.2.2.10 Input Protection
The input pins of the INA317 device are protected with internal diodes that are connected to the power-supply
rails. These diodes clamp the applied signal to prevent the signal from damaging the input circuitry. If the input
signal voltage exceeds the power supplies by more than 0.3 V, the input signal current must be limited to less
than 10 mA to protect the internal clamp diodes. Limit the current with a series input resistor. Some signal
sources are inherently current limited and do not require limiting resistors.
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Output Voltage (1 V/div)
Output Voltage (1 V/div)
8.2.3 Application Curves
Time (25 µs/div)
Time (100 µs/div)
Gain = 1
Gain = 100
Figure 37. Large-Signal Step Response
Output Voltage (50 mV/div)
Output Voltage (50 mV/div)
Figure 36. Large Signal Response
Time (10 µs/div)
Time (100 µs/div)
Gain = 1
Gain = 100
Figure 38. Small-Signal Step Response
Figure 39. Small-Signal Step Response
9 Power Supply Recommendations
The minimum power supply voltage for INA317 is 1.8 V and the maximum power supply voltage is 5.5 V. For
optimum performance, 3.3 V to 5 V is recommended. TI recommends adding a bypass capacitor at the input to
compensate for the layout and power supply source impedance.
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10 Layout
10.1 Layout Guidelines
TI recommends paying attention to good layout practices. Keep traces short and use a printed-circuit-board
(PCB) ground plane with surface-mount components placed as close to the device pins as possible. Place a 0.1µF bypass capacitor as close as possible the supply pins. Apply these guidelines throughout the analog circuit to
improve performance and reduce electromagnetic interference (EMI) susceptibility.
Instrumentation amplifiers vary in the susceptibility to radio-frequency interference (RFI). RFI is identified as a
variation in offset voltage or DC signal levels with changes in the interfering RF signal. The INA317 device is
designed to minimize susceptibility to RFI by incorporating passive RC filters with an 8-MHz corner frequency at
the VIN+ and VIN– inputs. As a result, the INA317 device demonstrates low sensitivity compared to previous
generation devices. However, strong RF fields can cause varied offset levels and may require additional
shielding.
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10.2 Layout Example
+V
C2
RG
-IN
OUT
±VS
INA317
R3
REF
RG
+VS
R2
+IN
R1
C1
Ground plane
removed at gain
resistor to minimize
parasitic capacitance
-V
Use ground pours for
shielding the input
signal pairs
R3
+V
GND
R1
Input traces routed
adjacent to each other
1
RG
RG
8
±IN
+VS
7
+IN
OUT
6
REF
5
±IN
2
+IN
3
4
-VS
R2
C2
GND
OUT
Low-impedance
connection for
reference terminal
C1
-V
Place bypass
capacitors as close to
IC as possible
Copyright © 2017, Texas Instruments Incorporated
Figure 40. INA317 Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI (Free Download Software)
Using TINA-TI SPICE-Based Analog Simulation Program With The INA317
TINA is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully functional version of the TINA software, preloaded with a library of macromodels in addition to a range
of both passive and active models. It provides all the conventional DC, transient, and frequency domain analysis
of SPICE as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways.
Virtual instruments offer users the ability to select input waveforms and probe circuit nodes, voltages, and
waveforms, creating a dynamic quick-start tool.
Figure 41 and Figure 42 show example TINA-TI circuits for the INA317 device that can be used to develop,
modify, and assess the circuit design for specific applications. Links to download these simulation files are given
below.
NOTE
These files require that either the TINA software (from DesignSoft) or TINA-TI software be
installed. Download the free TINA-TI software from the TINA-TI folder.
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Device Support (continued)
VoA1
Half of matched
monolithic dual
NPN transistors
(example: MMDT3904)
Vout
8
Ref
RG V+
5
+
3
7
VCC
VCC
Vref+
Vref+
VM1
U5 OPA369
++
6
Vdiff
Vref+
Half of matched
monolithic dual
NPN transistors
(example: MMDT3904)
-
R8 10k
Out
U1 OPA335
VCC
4
5
1
Optional buffer for driving
SAR converters with
sampling systems of ³ 33 kHz.
VCC
+
+
V
U1 INA317
C1 1n
1
+
4
RG V-
Vref+
Input I 10n
2
-
R3 14k
2 _
3
VoA2
Rset 2.5M
3
uC Vref/2 2.5
1
+
+
4
5
U6 OPA369
VCC
Vref+
V1 5
uC Vref/2 2.5
2
-
Copyright © 2017, Texas Instruments Incorporated
(1) The following link launches the TI logarithmic amplifiers web page: Logarithmic Amplifier Products Home Page
(2)
Temperature compensation of logging transistors is not shown.
(3)
For monolithic logarithmic amplifiers (such as LOG112 or LOG114), see the link in Note 1.
Figure 41. Low-Power Log Function Circuit for Portable Battery-Powered Systems
(Example Glucose Meter)
To download a compressed file that contains the TINA-TI simulation file for this circuit, click the following link:
Log Circuit.
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Device Support (continued)
3V
R
1
2k
RWa
3
EMU21 RTD3
-
Pt100 RTD
VT+
U2
OPA333
RWb
3
+
RTD+
VT 25
+
2 _
3V
VT-
RTD-
Mon+
+
U1 INA317
V
Out
GAIN
Mon-
100 k
RWc
4
Temp (°C)
(Volts = °C)
1
R
4
RG V-
R
ZERO
100 k
8
3
Ref
RG V+
5
+
7
V
V
DIFF
PGA112
MSP430
6
REF+
3V
VRTD
RWd
3
RTD Resistance
(Volts = Ohms)
+
+
A
I
A
REF1
I
REF2
3V
V
U1 REF3212
EN
REF
V
3V
REF
+
In
OUTS
GNDF GNDS
C
7
470 nF
V
Use BF861A
S
OUTF
3V
+
T3 BF256A
OPA3331 OPA333
Use BF861A
3V
T1 BF256A
+
G
REF
+
U3
OPA333
-
V4 3
R
R
SET2
SET1
2.5 k
2.5 k
Copyright © 2017, Texas Instruments Incorporated
RWa, RWb, RWc, and RWd simulate wire resistance. These resistors are included to show the 4-wire sense technique immunity to line
mismatches. This method assumes the use of a 4-wire RTD.
Figure 42. 4-Wire, 3-V Conditioner for a PT100 RTD With Programmable Gain Acquisition System
To download a compressed file that contains the TINA-TI simulation file for this circuit, click the following link:
PT100 RTD.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Precision, Low-Noise, Rail-to-Rail Output, 36-V, Zero-Drift Operational Amplifiers
• 50 µV VOS, 0.25 µV/°C, 35 µA CMOS OPERATIONAL AMPLIFIERS Zerø-Drift Series
• 4ppm/°C, 100 µA, SOT23-6 SERIES VOLTAGE REFERENCE
• Circuit Board Layout Techniques
11.3 Trademarks
All trademarks are the property of their respective owners.
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11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
21-Feb-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
INA317IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
I317
INA317IDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
I317
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
21-Feb-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
INA317IDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
INA317IDGKT
VSSOP
DGK
8
250
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
INA317IDGKR
VSSOP
DGK
8
2500
366.0
364.0
50.0
INA317IDGKT
VSSOP
DGK
8
250
366.0
364.0
50.0
Pack Materials-Page 2
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