Texas Instruments | INA20x High-Side Measurement Current-Shunt Monitor With Open-Drain Comparator and Reference (Rev. E) | Datasheet | Texas Instruments INA20x High-Side Measurement Current-Shunt Monitor With Open-Drain Comparator and Reference (Rev. E) Datasheet

Texas Instruments INA20x High-Side Measurement Current-Shunt Monitor With Open-Drain Comparator and Reference (Rev. E) Datasheet
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INA200, INA201, INA202
SBOS374E – NOVEMBER 2006 – REVISED SEPTEMBER 2017
INA20x High-Side Measurement Current-Shunt Monitor
With Open-Drain Comparator and Reference
1 Features
3 Description
•
•
The INA200, INA201, and INA202 devices are highside current-shunt monitors with voltage output and
integrated comparator. The INA20x devices can
sense drops across shunts at common-mode
voltages from –16 V to 80 V. The INA20x series is
available with three output voltage scales: 20 V/V, 50
V/V, and 100 V/V, with a bandwidth up to 500-kHz.
1
•
•
•
•
•
•
•
•
Complete Current Sense Solution
Three Gain Options Available:
– INA200 = 20 V/V
– INA201 = 50 V/V
– INA202 = 100 V/V
0.6-V Internal Voltage Reference
Internal Open-Drain Comparator
Latching Capability on Comparator
Common-Mode Range: –16 V to 80 V
High Accuracy: 3.5% Maximum Error Over
Temperature
Bandwidth: 500 kHz (INA200)
Quiescent Current: 1800 μA (Maximum)
Packages: SOIC-8, VSSOP-8
The INA200, INA201, and INA202 devices
incorporate an open-drain comparator and internal
reference providing a 0.6-V threshold. External
dividers set the current trip point. The comparator
includes a latching capability, that can be made
transparent by grounding (or leaving open) the
RESET pin.
The INA200, INA201, and INA202 devices operate
from a single 2.7-V to 18-V supply, drawing a
maximum of 1800 μA of supply current. Package
options include the very small VSSOP-8 and the
SOIC-8. All versions are specified over the extended
operating temperature range of –40°C to +125°C.
2 Applications
•
•
•
•
•
•
•
Notebook Computers
Cell Phones
Telecom Equipment
Automotive
Power Management
Battery Chargers
Welding Equipment
Device Information(1)
PART NUMBER
INA200
INA201
INA202
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
1
INA200 (G = 20)
INA201 (G = 50)
INA202 (G = 100)
VS
2 OUT
G
VIN+
8
VIN-
7
0.6-V
Reference
3 CMPIN
Comparator
4
CMPOUT 6
GND
RESET 5
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA200, INA201, INA202
SBOS374E – NOVEMBER 2006 – REVISED SEPTEMBER 2017
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
7
7
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: Current-Shunt Monitor .....
Electrical Characteristics: Comparator......................
Electrical Characteristics: General ............................
Typical Characteristics ..............................................
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 19
8
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application ................................................. 22
9
Power Supply Recommendations...................... 23
9.1 Output vs Supply Ramp Considerations ................. 23
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 25
11 Device and Documentation Support ................. 26
11.1
11.2
11.3
11.4
11.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
12 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (October 2015) to Revision E
Page
•
Reformatted Thermal Information table note ......................................................................................................................... 4
•
Corrected typo in Voltage Output section in Electrical Characteristics table ......................................................................... 6
•
Added text to Comparator subsection in Feature Description section ................................................................................. 14
•
Added Figure 31 to Feature Description section .................................................................................................................. 18
•
Added Output vs Supply Ramp Considerations subsection in Feature Description section................................................ 23
•
Added Figure 36, Figure 37, and Figure 38 ......................................................................................................................... 23
Changes from Revision C (October 2010) to Revision D
•
Page
Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................... 4
Changes from Revision B (October, 2007) to Revision C
Page
•
Revised front-page figure ....................................................................................................................................................... 1
•
Changed title of data sheet..................................................................................................................................................... 1
•
Updated document format to current standards..................................................................................................................... 1
2
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SBOS374E – NOVEMBER 2006 – REVISED SEPTEMBER 2017
5 Pin Configuration and Functions
DGK and D Packages
8-Pin VSSOP and SOIC
Top View
VS
1
8
VIN+
OUT
2
7
VIN-
CMPIN
3
6
CMPOUT
GND
4
5
RESET
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
CMPIN
3
Analog input
CMPOUT
6
Analog
output
Comparator output
GND
4
Analog
Ground
OUT
2
Analog
output
Output voltage
RESET
5
Analog input
Comparator reset pin, active low
VIN–
7
Analog input
Connect to shunt low side
VIN+
8
Analog input
Connect to shunt high side
VS
1
Analog
Comparator input
Power supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
2.7
18
V
Differential (VIN+) – (VIN–)
–18
18
V
Common-mode (2)
–16
80
V
Comparator analog input and reset pins (2)
GND – 0.3
(Vs) + 0.3
V
(2)
GND – 0.3
(Vs) + 0.3
V
GND – 0.3
18
V
5
mA
Supply voltage, Vs
Current-shunt monitor
analog inputs, VIN+, VIN–
Analog output, OUT
Comparator output, OUT (2)
Input current into any pin (2)
Operating temperature
–55
150
°C
Junction temperature
–65
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
This voltage may exceed the ratings shown if the current at that pin is limited to 5 mA.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±4000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
–16
12
80
Operating supply voltage
2.7
12
18
V
Operating free-air temperature
–40
25
125
°C
VCM
Common-mode input voltage
VS
TA
UNIT
V
6.4 Thermal Information
INA20x
THERMAL METRIC (1)
D (SOIC)
DGK (SOIC)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
110.5
162.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
50.4
37.7
°C/W
RθJB
Junction-to-board thermal resistance
52.7
82.9
°C/W
ψJT
Junction-to-top characterization parameter
7.8
1.3
°C/W
ψJB
Junction-to-board characterization parameter
51.9
81.4
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics: Current-Shunt Monitor
at TA = 25°C, VS = 12 V, VCM = 12 V, VSENSE = 100 mV, RL = 10 kΩ to GND, RPULL-UP = 5.1 kΩ connected from CMPOUT to VS,
and CMPIN = GND, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.15
(VS – 0.25) / Gain
UNIT
INPUT
VSENSE
Full-scale sense input voltage
VSENSE = VIN+ – VIN–
VCM
Common-mode input range
TA = –40°C to 125°C
–16
VIN+ = –16 V to 80 V
80
CMR
Common-mode rejection
VIN+ = 12 V to 80 V, TA = –40°C to 125°C
100
TA = 25°C
Offset voltage, RTI (1)
VOS
80
100
V
dB
123
±0.5
V
dB
±2.5
mV
TA = 25°C to 125°C
±3
mV
TA = –40°C to 25°C
±3.5
mV
dVOS/dT
Offset voltage, RTI, vs
temperature
TMIN to TMAX, TA = –40°C to 125°C
PSR
Offset voltage, RTI, vs power
supply
VOUT = 2 V, VIN+ = 18 V, 2.7 V, TA = –40°C to
125°C
2.5
100
μV/V
IB
Input bias current, VIN– pin
TA = –40°C to 125°C
±9
±16
μA
(1)
5
μV/°C
Offset is extrapolated from measurements of the output at 20-mV and 100-mV VSENSE.
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Electrical Characteristics: Current-Shunt Monitor (continued)
at TA = 25°C, VS = 12 V, VCM = 12 V, VSENSE = 100 mV, RL = 10 kΩ to GND, RPULL-UP = 5.1 kΩ connected from CMPOUT to VS,
and CMPIN = GND, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT (VSENSE ≥ 20 mV)
G
Gain
INA200
20
V/V
INA201
50
V/V
INA202
100
VSENSE = 20 mV to 100 mV
Gain error
±0.2%
VSENSE = 20 mV to 100 mV, TA = –40°C to
125°C
±2%
VSENSE = 120 mV, VS = 16 V
RO
Total output error (2)
VSENSE = 120 mV, VS = 16 V, TA = –40°C to
125°C
Nonlinearity error (3)
VSENSE = 20 mV to 100 mV
±0.75%
±2.2%
±3.5%
±0.002%
Output impedance
Maximum capacitive load
V/V
±1%
No sustained oscillation
1.5
Ω
10
nF
300
mV
OUTPUT (VSENSE < 20 mV) (4)
Output
VOLTAGE OUTPUT
INA200, INA201,
INA202
–16 V ≤ VCM < 0 V
INA200
0 V ≤ VCM ≤ VS, VS =
5V
0.4
V
INA201
0 V ≤ VCM ≤ VS, VS =
5V
1
V
INA202
0 V ≤ VCM ≤ VS, VS =
5V
2
V
INA200, INA201,
INA202
VS < VCM ≤ 80 V
300
mV
(5)
Output swing to the positive rail
VIN– = 11 V, VIN+ = 12 V, TA = –40°C to 125°C
(Vs) – 0.15
(Vs) – 0.25
V
Output swing to GND (6)
VIN– = 0 V, VIN+ = –0.5 V, TA = –40°C to 125°C
(GND) + 0.004
(GND) + 0.05
V
FREQUENCY RESPONSE
BW
Bandwidth
Phase margin
SR
INA200
CLOAD = 5 pF
500
kHz
INA201
CLOAD = 5 pF
300
kHz
INA202
CLOAD = 5 pF
200
kHz
CLOAD < 10 nF
Slew rate
Settling time (1%)
VSENSE = 10 mVPP to 100 mVPP,
CLOAD = 5 pF
40
°C
1
V/μs
2
μs
40
nV/√Hz
NOISE, RTI
Voltage noise density
(2)
(3)
(4)
(5)
(6)
6
Total output error includes effects of gain error and VOS.
Linearity is best fit to a straight line.
For details on this region of operation, see Accuracy Variations section in Device Functional Modes.
See Figure 8.
Specified by design.
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6.6 Electrical Characteristics: Comparator
at TA = 25°C, VS = 12 V, VCM = 12 V, VSENSE = 100 mV, RL = 10 kΩ to GND, and RPULL-UP = 5.1 kΩ connected from CMPOUT to
VS, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = 25°C
590
608
620
mV
TA = –40°C to 125°C
586
625
mV
OFFSET VOLTAGE
Threshold
Hysteresis (1)
TA = –40°C to 85°C
–8
mV
INPUT BIAS CURRENT (2)
Input bias current, CMPin PIN
0.005
Input bias current, CMPin PIN, vs temperature
TA = –40°C to 125°C
10
nA
15
nA
INPUT VOLTAGE RANGE
Input voltage range, CMPin PIN
0 V to VS – 1.5 V
V
OUTPUT (OPEN-DRAIN)
Large-signal differential voltage gain
CMP VOUT 1 V to 4 V,
RL ≥ 15 kΩ connected to 5 V
ILKG
High-level leakage current (3) (4)
VID = 0.4 V, VOH = VS
0.0001
1
μA
VOL
Low-level output voltage (3)
VID = –0.6 V, IOL = 2.35 mA
220
300
mV
RL to 5 V, CL = 15 pF, 100-mV Input
Step with 5-mV overdrive
1.3
200
V/mV
RESPONSE TIME
Response time (5)
μs
RESET
RESET threshold (6)
1.1
Logic input impedance
Minimum RESET pulse width
RESET propagation delay
(1)
(2)
(3)
(4)
(5)
(6)
V
2
MΩ
1.5
μs
3
μs
Hysteresis refers to the threshold (the threshold specification applies to a rising edge of a noninverting input) of a falling edge on the
noninverting input of the comparator; refer to Figure 1.
Specified by design.
VID refers to the differential voltage at the comparator inputs.
Open-drain output can be pulled to the range of 2.7 to 18 V, regardless of VS.
The comparator response time specified is the interval between the input step function and the instant when the output crosses 1.4 V.
The RESET input has an internal 2 MΩ (typical) pull-down. Leaving RESET open results in a LOW state, with transparent comparator
operation.
6.7 Electrical Characteristics: General
at TA = 25°C, VS = 12 V, VCM = 12 V, VSENSE = 100 mV, RL = 10 kΩ to GND, RPULL-UP = 5.1 kΩ connected from CMPOUT to VS,
and CMPIN = 1 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
18
V
1350
1800
μA
1850
μA
POWER SUPPLY
VS
IQ
Operating power supply
Quiescent current
TA = –40°C to 125°C
2.7
VOUT = 2 V
VSENSE = 0 mV, TA = –40°C to 125°C
Comparator power-on reset
threshold (1)
1.5
V
TEMPERATURE
θJA
(1)
Specified temperature
–40
125
°C
Operating temperature
–55
150
°C
Storage temperature
–65
150
Thermal resistance
°C
VSSOP-8 Surface-Mount
200
°C/W
SOIC-8
150
°C/W
The INA200, INA201, and INA202 are designed to power-up with the comparator in a defined reset state as long as RESET is open or
grounded. The comparator is in reset as long as the power supply is below the voltage shown here. The comparator assumes a state
based on the comparator input above this supply voltage. If RESET is high at power-up, the comparator output comes up high and
requires a reset to assume a low state, if appropriate.
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VTHRESHOLD
0.592V 0.6V
Input Voltage
Hysteresis = VTHRESHOLD - 8mV
Figure 1. Typical Comparator Hysteresis
8
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6.8 Typical Characteristics
at TA = 25°C, VS = 12 V, VIN+ = 12 V, and VSENSE = 100 mV, (unless otherwise noted)
45
G = 50
35
30
Gain (dB)
30
G = 100
40
G = 50
35
Gain (dB)
45
CLOAD = 1000pF
G = 100
40
G = 20
25
20
G = 20
25
20
15
15
10
10
5
5
10k
100k
10k
1M
100k
Frequency (Hz)
Figure 2. Gain vs Frequency
Figure 3. Gain vs Frequency
20
140
18
130
Common-Mode and
Power-Supply Rejection (dB)
100V/V
16
14
VOUT (V)
1M
Frequency (Hz)
50V/V
12
10
8
20V/V
6
4
120
CMR
110
100
90
PSR
80
70
60
50
2
40
0
100
20
200
300
400
500
600
700
800
900
10
100
1k
VDIFFERENTIAL (mV)
100k
Frequency (Hz)
Figure 4. Gain Plot
Figure 5. Common-Mode and Power-Supply Rejection vs
Frequency
4.0
0.1
3.5
0.09
0.08
3.0
Output Error (% )
Output Error
(% error of the ideal output value)
10k
2.5
2.0
1.5
1.0
0.07
0.06
0.05
0.04
0.03
0.02
0.5
0.01
0
0
50
100 150
200
250 300
350 400 450 500
0
-16 -12 -8 -4
VSENSE (mV)
0
4
8
12 16 20
...
76 80
Common-Mode Voltage (V)
Figure 6. Output Error vs VSENSE
Figure 7. Output Error vs Common-Mode Voltage
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Typical Characteristics (continued)
at TA = 25°C, VS = 12 V, VIN+ = 12 V, and VSENSE = 100 mV, (unless otherwise noted)
3.5
12
11
VS = 12V
10
2.5
+25°C
8
-40°C
+125°C
7
6
VS = 3V
5
Sourcing Current
+25°C
4
-40°C
Output stage is designed
to source current. Current
sinking capability is
approximately 400mA.
3
2
1
+125°C
0
0
IQ (mA)
Output Voltage (V)
3.0
Sourcing Current
9
2.0
1.5
1.0
0.5
0
5
10
20
15
25
30
0
2
1
Output Current (mA)
IQ (mA)
1.50
1.25
VS = 12V
1.00
VS = 2.7V
VSENSE = 0mV
7
6
8
0.75
10
-40°C
30
+25°C
26
+125°C
22
18
14
10
6
0
4
8
12 16 20 24 28 32 36
2.5 3.5
4.5
VCM (V)
5.5 6.5
7.5
8.5
9.5 10.5 11.5 17
18
Supply Voltage (V)
Figure 10. Quiescent Current vs Common-Mode Voltage
Figure 11. Output Short-Circuit Current vs Supply Voltage
G = 20
Output Voltage (50mV/div)
Output Voltage (500mV/div)
G = 20
VSENSE = 20mV to 30mV
VSENSE = 20mV to 110mV
Time (2ms/div)
Time (2ms/div)
Figure 12. Step Response
10
9
Figure 9. Quiescent Current vs Output Voltage
Output Short-Circuit Current (mA)
VS = 2.7V
VS = 12V
0.50
-16 -12 -8 -4
5
34
VSENSE = 100mV
1.75
4
Output Voltage (V)
Figure 8. Positive Output Voltage Swing vs Output Current
2.00
3
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Figure 13. Step Response
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Typical Characteristics (continued)
at TA = 25°C, VS = 12 V, VIN+ = 12 V, and VSENSE = 100 mV, (unless otherwise noted)
G = 50
Output Voltage (50mV/div)
Output Voltage (100mV/div)
G = 20
VSENSE = 90mV to 100mV
VSENSE = 20mV to 30mV
Time (2ms/div)
Time (5ms/div)
Figure 14. Step Response
Figure 15. Step Response
G = 50
Output Voltage (1V/div)
Output Voltage (100mV/div)
G = 50
VSENSE = 90mV to 100mV
VSENSE = 20mV to 110mV
Time (5ms/div)
Time (5ms/div)
Figure 16. Step Response
Figure 17. Step Response
600
G = 100
Output Voltage (2V/div)
500
VOL (mV)
400
300
200
100
0
VSENSE = 20mV to 110mV
0
1
2
3
4
5
6
ISINK (mA)
Time (10ms/div)
Figure 18. Step Response
Figure 19. Comparator VOL vs ISINK
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Typical Characteristics (continued)
at TA = 25°C, VS = 12 V, VIN+ = 12 V, and VSENSE = 100 mV, (unless otherwise noted)
600
602
Comparator Trip Point (mV)
599
Reset Voltage (mV)
598
597
596
595
594
593
592
601
600
599
598
597
591
596
590
2
4
6
8
10
12
14
16
18
-50
0
-25
Supply Voltage (V)
Figure 20. Comparator Trip Point vs Supply Voltage
50
75
100
125
Figure 21. Comparator Trip Point vs Temperature
200
1.2
175
1.0
Reset Voltage (V)
Propagation Delay (ns)
25
Temperature (°C)
150
125
100
75
0.8
0.6
0.4
0.2
50
0
0
20
40
60
80
100 120 140
160 180
2
200
4
Overdrive Voltage (mV)
6
8
10
12
14
16
18
Supply Voltage (V)
Figure 22. Comparator Propagation Delay vs Overdrive
Voltage
Figure 23. Comparator Reset Voltage vs Supply Voltage
300
Propagation Delay (ns)
275
Input
200mV/div
250
225
200
175
Output
2V/div
150
125
-50
-25
0
25
50
75
100
125
VOD = 5mV
2ms/div
Temperature (°C)
Figure 24. Comparator Propagation Delay vs Temperature
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Figure 25. Comparator Propagation Delay
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7 Detailed Description
7.1 Overview
The INA200, INA201, and INA202 devices are high-side current-shunt monitors with voltage output. The INA20x
devices can sense drops across shunts at common-mode voltages from –16 V to 80 V. The INA200–INA202
devices are available with three output voltage scales: 20 V/V, 50 V/V, and 100 V/V, with up to 500-kHz
bandwidth. The INA200, INA201, and INA202 devices incorporate an open-drain comparator and internal
reference providing a 0.6-V threshold. External dividers set the current trip point. The comparator includes a
latching capability, that can be made transparent by grounding (or leaving open) the RESET pin. The INA200,
INA201, and INA202 devices operate from a single 2.7 to 18-V supply, drawing a maximum of 1800 μA of supply
current. Package options include the very small MSOP-8 and the SO-8. All versions are specified over the
extended operating temperature range of –40°C to +125°C.
7.2 Functional Block Diagram
VS
VIN+
OUT
G
VIN-
0.6-V
Reference
CMPIN
Comparator
GND
CMPOUT
RESET
7.3 Feature Description
7.3.1 Basic Connections
Figure 26 shows the basic connections of the INA20x devices. The input pins (VIN+ and VIN–) must be connected
as closely as possible with Kelvin connections to the shunt resistor to minimize any resistance in series with the
shunt resistance.
Power-supply bypass capacitors are required for stability. Applications with noisy or high-impedance power
supplies may require additional decoupling capacitors to reject power-supply noise. Connect bypass capacitors
close to the device pins.
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RSHUNT
3m
Load Supply
-18 V to 80 V
Load
5-V Supply
INA200
(G = 20)
1
VS
2 OUT
CBYPASS 0.01 µF
G
R1
VIN+
8
VIN-
7
CMPOUT
6
RPULLUP
4.7 k
0.6-V
Reference
3 CMPIN
Comparator
R2
4 GND
RESET 5
Transparent / Reset
SW
Latch
Copyright © 2017, Texas Instruments Incorporated
Figure 26. INA200 Basic Connections
7.3.2 Selecting RS
The selected value for the shunt resistor, RS, depends on the application and is a compromise between smallsignal accuracy and maximum permissible voltage loss in the measurement line. High values of RS provide better
accuracy at lower currents by minimizing the effects of offset, while low values of RS minimize voltage loss in the
supply line. For most applications, using an RS value that provides a full-scale shunt voltage range of 50 mV to
100 mV results in the best performance. Maximum input voltage for accurate measurements is 500 mV, but
output voltage is limited by supply.
7.3.3 Comparator
The INA200, INA201, and INA202 devices incorporate an open-drain comparator. This comparator typically has
2 mV of offset and a 1.3-μs (typical) response time. The output of the comparator latches and is reset through
the RESET pin; see Figure 28.
When Vs and RESET are different, TI recommends adding a low-pass filter (LPF) on the RESET pin to avoid
comparator behavior inconsistent with the data sheet. For instance, with a 12-V supply and a 3.3-V RESET, a
rise time of 400 ns is appropriate. Similarly, with an 18-V supply and a 2.7-V RESET, a 1-µs rise time is
appropriate; see Figure 31.
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RSHUNT << RFILTER
3m
VSUPPLY
Load
INA200-INA202
RFILTER < 100
RFILTER < 100
CFILTER
VS
VIN+
OUT
G
VIN-
0.6-V
Reference
f-3dB
CMPIN
Comparator
CMPOUT
f-3dB =
1
2Œ(2RFILTER)CFILTER
RESET
GND
SO-14, TSSOP-14
Copyright © 2017, Texas Instruments Incorporated
Figure 27. Input Filter (Gain Error: 1.5% to 2.8%)
0.6V
VIN
0V
CMPOUT
RESET
Figure 28. Comparator Latching Capability
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Shunt
Option 1
Shunt
Option 2
Supply
R3
To VIN+
To VIN-
To VIN+
To VIN-
4.5 V to 5.5 V
R4
Q1
2N3904
Load
INA200 (G = 20)
INA201 (G = 50)
INA202 (G = 100)
1
VS
To VIN+
2 OUT
G
VIN+
8
VIN-
7
CMPOUT
6
RESET
5
Shunt
Option 3
From
Shunt Option
1, 2, or 3
To VIN-
0.6-V
Reference
R1
3 CMPIN
Comparator
R2
4
GND
RESET
Copyright © 2017, Texas Instruments Incorporated
(1)
Q1 cascodes the comparator output to drive a high-side FET (the 2N3904) shown is good up to 60 V. The shunt can
be located in any one of the three locations shown. The latching capability must be used in shutdown applications to
prevent oscillation at the trip point.
Figure 29. High-Side Switch Overcurrent Shutdown
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RSHUNT
Supply
4.5 V to 5.5 V
1
INA200 (G = 20)
INA201 (G = 50)
INA202 (G = 100)
VS
2 OUT
VIN+
8
VIN-
7
CMPOUT
6
G
R5 2.2 k
0.6-V
Reference
R3
3 CMPIN
Comparator
R4
4
RESET 5
GND
INA200 (G = 20)
INA201 (G = 50)
INA202 (G = 100)
1
VS
2 OUT
R6 2.2 k
VIN+
8
VIN-
7
CMPOUT
6
G
0.6-V
Reference
R3
3 CMPIN
Comparator
CMPOUT
R4
R7 200 k
4
RESET 5
GND
Copyright © 2017, Texas Instruments Incorporated
(1)
It is possible to set different limits for each direction.
Figure 30. Bidirectional Overcurrent Comparator
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VS
VIN+
OUT
G
VIN-
0.6-V
Reference
CMPIN
Comparator
GND
CMPOUT
RESET 5
Rf
Controller
Cf
GND
Figure 31. Filter on RESET Pin
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7.4 Device Functional Modes
7.4.1 Input Filtering
An obvious and straightforward location for filtering is at the output of the INA20x series; however, this location
negates the advantage of the low output impedance of the internal buffer. The only other option for filtering is at
the input pins of the INA20x devices, which is complicated by the internal 5 kΩ + 30% input impedance. This is
shown in Figure 27. Using the lowest possible resistor values minimizes the initial shift in gain and effects of
tolerance. The effect on initial gain is shown in Equation 1:
Gain Error % = 100 - 100 ´
5kW
5kW + RFILT
(1)
Total effect on gain error can be calculated by replacing the 5-kΩ term with 5 kΩ – 30%, (or 3.5 kΩ) or 5 kΩ +
30% (or 6.5 kΩ). The tolerance extremes of RFILT can be inserted into the equation. If a pair of 100-Ω 1%
resistors are used on the inputs, the initial gain error equals 1.96%. Worst-case tolerance conditions always
occur at the lower excursion of the internal 5-kΩ resistor (3.5 kΩ), and the higher excursion of RFILT – 3% in this
case.
The specified accuracy of the INA20x devices must then be combined in addition to these tolerances. While this
discussion treated accuracy worst-case conditions by combining the extremes of the resistor values, it is
appropriate to use geometric mean or root sum square calculations to total the effects of accuracy variations.
7.4.2 Accuracy Variations as a Result of VSENSE and Common-Mode Voltage
The accuracy of the INA200, INA201, and INA202 current shunt monitors is a function of two main variables:
VSENSE (VIN+ – VIN–), common-mode voltage, (VCM), relative to the supply voltage (VS). VCM is expressed as (VIN+
+ VIN–) / 2; however, in practice, VCM is seen as the voltage at VIN+ because the voltage drop across VSENSE is
typically small.
This section addresses the accuracy of these specific operating regions:
• Normal Case 1: VSENSE ≥ 20 mV, VCM ≥ VS
• Normal Case 2: VSENSE ≥ 20 mV, VCM < VS
• Low VSENSE Case 1: VSENSE < 20 mV, –16 V ≤ VCM < 0
• Low VSENSE Case 2: VSENSE < 20 mV, 0 V ≤ VCM ≤ VS
• Low VSENSE Case 3: VSENSE < 20 mV, VS < VCM ≤ 80 V
7.4.2.1 Normal Case 1: VSENSE ≥ 20 mv, VCM ≥ VS
This region of operation provides the highest accuracy. Here, the input offset voltage is characterized and
measured using a two-step method. First, the gain is determined by Equation 2.
VOUT1 - VOUT2
G=
100mV - 20mV
where
•
•
VOUT1 = output voltage with VSENSE = 100 mV
VOUT2 = output voltage with VSENSE = 20 mV
(2)
Then the offset voltage is measured at VSENSE = 100 mV, and referred to the input (RTI) of the current shunt
monitor, as shown in Electrical Characteristics: Current-Shunt Monitor.
VOUT1
VOSRTI (Referred-To-Input) =
- 100mV
G
(3)
In the Typical Characteristics, Figure 7 shows the highest accuracy for the this region of operation. In this plot,
VS = 12 V. For VCM ≥ 12 V, the output error is at the minimum value. This case creates the VSENSE ≥ 20-mV
output specifications in Electrical Characteristics: Current-Shunt Monitor .
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Device Functional Modes (continued)
7.4.2.2 Normal Case 2: VSENSE ≥ 20 mv, VCM < VS
This region of operation is less accurate than normal case 1 as a result of the common-mode operating area in
which the part functions, as shown in the Figure 7 curve (Figure 7). As noted, for this graph VS = 12 V; for VCM <
12 V, the output error increases as VCM decreases to less than 12 V, with a typical maximum error of 0.005% at
the most negative VCM = –16 V.
7.4.2.3 Low VSENSE Case 1: VSENSE < 20 mV, –16 V ≤ VCM < 0
and Low VSENSE Case 3: VSENSE < 20 mV, VS < VCM ≤ 80 V
Although the INA200 family of devices are not designed for accurate operation in these regions, some
applications are exposed to these conditions. For example, when monitoring power supplies that are switched on
and off while VS is still applied to the INA20x devices, it is important to know what the behavior of the devices is
in these regions.
As VSENSE approaches 0 mV, in these VCM regions, the accuracy of the device output degrades. A larger-thannormal offset can appear at the current shunt monitor output with a typical maximum value of VOUT = 300 mV for
VSENSE = 0 mV. As VSENSE approaches 20 mV, VOUT returns to the expected output value with accuracy as
shown in Electrical Characteristics: Current-Shunt Monitor. Figure 32 shows this effect using the INA202 (gain =
100).
2.0
1.8
1.6
VOUT (V)
1.4
1.2
Actual
1.0
0.8
Ideal
0.6
0.4
0.2
0
0
2
4
6
8
10
12
14
16
18
20
VSENSE (mV)
Figure 32. Example For Low VSENSE Cases 1 and 3 (INA202, Gain = 100)
7.4.2.4 Low VSENSE Case 2: VSENSE < 20 mV, 0 V ≤ VCM ≤ VS
This region of operation is the least accurate for the INA20x family. To achieve the wide input common-mode
voltage range, these devices use two op amp front ends in parallel. One op amp front end operates in the
positive input common-mode voltage range, and the other in the negative input region. For this case, neither of
these two internal amplifiers dominates and overall loop gain is low. Within this region, VOUT approaches voltages
close to linear operation levels for normal case 2. This deviation from linear operation becomes greatest the
closer VSENSE approaches 0 V. Within this region, as VSENSE approaches 20 mV, device operation is closer to that
is described in normal case 2. Figure 33 shows this behavior for the INA202. The VOUT maximum peak for this
case is tested by maintaining a constant VS, setting VSENSE equal to 0 mV and sweeping VCM from 0 V to VS. The
exact VCM at which VOUT peaks during this test varies from device to device, but the VOUT maximum peak is
tested to be less than the specified VOUT tested limit.
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Device Functional Modes (continued)
2.4
2.2 INA202 VOUT Tested Limit
(1)
VCM1
2.0
Ideal
1.8
VCM2
VOUT (V)
1.6
1.4
VCM3
1.2
1.0
0.8
VOUT tested limit at
VSENSE = 0mV, 0 £ VCM1 £ VS.
VCM4
0.6
VCM2, VCM3, and VCM4 illustrate the variance
from part to part of the VCM that can cause
maximum VOUT with VSENSE < 20mV.
0.4
0.2
0
0
2
4
6
8
10
12
14
16
18
20
22
24
VSENSE (mV)
NOTE: (1) INA200 VOUT Tested Limit = 0.4V. INA201 VOUT Tested Limit = 1V.
Figure 33. Example For Low VSENSE Case 2 (INA202, Gain = 100)
7.4.3 Transient Protection
The –16 to 80 V common-mode range of the INA20x devices is ideal for withstanding automotive fault conditions
ranging from 12-V battery reversal up to 80-V transients, since no additional protective components are required
up to those levels. In the event that the INA20x devices are exposed to transients on the inputs in excess of their
ratings, then external transient absorption with semiconductor transient absorbers (such as Zeners) are required.
TI does not recommend using MOVs or VDRs, except when they are used in addition to a semiconductor
transient absorber. Select the transient absorber so the absorber does not allow the INA20x devices to be
exposed to transients greater than 80 V (that is, allow for transient absorber tolerance and additional voltage due
to transient absorber dynamic impedance). Despite the use of internal Zener-type ESD protection, the INA20x
devices do not lend themselves to using external resistors in series with the inputs since the internal gain
resistors can vary up to ±30%. (If gain accuracy is not important, then resistors can be added in series with the
INA200, INA201, and INA202 inputs with two equal resistors on each input.)
7.4.4 Output Voltage Range
The output of the INA20x devices is accurate within the output voltage swing range set by the power supply pin
(VS.) This performance is best illustrated when using the INA202 (a gain of 100 version), where a 100-mV fullscale input from the shunt resistor requires an output voltage swing of 10 V, and a power-supply voltage
sufficient to achieve 10 V on the output.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The INA20x series is designed to enable simple configuration for detecting overcurrent conditions and current
monitoring in an application. This device is individually targeted towards overcurrent detection of a single
threshold. However, this device can pair with additional devices and circuitry to create more complex monitoring
functional blocks.
8.2 Typical Application
RSHUNT
Supply
To VIN+
To VINLoad
4.5 V to 5.5 V
To VIN+
INA200 (G = 20)
INA201 (G = 50)
INA202 (G = 100)
1
VS
To VIN-
VIN+
2 OUT
G
VIN-
8
7
From
Shunt Option
1, 2, or 3
R1 22 k
0.6-V
Reference
R3
Shunt
Option 2
R4 2.2 k
To VIN+
Shunt
Option 3
3 CMPIN
Comparator
CMPOUT
To VINQ1 2N3904
6
R4
4
RESET 5
GND
Copyright © 2017, Texas Instruments Incorporated
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In this case, Q inverts the comparator output.
Figure 34. Low-Side Switch Overcurrent Shutdown
8.2.1 Design Requirements
The device measures current through a resistive shunt with current flowing in one direction that enables
detection of an overcurrent event only when the differential input voltage exceeds the threshold limit. When the
current reaches the set limit of the divider R1 / R2, the output of CMPOUT transitions high, which turns Q1 on,
pulls the gate of the pass-FET low, and turns off the flow off current.
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Typical Application (continued)
8.2.2 Detailed Design Procedure
Figure 34 shows the basic connections of the device. The input terminals (IN+ and IN –) must be connected as
closely as possible to the current-sensing resistor to minimize any resistance in series with the shunt resistance.
Additional resistance between the current-sensing resistor and input terminals results in errors in the
measurement. When input current flows through this external input resistance, the voltage developed across the
shunt resistor differs from the voltage reaching the input terminals.
Use the gain of the INA20x and shunt value to calculate the OUT voltage for the desired trip current. Configure
R1 and R2 so that the current trip point is equal to the 0.6-V reference voltage.
8.2.3 Application Curve
1.2
Comp_IN
I_Load
CMP_OUT
OUT
1
0.8
0.6
0.4
0.2
0
0
0.1
0.2
0.3
0.4
0.5
*Time
0.6
0.7
0.8
0.9
1
Figure 35. Low-Side Switch Overcurrent Shutdown Response
9 Power Supply Recommendations
The input circuitry of the INA20x devices can accurately measure beyond the power-supply voltage, Vs. For
example, the Vs power supply is 5 V, whereas the load power-supply voltage is up to 80 V. However, the output
voltage range of the OUT pin is limited by the voltages on the power supply pin.
9.1 Output vs Supply Ramp Considerations
Figure 36, Figure 37, and Figure 38 show the typical output voltages for high and low-side configurations with the
given ramp supply voltage. These fluctuations on the output during power-up may require a controller to
incorporate a blanking time to disregard the artifacts.
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Output vs Supply Ramp Considerations (continued)
3
5
2.5
4.5
4
Vs
1.5
3.5
1
3
0.5
2.5
0
2
-0.5
1.5
Vout (High Side)
-1
1
-1.5
Output Voltage (V)
Supply Voltage (V)
2
0.5
-2
0
Vout (Low Side)
-2.5
0
1
2
3
4
5
6
7
Time (mSec)
8
9
10
11
-0.5
12
D200
Figure 36. Analog Output vs Supply Ramp (INA200)
3
5
2.5
4.5
4
Vs
1.5
3.5
1
3
0.5
2.5
0
2
-0.5
1.5
Vout (High Side)
-1
1
-1.5
Output Voltage (V)
Supply Voltage (V)
2
0.5
-2
0
Vout (Low Side)
-2.5
0
1
2
3
4
5
6
7
Time (mSec)
8
9
10
11
-0.5
12
D201
Figure 37. Analog Output vs Supply Ramp (INA201)
3
5
2.5
4.5
4
Vs
1.5
3.5
1
3
0.5
2.5
0
2
-0.5
1.5
-1
1
Vout (High Side)
-1.5
Output Voltage (V)
Supply Voltage (V)
2
0.5
-2
0
Vout (Low Side)
-2.5
0
1
2
3
4
5
6
7
Time (mSec)
8
9
10
11
-0.5
12
D202
Figure 38. Analog Output vs Supply Ramp (INA202)
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10 Layout
10.1 Layout Guidelines
•
•
Connect the input pins to the sensing resistor using a Kelvin or 4-wire connection. This connection technique
ensures that only the current-sensing resistor impedance is detected between the input pins. Poor routing of
the current-sensing resistor commonly results in additional resistance present between the input pins. Given
the very-low-ohmic value of the current resistor, any additional high-current carrying impedance causes
significant measurement errors.
The power-supply bypass capacitor must be placed as close as possible to the supply and ground pins. The
recommended value of this bypass capacitor is 0.1 μF. Additional decoupling capacitance can be added to
compensate for noisy or high-impedance power supplies.
10.2 Layout Example
Via to Power or Ground Plane
Via to Internal Layer
Supply Voltage
VS
VIN+
OUT
VIN-
Shunt Resistor
Supply Bypass
Capacitor
R1
CMPIN
CMPOUT
GND
RESET
R2
RPULL-UP
RESET
Output Signal
Figure 39. INA20x Layout Example
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11 Device and Documentation Support
11.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
INA200
Click here
Click here
Click here
Click here
Click here
INA201
Click here
Click here
Click here
Click here
Click here
INA202
Click here
Click here
Click here
Click here
Click here
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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26-Aug-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
INA200AID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA
200A
INA200AIDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
BQH
INA200AIDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
BQH
INA200AIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA
200A
INA201AID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA
201A
INA201AIDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
BQJ
INA201AIDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
BQJ
INA201AIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA
201A
INA202AID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA
202A
INA202AIDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
BQL
INA202AIDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
BQL
INA202AIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA
202A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2017
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF INA200, INA201, INA202 :
• Automotive: INA200-Q1, INA201-Q1, INA202-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jan-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
INA200AIDGKR
VSSOP
DGK
8
INA200AIDGKT
VSSOP
DGK
INA200AIDR
SOIC
D
INA201AIDGKR
VSSOP
INA201AIDGKT
VSSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
8
250
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
DGK
8
250
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
INA201AIDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
INA202AIDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
INA202AIDGKT
VSSOP
DGK
8
250
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
INA202AIDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jan-2020
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
INA200AIDGKR
VSSOP
DGK
8
2500
366.0
364.0
50.0
INA200AIDGKT
VSSOP
DGK
8
250
366.0
364.0
50.0
INA200AIDR
SOIC
D
8
2500
367.0
367.0
35.0
INA201AIDGKR
VSSOP
DGK
8
2500
366.0
364.0
50.0
INA201AIDGKT
VSSOP
DGK
8
250
366.0
364.0
50.0
INA201AIDR
SOIC
D
8
2500
367.0
367.0
35.0
INA202AIDGKR
VSSOP
DGK
8
2500
366.0
364.0
50.0
INA202AIDGKT
VSSOP
DGK
8
250
366.0
364.0
50.0
INA202AIDR
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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