Texas Instruments | TLC2272M-MIL Advanced LinCMOS Rail-to-Rail Operational Amplifier | Datasheet | Texas Instruments TLC2272M-MIL Advanced LinCMOS Rail-to-Rail Operational Amplifier Datasheet

Texas Instruments TLC2272M-MIL Advanced LinCMOS Rail-to-Rail Operational Amplifier Datasheet
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TLC2272M-MIL
SLOS983 – JUNE 2017
TLC2272M-MIL Advanced LinCMOS Rail-to-Rail Operational Amplifier
1 Features
•
•
•
•
1
•
•
•
•
•
•
•
Output Swing Includes Both Supply Rails
Low Noise: 9 nV/√Hz Typical at f = 1 kHz
Low-Input Bias Current: 1-pA Typical
Fully-Specified for Both Single-Supply and SplitSupply Operation
Common-Mode Input Voltage Range Includes
Negative Rail
High-Gain Bandwidth: 2.2-MHz Typical
High Slew Rate: 3.6-V/μs Typical
Low Input Offset Voltage: 2.5 mV Maximum at
TA = 25°C
Macromodel Included
Performance Upgrades for the TLC272 and
TLC274
Available in Q-Temp Automotive
The TLC2272M-MIL device also makes a great
upgrade to the TLC272 in standard designs, offering
increased output dynamic range, lower noise voltage,
and lower input offset voltage. This enhanced feature
set allows the device to be used in a wider range of
applications. For applications that require higher
output drive and wider input voltage range, see the
TLV2432 and TLV2442 devices.
If the design requires single amplifiers, see the
TLV2211, TLV2221 and TLV2231 family. These
devices are single rail-to-rail operational amplifiers in
the SOT-23 package. Their small size and low power
consumption make them ideal for high density,
battery-powered equipment.
Device Information(1)
PART NUMBER
TLC2272M-MIL
2 Applications
White Goods (Refrigerators, Washing Machines)
Hand-held Monitoring Systems
Configuration Control and Print Support
Transducer Interfaces
Battery-Powered Applications
3 Description
The TLC2272M-MIL device is a dual operational
amplifier from Texas Instruments. The device exhibits
rail-to-rail output performance for increased dynamic
range in single- or split-supply applications. The
TLC2272M-MIL device offers 2 MHz of bandwidth
and 3 V/μs of slew rate for higher-speed applications.
Thee device offers comparable ac performance while
having better noise, input offset voltage, and power
dissipation than existing CMOS operational
amplifiers. The TLC2272M-MIL device has a noise
voltage of 9 nV/√Hz, two times lower than competitive
solutions.
The TLC2272M-MIL device, exhibiting high input
impedance and low noise, is excellent for small-signal
conditioning for high-impedance sources such as
piezoelectric transducers. Because of the micropower
dissipation levels, the device works well in hand-held
monitoring and remote-sensing applications. In
addition, the rail-to-rail output feature, with single- or
split-supplies, makes this device a great choice when
interfacing with analog-to-digital converters (ADCs).
For precision applications, the TLC2272AM-MIL
device is available with a maximum input offset
voltage of 950 μV. This device is fully characterized
at 5 V and ±5 V.
BODY SIZE (NOM)
3,91 mm × 4,90 mm
CDIP (8)
6,67 mm × 9,60 mm
LCCC (20)
8,89 mm × 8,89 mm
CFP (10)
6,35 mm × 6,35 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Maximum Peak-to-Peak Output Voltage vs
Supply Voltage
V(OPP)
V
O(PP) − Maximum Peak-to-Peak Output Voltage − V
•
•
•
•
•
PACKAGE
SOIC (8)
16
TA = 25°C
14
12
IO = ± 50 µA
10
IO = ± 500 µA
8
6
4
4
6
8
10
12
14
16
|VDD ±| − Supply Voltage − V
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLC2272M-MIL
SLOS983 – JUNE 2017
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.3 Feature Description................................................. 20
7.4 Device Functional Modes........................................ 20
1
1
1
2
3
5
8
8.1 Application Information............................................ 21
8.2 Typical Application .................................................. 22
9 Power Supply Recommendations...................... 24
10 Layout................................................................... 25
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
TLC2272M-MIL Electrical Characteristics VDD = 5 V 6
TLC2272M-MIL Electrical Characteristics VDD± = ±5
V................................................................................. 8
6.7 Typical Characteristics ............................................ 10
7
Application and Implementation ........................ 21
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 25
11 Device and Documentation Support ................. 26
11.1
11.2
11.3
11.4
11.5
Detailed Description ............................................ 20
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
12 Mechanical, Packaging, and Orderable
Information ........................................................... 26
7.1 Overview ................................................................. 20
7.2 Functional Block Diagram ....................................... 20
4 Revision History
2
DATE
REVISION
NOTE
June 2017
*
Initial release
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5 Pin Configuration and Functions
D or JG Package
8-Pin SOIC or CDIP
Top View
1OUT
1
U Package
10-Pin CFP
Top View
VDD+
8
NC
1
10
NC
1IN–
2
7
2OUT
1OUT
2
9
VDD! +
1IN+
3
6
2IN–
1IN–
3
8
2OUT
4
5
2IN+
1IN+
4
7
2IN–
VDD! –/GND
5
6
2IN+
VDD–/GND
Not to scale
Not to scale
NC
19
NC
1
VDD" +
1OUT
2
NC – No internal connection
20
NC
3
FK Package
20-Pin LCCC
Top View
5
17
2OUT
NC
6
16
NC
1IN+
7
15
2IN–
NC
8
14
NC
13
1IN–
12
NC
11
18
10
4
9
NC
NC
2IN+
NC
VDD" –/GND
NC
Not to scale
NC – No internal connection
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Pin Functions
PIN
NAME
NO.
I/O
D or JG
FK
U
1IN+
3
7
4
1IN–
2
5
1OUT
1
2
2IN+
5
2IN–
DESCRIPTION
I
Non-inverting input, Channel 1
3
I
Inverting input, Channel 1
2
O
Output, Channel 1
12
6
I
Non-inverting input, Channel 2
6
15
7
I
Inverting input, Channel 2
2OUT
7
17
8
O
Output, Channel 2
VDD+
8
20
9
—
Positive (highest) supply
VDD–
—
—
—
—
Negative (lowest) supply
VDD–/GND
4
10
5
—
Negative (lowest) supply
—
1, 3, 4, 6, 8, 9,
11, 13, 14, 16,
18, 19
1, 10
—
No connection
NC
4
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
8
V
Supply voltage, VDD+ (2)
VDD–
(2)
–8
V
Differential input voltage, VID (3)
±16
V
VDD+
V
Input current, II (any input)
±5
mA
Output current, IO
±50
mA
Total current into VDD+
±50
mA
±50
mA
Input voltage, VI (any input) (2)
VDD− − 0.3
Total current out of VDD–
Duration of short-circuit current at (or below) 25°C (4)
Unlimited
Operating ambient temperature range, TA
–55
125
Storage temperature, Tstg
–65
150
(1)
(2)
(3)
(4)
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to the midpoint between VDD+ and VDD–.
Differential voltages are at IN+ with respect to IN–. Excessive current will flow if input is brought below VDD– – 0.3 V.
The output may be shorted to either supply. Temperature or supply voltages must be limited to ensure that the maximum dissipation
rating is not exceeded.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC
Q100-002 (1)
Devices in D packages
±2000
Charged-device model (CDM), per
AEC Q100-011
Devices in D packages
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
MAX
±2.2
±8
V
Input voltage
VDD−
VDD+ − 1.5
V
VIC
Common-mode input voltage
VDD−
VDD+ − 1.5
V
TA
Operating ambient temperature
–55
125
°C
VDD±
Supply voltage
VI
UNIT
6.4 Thermal Information
TLC2272M-MIL
THERMAL METRIC (1)
D (SOIC)
JG (CDIP)
8-PIN
(2) (3)
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
FK (LCCC)
U (CFP)
20-PIN
10-PIN
UNIT
115.6
—
—
°C/W
61.8
18
121.3
°C/W
Junction-to-board thermal resistance
55.9
—
—
°C/W
ψJT
Junction-to-top characterization parameter
14.3
—
—
°C/W
ψJB
Junction-to-board characterization parameter
55.4
—
—
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
8.68
°C/W
(1)
(2)
(3)
(2) (3)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
Maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) − TA) / RθJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with JESD 51-7 (plastic) or MIL-STD-883 Method 1012 (ceramic).
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6.5 TLC2272M-MIL Electrical Characteristics VDD = 5 V
at specified ambient temperature, VDD = 5 V; TA = 25°C, unless otherwise noted.
PARAMETER
VIO
Input offset voltage
αVIO
Temperature coefficient of
input offset voltage
Input offset voltage long-term drift
TEST CONDITIONS
VIC = 0 V, VDD± = ±2.5 V,
VO = 0 V, RS = 50 Ω
(1)
MIN
TA = 25°C
3000
2
VIC = 0 V, VDD± = ±2.5 V, VO = 0 V, RS = 50 Ω
0.002
Input offset current
VIC = 0 V, VDD± = ±2.5 V,
VO = 0 V, RS = 50 Ω
IIB
Input bias current
VIC = 0 V, VDD± = ±2.5 V,
VO = 0 V, RS = 50 Ω
TA = 25°C
VICR
Common-mode input voltage
RS = 50 Ω; |VIO | ≤ 5 mV
0.5
TA = –55°C to 125°C
1
TA = –55°C to 125°C
TA = 25°C
TA = –55°C to 125°C
IOH = –200 μA
IOL = 500 μA
IOL = 5 mA
Large-signal differential
voltage amplification
AVD
2.5
4
0
2.5
3.5
TA = 25°C
4.85
TA = –55°C to 125°C
4.85
TA = 25°C
4.25
TA = –55°C to 125°C
4.25
VIC = 2.5 V, VO = 1 V to 4 V,
RL = 10 kΩ (2)
0.9
TA = –55°C to 125°C
10
TA = –55°C to 125°C
10
35
V/mV
1012
zo
Closed-loop output impedance
f = 1 MHz, AV = 10
CMRR
Common-mode rejection ratio
VIC = 0 V to 2.7 V,
VO = 2.5 V, RS = 50 Ω
TA = 25°C
70
TA = –55°C to 125°C
70
kSVR
Supply-voltage rejection ratio
(ΔVDD / ΔVIO)
VDD = 4.4 V to 16 V,
VIC = VDD / 2, no load
TA = 25°C
80
TA = –55°C to 125°C
80
IDD
Supply currrent
VO = 2.5 V, no load
SR
Slew rate at unity gain
VO = 0.5 V to 2.5 V,
RL = 10 kΩ (2), CL = 100 pF (2)
Vn
Equivalent input noise voltage
VNPP
Peak-to-peak equivalent
input noise voltage
In
Equivalent input noise current
Ω
12
Ω
8
pF
140
Ω
10
TA = 25°C
75
2.2
TA = –55°C to 125°C
2.3
TA = –55°C to 125°C
1.7
3.6
50
f = 1 kHz
9
1
f = 0.1 Hz to 10 Hz
1.4
0.6
AV = 1
0.0013%
AV = 10
0.004%
AV = 100
0.03%
Gain-bandwidth product
f = 10 kHz, RL = 10 kΩ (2), CL = 100 pF (2)
Maximum output-swing bandwidth
VO(PP) = 2 V, AV = 1, RL = 10 kΩ (2), CL = 100 pF (2)
Settling time
AV = –1, RL = 10 kΩ (2),
Step = 0.5 V to 2.5 V, CL = 100 pF (2)
dB
3
3
TA = 25°C
f = 0.1 Hz to 1 Hz
dB
95
f = 10 Hz
VO = 0.5 V to 2.5 V,
f = 20 kHz, RL = 10 kΩ (2)
V
1.5
175
f = 10 kHz, P package
6
0.15
1.5
TA = 25°C
Common-mode input capacitance
(2)
V
0.15
TA = 25°C
Common-mode input resistance
(1)
V
4.65
0.09
ci
ts
pA
4.93
TA = –55°C to 125°C
ri
BOM
pA
0.01
TA = 25°C
Differential input resistance
THD+N Total harmonic distortion + noise
60
–0.3
VIC = 2.5 V, VO = 1 V to 4 V; RL = 1 MΩ (2)
rid
μV/mo
60
800
IOL = 50 μA
VIC = 2.5 V
µV
4.99
IOH = –1 mA
Low-level output voltage
UNIT
μV/°C
800
IOH = –20 μA
VOL
2500
VIC = 0 V, VDD± = ±2.5 V, VO = 0 V, RS = 50 Ω
IIO
High-level output voltage
MAX
300
TA = –55°C to 125°C
TA = 25°C
VOH
TYP
mA
V/µs
nV/√Hz
µV
fA/√Hz
2.18
MHz
1
MHz
To 0.1%
1.5
To 0.01%
2.6
µs
Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
Referenced to 0 V.
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TLC2272M-MIL Electrical Characteristics VDD = 5 V (continued)
at specified ambient temperature, VDD = 5 V; TA = 25°C, unless otherwise noted.
PARAMETER
φm
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Phase margin at unity gain
RL = 10 kΩ (2), CL = 100 pF (2)
50
°
Gain margin
RL = 10 kΩ (2), CL = 100 pF (2)
10
dB
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6.6 TLC2272M-MIL Electrical Characteristics VDD± = ±5 V
at specified ambient temperature, VDD± = ±5 V; TA = 25°C, unless otherwise noted.
PARAMETER
VIO
Input offset voltage
αVIO
Temperature coefficient of
input offset voltage
Input offset voltage long-term drift
TEST CONDITIONS
MIN
TA = 25°C
VIC = 0 V, VO = 0 V,
RS = 50 Ω
3000
2
VIC = 0 V, VO = 0 V, RS = 50 Ω
VIC = 0 V, VO = 0 V,
RS = 50 Ω
IIB
Input bias current
VIC = 0 V, VO = 0 V,
RS = 50 Ω
TA = 25°C
VICR
Common-mode input voltage
RS = 50 Ω; |VIO | ≤ 5 mV
0.5
TA = –55°C to 125°C
1
TA = 25°C
TA = –55°C to 125°C
Maximum positive peak
output voltage
–5.3
0
4
–5
0
3.5
IO = –200 μA
TA = 25°C
4.85
TA = –55°C to 125°C
4.85
TA = 25°C
4.25
TA = –55°C to 125°C
4.25
IO = 50 μA
VIC = 0 V,
IO = 500 μA
IO = 5 mA
Large-signal differential
voltage amplification
VO = ±4 V; RL = 10 kΩ
–4.85
TA = –55°C to 125°C
–4.85
TA = 25°C
–3.5
TA = –55°C to 125°C
–3.5
TA = 25°C
20
TA = –55°C to 125°C
20
V
4.93
V
4.65
–4.91
V
–4.1
50
V/mV
300
1012
Differential input resistance
ri
Common-mode input resistance
ci
Common-mode input capacitance
f = 10 kHz, P package
zo
Closed-loop output impedance
f = 1 MHz, AV = 10
CMRR
Common-mode rejection ratio
VIC = –5 V to 2.7 V,
VO = 0 V, RS = 50 Ω
TA = 25°C
75
TA = –55°C to 125°C
75
kSVR
Supply-voltage rejection ratio
(ΔVDD / ΔVIO)
VDD+ = 2.2 V to ±8 V,
VIC = 0 V, no load
TA = 25°C
80
TA = –55°C to 125°C
80
IDD
Supply currrent
VO = 0 V, no load
SR
Slew rate at unity gain
VO = ±2.3 V,
RL = 10 kΩ, CL = 100 pF
Vn
Equivalent input noise voltage
VNPP
Peak-to-peak equivalent
input noise voltage
In
Equivalent input noise current
THD+N Total harmonic distortion + noise
pA
–4.99
TA = 25°C
VO = ±4 V; RL = 1 MΩ
rid
pA
4.99
IO = –1 mA
Maximum negative
peak output voltage
60
800
IO = –20 μA
µV
μV/mo
60
800
TA = –55°C to 125°C
UNIT
μV/°C
0.002
Input offset current
AVD
2500
VIC = 0 V, VO = 0 V, RS = 50 Ω
(1)
IIO
VOM–
MAX
300
TA = –55°C to 125°C
TA = 25°C
VOM+
TYP
Ω
12
Ω
8
pF
130
Ω
10
TA = 25°C
80
95
2.4
TA = –55°C to 125°C
2.3
TA = –55°C to 125°C
1.7
3.6
f = 10 Hz
50
f = 1 kHz
9
1
f = 0.1 Hz to 10 Hz
1.4
0.6
VO = ±2.3,
f = 20 kHz, RL = 10 kΩ
dB
3
3
TA = 25°C
f = 0.1 Hz to 1 Hz
dB
AV = 1
0.0011%
AV = 10
0.004%
AV = 100
0.03%
mA
V/µs
nV/√Hz
µV
fA/√Hz
Gain-bandwidth product
f = 10 kHz, RL = 10 kΩ, CL = 100 pF
2.25
MHz
Maximum output-swing bandwidth
VO(PP) = 4.6 V, AV = 1, RL = 10 kΩ, CL = 100 pF
0.54
MHz
ts
Settling time
AV = –1, RL = 10 kΩ,
Step = –2.3 V to 2.3 V, CL = 100 pF
φm
Phase margin at unity gain
RL = 10 kΩ, CL = 100 pF
BOM
(1)
8
To 0.1%
1.5
To 0.01%
3.2
52
µs
°
Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
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TLC2272M-MIL Electrical Characteristics VDD± = ±5 V (continued)
at specified ambient temperature, VDD± = ±5 V; TA = 25°C, unless otherwise noted.
PARAMETER
Gain margin
TEST CONDITIONS
RL = 10 kΩ, CL = 100 pF
MIN
TYP
MAX
10
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UNIT
dB
9
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6.7 Typical Characteristics
Table 1. Table of Graphs
FIGURE (1)
Distribution
VIO
Input offset voltage
αVIO
Input offset voltage temperature coefficient
IIB / IIO
Input bias and input offset current
VI
Input voltage
VOH
1, 2
vs Common-mode voltage
3, 4
Distribution
5, 6
vs ambient temperature
7
vs Supply voltage
(2)
(2)
8
vs ambient temperature
9 (2)
High-level output voltage
vs High-level output current
10 (2)
VOL
Low-level output voltage
vs Low-level output current
11, 12 (2)
VOM+
Maximum positive peak output voltage
vs Output current
13 (2)
VOM-
Maximum negative peak output voltage
vs Output current
14 (2)
VO(PP)
Maximum peak-to-peak output voltage
vs Frequency
15
vs Supply voltage
16
IOS
Short-circuit output current
VO
Output voltage
vs Differential input voltage
Large-signal differential voltage amplification
vs Load resistance
Large-signal differential voltage amplification and phase margin
vs Frequency
Large-signal differential voltage amplification
vs ambient temperature
Output impedance
vs Frequency
25, 26
vs Frequency
27
vs ambient temperature
28
AVD
z0
CMRR
Common-mode rejection ratio
kSVR
Supply-voltage rejection ratio
IDD
Supply current
SR
Vn
18, 19
20
21, 22
23 (2), 24 (2)
vs Frequency
29, 30
31 (2)
vs ambient temperature
vs Supply voltage
vs ambient temperature
32 (2),
vs ambient temperature
36, 37
Voltage-follower large-signal pulse response
38, 39
Inverting small-signal pulse response
40, 41
Voltage-follower small-signal pulse response
42, 43
vs Frequency
Noise voltage over a 10-second period
(1)
(2)
10
44, 45
46
Integrated noise voltage
vs Frequency
47
Total harmonic distortion + noise
vs Frequency
48
Gain-bandwidth product
φm
34
35 (2)
Inverting large-signal pulse response
Equivalent input noise voltage
THD+N
(2)
(2) (2)
33 ,
vs Load Capacitance
Slew rate
VO
17 (2)
vs ambient temperature
vs Supply voltage
vs ambient temperature
49
50 (2)
Phase margin
vs Load capacitance
51
Gain margin
vs Load capacitance
52
For all graphs where VDD = 5 V, all loads are referenced to 2.5 V.
Data at high and low temperatures are applicable only within the rated operating ambient temperature range of the device.
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15
20
891 Amplifiers From
2 Wafer Lots
VDD = ± 2.5 V
TA = 25°C
Percentage of Amplifiers − %
Percentage of Amplifiers − %
20
10
5
0
−1.6 −1.2 − 0.8 − 0.4
0
0.4
0.8
1.2
10
5
0
−1.6 −1.2 −0.8 − 0.4
1.6
0.4
0.8
1.2
1.6
VIO − Input Offset Voltage − mV
Figure 1. Distribution of Input Offset Voltage
Figure 2. Distribution of Input Offset Voltage
1
VIO − Input Offset Voltage − mV
VIO
VDD = 5 V
TA = 25°C
RS = 50 Ω
0.5
0
−0.5
−1
−1
0
2
1
3
4
VDD = ± 5 V
TA = 25°C
RS = 50 Ω
0.5
0
−0.5
−1
−6 −5 −4 −3 −2
5
Figure 3. Input Offset Voltage vs Common-Mode Voltage
0
2
1
3
4
5
Figure 4. Input Offset Voltage vs Common-Mode Voltage
25
25
128 Amplifiers From
2 Wafer Lots
VDD = ± 2.5 V
P Package
25°C to 125°C
Percentage of Amplifiers − %
20
−1
VIC − Common-Mode Voltage − V
VIC − Common-Mode Voltage − V
Percentage of Amplifiers − %
0
VIO − Input Offset Voltage − mV
1
VIO
VIO − Input Offset Voltage − mV
15
891 Amplifiers From
2 Wafer Lots
VDD = ± 5 V
TA = 25°C
15
10
5
0
−5 −4
−3
−2
−1
0
1
2
3
4
5
20
15
10
5
0
−5 −4
−3
−2
−1
0
1
2
3
4
5
αV IO − Temperature Coefficient − µV/°C
αV IO − Temperature Coefficient − µV/°C
Figure 5. Distribution of Amplifiers vs
Input Offset Voltage Temperature Coefficient
128 Amplifiers From
2 Wafer Lots
VDD = ± 5 V
P Package
25°C to 125°C
Figure 6. Distribution of Amplifiers vs
Input Offset Voltage Temperature Coefficient
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12
35
30
TA = 25°C
RS = 50 Ω
10
VDD = ± 2.5 V
VIC = 0 V
VO = 0 V
RS = 50 Ω
8
6
25
V I − Input Voltage − V
IIB
I IO − Input Bias and Input Offset Currents − pA
IIB and IIO
SLOS983 – JUNE 2017
20
IIB
15
IIO
10
4
2
|VIO| ≤ 5 mV
0
−2
−4
−6
5
−8
− 10
0
25
45
65
85
105
2
125
3
4
5
6
7
Figure 8. Input Voltage vs Supply Voltage
Figure 7. Input Bias and Input Offset Current vs
Ambient Temperature
5
6
VDD = 5 V
V0H
V
OH − High-Level Output Voltage − V
VDD = 5 V
V I − Input Voltage − V
4
3
|VIO| ≤ 5 mV
2
1
0
−1
−75 − 50
5
4
TA = 125°C
3
TA = 25°C
2
TA = − 55°C
1
0
− 25
0
25
50
75
100
125
0
TA − Free-Air Temperature − °C
1.4
VOL
VOL − Low-Level Output Voltage − V
VDD = 5 V
TA = 25°C
VOL
VOL − Low-Level Output Voltage − V
2
3
4
Figure 10. High-Level Output Voltage vs
High-Level Output Current
1.2
1
VIC = 0 V
0.8
VIC = 1.25 V
0.6
0.4
1
IOH − High-Level Output Current − mA
Figure 9. Input Voltage vs Ambient Temperature
VIC = 2.5 V
0.2
0
VDD = 5 V
VIC = 2.5 V
1.2
1
TA = 125°C
0.8
TA = 25°C
0.6
TA = − 55°C
0.4
0.2
0
0
1
2
3
4
IOL − Low-Level Output Current − mA
5
Figure 11. Low-Level Output Voltage vs
Low-Level Output Current
12
8
|VDD ±| − Supply Voltage − V
TA − Free-Air Temperature − °C
0
5
1
2
3
4
IOL − Low-Level Output Current − mA
6
Figure 12. Low-Level Output Voltage vs
Low-Level Output Current
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5
VDD ± = ± 5 V
4
TA = − 55°C
TA = 25°C
3
TA = 125°C
2
1
0
1
2
3
4
5
V OM − − Maximum Negative Peak Output Voltage − V
SLOS983 – JUNE 2017
V OM + − Maximum Positive Peak Output Voltage − V
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− 3.8
VDD = ± 5 V
VIC = 0 V
−4
TA = 125°C
− 4.2
TA = 25°C
− 4.4
TA = − 55°C
− 4.6
− 4.8
−5
0
1
2
10
5
6
16
RL = 10 kΩ
TA = 25°C
9
8
7
6
VDD = 5 V
5
4
VDD = ± 5 V
3
2
1
VID = − 100 mV
12
8
4
0
VID = 100 mV
−4
VO = 0 V
TA = 25°C
−8
0
10 k
100 k
2
10 M
1M
f − Frequency − Hz
15
4
5
6
7
8
Figure 16. Short-Circuit Output Current vs Supply Voltage
5
VO = 0 V
VDD = ± 5 V
VID = − 100 mV
11
VO − Output Voltage − V
4
7
−3
−1
VDD = 5 V
TA = 25°C
RL = 10 kΩ
VIC = 2.5 V
3
2
1
VID = 100 mV
−5
−50
3
|VDD ±| − Supply Voltage − V
Figure 15. Maximum Peak-to-Peak Output Voltage vs
Frequency
IIOS
OS − Short-Circuit Output Current − mA
4
Figure 14. Maximum Negative Peak Output Voltage vs
Output Current
IIOS
OS − Short-Circuit Output Current − mA
V(OPP)
V O(PP) − Maximum Peak-to-Peak Output Voltage − V
Figure 13. Maximum Positive Peak Output Voltage vs
Output Current
− 75
3
IO − Output Current − mA
|IO| − Output Current − mA
−25
0
25
50
75 100
TA − Free-Air Temperature − °C
125
Figure 17. Short-Circuit Output Current vs
Ambient Temperature
0
− 800
800
−400
0
400
VID − Differential Input Voltage − µV
1200
Figure 18. Output Voltage vs Differential Input Voltage
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5
1000
VDD = ± 5 V
TA = 25°C
RL = 10 kΩ
VIC = 0 V
VO = ± 1 V
TA = 25°C
AVD
AVD− Large-Signal Differential
Voltage Amplification − dB
3
VO − Output Voltage − V
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1
−1
100
VDD = ± 5 V
10
VDD = 5 V
1
−3
0.1
0.1
−5
0
250 500 750 1000
−1000 − 750 − 500 − 250
VID − Differential Input Voltage − µV
AVD
AVD− Large-Signal Differential
Voltage Amplification − dB
60
180°
80
135°
60
40
90°
20
45°
0
0°
−20
−45°
−40
1k
10 k
100 k
1M
Figure 20. Large-Signal Differential Voltage Amplification vs
Load Resistance
−90°
10 M
AVD
AVD− Large-Signal Differential
Voltage Amplification − dB
VDD = 5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
φ
om
m − Phase Margin
80
90°
20
45°
0°
0
−20
−45°
−40
1k
10 k
−90°
10 M
Figure 22. Large-Signal Differential Voltage Amplification
and Phase Margin vs Frequency
AVD
AVD− Large-Signal Differential
Voltage Amplification − V/mV
AVD
AVD− Large-Signal Differential
Voltage Amplification − V/mV
100 k
1M
f − Frequency − Hz
1k
VDD = 5 V
VIC = 2.5 V
VO = 1 V to 4 V
RL = 1 MΩ
100
RL = 10 kΩ
−50
− 25
0
25
50
75 100
TA − Free-Air Temperature − °C
125
Figure 23. Large-Signal Differential Voltage Amplification vs
Ambient Temperature
14
135°
40
1k
10
− 75
180°
VDD = ± 5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
f − Frequency − Hz
Figure 21. Large-Signal Differential Voltage Amplification
and Phase Margin vs Frequency
100
φ
om
m − Phase Margin
Figure 19. Output Voltage vs Differential Input Voltage
1
10
RL − Load Resistance − kΩ
VDD = ± 5 V
VIC = 0 V
VO = ± 4 V
RL = 1 MΩ
100
RL = 10 kΩ
10
− 75
−50
− 25
0
25
50
75 100
TA − Free-Air Temperature − °C
125
Figure 24. Large-Signal Differential Voltage Amplification vs
Ambient Temperature
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1000
1000
zo
O
zo − Output Impedance − Ω
VDD = ± 5 V
TA = 25°C
100
AV = 100
10
AV = 10
1
AV = 1
0.1
100
1k
10 k
100 k
AV = 100
10
AV = 10
1
0.1
100
1M
1k
100 k
1M
f − Frequency − Hz
Figure 25. Output Impedance vs Frequency
Figure 26. Output Impedance vs Frequency
90
TA = 25°C
VDD = ± 5 V
80
VDD = 5 V
60
40
20
10
100
1k
10 k
100 k
1M
86
82
10 M
VDD = ± 5 V
VIC = − 5 V to 2.7 V
78
VDD = 5 V
74
70
−75
0
VIC = 0 V to 2.7 V
−50
Figure 27. Common-Mode Rejection Ratio vs Frequency
0
25
50
75
100
125
Figure 28. Common-Mode Rejection Ratio vs
Ambient Temperature
100
100
kSVR
k
SVR − Supply-Voltage Rejection Ratio − dB
VDD = 5 V
TA = 25°C
80
60
kSVR+
40
kSVR −
20
0
−20
10
−25
TA − Free-Air Temperature − °C
f − Frequency − Hz
kSVR
k SVR − Supply-Voltage Rejection Ratio − dB
10 k
f − Frequency − Hz
100
CMRR − Common-Mode Rejection Ratio − dB
100
AV = 1
CMRR − Common-Mode Rejection Ratio − dB
zo
O
zo − Output Impedance − Ω
VDD = 5 V
TA = 25°C
100
1k
10 k
100 k
1M
10 M
VDD = ± 5 V
TA = 25°C
80
60
kSVR+
40
kSVR −
20
0
−20
10
f − Frequency − Hz
100
1k
10 k
100 k
1M
10 M
f − Frequency − Hz
Figure 29. Supply-Voltage Rejection Ratio vs Frequency
Figure 30. Supply-Voltage Rejection Ratio vs Frequency
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3
VDD ± = ± 2.2 V to ± 8 V
VO = 0 V
VO = 0 V
No Load
105
2.4
IIDD
DD − Supply Current − mA
kSVR
k
SVR − Supply Voltage Rejection Ratio − dB
110
100
95
1.8
TA = 25°C
TA = − 55°C
1.2
TA = 125°C
0.6
90
85
− 75
0
− 50
−25
0
25
50
75
100
0
125
1
TA − Free-Air Temperature − °C
2
3
4
5
6
|VDD ± | − Supply Voltage − V
3
5
VDD = 5 V
AV = − 1
TA = 25°C
VDD = ± 5 V
VO = 0 V
4
SR − Slew Rate − V/ µs
IIDD
DD − Supply Current − mA
2.4
VDD = 5 V
VO = 2.5 V
1.8
1.2
SR −
3
2
SR +
1
0.6
− 50
−25
0
25
50
75
100
0
10
125
100
1k
CL − Load Capacitance − pF
TA − Free-Air Temperature − °C
5
5
VDD = 5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
AV = − 1
SR −
4
SR +
2
VDD = 5 V
RL = 10 kΩ
CL = 100 pF
AV = 1
1
16
VO − Output Voltage − mV
VO
SR − Slew Rate − V/ µs
4
3
10 k
Figure 34. Slew Rate vs Load Capacitance
Figure 33. Supply Current vs Ambient Temperature
0
− 75
8
Figure 32. Supply Current vs Supply Voltage
Figure 31. Supply-Voltage Rejection Ratio vs
Ambient Temperature
0
− 75
7
3
2
1
0
−50
−25
0
25
50
75
100
125
0
1
2
3
4
5
6
7
8
9
TA − Free-Air Temperature − °C
t − Time − µs
Figure 35. Slew Rate vs Ambient Temperature
Figure 36. Inverting Large-Signal Pulse Response
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5
3
2
4
VO − Output Voltage − V
VO
4
V
VO
O − Output Voltage − V
5
VDD = ± 5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
AV = − 1
1
0
−1
−2
VDD = 5 V
RL = 10 kΩ
CL = 100 pF
AV = 1
TA = 25°C
3
2
1
−3
−4
−5
0
0
1
2
3
4
5
6
7
8
9
0
1
2
3
t − Time − µs
Figure 37. Inverting Large-Signal Pulse Response
5
5
6
7
8
9
2
VDD = 5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
AV = −1
2.6
VO − Output Voltage − V
VO
3
Figure 38. Voltage-Follower Large-Signal Pulse Response
2.65
VDD = ± 5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
AV = 1
4
VO − Output Voltage − V
VO
4
t − Time − µs
1
0
−1
−2
−3
2.55
2.5
2.45
−4
−5
2.4
0
1
2
3
4
5
6
7
8
9
0
0.5
1 1.5
2 2.5 3
3.5 4
4.5
5 5.5
t − Time − µs
t − Time − µs
Figure 39. Voltage-Follower Large-Signal Pulse Response
Figure 40. Inverting Small-Signal Pulse Response
2.65
VDD = ± 5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
AV = 1
50
2.6
VO − Output Voltage − V
VO
VO − Output Voltage − mV
VO
100
0
−50
VDD = 5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
AV = 1
2.55
2.5
2.45
2.4
−100
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
t − Time − µs
t − Time − µs
Figure 41. Inverting Small-Signal Pulse Response
Figure 42. Voltage-Follower Small-Signal Pulse Response
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VDD = ± 5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
AV = 1
50
Vn
nV HzHz
Vn − Equivalent Input Noise Voltage − nV/
VO − Output Voltage − mV
VO
100
www.ti.com
0
−50
VDD = 5 V
TA = 25°C
RS = 20 Ω
40
30
20
10
0
−100
100
1k
f − Frequency − Hz
Figure 43. Voltage-Follower Small-Signal Pulse Response
Figure 44. Equivalent Input Noise Voltage vs Frequency
1
1.5
60
1000
VDD = ± 5 V
TA = 25°C
RS = 20 Ω
500
40
30
20
250
0
−250
−500
10
−750
0
10
−1000
10 k
100
1k
f − Frequency − Hz
10
1
0.1
100
1k
6
8
10
Figure 46. Noise Voltage Over a 10-Second Period
THD + N − Total Harmonic Distortion Plus Noise − %
Calculated Using
Ideal Pass-Band Filter
Lower Frequency = 1 Hz
TA= 25°C
10
4
t − Time − s
100
1
2
0
Figure 45. Equivalent Input Noise Voltage vs Frequency
µ V RMS
Integrated Noise Voltage − uVRMS
VDD = 5 V
f = 0.1 Hz to 10 Hz
TA = 25°C
750
Noise Voltage − nV
Vn
nV HzHz
Vn − Equivalent Input Noise Voltage − nV/
0.5
10
10 k
t − Time − µs
0
18
60
10 k
100 k
1
VDD = 5 V
TA = 25°C
RL = 10 kΩ
0.1
AV = 100
0.01
AV = 10
0.001
0.0001
100
AV = 1
1k
10 k
100 k
f − Frequency − Hz
f − Frequency − Hz
Figure 47. Integrated Noise Voltage vs Frequency
Figure 48. Total Harmonic Distortion + Noise vs Frequency
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3
f = 10 kHz
RL = 10 kΩ
CL = 100 pF
TA = 25°C
2.4
VDD = 5 V
f = 10 kHz
RL = 10 kΩ
CL = 100 pF
2.8
Gain-Bandwidth Product − MHz
Gain-Bandwidth Product − MHz
2.5
2.3
2.2
2.1
2.6
2.4
2.2
2
1.8
1.6
1.4
2
0
1
6
2
3
4
5
|VDD ±| − Supply Voltage − V
7
8
Figure 49. Gain-Bandwidth Product vs Supply Voltage
75°
−50
−25
0
25
50
75 100
TA − Free-Air Temperature − °C
125
Figure 50. Gain-Bandwidth Product vs Ambient Temperature
15
VDD = ± 5 V
TA = 25°C
Rnull = 100 Ω
60°
12
Rnull = 50 Ω
Gain Margin − dB
φ m − Phase Margin
om
− 75
45°
Rnull = 20 Ω
30°
VDD = 5 V
AV = 1
RL = 10 kΩ
TA = 25°C
9
6
10 kΩ
15°
10 kΩ
0°
10
3
VDD +
Rnull
VI
Rnull = 0
CL
VDD −
Rnull = 10 Ω
100
1000
CL − Load Capacitance − pF
10000
Figure 51. Phase Margin vs Load Capacitance
0
10
100
1000
CL − Load Capacitance − pF
10000
Figure 52. Gain Margin vs Load Capacitance
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7 Detailed Description
7.1 Overview
The TLC2272M-MIL device is a rail-to-rail output operational amplifier. The device operates from a 4.4-V to 16-V
single supply or ±2.2-V to ±8-V dual supply, is unity-gain stable, and is suitable for a wide range of generalpurpose applications.
7.2 Functional Block Diagram
VDD +
Q3
Q6
Q9
Q12
Q14
Q16
IN +
OUT
C1
IN −
R5
Q1
Q4
Q13
Q15
Q17
D1
Q2
Q5
R3
R4
Q7
Q8
Q10
Q11
R1
R2
VDD−
Table 2. Device Component Count (1)
(1)
COMPONENT
COUNT
Transistors
38
Resistors
26
Diodes
9
Capacitors
3
Includes both amplifiers and all ESD, bias, and trim circuitry.
7.3 Feature Description
The TLC2272M-MIL device features 2-MHz bandwidth and voltage noise of 9 nV/√Hz with performance rated
from 4.4 V to 16 V across a temperature range of –55°C to 125°C). LinMOS suits a wide range of audio,
automotive, industrial, and instrumentation applications.
7.4 Device Functional Modes
The TLC2272M-MIL device is powered on when the supply is connected. The device may operate with single or
dual supply, depending on the application. The device is in its full-performance mode once the supply is above
the recommended value.
20
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Macromodel Information
Macromodel information provided was derived using MicroSim Parts™, the model generation software used with
MicroSim PSpice™. The Boyle macromodel (1) and subcircuit in Figure 53 were generated using the TLC2272MMIL typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the
following key parameters can be generated to a tolerance of 20% (in most cases):
• Maximum positive output voltage swing
• Maximum negative output voltage swing
• Slew rate
• Quiescent power dissipation
• Input bias current
• Open-loop voltage amplification
• Unity-gain frequency
• Common-mode rejection ratio
• Phase margin
• DC output resistance
• AC output resistance
• Short-circuit output current limit
99
DIN
3
EGND +
VCC +
9
RSS
10
VC
IN −
J1
DP
J2
11
VAD
VCC −
DC
12
C1
RD1
R2
−
53
IN +
HLIM
−
+
−
+
VIN
7
+
GCM
GA
VLIM
8
−
RD2
RO1
DE
5
54
4
−
−
C2
6
60
+
−
+ DIP
91
+
VIP
90
RO2
VB
RP
2
1
92
FB
−
+
ISS
−
+
VE
.SUBCKT TLC227x 1 2 3 4 5
C1
11
1214E−12
C2
6
760.00E−12
DC
5
53DX
DE
54
5DX
DLP
90
91DX
DLN
92
90DX
DP
4
3DX
EGND
99
0POLY (2) (3,0) (4,) 0 .5 .5
FB
99
0POLY (5) VB VC VE VLP VLN 0
+ 984.9E3 −1E6 1E6 1E6 −1E6
GA
6
011 12 377.0E−6
GCM 0 6 10 99 134E−9
ISS
3
10DC 216.OE−6
HLIM
90
0VLIM 1K
J1
11
210 JX
J2
12
110 JX
R2
6
9100.OE3
OUT
RD1
60
112.653E3
RD2
60
122.653E3
R01
8
550
R02
7
9950
RP
3
44.310E3
RSS
10
99925.9E3
VAD
60
4−.5
VB
9
0DC 0
VC 3 53 DC .78
VE
54
4DC .78
VLIM
7
8DC 0
VLP
91
0DC 1.9
VLN
0
92DC 9.4
.MODEL DX D (IS=800.0E−18)
.MODEL JX PJF (IS=1.500E−12BETA=1.316E-3
+ VTO=−.270)
.ENDS
Figure 53. Boyle Macromodel and Subcircuit
(1)
Macromodeling of Integrated Circuit Operational Amplifiers, IEEE Journal of Solid-State Circuits, SC-9, 353 (1974).
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8.2 Typical Application
8.2.1 High-Side Current Monitor
VBAT
V1
ILOUD
V2
RS
0.1 µF
R1
R
ILOAD
VOUT
+
_
R2
47 kΩ
Rg
Figure 54. Equivalent Schematic (Each Amplifier)
8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 3 as the input parameters.
Table 3. Design Parameters
PARAMETER
VALUE
VBAT
Battery voltage
12 V
RSENSE
Sense resistor
ILOAD
Load current
0.1 Ω
0 A to 10 A
Operational amplifier
Set in differential configuration with gain = 10
8.2.1.2 Detailed Design Procedure
This circuit is designed for measuring the high-side current in automotive body control modules with a 12-V
battery or similar applications. The operational amplifier is set as differential with an external resistor network.
8.2.1.2.1 Differential Amplifier Equations
Equation 1 and Equation 2 are used to calculate VOUT.
VOUT
VOUT
æ R R
1æ R
R
ç
1+ ç 1 +
- 1
ç
2 è R2 Rg
Rg ç Rg R2 V1 + V2
=
´
+
ç
R
R
R ç
2
1+ 1
1+ 1
çç
R2
R2
è
æ R R
1æ R
R
ç
1+ ç 1 +
- 1
2 çè R2 Rg
Rg ç Rg R2
=
´ VBAT +
ç
R1
R
R ç
1+
1+ 1
çç
R2
R2
è
ö
ö
÷
÷
÷
ø (V - V ) ÷
1
2 ÷
÷
÷÷
ø
(1)
ö
ö
÷
÷
÷
÷
ø ´R ´I
S
Load ÷
÷
÷÷
ø
(2)
In an ideal case R1 = R and R2 = Rg, and VOUT can then be calculated using Equation 3:
Rg
VOUT =
´ RS ´ ILoad
R
22
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However, as the resistors have tolerances, they cannot be perfectly matched.
R1 = R ± ΔR1
R2 = R2 ± ΔR2
R = R ± ΔR
Rg = Rg ± ΔRg
DR
Tol =
R
(4)
By developing the equations and neglecting the second order, the worst case is when the tolerances add up.
This is shown by Equation 5.
æ
æ
Rg
2R ö ö Rg
VOUT = ± (4 Tol)
´ VBAT + ç 1 ± 2 Tol ç 1 +
÷÷
´ RS ´ ILOAD
ç
÷÷
ç
R + Rg
è R + Rg ø ø R
è
where
•
•
Tol = 0.01 for 1%
Tol = 0.001 for 0.1%
(5)
If the resistors are perfectly matched, then Tol = 0 and VOUT is calculated using Equation 6.
Rg
VOUT =
´ RS ´ ILOAD
R
(6)
The highest error is from the common mode, as shown in Equation 7.
Rg
4 (Tol)
´ VBAT
R + Rg
(7)
Gain of 10, Rg / R = 10, and Tol = 1%:
Common mode error = ((4 × 0.01) / 1.1) × 12 V = 0.436 V
Gain of 10 and Tol = 0.1%:
Common mode error = 43.6 mV
The resistors were chosen from 2% batches.
R1 and R 12 kΩ
R2 and Rg 120 kΩ
Ideal Gain = 120 / 12 = 10
The measured value of the resistors:
R1 = 11.835 kΩ
R = 11.85 kΩ
R2 = 117.92 kΩ
Rg = 118.07 kΩ
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1.2
12
1
10
Output Voltage (V)
Output Voltage (V)
8.2.1.3 Application Curves
0.8
0.6
0.4
0.2
8
6
4
2
Measured
Ideal
Measured
Ideal
0
0
0
0.2
0.4
0.6
0.8
Load Current (A)
1
1.2
0
2
D001
Figure 55. Output Voltage Measured vs Ideal
(0 to 1 A)
4
6
8
Load Current (A)
10
12
D001
Figure 56. Output Voltage Measured vs Ideal
(0 to 10 A)
9 Power Supply Recommendations
Supply voltage for a single supply is from 4.4 V to 16 V, and from ±2.2 V to ±8 V for a dual supply. In the highside sensing application, the supply is connected to a 12-V battery.
24
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10 Layout
10.1 Layout Guidelines
The TLC2272M-MIL device is a wideband amplifier. To realize the full operational performance of the device,
good high-frequency printed-circuit-board (PCB) layout practices are required. Low-loss 0.1-μF bypass capacitors
must be connected between each supply pin and ground as close to the device as possible. The bypass
capacitor traces should be designed for minimum inductance.
10.2 Layout Example
Figure 57. Layout Example
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
MicroSim Parts, PSpice are trademarks of MicroSim.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9555201NXD
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
Q2272M
5962-9555201NXDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
Q2272M
5962-9555201Q2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629555201Q2A
TLC2272
MFKB
5962-9555201QHA
ACTIVE
CFP
U
10
1
TBD
A42
N / A for Pkg Type
-55 to 125
9555201QHA
TLC2272M
5962-9555201QPA
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
9555201QPA
TLC2272M
TLC2272MFKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629555201Q2A
TLC2272
MFKB
TLC2272MJG
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
TLC2272MJG
TLC2272MJGB
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
9555201QPA
TLC2272M
TLC2272MUB
ACTIVE
CFP
U
10
1
TBD
A42
N / A for Pkg Type
-55 to 125
9555201QHA
TLC2272M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2017
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
5962-9555201NXDR
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
5962-9555201NXDR
SOIC
D
8
2500
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
0.063 (1,60)
0.015 (0,38)
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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