Texas Instruments | INA250-Q1, Automotive 36-V, Low- or High-Side, Bidirectional, Zero-Drift Current-Shunt Monitor With Precision Integrated Shunt Resistor (Rev. A) | Datasheet | Texas Instruments INA250-Q1, Automotive 36-V, Low- or High-Side, Bidirectional, Zero-Drift Current-Shunt Monitor With Precision Integrated Shunt Resistor (Rev. A) Datasheet

Texas Instruments INA250-Q1, Automotive 36-V, Low- or High-Side, Bidirectional, Zero-Drift Current-Shunt Monitor With Precision Integrated Shunt Resistor (Rev. A) Datasheet
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INA250-Q1
SBOS805A – JULY 2016 – REVISED NOVEMBER 2016
INA250-Q1, Automotive 36-V, Low- or High-Side, Bidirectional, Zero-Drift
Current-Shunt Monitor With Precision Integrated Shunt Resistor
1 Features
2 Applications
•
•
•
•
•
•
•
1
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C5
Precision Integrated Shunt Resistor:
– Shunt Resistor: 2-mΩ
– Shunt Resistor Tolerance: 0.1% (Maximum)
– 15 A Continuous from –40°C to +85°C
– 0°C to +125°C Temperature Coefficient:
10 ppm/°C
High Accuracy:
– Gain Error (Shunt and Amplifier): 0.3%
(Maximum)
– Offset Current: 50 mA (Maximum, INA250A2Q1)
Four Available Gains:
– INA250A1-Q1: 200 mV/A
– INA250A2-Q1: 500 mV/A
– INA250A3-Q1: 800 mV/A
– INA250A4-Q1: 2 V/A
Wide Common-Mode Range: –0.1 V to 36 V
Specified Operating Temperature: –40°C to
+125°C
Body Control Modules
DC/DC Converter
Battery Management Systems
Engine Control Systems
Suspension Systems
3 Description
The automotive qualified INA250-Q1 is a voltageoutput, current-sensing amplifier family that integrates
an internal precision shunt resistor to enable highaccuracy current measurements at common-mode
voltages that may vary from 0 V to 36 V, independent
of the supply voltage.
The INA250-Q1 family is available in four output
voltage scales: 200 mV/A, 500 mV/A, 800 mV/A, and
2 V/A. This device is fully tested and specified for
continuous currents up to 10 amps at the maximum
temperature of +125°C. The INA250-Q1 device
operates from a single 2.7-V to 36-V supply and
draws a maximum of 300 µA of supply current. All
INA250-Q1 gain versions are specified over the
extended operating temperature range of –40°C to
+125°C, and are available in a TSSOP-16 package.
Device Information(1)
PART NUMBER
INA250-Q1
PACKAGE
TSSOP (16)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
Device Supply
(2.7 V to 36 V)
CBYPASS
0.1 µF
Power Rail
(0 V to 36 V)
IN+
SH+
VIN+
VS
REF
Microcontroller
+
OUT
ADC
±
IN-
SH-
VIN-
GND
ADC
Load
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA250-Q1
SBOS805A – JULY 2016 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
6
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 16
8
Applications and Implementation ...................... 20
8.1 Application Information............................................ 20
8.2 Typical Applications ................................................ 20
9 Power Supply Recommendations...................... 24
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Examples................................................... 25
11 Device and Documentation Support ................. 27
11.1
11.2
11.3
11.4
11.5
11.6
Receiving Notification of Documentation Updates
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (July 2016) to Revision A
Page
•
Document status changed from Product Preview to Production Data .................................................................................. 1
•
Changed maximum charged-device model ESD value from ±750 to ±1000 ........................................................................ 4
•
Changed maximum IB values in the Electrical Characteristics table from ±35 to ±40............................................................ 6
2
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SBOS805A – JULY 2016 – REVISED NOVEMBER 2016
5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
IN-
1
16
IN+
IN-
2
15
IN+
IN-
3
14
IN+
SH-
4
13
SH+
VIN-
5
12
VIN+
GND
6
11
GND
REF
7
10
VS
GND
8
9
OUT
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
GND
6, 8, 11
Analog
IN–
1, 2, 3
Analog input
Ground
Connect to load
IN+
14, 15, 16
Analog input
Connect to supply
OUT
9
REF
7
Analog input
SH–
4
Analog output
Kelvin connection to internal shunt. Connect to VIN– if no filtering is needed.
See Figure 33 for filter recommendations.
SH+
13
Analog output
Kelvin connection to internal shunt. Connect to VIN+ if no filtering is needed.
See Figure 33 for filter recommendations.
VIN–
5
Analog input
Voltage input from load side of shunt resistor.
VIN+
12
Analog input
Voltage input from supply side of shunt resistor.
VS
10
Analog
Analog output Output voltage
Reference voltage, 0 V to VS (up to 18 V)
Device power supply, 2.7 V to 36 V
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage (VS)
MAX
UNIT
40
V
Analog input current
Continuous current
±15
A
Analog inputs (IN+, IN–)
Common-mode
GND – 0.3
40
V
Common-mode
GND – 0.3
40
–40
40
GND – 0.3
VS + 0.3
V
GND – 0.3
40
V
GND – 0.3
(VS + 0.3) up to 18
V
–55
150
Analog inputs (VIN+, VIN–)
Differential (VIN+) – (VIN–)
Analog inputs (REF)
Analog outputs (SH+, SH–)
Common-mode
Analog outputs (OUT)
Operating, TA
Temperature
Junction, TJ
150
Storage, Tstg
(1)
V
–65
°C
150
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
MAX
VS
Operating supply voltage
2.7
36
V
TA
Operating free-air temperature
–40
125
°C
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36
UNIT
Common-mode input voltage
4
0
NOM
VCM
V
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SBOS805A – JULY 2016 – REVISED NOVEMBER 2016
6.4 Thermal Information
INA250-Q1
THERMAL METRIC (1)
PW (TSSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
104.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
42.3
°C/W
RθJB
Junction-to-board thermal resistance
48.5
°C/W
ψJT
Junction-to-top characterization parameter
4.5
°C/W
ψJB
Junction-to-board characterization parameter
48
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).
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6.5 Electrical Characteristics
at TA = 25°C, VS = 5 V, VIN+ = 12 V, VREF = 2.5 V, ISENSE = IN+ = 0 A, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
VCM
Common-mode input range
CMR
Common-mode rejection
Offset current, RTI (1)
IOS
dIOS/dT
RTI versus temperature
PSR
IB
Reference input range
36
94
102
INA250A2-Q1, VIN+ = 0 V to 36 V,
TA = –40°C to 125°C
97
110
INA250A3-Q1, VIN+ = 0 V to 36 V,
TA = –40°C to 125°C
106
114
INA250A4-Q1, VIN+ = 0 V to 36 V,
TA = –40°C to 125°C
108
118
INA250A1-Q1, ISENSE = 0 A
±15
±100
INA250A2-Q1, ISENSE = 0 A
±12.5
±50
INA250A3-Q1, ISENSE = 0 A
±5
±30
INA250A4-Q1, ISENSE = 0 A
±5
±20
TA = –40°C to 125°C
IB+, IB-, ISENSE = 0 A
(2)
V
dB
VS = 2.7 V to 36 V, TA = –40°C to 125°C
Input bias current
VREF
–0.1
INA250A1-Q1, VIN+ = 0 V to 36 V,
TA = –40°C to 125°C
mA
25
250
μA/°C
±0.03
±1
mA/V
±28
±40
μA
(VS) up to 18
V
0
SHUNT RESISTOR (3)
RSHUNT
Shunt resistance
(SH+ to SH–)
Package resistance
Resistor temperature
coefficient
ISENSE
(1)
(2)
(3)
(4)
(5)
6
Equivalent resistance when used with
onboard amplifier
Used as stand-alone resistor (4)
1.998
2
2.002
1.9
2
2.1
IN+ to IN–
4.5
TA = –40°C to 125°C
15
TA = –40°C to 0°C
50
TA = 0°C to 125°C
10
Maximum continuous
current (5)
TA = –40°C to 85°C
Shunt short time overload
ISENSE = 30 A for 5 seconds
±0.05%
Shunt thermal shock
–65°C to 150°C, 500 cycles
±0.1%
Shunt resistance to solder
heat
260°C solder, 10 s
±0.1%
Shunt high temperature
exposure
1000 hours, TA = 150°C
Shunt cold temperature
storage
24 hours, TA = –65°C
mΩ
mΩ
ppm/°C
±15
A
±0.15%
±0.025%
RTI = referred-to-input.
The supply voltage range maximum is 36 V, but the reference voltage cannot be higher than 18 V.
See the Integrated Shunt Resistor section for additional information regarding the integrated current-sensing resistor.
The internal shunt resistor is intended to be used with the internal amplifier and is not intended to be used as a stand-alone resistor. See
the Integrated Shunt Resistor section for more information.
See Figure 30 and the Layout section for additional information on the current derating and layout recommendations to improve the
current handling capability of the device at higher temperatures.
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SBOS805A – JULY 2016 – REVISED NOVEMBER 2016
Electrical Characteristics (continued)
at TA = 25°C, VS = 5 V, VIN+ = 12 V, VREF = 2.5 V, ISENSE = IN+ = 0 A, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
G
Gain
INA250A1-Q1
200
INA250A2-Q1
500
INA250A3-Q1
800
INA250A4-Q1
2
ISENSE = –10 A to 10 A, TA = 25°C
System gain error (6)
±0.05%
ISENSE = –10 A to 10 A,
TA = –40°C to 125°C
RO
45
ISENSE = 0.5 A to 10 A
ppm/°C
±0.03%
Output impedance
Maximum capacitive load
V/A
±0.3%
±0.75%
TA = –40°C to 125°C
Nonlinearity error
mV/A
No sustained oscillation
1.5
Ω
1
nF
VOLTAGE OUTPUT (7)
Swing to VS power-supply
rail
RL = 10 kΩ to GND
(VS) – 0.1
(VS) – 0.2
Swing to GND
RL = 10 kΩ to GND
(VGND) + 25
(VGND) + 50
V
mV
FREQUENCY RESPONSE
BW
Bandwidth
SR
Slew rate
INA250A1-Q1, CL = 10 pF
50
INA250A2-Q1, CL = 10 pF
50
INA250A3-Q1, CL = 10 pF
35
INA250A4-Q1, CL = 10 pF
11
CL = 10 pF
0.2
INA250A1-Q1
51
INA250A2-Q1
35
INA250A3-Q1
37
INA250A4-Q1
27
kHz
V/μs
NOISE, RTI (1)
Voltage noise density
nV/√Hz
POWER SUPPLY
VS
Operating voltage range
IQ
Quiescent current
2.7
TA = –40°C to 125°C
200
36
V
300
μA
125
°C
TEMPERATURE RANGE
Specified range
(6)
(7)
–40
System gain error includes amplifier gain error and the integrated sense resistor tolerance. System gain error does not include the stress
related characteristics of the integrated sense resistor. These characteristics are described in the Shunt Resistor section of the Electrical
Characteristics table.
See Output Voltage Swing vs Output Current (Figure 19).
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6.6 Typical Characteristics
45
40
35
30
25
20
15
5
10
0
-5
-10
-15
-20
160
140
120
80
100
60
40
0
20
-20
-40
-60
-80
-100
-120
-25
Population
Population
at TA = 25°C, VS = 5 V, VIN+ = 12 V, VREF = 2.5 V, ISENSE = IN+ = 0 A, unless otherwise noted.
Offset Current (mA)
Offset Current (mA)
C001
Figure 2. INA250A2-Q1 Input Offset Distribution
Offset Current (mA)
40
35
30
25
20
15
10
5
0
-5
-10
-15
-20
-25
-30
Population
40
35
30
25
20
15
10
5
0
-5
-10
-15
-20
-25
-30
Population
Figure 1. INA250A1-Q1 Input Offset Distribution
Offset Current (mA)
Figure 3. INA250A3-Q1 Input Offset Distribution
Figure 4. INA250A4-Q1 Input Offset Distribution
50
30
20
Population
10
0
-10
-20
150
8
6
4
2
0
-2
-4
Common-Mode Rejection Ratio (mA/V)
Figure 5. Input Offset vs Temperature
8
125
16
100
14
25
50
75
Temperature (°C)
12
0
10
-25
-6
-50
-50
-8
-40
-10
INA250A1-Q1
INA250A2-Q1
INA250A3-Q1
INA250A4-Q1
-30
-12
Input Offset Current (mA)
40
Figure 6. INA250A1-Q1 Common-Mode Rejection Ratio
Distribution
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Typical Characteristics (continued)
5
4
4.5
3
3.5
2
2.5
1
1.5
0
-1
0.5
Common-Mode Rejection Ratio (mA/V)
-0.5
-2
-1.5
5
4
4.5
3
3.5
2
2.5
1
1.5
0
0.5
-1
-0.5
-1.5
-2
Population
Population
at TA = 25°C, VS = 5 V, VIN+ = 12 V, VREF = 2.5 V, ISENSE = IN+ = 0 A, unless otherwise noted.
Common-Mode Rejection Ratio (mA/V)
C003
Figure 7. INA250A2-Q1 Common-Mode Rejection Ratio
Distribution
Figure 8. INA250A3-Q1 Common-Mode Rejection Ratio
Distribution
4
INA250A1-Q1
INA250A2-Q1
INA250A3-Q1
INA250A4-Q1
3.5
Population
CMRR (mA/V)
3
2.5
2
1.5
1
2.5
2
2.25
1.5
1.75
1
1.25
0.5
0.75
0.25
0
-0.5
-0.25
-0.75
-1
0.5
0
-50
-25
0
25
50
75
Temperature (°C)
100
125
150
Common-Mode Rejection Ratio (mA/V)
Figure 9. INA250A4-Q1 Common-Mode Rejection Ratio
Distribution
Figure 10. Common-Mode Rejection Ratio vs Temperature
0
Population
PSRR (µA/V)
-20
-40
-60
150
125
100
75
50
25
0
-25
-50
-75
-100
-125
-150
-80
Power Supply Rejection Ratio (µA/V)
-100
±50
Figure 11. Power-Supply Rejection Ratio Distribution
±25
0
25
50
75
100
125
Temperature (ƒC)
C005
150
C006
Figure 12. Power-Supply Rejection Ratio vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, VIN+ = 12 V, VREF = 2.5 V, ISENSE = IN+ = 0 A, unless otherwise noted.
0.5
0.4
0.2
0.1
Population
Gain Error (%)
0.3
0
-0.1
-0.2
-0.3
-0.4
C033
0.25
0.2
150
0.15
125
0.1
100
0.05
75
0
50
-0.05
25
Temperature (ƒC)
-0.1
0
-0.15
±25
-0.2
±50
-0.25
-0.5
System Gain Error (%)
C007
System gain error = RSHUNT error + amplifier gain error,
load current = 10 A
Figure 14. System Gain Error Distribution
Figure 13. System Gain Error vs Temperature
80
0.5
0.4
60
0.2
40
0.1
Gain (dB)
Gain Error (%)
0.3
0
-0.1
20
0
-0.2
INA250A1-Q1
INA250A2-Q1
INA250A3-Q1
INA250A4-Q1
-0.3
-20
-0.4
-0.5
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
-40
1
150
10
100
C008
1k
10k
Frequency (Hz)
100k
1M
VCM = 12 V, ISENSE = 500 mAPP
Figure 16. Amplifier Gain vs Frequency
Figure 15. Amplifier Gain Error vs Temperature
120
160
140
100
100
CMR (dB)
PSR (dB)
120
80
60
40
80
60
40
20
0
1
20
10
100
1k
10k
Frequency (Hz)
100k
1M
0.1
Figure 17. Power-Supply Rejection vs Frequency
10
10
100
1k
Frequency (Hz)
10k
100k
C011
C010
VCM = 12 V, VREF = 2.5 V, ISENSE = 0 A,
VS = 5 V + 250-mV sine disturbance
1
VS = 5 V, VREF = 2.5 V, ISENSE = 0 A, VCM = 1-V sine wave
Figure 18. Common-Mode Rejection vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, VIN+ = 12 V, VREF = 2.5 V, ISENSE = IN+ = 0 A, unless otherwise noted.
60
VS
-40°C
50
25°C
Input Bias Current (µA)
Output Voltage Swing (V)
VS - 1
125°C
VS - 2
VS - 3
GND + 3
GND + 2
IB+, IB-, VREF = 0 V
40
30
20
IB+, IB-, VREF = 2.5 V
10
0
GND + 1
GND
0
2
4
6
8
10
12
14
±10
0
16
5
10
15
20
25
30
35
40
Common-Mode Voltage (V)
Current (mA)
C013
ISENSE = 0 A, VS = 5 V
Figure 19. Output Voltage Swing vs Output Current
Figure 20. Input Bias Current vs Common-Mode Voltage
(VS = 5 V)
40
40
35
Input Bias Current (µA)
Input Bias Current (µA)
35
30
IB+
25
20
IB15
10
IB+, IB30
25
20
15
5
0
0
10
5
10
15
20
25
30
35
Common-Mode Voltage (V)
±50
40
±25
0
25
50
75
100
125
150
Temperature (ƒC)
C014
ISENSE = 0 A, VS = 0 V, VREF = 0 V
C015
ISENSE = 0 A, VS = 5 V
Figure 21. Input Bias Current vs Common-Mode Voltage
(VS = 0 V)
Figure 22. Input Bias Current vs Temperature
400
250
350
VS = 5 V
300
VS = 2.7 V
Quiescent Current (µA)
Quiescent Current (µA)
VS = 36 V
250
200
150
225
200
175
100
50
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
150
0
5
10
15
20
25
30
35
Supply Voltage (V)
C016
VREF = VS / 2
40
C017
VREF = 2.5 V
Figure 23. Quiescent Current vs Temperature
Figure 24. Quiescent Current vs Supply Voltage
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, VIN+ = 12 V, VREF = 2.5 V, ISENSE = IN+ = 0 A, unless otherwise noted.
100
Referred-to-Input
Voltage Noise (200 nV/div)
Input-Referred
Voltage Noise (nV/Hz)
80
70
60
50
40
30
20
INA250A1-Q1
INA250A2-Q1
INA250A3-Q1
INA250A4-Q1
10
1
10
100
1k
Frequency (Hz)
10k
Time (1 s/div)
100k
C019
VS = 5 V, VREF = 2.5 V, ISENSE = 0 A
VS = 5 V, VCM = 0 V, ISENSE = 0 A
Figure 26. 0.1-Hz to 10-Hz Voltage Noise (Referred-to-Input)
2.5 V
Input
(5 V/div)
Output
(0.5 V/div)
INPUT
INA250A1-Q1
INA250A2-Q1
INA250A3-Q1
INA250A4-Q1
Input
Output
(0.5 V/div)
Figure 25. Input-Referred Voltage Noise vs Frequency
0V
Time (40 µs/div)
Time (30 Ps/div)
C021
Input = (VIN+) - (VIN-)
Input = VIN+, VREF = 2.5 V
Figure 27. Step Response
Output
(1 V/div)
Figure 28. Common-Mode Transient Response
Supply
(2 V/div)
0V
0V
Time (20 µs/div)
C024
Figure 29. Start-Up Response
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7 Detailed Description
7.1 Overview
The INA250-Q1 features a 2-mΩ, precision, current-sensing resistor and a 36-V common-mode, zero-drift
topology, precision, current-sensing amplifier integrated into a single package. High precision measurements are
enabled through the matching of the shunt resistor value and the current-sensing amplifier gain providing a
highly-accurate, system-calibrated solution. Multiple gain versions are available to allow for the optimization of
the desired full-scale output voltage based on the target current range expected in the application.
7.2 Functional Block Diagram
IN+
SH+
VS
VIN+
REF
+
OUT
-
IN-
SH-
VIN-
GND
7.3 Feature Description
7.3.1 Integrated Shunt Resistor
The INA250-Q1 features a precise, low-drift, current-sensing resistor to allow for precision measurements over
the entire specified temperature range of –40°C to +125°C. The integrated current-sensing resistor ensures
measurement stability overtemperature and improves layout and board constraint difficulties common in high
precision measurements.
The onboard current-sensing resistor is designed as a 4-wire (or Kelvin) connected resistor that enables accurate
measurements through a force-sense connection. Connecting the amplifier inputs pins (VIN– and VIN+) to the
sense pins of the shunt resistor (SH– and SH+) eliminates many of the parasitic impedances commonly found in
typical very-low sensing-resistor level measurements. Although the sense connection of the current-sensing
resistor may be accessed through the SH+ and SH– pins, this resistor is not intended to be used as a standalone component. The INA250-Q1 device is system-calibrated to ensure that the current-sensing resistor and
current-sensing amplifier are both precisely matched to one another. Using the shunt resistor without the
onboard amplifier results in a current-sensing resistor tolerance of approximately 5%. To achieve the optimized
system gain specification, the onboard sensing resistor must be used with the internal current-sensing amplifier.
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Feature Description (continued)
The INA250-Q1 has approximately 4.5-mΩ of package resistance. 2 mΩ of this total package resistance is a
precisely-controlled resistance from the Kelvin-connected current-sensing resistor used by the amplifier. The
power dissipation requirements of the system and package are based on the total 4.5-mΩ package resistance
between the IN+ and IN– pins. The heat dissipated across the package when current flows through the device
ultimately determines the maximum current that may be safely handled by the package. The current consumption
of the silicon is relatively low, leaving the total package resistance carrying the high load current as the primary
contributor to the total power dissipation of the package. The maximum safe-operating current level ensures that
the heat dissipated across the package is limited so that the resistor and the package are not damaged, and the
internal junction temperature of the silicon does not exceed a +150°C limit.
External factors (such as ambient temperature, external air flow, and PCB layout) may contribute to how
effectively the heat developed from the current flowing through the total package resistance may be removed
from the device. Under the conditions of no air flow, a maximum ambient temperature of +85°C, and 1-oz.
copper input power planes, the INA250-Q1 device can accommodate continuous current levels up to 15 A. As
shown in Figure 30, the current handling capability is derated at temperatures above the +85°C level with safe
operation up to 10 A at a +125°C ambient temperature. With air flow and larger 2-oz. copper input power planes,
the INA250-Q1 may safely accommodate continuous current levels up to 15 A over the entire –40°C to +125°C
temperature range.
20
Maximum Continuous
Current (A)
17.5
15
12.5
10
7.5
5
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
C026
Figure 30. Maximum Current vs Temperature
7.3.2 Short-Circuit Duration
The INA250-Q1 features a physical shunt resistance that can withstand current levels higher than the continuous
handling limit of 15 A without sustaining damage to the current-sensing resistor or the current-sensing amplifier if
the excursions are brief. Figure 31 shows the short-circuit duration curve for the INA250-Q1.
100
Current (A)
80
60
40
20
0
0.1
1
10
Time (s)
100
C027
Figure 31. Short-Circuit Duration
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Feature Description (continued)
7.3.3 Temperature Stability
System calibration is common for many industrial applications to eliminate initial component and system-level
errors that may be present. A system-level calibration may reduce the initial accuracy requirement for many of
the individual components because the calibration procedure eliminates these errors associated with the
components Performing this calibration may enable precision measurements at the system calibration
temperature, but as the system temperature changes as a result of external ambient changes or self heating,
measurement errors are reintroduced. Without using accurate temperature compensation in addition to the initial
adjustment, the calibration procedure is ineffective in accounting for these temperature-induced changes. One of
the primary benefits of the very-low-temperature coefficient of the INA250-Q1(including the integrated currentsensing resistor and current-sensing amplifier) is that the device measurement remains highly accurate, even
when the temperature changes throughout the specified temperature range.
The drift performance of the integrated current-sensing resistor is shown in Figure 32. Although several
temperature ranges are specified in the Electrical Characteristics table, applications operating in ranges other
than those described may use Figure 32 to determine how much variance in the shunt resistor value may be
expected. As with any resistive element, the tolerance of the component varies when exposed to different
temperature conditions. For the current-sensing resistor integrated in the INA250-Q1, the resistor varies more
when operating in temperatures ranging from –40°C to 0°C than when operating in ranges from 0°C to +125°C.
However, even in the –40°C to 0°C temperature range, the drift is still low at 25 ppm/°C.
Shunt Resistance (m )
2.005
2
1.995
1.99
±50
±25
0
25
50
75
100
Temperature (ƒC)
125
150
C030
Figure 32. Sensing Resistor vs Temperature
An additional aspect to consider is that when current flows through the current-sensing resistor, power dissipates
across this component. This dissipated power results in an increase in the internal temperature of the package,
including the integrated sensing resistor. This resistor self-heating effect results in an increase of the resistor
temperature helping to move the component out of the colder, wider drift temperature region.
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7.4 Device Functional Modes
7.4.1 Amplifier Operation
The INA250-Q1 current-sense amplifier may be configured to measure both unidirectional and bidirectional
currents through the reference voltage level applied to the reference pin (REF). The reference voltage
connected to REF sets the output level that corresponds with a zero input current condition. For unidirectional
operation, tie the REF pin to ground so that when the current increases, the output signal also increases
upwards from this reference voltage (or ground in this case). For bidirectional currents, an external voltage
source may be used as the reference voltage connected to the REF pin to bias up the output. Set the reference
voltage to enable sufficient range above and below this level based on the expected current range to be
measured. Positive currents result in an output signal that increases from the zero-current output level set by the
reference voltage, whereas negative currents result in an output signal that decreases.
Equation 1 shows the amplifier transfer function for both unidirectional and bidirectional amplifiers:
VOUT = (ILOAD × GAIN) + VREF
where:
•
•
•
ILOAD is the current being measured passing through the internal shunt resistor,
GAIN is the corresponding gain (mA/V) of the selected device, and
VREF is the voltage applied to the REF pin
(1)
As with any difference amplifier, the INA250-Q1 common-mode rejection ratio is affected by any impedance
present at the REF input. This concern is not a problem when the REF pin is connected directly to a reference or
power supply. When using resistive dividers from a power supply or a reference voltage, buffer the REF pin with
an op amp.
7.4.2 Input Filtering
An obvious and straightforward location for filtering is at the device output; however, this location negates the
advantage of the low output impedance of the output stage buffer. The input then represents the best location for
implementing external filtering. Figure 33 shows the typical implementation of the input filter for the device.
CF
RS
VIN-
SH-
¦-3dB =
1
RINT
2ŒRSCF
¦-3dB
Bias
+
RINT
SH+
OUT
REF
VIN+
RS
CF
Figure 33. Input Filter
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Device Functional Modes (continued)
However, the addition of external series resistance at the input pins to the amplifier creates an additional error in
the measurement. If possible, keep the value of these series resistors to 10 Ω or less to reduce the affect to
accuracy. The internal bias network illustrated in Figure 33 at the input pins creates a mismatch in input bias
currents when a differential voltage is applied between the input pins, as shown in Figure 34.
80
Input Bias Current (µA)
70
IB+
60
50
40
30
20
IB-
10
0
±10
±20
0
20
40
60
80
Differential Input Voltage (mV)
100
C029
Figure 34. Input Bias Current vs Differential Input Voltage
7.4.2.1 Calculating Gain Error Resulting from External Filter Resistance
If additional external series filter resistors are added to the circuit, the mismatch in bias currents results in a
mismatch of voltage drops across the filter resistors. This mismatch creates a differential error voltage that
subtracts from the voltage developed across the Kelvin connection of the shunt resistor, thus reducing the
voltage that reaches the amplifier input terminals. Without the additional series resistance, the mismatch in input
bias currents has little effect on device operation as a result of the low input bias current of the amplifier and the
typically low impedance of the traces between the shunt and amplifier input pins. The amount of error these
external filter resistors add to the measurement may be calculated using Equation 3, where the gain error factor
is calculated using Equation 2.
The amount of variance between the differential voltage present at the device input relative to the voltage
developed at the shunt resistor is based both on the external series resistance value as well as the internal input
resistors, RINT, as shown in Figure 33. The reduction of the shunt voltage reaching the device input pins appears
as a gain error when comparing the output voltage relative to the voltage across the shunt resistor. A factor may
be calculated to determine the amount of gain error that is introduced by the addition of external series
resistance. Equation 2 calculates the expected deviation from the shunt voltage compared to the expected
voltage at the device input pins.
(1250 ´ RINT)
Gain Error Factor =
(1250 ´ RS) + (1250 ´ RINT) + (RS ´ RINT)
where:
•
•
RINT is the internal input resistor and
RS is the external series resistance
(2)
Gain Error (%) = 100 - (100 ´ Gain Error Factor)
(3)
With the adjustment factor equation including the device internal input resistance, this factor varies with each
gain version, as shown in Table 1. Table 2 lists the gain error factor for each individual device.
Equation 3 calculates the expected gain error from the addition of the external series resistors.
Table 1. Input Resistance
DEVICE
GAIN
RINT
INA250A1-Q1
200 mV/A
50 kΩ
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Device Functional Modes (continued)
Table 1. Input Resistance (continued)
DEVICE
GAIN
RINT
INA250A2-Q1
500 mV/A
20 kΩ
INA250A3-Q1
800 mV/A
12.5 kΩ
INA250A4-Q1
2 V/A
5 kΩ
Table 2. Device Gain Error Factor
DEVICE
SIMPLIFIED GAIN ERROR FACTOR
50,000
INA250A1-Q1
(41 · RS) + 50,000
20,000
INA250A2-Q1
(17 · RS) + 20,000
12,500
INA250A3-Q1
(11 · RS) + 12,500
1,000
INA250A4-Q1
RS + 1,000
For example, using an INA250A2-Q1 device and the corresponding gain error equation from Table 2, a series
resistance of 10-Ω results in a gain error factor of 0.991. The corresponding gain error is then calculated using
Equation 3, resulting in a gain error of approximately 0.84% because of the external 10-Ω series resistors.
7.4.3 Shutting Down the Device
Although the device does not have a shutdown pin, the low power consumption allows for the device to be
powered from the output of a logic gate or transistor switch that may turn on and turn off the voltage connected
to the device power-supply pin. However, in current-shunt monitoring applications, there is also a concern for
how much current is drained from the shunt circuit in shutdown conditions. Evaluating this current drain involves
considering the simplified schematic in shutdown mode, as shown in Figure 35.
Shutdown
Control
CBYPASS
0.1 µF
Supply
Voltage
Supply
IN+
VS
REF
+
OUT
-
IN-
GND
Load
Figure 35. Shutting Down the Device
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Note that there is typically an approximate 1-MΩ impedance (from the combination of the feedback and input
resistors) from each device input to the REF pin. The amount of current flowing through these pins depends on
the respective configuration. For example, if the REF pin is grounded, calculating the effect of the 1-MΩ
impedance from the shunt to ground is straightforward. However, if the reference or op amp is powered when the
device is shut down, the calculation is direct. Instead of assuming 1 MΩ to ground, assume 1 MΩ to the
reference voltage. If the reference or op amp is also shut down, some knowledge of the reference or op amp
output impedance under shutdown conditions is required. For instance, if the reference source functions similar
to an open circuit when un-powered, little or no current flows through the 1-MΩ path.
7.4.4 Using the Device with Common-Mode Transients Above 36 V
With a small amount of additional circuitry, the device may be used in circuits subject to transients higher than
36 V (such as in automotive applications). Use only zener diodes or zener-type transient absorbers (sometimes
referred to as transzorbs); any other type of transient absorber has an unacceptable time delay. Start by adding
a pair of resistors, as shown in Figure 36, as a working impedance for the zener. Keeping these resistors as
small as possible is preferable; a resistor value of 10-Ω is the most common. This value limits the effect on
accuracy with the addition of these external components, as described in the Input Filtering section. Device
interconnections between the shunt resistor and amplifier have a current handling limit of 1 A. Using a 10-Ω
resistor limits the allowable transient range to 10 V above the zener clamp so the device is not damaged. Larger
resistor values may be used in this protection circuit to accommodate a larger transient voltage range, which
results in a larger effect on gain error. Because this circuit limits only short-term transients, many applications are
satisfied with a 10-Ω resistor, along with conventional zener diodes of the lowest power rating available.
2.7-V to 36-V
Supply
CBYPASS
0.1 µF
VS
Supply
IN-
SH+
SH-
VIN+
VIN-
Load
RZ
” 10
+
RZ
” 10
IN+
REF
OUT
GND
Figure 36. Device Transient Protection
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8 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The INA250-Q1 measures the voltage developed across the internal current-sensing resistor when current
passes through the device. The ability to drive the reference pin to adjust the functionality of the output signal
offers multiple configurations, as discussed in this section.
8.2 Typical Applications
8.2.1 Current Summing
Supply
2.7-V to 36-V
Supply
CBYPASS
0.1 µF
VS
IN+
REF
+
OUT
2.7-V to 36-V
Supply
CBYPASS
0.1 µF
IN-
GND
Load
Supply
Supply
VS
IN+
GND
IN-
REF
2.7-V to 36-V
Supply
IN+
CBYPASS
0.1 µF
OUT
-
VS
REF
+
-
IN-
+
OUT
Summed
Output
Load
GND
Load
Figure 37. Daisy-Chain Configuration
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Typical Applications (continued)
8.2.1.1 Design Requirements
Three daisy-chained devices are illustrated in Figure 37. The reference input of the first INA250-Q1 device sets
the quiescent level on the output of all the INA250-Q1 devices in the string.
8.2.1.2 Detailed Design Procedure
The outputs of multiple INA250-Q1 devices are easily summed by connecting the output signal of one INA250Q1 device to the reference input of a second INA250-Q1 device. Summing beyond two devices is possible by
repeating this configuration, connecting the output signal of the next INA250-Q1 device to the reference pin of a
subsequent INA250-Q1 in the chain. The output signal of the final INA250-Q1 device in this chain includes the
current level information for all channels in the chain.
Output Voltage
(1 V/diV)
8.2.1.3 Application Curve
0V
Output
Input Current
(1 A/div)
Input B
0A
0A
Input A
Time (0.5 ms/div)
C034
VS = 5 V, VREF = 2.5 V
Figure 38. Daisy-Chain Configuration Output Response
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Typical Applications (continued)
8.2.2 Parallel Multiple INA250-Q1 Devices for Higher Current
2.7-V to 36-V
Supply
CBYPASS
0.1 µF
VS
2.7-V to 36-V
Supply
Supply
IN+
IN+
CBYPASS
0.1 µF
VS
REF
OUT
REF
+
+
-
OUT
From Out of
First Channel
Paralleled
Output
-
To REF of Second
Channel
GND
IN-
IN-
GND
Load
Figure 39. Parallel Summing Configuration
8.2.2.1 Design Requirements
The parallel connection for multiple INA250-Q1 devices may reduce the equivalent overall sense resistance,
enabling monitoring of higher current levels than a single device is able to accommodate alone. This
configuration also uses a summing arrangement, as described in the Current Summing section. A parallel
summing configuration is shown in Figure 39.
8.2.2.2 Detailed Design Procedure
With a summing configuration, the output of the first channel is fed into the reference input of the second, adding
the distributed measurements back together into a single measured value.
Output Voltage
(5 V/div)
8.2.2.3 Application Curve
Output B
12 V
Input Current
(10 A/div)
Outut A
0A
Input
Time (0.5 ms/div)
C036
VS = 24 V, VREF = 12 V
Figure 40. Parallel Configuration Output Response
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Typical Applications (continued)
8.2.3 Current Differencing
Supply
IN+
2.7-V to 36-V
Supply
CBYPASS
0.1 µF
Supply, Reference
Voltage
VS
+
+
REF
OUT
-
To REF of
Second Channel
IN-
GND
Q1
D1
Mosfet
Drive
Circuits
D2
2.7-V to 36-V
Supply
CBYPASS
0.1 µF
Q2
IN-
VS
+
OUT
REF
IN+
Differenced
Output
From Out of First
Channel
GND
Figure 41. Current Differencing Configuration
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Typical Applications (continued)
8.2.3.1 Design Requirements
Occasionally, the need may arise to confirm that the current into a load is identical to the current coming out of a
load, such as when performing diagnostic testing or fault detection. This procedure requires precision current
differencing. This method is the same as current summing, except that the two amplifiers have the respective
inputs connected opposite of each other. Under normal operating conditions, the final output is close to the
reference value and proportional to any current difference. Figure 41 is an example of two INA250-Q1 devices
connected for current differencing.
8.2.3.2 Detailed Design Procedure
The load current may also be measured directly at the output of the first channel. Although technically this
configuration is current differencing, this connection (see Figure 41) is intended to allow the upper (positive)
sense channel to report any positive-going excursions in the overall output, and the lower (negative) sense
channel to report any negative-going excursions.
Output Voltage
(250 mV/div)
8.2.3.3 Application Curve
2.5 V
Input B
Input Current
(2.5 A/div)
Input A
0A
Time (25 ms/div)
C035
VS = 5 V, VREF = 2.5 V
Figure 42. Current Differencing Configuration Output Response
9 Power Supply Recommendations
The input circuitry of the device may accurately measure signals on common-mode voltages beyond the powersupply voltage, VS. For example, the voltage applied to the VS power-supply pin may be 5 V, whereas the load
power-supply voltage being monitored (the common-mode voltage) may be as high as 36 V. Note that the device
may withstand the full 0-V to 36-V range at the input pins, regardless of whether the device has power applied or
not. Power-supply bypass capacitors are required for stability, and must be placed as closely as possible to the
supply and ground pins of the device. A typical value for this supply bypass capacitor is 0.1 μF. Applications with
noisy or high-impedance power supplies may require additional decoupling capacitors to reject power-supply
noise.
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10 Layout
10.1 Layout Guidelines
•
•
•
•
The INA250-Q1 is specified for current handling of up to 10 A over the entire –40°C to +125°C temperature
range using a 1-oz. copper pour for the input power plane as well as no external airflow passing over the
device.
The primary current-handling limitation for the INA250-Q1 is how much heat is dissipated inside the package.
Efforts to improve heat transfer out of the package and into the surrounding environment improve the ability of
the device to handle currents of up to 15 A over the entire –40°C to +125°C temperature range.
Heat transfer improvements primarily involve larger copper power traces and planes with increased copper
thickness (2 oz.) as well as providing airflow to pass over the device. The INA250EVM (SBOU153) is capable
of supporting 15 A at temperatures up to +125°C.
Place the power-supply bypass capacitor as close as possible to the supply and ground pins. TI recommends
a bypass capacitor value of 0.1 µF. Additional decoupling capacitance may be added to compensate for noisy
or high-impedance power supplies.
10.2 Layout Examples
Figure 43. Recommended Layout
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Layout Examples (continued)
J101
J102
J201
J202
108-0740-001
108-0740-001
108-0740-001
108-0740-001
C103
TP101
TP102
C203
TP201
DNP
TP104
16
15
14
DNP
12
R101
GND1
VS1
0
T101
REF1
1
2
3
4
TP106
13
7
10
IN+
IN+
IN+
INININ-
VIN+
VIN-
SH+
SH-
GND1
TP105
1
2
3
DNP
5
R102
4
GND1
OUT
9
GND
GND
GND
6
8
11
16
15
14
DNP
12
R201
GND2
OUT1
TP206
10
IN+
IN+
IN+
INININ-
VIN+
VIN-
SH+
SH-
ED555/4DS
GND2
TP205
1
2
3
C205
DNP
5
R202
4
OUT
9
VS
GND
GND
GND
6
8
11
OUT2
TP207
INA250A2PWR
TP208
TP203
C202
TP109
TP209
0.1µF
C101
VS1
0.1µF
C201
VS2
1µF
1µF
GND1
GND2
J301
108-0740-001
C303
TP301
J302
J401
J402
108-0740-001
108-0740-001
TP302
108-0740-001
C403
TP401
DNP
TP304
C304
DNP
12
R301
GND3
VS3
0
T301
1
2
3
4
ED555/4DS
REF3
TP306
13
7
10
IN+
IN+
IN+
INININ-
VIN+
VIN-
SH+
SH-
REF
OUT
VS
GND
GND
GND
REF3
OUT3
TP305
1
2
3
DNP
5
R302
4
OUT3
6
8
11
TP308
GND3
TP307
DNP
12
R401
GND4
1
2
3
4
ED555/4DS
13
0
T401
7
REF4
TP406
10
IN+
IN+
IN+
INININ-
VIN+
VIN-
SH+
SH-
REF
OUT
VS
GND
GND
GND
REF4
OUT4
TP405
1
2
3
C405
DNP
5
R402
4
OUT4
6
8
11
TP408
0.1µF
C301
TP407
TP403
C402
TP309
VS3
GND4
0
9
INA250A4PWR
GND4
TP303
C302
C404
16
15
14
VS4
0
9
U401
TP404
C305
INA250A3PWR
GND3
TP402
DNP
U301
16
15
14
GND2
0
REF
REF2
OUT2
TP103
C102
7
REF2
1
2
3
4
TP107
13
0
T201
INA250A1PWR
TP108
C204
VS2
0
VS
U201
TP204
C105
REF
REF1
OUT1
ED555/4DS
DNP
U101
C104
TP202
TP409
0.1µF
C401
VS4
1µF
1µF
GND3
GND4
Figure 44. Recommended Layout Schematic
26
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Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: INA250-Q1
INA250-Q1
www.ti.com
SBOS805A – JULY 2016 – REVISED NOVEMBER 2016
11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates — go to the product folder for your device on ti.com. In the
upper right-hand corner, click the Alert me button to register and receive a weekly digest of product information
that has changed (if any). For change details, check the revision history of any revised document.
11.2 Documentation Support
11.2.1 Related Documentation
• INA250EVM User Guide (SBOU153).
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: INA250-Q1
27
INA250-Q1
SBOS805A – JULY 2016 – REVISED NOVEMBER 2016
www.ti.com
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: INA250-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Mar-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
INA250A1QPWRQ1
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
Q250A1
INA250A2QPWRQ1
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
Q250A2
INA250A3QPWRQ1
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
Q250A3
INA250A4QPWRQ1
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
Q250A4
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Mar-2017
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF INA250-Q1 :
• Catalog: INA250
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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