Texas Instruments | TLC08x-Q1 Wide-Bandwidth High-Output-Drive Single-Supply Operational Amplifiers (Rev. E) | Datasheet | Texas Instruments TLC08x-Q1 Wide-Bandwidth High-Output-Drive Single-Supply Operational Amplifiers (Rev. E) Datasheet

Texas Instruments TLC08x-Q1 Wide-Bandwidth High-Output-Drive Single-Supply Operational Amplifiers (Rev. E) Datasheet
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TLC082-Q1, TLC084-Q1
SLOS510E – SEPTEMBER 2006 – REVISED OCTOBER 2016
TLC08x-Q1 Wide-Bandwidth High-Output-Drive Single-Supply Operational Amplifiers
1 Features
3 Description
•
•
The TLC08x-Q1 is the first general purpose
operational amplifier to highlight TI's BiCMOS
technology. The BiMOS family concept is simple:
provide an upgrade path for BiFET users who are
moving away from dual-supply to single-supply
systems and demand higher AC and DC
performance. With performance rated from 4.5 V to
16 V across an automotive temperature range (–40°C
to 125°C), BiMOS suits a wide range of audio,
automotive,
industrial,
and
instrumentation
applications.
1
•
•
•
•
•
•
Wide Bandwidth: 10 MHz
High-Output Drive
– IOH: 57 mA at VDD –1.5 V
– IOL: 55 mA at 0.5 V
High Slew Rate
– SR+: 16 V/μs
– SR−: 19 V/μs
Wide Supply Range: 4.5 V to 16 V
Supply Current: 1.9 mA per Channel
Low Input Noise Voltage: 8.5 nV√Hz
Input Offset Voltage: 60 μV
Ultra-Small 8-Pin MSOP-PowerPAD Package for
TLC082-Q1
Developed in TI’s patented LBC3 BiCMOS process,
the BiMOS amplifiers combine a very high input
impedance, low-noise CMOS front end with a highdrive bipolar output stage, thus providing the optimum
performance features of both. AC performance
improvements
over
the
TL08x-Q1
BiFET
predecessors include a bandwidth of 10 MHz and
voltage noise of 8.5 nV/√Hz. These features enable
the TLC08x-Q1 devices to be suitable for ADAS
(such as short-range radar) and body in automotive.
The TLC082-Q1 is also suitable in infotainment and
cluster as a pre amp in car audio applications.
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
Automotive
Blind Spot Detection
Engine Control Units
Electric Mirrors
HVAC
Steering
Collision Warnings
Telematics
Clusters
Audio
Industrial
Instrumentations
DC improvements include an ensured VICR that
includes ground, a factor of four reduction in input
offset voltage down to 1.5 mV (maximum), and a
power-supply rejection improvement of greater than
40 dB to 130 dB. Added to this list of impressive
features is the ability to drive ±50-mA loads
comfortably from an ultrasmall-footprint MSOP
PowerPAD™ package, which positions the TLC08xQ1 as the ideal high-performance, general-purpose
operational amplifier family.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TLC082-Q1
MSOP-PowerPAD (8)
3.00 mm × 3.00 mm
TLC084-Q1
HTSSOP (20)
6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Operational Amplifier
−
+
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLC082-Q1, TLC084-Q1
SLOS510E – SEPTEMBER 2006 – REVISED OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
4
5
6
7
7
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: VDD = 5 V.........................
Electrical Characteristics: VDD = 12 V.......................
Operating Characteristics: VDD = 5 V .......................
Operating Characteristics: VDD = 12 V .....................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 15
Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 16
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 16
8.5 Programming .......................................................... 16
9
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Applications ............................................... 18
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 26
12 Device and Documentation Support ................. 27
12.1 Documentation Support ........................................
12.2 Related Links ........................................................
12.3 Receiving Notification of Documentsation
Updates....................................................................
12.4 Community Resources..........................................
12.5 Trademarks ...........................................................
12.6 Electrostatic Discharge Caution ............................
12.7 Glossary ................................................................
27
27
27
27
27
27
27
13 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (August 2016) to Revision E
•
Page
Changed y-axis label from Phase Margin to Gain Margin for the Gain Margin vs Load Capacitance graph ...................... 11
Changes from Revision C (January 2016) to Revision D
Page
•
Deleted the Maximum Power Dissipation vs Free-Air Temperature graph .......................................................................... 25
•
Added the Receiving Notification of Documentation Updates section ................................................................................. 27
Changes from Revision B (May 2011) to Revision C
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Deleted Ultralow-Power Shutdown Mode bullet from Features ............................................................................................. 1
•
Deleted Typical Pin Indicators image from Pin Configuration and Functions ....................................................................... 3
•
Deleted VIH and VIL rows in Recommended Operating Conditions ..................................................................................... 4
•
Deleted Shutdown Forward and Reverse Isolation vs Frequency graphs (formerly Figures 38 and 39) from Typical
Characteristics ...................................................................................................................................................................... 14
2
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SLOS510E – SEPTEMBER 2006 – REVISED OCTOBER 2016
5 Pin Configuration and Functions
DGN Package
8-Pin MSOP With PowerPAD
Top View
1OUT
1IN −
1IN +
GND
1
8
2
7
3
6
4
5
PWP Package
20-Pin HTSSOP
Top View
VDD
2OUT
2IN −
2IN+
1OUT
1IN−
1IN+
VDD
2IN+
2IN−
2OUT
NC
NC
NC
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
NC
NC
NC
NC − No internal connection
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
TLC082-Q1
TLC084-Q1
1IN+
3
3
I
Noninverting input, Channel 1
1IN–
2
2
I
Inverting input, Channel 1
1OUT
1
1
O
Output, Channel 1
2IN+
5
5
I
Noninverting input, Channel 2
2IN–
6
6
I
Inverting input, Channel 2
2OUT
7
7
O
Output, Channel 2
3IN+
—
16
I
Noninverting input, Channel 3
3IN–
—
15
I
Inverting input, Channel 3
3OUT
—
14
O
Output, Channel 3
4IN+
—
18
I
Noninverting input, Channel 4
4IN–
—
19
I
Inverting input, Channel 4
4OUT
—
20
O
Output, Channel 4
GND
4
17
—
Negative (lowest) power supply
NC
—
8 to13
—
Non-connect
VDD
8
4
I
Positive (highest) power supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VDD
Supply voltage (2)
VID
Differential input voltage
Continuous total power dissipation
MIN
MAX
UNIT
–0.3
17
V
±VDD
V
See Thermal Information
TJ
Operating junction temperature
–40
125
°C
TA
Operating ambient temperature
–40
125
°C
TJ(max)
Maximum junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to GND.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002
Electrostatic
discharge
V(ESD)
(1)
(1)
Charged-device model (CDM), per AEC Q100-011
UNIT
±2000
All pins
±500
Corner pins (1, 4, 5, and 8)
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Single supply
VDD
Supply voltage
VICR
Common-mode input voltage
TJ
Operating junction temperature
Split supply
MIN
MAX
4.5
16
±2.25
±8
GND VDD – 2
–40
125
UNIT
V
V
°C
6.4 Thermal Information
THERMAL METRIC
(1)
TLC082-Q1
TLC084-Q1
DGN (MSOP-PowerPAD)
PWP (HTSSOP)
8-PIN
20-PIN
UNIT
RθJA
Junction-to-ambient thermal resistance
58.1
40
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
55.2
46.7
°C/W
RθJB
Junction-to-board thermal resistance
35.3
22.9
°C/W
ψJT
Junction-to-top characterization parameter
2.1
1
°C/W
ψJB
Junction-to-board characterization parameter
35.9
26.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6.9
2.6
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLOS510E – SEPTEMBER 2006 – REVISED OCTOBER 2016
6.5 Electrical Characteristics: VDD = 5 V
VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO
Input offset voltage
VDD = 5 V, VIC = 2.5 V,
VO = 2.5 V, RS = 50 Ω
αVIO
Temperature coefficient of input
offset voltage
VDD = 5 V, VIC = 2.5 V,
VO = 2.5 V, RS = 50 Ω
IIO
Input offset current
VDD = 5 V, VIC = 2.5 V,
VO = 2.5 V, RS = 50 Ω
IIB
Input bias current
VDD = 5 V, VIC = 2.5 V,
VO = 2.5 V, RS = 50 Ω
VICR
Common-mode input voltage
RS = 50 Ω
IOH = –1 mA
IOH = –20 mA
VOH
High-level output voltage
VIC = 2.5 V
IOH = –35 mA
IOH = –50 mA
IOL = 1 mA
IOL = 20 mA
VOL
Low-level output voltage
VIC = 2.5 V
IOL = 35 mA
IOL = 50 mA
Sourcing
TJ (1)
MIN
25°C
TYP
MAX
390
1900
Full range
3300
1.2
25°C
1.9
Full range
3
Full range
25°C
0 to 3
0 to 3.5
0 to 3
0 to 3.5
25°C
4.1
4.3
Full range
3.9
25°C
3.7
Full range
3.5
25°C
3.4
Full range
3.2
25°C
3.2
Full range
50
50
700
Full range
μV
μV/°C
700
25°C
UNIT
pA
pA
V
4
V
3.8
3.6
3
25°C
0.18
Full range
0.25
0.35
25°C
0.35
Full range
0.39
0.45
25°C
0.43
Full range
0.55
V
0.7
25°C
0.45
Full range
0.63
0.7
100
IOS
Short-circuit output current
IO
Output current
AVD
Large-signal differential voltage
amplification
rj(d)
Differential input resistance
25°C
1000
GΩ
CIC
Common-mode input capacitance
f = 10 kHz
25°C
22.9
pF
ZO
Closed-loop output impedance
f = 10 kHz, AV = 10
25°C
0.25
Ω
Sinking
VOH = 1.5 V from positive rail
VOL = 0.5 V from negative rail
VO(PP) = 3 V, RL = 10 kΩ
CMRR
Common-mode rejection ratio
VIC = 0 to 3 V, RS = 50 Ω
kSVR
Supply voltage rejection ratio
(ΔVDD / ΔVIO)
VDD = 4.5 V to 16 V,
VIC = VDD/2, No load
IDD
Supply current (per channel)
VO = 2.5 V, No load
(1)
25°C
57
25°C
100
Full range
100
25°C
70
Full range
70
25°C
80
Full range
80
25°C
mA
55
25°C
Full range
mA
100
120
dB
110
dB
100
1.8
dB
2.5
3.5
mA
Full range is –40°C to 125°C.
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6.6 Electrical Characteristics: VDD = 12 V
VDD = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO
Input offset voltage
VDD = 12 V, VIC = 6 V,
VO = 6 V, RS = 50 Ω
αVIO
Temperature coefficient of input
offset voltage
VDD = 12 V, VIC = 6 V,
VO = 6 V, RS = 50 Ω
IIO
Input offset current
VDD = 12 V, VIC = 6 V,
VO = 6 V, RS = 50 Ω
IIB
Input bias current
VDD = 12 V, VIC = 6 V,
VO = 6 V, RS = 50 Ω
VICR
Common-mode input voltage
RS = 50 Ω
IOH = –1 mA
IOH = –20 mA
VOH
High-level output voltage
VIC = 6 V
IOH = –35 mA
IOH = –50 mA
IOL = 1 mA
IOL = 20 mA
VOL
Low-level output voltage
VIC = 6 V
IOL = 35 mA
IOL = 50 mA
Sourcing
TJ
(1)
MIN
25°C
TYP
MAX
390
1900
Full range
3300
1.2
25°C
1.5
Full range
3
Full range
25°C
0 to 10 0 to 10.5
0 to 10 0 to 10.5
25°C
Full range
50
50
700
Full range
11.1
μV
μV/°C
700
25°C
UNIT
pA
pA
V
11.2
11
25°C
10.8
Full range
10.7
25°C
10.6
Full range
10.3
25°C
10.3
Full range
10.1
25°C
11
V
10.7
10.5
0.17
Full range
0.25
0.35
25°C
0.35
Full range
0.45
0.55
25°C
0.4
Full range
0.52
V
0.6
25°C
0.45
Full range
0.6
0.7
150
IOS
Short-circuit output current
IO
Output current
AVD
Large-signal differential voltage
amplification
rj(d)
Differential input resistance
25°C
1000
GΩ
CIC
Common-mode input capacitance
f = 10 kHz
25°C
21.6
pF
ZO
Closed-loop output impedance
f = 10 kHz, AV = 10
25°C
0.25
Ω
Sinking
VOH = 1.5 V from positive rail
VOL = 0.5 V from negative rail
VO(PP) = 8 V, RL = 10 kΩ
CMRR
Common-mode rejection ratio
VIC = 0 to 10 V, RS = 50 Ω
kSVR
Supply voltage rejection ratio
(ΔVDD / ΔVIO)
VDD = 4.5 V to 16 V, VIC = VDD
/ 2, No load
IDD
Supply current (per channel)
VO = 7.5 V, No load
(1)
6
25°C
57
25°C
110
Full range
110
25°C
80
Full range
80
25°C
80
Full range
80
25°C
mA
55
25°C
Full range
mA
150
130
dB
110
dB
100
1.9
dB
2.9
3.5
mA
Full range is –40°C to 125°C.
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SLOS510E – SEPTEMBER 2006 – REVISED OCTOBER 2016
6.7 Operating Characteristics: VDD = 5 V
VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SR+
Positive slew rate at unity
gain
VO(PP) = 0.8 V, CL = 50 pF, RL = 10 kΩ
SR–
Negative slew rate at unity
gain
VO(PP) = 0.8 V, CL = 50 pF, RL = 10 kΩ
Vn
Equivalent input noise
voltage
In
Equivalent input noise current f = 1 kHz
THD+N
Total harmonic distortion
plus noise
Gain-bandwidth product
ts
Settling time
φm
(1)
f = 100 Hz
TJ (1)
MIN
TYP
25°C
10
16
Full range
9
25°C
11
Full range
8.5
VO(PP) = 3 V,
RL = 10 kΩ and 250 Ω,
f = 1 kHz
0.1%
V(STEP)PP = 1 V, AV = –1,
CL = 47 pF, RL = 10 kΩ
0.1%
Phase margin
RL = 10 kΩ
Gain margin
RL = 10 kΩ
0.01%
CL = 0 pF
CL = 50 pF
CL = 0 pF
—
0.085%
10
MHz
0.18
0.39
25°C
μs
0.18
0.01%
CL = 50 pF
fA/√Hz
0.012%
25°C
V(STEP)PP = 1 V, AV = –1,
CL = 10 pF, RL = 10 kΩ
nV/√Hz
0.002%
25°C
AV = 100
f = 10 kHz, RL = 10 kΩ
V/μs
0.6
AV = 1
AV = 10
19
8.5
25°C
UNIT
V/μs
12
25°C
f = 1 kHz
MAX
0.39
32
25°C
°
40
2.2
25°C
dB
3.3
Full range is –40°C to 125°C.
6.8 Operating Characteristics: VDD = 12 V
VDD = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SR+
Positive slew rate at unity
gain
VO(PP) = 2 V, CL = 50 pF, RL = 10 kΩ
SR–
Negative slew rate at unity
gain
VO(PP) = 2 V, CL = 50 pF, RL = 10 kΩ
Vn
Equivalent input noise
voltage
In
Equivalent input noise current f = 1 kHz
THD+N
ts
φm
(1)
f = 100 Hz
VO(PP) = 8 V,
RL = 10 kΩ and 250 Ω,
f = 1 kHz
Gain-bandwidth product
f = 10 kHz, RL = 10 kΩ
Settling time
AV = 10
9.5
25°C
12.5
Full range
0.01%
25°C
CL = 0 pF
CL = 50 pF
CL = 0 pF
UNIT
V/μs
19
V/μs
10
14
8.5
0.6
nV/√Hz
fA/√Hz
0.005%
—
0.022%
10
MHz
0.17
25°C
0.01%
CL = 50 pF
MAX
0.002%
25°C
0.1%
RL = 10 kΩ
Full range
AV = 100
V(STEP)PP = 1 V, AV = –1,
CL = 47 pF, RL = 10 kΩ
Gain margin
16
25°C
V(STEP)PP = 1 V, AV = –1,
CL = 10 pF, RL = 10 kΩ
RL = 10 kΩ
TYP
10
AV = 1
0.1%
Phase margin
MIN
25°C
25°C
f = 1 kHz
Total harmonic distortion
plus noise
TJ (1)
0.22
0.17
μs
0.29
25°C
25°C
37
42
3.1
4
deg
dB
Full range is –40°C to 125°C.
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6.9 Typical Characteristics
Table 1. Table of Graphs
GRAPH NAME
FIGURE NO.
VIO
Input offset voltage
vs Common-mode input voltage
IIO
Input offset current
vs Free-air temperature
Figure 3
IIB
Input bias current
vs Free-air temperature
Figure 4
VOH
High-level output voltage
vs High-level output current
Figure 5, Figure 7
VOL
Low-level output voltage
vs Low-level output current
Figure 6, Figure 8
ZO
Output impedance
vs Frequency
Figure 9
IDD
Supply current
vs Supply voltage
Figure 10
PSRR
Power supply rejection ratio
vs Frequency
Figure 11
CMRR
Common-mode rejection ratio
vs Frequency
Figure 12
Vn
Equivalent input noise voltage
vs Frequency
Figure 13
VO(PP)
Peak-to-peak output voltage
vs Frequency
Figure 14, Figure 15
Crosstalk
vs Frequency
Figure 16
Differential voltage gain and Phase
vs Frequency
Figure 17, Figure 18
Phase margin
vs Load capacitance
Figure 19, Figure 20
Gain margin
vs Load capacitance
Figure 21, Figure 22
Gain-bandwidth product
vs Supply voltage
φm
Figure 1, Figure 2
Figure 23
vs Supply voltage
SR
Slew rate
THD+N
Total harmonic distortion plus noise
Figure 24
vs Free-air temperature
Figure 25, Figure 26
vs Frequency
Figure 27, Figure 28
vs Peak-to-peak output voltage
Figure 29, Figure 30
Large-signal follower pulse response
8
Figure 31, Figure 32
Small-signal follower pulse response
Figure 33
Large-signal inverting pulse response
Figure 34, Figure 34
Small-signal inverting pulse response
Figure 36
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SLOS510E – SEPTEMBER 2006 – REVISED OCTOBER 2016
1500
VDD = 5 V
TA = 25° C
800
600
400
200
0
−200
−400
1100
900
700
500
300
100
−100
−300
−600
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
−500
0
1
2
3
4
5
6
7
8
9 10 11 12
VICR − Common-Mode Input Voltage − V
VICR − Common-Mode Input Voltage − V
Figure 1. Input Offset Voltage
vs Common-Mode Input Voltage
Figure 2. Input Offset Voltage
vs Common-Mode Input Voltage
300
VDD = 5 V
250
200
150
100
IIB
50
0
IIO
−50
−100
−55 −40 −25 −10 5 20 35 50 65 80 95 110 125
I IB / I IO − Input Bias and Input Offset Current − pA
I IB / I IO − Input Bias and Input Offset Current − pA
VDD = 12 V
TA = 25° C
1300
V IO − Input Offset Voltage − mV
V IO − Input Offset Voltage − m V
1000
20
0
IIO
−20
−40
−60
−80
−100
IIB
−120
VDD = 12 V
−140
−160
−55 −40 −25 −10 5 20 35 50 65 80 95 110 125
TA − Free-Air Temperature − °C
TA − Free-Air Temperature − °C
Figure 3. Input Bias Current and Input Offset Current
vs Free-Air Temperature
Figure 4. Input Bias Current and Input Offset Current
vs Free-Air Temperature
1.0
VDD = 5 V
4.5
TA = 70°C
TA = 25°C
4.0
TA = −40°C
3.5
TA = 125°C
3.0
2.5
VOL − Low-Level Output Voltage − V
VOH − High-Level Output Voltage − V
5.0
VDD = 5 V
0.9
0.8
0.7
TA = 125°C
0.6
TA = 70°C
TA = 25°C
0.5
0.4
0.3
TA = −40°C
0.2
0.1
0.0
2.0
0
5
10 15 20 25 30 35 40 45 50
IOH - High-Level Output Current - mA
Figure 5. High-Level Output Voltage
vs High-Level Output Current
0
5 10 15 20 25 30 35 40 45 50
IOL - Low-Level Output Current - mA
Figure 6. Low-Level Output Voltage
vs Low-Level Output Current
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1.0
VOL − Low-Level Output Voltage − V
VOH − High-Level Output Voltage − V
12.0
TA = 125°C
TA = 70°C
11.5
11.0
10.5
TA = −40°C
TA = 25°C
10.0
9.5
VDD = 12 V
0.9
0.8
TA = 25°C
0.5
0.4
0.3
TA = −40°C
0.2
0.1
VDD = 12 V
0.0
0
0
5 10 15 20 25 30 35 40 45 50
IOH - High-Level Output Current - mA
5 10 15 20 25 30 35 40 45 50
IOL - Low-Level Output Current - mA
Figure 8. Low-Level Output Voltage
vs Low-Level Output Current
Figure 7. High-Level Output Voltage
vs High-Level Output Current
1000
2.4
VDD = 5 V and 12 V
TA = 25°C
100
10
AV = 100
1
AV = 1
0.10
AV = 10
0.01
100
TA = −40°C
2.0
1.8
TA = 125°C
1.6
TA = 70°C
1.4
1.2
AV = 1
Per Channel
1.0
1k
10k
100k
1M
f - Frequency - Hz
4
10M
Figure 9. Output Impedance vs Frequency
120
VDD = 12 V
100
80
60
40
VDD = 5 V
20
0
10
100
1k
10k
100k
1M
10M
5
10
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7 8 9 10 11 12 13 14 15
VDD − Supply Voltage - V
140
VDD = 5 V and 12 V
TA = 25°C
120
100
80
60
40
20
0
100
1k
f − Frequency − Hz
Figure 11. Power-Supply Rejection Ratio vs Frequency
6
Figure 10. Supply Current vs Supply Voltage
CMRR − Common-Mode Rejection Ratio − dB
140
0
TA = 25°C
2.2
I DD − Supply Current − mA
Z o − Output Impedance − W
TA = 70°C
0.6
9.0
PSRR − Power−Supply Rejection Ratio − dB
TA = 125°C
0.7
10k
100k
1M
f - Frequency - Hz
10M
Figure 12. Common-Mode Rejection Ration vs Frequency
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VO(PP) − Peak-to-Peak Output Voltage − V
35
30
25
20
15
VDD = 12 V
10
VDD = 5 V
5
0
10
100
1k
10k
12
VDD = 12 V
10
8
6
VDD = 5 V
4
THD+N ≤ 5%
RL = 600 W
TA = 25°C
2
0
100k
10k
100k
1M
f - Frequency - Hz
f − Frequency − Hz
Figure 14. Peak-to-Peak Output Voltage vs Frequency
12
0
−40
8
6
VDD = 5 V
4
−60
−80
−100
−120
THD+N ≤ 5%
RL= 10 kW
TA = 25°C
2
0
10k
−140
100k
1M
f - Frequency - Hz
−160
10
10M
−45
Phase
−90
30
20
−135
10
−20
1k
VDD = ±2.5 V
RL = 10 kW
CL = 0 pF
TA = 25°C
10k
100k
−180
1M
10M
−225
100M
A VD − Different Voltage Gain − dB
Gain
50
−10
10k
80
70
40
1k
100k
Figure 16. Crosstalk vs Frequency
0
Phase − °
A VD − Different Voltage Gain − dB
80
60
100
f − Frequency − Hz
Figure 15. Peak-to-Peak Output Voltage vs Frequency
0
VDD = 5 V and 12 V
AV = 1
RL = 10 kW
VI(PP) = 2 V
For All Channels
−20
VDD = 12 V
10
Crosstalk − dB
V O(PP) − Peak-to-Peak Output Voltage − V
Figure 13. Equivalent Input Noise Voltage vs Frequency
10M
0
70
Gain
60
−45
50
Phase
40
−90
30
20
−135
Phase − °
Vn − Equivalent Input Noise Voltage − nV/ÖHz
40
10
0
−10
−20
1k
VDD = ±6 V
RL = 10 kW
CL = 0 pF
TA = 25°C
10k
f − Frequency − Hz
−180
100k
1M
10M
−225
100M
f − Frequency − Hz
Figure 17. Differential Voltage Gain and Phase
vs Frequency
Figure 18. Differential Voltage Gain and Phase
vs Frequency
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40°
45°
Rnull = 0 W
Rnull = 100 W
35°
35°
f m − Phase Margin
f m − Phase Margin
30°
25°
Rnull = 50 W
20°
Rnull = 20 W
15°
10°
5°
Rnull = 0 W
40°
VDD = 5 V
RL = 10 kW
TA = 25°C
Rnull = 50 W
30°
Rnull = 100 W
25°
20°
Rnull = 20 W
15°
VDD = 12 V
RL = 10 kW
TA = 25°C
10°
5°
0°
10
0°
10
100
100
CL − Load Capacitance − pF
CL − Load Capacitance − pF
Figure 19. Phase Margin vs Load Capacitance
Figure 20. Phase Margin vs Load Capacitance
4
5
Rnull = 0 W
Rnull = 0 W
4.5
2.5
2
Rnull = 50 W
1.5
1
0.5
VDD = 5 V
RL = 10 kW
TA = 25°C
Rnull = 100 W
4
Rnull = 100 W
3
G − Gain Margin − dB
G − Gain Margin − dB
3.5
3.5
3
2.5
Rnull = 50 W
2
Rnull = 20 W
1.5
VDD = 12 V
RL = 10 kW
TA = 25°C
1
Rnull = 20 W
0.5
0
10
0
10
100
100
CL − Load Capacitance − pF
CL − Load Capacitance − pF
Figure 22. Gain Margin vs Load Capacitance
22
10.0
CL = 11 pF
9.9
9.8
20
9.7
RL = 10 kW
9.6
9.5
9.4
RL = 600 W and 10 kW
CL = 50 pF
AV = 1
21
TA = 25°C
SR − Slew Rate − V/ ms
GBWP − Gain-Bandwidth Product − MHz
Figure 21. Gain Margin vs Load Capacitance
RL = 600 W
9.3
19
Slew Rate −
18
17
16
Slew Rate +
15
9.2
14
9.1
13
12
9.0
4
5
6
7
8
9
10 11 12 13 14 15 16
4
5
VDD - Supply Voltage - V
Figure 23. Gain-Bandwidth Product vs Supply Voltage
12
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6
7 8 9 10 11 12 13 14 15 16
VDD - Supply Voltage - V
Figure 24. Slew Rate vs Supply Voltage
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25
25
SR − Slew Rate − V/ ms
Slew Rate −
20
SR − Slew Rate − V/ ms
Slew Rate −
20
VDD = 5 V
RL= 600 W and 10 kW
CL = 50 pF
AV = 1
15
Slew Rate +
10
Slew Rate +
10
VDD = 12 V
RL= 600 Ω and 10 kΩ
CL = 50 pF
AV = 1
5
5
0
−55 −35 −15 5 25 45 65 85 105 125
TA - Free-Air Temperature - °C
0
−55 −35 −15 5 25 45 65 85 105 125
TA - Free-Air Temperature - °C
Figure 25. Slew Rate vs Free-Air Temperature
Figure 26. Slew Rate vs Free-Air Temperature
0.1
1
VDD = 5 V
VO(PP) = 2 V
RL = 10 kW
AV = 100
0.1
AV = 10
0.01
AV = 1
0.001
100
1k
10k
VDD = 12 V
VO(PP) = 8 V
RL = 10 kW
Total Harmonic Distortion + Noise − %
Total Harmonic Distortion + Noise − %
15
100k
AV = 100
0.01
AV = 10
AV = 1
0.001
100
1k
Figure 27. Total Harmonic Distortion + Noise vs Frequency
10
VDD = 5 V
AV = 1
f = 1 kHz
RL = 250 W
1
0.1
RL = 600 W
0.01
RL = 10 kW
0.001
0.0001
0.25
0.75
1.25 1.75 2.25
100k
Figure 28. Total Harmonic Distortion + Noise Frequency
2.75
3.25 3.75
VO(PP) − Peak-to-Peak Output Voltage − V
Figure 29. Total Harmonic Distortion Plus
Peak-to-Peak Output Voltage
Total Harmonic Distortion + Noise − %
Total Harmonic Distortion + Noise − %
10
10k
f − Frequency − Hz
f − Frequency − Hz
VDD = 12 V
AV = 1
f = 1 kHz
1
RL = 250 W
0.1
RL = 600 W
0.01
0.001
RL = 10 kW
0.0001
0.5
2.5
4.5
6.5
8.5
10.5
VO(PP) − Peak-to-Peak Output Voltage − V
Figure 30. Total Harmonic Distortion Plus
Peak-to-Peak Output Voltage
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VI (5 V/Div)
V O − Output Voltage − V
V O − Output Voltage − V
VI (1 V/Div)
VO (500 mV/Div)
VDD = 5 V
RL = 600 W
and 10 kW
CL = 8 pF
TA = 25°C
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8 2
VO (2 V/Div)
VDD = 12 V
RL = 600 W
and 10 kW
CL = 8 pF
TA = 25°C
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
t − Time − ms
t − Time − ms
Figure 31. Large-Signal Follower Pulse Response
Figure 32. Large-Signal Follower Pulse Response
VI (2 V/div)
V O − Output Voltage − V
V O − Output Voltage − V
VI(100mV/Div)
VO(50mV/Div)
VDD = 5 V and 12 V
RL = 600 W and 10 kW
CL = 8 pF
TA = 25°C
0
VDD = 5 V
RL = 600 W
and 10 kW
CL = 8 pF
TA = 25°C
VO (500 mV/Div)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.10
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
t − Time − ms
t − Time − ms
Figure 33. Small-Signal Follower Pulse Response
Figure 34. Large-Signal Follower Pulse Response
VI (100 mV/div)
V O − Output Voltage − V
V O − Output Voltage − V
VI (5 V/div)
VDD = 12 V
RL = 600 W
and 10 kW
CL = 8 pF
TA = 25°C
VDD = 5 V and 12 V
RL = 600 W and 10 kW
CL = 8 pF
TA = 25°C
VO (50 mV/Div)
VO (2 V/Div)
0
14
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
t − Time − ms
t − Time − ms
Figure 35. Large-Signal Inverting Pulse Response
Figure 36. Small-Signal Inverting Pulse Response
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7 Parameter Measurement Information
_
Rnull
+
RL
CL
Figure 37. Voltage Follower Circuit
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8 Detailed Description
8.1 Overview
The TLC08x-Q1 BiCMOS amplifiers provide an upgrade path for BiFET users who are moving away from dualsupply to single-supply systems and demand higher AC and DC performance. With performance rated from 4.5
V to 16 V across an automotive temperature range (–40°C to 125°C), BiMOS suits a wide range of audio,
automotive, industrial, and instrumentation applications. BiCMOS amplifiers combine a very high input low-noise
CMOS front end drive bipolar output stage, thus providing the optimum performance features of both. AC
performance include a bandwidth of 10 MHz and voltage noise of 8.5 nV/√Hz.
8.2 Functional Block Diagram
Operational Amplifier
−
+
8.3 Feature Description
The TLC08x-Q1 family features 10-MHz bandwidth and voltage noise of 8.5 nV/√Hz with performance rated from
4.5 V to 16 V across an automotive temperature range (–40°C to 125°C). BiMOS suits a wide range of audio,
automotive, industrial, and instrumentation applications.
8.4 Device Functional Modes
The TLC08x-Q1 family of devices is powered on when the supply is connected. The device can operate with
single or dual supply, depending on the application. The device is in its full performance once the supply is above
the recommended value.
8.5 Programming
8.5.1 Macromodel Information
Derivation of the provided macromodel information was by use of Microsim Parts™, the model generation
software used with Microsim PSpice™. The Boyle macromodel (1) and subcircuit in Figure 38 are generated
using the TLC08x-Q1 typical electrical and operating characteristics at TA = 25°C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
• Maximum positive output voltage swing
• Maximum negative output voltage swing
• Slew rate
• Quiescent power dissipation
• Input bias current
• Open-loop voltage amplification
• Unity-gain frequency
• Common-mode rejection ratio
• Phase margin
• DC output resistance
• AC output resistance
• Short-circuit output current limit
(1)
16
G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, Macromodeling of Integrated Circuit Operational Amplifiers, IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
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SLOS510E – SEPTEMBER 2006 – REVISED OCTOBER 2016
99
DLN
3
EGND +
VDD
9
RSS
ISS
10
VC
IN −
J1
DP
J2
IN +
11
RD1
VAD
GND
DC
12
C1
R2
−
53
−
91
+
VLP
−
−
+
VLN
7
+
GA
GCM
VLIM
8
−
RD2
RO1
DE
5
54
4
DLP
C2
6
60
+
−
+
HLIM
−
+
90
RO2
VB
RP
2
1
92
FB
−
+
−
+
VE
∗DEVICE=TLC08X_5V, OPAMP, PJF, INT
∗ TLC08X_5V − 5V operational amplifier ”macromodel” subcircuit
∗ created using Parts release 8.0 on 12/16/99 at 14:03
∗ Parts is a MicroSim product.
∗
∗ connections:
non-inverting input
∗
inverting input
∗
positive power supply
∗
negative power supply
∗
output
∗
.subckt TLC08X_5V 1 2 3 4 5
∗
c1
11 12 4.6015E−12
c2
6 7 8.0000E−12
css
10 99 986.29E−15
dc
5 53 dy
de
54 5 dy
dlp
90 91 dx
dln
92 90 dx
dp
4 3 dx
egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5
fb
7 99 poly(5) vb vc ve vlp vln 0 13.984E6 −1E3 1E3
14E6 −14E6
OUT
ga
gcm
ioff
iss
hlim
j1
j2
r2
rd1
rd2
ro1
ro2
rp
rss
vb
vc
ve
vlim
vlp
vln
.model
.model
.model
.model
.ends
6
0
0
3
90
11
12
6
4
4
8
7
3
10
9
3
54
7
91
0
dx
dy
jx1
jx2
0 11 12 402.12E−6
6 10 99 1.5735E−6
6 dc 1.212E−6
10 dc 130.40E−6
0 vlim 1K
2 10 jx1
1 10 jx2
9
100.00E3
11
2.4868E3
12
2.4868E3
5 10
99 10
4
2.8249E3
99
1.5337E6
0 dc 0
53 dc 1.5537
4 dc .84373
8 dc 0
0 dc 117.60
92 dc 117.60
D(Is=800.00E−18)
D(Is=800.00E−18 Rs=1m Cjo=10p)
PJF(Is=80.000E−15 Beta=1.2401E−3 Vto=−1)
PJF(Is=80.000E−15 Beta=1.2401E−3 Vto=−1)
Figure 38. Boyle Macromodel and Subcircuit
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TLC08x-Q1 devices features wide supply voltage range, high-output current drive in the order of 60 mA, low
input offset voltage, a high unity gain bandwidth 10 MHz and high slew of 16 V/µS. These features make the
device suitable in amplifying high-frequency and slew rate signals.
9.2 Typical Applications
9.2.1 TLC08x-Q1 Single-Supply Typical Application
Some applications require amplification of low amplitude and relatively high-frequency input signal. The sine
wave maximum slew rate is at zero crossing. The amplified signal distorts if the minimum slew rate is not met.
Operational amplifier slew rate must be higher than 2 × π × F × V, where F is the input signal frequency and V is
the output signal amplitude. TLC08x-Q1 Slew rate of 16 V/µS is capable of delivering an output signal of 2-V
peak and 1-MHz frequency with no distortion. See Figure 45 for an application curve that shows the results of
Figure 39.
9K
VDD
0.1 µF
IK
–
VOUT
IK
VIN
+
50 W
GND
Figure 39. TLC08x-Q1 Typical Application
9.2.1.1 Design Requirements
Use the following parameters for this design example:
• Noninverting configuration with gain of 10 or 20 dB
• Single supply minimum: 4.5 V
• Single supply maximum: 16 V
• Output common mode minimum should be higher than output level VOL
• Output common mode maximum should be lower than output level VOH
• Unity gain bandwidth: 10 MHz
• Output load current lower than 60 mA
• Maximum input signal frequency below 1 MHz for less than –3-dB attenuation at 1 MHz
18
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Typical Applications (continued)
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Driving a Capacitive Load
When the amplifier is configured in this manner, capacitive loading directly on the output decreases the device
phase margin, leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater than
10 pF, TI recommends placing a resistor in series (RNULL) with the output of the amplifier, as shown in Figure 40.
A minimum value of 20 Ω should work well for most applications.
RF
RG
Input
_
RNULL
Output
+
CLOAD
Figure 40. Driving a Capacitive Load
9.2.1.2.2 Offset Voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The schematic and formula in Figure 41 can be used to calculate the output offset
voltage.
RF
IIB−
RG
+
VI
−
+
VO
RS
IIB+
æ æ R öö
æ æ R öö
VOO = VIO ç 1 + ç F ÷ ÷ ± IIB + RS ç 1 + ç F ÷ ÷ ± IIB - RF
ç
÷
ç
÷
è è RG ø ø
è è RG ø ø
Figure 41. Output Offset Voltage Model
9.2.1.2.3 High-Speed CMOS Input Amplifiers
The TLC08x-Q1 is a family of high-speed low-noise CMOS input operational amplifiers that has an input
capacitance on the order of 20 pF. Any resistor used in the feedback path adds a pole in the transfer function
equivalent to the input capacitance multiplied by the combination of source resistance and feedback resistance.
For example, a gain of –10, a source resistance of 1 kΩ, and a feedback resistance of 10 kΩ add an additional
pole at approximately 8 MHz. This is more apparent with CMOS amplifiers than bipolar amplifiers due to their
greater input capacitance.
This is of little consequence on slower CMOS amplifiers, as this pole normally occurs at frequencies above their
unity-gain bandwidth. However, the TLC08x-Q1 with its 10-MHz bandwidth means that this pole normally occurs
at frequencies where there is on the order of 5-dB gain left and the phase shift adds considerably.
The effect of this pole is the strongest with large feedback resistances at small closed-loop gains. As the
feedback resistance is increased, the gain peaking increases at a lower frequency and the 180° phase-shift
crossover point also moves down in frequency, decreasing the phase margin.
For the TLC08x-Q1, the maximum feedback resistor recommended is 5 kΩ; larger resistances can be used but a
capacitor in parallel with the feedback resistor is recommended to counter the effects of the input capacitance
pole.
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Typical Applications (continued)
The TLC08x-Q1 with a 1-V step response has an 80% overshoot with a natural frequency of 3.5 MHz when
configured as a unity gain buffer and with a 10-kΩ feedback resistor. By adding a 10-pF capacitor in parallel with
the feedback resistor, the overshoot is reduced to 40% and eliminates the natural frequency, resulting in a much
faster settling time (see Figure 42). The 10-pF capacitor was chosen for convenience only.
V I − Input Voltage − V
Load capacitance had little effect on these measurements due to the excellent output drive capability of the
TLC08x-Q1.
2
VIN
V O − Output Voltage − V
1
0
With
CF = 10 pF
−1
1.5
10 pF
10 kW
_
1
+
IN
0.5
VOUT
0
VDD = ±5 V
AV = +1
RF = 10 kW
RL = 600 W
CL = 22 pF
600 W
50 W
22 pF
−0.5
0 0.2 0.4 0.6 0.8
t - Time - ms
1
1.2 1.4 1.6
Figure 42. 1-V Step Response
9.2.1.2.4 General Configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see
Figure 43).
RG
RF
−
VO
+
VI
R1
C1
f-3dB =
1
2pR1C1
VO æ
R öæ
1
ö
= ç1 + F ÷
VI è RG ø çè 1 + sR1C1 ÷ø
Figure 43. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple-pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is eight to ten times the filter frequency
bandwidth. Failure to do this can result in phase shift of the amplifier.
20
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Typical Applications (continued)
C1
+
_
VI
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
R2
f
C2
RG
RF
–3dB =
RG =
(
1
2 RC
RF
1
2−
Q
)
Figure 44. 2-Pole Low-Pass Sallen-Key Filter
9.2.1.3 Application Curve
Input
Output
Gain Vout / Vin = 1.471 V / 0.2 V = 7.335
Gain(db) = 20 Log (7.335) = 17.33 dB
and is 2.7 dB below 10 dB
Figure 45. Single Supply Application at 1-MHz Input Signal
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Typical Applications (continued)
9.2.2 Dual-Supply Typical Application
The dual-supply application has a gain of 10 and a bandwidth of 1 MHz.
9K
VDD
0.1 µF
IK
–
VOUT
IK
VIN
+
50 W
–VDD
Figure 46. Dual Supply Typical Application Schematic
9.2.2.1 Design Requirements
Use the following parameters for this design example:
• Noninverting configuration with gain of 10 or 20 dB
• Dual supply minimum: ±2.25 V
• Dual supply maximum: ±8 V
• Output common mode minimum should be higher than output level VOL
• Output common mode maximum should be lower than output level VOH
• Unity gain bandwidth: 10 MHz
• Maximum input signal frequency is 1 MHz for less than 3-dB attenuation at 1 MHz
• Output load current lower than 60 mA
9.2.2.2 Detailed Design Procedure
For this example, see Detailed Design Procedure in TLC08x-Q1 Single-Supply Typical Application.
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Typical Applications (continued)
9.2.2.3 Application Curve
Input
Output
Figure 47. Dual Supply Application at 1-MHz Input Signal
10 Power Supply Recommendations
The TLC08x-Q1 operational amplifier is specified for use on a single supply from 4.5 V to 16 V (or a dual supply
from over a temperature range of −40°C to 125°C. The device continues to function below this range, but
performance is not specified. Place bypass capacitors close to the power supply pins to reduce noise coupling in
from noisy or high-impedance power supplies. For more detailed information on bypass capacitor placement, see
Layout Guidelines.
11 Layout
11.1 Layout Guidelines
To achieve the levels of high performance of the TLC08x-Q1, follow proper printed-circuit board (PCB) design
techniques. A general set of guidelines is given in the following.
Ground planes TI highly recommends using a ground plane on the board to provide all components with a lowinductive ground connection. However, in the areas of the amplifier inputs and output, the ground
plane can be removed to minimize the stray capacitance.
Proper power-supply decoupling Use a 6.8-μF tantalum capacitor in parallel with a 0.1-μF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-μF ceramic capacitor should always be used on the supply
terminal of every amplifier. In addition, the 0.1-μF capacitor should be placed as close as possible
to the supply terminal. As this distance increases, the inductance in the connecting trace makes the
capacitor less effective. The designer should strive for distances of less than 0.1 inches between
the device power terminals and the ceramic capacitors.
Sockets
Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the PCB is the
best implementation.
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Layout Guidelines (continued)
Short trace runs and compact part placements Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the
inverting input of the amplifier. Its length should be kept as short as possible. This helps minimize
stray capacitance at the input of the amplifier.
Surface-mount passive components TI recommends using surface-mount passive components for highperformance amplifier circuits for several reasons. First, because of the extremely low lead
inductance of surface-mount components, the problem with stray series inductance is greatly
reduced. Second, the small size of surface-mount components naturally leads to a more-compact
layout, thereby minimizing both stray inductance and capacitance. If leaded components are used,
TI recommends keeping the lead lengths as short as possible.
11.1.1 General PowerPAD™ Design Considerations
The TLC08x-Q1 is available in a thermally-enhanced PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die is mounted [see Figure 48(a) and Figure 48(b)]. This
arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see
Figure 48(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance
can be achieved by providing a good thermal path away from the thermal pad.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
NOTE A: The thermal pad is electrically isolated from all terminals in the package.
Figure 48. Views of Thermally-Enhanced DGN Package
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
NOTE
Soldering the thermal pad to the PCB is always required, even with applications that have
low power dissipation.
This soldering provides the necessary thermal and mechanical connection between the lead frame die pad and
the PCB. Although there are many ways to properly heatsink the PowerPAD package, the following steps list the
recommended approach.
The thermal pad must be connected to the most-negative supply voltage (GND pin potential) of the device.
1. Prepare the PCB with a top-side etch pattern (see the landing patterns at the end of this data sheet). There
should be etch for the leads, as well as etch for the thermal pad.
2. Place five holes (dual) or nine holes (quad) in the area of the thermal pad. These holes should be 13 mils in
diameter. Keep them small so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the TLC08x-Q1 device. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal-pad
area to be soldered, so that wicking is not a problem.
4. Connect all holes to the internal plane that is at the same potential as the ground pin of the device.
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Layout Guidelines (continued)
5. When connecting these holes to this internal plane, do not use the typical web or spoke via connection
methodology. Web connections have a high-thermal-resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In
this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the
holes under the TLC08x-Q1 PowerPAD package should make their connection to the internal ground plane
with a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal-pad area with its five
holes (dual) or nine holes (quad) exposed. The bottom-side solder mask should cover the five or nine holes
of the thermal-pad area. This prevents solder from being pulled away from the thermal-pad area during the
reflow process.
7. Apply solder paste to the exposed thermal-pad area and all of the IC terminals.
8. With these preparatory steps in place, the TLC08x-Q1 IC is simply placed in position and run through the
solder reflow operation as any standard surface-mount component. This results in a part that is properly
installed.
For a given RθJA, use Equation 1 to calculate the maximum power dissipation.
æT
- TA ö
PD = ç MAX
÷
è RqJA ø
Where:
PD = Maximum power dissipation of TLC08x IC (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA
= Free-ambient air temperature (°C)
R qJA = R qJC + R qCA
R qJC = Thermal coefficient from junction to case
R qCA = Thermal coefficient from case to ambient air (°C/W)
(1)
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the device,
especially multi-amplifier devices. Because these devices have linear output stages (class A-B), most of the heat
dissipation is at low-output voltages with high-output currents.
The other key factor when dealing with power dissipation is how the devices are mounted on the PCB. The
PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a
copper plane to fully use the heat dissipation properties of the thermal pad. The SOIC package, on the other
hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the
device, RθJA decreases and the heat dissipation capability increases. The currents and voltages shown in Typical
Characteristics are for the total package. For the dual or quad amplifier packages, the sum of the RMS output
currents and voltages should be used to choose the proper package.
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11.2 Layout Example
+
VIN
VOUT
RG
RF
(Schematic Representation)
Place components
close to device and to
Run the input
each other to reduce
traces as far away
parasitic errors
from the supply
lines as possible
VS+
RF
N/C
N/C
GND
±IN
V+
VIN
+IN
OUTPUT
V±
N/C
RG
Use low-ESR,
ceramic bypass
capacitor
GND
VS±
GND
Use low-ESR, ceramic
bypass capacitor
VOUT
Ground (GND) plane on another layer
Figure 49. Operational Amplifier Board Layout for Noninverting Configuration
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SLOS510E – SEPTEMBER 2006 – REVISED OCTOBER 2016
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
TLC081 EMI Immunity Performance (SBOT011)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLC082-Q1
Click here
Click here
Click here
Click here
Click here
TLC084-Q1
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentsation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
Parts, PSpice are trademarks of MicroSim Corporation.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation pane.
Copyright © 2006–2016, Texas Instruments Incorporated
Product Folder Links: TLC082-Q1 TLC084-Q1
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27
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLC082QDGNRQ1
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
QXO
TLC084QPWPRQ1
ACTIVE
HTSSOP
PWP
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
TLC084Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2019
OTHER QUALIFIED VERSIONS OF TLC082-Q1, TLC084-Q1 :
• Catalog: TLC082, TLC084
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TLC082QDGNRQ1
Package Package Pins
Type Drawing
SPQ
HVSSOP
2500
DGN
8
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
12.4
Pack Materials-Page 1
5.3
B0
(mm)
K0
(mm)
P1
(mm)
3.4
1.4
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLC082QDGNRQ1
HVSSOP
DGN
8
2500
346.0
346.0
29.0
Pack Materials-Page 2
PACKAGE OUTLINE
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SCALE 4.000
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
NOTE 3
1.95
4
5
8X
B
3.1
2.9
NOTE 4
0.38
0.25
0.13
C A B
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
1.89
1.63
9
1.1 MAX
8
1
0 -8
0.15
0.05
0.7
0.4
DETAIL A
A 20
1.57
1.28
TYPICAL
4225481/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.57)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
9
(1.89)
(1.22)
6X (0.65)
5
4
( 0.2) TYP
VIA
(0.55)
SEE DETAILS
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4225481/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
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EXAMPLE STENCIL DESIGN
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.57)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8X (0.45)
8
1
SYMM
(1.89)
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
(4.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
1.76 X 2.11
1.57 X 1.89 (SHOWN)
1.43 X 1.73
1.33 X 1.60
4225481/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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