Texas Instruments | TLVx171 36-V, Single-Supply, Low-Power Operational Amplifiers for Cost-Sensitive Systems | Datasheet | Texas Instruments TLVx171 36-V, Single-Supply, Low-Power Operational Amplifiers for Cost-Sensitive Systems Datasheet

Texas Instruments TLVx171 36-V, Single-Supply, Low-Power Operational Amplifiers for Cost-Sensitive Systems Datasheet
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TLV171, TLV2171, TLV4171
SBOS783 – SEPTEMBER 2016
TLVx171
36-V, Single-Supply, Low-Power Operational Amplifiers for Cost-Sensitive Systems
1 Features
3 Description
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The 36-V TLVx171 family provides a low-power
option for cost-conscious industrial and personal
electronics systems requiring an electromagnetic
interference (EMI)-hardened, low-noise, single-supply
operational amplifier (op amp) that operates on
supplies ranging from 2.7 V (±1.35 V) to 36 V
(±18 V). The single-channel TLV171, dual-channel
TLV2171, and quad-channel TLV4171 provide low
offset, drift, quiescent current balanced with high
bandwidth for the power. The devices are available in
micropackages for space-constrained systems and
feature identical specifications for maximum design
flexibility.
1
Supply Range: 2.7 V to 36 V, ±1.35 V to ±18 V
Low Noise: 16 nV/√Hz
Low Offset Drift: ±1 μV/°C (typical)
EMI-Hardened with RFI-Filtered Inputs
Input Range Includes the Negative Supply
Unity-Gain Stable: 200-pF Capacitive Load
Rail-to-Rail Output
Gain Bandwidth: 3 MHz
Low Quiescent Current: 525 µA per Amplifier
High Common-Mode Rejection: 105 dB (typical)
Low Bias Current: 10 pA
2 Applications
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•
•
•
•
•
•
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Transducers
Currency Counters
AC-DC Converters
Power Modules
Inverters
Test Equipment
Battery-Powered Instruments
TFT-LCD Drive Circuits
Active Filters
Unlike most op amp, which are specified at only one
supply voltage, the TLVx171 family is specified from
2.7 V to 36 V. Input signals beyond the supply rails
do not cause phase reversal. The TLVx171 family is
stable with capacitive loads up to 200 pF. The input
can operate 100 mV below the negative rail and
within 2 V of the top rail during normal operation.
These devices can operate with a full rail-to-rail input
100 mV beyond the top rail, but with reduced
performance within 2 V of the top rail.
The TLVx171 op amp family is specified from –40°C
to +125°C.
Device Information(1)
PART NUMBER
TLV171
TLV2171
TLV4171
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
SOT-23 (5)
2.90 mm × 1.60 mm
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (14)
8.65 mm × 3.91 mm
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Offset Voltage vs Common-Mode Voltage
Offset Voltage vs Power Supply
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV171, TLV2171, TLV4171
SBOS783 – SEPTEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
5
5
5
6
6
6
7
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information: TLV171 ...................................
Thermal Information: TLV2171 .................................
Thermal Information: TLV4171 .................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
7.4 Device Functional Modes........................................ 19
8
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application .................................................. 20
9 Power Supply Recommendations...................... 22
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 23
11 Device and Documentation Support ................. 24
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Description................................................. 15
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
25
25
25
25
25
25
25
12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
2
DATE
REVISION
NOTES
September 2016
*
Initial release.
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5 Pin Configuration and Functions
TLV171: DBV Package
5-Pin SOT-23
Top View
OUT
1
V-
2
+IN
3
TLV171: D Package
8-Pin SOIC
Top View
V+
5
4
NC(1)
1
8
NC(1)
-IN
2
7
V+
+IN
3
6
OUT
V-
4
5
NC(1)
-IN
Pin Functions: TLV171
PIN
NAME
TLV171
I/O
DESCRIPTION
DBV
D
IN–
4
2
I
Negative (inverting) input
IN+
3
3
I
Positive (noninverting) input
NC
(1)
—
1, 5, 8
—
No internal connection (can be left floating)
OUT
1
6
O
Output
V+
5
7
—
Positive (highest) power supply
V–
2
4
—
Negative (lowest) power supply
(1)
NC indicates no internal connection.
TLV2171: D and DGK Packages
8-Pin SOIC and VSSOP
Top View
OUT A
1
8
V+
-IN A
2
7
OUT B
+IN A
3
6
-IN B
V-
4
5
+IN B
Pin Functions: TLV2171
PIN
NAME
TLV2171
I/O
DESCRIPTION
D
DGK
–IN A
2
2
I
Inverting input, channel A
–IN B
6
6
I
Inverting input, channel B
+IN A
3
3
I
Noninverting input, channel A
+IN B
5
5
I
Noninverting input, channel B
OUT A
1
1
O
Output, channel A
OUT B
7
7
O
Output, channel B
V–
4
4
—
Negative (lowest) power supply
V+
8
8
—
Positive (highest) power supply
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TLV4171: D and PW Packages
14-Pin SOIC and TSSOP
Top View
OUT A
1
14
OUT D
-IN A
2
13
-IN D
+IN A
3
12
+IN D
V+
4
11
V-
+IN B
5
10
+IN C
-IN B
6
9
-IN C
OUT B
7
8
OUT C
Pin Functions: TLV4171
PIN
I/O
DESCRIPTION
NAME
D
PW
–IN A
2
2
I
Inverting input, channel A
+IN A
3
3
I
Noninverting input, channel A
–IN B
6
6
I
Inverting input, channel B
+IN B
5
5
I
Noninverting input, channel B
–IN C
9
9
I
Inverting input, channel C
+IN C
10
10
I
Noninverting input, channel C
–IN D
13
13
I
Inverting input, channel D
+IN D
12
12
I
Noninverting input, channel D
OUT A
1
1
O
Output, channel A
OUT B
7
7
O
Output, channel B
OUT C
8
8
O
Output, channel C
OUT D
14
14
O
Output, channel D
V–
11
11
—
Negative (lowest) power supply
V+
4
4
—
Positive (highest) power supply
4
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range, unless otherwise noted. (1)
MIN
MAX
–20
20
Signal input pin
(V−) − 0.5
(V+) + 0.5
Signal input pin
–10
10
Supply voltage, V+ to V−
Voltage
Current
Output short-circuit (2)
Operating, TA
Temperature
(2)
V
mA
Continuous
–55
150
Junction, TJ
150
Storage, Tstg
(1)
UNIT
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±750
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage (V+ – V–)
Single supply
Dual supply
Specified temperature
NOM
MAX
2.7
36
±1.35
±18
–40
+125
UNIT
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V
°C
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6.4 Thermal Information: TLV171
TLV171
THERMAL METRIC (1)
D (SOIC)
DBV (SOT-23)
8 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
149.5
245.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
97.9
133.9
°C/W
RθJB
Junction-to-board thermal resistance
87.7
83.6
°C/W
ψJT
Junction-to-top characterization parameter
35.5
18.2
°C/W
ψJB
Junction-to-board characterization parameter
89.5
83.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: TLV2171
TLV2171
THERMAL METRIC (1)
D (SOIC)
DGK (VSSOP)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
134.3
175.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
72.1
74.9
°C/W
RθJB
Junction-to-board thermal resistance
60.6
22.2
°C/W
ψJT
Junction-to-top characterization parameter
18.2
1.6
°C/W
ψJB
Junction-to-board characterization parameter
53.8
22.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: TLV4171
TLV4171
THERMAL METRIC
(1)
D (SOIC)
PW (TSSOP)
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
93.2
106.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
51.8
24.4
°C/W
RθJB
Junction-to-board thermal resistance
49.4
59.3
°C/W
ψJT
Junction-to-top characterization parameter
13.5
0.6
°C/W
ψJB
Junction-to-board characterization parameter
42.2
54.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.7 Electrical Characteristics
at TA = 25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.75
±2.7
UNIT
OFFSET VOLTAGE
TA = 25°C
VOS
Input offset voltage
dVOS/dT
Input offset voltage drift
TA = –40°C to +125°C
PSRR
Input offset voltage vs power supply
VS = 4 V to 36 V, TA = –40°C to +125°C
TA = –40°C to +125°C
mV
±3.0
1
90
µV/°C
105
dB
±10
pA
±4
pA
3
µVPP
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
NOISE
Input voltage noise
en
Input voltage noise density
f = 0.1 Hz to 10 Hz
f = 100 Hz
27
f = 1 kHz
16
nV/√Hz
INPUT VOLTAGE
Common-mode voltage range (1)
VCM
CMRR
Common-mode rejection ratio
(V–) – 0.1
VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TA = –40°C to +125°C
94
(V+) – 2
V
105
dB
INPUT IMPEDANCE
Differential
100 || 3
Common-mode
MΩ || pF
6 || 3
1012 Ω || pF
130
dB
3.0
MHz
1.5
V/µs
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
VS = 36 V,
(V–) + 0.35 V < VO < (V+) – 0.35 V,
TA = –40°C to +125°C
94
FREQUENCY RESPONSE
GBP
Gain bandwidth product
SR
Slew rate
tS
THD+N
(1)
G = +1
To 0.1%, VS = ±18 V, G = +1, 10-V step
6
Settling time
To 0.01% (12 bits), VS = ±18 V, G = +1,
10-V step
10
Overload recovery time
VIN × gain > VS
Total harmonic distortion + noise
G = +1, f = 1 kHz, VO = 3 VRMS
2
µs
µs
0.0002%
The input range can be extended beyond (V+) – 2 V up to V+. See the Typical Characteristics and Application and Implementation
sections for additional information.
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Electrical Characteristics (continued)
at TA = 25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
VO
Voltage output swing
Positive rail, VS = ±18 V, RL = 10 kΩ,
TA = 25°C
160
mV
Negative rail, VS = ±18 V, RL = 10 kΩ,
TA = 25°C
90
mV
RL = 10 kΩ, AOL ≥ 94 dB,
TA = –40°C to +125°C
ISC
Short-circuit current
CLOAD
Capacitive load drive
RO
Open-loop output resistance
(V–) + 0.35
(V+) – 0.35
25
mA
–35
See Typical Characteristics
f = 1 MHz, IO = 0 A
V
pF
150
Ω
POWER SUPPLY
VS
Specified voltage range
IQ
Quiescent current per amplifier
2.7
IO = 0 A, TA = –40°C to +125°C
525
36
V
695
µA
TEMPERATURE
8
Specified range
–40
125
°C
Operating range
–55
150
°C
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6.8 Typical Characteristics
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Table 1. Characteristic Performance Measurements
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
Figure 1
Offset Voltage vs Common-Mode Voltage
Figure 2
Offset Voltage vs Common-Mode Voltage (Upper Stage)
Figure 3
Input Bias Current and Input Offset Current vs Temperature
Figure 4
Output Voltage Swing vs Output Current (Maximum Supply)
Figure 5
CMRR and PSRR vs Frequency (Referred-to-Input)
Figure 6
0.1-Hz to 10-Hz Noise
Figure 7
Input Voltage Noise Spectral Density vs Frequency
Figure 8
Quiescent Current vs Supply Voltage
Figure 9
Open-Loop Gain and Phase vs Frequency
Figure 10
Closed-Loop Gain vs Frequency
Figure 11
Open-Loop Gain vs Temperature
Figure 12
Open-Loop Output Impedance vs Frequency
Figure 13
Small-Signal Overshoot vs Capacitive Load
Figure 14, Figure 15
No Phase Reversal
Figure 16
Small-Signal Step Response (100 mV)
Figure 17, Figure 18
Large-Signal Step Response
Figure 19, Figure 20
Large-Signal Settling Time (10-V Positive Step)
Figure 21
Large-Signal Settling Time (10-V Negative Step)
Figure 22
Short-Circuit Current vs Temperature
Figure 23
Maximum Output Voltage vs Frequency
Figure 24
EMIRR IN+ vs Frequency
Figure 25
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16
1000
14
800
600
12
400
10
200
VOS (mV)
Percentage of Amplifiers (%)
SBOS783 – SEPTEMBER 2016
8
6
0
-200
4
-400
2
-600
-800
0
VCM = -18.1 V
-1200
-1100
-1000
-900
-800
-700
-600
-500
-400
-300
-200
-100
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
-1000
-20
-15
-10
5
10
15
20
VCM (V)
10 typical units shown
Distribution taken from 3500 amplifiers
Figure 2. Offset Voltage vs Common-Mode Voltage
Figure 1. Offset Voltage Production Distribution
10000
10000
IB+
8000
Input Bias Current (pA)
6000
4000
VOS (mV)
0
-5
Offset Voltage (mV)
2000
0
-2000
Normal
Operation
-4000
VCM = +18.1V
-6000
IB-
1000
IB
IOS
100
10
IOS
1
-8000
-10000
15.5
0
16
16.5
17
17.5
18
18.5
-75
-50
0
-25
25
50
75
100
125
150
Temperature (°C)
VCM (V)
10 typical units shown
Figure 3. Offset Voltage vs Common-Mode Voltage
(Upper Stage)
Figure 4. Input Bias Current and Input Offset Current vs
Temperature
140
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
18
Output Voltage (V)
17
16
15
14.5
-14.5
-15
-40°C
+25°C
+85°C
+125°C
-16
-17
120
100
80
60
40
+PSRR
-PSRR
CMRR
20
0
-18
0
2
4
6
8
10
12
14
16
1
10
Figure 5. Output Voltage Swing vs Output Current
(Maximum Supply)
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Output Current (mA)
Figure 6. CMRR and PSRR vs Frequency
(Referred-to Input)
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1mV/div
Voltage Noise Density (nV/ÖHz)
1000
100
10
1
1
10
100
Time (1s/div)
1k
Figure 7. 0.1-Hz to 10-Hz Noise
100k
1M
Figure 8. Input Voltage Noise Spectral Density vs Frequency
0.6
180
180
Gain
0.55
135
135
Phase
0.45
0.4
90
90
45
45
0
0
Phase (°)
Gain (dB)
0.5
IQ (mA)
10k
Frequency (Hz)
0.35
0.3
Specified Supply-Voltage Range
0.25
-45
0
4
8
12
16
20
24
28
32
36
1
10
100
Supply Voltage (V)
1k
10k
100k
-45
10M
Frequency (Hz)
Figure 9. Quiescent Current vs Supply Voltage
Figure 10. Open-Loop Gain and Phase vs Frequency
3
25
20
VS = 2.7V
VS = 4V
VS = 36V
2.5
15
2
AOL (mV/V)
10
Gain (dB)
1M
5
0
1.5
1
-5
-10
G = 10
G=1
G = -1
-15
0.5
0
-20
10k
100k
1M
10M
100M
-75
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Frequency (Hz)
5 typical units shown
Figure 11. Closed-Loop Gain vs Frequency
Figure 12. Open-Loop Gain vs Temperature
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1M
100k
ZO (W)
10k
1k
100
G = +1
+18V
10
ROUT
W
W
W
1
1m
1
10
100
1k
10k
100k
1M
RL
-18V
CL
10M
Frequency (Hz)
100-mV output step, RL = 10 kΩ
Figure 13. Open-Loop Output Impedance vs Frequency
Figure 14. Small-Signal Overshoot vs Capacitive Load
+18V
5V/div
-18V
37VPP
Sine Wave
(±18.5V)
RI = 10kW
RF = 10kW
G = -1
+18V
ROUT
W
W
W
CL
-18V
Time (100ms/div)
100-mV output step, RL = 10 kΩ
Figure 16. No Phase Reversal
Figure 15. Small-Signal Overshoot vs Capacitive Load
+18V
G = +1
-18V
RL
CL = 100pF
20mV/div
20mV/div
CL
RI
= 2kW
RF
= 2kW
+18V
CL
-18V
G = -1
Time (20ms/div)
Time (1ms/div)
RL = 10 kΩ, CL = 100 pF
Figure 17. Small-Signal Step Response (100 mV)
12
Figure 18. Small-Signal Step Response (100 mV)
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+18V
G = +1
-18V
RL
2V/div
20mV/div
CL
Time (4ms/div)
Time (1ms/div)
G = –1, RL = 10 kΩ, CL = 100 pF
G = +1, RL = 10 kΩ, CL = 100 pF
Figure 20. Large-Signal Step Response
10
8
8
6
6
4
D From Final Value (mV)
D From Final Value (mV)
Figure 19. Large-Signal Step Response
10
12-Bit Settling
2
0
-2
(±1/2LSB = ±0.024%)
-4
-6
-8
4
12-Bit Settling
2
0
-2
(±1/2LSB = ±0.024%)
-4
-6
-8
-10
-10
0
4
8
12
16
20
24
28
32
36
0
4
8
12
16
Time (ms)
10-V positive step, G = –1
24
28
32
36
10-V negative step, G = –1
Figure 21. Large-Signal Settling Time
Figure 22. Large-Signal Settling Time
15
50
VS = ±15V
45
12.5
Output Voltage (VPP)
ISC, Sink
40
35
ISC (mA)
20
Time (ms)
30
25
20
ISC, Source
15
10
10
Maximum output voltage without
slew-rate induced distortion.
7.5
VS = ±5V
5
2.5
5
VS = ±1.35V
0
0
-75
-50
-25
0
25
50
75
100
125
150
10k
Figure 23. Short-Circuit Current vs Temperature
100k
1M
10M
Frequency (Hz)
Temperature (°C)
Figure 24. Maximum Output Voltage vs Frequency
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120
EMIRR IN+ (db)
100
80
60
40
20
0
10
100
1k
Frequency (MHz)
10k
Figure 25. EMIRR IN+ vs Frequency
14
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7 Detailed Description
7.1 Overview
The TLVx171 family of operational amplifiers provides high overall performance, making these devices ideal for
many general-purpose applications. The excellent offset drift of only 2 μV/°C provides excellent stability over the
entire temperature range. In addition, the device family offers very good overall performance with high commonmode rejection ratio (CMRR), power-supply rejection ratio (PSRR), and open-loop voltage gain (AOL).
7.2 Functional Block Diagram
PCH
FF Stage
Ca
Cb
IN+
PCH
Input Stage
2nd Stage
Output
Stage
OUT
IN-
NCH
Input Stage
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Operating Characteristics
The TLVx171 family of amplifiers is specified for operation from 2.7 V to 36 V, single supply (±1.35 V to ±18 V,
dual supply). Many of the specifications apply from –40°C to +125°C. Parameters that can exhibit significant
variance with regard to operating voltage or temperature are presented in the Typical Characteristics section.
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Feature Description (continued)
7.3.2 Phase-Reversal Protection
The TLVx171 family has an internal phase-reversal protection. Many operational amplifiers exhibit a phase
reversal when the input is driven beyond the linear common-mode range. This condition is most often
encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range,
causing the output to reverse into the opposite rail. The input of the TLVx171 prevents phase reversal with
excessive common-mode voltage. Instead, the output limits into the appropriate rail. This performance is shown
in Figure 26.
+18V
5V/div
-18V
37VPP
Sine Wave
(±18.5V)
Time (100ms/div)
Figure 26. No Phase Reversal
7.3.3 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits for protection from
accidental ESD events both before and during product assembly.
A good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is helpful.
Figure 27 illustrates the ESD circuits contained in the TLVx171 (indicated by the dashed line area). The ESD
protection circuitry involves several current-steering diodes connected from the input and output pins and routed
back to the internal power-supply lines, where the diodes meet at an absorption device internal to the operational
amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
16
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Feature Description (continued)
TVS
+
±
RF
+VS
R1
IN±
250 Ÿ
RS
IN+
250 Ÿ
+
Power-Supply
ESD Cell
ID
VIN
RL
+
±
+
±
±VS
TVS
Copyright © 2016, Texas Instruments Incorporated
Figure 27. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, highcurrent pulse when discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device can activate. The absorption
device has a trigger, or threshold voltage, that is above the normal operating voltage of the TLVx171 but below
the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly activates
and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit (as shown in Figure 27), the ESD protection components
are intended to remain inactive and do not become involved in the application circuit operation. However,
circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. If this
condition occurs, there is a risk that some internal ESD protection circuits can turn on and conduct current. Any
such current flow occurs through steering-diode paths and rarely involves the absorption device.
Figure 27 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the
current, one of the upper input steering diodes conducts and directs current to V+. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
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Feature Description (continued)
Another common question involves what happens to the amplifier if an input signal is applied to the input when
the power supplies (V+ or V–) are at 0 V. Again, this question depends on the supply characteristic when at 0 V,
or at a level below the input signal amplitude. If the supplies appear as high impedance, then the input source
supplies the operational amplifier current through the current-steering diodes. This state is not a normal bias
condition; most likely, the amplifier does not operate normally. If the supplies are low impedance, then the current
through the steering diodes can become quite high. The current level depends on the ability of the input source
to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the
supply pins; see Figure 27. Select the Zener voltage so that the diode does not turn on during normal operation.
However, the Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise
above the safe-operating, supply-voltage level.
The TLVx171 input pins are protected from excessive differential voltage with back-to-back diodes; see
Figure 27. In most circuit applications, the input protection circuitry has no effect. However, in low-gain or G = 1
circuits, fast-ramping input signals can forward-bias these diodes because the output of the amplifier cannot
respond rapidly enough to the input ramp. If the input signal is fast enough to create this forward-bias condition,
limit the input signal current to 10 mA or less. If the input signal current is not inherently limited, an input series
resistor can be used to limit the input signal current. This input series resistor degrades the low-noise
performance of the TLVx171. Figure 27 illustrates an example configuration that implements a current-limiting
feedback resistor.
7.3.4 Capacitive Load and Stability
The dynamic characteristics of the TLVx171 are optimized for common operating conditions. The combination of
low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and can lead to gain
peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output. The simplest way
to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series with the output.
Figure 28 and Figure 29 show graphs of small-signal overshoot versus capacitive load for several values of
ROUT. Also, see applications bulletin AB-028, Feedback Plots Define Op Amp AC Performance for details of
analysis techniques and application circuits.
G = +1
+18V
RI = 10kW
RF = 10kW
ROUT
G = -1
+18V
W
W
W
-18V
RL
100-mV output step, G = 1, RL = 10 kΩ
Figure 28. Small-Signal Overshoot vs Capacitive Load
18
W
W
W
CL
ROUT
CL
-18V
100-mV output step, G = –1, RL = 10 kΩ
Figure 29. Small-Signal Overshoot vs Capacitive Load
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7.4 Device Functional Modes
7.4.1 Common-Mode Voltage Range
The input common-mode voltage range of the TLVx171 family extends 100 mV below the negative rail and within
2 V of the top rail for normal operation.
This device family can operate with a full rail-to-rail input 100 mV beyond the top rail, but with reduced
performance within 2 V of the top rail.
7.4.2 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from the
saturated state to the linear state. The output devices of the operational amplifier enter the saturation region
when the output voltage exceeds the rated operating voltage, either resulting from the high input voltage or the
high gain. After the device enters the saturation region, the charge carriers in the output devices need time to
return back to the normal state. After the charge carriers return back to the equilibrium state, the device begins to
slew at the normal slew rate. Thus, the propagation delay in case of an overload condition is the sum of the
overload recovery time and the slew time. The overload recovery time for the TLVx171 is approximately 2 µs.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLVx171 family of operational amplifiers provides high overall performance in a large number of generalpurpose applications. As with all amplifiers, applications with noisy or high-impedance power supplies require
decoupling capacitors placed close to the device pins. In most cases, 0.1-µF capacitors are adequate. Follow the
additional recommendations in the Layout Guidelines section in order to achieve the maximum performance from
this device. Many applications can introduce capacitive loading to the output of the amplifier (potentially causing
instability). One method of stabilizing the amplifier in such applications is to add an isolation resistor between the
amplifier output and the capacitive load. The design process for selecting this resistor is given in the Typical
Application section.
8.2 Typical Application
This circuit can be used to drive capacitive loads such as cable shields, reference buffers, MOSFET gates, and
diodes. The circuit uses an isolation resistor (RISO) to stabilize the output of an operational amplifier. RISO
modifies the open-loop gain of the system to ensure that the circuit has sufficient phase margin.
+VS
VOUT
RISO
+
VIN
+
±
CLOAD
-VS
Copyright © 2016, Texas Instruments Incorporated
Figure 30. Unity-Gain Buffer With RISO Stability Compensation
8.2.1 Design Requirements
The design requirements are:
• Supply voltage: 30 V (±15 V)
• Capacitive loads: 100 pF, 1000 pF, 0.01 μF, 0.1 μF, and 1 μF
• Phase margin: 45° and 60°
8.2.2 Detailed Design Procedure
Figure 30 shows a unity-gain buffer driving a capacitive load. Equation 1 shows the transfer function for the
circuit in Figure 30. Not shown in Figure 30 is the open-loop output resistance of the operational amplifier, RO.
1 + CLOAD × RISO × s
T(s) =
1 + Ro + RISO × CLOAD × s
(1)
The transfer function in Equation 1 has a pole and a zero. The frequency of the pole (fp) is determined by (RO +
RISO) and CLOAD. Components RISO and CLOAD determine the frequency of the zero (fz). A stable system is
obtained by selecting RISO such that the rate of closure (ROC) between the open-loop gain (AOL) and 1/β is 20
dB/decade. Figure 31 illustrates this concept. The 1/β curve for a unity-gain buffer is 0 dB.
20
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Typical Application (continued)
120
AOL
100
1
fp
2 u Πu RISO
Gain (dB)
80
60
Ro
u CLOAD
40 dB
fz
40
1
2 u Πu RISO u CLOAD
1 dec
1/
20
ROC
20 dB
dec
0
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Figure 31. Unity-Gain Amplifier With RISO Compensation
ROC stability analysis is typically simulated. The validity of the analysis depends on multiple factors, especially
the accurate modeling of RO. In addition to simulating the ROC, a robust stability analysis includes a
measurement of overshoot percentage and ac gain peaking of the circuit using a function generator,
oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. Table 2
shows the overshoot percentage and ac gain peaking that correspond to phase margins of 45° and 60°. For
more details on this design and other alternative devices that can be used in place of the TLV171, see the
Precision Design, Capacitive Load Drive Solution Using an Isolation Resistor.
Table 2. Phase Margin versus Overshoot and AC Gain
Peaking
PHASE
MARGIN
OVERSHOOT
AC GAIN PEAKING
45°
23.3%
2.35 dB
60°
8.8%
0.28 dB
8.2.3 Application Curve
Using the described methodology, the values of RISO that yield phase margins of 45º and 60º for various
capacitive loads were determined. The results are shown in Figure 32.
10000
45° Phase Margin
Isolation Resistor (RISO,
)
60° Phase Margin
1000
100
10
0.1
1
10
100
Capacitive Load (nF)
1000
C002
Figure 32. Isolation Resistor Required for Various Capacitive Loads to Achieve a Target Phase Margin
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9 Power Supply Recommendations
The TLVx171 is specified for operation from 2.7 V to 36 V (±1.35 V to ±18 V); many specifications apply from
–40°C to +85°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are presented in the Typical Characteristics section.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings table.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the
operational amplifier itself. Bypass capacitors are used to reduce the coupled noise by providing lowimpedance power sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds, paying attention to the flow of the ground current.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 34, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
22
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10.2 Layout Example
+
VIN
VOUT
RG
RF
Copyright © 2016, Texas Instruments Incorporated
Figure 33. Schematic Representation
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors
VS+
RF
N/C
N/C
GND
±IN
V+
VIN
+IN
OUTPUT
V±
N/C
RG
Use low-ESR,
ceramic bypass
capacitor
GND
VS±
GND
Use low-ESR, ceramic
bypass capacitor
VOUT
Ground (GND) plane on another layer
Figure 34. Operational Amplifier Board Layout for a Noninverting Configuration
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ is
a free, fully-functional version of the TINA software, preloaded with a library of macromodels in addition to a
range of both passive and active models. TINA-TI™ provides all the conventional dc, transient, and frequency
domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI™ offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, thus creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or the TINA-TI™
software be installed. Download the free TINA-TI™ software from the TINA-TI™ folder.
11.1.1.2 DIP Adapter EVM
The DIP Adapter EVM tool provides an easy, low-cost way to prototype small surface-mount devices. The
evaluation tool these TI packages: D or U (SOIC-8), PW (TSSOP-8), DGK (VSSOP-8), DBV (SOT23-6, SOT235, and SOT23-3), DCK (SC70-6 and SC70-5), and DRL (SOT563-6). The DIP adapter EVM can also be used
with terminal strips or can be wired directly to existing circuits.
11.1.1.3 Universal Op Amp EVM
The Universal Op Amp EVM is a series of general-purpose, blank circuit boards that simplify prototyping circuits
for a variety of device package types. The evaluation module board design allows many different circuits to be
constructed easily and quickly. Five models are offered, with each model intended for a specific package type.
PDIP, SOIC, MSOP, TSSOP, and SOT23 packages are all supported.
NOTE
These boards are unpopulated, so users must provide their own devices. TI recommends
requesting several op amp device samples when ordering the Universal Op Amp EVM.
11.1.1.4 TI Precision Designs
TI precision designs are analog solutions created by TI’s precision analog applications experts and offer the
theory of operation, component selection, simulation, a complete PCB schematic and layout, bill of materials, and
measured performance of many useful circuits. TI precision designs are available online at
http://www.ti.com/ww/en/analog/precision-designs/.
11.1.1.5 WEBENCH® Filter Designer
The WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The
WEBENCH® filter designer enables optimized filter designs to be created by using a selection of TI operational
amplifiers and passive components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® design center, the WEBENCH® filter designer allows
complete multistage active filter solutions to be designed, optimized, and simulated within minutes.
24
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11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
Feedback Plots Define Op Amp AC Performance Application Bulletin (SBOA015)
11.3 Related Links
Table 3 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLV171
Click here
Click here
Click here
Click here
Click here
TLV2171
Click here
Click here
Click here
Click here
Click here
TLV4171
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 Trademarks
TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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25
PACKAGE OPTION ADDENDUM
www.ti.com
2-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV171IDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
14RT
TLV171IDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
14RT
TLV171IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLV171
TLV2171IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
14OV
TLV2171IDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
14OV
TLV2171IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TL2171
TLV4171ID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
TLV4171
TLV4171IDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
TLV4171
TLV4171IPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLV4171
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-Apr-2017
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TLV171IDBVR
SOT-23
DBV
5
3000
180.0
TLV171IDBVT
SOT-23
DBV
5
250
TLV171IDR
SOIC
D
8
2500
TLV2171IDGKR
VSSOP
DGK
8
TLV2171IDGKT
VSSOP
DGK
TLV2171IDR
SOIC
TLV4171IDR
SOIC
TLV4171IPWR
TSSOP
B0
(mm)
K0
(mm)
P1
(mm)
8.4
3.23
3.17
1.37
4.0
180.0
8.4
3.23
3.17
1.37
330.0
12.4
6.4
5.2
2.1
2500
330.0
12.4
5.3
3.4
8
250
330.0
12.4
5.3
D
8
2500
330.0
12.4
D
14
2500
330.0
16.4
PW
14
2000
330.0
12.4
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
8.0
Q3
4.0
8.0
Q3
8.0
12.0
Q1
1.4
8.0
12.0
Q1
3.4
1.4
8.0
12.0
Q1
6.4
5.2
2.1
8.0
12.0
Q1
6.5
9.0
2.1
8.0
16.0
Q1
6.9
5.6
1.6
8.0
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV171IDBVR
SOT-23
DBV
5
3000
202.0
201.0
28.0
TLV171IDBVT
SOT-23
DBV
5
250
223.0
270.0
35.0
TLV171IDR
SOIC
D
8
2500
367.0
367.0
35.0
TLV2171IDGKR
VSSOP
DGK
8
2500
366.0
364.0
50.0
TLV2171IDGKT
VSSOP
DGK
8
250
366.0
364.0
50.0
TLV2171IDR
SOIC
D
8
2500
367.0
367.0
35.0
TLV4171IDR
SOIC
D
14
2500
367.0
367.0
38.0
TLV4171IPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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