Texas Instruments | OPAx330 50-μV VOS, 0.25-μV/°C, 35-μA CMOS Operational Amplifiers Zero-Drift Series (Rev. G) | Datasheet | Texas Instruments OPAx330 50-μV VOS, 0.25-μV/°C, 35-μA CMOS Operational Amplifiers Zero-Drift Series (Rev. G) Datasheet

Texas Instruments OPAx330 50-μV VOS, 0.25-μV/°C, 35-μA CMOS Operational Amplifiers Zero-Drift Series (Rev. G) Datasheet
Sample &
Buy
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
Reference
Design
OPA330, OPA2330, OPA4330
SBOS432G – AUGUST 2008 – REVISED AUGUST 2016
OPAx330 50-μV VOS, 0.25-μV/°C, 35-μA CMOS Operational Amplifiers
Zero-Drift Series
1 Features
3 Description
•
•
•
•
•
•
•
•
•
The OPA330 series of CMOS operational amplifiers
offer precision performance at a very competitive
price. These devices are members of the Zero-Drift
family of amplifiers which use a proprietary autocalibration technique to simultaneously provide low
offset voltage (50-μV maximum) and near-zero drift
over time and temperature at only 35 μA (maximum)
of quiescent current. The OPA330 family features railto-rail input and output in addition to near-flat 1/f
noise, making this amplifier ideal for many
applications and much easier to design into a system.
These devices are optimized for low-voltage
operation as low as 1.8 V (±0.9 V) and up to 5.5 V
(±2.75 V).
1
Unmatched Price Performance
Low Offset Voltage: 50 µV (Maximum)
Zero Drift: 0.25 µV/°C (Maximum)
Low Noise: 1.1 µVPP, 0.1 Hz to 10 Hz
Quiescent Current: 35 µA (Maximum)
Supply Voltage: 1.8 V to 5.5 V
Rail-to-Rail Input and Output
Internal EMI Filtering
microSize Packages: DSBGA, SC70, VQFN
2 Applications
•
•
•
•
•
•
•
Battery-Powered Instruments
Temperature Measurements
Transducer Applications
Electronic Scales
Medical Instrumentation
Handheld Test Equipment
Current Sense
The OPA330 (single version) is available in the 5-pin
DSBGA, 5-pin SC70, 5-pin SOT-23, and 8-pin SOIC
packages. The OPA2330 (dual version) is offered in 3
mm × 3 mm, 8-pin SON, 8-pin VSSOP, and 8-pin
SOIC packages. The OPA4330 is offered in the
standard 14-pin SOIC and 14-pin TSSOP packages,
as well as in the space-saving 14-pin VQFN package.
All versions are specified for operation from –40°C to
125°C.
Device Information(1)
PART NUMBER
OPA330
Bidirectional, Low-Side Current Sense
VCC
VCC
R5
–
OPA2330
+
R6
ILOAD
OPA4330
R2
R1
VBUS
+
±
+
RSHUNT
VOUT
–
R3
VCC
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
SOT (5)
2.90 mm × 1.60 mm
SC70 (5)
2.00 mm × 1.25 mm
DSBGA (5)
0.00 mm × 0.00 mm
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
SON (8)
3.00 mm × 3.00 mm
SOIC (14)
8.65 mm × 3.91 mm
TSSOP (14)
5.00 mm × 4.40 mm
VQFN (14)
3.50 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
RL
R4
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA330, OPA2330, OPA4330
SBOS432G – AUGUST 2008 – REVISED AUGUST 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configurations and Functions .......................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
1
1
1
2
4
4
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information: OPA330 .................................. 8
Thermal Information: OPA2330 ................................ 8
Thermal Information: OPA4330 ................................ 8
Electrical Characteristics........................................... 9
Typical Characteristics ............................................ 10
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 14
9
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application .................................................. 17
9.3 System Examples ................................................... 19
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 22
12 Device and Documentation Support ................. 23
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
Device Support ....................................................
Documentation Support .......................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
24
24
24
24
24
24
24
13 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (June 2016) to Revision G
Page
•
Changed Pin Functions: OPA330 so each pin has a separate row ....................................................................................... 4
•
Changed position of Input Voltage Range, CMRR parameter specification values in Electrical Characteristics table.......... 9
•
Changed position of Open-Loop Gain, AOL parameter specification values in Electrical Characteristics table ..................... 9
Changes from Revision E (February 2011) to Revision F
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Added current package designators to second paragraph of Description section ................................................................ 1
•
Removed Package Information table, see POA at the end of the datasheet......................................................................... 1
•
Changed Product Family Package Comparison table to Device Comparison table; moved from page 1 of document ........ 4
Changes from Revision D (June 2010) to Revision E
Page
•
Changed document status from Mixed Status to Production Data ........................................................................................ 1
•
Deleted footnote 2 from the Package Information table......................................................................................................... 1
•
Added remaining thermal information data............................................................................................................................. 8
2
Submit Documentation Feedback
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: OPA330 OPA2330 OPA4330
OPA330, OPA2330, OPA4330
www.ti.com
SBOS432G – AUGUST 2008 – REVISED AUGUST 2016
Changes from Revision C (October 2009) to Revision D
Page
•
Added last Applications bullet................................................................................................................................................. 1
•
Deleted footnote 2 and shading from all packages except QFN-14; moved WCSP-5, SOIC-14, and TSSOP-14
packages to Production Data status; and added package marking information to Package Information table ..................... 1
•
Deleted footnote 1 from Product Family Package Comparison table .................................................................................... 4
•
Moved TSSOP-14 thermal resistance to MSOP-8, SOIC-8 thermal resistance parameter in Electrical Characteristics
table ........................................................................................................................................................................................ 9
•
Deleted SOIC-14 and QFN-14 rows from Temperature Range section in Electrical Characteristics table ........................... 9
•
Added OPA330YFF, OPA4330 Input Bias Current parameter to Electrical Characteristics table ......................................... 9
•
Added Input Voltage Range, OPA330YFF, OPA4330 Common-Mode Rejection Ratio parameter to Electrical
Characteristics table ............................................................................................................................................................... 9
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: OPA330 OPA2330 OPA4330
Submit Documentation Feedback
3
OPA330, OPA2330, OPA4330
SBOS432G – AUGUST 2008 – REVISED AUGUST 2016
www.ti.com
5 Device Comparison Table
PACKAGE-LEADS
DEVICE
NO OF
CHANNELS
DSBGA
SOIC
SOT
SC70
VSSOP
SON
VQFN
TSSOP
OPA330
1
5
8
5
5
—
—
—
—
OPA2330
2
—
8
—
—
8
8
—
—
OPA4330
4
—
14
—
—
—
—
14
14
6 Pin Configurations and Functions
OPA330: D Package
8-Pin SOIC
Top View
(1)
1
8
NC
-IN
2
7
V+
+IN
3
6
OUT
V-
4
5
NC
NC
(1)
(1)
OPA330: DCK Package
5-Pin SC70
Top View
(1)
+IN
1
V-
2
-IN
3
NC denotes no internal connection.
5
V+
4
OUT
OPA330: YFF Package
5-Pin DSBGA
Top View
OPA330: DBV Package
5-Pin SOT-23
Top View
C3
C1
OUT
INB2
OUT
1
V-
2
+IN
3
5
VS-
V+
A3
A1
VS+
4
IN+
-IN
Pin Functions: OPA330
PIN
NAME
–IN
SOIC
SOT-23
SC70
DSBGA
2
4
3
C1
I/O
DESCRIPTION
I
Negative (inverting) input
Positive (noninverting) input
+IN
3
3
1
A1
I
NC
1, 5, 8
—
—
—
—
No internal connection (can be left floating)
OUT
6
1
4
C3
O
Output
V–
4
2
2
—
—
Negative (lowest) power supply
V+
7
5
5
—
—
Positive (highest) power supply
VS–
—
—
—
B2
—
Negative (lowest) power supply
VS+
—
—
—
A3
—
Positive (highest) power supply
4
Submit Documentation Feedback
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: OPA330 OPA2330 OPA4330
OPA330, OPA2330, OPA4330
www.ti.com
SBOS432G – AUGUST 2008 – REVISED AUGUST 2016
OPA2330: D and DGK Packages
8-Pin SOIC and 8-Pin VSSOP
Top View
OUT A
1
8
V+
7
OUT B
OPA2330: DRB Package
8-Pin SON
Top View
A
-IN A
2
OUT A
1
Exposed
Thermal
Die Pad
on
(1)
Underside
B
+IN A
3
6
-IN B
-IN A
2
V-
4
5
+IN B
+IN A
3
V-
4
(1)
8
V+
7
OUT B
6
-IN B
5
+IN B
Connect thermal die pad to V–.
Pin Functions: OPA2330
PIN
I/O
DESCRIPTION
NAME
SOIC,
VSSOP
SON
–IN A
2
2
I
Negative (inverting) input signal, channel A
+IN A
3
3
I
Positive (noninverting) input signal, channel A
–IN B
6
6
I
Negative (inverting) input signal, channel B
+IN B
5
5
I
Positive (noninverting) input signal, channel B
OUT A
1
1
O
Output channel A
OUT B
7
7
O
Output channel B
V–
4
4
—
Negative (lowest) power supply
V+
8
8
—
Positive (highest) power supply
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: OPA330 OPA2330 OPA4330
Submit Documentation Feedback
5
OPA330, OPA2330, OPA4330
SBOS432G – AUGUST 2008 – REVISED AUGUST 2016
www.ti.com
OPA4330: D Package
14-Pin SOIC
Top View
OUT A
1
-IN A
2
+IN A
OPA4330: PW Package
14-Pin TSSOP
Top View
14
OUT D
13
-IN D
3
12
+IN D
V+
4
11
V-
+IN B
5
10
+IN C
A
D
B
C
-IN B
6
9
-IN C
OUT B
7
8
OUT C
OUT A
1
14
OUT D
-IN A
2
13
-IN D
+IN A
3
12
+IN D
V+
4
11
V-
+IN B
5
10
+IN C
-IN B
6
9
-IN C
OUT B
7
8
OUT C
(1)
OUT A
OUT D
1
14
OPA4330: RGY Package
14-Pin VQFN
Top View
-IN A
2
+IN A
3
V+
4
Exposed
Thermal Die
Pad on
+IN B
5
Underside
-IN B
6
13
-IN D
12
+IN D
11
V-
10
+IN C
9
-IN C
7
8
OUT B
OUT C
(1)
Connect thermal die pad to V–.
Pin Functions: OPA4330
PIN
I/O
DESCRIPTION
NAME
SOIC
TSSOP
VQFN
–IN A
2
2
2
I
Negative (inverting) input signal, channel A
+IN A
3
3
3
I
Positive (noninverting) input signal, channel A
–IN B
6
6
6
I
Negative (inverting) input signal, channel B
+IN B
5
5
5
I
Positive (noninverting) input signal, channel B
–IN C
9
9
9
I
Negative (inverting) input signal, channel C
+IN C
10
10
10
I
Positive (noninverting) input signal, channel C
–IN D
13
13
13
I
Negative (inverting) input signal, channel D
+IN D
12
12
12
I
Positive (noninverting) input signal, channel D
OUT A
1
1
1
O
Output channel A
OUT B
7
7
7
O
Output channel B
OUT C
8
8
8
O
Output channel C
OUT D
14
14
14
O
Output channel D
V–
11
11
11
—
Negative (lowest) power supply
V+
4
4
4
—
Positive (highest) power supply
6
Submit Documentation Feedback
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: OPA330 OPA2330 OPA4330
OPA330, OPA2330, OPA4330
www.ti.com
SBOS432G – AUGUST 2008 – REVISED AUGUST 2016
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply, VS = (V+) – (V–)
Voltage
Signal input terminals
(2)
(TBD should terminal be pin?)
Signal input terminals (2)
Current
(3)
(V+) + 0.3
V
–10
10
mA
150
°C
150
°C
150
°C
–40
Junction, TJ
Storage, Tstg
(2)
V
Continuous
Operating range, TA
(1)
UNIT
7
(V–) –0.3
Output short-circuit (3)
Temperature
MAX
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should
be current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
Machine model (MM)
±400
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
(V+) – (V–)
Supply voltage
TA
Specified temperature
MIN
NOM
MAX
±0.9 (1.8)
±2.5 (5)
±2.75 (5.5)
V
–40
25
125
°C
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: OPA330 OPA2330 OPA4330
UNIT
Submit Documentation Feedback
7
OPA330, OPA2330, OPA4330
SBOS432G – AUGUST 2008 – REVISED AUGUST 2016
www.ti.com
7.4 Thermal Information: OPA330
OPA330
THERMAL METRIC (1)
D (SOIC)
DBV (SOT-23)
DCK (SC70)
YFF (DSBGA)
8 PINS
5 PINS
5 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
140.1
220.8
298.4
130
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
89.8
97.5
65.4
54
°C/W
RθJB
Junction-to-board thermal resistance
80.6
61.7
97.1
51
°C/W
ψJT
Junction-to-top characterization parameter
28.7
7.6
0.8
1
°C/W
ψJB
Junction-to-board characterization parameter
80.1
61.1
95.5
50
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Thermal Information: OPA2330
OPA2330
THERMAL METRIC (1)
D (SOIC)
DGK (VSSOP)
DRB (SON)
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
124
180.3
46.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
73.7
48.1
26.3
°C/W
RθJB
Junction-to-board thermal resistance
64.4
100.9
22.2
°C/W
ψJT
Junction-to-top characterization parameter
18
2.4
1.6
°C/W
ψJB
Junction-to-board characterization parameter
63.9
99.3
22.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
10.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Thermal Information: OPA4330
OPA4330
THERMAL METRIC (1)
D (SOIC)
PW (TSSOP)
RGY (VQFN)
UNIT
14 PINS
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
83.8
120.8
49.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
70.7
34.3
75.3
°C/W
RθJB
Junction-to-board thermal resistance
59.5
62.8
61.9
°C/W
ψJT
Junction-to-top characterization parameter
11.6
1
1.2
°C/W
ψJB
Junction-to-board characterization parameter
37.7
56.5
19.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
4.6
°C/W
(1)
8
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Documentation Feedback
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: OPA330 OPA2330 OPA4330
OPA330, OPA2330, OPA4330
www.ti.com
SBOS432G – AUGUST 2008 – REVISED AUGUST 2016
7.7 Electrical Characteristics
at TA = 25°C, RL = 10 kΩ connected to midsupply, VS = 1.8 V to 5.5 V, and VCM = VOUT = midsupply (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
8
50
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
VS = 5 V
dVOS/dT
Input offset voltage
versus temperature
At TA = –40°C to +125°C
0.02
0.25
µV/°C
PSRR
Input offset voltage
versus power supply
At TA = –40°C to +125°C
1
10
µV/V
Long-term stability (1)
VS = 1.8 V to 5.5 V
See
Channel separation, dc
µV
(1)
0.1
µV/V
INPUT BIAS CURRENT
IB
Input bias current
At 25°C
OPA330YFF,
OPA4330
At TA = –40°C to +125°C
IOS
±200
±500
pA
±70
±300
pA
±300
pA
±400
±1000
pA
±140
±600
pA
Input offset current
At 25°C
Input voltage noise
density
f = 1 kHz
55
nV/√Hz
f = 0.01 Hz to 1 Hz
0.3
µVPP
f = 0.1 Hz to 10 Hz
1.1
µVPP
f = 10 Hz
100
fA/√Hz
OPA330YFF,
OPA4330
NOISE
en
Input voltage noise
in
Input current noise
INPUT VOLTAGE RANGE
Common-mode voltage
range
VCM
(V–) – 0.1
At TA = –40°C to +125°C,
(V–) – 0.1 V < VCM < (V+) + 0.1 V
CMRR
(V+) + 0.1
V
100
115
dB
100
115
dB
100
115
dB
Differential
2
pF
Common-mode
4
pF
115
dB
Common-mode rejection
ratio
At TA = –40°C to +125°C,
(V–) – 0.1 V < VCM < (V+) + 0.1 V,
VS = 5.5 V
OPA330YFF,
OPA4330
INPUT CAPACITANCE
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
At TA = –40°C to +125°C,
(V–) + 100 mV < VO < (V+) – 100 mV, RL = 10 kΩ
100
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
CL = 100 pF
350
kHz
SR
Slew rate
G = +1
0.16
V/µs
Voltage output swing
from rail
At TA = –40°C to +125°C
OUTPUT
ISC
Short-circuit current
CL
Capacitive load drive
Open-loop output
impedance
30
100
±5
mV
mA
See Typical Characteristics
f = 350 kHz, IO = 0 mA
2
kΩ
POWER SUPPLY
VS
Specified voltage range
IQ
Quiescent current per
amplifier
At TA = –40°C to +125°C, IO = 0 mA
Turnon time
VS = 5 V
(1)
1.8
21
5.5
V
35
µA
100
µs
300-hour life test at 150°C demonstrated randomly distributed variation of approximately 1 µV.
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: OPA330 OPA2330 OPA4330
Submit Documentation Feedback
9
OPA330, OPA2330, OPA4330
SBOS432G – AUGUST 2008 – REVISED AUGUST 2016
www.ti.com
7.8 Typical Characteristics
At TA = 25°C, CL = 0 pF, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply, unless otherwise noted.
Table 1. Table of Graphs
DESCRIPTION
FIGURE NO.
Offset Voltage Production Distribution
Figure 1
Open-Loop Gain vs Frequency
Figure 2
Common-Mode Rejection Ratio vs Frequency
Figure 3
Power-Supply Rejection Ratio vs Frequency
Figure 4
Output Voltage Swing vs Output Current
Figure 5
Input Bias Current vs Common-Mode Voltage
Figure 6
Input Bias Current vs Temperature
Figure 7
Quiescent Current vs Temperature
Figure 8
Large-Signal Step Response
Figure 9
Small-Signal Step Response
Figure 10
Positive Overvoltage Recovery
Figure 11
Negative Overvoltage Recovery
Figure 12
Settling Time vs Closed-Loop Gain
Figure 13
Small-Signal Overshoot vs Load Capacitance
Figure 14
0.1-Hz to 10-Hz Noise
Figure 15
Current and Voltage Noise Spectral Density vs Frequency
Figure 16
Input Bias Current vs Input Differential Voltage
Figure 17
10
Submit Documentation Feedback
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: OPA330 OPA2330 OPA4330
OPA330, OPA2330, OPA4330
www.ti.com
SBOS432G – AUGUST 2008 – REVISED AUGUST 2016
120
250
100
200
AOL (dB)
150
Phase
60
100
40
50
Phase (°)
Population
80
Gain
20
0
0
-50
-100
10
24.00
18.00
21.00
12.00
15.00
6.00
9.00
0
3.00
-3.00
-9.00
-6.00
-15.00
-12.00
-21.00
-18.00
-24.00
-20
100
1k
10k
100k
1M
Frequency (Hz)
Offset Voltage (mV)
Figure 2. Open-Loop Gain vs Frequency
Figure 1. Offset Voltage Production Distribution
140
120
120
100
+PSRR
PSRR (dB)
CMRR (dB)
100
80
60
60
40
40
20
20
0
0
1
10
100
1k
10k
100k
1
1M
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
Figure 3. Common-Mode Rejection Ratio vs Frequency
Figure 4. Power-Supply Rejection Ratio vs Frequency
3
210
VS = ±2.75V
VS = ±0.9V
2
205
200
-40°C
+25°C
+125°C
0
-IB
195
1
+25°C
IB (pA)
Output Swing (V)
-PSRR
80
-40°C
-1
-190
+125°C
+25°C
-2
-195
+IB
-200
-205
-40°C
-3
190
-210
0
1
2
3
4
5
6
7
8
9
10
0
1
Output Current (mA)
Figure 5. Output Voltage Swing vs Output Current
2
3
4
5
Common-Mode Voltage (V)
Figure 6. Input Bias Current vs Common-Mode Voltage
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: OPA330 OPA2330 OPA4330
Submit Documentation Feedback
11
OPA330, OPA2330, OPA4330
SBOS432G – AUGUST 2008 – REVISED AUGUST 2016
250
www.ti.com
25
-IB
200
VS = 5.5V
-IB
150
20
100
VS = 1.8V
VS = 5.5V
VS = 1.8V
0
-50
15
IQ (mA)
IB (pA)
50
10
-100
+IB
-150
5
-200
+IB
-250
-50
0
-25
0
25
50
75
100
125
-50
-25
Figure 7. Input Bias Current vs Temperature
25
50
75
Output Voltage (50mV/div)
Output Voltage (1V/div)
Time (5ms/div)
Figure 9. Large-Signal Step Response
Figure 10. Small-Signal Step Response
0
Input
2V/div
Input
1V/div
Output
10kW
0
0
10kW
+2.5V
+2.5V
1kW
1kW
1V/div
125
G = +1
RL = 10kW
Time (50ms/div)
12
100
Figure 8. Quiescent Current vs Temperature
G=1
RL = 10kW
2V/div
0
Temperature (°C)
Temperature (°C)
0
Output
OPA330
OPA330
-2.5V
-2.5V
Time (50ms/div)
Time (50ms/div)
Figure 11. Positive Overvoltage Recovery
Figure 12. Negative Overvoltage Recovery
Submit Documentation Feedback
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: OPA330 OPA2330 OPA4330
OPA330, OPA2330, OPA4330
www.ti.com
SBOS432G – AUGUST 2008 – REVISED AUGUST 2016
40
600
4V Step
35
30
400
Overshoot (%)
Settling Time (ms)
500
300
200
25
20
15
0.001%
10
100
5
0.01%
0
0
1
10
10
100
100
1000
Gain (dB)
Load Capacitance (pF)
Figure 13. Settling Time vs Closed-Loop Gain
Figure 14. Small-Signal Overshoot vs Load Capacitance
500nV/div
1000
Continues with no 1/f (flicker) noise.
Current Noise
100
100
Voltage Noise
10
10
1
1s/div
Current Noise (fA/ÖHz)
Voltage Noise (nV/ÖHz)
1000
10
100
1k
10k
Frequency (Hz)
Figure 15. 0.1-Hz to 10-Hz Noise
50
Input Bias Current (mA)
40
30
Figure 16. Current and Voltage Noise Spectral Density vs
Frequency
Normal Operating Range
(see the Input Differential
Voltage section in the
Applications Information)
20
10
0
-10
-20
-30
Over-Driven Condition
Over-Driven Condition
-40
-50
-1V -800
-600 -400 -200
0
200
400
600
800
Input Differential Voltage (mV)
Figure 17. Input Bias Current vs Input Differential Voltage
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: OPA330 OPA2330 OPA4330
Submit Documentation Feedback
13
OPA330, OPA2330, OPA4330
SBOS432G – AUGUST 2008 – REVISED AUGUST 2016
www.ti.com
8 Detailed Description
8.1 Overview
The OPA330 family of Zerø-Drift amplifiers feature a proprietary auto-calibration technique to simultaneously
achieve near-zero drift over time and temperature at only 35 µA (maximum) of quiescent current while also
providing low offset voltage (50 µV maximum). These devices are unity-gain stable, precision operational
amplifiers free from unexpected output and phase reversal. The OPA330 series are also optimized for lowvoltage, single-supply operation: as low as 1.8 V (±0.9 V) and up to 5.5 V (±2.75 V).
The proprietary Zerø-Drift circuitry lowers the 1/f noise component as well as offers the advantage of low input
offset voltage over time and temperature. The OPA330 series of operational amplifiers are ideal for cost-sensitive
applications and applications that operate without regulation directly from battery power.
8.2 Functional Block Diagram
C2
CHOP1
GM1
CHOP2
Notch
Filter
GM2
GM3
OUT
+IN
-IN
C1
GM_FF
Copyright © 2016, Texas Instruments Incorporated
8.3 Feature Description
The OPA33x family is unity-gain stable and free from unexpected output phase reversal. These devices use
a proprietary auto-calibration technique to provide low offset voltage and very low drift over time and
temperature. For lowest offset voltage and precision performance, optimize circuit layout, and mechanical
conditions. Avoid temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple
junctions formed from connecting dissimilar conductors. Cancel these thermally-generated potentials by
assuring they are equal on both input terminals. Other layout and design considerations include:
• Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
• Thermally isolate components from power supplies or other heat sources.
• Shield operational amplifier and input circuitry from air currents, such as cooling fans.
Following these guidelines reduces the likelihood of junctions being at different temperatures, which can
cause thermoelectric voltage drift of 0.1 µV/°C or higher, depending on materials used.
8.4 Device Functional Modes
The OPAx330 has a single functional mode and is operational when the power-supply voltage is greater than
1.8 V (±0.9 V). The maximum power-supply voltage for the OPAx330 is 5.5 V (±2.75 V).
14
Submit Documentation Feedback
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: OPA330 OPA2330 OPA4330
OPA330, OPA2330, OPA4330
www.ti.com
SBOS432G – AUGUST 2008 – REVISED AUGUST 2016
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The OPA330, OPA2330, and OPA4330 are unity-gain stable, precision operational amplifiers free from
unexpected output and phase reversal. The use of proprietary Zerø-Drift circuitry gives the benefit of low input
offset voltage over time and temperature, as well as lowering the 1/f noise component. As a result of the high
PSRR, these devices work well in applications that run directly from battery power without regulation. The
OPA330 family is optimized for low-voltage, single-supply operation. These miniature, high-precision, low
quiescent current amplifiers offer high-impedance inputs that have a common-mode range 100 mV beyond the
supplies and a rail-to-rail output that swings within 100 mV of the supplies under normal test conditions. The
OPA330 series are precision amplifiers for cost-sensitive applications.
9.1.1 Operating Voltage
The OPA330 series operational amplifiers can be used with single or dual supplies from an operating range of
VS = 1.8 V (±0.9 V) up to 5.5 V (±2.75 V). Supply voltages greater than 7 V can permanently damage the device
(see Absolute Maximum Ratings). Key parameters that vary over the supply voltage or temperature range are
shown in Typical Characteristics.
9.1.2 Input Voltage
The OPA330, OPA2330, and OPA4330 input common-mode voltage range extends 0.1 V beyond the supply
rails. The OPA330 is designed to cover the full range without the troublesome transition region found in some
other rail-to-rail amplifiers.
Typically, input bias current is approximately 200 pA. Input voltages exceeding the power supplies however, can
cause excessive current to flow into or out of the input pins. Momentary voltages greater than the power supply
can be tolerated if the input current is limited to 10 mA. This limitation is easily accomplished with an input
resistor, as shown in Figure 18.
Current-limiting resistor
required if input voltage
exceeds supply rails by
³ 0.3V.
IOVERLOAD
10mA max
+5V
OPA330
VOUT
VIN
5kW
Copyright © 2016, Texas Instruments Incorporated
Figure 18. Input Current Protection
9.1.3 Input Differential Voltage
The typical input bias current of the OPA330 during normal operation is approximately 200 pA. In over-driven
conditions, the bias current can increase significantly (see Figure 17). The most common cause of an over-driven
condition occurs when the operational amplifier is outside of the linear range of operation. When the output of the
operational amplifier is driven to one of the supply rails the feedback loop requirements cannot be satisfied and a
differential input voltage develops across the input pins. This differential input voltage results in activation of
parasitic diodes inside the front end input chopping switches that combine with 10-kΩ electromagnetic
interference (EMI) filter resistors to create the equivalent circuit illustrated in Figure 19. Notice that the input bias
current remains within specification within the linear region.
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: OPA330 OPA2330 OPA4330
Submit Documentation Feedback
15
OPA330, OPA2330, OPA4330
SBOS432G – AUGUST 2008 – REVISED AUGUST 2016
www.ti.com
Application Information (continued)
10kW
Clamp
+In
CORE
-In
10kW
Copyright © 2016, Texas Instruments Incorporated
Figure 19. Equivalent Input Circuit
9.1.4 Internal Offset Correction
The OPA330, OPA2330, and OPA4330 operational amplifiers use an auto-calibration technique with a timecontinuous, 125-kHz operational amplifier in the signal path. This amplifier is zero-corrected every 8 µs using a
proprietary technique. Upon power up, the amplifier requires approximately 100 µs to achieve specified VOS
accuracy. This design has no aliasing or flicker noise.
9.1.5 EMI Susceptibility and Input Filtering
Operational amplifiers vary in their susceptibility to EMI. If conducted EMI enters the operational amplifier, the DC
offset observed at the amplifier output may shift from its nominal value while the EMI is present. This shift is a
result of signal rectification associated with the internal semiconductor junctions. While all operational amplifier
pin functions can be affected by EMI, the input pins are likely to be the most susceptible. The OPA330
operational amplifier family incorporates an internal input low-pass filter that reduces the amplifier response to
EMI. Both common-mode and differential mode filtering are provided by the input filter. The filter is designed for a
cutoff frequency of approximately 8 MHz (–3 dB), with a rolloff of 20 dB per decade.
9.1.6 Achieving Output Swing to the Operational Amplifier Negative Rail
Some applications require output voltage swings from 0 V to a positive full-scale voltage (such as 2.5 V) with
excellent accuracy. With most single-supply operational amplifiers, problems arise when the output signal
approaches 0 V, near the lower output swing limit of a single-supply operational amplifier. A good single-supply
operational amplifier may swing close to single-supply ground, but does not reach ground. The output of the
OPA330, OPA2330, and OPA4330 can be made to swing to ground, or slightly below, on a single-supply power
source. To do so requires the use of another resistor and an additional, more negative, power supply than the
operational amplifier negative supply. A pulldown resistor may be connected between the output and the
additional negative supply to pull the output down below the value that the output would otherwise achieve, as
shown in Figure 20.
V+ = +5V
OPA330
VOUT
VIN
RP = 20kW
Op Amp V- = GND
-5V
Additional
Negative
Supply
Copyright © 2016, Texas Instruments Incorporated
Figure 20. For VOUT Range to Ground
16
Submit Documentation Feedback
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: OPA330 OPA2330 OPA4330
OPA330, OPA2330, OPA4330
www.ti.com
SBOS432G – AUGUST 2008 – REVISED AUGUST 2016
Application Information (continued)
The OPA330, OPA2330, and OPA4330 have an output stage that allows the output voltage to be pulled to its
negative supply rail, or slightly below, using the technique previously described. This technique only works with
some types of output stages. The OPA330, OPA2330, and OPA4330 have been characterized to perform with
this technique; the recommended resistor value is approximately 20 kΩ. This configuration increases the current
consumption by several hundreds of microamps. Accuracy is excellent down to 0 V and as low as –2 mV.
Limiting and nonlinearity occur below –2 mV, but excellent accuracy returns as the output is again driven above
–2 mV. Lowering the resistance of the pulldown resistor allows the operational amplifier to swing even further
below the negative rail. Resistances as low as 10 kΩ can be used to achieve excellent accuracy down to
–10 mV.
9.1.7 Photosensitivity
Although the OPA330 YFF package has a protective backside coating that reduces the amount of light exposure
on the die, unless fully shielded, ambient light can reach the active region of the device. Input bias current for the
package is specified in the absence of light. Depending on the amount of light exposure in a given application, an
increase in bias current, and possible increases in offset voltage should be expected. Fluorescent lighting may
introduce noise or hum because of the time-varying light output. Best layout practices include end-product
packaging that provides shielding from possible light sources during operation.
9.2 Typical Application
9.2.1 Bidirectional Current-Sensing
This single-supply, low-side, bidirectional current-sensing solution detects load currents from –1 A to 1 A. The
single-ended output spans from 110 mV to 3.19 V. This design uses the OPA2330 because of its low offset
voltage and rail-to-rail input and output. One of the amplifiers is configured as a difference amplifier and the other
provides the reference voltage.
Figure 21 shows the solution.
VCC
VCC
VREF
R5
+
U1B
R6
ILOAD
VBUS
+
±
R2
R1
+
VSHUNT
±
+
RSHUNT
VOUT
U1A
R3
RL
VCC
R4
Copyright © 2016, Texas Instruments Incorporated
Figure 21. Bidirectional Current-Sensing Schematic
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: OPA330 OPA2330 OPA4330
Submit Documentation Feedback
17
OPA330, OPA2330, OPA4330
SBOS432G – AUGUST 2008 – REVISED AUGUST 2016
www.ti.com
Typical Application (continued)
9.2.1.1 Design Requirements
This solution has the following requirements:
• Supply voltage: 3.3 V
• Input: –1 A to 1 A
• Output: 1.65 V ±1.54 V (110 mV to 3.19 V)
9.2.1.2 Detailed Design Procedure
The load current, ILOAD, flows through the shunt resistor (RSHUNT) to develop the shunt voltage, VSHUNT. The shunt
voltage is then amplified by the difference amplifier, which consists of U1A and R1 through R4. The gain of the
difference amplifier is set by the ratio of R4 to R3. To minimize errors, set R2 = R4 and R1 = R3. The reference
voltage, VREF, is supplied by buffering a resistor divider using U1B. The transfer function is given by Equation 1.
VOUT = VSHUNT ´ GainDiff_Amp + VREF
where
•
•
VSHUNT = ILOAD ´ RSHUNT
GainDiff_Amp =
R4
R3
VREF = VCC ´
•
R6
R5 + R6
(1)
There are two types of errors in this design: offset and gain. Gain errors are introduced by the tolerance of the
shunt resistor and the ratios of R4 to R3 and, similarly, R2 to R1. Offset errors are introduced by the voltage
divider (R5 and R6) and how closely the ratio of R4/R3 matches R2/R1. The latter value impacts the CMRR of the
difference amplifier, which ultimately translates to an offset error.
Because this is a low-side measurement, the value of VSHUNT is the ground potential for the system load.
Therefore, it is important to place a maximum value on VSHUNT. In this design, the maximum value for VSHUNT is
set to 100 mV. Equation 2 calculates the maximum value of the shunt resistor given a maximum shunt voltage of
100 mV and maximum load current of 1 A.
V
RSHUNT(Max) = SHUNT(Max) = 100 mV = 100 mW
ILOAD(Max)
1A
(2)
The tolerance of RSHUNT is directly proportional to cost. For this design, a shunt resistor with a tolerance of 0.5%
was selected. If greater accuracy is required, select a 0.1% resistor or better.
The load current is bidirectional; therefore, the shunt voltage range is –100 mV to 100 mV. This voltage is divided
down by R1 and R2 before reaching the operational amplifier, U1A. Take care to ensure that the voltage present
at the noninverting node of U1A is within the common-mode range of the device. Therefore, it is important to use
an operational amplifier, such as the OPA330, that has a common-mode range that extends below the negative
supply voltage. Finally, to minimize offset error, note that the OPA330 has a typical offset voltage of merely
±8 µV (±50 µV maximum).
Given a symmetric load current of –1 A to 1 A, the voltage divider resistors (R5 and R6) must be equal. To be
consistent with the shunt resistor, a tolerance of 0.5% was selected. To minimize power consumption,
10-kΩ resistors were used.
To set the gain of the difference amplifier, the common-mode range and output swing of the OPA330 must be
considered. Equation 3 and Equation 4 depict the typical common-mode range and maximum output swing,
respectively, of the OPA330 given a 3.3-V supply.
–100 mV < VCM < 3.4 V
100 mV < VOUT < 3.2 V
(3)
(4)
The gain of the difference amplifier can now be calculated as shown in Equation 5.
VOUT_Max - VOUT_Min
3.2 V - 100 mV
V
= 15.5
=
GainDiff_Amp =
V
100 mW ´ [1 A - (- 1A)]
RSHUNT ´ (IMAX - IMIN)
18
Submit Documentation Feedback
(5)
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: OPA330 OPA2330 OPA4330
OPA330, OPA2330, OPA4330
www.ti.com
SBOS432G – AUGUST 2008 – REVISED AUGUST 2016
Typical Application (continued)
The resistor value selected for R1 and R3 was 1 kΩ. 15.4 kΩ was selected for R2 and R4 because it is the
nearest standard value. Therefore, the ideal gain of the difference amplifier is 15.4 V/V.
The gain error of the circuit primarily depends on R1 through R4. As a result of this dependence, 0.1% resistors
were selected. This configuration reduces the likelihood that the design requires a two-point calibration. A simple
one-point calibration, if desired, removes the offset errors introduced by the 0.5% resistors.
9.2.1.3 Application Curve
Output Voltage (V)
3.30
1.65
0
-1.0
-0.5
0
Input Current (A)
0.5
1.0
Figure 22. Bidirectional Current-Sensing Circuit Performance:
Output Voltage vs Input Current
9.3 System Examples
9.3.1 Single Operational Amplifier Bridge Amplifier
Figure 23 shows the basic configuration for a bridge amplifier.
VEX
R1
+5V
R R
R R
OPA330
VOUT
R1
VREF
Copyright © 2016, Texas Instruments Incorporated
Figure 23. Single Operational Amplifier Bridge Amplifier Schematic
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: OPA330 OPA2330 OPA4330
Submit Documentation Feedback
19
OPA330, OPA2330, OPA4330
SBOS432G – AUGUST 2008 – REVISED AUGUST 2016
www.ti.com
System Examples (continued)
9.3.2 Low-Side Current Monitor
A low-side current shunt monitor is shown in Figure 24.
RN are operational resistors used to isolate the ADS1100 from the noise of the digital I2C bus. Because the
ADS1100 is a 16-bit converter, a precise reference is essential for maximum accuracy. If absolute accuracy is
not required, and the 5-V power supply is sufficiently stable, the REF3130 may be omitted.
3V
+5V
REF3130
Load
R2
49.9kW
R1
4.99kW
R6
71.5kW
V
ILOAD
RSHUNT
1W
RN
56W
OPA330
R4
48.7kW
R3
4.99kW
ADS1100
R7
1.18kW
Stray Ground-Loop Resistance
RN
56W
2
IC
(PGA Gain = 4)
FS = 3.0V
Copyright © 2016, Texas Instruments Incorporated
NOTE: 1% resistors provide adequate common-mode rejection at small ground-loop errors.
Figure 24. Low-Side Current Monitor
9.3.3 Thermistor Measurement
Figure 25 shows the OPA330 in a typical thermistor circuit.
1MW
60kW
3V
NTC
Thermistor
1MW
100kW
OPA330
Copyright © 2016, Texas Instruments Incorporated
Figure 25. Thermistor Measurement Schematic
10 Power Supply Recommendations
The OPAx330 family of devices is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V). Parameters
that can exhibit significant variance with regard to operating voltage are presented in Typical Characteristics.
20
Submit Documentation Feedback
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: OPA330 OPA2330 OPA4330
OPA330, OPA2330, OPA4330
www.ti.com
SBOS432G – AUGUST 2008 – REVISED AUGUST 2016
11 Layout
11.1 Layout Guidelines
TI always recommends paying attention to good layout practice. Keep traces short and, when possible, use a
printed-circuit board (PCB) ground plane with surface-mount components placed as close to the device pins as
possible. Place a 0.1-µF capacitor closely across the supply pins. These guidelines must be applied throughout
the analog circuit to improve performance and provide benefits such as reducing the electromagnetic interference
(EMI) susceptibility.
For lowest offset voltage and precision performance, circuit layout, and mechanical conditions must be optimized.
Avoid temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple junctions formed
from connecting dissimilar conductors. These thermally-generated potentials can be made to cancel by assuring
they are equal on both input terminals. Other layout and design considerations include:
• Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
• Thermally isolate components from power supplies or other heat sources.
• Shield operational amplifier and input circuitry from air currents, such as cooling fans.
Following these guidelines reduces the likelihood of junctions being at different temperatures, which can cause
thermoelectric voltage drift of 0.1 µV/°C or higher, depending on materials used.
11.1.1 VQFN and SON Packages
The OPA4330 is offered in a VQFN package. The OPA2330 is available in a 8-pin SON package, which is a
VQFN package with lead contacts on only two sides of the bottom of the package. These leadless, near-chipscale packages maximize board space and enhance thermal and electrical characteristics through an exposed
pad. VQFN and SON packages are physically small, have a smaller routing area, improved thermal performance,
and improved electrical parasitics, with a pinout scheme that is consistent with other commonly-used packages,
such as SOIC and VSSOP. Additionally, the absence of external leads eliminates bent-lead issues.
The VQFN and SON package can be easily mounted using standard PCB assembly techniques. See the
application note, QFN/SON PCB Attachment (SLUA271), and the application report, Quad Flatpack No-Lead
Logic Packages (SCBA017), both available for download at www.ti.com.
NOTE
The exposed leadframe die pad on the bottom of the package should be connected to V–.
11.1.2 VQFN and SON Layout Guidelines
The leadframe die pad must be soldered to a thermal pad on the PCB. A mechanical data sheet showing an
example layout is attached at the end of this data sheet. Refinements to this layout may be required based on
assembly process requirements. Mechanical drawings located at the end of this data sheet list the physical
dimensions for the package and pad. The five holes in the landing pattern are optional, and are intended for use
with thermal vias that connect the leadframe die pad to the heat sink area on the PCB.
Soldering the exposed pad significantly improves board-level reliability during temperature cycling, key push,
package shear, and similar board-level tests. Even with applications that have low-power dissipation, the
exposed pad must be soldered to the PCB to provide structural integrity and long-term reliability.
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: OPA330 OPA2330 OPA4330
Submit Documentation Feedback
21
OPA330, OPA2330, OPA4330
SBOS432G – AUGUST 2008 – REVISED AUGUST 2016
www.ti.com
Layout Guidelines (continued)
11.1.3 OPA330 DSBGA
The OPA330 YFF package is a lead- (Pb-) free, die-level, wafer chip-scale package. Unlike devices that are in
plastic packages, these devices have no molding compound, lead frame, wire bonds, or leads. Using standard
surface-mount assembly procedures, the OPA330 YFF can be mounted to a printed-circuit board (PCB) without
additional underfill. Figure 26 and Figure 27 detail the pinout and package marking, respectively. See the
application note, NanoStar™ and NanoFree™ 300μm Solder Bump WCSP (SBVA017) for more detailed
information on package characteristics and PCB design.
C3
C1
IN-
Actual Size:
YMDTBDS
OUT
B2
VSA3
Exact Size (max):
0,862 mm x 1,156 mm
A1
Package Marking Code:
YMD = year/month/day
TBD = indicates OPA330AIYFF
S = for engineering purposes only
IN+
VS+
(Bump side down)
Figure 26. DSBGA Pin Description
Figure 27. YFF Package Marking
11.2 Layout Example
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors
VS+
RF
N/C
N/C
GND
±IN
V+
VIN
+IN
OUTPUT
V±
N/C
RG
Use low-ESR,
ceramic bypass
capacitor
GND
VS±
GND
Use low-ESR, ceramic
bypass capacitor
VOUT
Ground (GND) plane on another layer
Figure 28. OPAx330 Layout Example
22
Submit Documentation Feedback
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: OPA330 OPA2330 OPA4330
OPA330, OPA2330, OPA4330
www.ti.com
SBOS432G – AUGUST 2008 – REVISED AUGUST 2016
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ is
a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a
range of both passive and active models. TINA-TI provides all the conventional DC, transient, and frequency
domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
12.1.1.2 DIP Adapter EVM
The DIP Adapter EVM tool provides an easy, low-cost way to prototype small surface mount ICs. The evaluation
tool these TI packages: D or U (SOIC-8), PW (TSSOP-8), DGK (VSSOP-8), DBV (SOT23-6, SOT23-5 and
SOT23-3), DCK (SC70-6 and SC70-5), and DRL (SOT563-6). The DIP Adapter EVM may also be used with
terminal strips or may be wired directly to existing circuits.
12.1.1.3 Universal Operational Amplifier EVM
The Universal Op Amp EVM is a series of general-purpose, blank circuit boards that simplify prototyping circuits
for a variety of IC package types. The evaluation module board design allows many different circuits to be
constructed easily and quickly. Five models are offered, with each model intended for a specific package type.
PDIP, SOIC, VSSOP, TSSOP and SOT-23 packages are all supported.
NOTE
These boards are unpopulated, so users must provide their own ICs. TI recommends
requesting several op amp device samples when ordering the Universal Op Amp EVM.
12.1.1.4 TI Precision Designs
TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the
theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and
measured performance of many useful circuits. TI Precision Designs are available online at
http://www.ti.com/ww/en/analog/precision-designs/.
12.1.1.5 WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to
design, optimize, and simulate complete multistage active filter solutions within minutes.
12.1.1.6 Related Parts
For parts used in System Examples, see the following:
• Self-Calibrating, 16-Bit Analog-to-Digital Converter, ADS1100
• 20ppm/Degrees C Max, 100uA, SOT23-3 Series Voltage Reference, REF3130
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: OPA330 OPA2330 OPA4330
Submit Documentation Feedback
23
OPA330, OPA2330, OPA4330
SBOS432G – AUGUST 2008 – REVISED AUGUST 2016
www.ti.com
12.2 Documentation Support
12.2.1 Related Documentation
For additional information, see the following documents (available for download at www.ti.com):
• QFN/SON PCB Attachment (SLUA271)
• Quad Flatpack No-Lead Logic Packages (SCBA017)
• NanoStar™ and NanoFree™ 300μm Solder Bump WCSP (SBVA017)
12.3 Related Links
Table 2 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA330
Click here
Click here
Click here
Click here
Click here
OPA2330
Click here
Click here
Click here
Click here
Click here
OPA4330
Click here
Click here
Click here
Click here
Click here
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.6 Trademarks
NanoStar, NanoFree, TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
12.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
24
Submit Documentation Feedback
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: OPA330 OPA2330 OPA4330
OPA330, OPA2330, OPA4330
www.ti.com
SBOS432G – AUGUST 2008 – REVISED AUGUST 2016
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: OPA330 OPA2330 OPA4330
Submit Documentation Feedback
25
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA2330AID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
O2330A
OPA2330AIDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
OCGQ
OPA2330AIDGKRG4
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
OCGQ
OPA2330AIDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
OCGQ
OPA2330AIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
O2330A
OPA2330AIDRBR
ACTIVE
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
OCGQ
OPA2330AIDRBT
ACTIVE
SON
DRB
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
OCGQ
OPA2330AIDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
O2330A
OPA330AID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
O330A
OPA330AIDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
OCFQ
OPA330AIDBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
OCFQ
OPA330AIDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
OCFQ
OPA330AIDBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
OCFQ
OPA330AIDCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CHL
OPA330AIDCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CHL
OPA330AIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
O330A
OPA330AIDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
O330A
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA330AIYFFR
ACTIVE
DSBGA
YFF
5
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
OEH
OPA330AIYFFT
ACTIVE
DSBGA
YFF
5
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
OEH
OPA4330AID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O4330A
OPA4330AIDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O4330A
OPA4330AIPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O4330A
OPA4330AIPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O4330A
OPA4330AIRGYR
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
4330A
OPA4330AIRGYT
ACTIVE
VQFN
RGY
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
4330A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
OPA2330AIDGKR
VSSOP
DGK
8
OPA2330AIDGKT
VSSOP
DGK
OPA2330AIDR
SOIC
D
OPA2330AIDRBR
SON
OPA2330AIDRBT
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
8
250
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
DRB
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
SON
DRB
8
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
OPA330AIDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
OPA330AIDBVR
SOT-23
DBV
5
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
OPA330AIDBVT
SOT-23
DBV
5
250
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
OPA330AIDCKR
SC70
DCK
5
3000
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
OPA330AIDCKT
SC70
DCK
5
250
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
OPA330AIDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
OPA330AIYFFR
DSBGA
YFF
5
3000
180.0
8.4
0.91
1.21
0.68
2.0
8.0
Q1
OPA330AIYFFT
DSBGA
YFF
5
250
180.0
8.4
0.91
1.21
0.68
2.0
8.0
Q1
OPA4330AIDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
OPA4330AIPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
OPA4330AIRGYR
VQFN
RGY
14
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
OPA4330AIRGYT
VQFN
RGY
14
250
180.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2330AIDGKR
VSSOP
DGK
8
2500
364.0
364.0
27.0
OPA2330AIDGKT
VSSOP
DGK
8
250
364.0
364.0
27.0
OPA2330AIDR
SOIC
D
8
2500
367.0
367.0
35.0
OPA2330AIDRBR
SON
DRB
8
3000
367.0
367.0
35.0
OPA2330AIDRBT
SON
DRB
8
250
210.0
185.0
35.0
OPA330AIDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
OPA330AIDBVR
SOT-23
DBV
5
3000
203.0
203.0
35.0
OPA330AIDBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
OPA330AIDCKR
SC70
DCK
5
3000
203.0
203.0
35.0
OPA330AIDCKT
SC70
DCK
5
250
203.0
203.0
35.0
OPA330AIDR
SOIC
D
8
2500
367.0
367.0
35.0
OPA330AIYFFR
DSBGA
YFF
5
3000
182.0
182.0
20.0
OPA330AIYFFT
DSBGA
YFF
5
250
182.0
182.0
20.0
OPA4330AIDR
SOIC
D
14
2500
367.0
367.0
38.0
OPA4330AIPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
OPA4330AIRGYR
VQFN
RGY
14
3000
367.0
367.0
35.0
OPA4330AIRGYT
VQFN
RGY
14
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
D: Max = 1.146 mm, Min =1.086 mm
E: Max = 0.852 mm, Min =0.792 mm
PACKAGE OUTLINE
DRB0008B
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
EXPOSED
THERMAL PAD
1.65 0.05
(0.2) TYP
4
5
2X
1.95
2.4 0.05
8
1
6X 0.65
8X
PIN 1 ID
(OPTIONAL)
8X
0.5
0.3
0.35
0.25
0.1
0.05
C A B
C
4218876/A 12/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRB0008B
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
SYMM
8X (0.6)
1
8
8X (0.3)
(2.4)
(0.95)
6X (0.65)
4
5
(R0.05) TYP
(0.575)
( 0.2) VIA
TYP
(2.8)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218876/A 12/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRB0008B
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
8X (0.6)
METAL
TYP
1
8
8X (0.3)
(0.63)
SYMM
(1.06)
6X (0.65)
5
4
(R0.05) TYP
(1.47)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
81% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218876/A 12/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising